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review.evervolv.com / android_kernel_htc_msm8960 / 3f2bc4d6eb5a4fada842462ba22bb6bbb41d00c7 / . / arch / arm / mach-msm / devices-8960.c
blob: 886f1434086ba3178c4508673c4a3e66c895fbdc [file] [log] [blame]
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame^]1/* Copyright (c) 2011, Code Aurora Forum. All rights reserved.
2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 *
12 */
13
14#include <linux/kernel.h>
15#include <linux/list.h>
16#include <linux/platform_device.h>
17#include <linux/msm_rotator.h>
18#include <linux/gpio.h>
19#include <asm/clkdev.h>
20#include <linux/msm_kgsl.h>
21#include <linux/android_pmem.h>
22#include <mach/irqs-8960.h>
23#include <mach/board.h>
24#include <mach/msm_iomap.h>
25#include <mach/msm_hsusb.h>
26#include <mach/msm_sps.h>
27#include <mach/rpm.h>
28#include <mach/msm_bus_board.h>
29#include <mach/msm_memtypes.h>
30#include "clock.h"
31#include "devices.h"
32#include "devices-msm8x60.h"
33#include "footswitch.h"
34
35#ifdef CONFIG_MSM_MPM
36#include "mpm.h"
37#endif
38#ifdef CONFIG_MSM_DSPS
39#include <mach/msm_dsps.h>
40#endif
41
42
43/* Address of GSBI blocks */
44#define MSM_GSBI1_PHYS 0x16000000
45#define MSM_GSBI2_PHYS 0x16100000
46#define MSM_GSBI3_PHYS 0x16200000
47#define MSM_GSBI4_PHYS 0x16300000
48#define MSM_GSBI5_PHYS 0x16400000
49#define MSM_GSBI6_PHYS 0x16500000
50#define MSM_GSBI7_PHYS 0x16600000
51#define MSM_GSBI8_PHYS 0x1A000000
52#define MSM_GSBI9_PHYS 0x1A100000
53#define MSM_GSBI10_PHYS 0x1A200000
54#define MSM_GSBI11_PHYS 0x12440000
55#define MSM_GSBI12_PHYS 0x12480000
56
57#define MSM_UART2DM_PHYS (MSM_GSBI2_PHYS + 0x40000)
58#define MSM_UART5DM_PHYS (MSM_GSBI5_PHYS + 0x40000)
59
60/* GSBI QUP devices */
61#define MSM_GSBI1_QUP_PHYS (MSM_GSBI1_PHYS + 0x80000)
62#define MSM_GSBI2_QUP_PHYS (MSM_GSBI2_PHYS + 0x80000)
63#define MSM_GSBI3_QUP_PHYS (MSM_GSBI3_PHYS + 0x80000)
64#define MSM_GSBI4_QUP_PHYS (MSM_GSBI4_PHYS + 0x80000)
65#define MSM_GSBI5_QUP_PHYS (MSM_GSBI5_PHYS + 0x80000)
66#define MSM_GSBI6_QUP_PHYS (MSM_GSBI6_PHYS + 0x80000)
67#define MSM_GSBI7_QUP_PHYS (MSM_GSBI7_PHYS + 0x80000)
68#define MSM_GSBI8_QUP_PHYS (MSM_GSBI8_PHYS + 0x80000)
69#define MSM_GSBI9_QUP_PHYS (MSM_GSBI9_PHYS + 0x80000)
70#define MSM_GSBI10_QUP_PHYS (MSM_GSBI10_PHYS + 0x80000)
71#define MSM_GSBI11_QUP_PHYS (MSM_GSBI11_PHYS + 0x20000)
72#define MSM_GSBI12_QUP_PHYS (MSM_GSBI12_PHYS + 0x20000)
73#define MSM_QUP_SIZE SZ_4K
74
75#define MSM_PMIC1_SSBI_CMD_PHYS 0x00500000
76#define MSM_PMIC2_SSBI_CMD_PHYS 0x00C00000
77#define MSM_PMIC_SSBI_SIZE SZ_4K
78
79static struct resource resources_otg[] = {
80 {
81 .start = MSM8960_HSUSB_PHYS,
82 .end = MSM8960_HSUSB_PHYS + MSM8960_HSUSB_SIZE,
83 .flags = IORESOURCE_MEM,
84 },
85 {
86 .start = USB1_HS_IRQ,
87 .end = USB1_HS_IRQ,
88 .flags = IORESOURCE_IRQ,
89 },
90};
91
92struct platform_device msm_device_otg = {
93 .name = "msm_otg",
94 .id = -1,
95 .num_resources = ARRAY_SIZE(resources_otg),
96 .resource = resources_otg,
97 .dev = {
98 .coherent_dma_mask = 0xffffffff,
99 },
100};
101
102static struct resource resources_hsusb[] = {
103 {
104 .start = MSM8960_HSUSB_PHYS,
105 .end = MSM8960_HSUSB_PHYS + MSM8960_HSUSB_SIZE,
106 .flags = IORESOURCE_MEM,
107 },
108 {
109 .start = USB1_HS_IRQ,
110 .end = USB1_HS_IRQ,
111 .flags = IORESOURCE_IRQ,
112 },
113};
114
115struct platform_device msm_device_gadget_peripheral = {
116 .name = "msm_hsusb",
117 .id = -1,
118 .num_resources = ARRAY_SIZE(resources_hsusb),
119 .resource = resources_hsusb,
120 .dev = {
121 .coherent_dma_mask = 0xffffffff,
122 },
123};
124
125static struct resource resources_hsusb_host[] = {
126 {
127 .start = MSM8960_HSUSB_PHYS,
128 .end = MSM8960_HSUSB_PHYS + MSM8960_HSUSB_SIZE - 1,
129 .flags = IORESOURCE_MEM,
130 },
131 {
132 .start = USB1_HS_IRQ,
133 .end = USB1_HS_IRQ,
134 .flags = IORESOURCE_IRQ,
135 },
136};
137
138static u64 dma_mask = 0xffffffffULL;
139struct platform_device msm_device_hsusb_host = {
140 .name = "msm_hsusb_host",
141 .id = -1,
142 .num_resources = ARRAY_SIZE(resources_hsusb_host),
143 .resource = resources_hsusb_host,
144 .dev = {
145 .dma_mask = &dma_mask,
146 .coherent_dma_mask = 0xffffffff,
147 },
148};
149
150static struct resource resources_uart_gsbi2[] = {
151 {
152 .start = MSM8960_GSBI2_UARTDM_IRQ,
153 .end = MSM8960_GSBI2_UARTDM_IRQ,
154 .flags = IORESOURCE_IRQ,
155 },
156 {
157 .start = MSM_UART2DM_PHYS,
158 .end = MSM_UART2DM_PHYS + PAGE_SIZE - 1,
159 .name = "uartdm_resource",
160 .flags = IORESOURCE_MEM,
161 },
162 {
163 .start = MSM_GSBI2_PHYS,
164 .end = MSM_GSBI2_PHYS + PAGE_SIZE - 1,
165 .name = "gsbi_resource",
166 .flags = IORESOURCE_MEM,
167 },
168};
169
170struct platform_device msm8960_device_uart_gsbi2 = {
171 .name = "msm_serial_hsl",
172 .id = 0,
173 .num_resources = ARRAY_SIZE(resources_uart_gsbi2),
174 .resource = resources_uart_gsbi2,
175};
176
177static struct resource resources_uart_gsbi5[] = {
178 {
179 .start = GSBI5_UARTDM_IRQ,
180 .end = GSBI5_UARTDM_IRQ,
181 .flags = IORESOURCE_IRQ,
182 },
183 {
184 .start = MSM_UART5DM_PHYS,
185 .end = MSM_UART5DM_PHYS + PAGE_SIZE - 1,
186 .name = "uartdm_resource",
187 .flags = IORESOURCE_MEM,
188 },
189 {
190 .start = MSM_GSBI5_PHYS,
191 .end = MSM_GSBI5_PHYS + PAGE_SIZE - 1,
192 .name = "gsbi_resource",
193 .flags = IORESOURCE_MEM,
194 },
195};
196
197struct platform_device msm8960_device_uart_gsbi5 = {
198 .name = "msm_serial_hsl",
199 .id = 0,
200 .num_resources = ARRAY_SIZE(resources_uart_gsbi5),
201 .resource = resources_uart_gsbi5,
202};
203/* MSM Video core device */
204#ifdef CONFIG_MSM_BUS_SCALING
205static struct msm_bus_vectors vidc_init_vectors[] = {
206 {
207 .src = MSM_BUS_MASTER_HD_CODEC_PORT0,
208 .dst = MSM_BUS_SLAVE_EBI_CH0,
209 .ab = 0,
210 .ib = 0,
211 },
212 {
213 .src = MSM_BUS_MASTER_HD_CODEC_PORT1,
214 .dst = MSM_BUS_SLAVE_EBI_CH0,
215 .ab = 0,
216 .ib = 0,
217 },
218 {
219 .src = MSM_BUS_MASTER_AMPSS_M0,
220 .dst = MSM_BUS_SLAVE_EBI_CH0,
221 .ab = 0,
222 .ib = 0,
223 },
224 {
225 .src = MSM_BUS_MASTER_AMPSS_M0,
226 .dst = MSM_BUS_SLAVE_EBI_CH0,
227 .ab = 0,
228 .ib = 0,
229 },
230};
231static struct msm_bus_vectors vidc_venc_vga_vectors[] = {
232 {
233 .src = MSM_BUS_MASTER_HD_CODEC_PORT0,
234 .dst = MSM_BUS_SLAVE_EBI_CH0,
235 .ab = 54525952,
236 .ib = 436207616,
237 },
238 {
239 .src = MSM_BUS_MASTER_HD_CODEC_PORT1,
240 .dst = MSM_BUS_SLAVE_EBI_CH0,
241 .ab = 72351744,
242 .ib = 289406976,
243 },
244 {
245 .src = MSM_BUS_MASTER_AMPSS_M0,
246 .dst = MSM_BUS_SLAVE_EBI_CH0,
247 .ab = 500000,
248 .ib = 1000000,
249 },
250 {
251 .src = MSM_BUS_MASTER_AMPSS_M0,
252 .dst = MSM_BUS_SLAVE_EBI_CH0,
253 .ab = 500000,
254 .ib = 1000000,
255 },
256};
257static struct msm_bus_vectors vidc_vdec_vga_vectors[] = {
258 {
259 .src = MSM_BUS_MASTER_HD_CODEC_PORT0,
260 .dst = MSM_BUS_SLAVE_EBI_CH0,
261 .ab = 40894464,
262 .ib = 327155712,
263 },
264 {
265 .src = MSM_BUS_MASTER_HD_CODEC_PORT1,
266 .dst = MSM_BUS_SLAVE_EBI_CH0,
267 .ab = 48234496,
268 .ib = 192937984,
269 },
270 {
271 .src = MSM_BUS_MASTER_AMPSS_M0,
272 .dst = MSM_BUS_SLAVE_EBI_CH0,
273 .ab = 500000,
274 .ib = 2000000,
275 },
276 {
277 .src = MSM_BUS_MASTER_AMPSS_M0,
278 .dst = MSM_BUS_SLAVE_EBI_CH0,
279 .ab = 500000,
280 .ib = 2000000,
281 },
282};
283static struct msm_bus_vectors vidc_venc_720p_vectors[] = {
284 {
285 .src = MSM_BUS_MASTER_HD_CODEC_PORT0,
286 .dst = MSM_BUS_SLAVE_EBI_CH0,
287 .ab = 163577856,
288 .ib = 1308622848,
289 },
290 {
291 .src = MSM_BUS_MASTER_HD_CODEC_PORT1,
292 .dst = MSM_BUS_SLAVE_EBI_CH0,
293 .ab = 219152384,
294 .ib = 876609536,
295 },
296 {
297 .src = MSM_BUS_MASTER_AMPSS_M0,
298 .dst = MSM_BUS_SLAVE_EBI_CH0,
299 .ab = 1750000,
300 .ib = 3500000,
301 },
302 {
303 .src = MSM_BUS_MASTER_AMPSS_M0,
304 .dst = MSM_BUS_SLAVE_EBI_CH0,
305 .ab = 1750000,
306 .ib = 3500000,
307 },
308};
309static struct msm_bus_vectors vidc_vdec_720p_vectors[] = {
310 {
311 .src = MSM_BUS_MASTER_HD_CODEC_PORT0,
312 .dst = MSM_BUS_SLAVE_EBI_CH0,
313 .ab = 121634816,
314 .ib = 973078528,
315 },
316 {
317 .src = MSM_BUS_MASTER_HD_CODEC_PORT1,
318 .dst = MSM_BUS_SLAVE_EBI_CH0,
319 .ab = 155189248,
320 .ib = 620756992,
321 },
322 {
323 .src = MSM_BUS_MASTER_AMPSS_M0,
324 .dst = MSM_BUS_SLAVE_EBI_CH0,
325 .ab = 1750000,
326 .ib = 7000000,
327 },
328 {
329 .src = MSM_BUS_MASTER_AMPSS_M0,
330 .dst = MSM_BUS_SLAVE_EBI_CH0,
331 .ab = 1750000,
332 .ib = 7000000,
333 },
334};
335static struct msm_bus_vectors vidc_venc_1080p_vectors[] = {
336 {
337 .src = MSM_BUS_MASTER_HD_CODEC_PORT0,
338 .dst = MSM_BUS_SLAVE_EBI_CH0,
339 .ab = 372244480,
340 .ib = 1861222400,
341 },
342 {
343 .src = MSM_BUS_MASTER_HD_CODEC_PORT1,
344 .dst = MSM_BUS_SLAVE_EBI_CH0,
345 .ab = 501219328,
346 .ib = 2004877312,
347 },
348 {
349 .src = MSM_BUS_MASTER_AMPSS_M0,
350 .dst = MSM_BUS_SLAVE_EBI_CH0,
351 .ab = 2500000,
352 .ib = 5000000,
353 },
354 {
355 .src = MSM_BUS_MASTER_AMPSS_M0,
356 .dst = MSM_BUS_SLAVE_EBI_CH0,
357 .ab = 2500000,
358 .ib = 5000000,
359 },
360};
361static struct msm_bus_vectors vidc_vdec_1080p_vectors[] = {
362 {
363 .src = MSM_BUS_MASTER_HD_CODEC_PORT0,
364 .dst = MSM_BUS_SLAVE_EBI_CH0,
365 .ab = 222298112,
366 .ib = 1778384896,
367 },
368 {
369 .src = MSM_BUS_MASTER_HD_CODEC_PORT1,
370 .dst = MSM_BUS_SLAVE_EBI_CH0,
371 .ab = 330301440,
372 .ib = 1321205760,
373 },
374 {
375 .src = MSM_BUS_MASTER_AMPSS_M0,
376 .dst = MSM_BUS_SLAVE_EBI_CH0,
377 .ab = 2500000,
378 .ib = 700000000,
379 },
380 {
381 .src = MSM_BUS_MASTER_AMPSS_M0,
382 .dst = MSM_BUS_SLAVE_EBI_CH0,
383 .ab = 2500000,
384 .ib = 10000000,
385 },
386};
387
388static struct msm_bus_paths vidc_bus_client_config[] = {
389 {
390 ARRAY_SIZE(vidc_init_vectors),
391 vidc_init_vectors,
392 },
393 {
394 ARRAY_SIZE(vidc_venc_vga_vectors),
395 vidc_venc_vga_vectors,
396 },
397 {
398 ARRAY_SIZE(vidc_vdec_vga_vectors),
399 vidc_vdec_vga_vectors,
400 },
401 {
402 ARRAY_SIZE(vidc_venc_720p_vectors),
403 vidc_venc_720p_vectors,
404 },
405 {
406 ARRAY_SIZE(vidc_vdec_720p_vectors),
407 vidc_vdec_720p_vectors,
408 },
409 {
410 ARRAY_SIZE(vidc_venc_1080p_vectors),
411 vidc_venc_1080p_vectors,
412 },
413 {
414 ARRAY_SIZE(vidc_vdec_1080p_vectors),
415 vidc_vdec_1080p_vectors,
416 },
417};
418
419static struct msm_bus_scale_pdata vidc_bus_client_data = {
420 vidc_bus_client_config,
421 ARRAY_SIZE(vidc_bus_client_config),
422 .name = "vidc",
423};
424#endif
425
426#define MSM_VIDC_BASE_PHYS 0x04400000
427#define MSM_VIDC_BASE_SIZE 0x00100000
428
429static struct resource msm_device_vidc_resources[] = {
430 {
431 .start = MSM_VIDC_BASE_PHYS,
432 .end = MSM_VIDC_BASE_PHYS + MSM_VIDC_BASE_SIZE - 1,
433 .flags = IORESOURCE_MEM,
434 },
435 {
436 .start = VCODEC_IRQ,
437 .end = VCODEC_IRQ,
438 .flags = IORESOURCE_IRQ,
439 },
440};
441
442struct msm_vidc_platform_data vidc_platform_data = {
443#ifdef CONFIG_MSM_BUS_SCALING
444 .vidc_bus_client_pdata = &vidc_bus_client_data,
445#endif
446 .memtype = MEMTYPE_EBI1
447};
448
449struct platform_device msm_device_vidc = {
450 .name = "msm_vidc",
451 .id = 0,
452 .num_resources = ARRAY_SIZE(msm_device_vidc_resources),
453 .resource = msm_device_vidc_resources,
454 .dev = {
455 .platform_data = &vidc_platform_data,
456 },
457};
458
459#define MSM_WCNSS_PHYS 0x03000000
460#define MSM_WCNSS_SIZE 0x280000
461
462static struct resource resources_wcnss_wlan[] = {
463 {
464 .start = RIVA_APPS_WLAN_RX_DATA_AVAIL_IRQ,
465 .end = RIVA_APPS_WLAN_RX_DATA_AVAIL_IRQ,
466 .name = "wcnss_wlanrx_irq",
467 .flags = IORESOURCE_IRQ,
468 },
469 {
470 .start = RIVA_APPS_WLAN_DATA_XFER_DONE_IRQ,
471 .end = RIVA_APPS_WLAN_DATA_XFER_DONE_IRQ,
472 .name = "wcnss_wlantx_irq",
473 .flags = IORESOURCE_IRQ,
474 },
475 {
476 .start = MSM_WCNSS_PHYS,
477 .end = MSM_WCNSS_PHYS + MSM_WCNSS_SIZE - 1,
478 .name = "wcnss_mmio",
479 .flags = IORESOURCE_MEM,
480 },
481};
482
483struct platform_device msm_device_wcnss_wlan = {
484 .name = "wcnss_wlan",
485 .id = 0,
486 .num_resources = ARRAY_SIZE(resources_wcnss_wlan),
487 .resource = resources_wcnss_wlan,
488};
489
490#define MSM_SDC1_BASE 0x12400000
491#define MSM_SDC1_DML_BASE (MSM_SDC1_BASE + 0x800)
492#define MSM_SDC1_BAM_BASE (MSM_SDC1_BASE + 0x2000)
493#define MSM_SDC2_BASE 0x12140000
494#define MSM_SDC2_DML_BASE (MSM_SDC2_BASE + 0x800)
495#define MSM_SDC2_BAM_BASE (MSM_SDC2_BASE + 0x2000)
496#define MSM_SDC2_BASE 0x12140000
497#define MSM_SDC3_BASE 0x12180000
498#define MSM_SDC3_DML_BASE (MSM_SDC3_BASE + 0x800)
499#define MSM_SDC3_BAM_BASE (MSM_SDC3_BASE + 0x2000)
500#define MSM_SDC4_BASE 0x121C0000
501#define MSM_SDC4_DML_BASE (MSM_SDC4_BASE + 0x800)
502#define MSM_SDC4_BAM_BASE (MSM_SDC4_BASE + 0x2000)
503#define MSM_SDC5_BASE 0x12200000
504#define MSM_SDC5_DML_BASE (MSM_SDC5_BASE + 0x800)
505#define MSM_SDC5_BAM_BASE (MSM_SDC5_BASE + 0x2000)
506
507static struct resource resources_sdc1[] = {
508 {
509 .name = "core_mem",
510 .flags = IORESOURCE_MEM,
511 .start = MSM_SDC1_BASE,
512 .end = MSM_SDC1_DML_BASE - 1,
513 },
514 {
515 .name = "core_irq",
516 .flags = IORESOURCE_IRQ,
517 .start = SDC1_IRQ_0,
518 .end = SDC1_IRQ_0
519 },
520#ifdef CONFIG_MMC_MSM_SPS_SUPPORT
521 {
522 .name = "sdcc_dml_addr",
523 .start = MSM_SDC1_DML_BASE,
524 .end = MSM_SDC1_BAM_BASE - 1,
525 .flags = IORESOURCE_MEM,
526 },
527 {
528 .name = "sdcc_bam_addr",
529 .start = MSM_SDC1_BAM_BASE,
530 .end = MSM_SDC1_BAM_BASE + (2 * SZ_4K) - 1,
531 .flags = IORESOURCE_MEM,
532 },
533 {
534 .name = "sdcc_bam_irq",
535 .start = SDC1_BAM_IRQ,
536 .end = SDC1_BAM_IRQ,
537 .flags = IORESOURCE_IRQ,
538 },
539#endif
540};
541
542static struct resource resources_sdc2[] = {
543 {
544 .name = "core_mem",
545 .flags = IORESOURCE_MEM,
546 .start = MSM_SDC2_BASE,
547 .end = MSM_SDC2_DML_BASE - 1,
548 },
549 {
550 .name = "core_irq",
551 .flags = IORESOURCE_IRQ,
552 .start = SDC2_IRQ_0,
553 .end = SDC2_IRQ_0
554 },
555#ifdef CONFIG_MMC_MSM_SPS_SUPPORT
556 {
557 .name = "sdcc_dml_addr",
558 .start = MSM_SDC2_DML_BASE,
559 .end = MSM_SDC2_BAM_BASE - 1,
560 .flags = IORESOURCE_MEM,
561 },
562 {
563 .name = "sdcc_bam_addr",
564 .start = MSM_SDC2_BAM_BASE,
565 .end = MSM_SDC2_BAM_BASE + (2 * SZ_4K) - 1,
566 .flags = IORESOURCE_MEM,
567 },
568 {
569 .name = "sdcc_bam_irq",
570 .start = SDC2_BAM_IRQ,
571 .end = SDC2_BAM_IRQ,
572 .flags = IORESOURCE_IRQ,
573 },
574#endif
575};
576
577static struct resource resources_sdc3[] = {
578 {
579 .name = "core_mem",
580 .flags = IORESOURCE_MEM,
581 .start = MSM_SDC3_BASE,
582 .end = MSM_SDC3_DML_BASE - 1,
583 },
584 {
585 .name = "core_irq",
586 .flags = IORESOURCE_IRQ,
587 .start = SDC3_IRQ_0,
588 .end = SDC3_IRQ_0
589 },
590#ifdef CONFIG_MMC_MSM_SPS_SUPPORT
591 {
592 .name = "sdcc_dml_addr",
593 .start = MSM_SDC3_DML_BASE,
594 .end = MSM_SDC3_BAM_BASE - 1,
595 .flags = IORESOURCE_MEM,
596 },
597 {
598 .name = "sdcc_bam_addr",
599 .start = MSM_SDC3_BAM_BASE,
600 .end = MSM_SDC3_BAM_BASE + (2 * SZ_4K) - 1,
601 .flags = IORESOURCE_MEM,
602 },
603 {
604 .name = "sdcc_bam_irq",
605 .start = SDC3_BAM_IRQ,
606 .end = SDC3_BAM_IRQ,
607 .flags = IORESOURCE_IRQ,
608 },
609#endif
610};
611
612static struct resource resources_sdc4[] = {
613 {
614 .name = "core_mem",
615 .flags = IORESOURCE_MEM,
616 .start = MSM_SDC4_BASE,
617 .end = MSM_SDC4_DML_BASE - 1,
618 },
619 {
620 .name = "core_irq",
621 .flags = IORESOURCE_IRQ,
622 .start = SDC4_IRQ_0,
623 .end = SDC4_IRQ_0
624 },
625#ifdef CONFIG_MMC_MSM_SPS_SUPPORT
626 {
627 .name = "sdcc_dml_addr",
628 .start = MSM_SDC4_DML_BASE,
629 .end = MSM_SDC4_BAM_BASE - 1,
630 .flags = IORESOURCE_MEM,
631 },
632 {
633 .name = "sdcc_bam_addr",
634 .start = MSM_SDC4_BAM_BASE,
635 .end = MSM_SDC4_BAM_BASE + (2 * SZ_4K) - 1,
636 .flags = IORESOURCE_MEM,
637 },
638 {
639 .name = "sdcc_bam_irq",
640 .start = SDC4_BAM_IRQ,
641 .end = SDC4_BAM_IRQ,
642 .flags = IORESOURCE_IRQ,
643 },
644#endif
645};
646
647static struct resource resources_sdc5[] = {
648 {
649 .name = "core_mem",
650 .flags = IORESOURCE_MEM,
651 .start = MSM_SDC5_BASE,
652 .end = MSM_SDC5_DML_BASE - 1,
653 },
654 {
655 .name = "core_irq",
656 .flags = IORESOURCE_IRQ,
657 .start = SDC5_IRQ_0,
658 .end = SDC5_IRQ_0
659 },
660#ifdef CONFIG_MMC_MSM_SPS_SUPPORT
661 {
662 .name = "sdcc_dml_addr",
663 .start = MSM_SDC5_DML_BASE,
664 .end = MSM_SDC5_BAM_BASE - 1,
665 .flags = IORESOURCE_MEM,
666 },
667 {
668 .name = "sdcc_bam_addr",
669 .start = MSM_SDC5_BAM_BASE,
670 .end = MSM_SDC5_BAM_BASE + (2 * SZ_4K) - 1,
671 .flags = IORESOURCE_MEM,
672 },
673 {
674 .name = "sdcc_bam_irq",
675 .start = SDC5_BAM_IRQ,
676 .end = SDC5_BAM_IRQ,
677 .flags = IORESOURCE_IRQ,
678 },
679#endif
680};
681
682struct platform_device msm_device_sdc1 = {
683 .name = "msm_sdcc",
684 .id = 1,
685 .num_resources = ARRAY_SIZE(resources_sdc1),
686 .resource = resources_sdc1,
687 .dev = {
688 .coherent_dma_mask = 0xffffffff,
689 },
690};
691
692struct platform_device msm_device_sdc2 = {
693 .name = "msm_sdcc",
694 .id = 2,
695 .num_resources = ARRAY_SIZE(resources_sdc2),
696 .resource = resources_sdc2,
697 .dev = {
698 .coherent_dma_mask = 0xffffffff,
699 },
700};
701
702struct platform_device msm_device_sdc3 = {
703 .name = "msm_sdcc",
704 .id = 3,
705 .num_resources = ARRAY_SIZE(resources_sdc3),
706 .resource = resources_sdc3,
707 .dev = {
708 .coherent_dma_mask = 0xffffffff,
709 },
710};
711
712struct platform_device msm_device_sdc4 = {
713 .name = "msm_sdcc",
714 .id = 4,
715 .num_resources = ARRAY_SIZE(resources_sdc4),
716 .resource = resources_sdc4,
717 .dev = {
718 .coherent_dma_mask = 0xffffffff,
719 },
720};
721
722struct platform_device msm_device_sdc5 = {
723 .name = "msm_sdcc",
724 .id = 5,
725 .num_resources = ARRAY_SIZE(resources_sdc5),
726 .resource = resources_sdc5,
727 .dev = {
728 .coherent_dma_mask = 0xffffffff,
729 },
730};
731
732struct platform_device msm_device_smd = {
733 .name = "msm_smd",
734 .id = -1,
735};
736
737struct platform_device msm_device_bam_dmux = {
738 .name = "BAM_RMNT",
739 .id = -1,
740};
741
742struct resource msm_dmov_resource[] = {
743 {
744 .start = ADM_0_SCSS_1_IRQ,
745 .end = (resource_size_t)MSM_DMOV_BASE,
746 .flags = IORESOURCE_IRQ,
747 },
748};
749
750struct platform_device msm_device_dmov = {
751 .name = "msm_dmov",
752 .id = -1,
753 .resource = msm_dmov_resource,
754 .num_resources = ARRAY_SIZE(msm_dmov_resource),
755};
756
757static struct platform_device *msm_sdcc_devices[] __initdata = {
758 &msm_device_sdc1,
759 &msm_device_sdc2,
760 &msm_device_sdc3,
761 &msm_device_sdc4,
762 &msm_device_sdc5,
763};
764
765int __init msm_add_sdcc(unsigned int controller, struct mmc_platform_data *plat)
766{
767 struct platform_device *pdev;
768
769 if (controller < 1 || controller > 5)
770 return -EINVAL;
771
772 pdev = msm_sdcc_devices[controller-1];
773 pdev->dev.platform_data = plat;
774 return platform_device_register(pdev);
775}
776
777static struct resource resources_qup_i2c_gsbi4[] = {
778 {
779 .name = "gsbi_qup_i2c_addr",
780 .start = MSM_GSBI4_PHYS,
781 .end = MSM_GSBI4_PHYS + MSM_QUP_SIZE - 1,
782 .flags = IORESOURCE_MEM,
783 },
784 {
785 .name = "qup_phys_addr",
786 .start = MSM_GSBI4_QUP_PHYS,
787 .end = MSM_GSBI4_QUP_PHYS + 4 - 1,
788 .flags = IORESOURCE_MEM,
789 },
790 {
791 .name = "qup_err_intr",
792 .start = GSBI4_QUP_IRQ,
793 .end = GSBI4_QUP_IRQ,
794 .flags = IORESOURCE_IRQ,
795 },
796};
797
798struct platform_device msm8960_device_qup_i2c_gsbi4 = {
799 .name = "qup_i2c",
800 .id = 4,
801 .num_resources = ARRAY_SIZE(resources_qup_i2c_gsbi4),
802 .resource = resources_qup_i2c_gsbi4,
803};
804
805static struct resource resources_qup_i2c_gsbi3[] = {
806 {
807 .name = "gsbi_qup_i2c_addr",
808 .start = MSM_GSBI3_PHYS,
809 .end = MSM_GSBI3_PHYS + MSM_QUP_SIZE - 1,
810 .flags = IORESOURCE_MEM,
811 },
812 {
813 .name = "qup_phys_addr",
814 .start = MSM_GSBI3_QUP_PHYS,
815 .end = MSM_GSBI3_QUP_PHYS + 4 - 1,
816 .flags = IORESOURCE_MEM,
817 },
818 {
819 .name = "qup_err_intr",
820 .start = GSBI3_QUP_IRQ,
821 .end = GSBI3_QUP_IRQ,
822 .flags = IORESOURCE_IRQ,
823 },
824};
825
826struct platform_device msm8960_device_qup_i2c_gsbi3 = {
827 .name = "qup_i2c",
828 .id = 3,
829 .num_resources = ARRAY_SIZE(resources_qup_i2c_gsbi3),
830 .resource = resources_qup_i2c_gsbi3,
831};
832
833static struct resource resources_qup_i2c_gsbi10[] = {
834 {
835 .name = "gsbi_qup_i2c_addr",
836 .start = MSM_GSBI10_PHYS,
837 .end = MSM_GSBI10_PHYS + MSM_QUP_SIZE - 1,
838 .flags = IORESOURCE_MEM,
839 },
840 {
841 .name = "qup_phys_addr",
842 .start = MSM_GSBI10_QUP_PHYS,
843 .end = MSM_GSBI10_QUP_PHYS + 4 - 1,
844 .flags = IORESOURCE_MEM,
845 },
846 {
847 .name = "qup_err_intr",
848 .start = GSBI10_QUP_IRQ,
849 .end = GSBI10_QUP_IRQ,
850 .flags = IORESOURCE_IRQ,
851 },
852};
853
854struct platform_device msm8960_device_qup_i2c_gsbi10 = {
855 .name = "qup_i2c",
856 .id = 10,
857 .num_resources = ARRAY_SIZE(resources_qup_i2c_gsbi10),
858 .resource = resources_qup_i2c_gsbi10,
859};
860
861static struct resource resources_qup_i2c_gsbi12[] = {
862 {
863 .name = "gsbi_qup_i2c_addr",
864 .start = MSM_GSBI12_PHYS,
865 .end = MSM_GSBI12_PHYS + MSM_QUP_SIZE - 1,
866 .flags = IORESOURCE_MEM,
867 },
868 {
869 .name = "qup_phys_addr",
870 .start = MSM_GSBI12_QUP_PHYS,
871 .end = MSM_GSBI12_QUP_PHYS + 4 - 1,
872 .flags = IORESOURCE_MEM,
873 },
874 {
875 .name = "qup_err_intr",
876 .start = GSBI12_QUP_IRQ,
877 .end = GSBI12_QUP_IRQ,
878 .flags = IORESOURCE_IRQ,
879 },
880};
881
882struct platform_device msm8960_device_qup_i2c_gsbi12 = {
883 .name = "qup_i2c",
884 .id = 12,
885 .num_resources = ARRAY_SIZE(resources_qup_i2c_gsbi12),
886 .resource = resources_qup_i2c_gsbi12,
887};
888
889#ifdef CONFIG_MSM_CAMERA
890struct resource msm_camera_resources[] = {
891 {
892 .name = "vfe",
893 .start = 0x04500000,
894 .end = 0x04500000 + SZ_1M - 1,
895 .flags = IORESOURCE_MEM,
896 },
897 {
898 .name = "vfe",
899 .start = VFE_IRQ,
900 .end = VFE_IRQ,
901 .flags = IORESOURCE_IRQ,
902 },
903 {
904 .name = "vid_buf",
905 .flags = IORESOURCE_DMA,
906 },
907 {
908 .name = "ispif",
909 .start = 0x04800800,
910 .end = 0x04800800 + SZ_1K - 1,
911 .flags = IORESOURCE_MEM,
912 },
913 {
914 .name = "ispif",
915 .start = ISPIF_IRQ,
916 .end = ISPIF_IRQ,
917 .flags = IORESOURCE_IRQ,
918 },
919 {
920 .name = "csid0",
921 .start = 0x04800000,
922 .end = 0x04800000 + SZ_1K - 1,
923 .flags = IORESOURCE_MEM,
924 },
925 {
926 .name = "csid0",
927 .start = CSI_0_IRQ,
928 .end = CSI_0_IRQ,
929 .flags = IORESOURCE_IRQ,
930 },
931 {
932 .name = "csiphy0",
933 .start = 0x04800C00,
934 .end = 0x04800C00 + SZ_1K - 1,
935 .flags = IORESOURCE_MEM,
936 },
937 {
938 .name = "csiphy0",
939 .start = CSIPHY_4LN_IRQ,
940 .end = CSIPHY_4LN_IRQ,
941 .flags = IORESOURCE_IRQ,
942 },
943 {
944 .name = "csid1",
945 .start = 0x04800400,
946 .end = 0x04800400 + SZ_1K - 1,
947 .flags = IORESOURCE_MEM,
948 },
949 {
950 .name = "csid1",
951 .start = CSI_1_IRQ,
952 .end = CSI_1_IRQ,
953 .flags = IORESOURCE_IRQ,
954 },
955 {
956 .name = "csiphy1",
957 .start = 0x04801000,
958 .end = 0x04801000 + SZ_1K - 1,
959 .flags = IORESOURCE_MEM,
960 },
961 {
962 .name = "csiphy1",
963 .start = MSM8960_CSIPHY_2LN_IRQ,
964 .end = MSM8960_CSIPHY_2LN_IRQ,
965 .flags = IORESOURCE_IRQ,
966 },
967};
968
969int __init msm_get_cam_resources(struct msm_camera_sensor_info *s_info)
970{
971 s_info->resource = msm_camera_resources;
972 s_info->num_resources = ARRAY_SIZE(msm_camera_resources);
973 return 0;
974}
975#endif
976
977static struct resource resources_ssbi_pm8921[] = {
978 {
979 .start = MSM_PMIC1_SSBI_CMD_PHYS,
980 .end = MSM_PMIC1_SSBI_CMD_PHYS + MSM_PMIC_SSBI_SIZE - 1,
981 .flags = IORESOURCE_MEM,
982 },
983};
984
985struct platform_device msm8960_device_ssbi_pm8921 = {
986 .name = "msm_ssbi",
987 .id = 0,
988 .resource = resources_ssbi_pm8921,
989 .num_resources = ARRAY_SIZE(resources_ssbi_pm8921),
990};
991
992static struct resource resources_qup_spi_gsbi1[] = {
993 {
994 .name = "spi_base",
995 .start = MSM_GSBI1_QUP_PHYS,
996 .end = MSM_GSBI1_QUP_PHYS + SZ_4K - 1,
997 .flags = IORESOURCE_MEM,
998 },
999 {
1000 .name = "gsbi_base",
1001 .start = MSM_GSBI1_PHYS,
1002 .end = MSM_GSBI1_PHYS + 4 - 1,
1003 .flags = IORESOURCE_MEM,
1004 },
1005 {
1006 .name = "spi_irq_in",
1007 .start = MSM8960_GSBI1_QUP_IRQ,
1008 .end = MSM8960_GSBI1_QUP_IRQ,
1009 .flags = IORESOURCE_IRQ,
1010 },
1011};
1012
1013struct platform_device msm8960_device_qup_spi_gsbi1 = {
1014 .name = "spi_qsd",
1015 .id = 0,
1016 .num_resources = ARRAY_SIZE(resources_qup_spi_gsbi1),
1017 .resource = resources_qup_spi_gsbi1,
1018};
1019
1020struct platform_device msm_pcm = {
1021 .name = "msm-pcm-dsp",
1022 .id = -1,
1023};
1024
1025struct platform_device msm_pcm_routing = {
1026 .name = "msm-pcm-routing",
1027 .id = -1,
1028};
1029
1030struct platform_device msm_cpudai0 = {
1031 .name = "msm-dai-q6",
1032 .id = 0x4000,
1033};
1034
1035struct platform_device msm_cpudai1 = {
1036 .name = "msm-dai-q6",
1037 .id = 0x4001,
1038};
1039
1040struct platform_device msm_cpudai_hdmi_rx = {
1041 .name = "msm-dai-q6",
1042 .id = 8,
1043};
1044
1045struct platform_device msm_cpudai_bt_rx = {
1046 .name = "msm-dai-q6",
1047 .id = 0x3000,
1048};
1049
1050struct platform_device msm_cpudai_bt_tx = {
1051 .name = "msm-dai-q6",
1052 .id = 0x3001,
1053};
1054
1055struct platform_device msm_cpudai_fm_rx = {
1056 .name = "msm-dai-q6",
1057 .id = 0x3004,
1058};
1059
1060struct platform_device msm_cpudai_fm_tx = {
1061 .name = "msm-dai-q6",
1062 .id = 0x3005,
1063};
1064
1065struct platform_device msm_cpu_fe = {
1066 .name = "msm-dai-fe",
1067 .id = -1,
1068};
1069
1070struct platform_device msm_stub_codec = {
1071 .name = "msm-stub-codec",
1072 .id = 1,
1073};
1074
1075struct platform_device msm_voice = {
1076 .name = "msm-pcm-voice",
1077 .id = -1,
1078};
1079
1080struct platform_device msm_voip = {
1081 .name = "msm-voip-dsp",
1082 .id = -1,
1083};
1084
1085struct platform_device msm_lpa_pcm = {
1086 .name = "msm-pcm-lpa",
1087 .id = -1,
1088};
1089
1090struct platform_device msm_pcm_hostless = {
1091 .name = "msm-pcm-hostless",
1092 .id = -1,
1093};
1094
1095struct platform_device *msm_footswitch_devices[] = {
1096};
1097unsigned msm_num_footswitch_devices = ARRAY_SIZE(msm_footswitch_devices);
1098
1099#ifdef CONFIG_MSM_ROTATOR
1100#define ROTATOR_HW_BASE 0x04E00000
1101static struct resource resources_msm_rotator[] = {
1102 {
1103 .start = ROTATOR_HW_BASE,
1104 .end = ROTATOR_HW_BASE + 0x100000 - 1,
1105 .flags = IORESOURCE_MEM,
1106 },
1107 {
1108 .start = ROT_IRQ,
1109 .end = ROT_IRQ,
1110 .flags = IORESOURCE_IRQ,
1111 },
1112};
1113
1114static struct msm_rot_clocks rotator_clocks[] = {
1115 {
1116 .clk_name = "rot_clk",
1117 .clk_type = ROTATOR_CORE_CLK,
1118 .clk_rate = 160 * 1000 * 1000,
1119 },
1120 {
1121 .clk_name = "rotator_pclk",
1122 .clk_type = ROTATOR_PCLK,
1123 .clk_rate = 0,
1124 },
1125 {
1126 .clk_name = "rot_axi_clk",
1127 .clk_type = ROTATOR_AXI_CLK,
1128 .clk_rate = 0,
1129 },
1130};
1131
1132static struct msm_rotator_platform_data rotator_pdata = {
1133 .number_of_clocks = ARRAY_SIZE(rotator_clocks),
1134 .hardware_version_number = 0x01020309,
1135 .rotator_clks = rotator_clocks,
1136 .regulator_name = "fs_rot",
1137};
1138
1139struct platform_device msm_rotator_device = {
1140 .name = "msm_rotator",
1141 .id = 0,
1142 .num_resources = ARRAY_SIZE(resources_msm_rotator),
1143 .resource = resources_msm_rotator,
1144 .dev = {
1145 .platform_data = &rotator_pdata,
1146 },
1147};
1148#endif
1149
1150#define MIPI_DSI_HW_BASE 0x04700000
1151#define MDP_HW_BASE 0x05100000
1152
1153static struct resource msm_mipi_dsi1_resources[] = {
1154 {
1155 .name = "mipi_dsi",
1156 .start = MIPI_DSI_HW_BASE,
1157 .end = MIPI_DSI_HW_BASE + 0x000F0000 - 1,
1158 .flags = IORESOURCE_MEM,
1159 },
1160 {
1161 .start = DSI1_IRQ,
1162 .end = DSI1_IRQ,
1163 .flags = IORESOURCE_IRQ,
1164 },
1165};
1166
1167struct platform_device msm_mipi_dsi1_device = {
1168 .name = "mipi_dsi",
1169 .id = 1,
1170 .num_resources = ARRAY_SIZE(msm_mipi_dsi1_resources),
1171 .resource = msm_mipi_dsi1_resources,
1172};
1173
1174static struct resource msm_mdp_resources[] = {
1175 {
1176 .name = "mdp",
1177 .start = MDP_HW_BASE,
1178 .end = MDP_HW_BASE + 0x000F0000 - 1,
1179 .flags = IORESOURCE_MEM,
1180 },
1181 {
1182 .start = MDP_IRQ,
1183 .end = MDP_IRQ,
1184 .flags = IORESOURCE_IRQ,
1185 },
1186};
1187
1188static struct platform_device msm_mdp_device = {
1189 .name = "mdp",
1190 .id = 0,
1191 .num_resources = ARRAY_SIZE(msm_mdp_resources),
1192 .resource = msm_mdp_resources,
1193};
1194
1195static void __init msm_register_device(struct platform_device *pdev, void *data)
1196{
1197 int ret;
1198
1199 pdev->dev.platform_data = data;
1200 ret = platform_device_register(pdev);
1201 if (ret)
1202 dev_err(&pdev->dev,
1203 "%s: platform_device_register() failed = %d\n",
1204 __func__, ret);
1205}
1206
1207void __init msm_fb_register_device(char *name, void *data)
1208{
1209 if (!strncmp(name, "mdp", 3))
1210 msm_register_device(&msm_mdp_device, data);
1211 else if (!strncmp(name, "mipi_dsi", 8))
1212 msm_register_device(&msm_mipi_dsi1_device, data);
1213 else
1214 printk(KERN_ERR "%s: unknown device! %s\n", __func__, name);
1215}
1216
1217static struct resource resources_sps[] = {
1218 {
1219 .name = "pipe_mem",
1220 .start = 0x12800000,
1221 .end = 0x12800000 + 0x4000 - 1,
1222 .flags = IORESOURCE_MEM,
1223 },
1224 {
1225 .name = "bamdma_dma",
1226 .start = 0x12240000,
1227 .end = 0x12240000 + 0x1000 - 1,
1228 .flags = IORESOURCE_MEM,
1229 },
1230 {
1231 .name = "bamdma_bam",
1232 .start = 0x12244000,
1233 .end = 0x12244000 + 0x4000 - 1,
1234 .flags = IORESOURCE_MEM,
1235 },
1236 {
1237 .name = "bamdma_irq",
1238 .start = SPS_BAM_DMA_IRQ,
1239 .end = SPS_BAM_DMA_IRQ,
1240 .flags = IORESOURCE_IRQ,
1241 },
1242};
1243
1244struct msm_sps_platform_data msm_sps_pdata = {
1245 .bamdma_restricted_pipes = 0x06,
1246};
1247
1248struct platform_device msm_device_sps = {
1249 .name = "msm_sps",
1250 .id = -1,
1251 .num_resources = ARRAY_SIZE(resources_sps),
1252 .resource = resources_sps,
1253 .dev.platform_data = &msm_sps_pdata,
1254};
1255
1256#ifdef CONFIG_MSM_MPM
1257static uint16_t msm_mpm_irqs_m2a[MSM_MPM_NR_MPM_IRQS] = {
1258 [1] = MSM_GPIO_TO_INT(61),
1259 [4] = MSM_GPIO_TO_INT(87),
1260 [5] = MSM_GPIO_TO_INT(88),
1261 [6] = MSM_GPIO_TO_INT(89),
1262 [7] = MSM_GPIO_TO_INT(90),
1263 [8] = MSM_GPIO_TO_INT(91),
1264 [9] = MSM_GPIO_TO_INT(34),
1265 [10] = MSM_GPIO_TO_INT(38),
1266 [11] = MSM_GPIO_TO_INT(42),
1267 [12] = MSM_GPIO_TO_INT(46),
1268 [13] = MSM_GPIO_TO_INT(50),
1269 [14] = MSM_GPIO_TO_INT(54),
1270 [15] = MSM_GPIO_TO_INT(58),
1271 [16] = MSM_GPIO_TO_INT(63),
1272 [17] = MSM_GPIO_TO_INT(160),
1273 [18] = MSM_GPIO_TO_INT(162),
1274 [19] = MSM_GPIO_TO_INT(144),
1275 [20] = MSM_GPIO_TO_INT(146),
1276 [25] = USB1_HS_IRQ,
1277 [26] = TV_ENC_IRQ,
1278 [27] = HDMI_IRQ,
1279 [29] = MSM_GPIO_TO_INT(123),
1280 [30] = MSM_GPIO_TO_INT(172),
1281 [31] = MSM_GPIO_TO_INT(99),
1282 [32] = MSM_GPIO_TO_INT(96),
1283 [33] = MSM_GPIO_TO_INT(67),
1284 [34] = MSM_GPIO_TO_INT(71),
1285 [35] = MSM_GPIO_TO_INT(105),
1286 [36] = MSM_GPIO_TO_INT(117),
1287 [37] = MSM_GPIO_TO_INT(29),
1288 [38] = MSM_GPIO_TO_INT(30),
1289 [39] = MSM_GPIO_TO_INT(31),
1290 [40] = MSM_GPIO_TO_INT(37),
1291 [41] = MSM_GPIO_TO_INT(40),
1292 [42] = MSM_GPIO_TO_INT(41),
1293 [43] = MSM_GPIO_TO_INT(45),
1294 [44] = MSM_GPIO_TO_INT(51),
1295 [45] = MSM_GPIO_TO_INT(52),
1296 [46] = MSM_GPIO_TO_INT(57),
1297 [47] = MSM_GPIO_TO_INT(73),
1298 [48] = MSM_GPIO_TO_INT(93),
1299 [49] = MSM_GPIO_TO_INT(94),
1300 [50] = MSM_GPIO_TO_INT(103),
1301 [51] = MSM_GPIO_TO_INT(104),
1302 [52] = MSM_GPIO_TO_INT(106),
1303 [53] = MSM_GPIO_TO_INT(115),
1304 [54] = MSM_GPIO_TO_INT(124),
1305 [55] = MSM_GPIO_TO_INT(125),
1306 [56] = MSM_GPIO_TO_INT(126),
1307 [57] = MSM_GPIO_TO_INT(127),
1308 [58] = MSM_GPIO_TO_INT(128),
1309 [59] = MSM_GPIO_TO_INT(129),
1310};
1311
1312static uint16_t msm_mpm_bypassed_apps_irqs[] = {
1313 TLMM_MSM_SUMMARY_IRQ,
1314 RPM_APCC_CPU0_GP_HIGH_IRQ,
1315 RPM_APCC_CPU0_GP_MEDIUM_IRQ,
1316 RPM_APCC_CPU0_GP_LOW_IRQ,
1317 RPM_APCC_CPU0_WAKE_UP_IRQ,
1318 RPM_APCC_CPU1_GP_HIGH_IRQ,
1319 RPM_APCC_CPU1_GP_MEDIUM_IRQ,
1320 RPM_APCC_CPU1_GP_LOW_IRQ,
1321 RPM_APCC_CPU1_WAKE_UP_IRQ,
1322 MSS_TO_APPS_IRQ_0,
1323 MSS_TO_APPS_IRQ_1,
1324 MSS_TO_APPS_IRQ_2,
1325 MSS_TO_APPS_IRQ_3,
1326 MSS_TO_APPS_IRQ_4,
1327 MSS_TO_APPS_IRQ_5,
1328 MSS_TO_APPS_IRQ_6,
1329 MSS_TO_APPS_IRQ_7,
1330 MSS_TO_APPS_IRQ_8,
1331 MSS_TO_APPS_IRQ_9,
1332 LPASS_SCSS_GP_LOW_IRQ,
1333 LPASS_SCSS_GP_MEDIUM_IRQ,
1334 LPASS_SCSS_GP_HIGH_IRQ,
1335 SPS_MTI_31,
1336};
1337
1338struct msm_mpm_device_data msm_mpm_dev_data = {
1339 .irqs_m2a = msm_mpm_irqs_m2a,
1340 .irqs_m2a_size = ARRAY_SIZE(msm_mpm_irqs_m2a),
1341 .bypassed_apps_irqs = msm_mpm_bypassed_apps_irqs,
1342 .bypassed_apps_irqs_size = ARRAY_SIZE(msm_mpm_bypassed_apps_irqs),
1343 .mpm_request_reg_base = MSM_RPM_BASE + 0x9d8,
1344 .mpm_status_reg_base = MSM_RPM_BASE + 0xdf8,
1345 .mpm_apps_ipc_reg = MSM_APCS_GCC_BASE + 0x008,
1346 .mpm_apps_ipc_val = BIT(1),
1347 .mpm_ipc_irq = RPM_APCC_CPU0_GP_MEDIUM_IRQ,
1348
1349};
1350#endif
1351
1352struct clk_lookup msm_clocks_8960_dummy[] = {
1353 CLK_DUMMY("pll2", PLL2, NULL, 0),
1354 CLK_DUMMY("pll8", PLL8, NULL, 0),
1355 CLK_DUMMY("pll4", PLL4, NULL, 0),
1356
1357 CLK_DUMMY("afab_clk", AFAB_CLK, NULL, 0),
1358 CLK_DUMMY("afab_a_clk", AFAB_A_CLK, NULL, 0),
1359 CLK_DUMMY("cfpb_clk", CFPB_CLK, NULL, 0),
1360 CLK_DUMMY("cfpb_a_clk", CFPB_A_CLK, NULL, 0),
1361 CLK_DUMMY("dfab_clk", DFAB_CLK, NULL, 0),
1362 CLK_DUMMY("dfab_a_clk", DFAB_A_CLK, NULL, 0),
1363 CLK_DUMMY("ebi1_clk", EBI1_CLK, NULL, 0),
1364 CLK_DUMMY("ebi1_a_clk", EBI1_A_CLK, NULL, 0),
1365 CLK_DUMMY("mmfab_clk", MMFAB_CLK, NULL, 0),
1366 CLK_DUMMY("mmfab_a_clk", MMFAB_A_CLK, NULL, 0),
1367 CLK_DUMMY("mmfpb_clk", MMFPB_CLK, NULL, 0),
1368 CLK_DUMMY("mmfpb_a_clk", MMFPB_A_CLK, NULL, 0),
1369 CLK_DUMMY("sfab_clk", SFAB_CLK, NULL, 0),
1370 CLK_DUMMY("sfab_a_clk", SFAB_A_CLK, NULL, 0),
1371 CLK_DUMMY("sfpb_clk", SFPB_CLK, NULL, 0),
1372 CLK_DUMMY("sfpb_a_clk", SFPB_A_CLK, NULL, 0),
1373
1374 CLK_DUMMY("gsbi_uart_clk", GSBI1_UART_CLK, NULL, OFF),
1375 CLK_DUMMY("gsbi_uart_clk", GSBI2_UART_CLK,
1376 "msm_serial_hsl.0", OFF),
1377 CLK_DUMMY("gsbi_uart_clk", GSBI3_UART_CLK, NULL, OFF),
1378 CLK_DUMMY("gsbi_uart_clk", GSBI4_UART_CLK, NULL, OFF),
1379 CLK_DUMMY("gsbi_uart_clk", GSBI5_UART_CLK, NULL, OFF),
1380 CLK_DUMMY("uartdm_clk", GSBI6_UART_CLK, NULL, OFF),
1381 CLK_DUMMY("gsbi_uart_clk", GSBI7_UART_CLK, NULL, OFF),
1382 CLK_DUMMY("gsbi_uart_clk", GSBI8_UART_CLK, NULL, OFF),
1383 CLK_DUMMY("gsbi_uart_clk", GSBI9_UART_CLK, NULL, OFF),
1384 CLK_DUMMY("gsbi_uart_clk", GSBI10_UART_CLK, NULL, OFF),
1385 CLK_DUMMY("gsbi_uart_clk", GSBI11_UART_CLK, NULL, OFF),
1386 CLK_DUMMY("gsbi_uart_clk", GSBI12_UART_CLK, NULL, OFF),
1387 CLK_DUMMY("spi_clk", GSBI1_QUP_CLK, "spi_qsd.0", OFF),
1388 CLK_DUMMY("gsbi_qup_clk", GSBI2_QUP_CLK, NULL, OFF),
1389 CLK_DUMMY("gsbi_qup_clk", GSBI3_QUP_CLK, NULL, OFF),
1390 CLK_DUMMY("gsbi_qup_clk", GSBI4_QUP_CLK,
1391 "qup_i2c.4", OFF),
1392 CLK_DUMMY("gsbi_qup_clk", GSBI5_QUP_CLK, NULL, OFF),
1393 CLK_DUMMY("gsbi_qup_clk", GSBI6_QUP_CLK, NULL, OFF),
1394 CLK_DUMMY("gsbi_qup_clk", GSBI7_QUP_CLK, NULL, OFF),
1395 CLK_DUMMY("gsbi_qup_clk", GSBI8_QUP_CLK, NULL, OFF),
1396 CLK_DUMMY("gsbi_qup_clk", GSBI9_QUP_CLK, NULL, OFF),
1397 CLK_DUMMY("gsbi_qup_clk", GSBI10_QUP_CLK, NULL, OFF),
1398 CLK_DUMMY("gsbi_qup_clk", GSBI11_QUP_CLK, NULL, OFF),
1399 CLK_DUMMY("gsbi_qup_clk", GSBI12_QUP_CLK, NULL, OFF),
1400 CLK_DUMMY("pdm_clk", PDM_CLK, NULL, OFF),
1401 CLK_DUMMY("pmem_clk", PMEM_CLK, NULL, OFF),
1402 CLK_DUMMY("prng_clk", PRNG_CLK, NULL, OFF),
1403 CLK_DUMMY("sdc_clk", SDC1_CLK, NULL, OFF),
1404 CLK_DUMMY("sdc_clk", SDC2_CLK, NULL, OFF),
1405 CLK_DUMMY("sdc_clk", SDC3_CLK, NULL, OFF),
1406 CLK_DUMMY("sdc_clk", SDC4_CLK, NULL, OFF),
1407 CLK_DUMMY("sdc_clk", SDC5_CLK, NULL, OFF),
1408 CLK_DUMMY("tsif_ref_clk", TSIF_REF_CLK, NULL, OFF),
1409 CLK_DUMMY("tssc_clk", TSSC_CLK, NULL, OFF),
1410 CLK_DUMMY("usb_hs_clk", USB_HS1_XCVR_CLK, NULL, OFF),
1411 CLK_DUMMY("usb_phy_clk", USB_PHY0_CLK, NULL, OFF),
1412 CLK_DUMMY("usb_fs_src_clk", USB_FS1_SRC_CLK, NULL, OFF),
1413 CLK_DUMMY("usb_fs_clk", USB_FS1_XCVR_CLK, NULL, OFF),
1414 CLK_DUMMY("usb_fs_sys_clk", USB_FS1_SYS_CLK, NULL, OFF),
1415 CLK_DUMMY("usb_fs_src_clk", USB_FS2_SRC_CLK, NULL, OFF),
1416 CLK_DUMMY("usb_fs_clk", USB_FS2_XCVR_CLK, NULL, OFF),
1417 CLK_DUMMY("usb_fs_sys_clk", USB_FS2_SYS_CLK, NULL, OFF),
1418 CLK_DUMMY("ce_pclk", CE2_CLK, NULL, OFF),
1419 CLK_DUMMY("ce_clk", CE1_CORE_CLK, NULL, OFF),
1420 CLK_DUMMY("spi_pclk", GSBI1_P_CLK, "spi_qsd.0", OFF),
1421 CLK_DUMMY("gsbi_pclk", GSBI2_P_CLK,
1422 "msm_serial_hsl.0", OFF),
1423 CLK_DUMMY("gsbi_pclk", GSBI3_P_CLK, NULL, OFF),
1424 CLK_DUMMY("gsbi_pclk", GSBI4_P_CLK,
1425 "qup_i2c.4", OFF),
1426 CLK_DUMMY("gsbi_pclk", GSBI5_P_CLK, NULL, OFF),
1427 CLK_DUMMY("uartdm_pclk", GSBI6_P_CLK, NULL, OFF),
1428 CLK_DUMMY("gsbi_pclk", GSBI7_P_CLK, NULL, OFF),
1429 CLK_DUMMY("gsbi_pclk", GSBI8_P_CLK, NULL, OFF),
1430 CLK_DUMMY("gsbi_pclk", GSBI9_P_CLK, NULL, OFF),
1431 CLK_DUMMY("gsbi_pclk", GSBI10_P_CLK, NULL, OFF),
1432 CLK_DUMMY("gsbi_pclk", GSBI11_P_CLK, NULL, OFF),
1433 CLK_DUMMY("gsbi_pclk", GSBI12_P_CLK, NULL, OFF),
1434 CLK_DUMMY("gsbi_pclk", GSBI12_P_CLK, NULL, OFF),
1435 CLK_DUMMY("tsif_pclk", TSIF_P_CLK, NULL, OFF),
1436 CLK_DUMMY("usb_fs_pclk", USB_FS1_P_CLK, NULL, OFF),
1437 CLK_DUMMY("usb_fs_pclk", USB_FS2_P_CLK, NULL, OFF),
1438 CLK_DUMMY("usb_hs_pclk", USB_HS1_P_CLK, NULL, OFF),
1439 CLK_DUMMY("sdc_pclk", SDC1_P_CLK, NULL, OFF),
1440 CLK_DUMMY("sdc_pclk", SDC2_P_CLK, NULL, OFF),
1441 CLK_DUMMY("sdc_pclk", SDC3_P_CLK, NULL, OFF),
1442 CLK_DUMMY("sdc_pclk", SDC4_P_CLK, NULL, OFF),
1443 CLK_DUMMY("sdc_pclk", SDC5_P_CLK, NULL, OFF),
1444 CLK_DUMMY("adm_clk", ADM0_CLK, NULL, OFF),
1445 CLK_DUMMY("adm_pclk", ADM0_P_CLK, NULL, OFF),
1446 CLK_DUMMY("pmic_arb_pclk", PMIC_ARB0_P_CLK, NULL, OFF),
1447 CLK_DUMMY("pmic_arb_pclk", PMIC_ARB1_P_CLK, NULL, OFF),
1448 CLK_DUMMY("pmic_ssbi2", PMIC_SSBI2_CLK, NULL, OFF),
1449 CLK_DUMMY("rpm_msg_ram_pclk", RPM_MSG_RAM_P_CLK, NULL, OFF),
1450 CLK_DUMMY("amp_clk", AMP_CLK, NULL, OFF),
1451 CLK_DUMMY("cam_clk", CAM0_CLK, NULL, OFF),
1452 CLK_DUMMY("cam_clk", CAM1_CLK, NULL, OFF),
1453 CLK_DUMMY("csi_src_clk", CSI0_SRC_CLK, NULL, OFF),
1454 CLK_DUMMY("csi_src_clk", CSI1_SRC_CLK, NULL, OFF),
1455 CLK_DUMMY("csi_clk", CSI0_CLK, NULL, OFF),
1456 CLK_DUMMY("csi_clk", CSI1_CLK, NULL, OFF),
1457 CLK_DUMMY("csi_pix_clk", CSI_PIX_CLK, NULL, OFF),
1458 CLK_DUMMY("csi_rdi_clk", CSI_RDI_CLK, NULL, OFF),
1459 CLK_DUMMY("csiphy_timer_src_clk", CSIPHY_TIMER_SRC_CLK, NULL, OFF),
1460 CLK_DUMMY("csi0phy_timer_clk", CSIPHY0_TIMER_CLK, NULL, OFF),
1461 CLK_DUMMY("csi1phy_timer_clk", CSIPHY1_TIMER_CLK, NULL, OFF),
1462 CLK_DUMMY("dsi_byte_div_clk", DSI1_BYTE_CLK, "mipi_dsi.1", OFF),
1463 CLK_DUMMY("dsi_byte_div_clk", DSI2_BYTE_CLK, "mipi_dsi.2", OFF),
1464 CLK_DUMMY("dsi_esc_clk", DSI1_ESC_CLK, "mipi_dsi.1", OFF),
1465 CLK_DUMMY("dsi_esc_clk", DSI2_ESC_CLK, "mipi_dsi.2", OFF),
1466 CLK_DUMMY("gfx2d0_clk", GFX2D0_CLK, NULL, OFF),
1467 CLK_DUMMY("gfx2d1_clk", GFX2D1_CLK, NULL, OFF),
1468 CLK_DUMMY("gfx3d_clk", GFX3D_CLK, NULL, OFF),
1469 CLK_DUMMY("ijpeg_clk", IJPEG_CLK, NULL, OFF),
1470 CLK_DUMMY("imem_clk", IMEM_CLK, NULL, OFF),
1471 CLK_DUMMY("jpegd_clk", JPEGD_CLK, NULL, OFF),
1472 CLK_DUMMY("mdp_clk", MDP_CLK, NULL, OFF),
1473 CLK_DUMMY("mdp_vsync_clk", MDP_VSYNC_CLK, NULL, OFF),
1474 CLK_DUMMY("lut_mdp", LUT_MDP_CLK, NULL, OFF),
1475 CLK_DUMMY("rot_clk", ROT_CLK, NULL, OFF),
1476 CLK_DUMMY("tv_src_clk", TV_SRC_CLK, NULL, OFF),
1477 CLK_DUMMY("tv_enc_clk", TV_ENC_CLK, NULL, OFF),
1478 CLK_DUMMY("tv_dac_clk", TV_DAC_CLK, NULL, OFF),
1479 CLK_DUMMY("vcodec_clk", VCODEC_CLK, NULL, OFF),
1480 CLK_DUMMY("mdp_tv_clk", MDP_TV_CLK, NULL, OFF),
1481 CLK_DUMMY("hdmi_clk", HDMI_TV_CLK, NULL, OFF),
1482 CLK_DUMMY("hdmi_app_clk", HDMI_APP_CLK, NULL, OFF),
1483 CLK_DUMMY("vpe_clk", VPE_CLK, NULL, OFF),
1484 CLK_DUMMY("vfe_clk", VFE_CLK, NULL, OFF),
1485 CLK_DUMMY("csi_vfe_clk", CSI0_VFE_CLK, NULL, OFF),
1486 CLK_DUMMY("vfe_axi_clk", VFE_AXI_CLK, NULL, OFF),
1487 CLK_DUMMY("ijpeg_axi_clk", IJPEG_AXI_CLK, NULL, OFF),
1488 CLK_DUMMY("mdp_axi_clk", MDP_AXI_CLK, NULL, OFF),
1489 CLK_DUMMY("rot_axi_clk", ROT_AXI_CLK, NULL, OFF),
1490 CLK_DUMMY("vcodec_axi_clk", VCODEC_AXI_CLK, NULL, OFF),
1491 CLK_DUMMY("vcodec_axi_a_clk", VCODEC_AXI_A_CLK, NULL, OFF),
1492 CLK_DUMMY("vcodec_axi_b_clk", VCODEC_AXI_B_CLK, NULL, OFF),
1493 CLK_DUMMY("vpe_axi_clk", VPE_AXI_CLK, NULL, OFF),
1494 CLK_DUMMY("amp_pclk", AMP_P_CLK, NULL, OFF),
1495 CLK_DUMMY("csi_pclk", CSI0_P_CLK, NULL, OFF),
1496 CLK_DUMMY("dsi_m_pclk", DSI1_M_P_CLK, "mipi_dsi.1", OFF),
1497 CLK_DUMMY("dsi_s_pclk", DSI1_S_P_CLK, "mipi_dsi.1", OFF),
1498 CLK_DUMMY("dsi_m_pclk", DSI2_M_P_CLK, "mipi_dsi.2", OFF),
1499 CLK_DUMMY("dsi_s_pclk", DSI2_S_P_CLK, "mipi_dsi.2", OFF),
1500 CLK_DUMMY("gfx2d0_pclk", GFX2D0_P_CLK, NULL, OFF),
1501 CLK_DUMMY("gfx2d1_pclk", GFX2D1_P_CLK, NULL, OFF),
1502 CLK_DUMMY("gfx3d_pclk", GFX3D_P_CLK, NULL, OFF),
1503 CLK_DUMMY("hdmi_m_pclk", HDMI_M_P_CLK, NULL, OFF),
1504 CLK_DUMMY("hdmi_s_pclk", HDMI_S_P_CLK, NULL, OFF),
1505 CLK_DUMMY("ijpeg_pclk", IJPEG_P_CLK, NULL, OFF),
1506 CLK_DUMMY("jpegd_pclk", JPEGD_P_CLK, NULL, OFF),
1507 CLK_DUMMY("imem_pclk", IMEM_P_CLK, NULL, OFF),
1508 CLK_DUMMY("mdp_pclk", MDP_P_CLK, NULL, OFF),
1509 CLK_DUMMY("smmu_pclk", SMMU_P_CLK, NULL, OFF),
1510 CLK_DUMMY("rotator_pclk", ROT_P_CLK, NULL, OFF),
1511 CLK_DUMMY("tv_enc_pclk", TV_ENC_P_CLK, NULL, OFF),
1512 CLK_DUMMY("vcodec_pclk", VCODEC_P_CLK, NULL, OFF),
1513 CLK_DUMMY("vfe_pclk", VFE_P_CLK, NULL, OFF),
1514 CLK_DUMMY("vpe_pclk", VPE_P_CLK, NULL, OFF),
1515 CLK_DUMMY("mi2s_osr_clk", MI2S_OSR_CLK, NULL, OFF),
1516 CLK_DUMMY("mi2s_bit_clk", MI2S_BIT_CLK, NULL, OFF),
1517 CLK_DUMMY("i2s_mic_osr_clk", CODEC_I2S_MIC_OSR_CLK, NULL, OFF),
1518 CLK_DUMMY("i2s_mic_bit_clk", CODEC_I2S_MIC_BIT_CLK, NULL, OFF),
1519 CLK_DUMMY("i2s_mic_osr_clk", SPARE_I2S_MIC_OSR_CLK, NULL, OFF),
1520 CLK_DUMMY("i2s_mic_bit_clk", SPARE_I2S_MIC_BIT_CLK, NULL, OFF),
1521 CLK_DUMMY("i2s_spkr_osr_clk", CODEC_I2S_SPKR_OSR_CLK, NULL, OFF),
1522 CLK_DUMMY("i2s_spkr_bit_clk", CODEC_I2S_SPKR_BIT_CLK, NULL, OFF),
1523 CLK_DUMMY("i2s_spkr_osr_clk", SPARE_I2S_SPKR_OSR_CLK, NULL, OFF),
1524 CLK_DUMMY("i2s_spkr_bit_clk", SPARE_I2S_SPKR_BIT_CLK, NULL, OFF),
1525 CLK_DUMMY("pcm_clk", PCM_CLK, NULL, OFF),
1526 CLK_DUMMY("iommu_clk", JPEGD_AXI_CLK, NULL, 0),
1527 CLK_DUMMY("iommu_clk", VFE_AXI_CLK, NULL, 0),
1528 CLK_DUMMY("iommu_clk", VCODEC_AXI_CLK, NULL, 0),
1529 CLK_DUMMY("iommu_clk", GFX3D_CLK, NULL, 0),
1530 CLK_DUMMY("iommu_clk", GFX2D0_CLK, NULL, 0),
1531 CLK_DUMMY("iommu_clk", GFX2D1_CLK, NULL, 0),
1532
1533 CLK_DUMMY("dfab_dsps_clk", DFAB_DSPS_CLK, NULL, 0),
1534 CLK_DUMMY("dfab_usb_hs_clk", DFAB_USB_HS_CLK, NULL, 0),
1535 CLK_DUMMY("dfab_sdc_clk", DFAB_SDC1_CLK, "msm_sdcc.1", 0),
1536 CLK_DUMMY("dfab_sdc_clk", DFAB_SDC2_CLK, "msm_sdcc.2", 0),
1537 CLK_DUMMY("dfab_sdc_clk", DFAB_SDC3_CLK, "msm_sdcc.3", 0),
1538 CLK_DUMMY("dfab_sdc_clk", DFAB_SDC4_CLK, "msm_sdcc.4", 0),
1539 CLK_DUMMY("dfab_sdc_clk", DFAB_SDC5_CLK, "msm_sdcc.5", 0),
1540 CLK_DUMMY("dfab_clk", DFAB_CLK, NULL, 0),
1541 CLK_DUMMY("dma_bam_pclk", DMA_BAM_P_CLK, NULL, 0),
1542};
1543
1544unsigned msm_num_clocks_8960_dummy = ARRAY_SIZE(msm_clocks_8960_dummy);
1545
1546#define LPASS_SLIMBUS_PHYS 0x28080000
1547#define LPASS_SLIMBUS_BAM_PHYS 0x28084000
1548/* Board info for the slimbus slave device */
1549static struct resource slimbus_res[] = {
1550 {
1551 .start = LPASS_SLIMBUS_PHYS,
1552 .end = LPASS_SLIMBUS_PHYS + 8191,
1553 .flags = IORESOURCE_MEM,
1554 .name = "slimbus_physical",
1555 },
1556 {
1557 .start = LPASS_SLIMBUS_BAM_PHYS,
1558 .end = LPASS_SLIMBUS_BAM_PHYS + 8191,
1559 .flags = IORESOURCE_MEM,
1560 .name = "slimbus_bam_physical",
1561 },
1562 {
1563 .start = SLIMBUS0_CORE_EE1_IRQ,
1564 .end = SLIMBUS0_CORE_EE1_IRQ,
1565 .flags = IORESOURCE_IRQ,
1566 .name = "slimbus_irq",
1567 },
1568 {
1569 .start = SLIMBUS0_BAM_EE1_IRQ,
1570 .end = SLIMBUS0_BAM_EE1_IRQ,
1571 .flags = IORESOURCE_IRQ,
1572 .name = "slimbus_bam_irq",
1573 },
1574};
1575
1576struct platform_device msm_slim_ctrl = {
1577 .name = "msm_slim_ctrl",
1578 .id = 1,
1579 .num_resources = ARRAY_SIZE(slimbus_res),
1580 .resource = slimbus_res,
1581 .dev = {
1582 .coherent_dma_mask = 0xffffffffULL,
1583 },
1584};
1585
1586#ifdef CONFIG_MSM_BUS_SCALING
1587static struct msm_bus_vectors grp3d_init_vectors[] = {
1588 {
1589 .src = MSM_BUS_MASTER_GRAPHICS_3D,
1590 .dst = MSM_BUS_SLAVE_EBI_CH0,
1591 .ab = 0,
1592 .ib = 0,
1593 },
1594};
1595
1596static struct msm_bus_vectors grp3d_nominal_vectors[] = {
1597 {
1598 .src = MSM_BUS_MASTER_GRAPHICS_3D,
1599 .dst = MSM_BUS_SLAVE_EBI_CH0,
1600 .ab = 0,
1601 .ib = 200800000U,
1602 },
1603};
1604
1605static struct msm_bus_vectors grp3d_max_vectors[] = {
1606 {
1607 .src = MSM_BUS_MASTER_GRAPHICS_3D,
1608 .dst = MSM_BUS_SLAVE_EBI_CH0,
1609 .ab = 0,
1610 .ib = 2096000000U,
1611 },
1612};
1613
1614static struct msm_bus_paths grp3d_bus_scale_usecases[] = {
1615 {
1616 ARRAY_SIZE(grp3d_init_vectors),
1617 grp3d_init_vectors,
1618 },
1619 {
1620 ARRAY_SIZE(grp3d_nominal_vectors),
1621 grp3d_nominal_vectors,
1622 },
1623 {
1624 ARRAY_SIZE(grp3d_max_vectors),
1625 grp3d_max_vectors,
1626 },
1627};
1628
1629static struct msm_bus_scale_pdata grp3d_bus_scale_pdata = {
1630 grp3d_bus_scale_usecases,
1631 ARRAY_SIZE(grp3d_bus_scale_usecases),
1632 .name = "grp3d",
1633};
1634
1635static struct msm_bus_vectors grp2d0_init_vectors[] = {
1636 {
1637 .src = MSM_BUS_MASTER_GRAPHICS_2D_CORE0,
1638 .dst = MSM_BUS_SLAVE_EBI_CH0,
1639 .ab = 0,
1640 .ib = 0,
1641 },
1642};
1643
1644static struct msm_bus_vectors grp2d0_max_vectors[] = {
1645 {
1646 .src = MSM_BUS_MASTER_GRAPHICS_2D_CORE0,
1647 .dst = MSM_BUS_SLAVE_EBI_CH0,
1648 .ab = 0,
1649 .ib = 248000000,
1650 },
1651};
1652
1653static struct msm_bus_paths grp2d0_bus_scale_usecases[] = {
1654 {
1655 ARRAY_SIZE(grp2d0_init_vectors),
1656 grp2d0_init_vectors,
1657 },
1658 {
1659 ARRAY_SIZE(grp2d0_max_vectors),
1660 grp2d0_max_vectors,
1661 },
1662};
1663
1664struct msm_bus_scale_pdata grp2d0_bus_scale_pdata = {
1665 grp2d0_bus_scale_usecases,
1666 ARRAY_SIZE(grp2d0_bus_scale_usecases),
1667 .name = "grp2d0",
1668};
1669
1670static struct msm_bus_vectors grp2d1_init_vectors[] = {
1671 {
1672 .src = MSM_BUS_MASTER_GRAPHICS_2D_CORE1,
1673 .dst = MSM_BUS_SLAVE_EBI_CH0,
1674 .ab = 0,
1675 .ib = 0,
1676 },
1677};
1678
1679static struct msm_bus_vectors grp2d1_max_vectors[] = {
1680 {
1681 .src = MSM_BUS_MASTER_GRAPHICS_2D_CORE1,
1682 .dst = MSM_BUS_SLAVE_EBI_CH0,
1683 .ab = 0,
1684 .ib = 248000000,
1685 },
1686};
1687
1688static struct msm_bus_paths grp2d1_bus_scale_usecases[] = {
1689 {
1690 ARRAY_SIZE(grp2d1_init_vectors),
1691 grp2d1_init_vectors,
1692 },
1693 {
1694 ARRAY_SIZE(grp2d1_max_vectors),
1695 grp2d1_max_vectors,
1696 },
1697};
1698
1699struct msm_bus_scale_pdata grp2d1_bus_scale_pdata = {
1700 grp2d1_bus_scale_usecases,
1701 ARRAY_SIZE(grp2d1_bus_scale_usecases),
1702 .name = "grp2d1",
1703};
1704#endif
1705
1706static struct resource kgsl_3d0_resources[] = {
1707 {
1708 .name = KGSL_3D0_REG_MEMORY,
1709 .start = 0x04300000, /* GFX3D address */
1710 .end = 0x0431ffff,
1711 .flags = IORESOURCE_MEM,
1712 },
1713 {
1714 .name = KGSL_3D0_IRQ,
1715 .start = GFX3D_IRQ,
1716 .end = GFX3D_IRQ,
1717 .flags = IORESOURCE_IRQ,
1718 },
1719};
1720
1721static struct kgsl_device_platform_data kgsl_3d0_pdata = {
1722 .pwr_data = {
1723 .pwrlevel = {
1724 {
1725 .gpu_freq = 266667000,
1726 .bus_freq = 2,
1727 },
1728 {
1729 .gpu_freq = 228571000,
1730 .bus_freq = 1,
1731 },
1732 {
1733 .gpu_freq = 266667000,
1734 .bus_freq = 0,
1735 },
1736 },
1737 .init_level = 0,
1738 .num_levels = 3,
1739 .set_grp_async = NULL,
1740 .idle_timeout = HZ/5,
1741#ifdef CONFIG_MSM_BUS_SCALING
1742 .nap_allowed = true,
1743#endif
1744 },
1745 .clk = {
1746 .name = {
1747 .clk = "gfx3d_clk",
1748 .pclk = "gfx3d_pclk",
1749 },
1750#ifdef CONFIG_MSM_BUS_SCALING
1751 .bus_scale_table = &grp3d_bus_scale_pdata,
1752#endif
1753 },
1754 .imem_clk_name = {
1755 .clk = NULL,
1756 .pclk = "imem_pclk",
1757 },
1758};
1759
1760struct platform_device msm_kgsl_3d0 = {
1761 .name = "kgsl-3d0",
1762 .id = 0,
1763 .num_resources = ARRAY_SIZE(kgsl_3d0_resources),
1764 .resource = kgsl_3d0_resources,
1765 .dev = {
1766 .platform_data = &kgsl_3d0_pdata,
1767 },
1768};
1769
1770static struct resource kgsl_2d0_resources[] = {
1771 {
1772 .name = KGSL_2D0_REG_MEMORY,
1773 .start = 0x04100000, /* Z180 base address */
1774 .end = 0x04100FFF,
1775 .flags = IORESOURCE_MEM,
1776 },
1777 {
1778 .name = KGSL_2D0_IRQ,
1779 .start = GFX2D0_IRQ,
1780 .end = GFX2D0_IRQ,
1781 .flags = IORESOURCE_IRQ,
1782 },
1783};
1784
1785static struct kgsl_device_platform_data kgsl_2d0_pdata = {
1786 .pwr_data = {
1787 .pwrlevel = {
1788 {
1789 .gpu_freq = 200000000,
1790 .bus_freq = 1,
1791 },
1792 {
1793 .gpu_freq = 200000000,
1794 .bus_freq = 0,
1795 },
1796 },
1797 .init_level = 0,
1798 .num_levels = 2,
1799 .set_grp_async = NULL,
1800 .idle_timeout = HZ/10,
1801#ifdef CONFIG_MSM_BUS_SCALING
1802 .nap_allowed = true,
1803#endif
1804 },
1805 .clk = {
1806 .name = {
1807 /* note: 2d clocks disabled on v1 */
1808 .clk = "gfx2d0_clk",
1809 .pclk = "gfx2d0_pclk",
1810 },
1811#ifdef CONFIG_MSM_BUS_SCALING
1812 .bus_scale_table = &grp2d0_bus_scale_pdata,
1813#endif
1814 },
1815};
1816
1817struct platform_device msm_kgsl_2d0 = {
1818 .name = "kgsl-2d0",
1819 .id = 0,
1820 .num_resources = ARRAY_SIZE(kgsl_2d0_resources),
1821 .resource = kgsl_2d0_resources,
1822 .dev = {
1823 .platform_data = &kgsl_2d0_pdata,
1824 },
1825};
1826
1827static struct resource kgsl_2d1_resources[] = {
1828 {
1829 .name = KGSL_2D1_REG_MEMORY,
1830 .start = 0x04200000, /* Z180 device 1 base address */
1831 .end = 0x04200FFF,
1832 .flags = IORESOURCE_MEM,
1833 },
1834 {
1835 .name = KGSL_2D1_IRQ,
1836 .start = GFX2D1_IRQ,
1837 .end = GFX2D1_IRQ,
1838 .flags = IORESOURCE_IRQ,
1839 },
1840};
1841
1842static struct kgsl_device_platform_data kgsl_2d1_pdata = {
1843 .pwr_data = {
1844 .pwrlevel = {
1845 {
1846 .gpu_freq = 200000000,
1847 .bus_freq = 1,
1848 },
1849 {
1850 .gpu_freq = 200000000,
1851 .bus_freq = 0,
1852 },
1853 },
1854 .init_level = 0,
1855 .num_levels = 2,
1856 .set_grp_async = NULL,
1857 .idle_timeout = HZ/10,
1858#ifdef CONFIG_MSM_BUS_SCALING
1859 .nap_allowed = true,
1860#endif
1861 },
1862 .clk = {
1863 .name = {
1864 .clk = "gfx2d1_clk",
1865 .pclk = "gfx2d1_pclk",
1866 },
1867#ifdef CONFIG_MSM_BUS_SCALING
1868 .bus_scale_table = &grp2d1_bus_scale_pdata,
1869#endif
1870 },
1871};
1872
1873struct platform_device msm_kgsl_2d1 = {
1874 .name = "kgsl-2d1",
1875 .id = 1,
1876 .num_resources = ARRAY_SIZE(kgsl_2d1_resources),
1877 .resource = kgsl_2d1_resources,
1878 .dev = {
1879 .platform_data = &kgsl_2d1_pdata,
1880 },
1881};
1882
1883#ifdef CONFIG_MSM_GEMINI
1884static struct resource msm_gemini_resources[] = {
1885 {
1886 .start = 0x04600000,
1887 .end = 0x04600000 + SZ_1M - 1,
1888 .flags = IORESOURCE_MEM,
1889 },
1890 {
1891 .start = JPEG_IRQ,
1892 .end = JPEG_IRQ,
1893 .flags = IORESOURCE_IRQ,
1894 },
1895};
1896
1897struct platform_device msm8960_gemini_device = {
1898 .name = "msm_gemini",
1899 .resource = msm_gemini_resources,
1900 .num_resources = ARRAY_SIZE(msm_gemini_resources),
1901};
1902#endif
1903
1904struct msm_rpm_map_data rpm_map_data[] __initdata = {
1905 MSM_RPM_MAP(TRIGGER_TIMED_TO, TRIGGER_TIMED, 1),
1906 MSM_RPM_MAP(TRIGGER_TIMED_SCLK_COUNT, TRIGGER_TIMED, 1),
1907
1908 MSM_RPM_MAP(RPM_CTL, RPM_CTL, 1),
1909
1910 MSM_RPM_MAP(CXO_CLK, CXO_CLK, 1),
1911 MSM_RPM_MAP(PXO_CLK, PXO_CLK, 1),
1912 MSM_RPM_MAP(APPS_FABRIC_CLK, APPS_FABRIC_CLK, 1),
1913 MSM_RPM_MAP(SYSTEM_FABRIC_CLK, SYSTEM_FABRIC_CLK, 1),
1914 MSM_RPM_MAP(MM_FABRIC_CLK, MM_FABRIC_CLK, 1),
1915 MSM_RPM_MAP(DAYTONA_FABRIC_CLK, DAYTONA_FABRIC_CLK, 1),
1916 MSM_RPM_MAP(SFPB_CLK, SFPB_CLK, 1),
1917 MSM_RPM_MAP(CFPB_CLK, CFPB_CLK, 1),
1918 MSM_RPM_MAP(MMFPB_CLK, MMFPB_CLK, 1),
1919 MSM_RPM_MAP(EBI1_CLK, EBI1_CLK, 1),
1920
1921 MSM_RPM_MAP(APPS_FABRIC_CFG_HALT_0, APPS_FABRIC_CFG_HALT, 2),
1922 MSM_RPM_MAP(APPS_FABRIC_CFG_CLKMOD_0, APPS_FABRIC_CFG_CLKMOD, 3),
1923 MSM_RPM_MAP(APPS_FABRIC_CFG_IOCTL, APPS_FABRIC_CFG_IOCTL, 1),
1924 MSM_RPM_MAP(APPS_FABRIC_ARB_0, APPS_FABRIC_ARB, 12),
1925
1926 MSM_RPM_MAP(SYS_FABRIC_CFG_HALT_0, SYS_FABRIC_CFG_HALT, 2),
1927 MSM_RPM_MAP(SYS_FABRIC_CFG_CLKMOD_0, SYS_FABRIC_CFG_CLKMOD, 3),
1928 MSM_RPM_MAP(SYS_FABRIC_CFG_IOCTL, SYS_FABRIC_CFG_IOCTL, 1),
1929 MSM_RPM_MAP(SYSTEM_FABRIC_ARB_0, SYSTEM_FABRIC_ARB, 27),
1930
1931 MSM_RPM_MAP(MMSS_FABRIC_CFG_HALT_0, MMSS_FABRIC_CFG_HALT, 2),
1932 MSM_RPM_MAP(MMSS_FABRIC_CFG_CLKMOD_0, MMSS_FABRIC_CFG_CLKMOD, 3),
1933 MSM_RPM_MAP(MMSS_FABRIC_CFG_IOCTL, MMSS_FABRIC_CFG_IOCTL, 1),
1934 MSM_RPM_MAP(MM_FABRIC_ARB_0, MM_FABRIC_ARB, 23),
1935
1936 MSM_RPM_MAP(PM8921_S1_0, PM8921_S1, 2),
1937 MSM_RPM_MAP(PM8921_S2_0, PM8921_S2, 2),
1938 MSM_RPM_MAP(PM8921_S3_0, PM8921_S3, 2),
1939 MSM_RPM_MAP(PM8921_S4_0, PM8921_S4, 2),
1940 MSM_RPM_MAP(PM8921_S5_0, PM8921_S5, 2),
1941 MSM_RPM_MAP(PM8921_S6_0, PM8921_S6, 2),
1942 MSM_RPM_MAP(PM8921_S7_0, PM8921_S7, 2),
1943 MSM_RPM_MAP(PM8921_S8_0, PM8921_S8, 2),
1944 MSM_RPM_MAP(PM8921_L1_0, PM8921_L1, 2),
1945 MSM_RPM_MAP(PM8921_L2_0, PM8921_L2, 2),
1946 MSM_RPM_MAP(PM8921_L3_0, PM8921_L3, 2),
1947 MSM_RPM_MAP(PM8921_L4_0, PM8921_L4, 2),
1948 MSM_RPM_MAP(PM8921_L5_0, PM8921_L5, 2),
1949 MSM_RPM_MAP(PM8921_L6_0, PM8921_L6, 2),
1950 MSM_RPM_MAP(PM8921_L7_0, PM8921_L7, 2),
1951 MSM_RPM_MAP(PM8921_L8_0, PM8921_L8, 2),
1952 MSM_RPM_MAP(PM8921_L9_0, PM8921_L9, 2),
1953 MSM_RPM_MAP(PM8921_L10_0, PM8921_L10, 2),
1954 MSM_RPM_MAP(PM8921_L11_0, PM8921_L11, 2),
1955 MSM_RPM_MAP(PM8921_L12_0, PM8921_L12, 2),
1956 MSM_RPM_MAP(PM8921_L13_0, PM8921_L13, 2),
1957 MSM_RPM_MAP(PM8921_L14_0, PM8921_L14, 2),
1958 MSM_RPM_MAP(PM8921_L15_0, PM8921_L15, 2),
1959 MSM_RPM_MAP(PM8921_L16_0, PM8921_L16, 2),
1960 MSM_RPM_MAP(PM8921_L17_0, PM8921_L17, 2),
1961 MSM_RPM_MAP(PM8921_L18_0, PM8921_L18, 2),
1962 MSM_RPM_MAP(PM8921_L19_0, PM8921_L19, 2),
1963 MSM_RPM_MAP(PM8921_L20_0, PM8921_L20, 2),
1964 MSM_RPM_MAP(PM8921_L21_0, PM8921_L21, 2),
1965 MSM_RPM_MAP(PM8921_L22_0, PM8921_L22, 2),
1966 MSM_RPM_MAP(PM8921_L23_0, PM8921_L23, 2),
1967 MSM_RPM_MAP(PM8921_L24_0, PM8921_L24, 2),
1968 MSM_RPM_MAP(PM8921_L25_0, PM8921_L25, 2),
1969 MSM_RPM_MAP(PM8921_L26_0, PM8921_L26, 2),
1970 MSM_RPM_MAP(PM8921_L27_0, PM8921_L27, 2),
1971 MSM_RPM_MAP(PM8921_L28_0, PM8921_L28, 2),
1972 MSM_RPM_MAP(PM8921_L29_0, PM8921_L29, 2),
1973 MSM_RPM_MAP(PM8921_CLK1_0, PM8921_CLK1, 2),
1974 MSM_RPM_MAP(PM8921_CLK2_0, PM8921_CLK2, 2),
1975 MSM_RPM_MAP(PM8921_LVS1, PM8921_LVS1, 1),
1976 MSM_RPM_MAP(PM8921_LVS2, PM8921_LVS2, 1),
1977 MSM_RPM_MAP(PM8921_LVS3, PM8921_LVS3, 1),
1978 MSM_RPM_MAP(PM8921_LVS4, PM8921_LVS4, 1),
1979 MSM_RPM_MAP(PM8921_LVS5, PM8921_LVS5, 1),
1980 MSM_RPM_MAP(PM8921_LVS6, PM8921_LVS6, 1),
1981 MSM_RPM_MAP(PM8921_LVS7, PM8921_LVS7, 1),
1982 MSM_RPM_MAP(NCP_0, NCP, 2),
1983 MSM_RPM_MAP(CXO_BUFFERS, CXO_BUFFERS, 1),
1984 MSM_RPM_MAP(USB_OTG_SWITCH, USB_OTG_SWITCH, 1),
1985 MSM_RPM_MAP(HDMI_SWITCH, HDMI_SWITCH, 1),
1986
1987};
1988unsigned int rpm_map_data_size = ARRAY_SIZE(rpm_map_data);
1989
1990struct platform_device msm_bus_sys_fabric = {
1991 .name = "msm_bus_fabric",
1992 .id = MSM_BUS_FAB_SYSTEM,
1993};
1994struct platform_device msm_bus_apps_fabric = {
1995 .name = "msm_bus_fabric",
1996 .id = MSM_BUS_FAB_APPSS,
1997};
1998struct platform_device msm_bus_mm_fabric = {
1999 .name = "msm_bus_fabric",
2000 .id = MSM_BUS_FAB_MMSS,
2001};
2002struct platform_device msm_bus_sys_fpb = {
2003 .name = "msm_bus_fabric",
2004 .id = MSM_BUS_FAB_SYSTEM_FPB,
2005};
2006struct platform_device msm_bus_cpss_fpb = {
2007 .name = "msm_bus_fabric",
2008 .id = MSM_BUS_FAB_CPSS_FPB,
2009};
2010
2011/* Sensors DSPS platform data */
2012#ifdef CONFIG_MSM_DSPS
2013
2014#define PPSS_REG_PHYS_BASE 0x12080000
2015
2016static struct dsps_clk_info dsps_clks[] = {};
2017static struct dsps_regulator_info dsps_regs[] = {};
2018
2019/*
2020 * Note: GPIOs field is intialized in run-time at the function
2021 * msm8960_init_dsps().
2022 */
2023
2024struct msm_dsps_platform_data msm_dsps_pdata = {
2025 .clks = dsps_clks,
2026 .clks_num = ARRAY_SIZE(dsps_clks),
2027 .gpios = NULL,
2028 .gpios_num = 0,
2029 .regs = dsps_regs,
2030 .regs_num = ARRAY_SIZE(dsps_regs),
2031 .dsps_pwr_ctl_en = 1,
2032 .signature = DSPS_SIGNATURE,
2033};
2034
2035static struct resource msm_dsps_resources[] = {
2036 {
2037 .start = PPSS_REG_PHYS_BASE,
2038 .end = PPSS_REG_PHYS_BASE + SZ_8K - 1,
2039 .name = "ppss_reg",
2040 .flags = IORESOURCE_MEM,
2041 },
2042};
2043
2044struct platform_device msm_dsps_device = {
2045 .name = "msm_dsps",
2046 .id = 0,
2047 .num_resources = ARRAY_SIZE(msm_dsps_resources),
2048 .resource = msm_dsps_resources,
2049 .dev.platform_data = &msm_dsps_pdata,
2050};
2051
2052#endif /* CONFIG_MSM_DSPS */