| Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | /* linux/include/asm-arm/arch-s3c2410/irqs.h |
| 2 | * |
| 3 | * Copyright (c) 2003-2005 Simtec Electronics |
| 4 | * Ben Dooks <ben@simtec.co.uk> |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License version 2 as |
| 8 | * published by the Free Software Foundation. |
| Ben Dooks | 46c09e1 | 2006-09-09 19:44:52 +0100 | [diff] [blame^] | 9 | */ |
| Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 10 | |
| 11 | |
| 12 | #ifndef __ASM_ARCH_IRQS_H |
| 13 | #define __ASM_ARCH_IRQS_H __FILE__ |
| 14 | |
| 15 | |
| 16 | /* we keep the first set of CPU IRQs out of the range of |
| 17 | * the ISA space, so that the PC104 has them to itself |
| 18 | * and we don't end up having to do horrible things to the |
| 19 | * standard ISA drivers.... |
| 20 | */ |
| 21 | |
| 22 | #define S3C2410_CPUIRQ_OFFSET (16) |
| 23 | |
| 24 | #define S3C2410_IRQ(x) ((x) + S3C2410_CPUIRQ_OFFSET) |
| 25 | |
| 26 | /* main cpu interrupts */ |
| 27 | #define IRQ_EINT0 S3C2410_IRQ(0) /* 16 */ |
| 28 | #define IRQ_EINT1 S3C2410_IRQ(1) |
| 29 | #define IRQ_EINT2 S3C2410_IRQ(2) |
| 30 | #define IRQ_EINT3 S3C2410_IRQ(3) |
| 31 | #define IRQ_EINT4t7 S3C2410_IRQ(4) /* 20 */ |
| 32 | #define IRQ_EINT8t23 S3C2410_IRQ(5) |
| 33 | #define IRQ_RESERVED6 S3C2410_IRQ(6) /* for s3c2410 */ |
| 34 | #define IRQ_CAM S3C2410_IRQ(6) /* for s3c2440 */ |
| 35 | #define IRQ_BATT_FLT S3C2410_IRQ(7) |
| 36 | #define IRQ_TICK S3C2410_IRQ(8) /* 24 */ |
| 37 | #define IRQ_WDT S3C2410_IRQ(9) |
| 38 | #define IRQ_TIMER0 S3C2410_IRQ(10) |
| 39 | #define IRQ_TIMER1 S3C2410_IRQ(11) |
| 40 | #define IRQ_TIMER2 S3C2410_IRQ(12) |
| 41 | #define IRQ_TIMER3 S3C2410_IRQ(13) |
| 42 | #define IRQ_TIMER4 S3C2410_IRQ(14) |
| 43 | #define IRQ_UART2 S3C2410_IRQ(15) |
| 44 | #define IRQ_LCD S3C2410_IRQ(16) /* 32 */ |
| 45 | #define IRQ_DMA0 S3C2410_IRQ(17) |
| 46 | #define IRQ_DMA1 S3C2410_IRQ(18) |
| 47 | #define IRQ_DMA2 S3C2410_IRQ(19) |
| 48 | #define IRQ_DMA3 S3C2410_IRQ(20) |
| 49 | #define IRQ_SDI S3C2410_IRQ(21) |
| 50 | #define IRQ_SPI0 S3C2410_IRQ(22) |
| 51 | #define IRQ_UART1 S3C2410_IRQ(23) |
| 52 | #define IRQ_RESERVED24 S3C2410_IRQ(24) /* 40 */ |
| 53 | #define IRQ_NFCON S3C2410_IRQ(24) /* for s3c2440 */ |
| 54 | #define IRQ_USBD S3C2410_IRQ(25) |
| 55 | #define IRQ_USBH S3C2410_IRQ(26) |
| 56 | #define IRQ_IIC S3C2410_IRQ(27) |
| 57 | #define IRQ_UART0 S3C2410_IRQ(28) /* 44 */ |
| 58 | #define IRQ_SPI1 S3C2410_IRQ(29) |
| 59 | #define IRQ_RTC S3C2410_IRQ(30) |
| 60 | #define IRQ_ADCPARENT S3C2410_IRQ(31) |
| 61 | |
| 62 | /* interrupts generated from the external interrupts sources */ |
| 63 | #define IRQ_EINT4 S3C2410_IRQ(32) /* 48 */ |
| 64 | #define IRQ_EINT5 S3C2410_IRQ(33) |
| 65 | #define IRQ_EINT6 S3C2410_IRQ(34) |
| 66 | #define IRQ_EINT7 S3C2410_IRQ(35) |
| 67 | #define IRQ_EINT8 S3C2410_IRQ(36) |
| 68 | #define IRQ_EINT9 S3C2410_IRQ(37) |
| 69 | #define IRQ_EINT10 S3C2410_IRQ(38) |
| 70 | #define IRQ_EINT11 S3C2410_IRQ(39) |
| 71 | #define IRQ_EINT12 S3C2410_IRQ(40) |
| 72 | #define IRQ_EINT13 S3C2410_IRQ(41) |
| 73 | #define IRQ_EINT14 S3C2410_IRQ(42) |
| 74 | #define IRQ_EINT15 S3C2410_IRQ(43) |
| 75 | #define IRQ_EINT16 S3C2410_IRQ(44) |
| 76 | #define IRQ_EINT17 S3C2410_IRQ(45) |
| 77 | #define IRQ_EINT18 S3C2410_IRQ(46) |
| 78 | #define IRQ_EINT19 S3C2410_IRQ(47) |
| 79 | #define IRQ_EINT20 S3C2410_IRQ(48) /* 64 */ |
| 80 | #define IRQ_EINT21 S3C2410_IRQ(49) |
| 81 | #define IRQ_EINT22 S3C2410_IRQ(50) |
| 82 | #define IRQ_EINT23 S3C2410_IRQ(51) |
| 83 | |
| 84 | |
| 85 | #define IRQ_EINT(x) S3C2410_IRQ((x >= 4) ? (IRQ_EINT4 + (x) - 4) : (S3C2410_IRQ(0) + (x))) |
| 86 | |
| 87 | #define IRQ_LCD_FIFO S3C2410_IRQ(52) |
| 88 | #define IRQ_LCD_FRAME S3C2410_IRQ(53) |
| 89 | |
| 90 | /* IRQs for the interal UARTs, and ADC |
| 91 | * these need to be ordered in number of appearance in the |
| 92 | * SUBSRC mask register |
| 93 | */ |
| 94 | #define IRQ_S3CUART_RX0 S3C2410_IRQ(54) /* 70 */ |
| 95 | #define IRQ_S3CUART_TX0 S3C2410_IRQ(55) /* 71 */ |
| 96 | #define IRQ_S3CUART_ERR0 S3C2410_IRQ(56) |
| 97 | |
| 98 | #define IRQ_S3CUART_RX1 S3C2410_IRQ(57) |
| 99 | #define IRQ_S3CUART_TX1 S3C2410_IRQ(58) |
| 100 | #define IRQ_S3CUART_ERR1 S3C2410_IRQ(59) |
| 101 | |
| 102 | #define IRQ_S3CUART_RX2 S3C2410_IRQ(60) |
| 103 | #define IRQ_S3CUART_TX2 S3C2410_IRQ(61) |
| 104 | #define IRQ_S3CUART_ERR2 S3C2410_IRQ(62) |
| 105 | |
| 106 | #define IRQ_TC S3C2410_IRQ(63) |
| 107 | #define IRQ_ADC S3C2410_IRQ(64) |
| 108 | |
| 109 | /* extra irqs for s3c2440 */ |
| 110 | |
| 111 | #define IRQ_S3C2440_CAM_C S3C2410_IRQ(65) |
| 112 | #define IRQ_S3C2440_CAM_P S3C2410_IRQ(66) |
| 113 | #define IRQ_S3C2440_WDT S3C2410_IRQ(67) |
| 114 | #define IRQ_S3C2440_AC97 S3C2410_IRQ(68) |
| 115 | |
| 116 | #define NR_IRQS (IRQ_S3C2440_AC97+1) |
| 117 | |
| 118 | |
| 119 | #endif /* __ASM_ARCH_IRQ_H */ |