blob: b59ce3cb380718a5030e9ce99e154ad5e9bd54db [file] [log] [blame]
Mike Frysinger3c1fbd52008-11-18 17:48:22 +08001/*
2 * Blackfin cache control code (simpler control-style functions)
3 *
4 * Copyright 2004-2008 Analog Devices Inc.
5 *
6 * Enter bugs at http://blackfin.uclinux.org/
7 *
8 * Licensed under the GPL-2 or later.
9 */
10
11#include <asm/blackfin.h>
12
13/* Invalidate the Entire Data cache by
14 * clearing DMC[1:0] bits
15 */
16void blackfin_invalidate_entire_dcache(void)
17{
18 u32 dmem = bfin_read_DMEM_CONTROL();
Mike Frysinger3c1fbd52008-11-18 17:48:22 +080019 bfin_write_DMEM_CONTROL(dmem & ~0xc);
20 SSYNC();
21 bfin_write_DMEM_CONTROL(dmem);
22 SSYNC();
23}
Sonic Zhang47e9ded2009-06-10 08:57:08 +000024
25/* Invalidate the Entire Instruction cache by
26 * clearing IMC bit
27 */
28void blackfin_invalidate_entire_icache(void)
29{
30 u32 imem = bfin_read_IMEM_CONTROL();
31 bfin_write_IMEM_CONTROL(imem & ~0x4);
32 SSYNC();
33 bfin_write_IMEM_CONTROL(imem);
34 SSYNC();
35}
36