blob: 954f9f907ee4e230a876a222dacaa7e950f81611 [file] [log] [blame]
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001/* Copyright (c) 2009-2011, Code Aurora Forum. All rights reserved.
2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 *
12 */
13
14#include <linux/module.h>
15#include <linux/kernel.h>
16#include <linux/sched.h>
17#include <linux/time.h>
18#include <linux/init.h>
19#include <linux/interrupt.h>
20#include <linux/spinlock.h>
21#include <linux/hrtimer.h>
22#include <linux/clk.h>
23#include <mach/hardware.h>
24#include <linux/io.h>
25#include <linux/debugfs.h>
26#include <linux/fb.h>
27#include <linux/msm_mdp.h>
28#include <linux/file.h>
29#include <linux/android_pmem.h>
30#include <linux/major.h>
31#include <asm/system.h>
32#include <asm/mach-types.h>
33#include <linux/semaphore.h>
34#include <linux/uaccess.h>
35#include <linux/mutex.h>
36#include <linux/msm_kgsl.h>
37#include "mdp.h"
38#include "msm_fb.h"
39#include "mdp4.h"
40
41#define VERSION_KEY_MASK 0xFFFFFF00
42
43struct mdp4_overlay_ctrl {
44 struct mdp4_pipe_desc ov_pipe[OVERLAY_PIPE_MAX];/* 4 */
45 struct mdp4_overlay_pipe plist[MDP4_MAX_PIPE]; /* 4 + 2 */
46 struct mdp4_overlay_pipe *stage[MDP4_MAX_MIXER][MDP4_MAX_STAGE + 2];
47 uint32 panel_3d;
48 uint32 panel_mode;
49 uint32 mixer0_played;
50 uint32 mixer1_played;
51} mdp4_overlay_db = {
52 .ov_pipe = {
53 {
54 .share = 0, /* RGB 1 */
55 },
56 {
57 .share = 0, /* RGB 2 */
58 },
59 {
60 .share = 1, /* VG 1 */
61 },
62 {
63 .share = 1, /* VG 2 */
64 },
65 },
66 .plist = {
67 {
68 .pipe_type = OVERLAY_TYPE_RGB,
69 .pipe_num = OVERLAY_PIPE_RGB1,
70 .pipe_ndx = 1,
71 },
72 {
73 .pipe_type = OVERLAY_TYPE_RGB,
74 .pipe_num = OVERLAY_PIPE_RGB2,
75 .pipe_ndx = 2,
76 },
77 {
78 .pipe_type = OVERLAY_TYPE_RGB, /* shared */
79 .pipe_num = OVERLAY_PIPE_VG1,
80 .pipe_ndx = 3,
81 },
82 {
83 .pipe_type = OVERLAY_TYPE_RGB, /* shared */
84 .pipe_num = OVERLAY_PIPE_VG2,
85 .pipe_ndx = 4,
86 },
87 {
88 .pipe_type = OVERLAY_TYPE_VIDEO, /* shared */
89 .pipe_num = OVERLAY_PIPE_VG1,
90 .pipe_ndx = 5,
91 },
92 {
93 .pipe_type = OVERLAY_TYPE_VIDEO, /* shared */
94 .pipe_num = OVERLAY_PIPE_VG2,
95 .pipe_ndx = 6,
96 },
97 },
98};
99
100static struct mdp4_overlay_ctrl *ctrl = &mdp4_overlay_db;
101static uint32 perf_level;
102static uint32 mdp4_del_res_rel;
103/* static array with index 0 for unset status and 1 for set status */
104static bool overlay_status[MDP4_OVERLAY_TYPE_MAX];
105
106void mdp4_overlay_status_write(enum mdp4_overlay_status type, bool val)
107{
108 overlay_status[type] = val;
109}
110
111bool mdp4_overlay_status_read(enum mdp4_overlay_status type)
112{
113 return overlay_status[type];
114}
115
116int mdp4_overlay_mixer_play(int mixer_num)
117{
118 if (mixer_num == MDP4_MIXER1)
119 return ctrl->mixer1_played;
120 else
121 return ctrl->mixer0_played;
122}
123
124void mdp4_overlay_panel_3d(int mixer_num, uint32 panel_3d)
125{
126 ctrl->panel_3d = panel_3d;
127}
128
129void mdp4_overlay_panel_mode(int mixer_num, uint32 mode)
130{
131 ctrl->panel_mode |= mode;
132}
133
134uint32 mdp4_overlay_panel_list(void)
135{
136 return ctrl->panel_mode;
137}
138
139void mdp4_overlay_dmae_cfg(struct msm_fb_data_type *mfd, int atv)
140{
141 uint32 dmae_cfg_reg;
142
143 if (atv)
144 dmae_cfg_reg = DMA_DEFLKR_EN;
145 else
146 dmae_cfg_reg = 0;
147
148 if (mfd->fb_imgType == MDP_BGR_565)
149 dmae_cfg_reg |= DMA_PACK_PATTERN_BGR;
150 else
151 dmae_cfg_reg |= DMA_PACK_PATTERN_RGB;
152
153
154 if (mfd->panel_info.bpp == 18) {
155 dmae_cfg_reg |= DMA_DSTC0G_6BITS | /* 666 18BPP */
156 DMA_DSTC1B_6BITS | DMA_DSTC2R_6BITS;
157 } else if (mfd->panel_info.bpp == 16) {
158 dmae_cfg_reg |= DMA_DSTC0G_6BITS | /* 565 16BPP */
159 DMA_DSTC1B_5BITS | DMA_DSTC2R_5BITS;
160 } else {
161 dmae_cfg_reg |= DMA_DSTC0G_8BITS | /* 888 16BPP */
162 DMA_DSTC1B_8BITS | DMA_DSTC2R_8BITS;
163 }
164
165 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
166
167 /* dma2 config register */
168 MDP_OUTP(MDP_BASE + 0xb0000, dmae_cfg_reg);
169 if (atv) {
170 MDP_OUTP(MDP_BASE + 0xb0070, 0xeb0010);
171 MDP_OUTP(MDP_BASE + 0xb0074, 0xf00010);
172 MDP_OUTP(MDP_BASE + 0xb0078, 0xf00010);
173 MDP_OUTP(MDP_BASE + 0xb3000, 0x80);
174 MDP_OUTP(MDP_BASE + 0xb3010, 0x1800040);
175 MDP_OUTP(MDP_BASE + 0xb3014, 0x1000080);
176 MDP_OUTP(MDP_BASE + 0xb4004, 0x67686970);
177 } else {
178 MDP_OUTP(MDP_BASE + 0xb0070, 0xff0000);
179 MDP_OUTP(MDP_BASE + 0xb0074, 0xff0000);
180 MDP_OUTP(MDP_BASE + 0xb0078, 0xff0000);
181 }
182
183 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
184}
185
186void unfill_black_screen(void)
187{
188 uint32 temp_src_format;
189
190 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
191 /*
192 * VG2 Constant Color
193 */
194 temp_src_format = inpdw(MDP_BASE + 0x30050);
195 MDP_OUTP(MDP_BASE + 0x30050, temp_src_format&(~BIT(22)));
196 /*
197 * MDP_OVERLAY_REG_FLUSH
198 */
199 MDP_OUTP(MDP_BASE + 0x18000, BIT(3));
200 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
201}
202
203void fill_black_screen(void)
204{
205 /*Black color*/
206 uint32 color = 0x00000000;
207 uint32 temp_src_format;
208 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
209 /*
210 * VG2 Constant Color
211 */
212 MDP_OUTP(MDP_BASE + 0x31008, color);
213 /*
214 * MDP_VG2_SRC_FORMAT
215 */
216 temp_src_format = inpdw(MDP_BASE + 0x30050);
217 MDP_OUTP(MDP_BASE + 0x30050, temp_src_format | BIT(22));
218 /*
219 * MDP_OVERLAY_REG_FLUSH
220 */
221 MDP_OUTP(MDP_BASE + 0x18000, BIT(3));
222 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
223}
224
225void mdp4_overlay_dmae_xy(struct mdp4_overlay_pipe *pipe)
226{
227
228 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
229
230 /* dma_p source */
231 MDP_OUTP(MDP_BASE + 0xb0004,
232 (pipe->src_height << 16 | pipe->src_width));
233 MDP_OUTP(MDP_BASE + 0xb0008, pipe->srcp0_addr);
234 MDP_OUTP(MDP_BASE + 0xb000c, pipe->srcp0_ystride);
235
236 /* dma_p dest */
237 MDP_OUTP(MDP_BASE + 0xb0010, (pipe->dst_y << 16 | pipe->dst_x));
238
239 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
240}
241
242void mdp4_overlay_dmap_cfg(struct msm_fb_data_type *mfd, int lcdc)
243{
244 uint32 dma2_cfg_reg;
245
246 dma2_cfg_reg = DMA_DITHER_EN;
247#ifdef BLT_RGB565
248 /* RGB888 is 0 */
249 dma2_cfg_reg |= DMA_BUF_FORMAT_RGB565; /* blt only */
250#endif
251
252 if (mfd->fb_imgType == MDP_BGR_565)
253 dma2_cfg_reg |= DMA_PACK_PATTERN_BGR;
254 else
255 dma2_cfg_reg |= DMA_PACK_PATTERN_RGB;
256
257
258 if (mfd->panel_info.bpp == 18) {
259 dma2_cfg_reg |= DMA_DSTC0G_6BITS | /* 666 18BPP */
260 DMA_DSTC1B_6BITS | DMA_DSTC2R_6BITS;
261 } else if (mfd->panel_info.bpp == 16) {
262 dma2_cfg_reg |= DMA_DSTC0G_6BITS | /* 565 16BPP */
263 DMA_DSTC1B_5BITS | DMA_DSTC2R_5BITS;
264 } else {
265 dma2_cfg_reg |= DMA_DSTC0G_8BITS | /* 888 16BPP */
266 DMA_DSTC1B_8BITS | DMA_DSTC2R_8BITS;
267 }
268
269 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
270
271#ifndef CONFIG_FB_MSM_LCDC_CHIMEI_WXGA_PANEL
272 if (lcdc)
273 dma2_cfg_reg |= DMA_PACK_ALIGN_MSB;
274#endif
275
276 /* dma2 config register */
277 MDP_OUTP(MDP_BASE + 0x90000, dma2_cfg_reg);
278
279 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
280}
281
282/*
283 * mdp4_overlay_dmap_xy: called form baselayer only
284 */
285void mdp4_overlay_dmap_xy(struct mdp4_overlay_pipe *pipe)
286{
287 uint32 off, bpp;
288
289 if (mdp_is_in_isr == FALSE)
290 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
291
292 /* dma_p source */
293 MDP_OUTP(MDP_BASE + 0x90004,
294 (pipe->src_height << 16 | pipe->src_width));
295 if (pipe->blt_addr) {
296#ifdef BLT_RGB565
297 bpp = 2; /* overlay ouput is RGB565 */
298#else
299 bpp = 3; /* overlay ouput is RGB888 */
300#endif
301 off = 0;
302 if (pipe->dmap_cnt & 0x01)
303 off = pipe->src_height * pipe->src_width * bpp;
304 MDP_OUTP(MDP_BASE + 0x90008, pipe->blt_addr + off);
305 /* RGB888, output of overlay blending */
306 MDP_OUTP(MDP_BASE + 0x9000c, pipe->src_width * bpp);
307 } else {
308 MDP_OUTP(MDP_BASE + 0x90008, pipe->srcp0_addr);
309 MDP_OUTP(MDP_BASE + 0x9000c, pipe->srcp0_ystride);
310 }
311
312 /* dma_p dest */
313 MDP_OUTP(MDP_BASE + 0x90010, (pipe->dst_y << 16 | pipe->dst_x));
314
315 if (mdp_is_in_isr == FALSE)
316 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
317}
318
319#define MDP4_VG_PHASE_STEP_DEFAULT 0x20000000
320#define MDP4_VG_PHASE_STEP_SHIFT 29
321
322static int mdp4_leading_0(uint32 num)
323{
324 uint32 bit = 0x80000000;
325 int i;
326
327 for (i = 0; i < 32; i++) {
328 if (bit & num)
329 return i;
330 bit >>= 1;
331 }
332
333 return i;
334}
335
336static uint32 mdp4_scale_phase_step(int f_num, uint32 src, uint32 dst)
337{
338 uint32 val;
339 int n;
340
341 n = mdp4_leading_0(src);
342 if (n > f_num)
343 n = f_num;
344 val = src << n; /* maximum to reduce lose of resolution */
345 val /= dst;
346 if (n < f_num) {
347 n = f_num - n;
348 val <<= n;
349 }
350
351 return val;
352}
353
354static void mdp4_scale_setup(struct mdp4_overlay_pipe *pipe)
355{
356 int ptype;
357
358 pipe->phasex_step = MDP4_VG_PHASE_STEP_DEFAULT;
359 pipe->phasey_step = MDP4_VG_PHASE_STEP_DEFAULT;
360 ptype = mdp4_overlay_format2type(pipe->src_format);
361
362 if (pipe->dst_h && pipe->src_h != pipe->dst_h) {
363 if (pipe->dst_h > pipe->src_h * 8) /* too much */
364 return;
365 pipe->op_mode |= MDP4_OP_SCALEY_EN;
366
367 if (pipe->pipe_num >= OVERLAY_PIPE_VG1) {
368 if (pipe->dst_h <= (pipe->src_h / 4))
369 pipe->op_mode |= MDP4_OP_SCALEY_MN_PHASE;
370 else
371 pipe->op_mode |= MDP4_OP_SCALEY_FIR;
372 }
373
374 pipe->phasey_step = mdp4_scale_phase_step(29,
375 pipe->src_h, pipe->dst_h);
376 }
377
378 if (pipe->dst_w && pipe->src_w != pipe->dst_w) {
379 if (pipe->dst_w > pipe->src_w * 8) /* too much */
380 return;
381 pipe->op_mode |= MDP4_OP_SCALEX_EN;
382
383 if (pipe->pipe_num >= OVERLAY_PIPE_VG1) {
384 if (pipe->dst_w <= (pipe->src_w / 4))
385 pipe->op_mode |= MDP4_OP_SCALEX_MN_PHASE;
386 else
387 pipe->op_mode |= MDP4_OP_SCALEX_FIR;
388 }
389
390 pipe->phasex_step = mdp4_scale_phase_step(29,
391 pipe->src_w, pipe->dst_w);
392 }
393}
394
395void mdp4_overlay_rgb_setup(struct mdp4_overlay_pipe *pipe)
396{
397 char *rgb_base;
398 uint32 src_size, src_xy, dst_size, dst_xy;
399 uint32 format, pattern;
400
401 rgb_base = MDP_BASE + MDP4_RGB_BASE;
402 rgb_base += (MDP4_RGB_OFF * pipe->pipe_num);
403
404 src_size = ((pipe->src_h << 16) | pipe->src_w);
405 src_xy = ((pipe->src_y << 16) | pipe->src_x);
406 dst_size = ((pipe->dst_h << 16) | pipe->dst_w);
407 dst_xy = ((pipe->dst_y << 16) | pipe->dst_x);
408
409 format = mdp4_overlay_format(pipe);
410 pattern = mdp4_overlay_unpack_pattern(pipe);
411
412#ifdef MDP4_IGC_LUT_ENABLE
413 pipe->op_mode |= MDP4_OP_IGC_LUT_EN;
414#endif
415
416 mdp4_scale_setup(pipe);
417
418 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
419
420 outpdw(rgb_base + 0x0000, src_size); /* MDP_RGB_SRC_SIZE */
421 outpdw(rgb_base + 0x0004, src_xy); /* MDP_RGB_SRC_XY */
422 outpdw(rgb_base + 0x0008, dst_size); /* MDP_RGB_DST_SIZE */
423 outpdw(rgb_base + 0x000c, dst_xy); /* MDP_RGB_DST_XY */
424
425 outpdw(rgb_base + 0x0010, pipe->srcp0_addr);
426 outpdw(rgb_base + 0x0040, pipe->srcp0_ystride);
427
428 outpdw(rgb_base + 0x0050, format);/* MDP_RGB_SRC_FORMAT */
429 outpdw(rgb_base + 0x0054, pattern);/* MDP_RGB_SRC_UNPACK_PATTERN */
430 outpdw(rgb_base + 0x0058, pipe->op_mode);/* MDP_RGB_OP_MODE */
431 outpdw(rgb_base + 0x005c, pipe->phasex_step);
432 outpdw(rgb_base + 0x0060, pipe->phasey_step);
433
434 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
435
436 mdp4_stat.pipe[pipe->pipe_num]++;
437}
438
439void mdp4_overlay_vg_setup(struct mdp4_overlay_pipe *pipe)
440{
441 char *vg_base;
442 uint32 frame_size, src_size, src_xy, dst_size, dst_xy;
443 uint32 format, pattern;
444 int pnum;
445
446 pnum = pipe->pipe_num - OVERLAY_PIPE_VG1; /* start from 0 */
447 vg_base = MDP_BASE + MDP4_VIDEO_BASE;
448 vg_base += (MDP4_VIDEO_OFF * pnum);
449
450 frame_size = ((pipe->src_height << 16) | pipe->src_width);
451 src_size = ((pipe->src_h << 16) | pipe->src_w);
452 src_xy = ((pipe->src_y << 16) | pipe->src_x);
453 dst_size = ((pipe->dst_h << 16) | pipe->dst_w);
454 dst_xy = ((pipe->dst_y << 16) | pipe->dst_x);
455
456 format = mdp4_overlay_format(pipe);
457 pattern = mdp4_overlay_unpack_pattern(pipe);
458
459 /* not RGB use VG pipe, pure VG pipe */
460 if (pipe->pipe_type != OVERLAY_TYPE_RGB)
461#ifdef MDP4_IGC_LUT_ENABLE
462 pipe->op_mode |= (MDP4_OP_CSC_EN | MDP4_OP_SRC_DATA_YCBCR |
463 MDP4_OP_IGC_LUT_EN);
464#else
465 pipe->op_mode |= (MDP4_OP_CSC_EN | MDP4_OP_SRC_DATA_YCBCR);
466#endif
467
468 mdp4_scale_setup(pipe);
469
470 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
471
472 outpdw(vg_base + 0x0000, src_size); /* MDP_RGB_SRC_SIZE */
473 outpdw(vg_base + 0x0004, src_xy); /* MDP_RGB_SRC_XY */
474 outpdw(vg_base + 0x0008, dst_size); /* MDP_RGB_DST_SIZE */
475 outpdw(vg_base + 0x000c, dst_xy); /* MDP_RGB_DST_XY */
476 outpdw(vg_base + 0x0048, frame_size); /* TILE frame size */
477
478 /* luma component plane */
479 outpdw(vg_base + 0x0010, pipe->srcp0_addr);
480
481 /* chroma component plane or planar color 1 */
482 outpdw(vg_base + 0x0014, pipe->srcp1_addr);
483
484 /* planar color 2 */
485 outpdw(vg_base + 0x0018, pipe->srcp2_addr);
486
487 outpdw(vg_base + 0x0040,
488 pipe->srcp1_ystride << 16 | pipe->srcp0_ystride);
489
490 outpdw(vg_base + 0x0044,
491 pipe->srcp3_ystride << 16 | pipe->srcp2_ystride);
492
493 outpdw(vg_base + 0x0050, format); /* MDP_RGB_SRC_FORMAT */
494 outpdw(vg_base + 0x0054, pattern); /* MDP_RGB_SRC_UNPACK_PATTERN */
495 outpdw(vg_base + 0x0058, pipe->op_mode);/* MDP_RGB_OP_MODE */
496 outpdw(vg_base + 0x005c, pipe->phasex_step);
497 outpdw(vg_base + 0x0060, pipe->phasey_step);
498
499 if (pipe->op_mode & MDP4_OP_DITHER_EN) {
500 outpdw(vg_base + 0x0068,
501 pipe->r_bit << 4 | pipe->b_bit << 2 | pipe->g_bit);
502 }
503
504 if (pipe->flags & MDP_SHARPENING) {
505 outpdw(vg_base + 0x8200,
506 mdp4_ss_table_value(pipe->req_data.dpp.sharp_strength,
507 0));
508 outpdw(vg_base + 0x8204,
509 mdp4_ss_table_value(pipe->req_data.dpp.sharp_strength,
510 1));
511 }
512
513 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
514
515 mdp4_stat.pipe[pipe->pipe_num]++;
516}
517
518int mdp4_overlay_format2type(uint32 format)
519{
520 switch (format) {
521 case MDP_RGB_565:
522 case MDP_RGB_888:
523 case MDP_BGR_565:
524 case MDP_XRGB_8888:
525 case MDP_ARGB_8888:
526 case MDP_RGBA_8888:
527 case MDP_BGRA_8888:
528 case MDP_RGBX_8888:
529 return OVERLAY_TYPE_RGB;
530 case MDP_YCRYCB_H2V1:
531 case MDP_Y_CRCB_H2V1:
532 case MDP_Y_CBCR_H2V1:
533 case MDP_Y_CRCB_H2V2:
534 case MDP_Y_CBCR_H2V2:
535 case MDP_Y_CBCR_H2V2_TILE:
536 case MDP_Y_CRCB_H2V2_TILE:
537 case MDP_Y_CR_CB_H2V2:
538 case MDP_Y_CB_CR_H2V2:
539 case MDP_Y_CRCB_H1V1:
540 case MDP_Y_CBCR_H1V1:
541 return OVERLAY_TYPE_VIDEO;
542 default:
543 mdp4_stat.err_format++;
544 return -ERANGE;
545 }
546
547}
548
549#define C3_ALPHA 3 /* alpha */
550#define C2_R_Cr 2 /* R/Cr */
551#define C1_B_Cb 1 /* B/Cb */
552#define C0_G_Y 0 /* G/luma */
553#define YUV_444_MAX_WIDTH 1280 /* Max width for YUV 444*/
554
555int mdp4_overlay_format2pipe(struct mdp4_overlay_pipe *pipe)
556{
557 switch (pipe->src_format) {
558 case MDP_RGB_565:
559 pipe->frame_format = MDP4_FRAME_FORMAT_LINEAR;
560 pipe->fetch_plane = OVERLAY_PLANE_INTERLEAVED;
561 pipe->a_bit = 0;
562 pipe->r_bit = 1; /* R, 5 bits */
563 pipe->b_bit = 1; /* B, 5 bits */
564 pipe->g_bit = 2; /* G, 6 bits */
565 pipe->alpha_enable = 0;
566 pipe->unpack_tight = 1;
567 pipe->unpack_align_msb = 0;
568 pipe->unpack_count = 2;
569 pipe->element2 = C2_R_Cr; /* R */
570 pipe->element1 = C0_G_Y; /* G */
571 pipe->element0 = C1_B_Cb; /* B */
572 pipe->bpp = 2; /* 2 bpp */
573 break;
574 case MDP_RGB_888:
575 pipe->frame_format = MDP4_FRAME_FORMAT_LINEAR;
576 pipe->fetch_plane = OVERLAY_PLANE_INTERLEAVED;
577 pipe->a_bit = 0;
578 pipe->r_bit = 3; /* R, 8 bits */
579 pipe->b_bit = 3; /* B, 8 bits */
580 pipe->g_bit = 3; /* G, 8 bits */
581 pipe->alpha_enable = 0;
582 pipe->unpack_tight = 1;
583 pipe->unpack_align_msb = 0;
584 pipe->unpack_count = 2;
585 pipe->element2 = C2_R_Cr; /* R */
586 pipe->element1 = C0_G_Y; /* G */
587 pipe->element0 = C1_B_Cb; /* B */
588 pipe->bpp = 3; /* 3 bpp */
589 break;
590 case MDP_BGR_565:
591 pipe->frame_format = MDP4_FRAME_FORMAT_LINEAR;
592 pipe->fetch_plane = OVERLAY_PLANE_INTERLEAVED;
593 pipe->a_bit = 0;
594 pipe->r_bit = 1; /* R, 5 bits */
595 pipe->b_bit = 1; /* B, 5 bits */
596 pipe->g_bit = 2; /* G, 6 bits */
597 pipe->alpha_enable = 0;
598 pipe->unpack_tight = 1;
599 pipe->unpack_align_msb = 0;
600 pipe->unpack_count = 2;
601 pipe->element2 = C1_B_Cb; /* B */
602 pipe->element1 = C0_G_Y; /* G */
603 pipe->element0 = C2_R_Cr; /* R */
604 pipe->bpp = 2; /* 2 bpp */
605 break;
606 case MDP_XRGB_8888:
607 pipe->frame_format = MDP4_FRAME_FORMAT_LINEAR;
608 pipe->fetch_plane = OVERLAY_PLANE_INTERLEAVED;
609 pipe->a_bit = 3; /* alpha, 4 bits */
610 pipe->r_bit = 3; /* R, 8 bits */
611 pipe->b_bit = 3; /* B, 8 bits */
612 pipe->g_bit = 3; /* G, 8 bits */
613 pipe->alpha_enable = 0;
614 pipe->unpack_tight = 1;
615 pipe->unpack_align_msb = 0;
616 pipe->unpack_count = 3;
617 pipe->element3 = C3_ALPHA; /* alpha */
618 pipe->element2 = C2_R_Cr; /* R */
619 pipe->element1 = C0_G_Y; /* G */
620 pipe->element0 = C1_B_Cb; /* B */
621 pipe->bpp = 4; /* 4 bpp */
622 break;
623 case MDP_ARGB_8888:
624 pipe->frame_format = MDP4_FRAME_FORMAT_LINEAR;
625 pipe->fetch_plane = OVERLAY_PLANE_INTERLEAVED;
626 pipe->a_bit = 3; /* alpha, 4 bits */
627 pipe->r_bit = 3; /* R, 8 bits */
628 pipe->b_bit = 3; /* B, 8 bits */
629 pipe->g_bit = 3; /* G, 8 bits */
630 pipe->alpha_enable = 1;
631 pipe->unpack_tight = 1;
632 pipe->unpack_align_msb = 0;
633 pipe->unpack_count = 3;
634 pipe->element3 = C3_ALPHA; /* alpha */
635 pipe->element2 = C2_R_Cr; /* R */
636 pipe->element1 = C0_G_Y; /* G */
637 pipe->element0 = C1_B_Cb; /* B */
638 pipe->bpp = 4; /* 4 bpp */
639 break;
640 case MDP_RGBA_8888:
641 pipe->frame_format = MDP4_FRAME_FORMAT_LINEAR;
642 pipe->fetch_plane = OVERLAY_PLANE_INTERLEAVED;
643 pipe->a_bit = 3; /* alpha, 4 bits */
644 pipe->r_bit = 3; /* R, 8 bits */
645 pipe->b_bit = 3; /* B, 8 bits */
646 pipe->g_bit = 3; /* G, 8 bits */
647 pipe->alpha_enable = 1;
648 pipe->unpack_tight = 1;
649 pipe->unpack_align_msb = 0;
650 pipe->unpack_count = 3;
651 pipe->element3 = C3_ALPHA; /* alpha */
652 pipe->element2 = C1_B_Cb; /* B */
653 pipe->element1 = C0_G_Y; /* G */
654 pipe->element0 = C2_R_Cr; /* R */
655 pipe->bpp = 4; /* 4 bpp */
656 break;
657 case MDP_RGBX_8888:
658 pipe->frame_format = MDP4_FRAME_FORMAT_LINEAR;
659 pipe->fetch_plane = OVERLAY_PLANE_INTERLEAVED;
660 pipe->a_bit = 3;
661 pipe->r_bit = 3; /* R, 8 bits */
662 pipe->b_bit = 3; /* B, 8 bits */
663 pipe->g_bit = 3; /* G, 8 bits */
664 pipe->alpha_enable = 0;
665 pipe->unpack_tight = 1;
666 pipe->unpack_align_msb = 0;
667 pipe->unpack_count = 3;
668 pipe->element3 = C3_ALPHA; /* alpha */
669 pipe->element2 = C1_B_Cb; /* B */
670 pipe->element1 = C0_G_Y; /* G */
671 pipe->element0 = C2_R_Cr; /* R */
672 pipe->bpp = 4; /* 4 bpp */
673 break;
674 case MDP_BGRA_8888:
675 pipe->frame_format = MDP4_FRAME_FORMAT_LINEAR;
676 pipe->fetch_plane = OVERLAY_PLANE_INTERLEAVED;
677 pipe->a_bit = 3; /* alpha, 4 bits */
678 pipe->r_bit = 3; /* R, 8 bits */
679 pipe->b_bit = 3; /* B, 8 bits */
680 pipe->g_bit = 3; /* G, 8 bits */
681 pipe->alpha_enable = 1;
682 pipe->unpack_tight = 1;
683 pipe->unpack_align_msb = 0;
684 pipe->unpack_count = 3;
685 pipe->element3 = C3_ALPHA; /* alpha */
686 pipe->element2 = C2_R_Cr; /* R */
687 pipe->element1 = C0_G_Y; /* G */
688 pipe->element0 = C1_B_Cb; /* B */
689 pipe->bpp = 4; /* 4 bpp */
690 break;
691 case MDP_YCRYCB_H2V1:
692 pipe->frame_format = MDP4_FRAME_FORMAT_LINEAR;
693 pipe->fetch_plane = OVERLAY_PLANE_INTERLEAVED;
694 pipe->a_bit = 0; /* alpha, 4 bits */
695 pipe->r_bit = 3; /* R, 8 bits */
696 pipe->b_bit = 3; /* B, 8 bits */
697 pipe->g_bit = 3; /* G, 8 bits */
698 pipe->alpha_enable = 0;
699 pipe->unpack_tight = 1;
700 pipe->unpack_align_msb = 0;
701 pipe->unpack_count = 3;
702 pipe->element3 = C0_G_Y; /* G */
703 pipe->element2 = C2_R_Cr; /* R */
704 pipe->element1 = C0_G_Y; /* G */
705 pipe->element0 = C1_B_Cb; /* B */
706 pipe->bpp = 2; /* 2 bpp */
707 pipe->chroma_sample = MDP4_CHROMA_H2V1;
708 break;
709 case MDP_Y_CRCB_H2V1:
710 case MDP_Y_CBCR_H2V1:
711 case MDP_Y_CRCB_H2V2:
712 case MDP_Y_CBCR_H2V2:
713 case MDP_Y_CRCB_H1V1:
714 case MDP_Y_CBCR_H1V1:
715 pipe->frame_format = MDP4_FRAME_FORMAT_LINEAR;
716 pipe->fetch_plane = OVERLAY_PLANE_PSEUDO_PLANAR;
717 pipe->a_bit = 0;
718 pipe->r_bit = 3; /* R, 8 bits */
719 pipe->b_bit = 3; /* B, 8 bits */
720 pipe->g_bit = 3; /* G, 8 bits */
721 pipe->alpha_enable = 0;
722 pipe->unpack_tight = 1;
723 pipe->unpack_align_msb = 0;
724 pipe->unpack_count = 1; /* 2 */
725 pipe->element3 = C0_G_Y; /* not used */
726 pipe->element2 = C0_G_Y; /* not used */
727 if (pipe->src_format == MDP_Y_CRCB_H2V1) {
728 pipe->element1 = C2_R_Cr; /* R */
729 pipe->element0 = C1_B_Cb; /* B */
730 pipe->chroma_sample = MDP4_CHROMA_H2V1;
731 } else if (pipe->src_format == MDP_Y_CRCB_H1V1) {
732 pipe->element1 = C2_R_Cr; /* R */
733 pipe->element0 = C1_B_Cb; /* B */
734 if (pipe->src_width > YUV_444_MAX_WIDTH)
735 pipe->chroma_sample = MDP4_CHROMA_H1V2;
736 else
737 pipe->chroma_sample = MDP4_CHROMA_RGB;
738 } else if (pipe->src_format == MDP_Y_CBCR_H2V1) {
739 pipe->element1 = C1_B_Cb; /* B */
740 pipe->element0 = C2_R_Cr; /* R */
741 pipe->chroma_sample = MDP4_CHROMA_H2V1;
742 } else if (pipe->src_format == MDP_Y_CBCR_H1V1) {
743 pipe->element1 = C1_B_Cb; /* B */
744 pipe->element0 = C2_R_Cr; /* R */
745 if (pipe->src_width > YUV_444_MAX_WIDTH)
746 pipe->chroma_sample = MDP4_CHROMA_H1V2;
747 else
748 pipe->chroma_sample = MDP4_CHROMA_RGB;
749 } else if (pipe->src_format == MDP_Y_CRCB_H2V2) {
750 pipe->element1 = C2_R_Cr; /* R */
751 pipe->element0 = C1_B_Cb; /* B */
752 pipe->chroma_sample = MDP4_CHROMA_420;
753 } else if (pipe->src_format == MDP_Y_CBCR_H2V2) {
754 pipe->element1 = C1_B_Cb; /* B */
755 pipe->element0 = C2_R_Cr; /* R */
756 pipe->chroma_sample = MDP4_CHROMA_420;
757 }
758 pipe->bpp = 2; /* 2 bpp */
759 break;
760 case MDP_Y_CBCR_H2V2_TILE:
761 case MDP_Y_CRCB_H2V2_TILE:
762 pipe->frame_format = MDP4_FRAME_FORMAT_VIDEO_SUPERTILE;
763 pipe->fetch_plane = OVERLAY_PLANE_PSEUDO_PLANAR;
764 pipe->a_bit = 0;
765 pipe->r_bit = 3; /* R, 8 bits */
766 pipe->b_bit = 3; /* B, 8 bits */
767 pipe->g_bit = 3; /* G, 8 bits */
768 pipe->alpha_enable = 0;
769 pipe->unpack_tight = 1;
770 pipe->unpack_align_msb = 0;
771 pipe->unpack_count = 1; /* 2 */
772 pipe->element3 = C0_G_Y; /* not used */
773 pipe->element2 = C0_G_Y; /* not used */
774 if (pipe->src_format == MDP_Y_CRCB_H2V2_TILE) {
775 pipe->element1 = C2_R_Cr; /* R */
776 pipe->element0 = C1_B_Cb; /* B */
777 pipe->chroma_sample = MDP4_CHROMA_420;
778 } else if (pipe->src_format == MDP_Y_CBCR_H2V2_TILE) {
779 pipe->element1 = C1_B_Cb; /* B */
780 pipe->element0 = C2_R_Cr; /* R */
781 pipe->chroma_sample = MDP4_CHROMA_420;
782 }
783 pipe->bpp = 2; /* 2 bpp */
784 break;
785 case MDP_Y_CR_CB_H2V2:
786 case MDP_Y_CB_CR_H2V2:
787 pipe->frame_format = MDP4_FRAME_FORMAT_LINEAR;
788 pipe->fetch_plane = OVERLAY_PLANE_PLANAR;
789 pipe->a_bit = 0;
790 pipe->r_bit = 3; /* R, 8 bits */
791 pipe->b_bit = 3; /* B, 8 bits */
792 pipe->g_bit = 3; /* G, 8 bits */
793 pipe->alpha_enable = 0;
794 pipe->unpack_tight = 1;
795 pipe->unpack_align_msb = 0;
796 pipe->unpack_count = 1; /* 2 */
797 pipe->element3 = C0_G_Y; /* not used */
798 pipe->element2 = C0_G_Y; /* not used */
799 if (pipe->src_format == MDP_Y_CR_CB_H2V2) {
800 pipe->element1 = C2_R_Cr; /* R */
801 pipe->element0 = C1_B_Cb; /* B */
802 pipe->chroma_sample = MDP4_CHROMA_420;
803 } else if (pipe->src_format == MDP_Y_CB_CR_H2V2) {
804 pipe->element1 = C1_B_Cb; /* B */
805 pipe->element0 = C2_R_Cr; /* R */
806 pipe->chroma_sample = MDP4_CHROMA_420;
807 }
808 pipe->bpp = 2; /* 2 bpp */
809 break;
810 default:
811 /* not likely */
812 mdp4_stat.err_format++;
813 return -ERANGE;
814 }
815
816 return 0;
817}
818
819/*
820 * color_key_convert: output with 12 bits color key
821 */
822static uint32 color_key_convert(int start, int num, uint32 color)
823{
824 uint32 data;
825
826 data = (color >> start) & ((1 << num) - 1);
827
828 /* convert to 8 bits */
829 if (num == 5)
830 data = ((data << 3) | (data >> 2));
831 else if (num == 6)
832 data = ((data << 2) | (data >> 4));
833
834 /* convert 8 bits to 12 bits */
835 data = (data << 4) | (data >> 4);
836
837 return data;
838}
839
840void transp_color_key(int format, uint32 transp,
841 uint32 *c0, uint32 *c1, uint32 *c2)
842{
843 int b_start, g_start, r_start;
844 int b_num, g_num, r_num;
845
846 switch (format) {
847 case MDP_RGB_565:
848 b_start = 0;
849 g_start = 5;
850 r_start = 11;
851 r_num = 5;
852 g_num = 6;
853 b_num = 5;
854 break;
855 case MDP_RGB_888:
856 case MDP_XRGB_8888:
857 case MDP_ARGB_8888:
858 case MDP_BGRA_8888:
859 b_start = 0;
860 g_start = 8;
861 r_start = 16;
862 r_num = 8;
863 g_num = 8;
864 b_num = 8;
865 break;
866 case MDP_RGBA_8888:
867 case MDP_RGBX_8888:
868 b_start = 16;
869 g_start = 8;
870 r_start = 0;
871 r_num = 8;
872 g_num = 8;
873 b_num = 8;
874 break;
875 case MDP_BGR_565:
876 b_start = 11;
877 g_start = 5;
878 r_start = 0;
879 r_num = 5;
880 g_num = 6;
881 b_num = 5;
882 break;
883 case MDP_Y_CB_CR_H2V2:
884 case MDP_Y_CBCR_H2V2:
885 case MDP_Y_CBCR_H2V1:
886 b_start = 8;
887 g_start = 16;
888 r_start = 0;
889 r_num = 8;
890 g_num = 8;
891 b_num = 8;
892 break;
893 case MDP_Y_CR_CB_H2V2:
894 case MDP_Y_CRCB_H2V2:
895 case MDP_Y_CRCB_H2V1:
896 case MDP_Y_CRCB_H1V1:
897 case MDP_Y_CBCR_H1V1:
898 b_start = 0;
899 g_start = 16;
900 r_start = 8;
901 r_num = 8;
902 g_num = 8;
903 b_num = 8;
904 break;
905 default:
906 b_start = 0;
907 g_start = 8;
908 r_start = 16;
909 r_num = 8;
910 g_num = 8;
911 b_num = 8;
912 break;
913 }
914
915 *c0 = color_key_convert(g_start, g_num, transp);
916 *c1 = color_key_convert(b_start, b_num, transp);
917 *c2 = color_key_convert(r_start, r_num, transp);
918}
919
920uint32 mdp4_overlay_format(struct mdp4_overlay_pipe *pipe)
921{
922 uint32 format;
923
924 format = 0;
925
926 if (pipe->solid_fill)
927 format |= MDP4_FORMAT_SOLID_FILL;
928
929 if (pipe->unpack_align_msb)
930 format |= MDP4_FORMAT_UNPACK_ALIGN_MSB;
931
932 if (pipe->unpack_tight)
933 format |= MDP4_FORMAT_UNPACK_TIGHT;
934
935 if (pipe->alpha_enable)
936 format |= MDP4_FORMAT_ALPHA_ENABLE;
937
938 if (pipe->flags & MDP_SOURCE_ROTATED_90)
939 format |= MDP4_FORMAT_90_ROTATED;
940 format |= (pipe->unpack_count << 13);
941 format |= ((pipe->bpp - 1) << 9);
942 format |= (pipe->a_bit << 6);
943 format |= (pipe->r_bit << 4);
944 format |= (pipe->b_bit << 2);
945 format |= pipe->g_bit;
946
947 format |= (pipe->frame_format << 29);
948
949 if (pipe->fetch_plane == OVERLAY_PLANE_PSEUDO_PLANAR ||
950 pipe->fetch_plane == OVERLAY_PLANE_PLANAR) {
951 /* video/graphic */
952 format |= (pipe->fetch_plane << 19);
953 format |= (pipe->chroma_site << 28);
954 format |= (pipe->chroma_sample << 26);
955 }
956
957 return format;
958}
959
960uint32 mdp4_overlay_unpack_pattern(struct mdp4_overlay_pipe *pipe)
961{
962 return (pipe->element3 << 24) | (pipe->element2 << 16) |
963 (pipe->element1 << 8) | pipe->element0;
964}
965
966/*
967 * mdp4_overlayproc_cfg: only be called from base layer
968 */
969void mdp4_overlayproc_cfg(struct mdp4_overlay_pipe *pipe)
970{
971 uint32 data, intf;
972 char *overlay_base;
973
974 intf = 0;
975 if (pipe->mixer_num == MDP4_MIXER1) {
976 overlay_base = MDP_BASE + MDP4_OVERLAYPROC1_BASE;/* 0x18000 */
977 intf = inpdw(MDP_BASE + 0x0038); /* MDP_DISP_INTF_SEL */
978 intf >>= 4;
979 intf &= 0x03;
980 } else
981 overlay_base = MDP_BASE + MDP4_OVERLAYPROC0_BASE;/* 0x10000 */
982
983 if (mdp_is_in_isr == FALSE)
984 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
985
986 /*
987 * BLT only siupport at primary display
988 */
989 if (pipe->mixer_num == MDP4_MIXER0 && pipe->blt_addr) {
990 int off, bpp;
991#ifdef BLT_RGB565
992 bpp = 2; /* overlay ouput is RGB565 */
993#else
994 bpp = 3; /* overlay ouput is RGB888 */
995#endif
996 data = pipe->src_height;
997 data <<= 16;
998 data |= pipe->src_width;
999 outpdw(overlay_base + 0x0008, data); /* ROI, height + width */
1000 if (ctrl->panel_mode & MDP4_PANEL_LCDC ||
1001 ctrl->panel_mode & MDP4_PANEL_DSI_VIDEO) {
1002 outpdw(overlay_base + 0x000c, pipe->blt_addr);
1003 outpdw(overlay_base + 0x0010, pipe->src_width * bpp);
1004 off = pipe->src_height * pipe->src_width * bpp;
1005 outpdw(overlay_base + 0x001c, pipe->blt_addr + off);
1006 /* LCDC - FRAME BUFFER + vsync rate */
1007 outpdw(overlay_base + 0x0004, 0x02);
1008 } else { /* MDDI */
1009 off = 0;
1010 if (pipe->ov_cnt & 0x01)
1011 off = pipe->src_height * pipe->src_width * bpp;
1012
1013 outpdw(overlay_base + 0x000c, pipe->blt_addr + off);
1014 /* overlay ouput is RGB888 */
1015 outpdw(overlay_base + 0x0010, pipe->src_width * bpp);
1016 outpdw(overlay_base + 0x001c, pipe->blt_addr + off);
1017 /* MDDI - BLT + on demand */
1018 outpdw(overlay_base + 0x0004, 0x08);
1019 }
1020#ifdef BLT_RGB565
1021 outpdw(overlay_base + 0x0014, 0x1); /* RGB565 */
1022#else
1023 outpdw(overlay_base + 0x0014, 0x0); /* RGB888 */
1024#endif
1025 } else {
1026 data = pipe->src_height;
1027 data <<= 16;
1028 data |= pipe->src_width;
1029 outpdw(overlay_base + 0x0008, data); /* ROI, height + width */
1030 outpdw(overlay_base + 0x000c, pipe->srcp0_addr);
1031 outpdw(overlay_base + 0x0010, pipe->srcp0_ystride);
1032 outpdw(overlay_base + 0x0004, 0x01); /* directout */
1033 }
1034
1035 if (pipe->mixer_num == MDP4_MIXER1) {
1036 if (intf == TV_INTF) {
1037 outpdw(overlay_base + 0x0014, 0x02); /* yuv422 */
1038 /* overlay1 CSC config */
1039 outpdw(overlay_base + 0x0200, 0x05); /* rgb->yuv */
1040 }
1041 }
1042
1043#ifdef MDP4_IGC_LUT_ENABLE
1044 outpdw(overlay_base + 0x0014, 0x4); /* GC_LUT_EN, 888 */
1045#endif
1046
1047 if (mdp_is_in_isr == FALSE)
1048 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
1049}
1050
1051int mdp4_overlay_pipe_staged(int mixer)
1052{
1053 uint32 data, mask, i;
1054 int p1, p2;
1055
1056 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
1057 data = inpdw(MDP_BASE + 0x10100);
1058 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
1059 p1 = 0;
1060 p2 = 0;
1061 for (i = 0; i < 8; i++) {
1062 mask = data & 0x0f;
1063 if (mask) {
1064 if (mask <= 4)
1065 p1++;
1066 else
1067 p2++;
1068 }
1069 data >>= 4;
1070 }
1071
1072 if (mixer)
1073 return p2;
1074 else
1075 return p1;
1076}
1077
1078void mdp4_mixer_stage_up(struct mdp4_overlay_pipe *pipe)
1079{
1080 uint32 data, mask, snum, stage, mixer, pnum;
1081
1082 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
1083
1084 stage = pipe->mixer_stage;
1085 mixer = pipe->mixer_num;
1086 pnum = pipe->pipe_num;
1087
1088 /* MDP_LAYERMIXER_IN_CFG, shard by both mixer 0 and 1 */
1089 data = inpdw(MDP_BASE + 0x10100);
1090
1091 if (mixer == MDP4_MIXER1)
1092 stage += 8;
1093
1094 if (pipe->pipe_num >= OVERLAY_PIPE_VG1) {/* VG1 and VG2 */
1095 pnum -= OVERLAY_PIPE_VG1; /* start from 0 */
1096 snum = 0;
1097 snum += (4 * pnum);
1098 } else {
1099 snum = 8;
1100 snum += (4 * pnum); /* RGB1 and RGB2 */
1101 }
1102
1103 mask = 0x0f;
1104 mask <<= snum;
1105 stage <<= snum;
1106 data &= ~mask; /* clear old bits */
1107
1108 data |= stage;
1109
1110 outpdw(MDP_BASE + 0x10100, data); /* MDP_LAYERMIXER_IN_CFG */
1111
1112 data = inpdw(MDP_BASE + 0x10100);
1113
1114 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
1115
1116 ctrl->stage[pipe->mixer_num][pipe->mixer_stage] = pipe; /* keep it */
1117}
1118
1119void mdp4_mixer_stage_down(struct mdp4_overlay_pipe *pipe)
1120{
1121 uint32 data, mask, snum, stage, mixer, pnum;
1122
1123 stage = pipe->mixer_stage;
1124 mixer = pipe->mixer_num;
1125 pnum = pipe->pipe_num;
1126
1127 if (pipe != ctrl->stage[mixer][stage]) /* not runing */
1128 return;
1129
1130 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
1131
1132 /* MDP_LAYERMIXER_IN_CFG, shard by both mixer 0 and 1 */
1133 data = inpdw(MDP_BASE + 0x10100);
1134
1135 if (mixer == MDP4_MIXER1)
1136 stage += 8;
1137
1138 if (pipe->pipe_num >= OVERLAY_PIPE_VG1) {/* VG1 and VG2 */
1139 pnum -= OVERLAY_PIPE_VG1; /* start from 0 */
1140 snum = 0;
1141 snum += (4 * pnum);
1142 } else {
1143 snum = 8;
1144 snum += (4 * pnum); /* RGB1 and RGB2 */
1145 }
1146
1147 mask = 0x0f;
1148 mask <<= snum;
1149 data &= ~mask; /* clear old bits */
1150
1151 outpdw(MDP_BASE + 0x10100, data); /* MDP_LAYERMIXER_IN_CFG */
1152
1153 data = inpdw(MDP_BASE + 0x10100);
1154
1155 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
1156
1157 ctrl->stage[pipe->mixer_num][pipe->mixer_stage] = NULL; /* clear it */
1158}
1159
1160void mdp4_mixer_blend_setup(struct mdp4_overlay_pipe *pipe)
1161{
1162 struct mdp4_overlay_pipe *bg_pipe;
1163 unsigned char *overlay_base, *rgb_base;
1164 uint32 c0, c1, c2, blend_op, constant_color = 0, rgb_src_format;
1165 int off;
1166
1167 if (pipe->mixer_num) /* mixer number, /dev/fb0, /dev/fb1 */
1168 overlay_base = MDP_BASE + MDP4_OVERLAYPROC1_BASE;/* 0x18000 */
1169 else
1170 overlay_base = MDP_BASE + MDP4_OVERLAYPROC0_BASE;/* 0x10000 */
1171
1172 /* stage 0 to stage 2 */
1173 off = 0x20 * (pipe->mixer_stage - MDP4_MIXER_STAGE0);
1174
1175 bg_pipe = mdp4_overlay_stage_pipe(pipe->mixer_num,
1176 MDP4_MIXER_STAGE_BASE);
1177 if (bg_pipe == NULL) {
1178 pr_err("%s: Error: no bg_pipe\n", __func__);
1179 return;
1180 }
1181
1182 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
1183
1184 blend_op = 0;
1185
1186 if (pipe->is_fg) {
1187 blend_op |= (MDP4_BLEND_FG_ALPHA_FG_CONST |
1188 MDP4_BLEND_BG_ALPHA_BG_CONST);
1189 outpdw(overlay_base + off + 0x108, pipe->alpha);
1190 outpdw(overlay_base + off + 0x10c, 0xff - pipe->alpha);
1191 if (pipe->alpha == 0xff) {
1192 rgb_base = MDP_BASE + MDP4_RGB_BASE;
1193 rgb_base += MDP4_RGB_OFF * bg_pipe->pipe_num;
1194 rgb_src_format = inpdw(rgb_base + 0x50);
1195 rgb_src_format |= MDP4_FORMAT_SOLID_FILL;
1196 outpdw(rgb_base + 0x50, rgb_src_format);
1197 outpdw(rgb_base + 0x1008, constant_color);
1198 }
1199 } else {
1200 if (bg_pipe->alpha_enable && pipe->alpha_enable) {
1201 /* both pipe have alpha */
1202 blend_op |= (MDP4_BLEND_FG_ALPHA_BG_PIXEL |
1203 MDP4_BLEND_FG_INV_ALPHA |
1204 MDP4_BLEND_BG_ALPHA_BG_PIXEL);
1205 } else if (bg_pipe->alpha_enable && pipe->alpha_enable == 0) {
1206 /* no alpha on both pipe */
1207 blend_op = (MDP4_BLEND_BG_ALPHA_BG_PIXEL |
1208 MDP4_BLEND_FG_ALPHA_BG_PIXEL |
1209 MDP4_BLEND_FG_INV_ALPHA);
1210 }
1211 }
1212
1213
1214 if (pipe->transp != MDP_TRANSP_NOP) {
1215 if (pipe->is_fg) {
1216 transp_color_key(pipe->src_format, pipe->transp,
1217 &c0, &c1, &c2);
1218 /* Fg blocked */
1219 blend_op |= MDP4_BLEND_FG_TRANSP_EN;
1220 /* lower limit */
1221 outpdw(overlay_base + off + 0x110,
1222 (c1 << 16 | c0));/* low */
1223 outpdw(overlay_base + off + 0x114, c2);/* low */
1224 /* upper limit */
1225 outpdw(overlay_base + off + 0x118,
1226 (c1 << 16 | c0));
1227 outpdw(overlay_base + off + 0x11c, c2);
1228 } else {
1229 transp_color_key(bg_pipe->src_format,
1230 pipe->transp, &c0, &c1, &c2);
1231 /* bg blocked */
1232 blend_op |= MDP4_BLEND_BG_TRANSP_EN;
1233 /* lower limit */
1234 outpdw(overlay_base + 0x180,
1235 (c1 << 16 | c0));/* low */
1236 outpdw(overlay_base + 0x184, c2);/* low */
1237 /* upper limit */
1238 outpdw(overlay_base + 0x188,
1239 (c1 << 16 | c0));/* high */
1240 outpdw(overlay_base + 0x18c, c2);/* high */
1241 }
1242 }
1243
1244 outpdw(overlay_base + off + 0x104, blend_op);
1245
1246 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
1247}
1248
1249void mdp4_overlay_reg_flush(struct mdp4_overlay_pipe *pipe, int all)
1250{
1251 struct mdp4_overlay_pipe *bg_pipe;
1252 uint32 bits = 0;
1253
1254 if (pipe->mixer_num == MDP4_MIXER1)
1255 bits |= 0x02;
1256 else
1257 bits |= 0x01;
1258
1259 if (all) {
1260 if (pipe->pipe_num <= OVERLAY_PIPE_RGB2) {
1261 if (pipe->pipe_num == OVERLAY_PIPE_RGB2)
1262 bits |= 0x20;
1263 else
1264 bits |= 0x10;
1265 } else {
1266 if (pipe->is_fg && pipe->alpha == 0xFF) {
1267 bg_pipe = mdp4_overlay_stage_pipe(
1268 pipe->mixer_num,
1269 MDP4_MIXER_STAGE_BASE);
1270 if (bg_pipe->pipe_num <= OVERLAY_PIPE_RGB2) {
1271 if (bg_pipe->pipe_num ==
1272 OVERLAY_PIPE_RGB2)
1273 bits |= 0x20;
1274 else
1275 bits |= 0x10;
1276 }
1277 }
1278 if (pipe->pipe_num == OVERLAY_PIPE_VG2)
1279 bits |= 0x08;
1280 else
1281 bits |= 0x04;
1282 }
1283 }
1284
1285 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
1286 outpdw(MDP_BASE + 0x18000, bits); /* MDP_OVERLAY_REG_FLUSH */
1287 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
1288}
1289
1290struct mdp4_overlay_pipe *mdp4_overlay_stage_pipe(int mixer, int stage)
1291{
1292 return ctrl->stage[mixer][stage];
1293}
1294
1295struct mdp4_overlay_pipe *mdp4_overlay_ndx2pipe(int ndx)
1296{
1297 struct mdp4_overlay_pipe *pipe;
1298
1299 if (ndx <= 0 || ndx > MDP4_MAX_PIPE)
1300 return NULL;
1301
1302 pipe = &ctrl->plist[ndx - 1]; /* ndx start from 1 */
1303
1304 if (pipe->pipe_used == 0)
1305 return NULL;
1306
1307 return pipe;
1308}
1309
1310struct mdp4_overlay_pipe *mdp4_overlay_pipe_alloc(
1311 int ptype, int mixer, int req_share)
1312{
1313 int i, j, ndx, found;
1314 struct mdp4_overlay_pipe *pipe, *opipe;
1315 struct mdp4_pipe_desc *pd;
1316
1317 found = 0;
1318 pipe = &ctrl->plist[0];
1319
1320 for (i = 0; i < MDP4_MAX_PIPE; i++) {
1321 if (pipe->pipe_type == ptype && pipe->pipe_used == 0) {
1322 pd = &ctrl->ov_pipe[pipe->pipe_num];
1323 if (pd->share) { /* pipe can be shared */
1324 if (pd->ref_cnt == 0) {
1325 /* not yet been used */
1326 found++;
1327 break;
1328 }
1329 /* pipe occupied already */
1330 if (req_share && pd->ref_cnt < MDP4_MAX_SHARE) {
1331 for (j = 0; j < MDP4_MAX_SHARE; j++) {
1332 ndx = pd->ndx_list[j];
1333 if (ndx != 0)
1334 break;
1335 }
1336 /* ndx satrt from 1 */
1337 opipe = &ctrl->plist[ndx - 1];
1338 /*
1339 * occupied pipe willing to share and
1340 * same mixer
1341 */
1342 if (opipe->pipe_share &&
1343 opipe->mixer_num == mixer) {
1344 found++;
1345 break;
1346 }
1347 }
1348 } else { /* not a shared pipe */
1349 if (req_share == 0 && pd->ref_cnt == 0) {
1350 found++;
1351 break;
1352 }
1353 }
1354 }
1355 pipe++;
1356 }
1357
1358 if (found) {
1359 init_completion(&pipe->comp);
1360 init_completion(&pipe->dmas_comp);
1361 pr_info("%s: pipe=%x ndx=%d num=%d share=%d cnt=%d\n",
1362 __func__, (int)pipe, pipe->pipe_ndx, pipe->pipe_num,
1363 pd->share, pd->ref_cnt);
1364 return pipe;
1365 }
1366
1367 pr_debug("%s: ptype=%d mixer=%d req_share=%d FAILED\n",
1368 __func__, ptype, mixer, req_share);
1369
1370 return NULL;
1371}
1372
1373
1374void mdp4_overlay_pipe_free(struct mdp4_overlay_pipe *pipe)
1375{
1376 int i;
1377 uint32 ptype, num, ndx;
1378 struct mdp4_pipe_desc *pd;
1379
1380 pr_debug("%s: pipe=%x ndx=%d\n", __func__,
1381 (int)pipe, pipe->pipe_ndx);
1382 pd = &ctrl->ov_pipe[pipe->pipe_num];
1383 if (pd->ref_cnt) {
1384 pd->ref_cnt--;
1385 for (i = 0; i < MDP4_MAX_SHARE; i++) {
1386 if (pd->ndx_list[i] == pipe->pipe_ndx) {
1387 pd->ndx_list[i] = 0;
1388 break;
1389 }
1390 }
1391 }
1392
1393 pd->player = NULL;
1394
1395 ptype = pipe->pipe_type;
1396 num = pipe->pipe_num;
1397 ndx = pipe->pipe_ndx;
1398
1399 memset(pipe, 0, sizeof(*pipe));
1400
1401 pipe->pipe_type = ptype;
1402 pipe->pipe_num = num;
1403 pipe->pipe_ndx = ndx;
1404}
1405
1406int mdp4_overlay_req_check(uint32 id, uint32 z_order, uint32 mixer)
1407{
1408 struct mdp4_overlay_pipe *pipe;
1409
1410 pipe = ctrl->stage[mixer][z_order];
1411
1412 if (pipe == NULL)
1413 return 0;
1414
1415 if (pipe->pipe_ndx == id) /* same req, recycle */
1416 return 0;
1417
1418 if (id == MSMFB_NEW_REQUEST) { /* new request */
1419 if (pipe->pipe_num >= OVERLAY_PIPE_VG1) /* share pipe */
1420 return 0;
1421 }
1422
1423 return -EPERM;
1424}
1425
1426static int mdp4_overlay_validate_downscale(struct mdp_overlay *req,
1427 struct msm_fb_data_type *mfd, uint32 perf_level, uint32 pclk_rate)
1428{
1429 __u32 panel_clk_khz, mdp_clk_khz;
1430 __u32 num_hsync_pix_clks, mdp_clks_per_hsync, src_wh;
1431 __u32 hsync_period_ps, mdp_period_ps, total_hsync_period_ps;
1432 unsigned long fill_rate_y_dir, fill_rate_x_dir;
1433 unsigned long fillratex100, mdp_pixels_produced;
1434 unsigned long mdp_clk_hz;
1435
1436 pr_debug("%s: LCDC Mode Downscale validation with MDP Core"
1437 " Clk rate\n", __func__);
1438 pr_debug("src_w %u, src_h %u, dst_w %u, dst_h %u\n",
1439 req->src_rect.w, req->src_rect.h, req->dst_rect.w,
1440 req->dst_rect.h);
1441
1442
1443 panel_clk_khz = pclk_rate/1000;
1444 mdp_clk_hz = mdp_perf_level2clk_rate(perf_level);
1445
1446 if (!mdp_clk_hz) {
1447 pr_debug("mdp_perf_level2clk_rate returned 0,"
1448 "Downscale Validation incomplete\n");
1449 return 0;
1450 }
1451
1452 mdp_clk_khz = mdp_clk_hz/1000;
1453
1454 num_hsync_pix_clks = mfd->panel_info.lcdc.h_back_porch +
1455 mfd->panel_info.lcdc.h_front_porch +
1456 mfd->panel_info.lcdc.h_pulse_width +
1457 mfd->panel_info.xres;
1458
1459 hsync_period_ps = 1000000000/panel_clk_khz;
1460 mdp_period_ps = 1000000000/mdp_clk_khz;
1461
1462 total_hsync_period_ps = num_hsync_pix_clks * hsync_period_ps;
1463 mdp_clks_per_hsync = total_hsync_period_ps/mdp_period_ps;
1464
1465 pr_debug("hsync_period_ps %u, mdp_period_ps %u,"
1466 "total_hsync_period_ps %u\n", hsync_period_ps,
1467 mdp_period_ps, total_hsync_period_ps);
1468
1469 src_wh = req->src_rect.w * req->src_rect.h;
1470 if (src_wh % req->dst_rect.h)
1471 fill_rate_y_dir = (src_wh / req->dst_rect.h) + 1;
1472 else
1473 fill_rate_y_dir = (src_wh / req->dst_rect.h);
1474
1475 fill_rate_x_dir = (mfd->panel_info.xres - req->dst_rect.w)
1476 + req->src_rect.w;
1477
1478 if (fill_rate_y_dir >= fill_rate_x_dir)
1479 fillratex100 = 100 * fill_rate_y_dir / mfd->panel_info.xres;
1480 else
1481 fillratex100 = 100 * fill_rate_x_dir / mfd->panel_info.xres;
1482
1483 pr_debug("mdp_clks_per_hsync %u, fill_rate_y_dir %lu,"
1484 "fill_rate_x_dir %lu\n", mdp_clks_per_hsync,
1485 fill_rate_y_dir, fill_rate_x_dir);
1486
1487 mdp_pixels_produced = 100 * mdp_clks_per_hsync/fillratex100;
1488 pr_debug("fillratex100 %lu, mdp_pixels_produced %lu\n",
1489 fillratex100, mdp_pixels_produced);
1490 if (mdp_pixels_produced <= mfd->panel_info.xres) {
1491 pr_err("%s(): LCDC underflow detected during downscale\n",
1492 __func__);
1493 return -ERANGE;
1494 }
1495
1496 return 0;
1497}
1498
1499static int mdp4_overlay_req2pipe(struct mdp_overlay *req, int mixer,
1500 struct mdp4_overlay_pipe **ppipe,
1501 struct msm_fb_data_type *mfd)
1502{
1503 struct mdp4_overlay_pipe *pipe;
1504 struct mdp4_pipe_desc *pd;
1505 int ret, ptype, req_share;
1506 int j;
1507
1508 if (mfd == NULL) {
1509 pr_err("%s: mfd == NULL, -ENODEV\n", __func__);
1510 return -ENODEV;
1511 }
1512
1513 if (mixer >= MDP4_MAX_MIXER) {
1514 pr_err("%s: mixer out of range!\n", __func__);
1515 mdp4_stat.err_mixer++;
1516 return -ERANGE;
1517 }
1518
1519 if (req->z_order < 0 || req->z_order > 2) {
1520 pr_err("%s: z_order=%d out of range!\n", __func__,
1521 req->z_order);
1522 mdp4_stat.err_zorder++;
1523 return -ERANGE;
1524 }
1525
1526 if (req->src_rect.h == 0 || req->src_rect.w == 0) {
1527 pr_err("%s: src img of zero size!\n", __func__);
1528 mdp4_stat.err_size++;
1529 return -EINVAL;
1530 }
1531
1532
1533 if (req->dst_rect.h > (req->src_rect.h * 8)) { /* too much */
1534 mdp4_stat.err_scale++;
1535 pr_err("%s: scale up, too much (h)!\n", __func__);
1536 return -ERANGE;
1537 }
1538
1539 if (req->src_rect.h > (req->dst_rect.h * 8)) { /* too little */
1540 mdp4_stat.err_scale++;
1541 pr_err("%s: scale down, too little (h)!\n", __func__);
1542 return -ERANGE;
1543 }
1544
1545 if (req->dst_rect.w > (req->src_rect.w * 8)) { /* too much */
1546 mdp4_stat.err_scale++;
1547 pr_err("%s: scale up, too much (w)!\n", __func__);
1548 return -ERANGE;
1549 }
1550
1551 if (req->src_rect.w > (req->dst_rect.w * 8)) { /* too little */
1552 mdp4_stat.err_scale++;
1553 pr_err("%s: scale down, too little (w)!\n", __func__);
1554 return -ERANGE;
1555 }
1556
1557 if (mdp_hw_revision == MDP4_REVISION_V1) {
1558 /* non integer down saceling ratio smaller than 1/4
1559 * is not supportted
1560 */
1561 if (req->src_rect.h > (req->dst_rect.h * 4)) {
1562 if (req->src_rect.h % req->dst_rect.h) {
1563 mdp4_stat.err_scale++;
1564 pr_err("%s: need integer (h)!\n", __func__);
1565 return -ERANGE;
1566 }
1567 }
1568
1569 if (req->src_rect.w > (req->dst_rect.w * 4)) {
1570 if (req->src_rect.w % req->dst_rect.w) {
1571 mdp4_stat.err_scale++;
1572 pr_err("%s: need integer (w)!\n", __func__);
1573 return -ERANGE;
1574 }
1575 }
1576 }
1577
1578 if (((req->src_rect.x + req->src_rect.w) > req->src.width) ||
1579 ((req->src_rect.y + req->src_rect.h) > req->src.height)) {
1580 mdp4_stat.err_size++;
1581 pr_err("%s invalid src rectangle\n", __func__);
1582 return -ERANGE;
1583 }
1584
1585 if (ctrl->panel_3d != MDP4_3D_SIDE_BY_SIDE) {
1586 int xres;
1587 int yres;
1588
1589 xres = mfd->panel_info.xres;
1590 yres = mfd->panel_info.yres;
1591
1592 if (((req->dst_rect.x + req->dst_rect.w) > xres) ||
1593 ((req->dst_rect.y + req->dst_rect.h) > yres)) {
1594 mdp4_stat.err_size++;
1595 pr_err("%s invalid dst rectangle\n", __func__);
1596 return -ERANGE;
1597 }
1598 }
1599
1600 ptype = mdp4_overlay_format2type(req->src.format);
1601 if (ptype < 0) {
1602 pr_err("%s: mdp4_overlay_format2type!\n", __func__);
1603 return ptype;
1604 }
1605
1606 req_share = (req->flags & MDP_OV_PIPE_SHARE);
1607
1608 if (req->id == MSMFB_NEW_REQUEST) /* new request */
1609 pipe = mdp4_overlay_pipe_alloc(ptype, mixer, req_share);
1610 else
1611 pipe = mdp4_overlay_ndx2pipe(req->id);
1612
1613 if (pipe == NULL) {
1614 pr_err("%s: pipe == NULL!\n", __func__);
1615 return -ENOMEM;
1616 }
1617
1618 /* no down scale at rgb pipe */
1619 if (pipe->pipe_num <= OVERLAY_PIPE_RGB2) {
1620 if ((req->src_rect.h > req->dst_rect.h) ||
1621 (req->src_rect.w > req->dst_rect.w)) {
1622 pr_err("%s: h>h || w>w!\n", __func__);
1623 return -ERANGE;
1624 }
1625 }
1626
1627 pipe->src_format = req->src.format;
1628 ret = mdp4_overlay_format2pipe(pipe);
1629 if (ret < 0) {
1630 pr_err("%s: mdp4_overlay_format2pipe!\n", __func__);
1631 return ret;
1632 }
1633
1634 /*
1635 * base layer == 1, reserved for frame buffer
1636 * zorder 0 == stage 0 == 2
1637 * zorder 1 == stage 1 == 3
1638 * zorder 2 == stage 2 == 4
1639 */
1640 if (req->id == MSMFB_NEW_REQUEST) { /* new request */
1641 pd = &ctrl->ov_pipe[pipe->pipe_num];
1642 for (j = 0; j < MDP4_MAX_SHARE; j++) {
1643 if (pd->ndx_list[j] == 0) {
1644 pd->ndx_list[j] = pipe->pipe_ndx;
1645 break;
1646 }
1647 }
1648 pipe->pipe_share = req_share;
1649 pd->ref_cnt++;
1650 pipe->pipe_used++;
1651 pipe->mixer_num = mixer;
1652 pipe->mixer_stage = req->z_order + MDP4_MIXER_STAGE0;
1653 pr_debug("%s: zorder=%d pipe ndx=%d num=%d\n", __func__,
1654 req->z_order, pipe->pipe_ndx, pipe->pipe_num);
1655
1656 }
1657
1658 pipe->src_width = req->src.width & 0x07ff; /* source img width */
1659 pipe->src_height = req->src.height & 0x07ff; /* source img height */
1660 pipe->src_h = req->src_rect.h & 0x07ff;
1661 pipe->src_w = req->src_rect.w & 0x07ff;
1662 pipe->src_y = req->src_rect.y & 0x07ff;
1663 pipe->src_x = req->src_rect.x & 0x07ff;
1664 pipe->dst_h = req->dst_rect.h & 0x07ff;
1665 pipe->dst_w = req->dst_rect.w & 0x07ff;
1666 pipe->dst_y = req->dst_rect.y & 0x07ff;
1667 pipe->dst_x = req->dst_rect.x & 0x07ff;
1668
1669 pipe->op_mode = 0;
1670
1671 if (req->flags & MDP_FLIP_LR)
1672 pipe->op_mode |= MDP4_OP_FLIP_LR;
1673
1674 if (req->flags & MDP_FLIP_UD)
1675 pipe->op_mode |= MDP4_OP_FLIP_UD;
1676
1677 if (req->flags & MDP_DITHER)
1678 pipe->op_mode |= MDP4_OP_DITHER_EN;
1679
1680 if (req->flags & MDP_DEINTERLACE)
1681 pipe->op_mode |= MDP4_OP_DEINT_EN;
1682
1683 if (req->flags & MDP_DEINTERLACE_ODD)
1684 pipe->op_mode |= MDP4_OP_DEINT_ODD_REF;
1685
1686 pipe->is_fg = req->is_fg;/* control alpha and color key */
1687
1688 pipe->alpha = req->alpha & 0x0ff;
1689
1690 pipe->transp = req->transp_mask;
1691
1692 *ppipe = pipe;
1693
1694 return 0;
1695}
1696
1697static int get_img(struct msmfb_data *img, struct fb_info *info,
1698 unsigned long *start, unsigned long *len, struct file **pp_file)
1699{
1700 int put_needed, ret = 0, fb_num;
1701 struct file *file;
1702#ifdef CONFIG_ANDROID_PMEM
1703 unsigned long vstart;
1704#endif
1705
1706 if (img->flags & MDP_BLIT_SRC_GEM) {
1707 *pp_file = NULL;
1708 return kgsl_gem_obj_addr(img->memory_id, (int) img->priv,
1709 start, len);
1710 }
1711
1712#ifdef CONFIG_ANDROID_PMEM
1713 if (!get_pmem_file(img->memory_id, start, &vstart, len, pp_file))
1714 return 0;
1715#endif
1716 file = fget_light(img->memory_id, &put_needed);
1717 if (file == NULL)
1718 return -1;
1719
1720 if (MAJOR(file->f_dentry->d_inode->i_rdev) == FB_MAJOR) {
1721 fb_num = MINOR(file->f_dentry->d_inode->i_rdev);
1722 if (get_fb_phys_info(start, len, fb_num))
1723 ret = -1;
1724 else
1725 *pp_file = file;
1726 } else
1727 ret = -1;
1728 if (ret)
1729 fput_light(file, put_needed);
1730 return ret;
1731}
1732
kuogee hsieh4aea2742011-07-06 11:05:05 -07001733#ifdef CONFIG_FB_MSM_MIPI_DSI
1734int mdp4_overlay_3d_sbys(struct fb_info *info, struct msmfb_overlay_3d *req)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001735{
1736 struct msm_fb_data_type *mfd = (struct msm_fb_data_type *)info->par;
1737 int ret = -EPERM;
1738
1739 if (mutex_lock_interruptible(&mfd->dma->ov_mutex))
1740 return -EINTR;
1741
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001742 if (ctrl->panel_mode & MDP4_PANEL_DSI_CMD) {
kuogee hsieh4aea2742011-07-06 11:05:05 -07001743 mdp4_dsi_cmd_3d_sbys(mfd, req);
1744 ret = 0;
1745 } else if (ctrl->panel_mode & MDP4_PANEL_DSI_VIDEO) {
1746 mdp4_dsi_video_3d_sbys(mfd, req);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001747 ret = 0;
1748 }
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001749 mutex_unlock(&mfd->dma->ov_mutex);
1750
1751 return ret;
1752}
kuogee hsieh4aea2742011-07-06 11:05:05 -07001753#else
1754int mdp4_overlay_3d_sbys(struct fb_info *info, struct msmfb_overlay_3d *req)
1755{
1756 /* do nothing */
1757 return -EPERM;
1758}
1759#endif
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001760
1761#ifdef CONFIG_FB_MSM_OVERLAY_WRITEBACK
1762int mdp4_overlay_blt(struct fb_info *info, struct msmfb_overlay_blt *req)
1763{
1764 struct msm_fb_data_type *mfd = (struct msm_fb_data_type *)info->par;
1765
1766 if (mfd == NULL)
1767 return -ENODEV;
1768
1769 if (mutex_lock_interruptible(&mfd->dma->ov_mutex))
1770 return -EINTR;
1771
1772 if (ctrl->panel_mode & MDP4_PANEL_DSI_CMD)
1773 mdp4_dsi_overlay_blt(mfd, req);
1774 else if (ctrl->panel_mode & MDP4_PANEL_DSI_VIDEO)
1775 mdp4_dsi_video_overlay_blt(mfd, req);
1776 else if (ctrl->panel_mode & MDP4_PANEL_LCDC)
1777 mdp4_lcdc_overlay_blt(mfd, req);
1778
1779 mutex_unlock(&mfd->dma->ov_mutex);
1780
1781 return 0;
1782}
1783
1784int mdp4_overlay_blt_offset(struct fb_info *info, struct msmfb_overlay_blt *req)
1785{
1786 int ret = 0;
1787
1788 struct msm_fb_data_type *mfd = (struct msm_fb_data_type *)info->par;
1789
1790 if (mutex_lock_interruptible(&mfd->dma->ov_mutex))
1791 return -EINTR;
1792
1793 if (ctrl->panel_mode & MDP4_PANEL_DSI_CMD)
1794 ret = mdp4_dsi_overlay_blt_offset(mfd, req);
1795 else if (ctrl->panel_mode & MDP4_PANEL_DSI_VIDEO)
1796 ret = mdp4_dsi_video_overlay_blt_offset(mfd, req);
1797 else if (ctrl->panel_mode & MDP4_PANEL_LCDC)
1798 ret = mdp4_lcdc_overlay_blt_offset(mfd, req);
1799
1800 mutex_unlock(&mfd->dma->ov_mutex);
1801
1802 return ret;
1803}
1804#endif
1805
1806int mdp4_overlay_get(struct fb_info *info, struct mdp_overlay *req)
1807{
1808 struct mdp4_overlay_pipe *pipe;
1809
1810 pipe = mdp4_overlay_ndx2pipe(req->id);
1811 if (pipe == NULL)
1812 return -ENODEV;
1813
1814 *req = pipe->req_data;
1815
1816 return 0;
1817}
1818
1819#define OVERLAY_VGA_SIZE 0x04B000
1820#define OVERLAY_720P_TILE_SIZE 0x0E6000
1821#define OVERLAY_WSVGA_SIZE 0x98000 /* 1024x608, align 600 to 32bit */
1822#define OVERLAY_PERF_LEVEL1 1
1823#define OVERLAY_PERF_LEVEL2 2
1824#define OVERLAY_PERF_LEVEL3 3
1825#define OVERLAY_PERF_LEVEL4 4
1826
1827#ifdef CONFIG_MSM_BUS_SCALING
1828#define OVERLAY_BUS_SCALE_TABLE_BASE 6
1829#endif
1830
1831static int mdp4_overlay_is_rgb_type(int format)
1832{
1833 switch (format) {
1834 case MDP_RGB_565:
1835 case MDP_RGB_888:
1836 case MDP_BGR_565:
1837 case MDP_XRGB_8888:
1838 case MDP_ARGB_8888:
1839 case MDP_RGBA_8888:
1840 case MDP_BGRA_8888:
1841 case MDP_RGBX_8888:
1842 return 1;
1843 default:
1844 return 0;
1845 }
1846}
1847
1848static uint32 mdp4_overlay_get_perf_level(struct mdp_overlay *req)
1849{
1850 int is_fg;
1851
1852 if (req->is_fg && ((req->alpha & 0x0ff) == 0xff))
1853 is_fg = 1;
1854
1855 if (req->flags & MDP_DEINTERLACE)
1856 return OVERLAY_PERF_LEVEL1;
1857
1858 if (mdp4_overlay_is_rgb_type(req->src.format) && is_fg &&
1859 ((req->src.width * req->src.height) <= OVERLAY_WSVGA_SIZE))
1860 return OVERLAY_PERF_LEVEL4;
1861 else if (mdp4_overlay_is_rgb_type(req->src.format))
1862 return OVERLAY_PERF_LEVEL1;
1863
1864 if (ctrl->ov_pipe[OVERLAY_PIPE_VG1].ref_cnt &&
1865 ctrl->ov_pipe[OVERLAY_PIPE_VG2].ref_cnt)
1866 return OVERLAY_PERF_LEVEL1;
1867
1868 if (req->src.width*req->src.height <= OVERLAY_VGA_SIZE)
1869 return OVERLAY_PERF_LEVEL3;
1870 else if (req->src.width*req->src.height <= OVERLAY_720P_TILE_SIZE)
1871 return OVERLAY_PERF_LEVEL2;
1872 else
1873 return OVERLAY_PERF_LEVEL1;
1874}
1875
1876int mdp4_overlay_set(struct fb_info *info, struct mdp_overlay *req)
1877{
1878 struct msm_fb_data_type *mfd = (struct msm_fb_data_type *)info->par;
1879 int ret, mixer;
1880 struct mdp4_overlay_pipe *pipe;
1881
1882 if (mfd == NULL) {
1883 pr_err("%s: mfd == NULL, -ENODEV\n", __func__);
1884 return -ENODEV;
1885 }
1886
1887 if (!mfd->panel_power_on) /* suspended */
1888 return -EPERM;
1889
1890 if (req->src.format == MDP_FB_FORMAT)
1891 req->src.format = mfd->fb_imgType;
1892
1893 if (mutex_lock_interruptible(&mfd->dma->ov_mutex)) {
1894 pr_err("%s: mutex_lock_interruptible, -EINTR\n", __func__);
1895 return -EINTR;
1896 }
1897
1898 perf_level = mdp4_overlay_get_perf_level(req);
1899
1900 if ((mfd->panel_info.type == LCDC_PANEL) &&
1901 (req->src_rect.h >
1902 req->dst_rect.h || req->src_rect.w > req->dst_rect.w)) {
1903 if (mdp4_overlay_validate_downscale(req, mfd,
1904 perf_level, mfd->panel_info.clk_rate)) {
1905 mutex_unlock(&mfd->dma->ov_mutex);
1906 return -ERANGE;
1907 }
1908 }
1909 if ((mfd->panel_info.type == MIPI_VIDEO_PANEL) &&
1910 (req->src_rect.h >
1911 req->dst_rect.h || req->src_rect.w > req->dst_rect.w)) {
1912 if (mdp4_overlay_validate_downscale(req, mfd,
1913 perf_level, (&mfd->panel_info.mipi)->dsi_pclk_rate)) {
1914 mutex_unlock(&mfd->dma->ov_mutex);
1915 return -ERANGE;
1916 }
1917 }
1918 mixer = mfd->panel_info.pdest; /* DISPLAY_1 or DISPLAY_2 */
1919
1920 ret = mdp4_overlay_req2pipe(req, mixer, &pipe, mfd);
1921 if (ret < 0) {
1922 mutex_unlock(&mfd->dma->ov_mutex);
1923 pr_err("%s: mdp4_overlay_req2pipe, ret=%d\n", __func__, ret);
1924 return ret;
1925 }
1926
1927#ifdef CONFIG_FB_MSM_MIPI_DSI
1928 /*
1929 * writeback (blt) mode to provide work around for
1930 * dsi cmd mode interface hardware bug.
1931 */
1932 if (ctrl->panel_mode & MDP4_PANEL_DSI_CMD) {
1933 if (mixer == MDP4_MIXER0 && req->dst_rect.x != 0) {
1934 mdp4_dsi_blt_dmap_busy_wait(mfd);
1935 mdp4_dsi_overlay_blt_start(mfd);
1936 }
1937 }
1938#endif
1939
1940 /* return id back to user */
1941 req->id = pipe->pipe_ndx; /* pipe_ndx start from 1 */
1942 pipe->req_data = *req; /* keep original req */
1943
1944 pipe->flags = req->flags;
1945
1946 if (pipe->flags & MDP_SHARPENING) {
1947 bool test = ((pipe->req_data.dpp.sharp_strength > 0) &&
1948 ((req->src_rect.w > req->dst_rect.w) &&
1949 (req->src_rect.h > req->dst_rect.h)));
1950 if (test) {
1951 pr_warn("%s: No sharpening while downscaling.\n",
1952 __func__);
1953 pipe->flags &= ~MDP_SHARPENING;
1954 }
1955 }
1956
1957 mdp4_stat.overlay_set[pipe->mixer_num]++;
1958
1959 if (ctrl->panel_mode & MDP4_PANEL_MDDI) {
1960 if (mdp_hw_revision == MDP4_REVISION_V2_1 &&
1961 pipe->mixer_num == MDP4_MIXER0)
1962 mdp4_overlay_status_write(MDP4_OVERLAY_TYPE_SET, true);
1963 }
1964
1965 mdp4_del_res_rel = 0;
1966 mutex_unlock(&mfd->dma->ov_mutex);
1967 mdp_set_core_clk(perf_level);
1968
1969#ifdef CONFIG_MSM_BUS_SCALING
1970 if (pipe->mixer_num == MDP4_MIXER0) {
1971 mdp_bus_scale_update_request(OVERLAY_BUS_SCALE_TABLE_BASE
1972 - perf_level);
1973 }
1974#endif
1975
1976 return 0;
1977}
1978
1979void mdp4_overlay_resource_release(void)
1980{
1981 if (mdp4_del_res_rel) {
1982 mdp_set_core_clk(OVERLAY_PERF_LEVEL4);
1983 mdp4_del_res_rel = 0;
1984 }
1985}
1986
1987int mdp4_overlay_unset(struct fb_info *info, int ndx)
1988{
1989 struct msm_fb_data_type *mfd = (struct msm_fb_data_type *)info->par;
1990 struct mdp4_overlay_pipe *pipe;
1991 uint32 flags;
1992
1993 if (mfd == NULL)
1994 return -ENODEV;
1995
1996 if (mutex_lock_interruptible(&mfd->dma->ov_mutex))
1997 return -EINTR;
1998
1999 pipe = mdp4_overlay_ndx2pipe(ndx);
2000
2001 if (pipe == NULL) {
2002 mutex_unlock(&mfd->dma->ov_mutex);
2003 return -ENODEV;
2004 }
2005
2006 if (pipe->mixer_num == MDP4_MIXER1)
2007 ctrl->mixer1_played = 0;
2008 else {
2009 /* mixer 0 */
2010 ctrl->mixer0_played = 0;
2011#ifdef CONFIG_FB_MSM_MIPI_DSI
2012 if (ctrl->panel_mode & MDP4_PANEL_DSI_CMD) {
2013 if (mfd->panel_power_on) {
2014 mdp4_dsi_blt_dmap_busy_wait(mfd);
2015 }
2016 }
2017#else
2018 if (ctrl->panel_mode & MDP4_PANEL_MDDI) {
2019 if (mfd->panel_power_on)
2020 mdp4_mddi_dma_busy_wait(mfd);
2021 }
2022#endif
2023 }
2024
2025 mdp4_mixer_stage_down(pipe);
2026
2027 if (pipe->mixer_num == MDP4_MIXER0) {
2028#ifdef CONFIG_FB_MSM_MIPI_DSI
2029 if (ctrl->panel_mode & MDP4_PANEL_DSI_CMD) {
2030 if (mfd->panel_power_on)
2031 if (mdp4_dsi_overlay_blt_stop(mfd) == 0)
2032 mdp4_dsi_cmd_overlay_restore();
2033 } else if (ctrl->panel_mode & MDP4_PANEL_DSI_VIDEO) {
2034 flags = pipe->flags;
2035 pipe->flags &= ~MDP_OV_PLAY_NOWAIT;
kuogee hsiehebca0c72011-07-14 13:30:33 -07002036 mdp4_overlay_reg_flush(pipe, 1);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002037 mdp4_overlay_dsi_video_vsync_push(mfd, pipe);
2038 pipe->flags = flags;
2039 }
2040#else
2041 if (ctrl->panel_mode & MDP4_PANEL_MDDI) {
2042 if (mdp_hw_revision == MDP4_REVISION_V2_1)
2043 mdp4_overlay_status_write(
2044 MDP4_OVERLAY_TYPE_UNSET, true);
2045 if (mfd->panel_power_on)
2046 mdp4_mddi_overlay_restore();
2047 }
2048#endif
2049 else if (ctrl->panel_mode & MDP4_PANEL_LCDC) {
2050 flags = pipe->flags;
2051 pipe->flags &= ~MDP_OV_PLAY_NOWAIT;
kuogee hsiehebca0c72011-07-14 13:30:33 -07002052 mdp4_overlay_reg_flush(pipe, 1);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002053 mdp4_overlay_lcdc_vsync_push(mfd, pipe);
2054 pipe->flags = flags;
2055 }
2056 }
2057#ifdef CONFIG_FB_MSM_DTV
2058 else { /* mixer1, DTV, ATV */
2059 flags = pipe->flags;
2060 pipe->flags &= ~MDP_OV_PLAY_NOWAIT;
2061 mdp4_overlay_dtv_vsync_push(mfd, pipe);
2062 pipe->flags = flags;
2063 }
2064#endif
2065
2066 mdp4_stat.overlay_unset[pipe->mixer_num]++;
2067
2068 mdp4_overlay_pipe_free(pipe);
2069
2070 if (!(ctrl->ov_pipe[OVERLAY_PIPE_VG1].ref_cnt +
2071 ctrl->ov_pipe[OVERLAY_PIPE_VG2].ref_cnt))
2072 mdp4_del_res_rel = 1;
2073
2074 mutex_unlock(&mfd->dma->ov_mutex);
2075
2076#ifdef CONFIG_MSM_BUS_SCALING
2077 if (pipe->mixer_num == MDP4_MIXER0)
2078 if (mfd->panel_power_on)
2079 mdp_bus_scale_update_request(2);
2080#endif
2081 return 0;
2082}
2083
2084struct tile_desc {
2085 uint32 width; /* tile's width */
2086 uint32 height; /* tile's height */
2087 uint32 row_tile_w; /* tiles per row's width */
2088 uint32 row_tile_h; /* tiles per row's height */
2089};
2090
2091void tile_samsung(struct tile_desc *tp)
2092{
2093 /*
2094 * each row of samsung tile consists of two tiles in height
2095 * and two tiles in width which means width should align to
2096 * 64 x 2 bytes and height should align to 32 x 2 bytes.
2097 * video decoder generate two tiles in width and one tile
2098 * in height which ends up height align to 32 X 1 bytes.
2099 */
2100 tp->width = 64; /* 64 bytes */
2101 tp->row_tile_w = 2; /* 2 tiles per row's width */
2102 tp->height = 32; /* 32 bytes */
2103 tp->row_tile_h = 1; /* 1 tiles per row's height */
2104}
2105
2106uint32 tile_mem_size(struct mdp4_overlay_pipe *pipe, struct tile_desc *tp)
2107{
2108 uint32 tile_w, tile_h;
2109 uint32 row_num_w, row_num_h;
2110
2111
2112 tile_w = tp->width * tp->row_tile_w;
2113 tile_h = tp->height * tp->row_tile_h;
2114
2115 row_num_w = (pipe->src_width + tile_w - 1) / tile_w;
2116 row_num_h = (pipe->src_height + tile_h - 1) / tile_h;
2117 return ((row_num_w * row_num_h * tile_w * tile_h) + 8191) & ~8191;
2118}
2119
2120int mdp4_overlay_play(struct fb_info *info, struct msmfb_overlay_data *req,
2121 struct file **pp_src_file, struct file **pp_src_plane1_file,
2122 struct file **pp_src_plane2_file)
2123{
2124 struct msm_fb_data_type *mfd = (struct msm_fb_data_type *)info->par;
2125 struct msmfb_data *img;
2126 struct mdp4_overlay_pipe *pipe;
2127 struct mdp4_pipe_desc *pd;
2128 ulong start, addr;
2129 ulong len = 0;
2130 struct file *p_src_file = 0;
2131 struct file *p_src_plane1_file = 0, *p_src_plane2_file = 0;
2132 uint32_t overlay_version = 0;
2133
2134 if (mfd == NULL)
2135 return -ENODEV;
2136
2137 if (!mfd->panel_power_on) /* suspended */
2138 return -EPERM;
2139
2140 pipe = mdp4_overlay_ndx2pipe(req->id);
2141 if (pipe == NULL) {
2142 pr_err("%s: req_id=%d Error\n", __func__, req->id);
2143 return -ENODEV;
2144 }
2145
2146 if (mutex_lock_interruptible(&mfd->dma->ov_mutex))
2147 return -EINTR;
2148
2149 pd = &ctrl->ov_pipe[pipe->pipe_num];
2150 if (pd->player && pipe != pd->player) {
2151 if (pipe->pipe_type == OVERLAY_TYPE_RGB) {
2152 mutex_unlock(&mfd->dma->ov_mutex);
2153 return 0; /* ignore it, kicked out already */
2154 }
2155 }
2156
2157 pd->player = pipe; /* keep */
2158
2159 img = &req->data;
2160 get_img(img, info, &start, &len, &p_src_file);
2161 if (len == 0) {
2162 mutex_unlock(&mfd->dma->ov_mutex);
2163 pr_err("%s: pmem Error\n", __func__);
2164 return -1;
2165 }
2166 *pp_src_file = p_src_file;
2167
2168 addr = start + img->offset;
2169 pipe->srcp0_addr = addr;
2170 pipe->srcp0_ystride = pipe->src_width * pipe->bpp;
2171
2172 if ((req->version_key & VERSION_KEY_MASK) == 0xF9E8D700)
2173 overlay_version = (req->version_key & ~VERSION_KEY_MASK);
2174
2175 if (pipe->fetch_plane == OVERLAY_PLANE_PSEUDO_PLANAR) {
2176 if (overlay_version > 0) {
2177 img = &req->plane1_data;
2178 get_img(img, info, &start, &len, &p_src_plane1_file);
2179 if (len == 0) {
2180 mutex_unlock(&mfd->dma->ov_mutex);
2181 pr_err("%s: Error to get plane1\n", __func__);
2182 return -EINVAL;
2183 }
2184 pipe->srcp1_addr = start + img->offset;
2185 *pp_src_plane1_file = p_src_plane1_file;
2186 } else if (pipe->frame_format ==
2187 MDP4_FRAME_FORMAT_VIDEO_SUPERTILE) {
2188 struct tile_desc tile;
2189
2190 tile_samsung(&tile);
2191 pipe->srcp1_addr = addr + tile_mem_size(pipe, &tile);
2192 } else {
2193 pipe->srcp1_addr = addr + (pipe->src_width *
2194 pipe->src_height);
2195 }
2196 pipe->srcp0_ystride = pipe->src_width;
2197 if ((pipe->src_format == MDP_Y_CRCB_H1V1) ||
2198 (pipe->src_format == MDP_Y_CBCR_H1V1)) {
2199 if (pipe->src_width > YUV_444_MAX_WIDTH)
2200 pipe->srcp1_ystride = pipe->src_width << 2;
2201 else
2202 pipe->srcp1_ystride = pipe->src_width << 1;
2203 } else
2204 pipe->srcp1_ystride = pipe->src_width;
2205
2206 } else if (pipe->fetch_plane == OVERLAY_PLANE_PLANAR) {
2207 if (overlay_version > 0) {
2208 img = &req->plane1_data;
2209 get_img(img, info, &start, &len, &p_src_plane1_file);
2210 if (len == 0) {
2211 mutex_unlock(&mfd->dma->ov_mutex);
2212 pr_err("%s: Error to get plane1\n", __func__);
2213 return -EINVAL;
2214 }
2215 pipe->srcp1_addr = start + img->offset;
2216 *pp_src_plane1_file = p_src_plane1_file;
2217
2218 img = &req->plane2_data;
2219 get_img(img, info, &start, &len, &p_src_plane2_file);
2220 if (len == 0) {
2221 mutex_unlock(&mfd->dma->ov_mutex);
2222 pr_err("%s: Error to get plane2\n", __func__);
2223 return -EINVAL;
2224 }
2225 pipe->srcp2_addr = start + img->offset;
2226 *pp_src_plane2_file = p_src_plane2_file;
2227 } else {
2228 addr += (pipe->src_width * pipe->src_height);
2229 pipe->srcp1_addr = addr;
2230 addr += ((pipe->src_width / 2) *
2231 (pipe->src_height / 2));
2232 pipe->srcp2_addr = addr;
2233 }
2234 pipe->srcp0_ystride = pipe->src_width;
2235 pipe->srcp1_ystride = pipe->src_width / 2;
2236 pipe->srcp2_ystride = pipe->src_width / 2;
2237 }
2238
2239 if (pipe->pipe_num >= OVERLAY_PIPE_VG1)
2240 mdp4_overlay_vg_setup(pipe); /* video/graphic pipe */
2241 else {
2242 if (pipe->flags & MDP_SHARPENING) {
2243 pr_warn(
2244 "%s: Sharpening/Smoothing not supported on RGB pipe\n",
2245 __func__);
2246 pipe->flags &= ~MDP_SHARPENING;
2247 }
2248 mdp4_overlay_rgb_setup(pipe); /* rgb pipe */
2249 }
2250
2251 mdp4_mixer_blend_setup(pipe);
2252 mdp4_mixer_stage_up(pipe);
2253
2254 if (pipe->mixer_num == MDP4_MIXER1) {
2255 ctrl->mixer1_played++;
2256 /* enternal interface */
2257 if (ctrl->panel_mode & MDP4_PANEL_DTV)
2258#ifdef CONFIG_FB_MSM_DTV
2259 mdp4_overlay_dtv_ov_done_push(mfd, pipe);
2260#else
2261 mdp4_overlay_reg_flush(pipe, 1);
2262#endif
2263 else if (ctrl->panel_mode & MDP4_PANEL_ATV)
2264 mdp4_overlay_reg_flush(pipe, 1);
2265 } else {
2266 /* primary interface */
2267 ctrl->mixer0_played++;
kuogee hsieh3de11f32011-07-08 14:09:11 -07002268 if (ctrl->panel_mode & MDP4_PANEL_LCDC) {
2269 mdp4_overlay_reg_flush(pipe, 1);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002270 mdp4_overlay_lcdc_vsync_push(mfd, pipe);
kuogee hsieh3de11f32011-07-08 14:09:11 -07002271 }
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002272#ifdef CONFIG_FB_MSM_MIPI_DSI
kuogee hsieh3de11f32011-07-08 14:09:11 -07002273 else if (ctrl->panel_mode & MDP4_PANEL_DSI_VIDEO) {
2274 mdp4_overlay_reg_flush(pipe, 1);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002275 mdp4_overlay_dsi_video_vsync_push(mfd, pipe);
kuogee hsieh3de11f32011-07-08 14:09:11 -07002276 }
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002277#endif
2278 else {
2279 /* mddi & mipi dsi cmd mode */
2280 if (pipe->flags & MDP_OV_PLAY_NOWAIT) {
2281 mdp4_stat.overlay_play[pipe->mixer_num]++;
2282 mutex_unlock(&mfd->dma->ov_mutex);
2283 return 0;
2284 }
2285#ifdef CONFIG_FB_MSM_MIPI_DSI
2286 if (ctrl->panel_mode & MDP4_PANEL_DSI_CMD) {
2287 mdp4_dsi_cmd_dma_busy_wait(mfd);
2288 mdp4_dsi_cmd_kickoff_video(mfd, pipe);
2289 }
2290#else
2291 if (ctrl->panel_mode & MDP4_PANEL_MDDI) {
2292 mdp4_mddi_dma_busy_wait(mfd);
2293 mdp4_mddi_kickoff_video(mfd, pipe);
2294 }
2295#endif
2296 }
2297 }
2298
2299 mdp4_stat.overlay_play[pipe->mixer_num]++;
2300
2301 mutex_unlock(&mfd->dma->ov_mutex);
2302
2303 return 0;
2304}