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review.evervolv.com / android_kernel_htc_msm8960 / 4c0d304651615fb084526704703201617d81cccd / . / arch / arm / mach-msm / board-fsm9xxx.c
blob: 5d619ea88230c9b0cca8353ab95e8a7dd544a6a2 [file] [log] [blame]
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]1/* Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved.
2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 *
12 */
13#include <linux/kernel.h>
14#include <linux/irq.h>
15#include <linux/gpio.h>
16#include <linux/platform_device.h>
17#include <linux/delay.h>
18#include <linux/io.h>
19#include <linux/mfd/pmic8058.h>
20#include <linux/regulator/pmic8058-regulator.h>
21#include <linux/i2c.h>
22#include <linux/dma-mapping.h>
23#include <linux/dmapool.h>
24#include <linux/regulator/pm8058-xo.h>
25
26#include <asm/mach-types.h>
27#include <asm/mach/arch.h>
28#include <asm/setup.h>
29
30#include <mach/mpp.h>
31#include <mach/board.h>
32#include <mach/memory.h>
33#include <mach/msm_iomap.h>
34#include <mach/dma.h>
35#include <mach/sirc.h>
36#include <mach/pmic.h>
37
38#include <mach/vreg.h>
39#include <mach/socinfo.h>
40#include "devices.h"
41#include "timer.h"
42#include "pm.h"
43#include "spm.h"
44#include <linux/regulator/consumer.h>
45#include <linux/regulator/machine.h>
46#include <linux/msm_adc.h>
47#include <linux/pmic8058-xoadc.h>
48#include <linux/m_adcproc.h>
49#include <linux/platform_data/qcom_crypto_device.h>
50
51#define PMIC_GPIO_INT 144
52#define PMIC_VREG_WLAN_LEVEL 2900
53#define PMIC_GPIO_SD_DET 165
54
55#define GPIO_EPHY_RST_N 37
56
57#define GPIO_GRFC_FTR0_0 136 /* GRFC 20 */
58#define GPIO_GRFC_FTR0_1 137 /* GRFC 21 */
59#define GPIO_GRFC_FTR1_0 145 /* GRFC 22 */
60#define GPIO_GRFC_FTR1_1 93 /* GRFC 19 */
61#define GPIO_GRFC_2 110
62#define GPIO_GRFC_3 109
63#define GPIO_GRFC_4 108
64#define GPIO_GRFC_5 107
65#define GPIO_GRFC_6 106
66#define GPIO_GRFC_7 105
67#define GPIO_GRFC_8 104
68#define GPIO_GRFC_9 103
69#define GPIO_GRFC_10 102
70#define GPIO_GRFC_11 101
71#define GPIO_GRFC_13 99
72#define GPIO_GRFC_14 98
73#define GPIO_GRFC_15 97
74#define GPIO_GRFC_16 96
75#define GPIO_GRFC_17 95
76#define GPIO_GRFC_18 94
77#define GPIO_GRFC_24 150
78#define GPIO_GRFC_25 151
79#define GPIO_GRFC_26 152
80#define GPIO_GRFC_27 153
81#define GPIO_GRFC_28 154
82#define GPIO_GRFC_29 155
83
Rohit Vaswani26512de2011-07-11 16:01:13 -0700[diff] [blame]84#define GPIO_USER_FIRST 58
85#define GPIO_USER_LAST 63
86
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]87#define FPGA_SDCC_STATUS 0x8E0001A8
88
89/* Macros assume PMIC GPIOs start at 0 */
90#define PM8058_GPIO_PM_TO_SYS(pm_gpio) (pm_gpio + NR_MSM_GPIOS)
91#define PM8058_GPIO_SYS_TO_PM(sys_gpio) (sys_gpio - NR_MSM_GPIOS)
92
93#define PMIC_GPIO_5V_PA_PWR 21 /* PMIC GPIO Number 22 */
94#define PMIC_GPIO_4_2V_PA_PWR 22 /* PMIC GPIO Number 23 */
95#define PMIC_MPP_3 2 /* PMIC MPP Number 3 */
96#define PMIC_MPP_6 5 /* PMIC MPP Number 6 */
97#define PMIC_MPP_7 6 /* PMIC MPP Number 7 */
98#define PMIC_MPP_10 9 /* PMIC MPP Number 10 */
99
100/*
101 * PM8058
102 */
103
104static int pm8058_gpios_init(void)
105{
106 int i;
107 int rc;
108 struct pm8058_gpio_cfg {
109 int gpio;
110 struct pm8058_gpio cfg;
111 };
112
113 struct pm8058_gpio_cfg gpio_cfgs[] = {
114 { /* 5V PA Power */
115 PMIC_GPIO_5V_PA_PWR,
116 {
117 .vin_sel = 0,
118 .direction = PM_GPIO_DIR_BOTH,
119 .output_value = 1,
120 .output_buffer = PM_GPIO_OUT_BUF_CMOS,
121 .pull = PM_GPIO_PULL_DN,
122 .out_strength = PM_GPIO_STRENGTH_HIGH,
123 .function = PM_GPIO_FUNC_NORMAL,
124 .inv_int_pol = 0,
125 },
126 },
127 { /* 4.2V PA Power */
128 PMIC_GPIO_4_2V_PA_PWR,
129 {
130 .vin_sel = 0,
131 .direction = PM_GPIO_DIR_BOTH,
132 .output_value = 1,
133 .output_buffer = PM_GPIO_OUT_BUF_CMOS,
134 .pull = PM_GPIO_PULL_DN,
135 .out_strength = PM_GPIO_STRENGTH_HIGH,
136 .function = PM_GPIO_FUNC_NORMAL,
137 .inv_int_pol = 0,
138 },
139 },
140 };
141
142 for (i = 0; i < ARRAY_SIZE(gpio_cfgs); ++i) {
143 rc = pm8058_gpio_config(gpio_cfgs[i].gpio, &gpio_cfgs[i].cfg);
144 if (rc < 0) {
145 pr_err("%s pmic gpio config failed\n", __func__);
146 return rc;
147 }
148 }
149
150 return 0;
151}
152
153static int pm8058_mpps_init(void)
154{
155 int rc;
156
157 /* Set up MPP 3 and 6 as analog outputs at 1.25V */
158 rc = pm8058_mpp_config_analog_output(PMIC_MPP_3,
159 PM_MPP_AOUT_LVL_1V25_2, PM_MPP_AOUT_CTL_ENABLE);
160 if (rc) {
161 pr_err("%s: Config mpp3 on pmic 8058 failed\n", __func__);
162 return rc;
163 }
164
165 rc = pm8058_mpp_config_analog_output(PMIC_MPP_6,
166 PM_MPP_AOUT_LVL_1V25_2, PM_MPP_AOUT_CTL_ENABLE);
167 if (rc) {
168 pr_err("%s: Config mpp5 on pmic 8058 failed\n", __func__);
169 return rc;
170 }
171 return 0;
172}
173
174static struct pm8058_gpio_platform_data pm8058_gpio_data = {
175 .gpio_base = PM8058_GPIO_PM_TO_SYS(0),
176 .irq_base = PM8058_GPIO_IRQ(PMIC8058_IRQ_BASE, 0),
177 .init = pm8058_gpios_init,
178};
179
180static struct pm8058_gpio_platform_data pm8058_mpp_data = {
181 .gpio_base = PM8058_GPIO_PM_TO_SYS(PM8058_GPIOS),
182 .irq_base = PM8058_MPP_IRQ(PMIC8058_IRQ_BASE, 0),
183 .init = pm8058_mpps_init,
184};
185
186static struct regulator_consumer_supply pm8058_vreg_supply[PM8058_VREG_MAX] = {
187 [PM8058_VREG_ID_L3] = REGULATOR_SUPPLY("8058_l3", NULL),
188 [PM8058_VREG_ID_L8] = REGULATOR_SUPPLY("8058_l8", NULL),
189 [PM8058_VREG_ID_L9] = REGULATOR_SUPPLY("8058_l9", NULL),
190 [PM8058_VREG_ID_L14] = REGULATOR_SUPPLY("8058_l14", NULL),
191 [PM8058_VREG_ID_L15] = REGULATOR_SUPPLY("8058_l15", NULL),
192 [PM8058_VREG_ID_L18] = REGULATOR_SUPPLY("8058_l18", NULL),
193 [PM8058_VREG_ID_S4] = REGULATOR_SUPPLY("8058_s4", NULL),
194
195 [PM8058_VREG_ID_LVS0] = REGULATOR_SUPPLY("8058_lvs0", NULL),
196};
197
198#define PM8058_VREG_INIT(_id, _min_uV, _max_uV, _modes, _ops, _apply_uV, \
199 _always_on, _pull_down) \
200 [_id] = { \
201 .init_data = { \
202 .constraints = { \
203 .valid_modes_mask = _modes, \
204 .valid_ops_mask = _ops, \
205 .min_uV = _min_uV, \
206 .max_uV = _max_uV, \
207 .apply_uV = _apply_uV, \
208 .always_on = _always_on, \
209 }, \
210 .num_consumer_supplies = 1, \
211 .consumer_supplies = &pm8058_vreg_supply[_id], \
212 }, \
213 .pull_down_enable = _pull_down, \
214 .pin_ctrl = 0, \
215 .pin_fn = PM8058_VREG_PIN_FN_ENABLE, \
216 }
217
218#define PM8058_VREG_INIT_LDO(_id, _min_uV, _max_uV) \
219 PM8058_VREG_INIT(_id, _min_uV, _max_uV, REGULATOR_MODE_NORMAL | \
220 REGULATOR_MODE_IDLE | REGULATOR_MODE_STANDBY, \
221 REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS | \
222 REGULATOR_CHANGE_MODE, 1, 1, 1)
223
224#define PM8058_VREG_INIT_SMPS(_id, _min_uV, _max_uV) \
225 PM8058_VREG_INIT(_id, _min_uV, _max_uV, REGULATOR_MODE_NORMAL | \
226 REGULATOR_MODE_IDLE | REGULATOR_MODE_STANDBY, \
227 REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS | \
228 REGULATOR_CHANGE_MODE, 1, 1, 1)
229
230#define PM8058_VREG_INIT_LVS(_id, _min_uV, _max_uV) \
231 PM8058_VREG_INIT(_id, _min_uV, _min_uV, REGULATOR_MODE_NORMAL, \
232 REGULATOR_CHANGE_STATUS, 0, 0, 1)
233
234static struct pm8058_vreg_pdata pm8058_vreg_init[PM8058_VREG_MAX] = {
235 PM8058_VREG_INIT_LDO(PM8058_VREG_ID_L3, 1800000, 1800000),
236 PM8058_VREG_INIT_LDO(PM8058_VREG_ID_L8, 2200000, 2200000),
237 PM8058_VREG_INIT_LDO(PM8058_VREG_ID_L9, 2050000, 2050000),
238 PM8058_VREG_INIT_LDO(PM8058_VREG_ID_L14, 2850000, 2850000),
239 PM8058_VREG_INIT_LDO(PM8058_VREG_ID_L15, 2200000, 2200000),
240 PM8058_VREG_INIT_LDO(PM8058_VREG_ID_L18, 2200000, 2200000),
241 PM8058_VREG_INIT_LVS(PM8058_VREG_ID_LVS0, 1800000, 1800000),
242 PM8058_VREG_INIT_SMPS(PM8058_VREG_ID_S4, 1300000, 1300000),
243};
244
245#define PM8058_VREG(_id) { \
246 .name = "pm8058-regulator", \
247 .id = _id, \
248 .platform_data = &pm8058_vreg_init[_id], \
249}
250
251#ifdef CONFIG_SENSORS_MSM_ADC
252static struct resource resources_adc[] = {
253 {
254 .start = PM8058_ADC_IRQ(PMIC8058_IRQ_BASE),
255 .end = PM8058_ADC_IRQ(PMIC8058_IRQ_BASE),
256 .flags = IORESOURCE_IRQ,
257 },
258};
259
260static struct adc_access_fn xoadc_fn = {
261 pm8058_xoadc_select_chan_and_start_conv,
262 pm8058_xoadc_read_adc_code,
263 pm8058_xoadc_get_properties,
264 pm8058_xoadc_slot_request,
265 pm8058_xoadc_restore_slot,
266 pm8058_xoadc_calibrate,
267};
268
269static struct msm_adc_channels msm_adc_channels_data[] = {
270 {"pmic_therm", CHANNEL_ADC_DIE_TEMP, 0, &xoadc_fn, CHAN_PATH_TYPE12,
271 ADC_CONFIG_TYPE2, ADC_CALIB_CONFIG_TYPE1, scale_pmic_therm},
272 {"ref_1250mv", CHANNEL_ADC_1250_REF, 0, &xoadc_fn, CHAN_PATH_TYPE13,
273 ADC_CONFIG_TYPE2, ADC_CALIB_CONFIG_TYPE2, scale_default},
274 {"xo_therm", CHANNEL_ADC_XOTHERM, 0, &xoadc_fn, CHAN_PATH_TYPE_NONE,
275 ADC_CONFIG_TYPE2, ADC_CALIB_CONFIG_TYPE5, tdkntcgtherm},
276 {"fsm_therm", CHANNEL_ADC_FSM_THERM, 0, &xoadc_fn, CHAN_PATH_TYPE6,
277 ADC_CONFIG_TYPE2, ADC_CALIB_CONFIG_TYPE5, tdkntcgtherm},
278 {"pa_therm", CHANNEL_ADC_PA_THERM, 0, &xoadc_fn, CHAN_PATH_TYPE7,
279 ADC_CONFIG_TYPE2, ADC_CALIB_CONFIG_TYPE5, tdkntcgtherm},
280};
281
282static struct msm_adc_platform_data msm_adc_pdata = {
283 .channel = msm_adc_channels_data,
284 .num_chan_supported = ARRAY_SIZE(msm_adc_channels_data),
285 .target_hw = FSM_9xxx,
286};
287
288static struct platform_device msm_adc_device = {
289 .name = "msm_adc",
290 .id = -1,
291 .dev = {
292 .platform_data = &msm_adc_pdata,
293 },
294};
295
296static void pmic8058_xoadc_mpp_config(void)
297{
298 int rc;
299
300 rc = pm8058_mpp_config_analog_input(XOADC_MPP_7,
301 PM_MPP_AIN_AMUX_CH5, PM_MPP_AOUT_CTL_DISABLE);
302 if (rc)
303 pr_err("%s: Config mpp7 on pmic 8058 failed\n", __func__);
304
305 rc = pm8058_mpp_config_analog_input(XOADC_MPP_10,
306 PM_MPP_AIN_AMUX_CH6, PM_MPP_AOUT_CTL_DISABLE);
307 if (rc)
308 pr_err("%s: Config mpp10 on pmic 8058 failed\n", __func__);
309}
310
311static struct regulator *vreg_ldo18_adc;
312
313static int pmic8058_xoadc_vreg_config(int on)
314{
315 int rc;
316
317 if (on) {
318 rc = regulator_enable(vreg_ldo18_adc);
319 if (rc)
320 pr_err("%s: Enable of regulator ldo18_adc "
321 "failed\n", __func__);
322 } else {
323 rc = regulator_disable(vreg_ldo18_adc);
324 if (rc)
325 pr_err("%s: Disable of regulator ldo18_adc "
326 "failed\n", __func__);
327 }
328
329 return rc;
330}
331
332static int pmic8058_xoadc_vreg_setup(void)
333{
334 int rc;
335
336 vreg_ldo18_adc = regulator_get(NULL, "8058_l18");
337 if (IS_ERR(vreg_ldo18_adc)) {
338 pr_err("%s: vreg get failed (%ld)\n",
339 __func__, PTR_ERR(vreg_ldo18_adc));
340 rc = PTR_ERR(vreg_ldo18_adc);
341 goto fail;
342 }
343
344 rc = regulator_set_voltage(vreg_ldo18_adc, 2200000, 2200000);
345 if (rc) {
346 pr_err("%s: unable to set ldo18 voltage to 2.2V\n", __func__);
347 goto fail;
348 }
349
350 return rc;
351fail:
352 regulator_put(vreg_ldo18_adc);
353 return rc;
354}
355
356static void pmic8058_xoadc_vreg_shutdown(void)
357{
358 regulator_put(vreg_ldo18_adc);
359}
360
361/* usec. For this ADC,
362 * this time represents clk rate @ txco w/ 1024 decimation ratio.
363 * Each channel has different configuration, thus at the time of starting
364 * the conversion, xoadc will return actual conversion time
365 * */
366static struct adc_properties pm8058_xoadc_data = {
367 .adc_reference = 2200, /* milli-voltage for this adc */
368 .bitresolution = 15,
369 .bipolar = 0,
370 .conversiontime = 54,
371};
372
373static struct xoadc_platform_data xoadc_pdata = {
374 .xoadc_prop = &pm8058_xoadc_data,
375 .xoadc_mpp_config = pmic8058_xoadc_mpp_config,
376 .xoadc_vreg_set = pmic8058_xoadc_vreg_config,
377 .xoadc_num = XOADC_PMIC_0,
378 .xoadc_vreg_setup = pmic8058_xoadc_vreg_setup,
379 .xoadc_vreg_shutdown = pmic8058_xoadc_vreg_shutdown,
380};
381#endif
382
Rohit Vaswani4c0d3042011-07-13 14:19:23 -0700[diff] [blame^]383#define XO_CONSUMERS(_id) \
384 static struct regulator_consumer_supply xo_consumers_##_id[]
385
386/*
387 * Consumer specific regulator names:
388 * regulator name consumer dev_name
389 */
390XO_CONSUMERS(A0) = {
391 REGULATOR_SUPPLY("8058_xo_a0", NULL),
392 REGULATOR_SUPPLY("a0_clk_buffer", "fsm_xo_driver"),
393};
394XO_CONSUMERS(A1) = {
395 REGULATOR_SUPPLY("8058_xo_a1", NULL),
396 REGULATOR_SUPPLY("a1_clk_buffer", "fsm_xo_driver"),
397};
398
399#define PM8058_XO_INIT(_id, _modes, _ops, _always_on) \
400 [PM8058_XO_ID_##_id] = { \
401 .init_data = { \
402 .constraints = { \
403 .valid_modes_mask = _modes, \
404 .valid_ops_mask = _ops, \
405 .always_on = _always_on, \
406 }, \
407 .num_consumer_supplies = \
408 ARRAY_SIZE(xo_consumers_##_id),\
409 .consumer_supplies = xo_consumers_##_id, \
410 }, \
411 }
412
413#define PM8058_XO_INIT_AX(_id) \
414 PM8058_XO_INIT(_id, REGULATOR_MODE_NORMAL, REGULATOR_CHANGE_STATUS, 0)
415
416static struct pm8058_xo_pdata pm8058_xo_init_pdata[PM8058_XO_ID_MAX] = {
417 PM8058_XO_INIT_AX(A0),
418 PM8058_XO_INIT_AX(A1),
419};
420
421#define PM8058_XO(_id) { \
422 .name = PM8058_XO_BUFFER_DEV_NAME, \
423 .id = _id, \
424 .platform_data = &pm8058_xo_init_pdata[_id], \
425 .pdata_size = sizeof(pm8058_xo_init_pdata[_id]), \
426}
427
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]428/* Put sub devices with fixed location first in sub_devices array */
429static struct mfd_cell pm8058_subdevs[] = {
430 { .name = "pm8058-mpp",
431 .platform_data = &pm8058_mpp_data,
432 .pdata_size = sizeof(pm8058_mpp_data),
433 },
434 {
435 .name = "pm8058-gpio",
436 .id = -1,
437 .platform_data = &pm8058_gpio_data,
438 .pdata_size = sizeof(pm8058_gpio_data),
439 },
440#ifdef CONFIG_SENSORS_MSM_ADC
441 {
442 .name = "pm8058-xoadc",
443 .id = -1,
444 .num_resources = ARRAY_SIZE(resources_adc),
445 .resources = resources_adc,
446 .platform_data = &xoadc_pdata,
447 .pdata_size =sizeof(xoadc_pdata),
448 },
449#endif
450 PM8058_VREG(PM8058_VREG_ID_L3),
451 PM8058_VREG(PM8058_VREG_ID_L8),
452 PM8058_VREG(PM8058_VREG_ID_L9),
453 PM8058_VREG(PM8058_VREG_ID_L14),
454 PM8058_VREG(PM8058_VREG_ID_L15),
455 PM8058_VREG(PM8058_VREG_ID_L18),
456 PM8058_VREG(PM8058_VREG_ID_S4),
457 PM8058_VREG(PM8058_VREG_ID_LVS0),
458 PM8058_XO(PM8058_XO_ID_A0),
459 PM8058_XO(PM8058_XO_ID_A1),
460};
461
462static struct pm8058_platform_data pm8058_fsm9xxx_data = {
463 .irq_base = PMIC8058_IRQ_BASE,
464
465 .num_subdevs = ARRAY_SIZE(pm8058_subdevs),
466 .sub_devices = pm8058_subdevs,
467};
468
469static struct i2c_board_info pm8058_boardinfo[] __initdata = {
470 {
471 I2C_BOARD_INFO("pm8058-core", 0x55),
472 .irq = MSM_GPIO_TO_INT(47),
473 .platform_data = &pm8058_fsm9xxx_data,
474 },
475};
476
477static int __init buses_init(void)
478{
479 if (gpio_tlmm_config(GPIO_CFG(PMIC_GPIO_INT, 5, GPIO_CFG_INPUT,
480 GPIO_CFG_NO_PULL, GPIO_CFG_2MA), GPIO_CFG_ENABLE))
481 pr_err("%s: gpio_tlmm_config (gpio=%d) failed\n",
482 __func__, PMIC_GPIO_INT);
483
484 i2c_register_board_info(0 /* I2C_SSBI ID */, pm8058_boardinfo,
485 ARRAY_SIZE(pm8058_boardinfo));
486
487 return 0;
488}
489
490/*
491 * EPHY
492 */
493
494static struct msm_gpio phy_config_data[] = {
495 { GPIO_CFG(GPIO_EPHY_RST_N, 0, GPIO_CFG_OUTPUT,
496 GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "MAC_RST_N" },
497};
498
499static int __init phy_init(void)
500{
501 msm_gpios_request_enable(phy_config_data, ARRAY_SIZE(phy_config_data));
502 gpio_direction_output(GPIO_EPHY_RST_N, 0);
503 udelay(100);
504 gpio_set_value(GPIO_EPHY_RST_N, 1);
505
506 return 0;
507}
508
509/*
510 * RF
511 */
512
513static struct msm_gpio grfc_config_data[] = {
514 { GPIO_CFG(GPIO_GRFC_FTR0_0, 7, GPIO_CFG_OUTPUT,
515 GPIO_CFG_PULL_DOWN, GPIO_CFG_4MA), "HH_RFMODE1_0" },
516 { GPIO_CFG(GPIO_GRFC_FTR0_1, 7, GPIO_CFG_OUTPUT,
517 GPIO_CFG_PULL_DOWN, GPIO_CFG_4MA), "HH_RFMODE1_1" },
518 { GPIO_CFG(GPIO_GRFC_FTR1_0, 7, GPIO_CFG_OUTPUT,
519 GPIO_CFG_PULL_DOWN, GPIO_CFG_4MA), "HH_RFMODE2_0" },
520 { GPIO_CFG(GPIO_GRFC_FTR1_1, 7, GPIO_CFG_OUTPUT,
521 GPIO_CFG_PULL_DOWN, GPIO_CFG_4MA), "HH_RFMODE2_1" },
522 { GPIO_CFG(GPIO_GRFC_2, 7, GPIO_CFG_OUTPUT,
523 GPIO_CFG_PULL_DOWN, GPIO_CFG_4MA), "GPIO_GRFC_2" },
524 { GPIO_CFG(GPIO_GRFC_3, 7, GPIO_CFG_OUTPUT,
525 GPIO_CFG_PULL_DOWN, GPIO_CFG_4MA), "GPIO_GRFC_3" },
526 { GPIO_CFG(GPIO_GRFC_4, 7, GPIO_CFG_OUTPUT,
527 GPIO_CFG_PULL_DOWN, GPIO_CFG_4MA), "GPIO_GRFC_4" },
528 { GPIO_CFG(GPIO_GRFC_5, 7, GPIO_CFG_OUTPUT,
529 GPIO_CFG_PULL_DOWN, GPIO_CFG_4MA), "GPIO_GRFC_5" },
530 { GPIO_CFG(GPIO_GRFC_6, 7, GPIO_CFG_OUTPUT,
531 GPIO_CFG_PULL_DOWN, GPIO_CFG_4MA), "GPIO_GRFC_6" },
532 { GPIO_CFG(GPIO_GRFC_7, 7, GPIO_CFG_OUTPUT,
533 GPIO_CFG_PULL_DOWN, GPIO_CFG_4MA), "GPIO_GRFC_7" },
534 { GPIO_CFG(GPIO_GRFC_8, 7, GPIO_CFG_OUTPUT,
535 GPIO_CFG_PULL_DOWN, GPIO_CFG_4MA), "GPIO_GRFC_8" },
536 { GPIO_CFG(GPIO_GRFC_9, 7, GPIO_CFG_OUTPUT,
537 GPIO_CFG_PULL_DOWN, GPIO_CFG_4MA), "GPIO_GRFC_9" },
538 { GPIO_CFG(GPIO_GRFC_10, 7, GPIO_CFG_OUTPUT,
539 GPIO_CFG_PULL_DOWN, GPIO_CFG_4MA), "GPIO_GRFC_10" },
540 { GPIO_CFG(GPIO_GRFC_11, 7, GPIO_CFG_OUTPUT,
541 GPIO_CFG_PULL_DOWN, GPIO_CFG_4MA), "GPIO_GRFC_11" },
542 { GPIO_CFG(GPIO_GRFC_13, 7, GPIO_CFG_OUTPUT,
543 GPIO_CFG_PULL_DOWN, GPIO_CFG_4MA), "GPIO_GRFC_13" },
544 { GPIO_CFG(GPIO_GRFC_14, 7, GPIO_CFG_OUTPUT,
545 GPIO_CFG_PULL_DOWN, GPIO_CFG_4MA), "GPIO_GRFC_14" },
546 { GPIO_CFG(GPIO_GRFC_15, 7, GPIO_CFG_OUTPUT,
547 GPIO_CFG_PULL_DOWN, GPIO_CFG_4MA), "GPIO_GRFC_15" },
548 { GPIO_CFG(GPIO_GRFC_16, 7, GPIO_CFG_OUTPUT,
549 GPIO_CFG_PULL_DOWN, GPIO_CFG_4MA), "GPIO_GRFC_16" },
550 { GPIO_CFG(GPIO_GRFC_17, 7, GPIO_CFG_OUTPUT,
551 GPIO_CFG_PULL_DOWN, GPIO_CFG_4MA), "GPIO_GRFC_17" },
552 { GPIO_CFG(GPIO_GRFC_18, 7, GPIO_CFG_OUTPUT,
553 GPIO_CFG_PULL_DOWN, GPIO_CFG_4MA), "GPIO_GRFC_18" },
554 { GPIO_CFG(GPIO_GRFC_24, 7, GPIO_CFG_OUTPUT,
555 GPIO_CFG_PULL_DOWN, GPIO_CFG_4MA), "GPIO_GRFC_24" },
556 { GPIO_CFG(GPIO_GRFC_25, 7, GPIO_CFG_OUTPUT,
557 GPIO_CFG_PULL_DOWN, GPIO_CFG_4MA), "GPIO_GRFC_25" },
558 { GPIO_CFG(GPIO_GRFC_26, 7, GPIO_CFG_OUTPUT,
559 GPIO_CFG_PULL_DOWN, GPIO_CFG_4MA), "GPIO_GRFC_26" },
560 { GPIO_CFG(GPIO_GRFC_27, 7, GPIO_CFG_OUTPUT,
561 GPIO_CFG_PULL_DOWN, GPIO_CFG_4MA), "GPIO_GRFC_27" },
562 { GPIO_CFG(GPIO_GRFC_28, 7, GPIO_CFG_OUTPUT,
563 GPIO_CFG_PULL_DOWN, GPIO_CFG_4MA), "GPIO_GRFC_28" },
564 { GPIO_CFG(GPIO_GRFC_29, 7, GPIO_CFG_OUTPUT,
565 GPIO_CFG_PULL_DOWN, GPIO_CFG_4MA), "GPIO_GRFC_29" },
566 { GPIO_CFG(39, 1, GPIO_CFG_OUTPUT,
567 GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "PP2S_EXT_SYNC" },
568};
569
570static int __init grfc_init(void)
571{
572 msm_gpios_request_enable(grfc_config_data,
573 ARRAY_SIZE(grfc_config_data));
574
575 return 0;
576}
577
578/*
579 * UART
580 */
581
582#ifdef CONFIG_SERIAL_MSM_CONSOLE
583static struct msm_gpio uart1_config_data[] = {
584 { GPIO_CFG(138, 1, GPIO_CFG_INPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA),
585 "UART1_Rx" },
586 { GPIO_CFG(139, 1, GPIO_CFG_OUTPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA),
587 "UART1_Tx" },
588};
589
590static void fsm9xxx_init_uart1(void)
591{
592 msm_gpios_request_enable(uart1_config_data,
593 ARRAY_SIZE(uart1_config_data));
594
595}
596#endif
597
598/*
599 * SSBI
600 */
601
602#ifdef CONFIG_I2C_SSBI
603static struct msm_i2c_ssbi_platform_data msm_i2c_ssbi1_pdata = {
604 .controller_type = FSM_SBI_CTRL_SSBI,
605};
606
607static struct msm_i2c_ssbi_platform_data msm_i2c_ssbi2_pdata = {
608 .controller_type = FSM_SBI_CTRL_SSBI,
609};
610
611static struct msm_i2c_ssbi_platform_data msm_i2c_ssbi3_pdata = {
612 .controller_type = FSM_SBI_CTRL_SSBI,
613};
614
615/* Intialize GPIO configuration for SSBI */
616static struct msm_gpio ssbi_gpio_config_data[] = {
617 { GPIO_CFG(140, 1, GPIO_CFG_OUTPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_4MA),
618 "SSBI_1" },
619 { GPIO_CFG(141, 1, GPIO_CFG_OUTPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_4MA),
620 "SSBI_2" },
621 { GPIO_CFG(92, 2, GPIO_CFG_OUTPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_4MA),
622 "SSBI_3" },
623};
624
625static void
626fsm9xxx_init_ssbi_gpio(void)
627{
628 msm_gpios_request_enable(ssbi_gpio_config_data,
629 ARRAY_SIZE(ssbi_gpio_config_data));
630
631}
632#endif
633
634/*
Rohit Vaswani26512de2011-07-11 16:01:13 -0700[diff] [blame]635 * User GPIOs
636 */
637
638static void user_gpios_init(void)
639{
640 unsigned int gpio;
641
642 for (gpio = GPIO_USER_FIRST; gpio <= GPIO_USER_LAST; ++gpio)
643 gpio_tlmm_config(GPIO_CFG(gpio, 0, GPIO_CFG_INPUT,
644 GPIO_CFG_NO_PULL, GPIO_CFG_2MA), GPIO_CFG_ENABLE);
645}
646
647/*
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]648 * Crypto
649 */
650
651#define QCE_SIZE 0x10000
652
653#define QCE_0_BASE 0x80C00000
654#define QCE_1_BASE 0x80E00000
655#define QCE_2_BASE 0x81000000
656
657#define QCE_NO_HW_KEY_SUPPORT 0 /* No shared HW key with external */
658#define QCE_NO_SHARE_CE_RESOURCE 0 /* No CE resource shared with TZ */
659#define QCE_NO_CE_SHARED 0 /* CE not shared with TZ */
660#define QCE_NO_SHA_HMAC_SUPPORT 0 /* No SHA-HMAC by SHA operation */
661
662static struct resource qcrypto_resources[] = {
663 [0] = {
664 .start = QCE_0_BASE,
665 .end = QCE_0_BASE + QCE_SIZE - 1,
666 .flags = IORESOURCE_MEM,
667 },
668 [1] = {
669 .name = "crypto_channels",
670 .start = DMOV_CE1_IN_CHAN,
671 .end = DMOV_CE1_OUT_CHAN,
672 .flags = IORESOURCE_DMA,
673 },
674 [2] = {
675 .name = "crypto_crci_in",
676 .start = DMOV_CE1_IN_CRCI,
677 .end = DMOV_CE1_IN_CRCI,
678 .flags = IORESOURCE_DMA,
679 },
680 [3] = {
681 .name = "crypto_crci_out",
682 .start = DMOV_CE1_OUT_CRCI,
683 .end = DMOV_CE1_OUT_CRCI,
684 .flags = IORESOURCE_DMA,
685 },
686 [4] = {
687 .name = "crypto_crci_hash",
688 .start = DMOV_CE1_HASH_CRCI,
689 .end = DMOV_CE1_HASH_CRCI,
690 .flags = IORESOURCE_DMA,
691 },
692};
693
694static struct msm_ce_hw_support qcrypto_ce_hw_suppport = {
695 .ce_shared = QCE_NO_CE_SHARED,
696 .shared_ce_resource = QCE_NO_SHARE_CE_RESOURCE,
697 .hw_key_support = QCE_NO_HW_KEY_SUPPORT,
698 .sha_hmac = QCE_NO_SHA_HMAC_SUPPORT,
699};
700
701struct platform_device qcrypto_device = {
702 .name = "qcrypto",
703 .id = 0,
704 .num_resources = ARRAY_SIZE(qcrypto_resources),
705 .resource = qcrypto_resources,
706 .dev = {
707 .coherent_dma_mask = DMA_BIT_MASK(32),
708 .platform_data = &qcrypto_ce_hw_suppport,
709 },
710};
711
712static struct resource qcedev_resources[] = {
713 [0] = {
714 .start = QCE_0_BASE,
715 .end = QCE_0_BASE + QCE_SIZE - 1,
716 .flags = IORESOURCE_MEM,
717 },
718 [1] = {
719 .name = "crypto_channels",
720 .start = DMOV_CE1_IN_CHAN,
721 .end = DMOV_CE1_OUT_CHAN,
722 .flags = IORESOURCE_DMA,
723 },
724 [2] = {
725 .name = "crypto_crci_in",
726 .start = DMOV_CE1_IN_CRCI,
727 .end = DMOV_CE1_IN_CRCI,
728 .flags = IORESOURCE_DMA,
729 },
730 [3] = {
731 .name = "crypto_crci_out",
732 .start = DMOV_CE1_OUT_CRCI,
733 .end = DMOV_CE1_OUT_CRCI,
734 .flags = IORESOURCE_DMA,
735 },
736 [4] = {
737 .name = "crypto_crci_hash",
738 .start = DMOV_CE1_HASH_CRCI,
739 .end = DMOV_CE1_HASH_CRCI,
740 .flags = IORESOURCE_DMA,
741 },
742};
743
744static struct msm_ce_hw_support qcedev_ce_hw_suppport = {
745 .ce_shared = QCE_NO_CE_SHARED,
746 .shared_ce_resource = QCE_NO_SHARE_CE_RESOURCE,
747 .hw_key_support = QCE_NO_HW_KEY_SUPPORT,
748 .sha_hmac = QCE_NO_SHA_HMAC_SUPPORT,
749};
750
751static struct platform_device qcedev_device = {
752 .name = "qce",
753 .id = 0,
754 .num_resources = ARRAY_SIZE(qcedev_resources),
755 .resource = qcedev_resources,
756 .dev = {
757 .coherent_dma_mask = DMA_BIT_MASK(32),
758 .platform_data = &qcedev_ce_hw_suppport,
759 },
760};
761
762static struct resource ota_qcrypto_resources[] = {
763 [0] = {
764 .start = QCE_1_BASE,
765 .end = QCE_1_BASE + QCE_SIZE - 1,
766 .flags = IORESOURCE_MEM,
767 },
768 [1] = {
769 .name = "crypto_channels",
770 .start = DMOV_CE2_IN_CHAN,
771 .end = DMOV_CE2_OUT_CHAN,
772 .flags = IORESOURCE_DMA,
773 },
774 [2] = {
775 .name = "crypto_crci_in",
776 .start = DMOV_CE2_IN_CRCI,
777 .end = DMOV_CE2_IN_CRCI,
778 .flags = IORESOURCE_DMA,
779 },
780 [3] = {
781 .name = "crypto_crci_out",
782 .start = DMOV_CE2_OUT_CRCI,
783 .end = DMOV_CE2_OUT_CRCI,
784 .flags = IORESOURCE_DMA,
785 },
786 [4] = {
787 .name = "crypto_crci_hash",
788 .start = DMOV_CE2_HASH_CRCI,
789 .end = DMOV_CE2_HASH_CRCI,
790 .flags = IORESOURCE_DMA,
791 },
792};
793
794struct platform_device ota_qcrypto_device = {
795 .name = "qcota",
796 .id = 0,
797 .num_resources = ARRAY_SIZE(ota_qcrypto_resources),
798 .resource = ota_qcrypto_resources,
799 .dev = {
800 .coherent_dma_mask = DMA_BIT_MASK(32),
801 },
802};
803
804/*
805 * Devices
806 */
807
808static struct platform_device *devices[] __initdata = {
809 &msm_device_smd,
810 &msm_device_dmov,
811 &msm_device_nand,
812#ifdef CONFIG_I2C_SSBI
813 &msm_device_ssbi1,
814 &msm_device_ssbi2,
815 &msm_device_ssbi3,
816#endif
817#ifdef CONFIG_SENSORS_MSM_ADC
818 &msm_adc_device,
819#endif
820#ifdef CONFIG_I2C_QUP
821 &msm_gsbi1_qup_i2c_device,
822#endif
823#if defined(CONFIG_SERIAL_MSM) || defined(CONFIG_MSM_SERIAL_DEBUGGER)
824 &msm_device_uart1,
825#endif
826#if defined(CONFIG_QFP_FUSE)
827 &fsm_qfp_fuse_device,
828#endif
829 &qfec_device,
830 &qcrypto_device,
831 &qcedev_device,
832 &ota_qcrypto_device,
Rohit Vaswani4c0d3042011-07-13 14:19:23 -0700[diff] [blame^]833 &fsm_xo_device,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]834};
835
836static struct msm_acpu_clock_platform_data fsm9xxx_clock_data = {
837 .acpu_switch_time_us = 50,
838 .vdd_switch_time_us = 62,
839};
840
841static void __init fsm9xxx_init_irq(void)
842{
843 msm_init_irq();
844 msm_init_sirc();
845}
846
847#ifdef CONFIG_MSM_SPM
848static struct msm_spm_platform_data msm_spm_data __initdata = {
849 .reg_base_addr = MSM_SAW_BASE,
850
851 .reg_init_values[MSM_SPM_REG_SAW_CFG] = 0x05,
852 .reg_init_values[MSM_SPM_REG_SAW_SPM_CTL] = 0x18,
853 .reg_init_values[MSM_SPM_REG_SAW_SPM_SLP_TMR_DLY] = 0x00006666,
854 .reg_init_values[MSM_SPM_REG_SAW_SPM_WAKE_TMR_DLY] = 0xFF000666,
855
856 .reg_init_values[MSM_SPM_REG_SAW_SPM_PMIC_CTL] = 0xE0F272,
857 .reg_init_values[MSM_SPM_REG_SAW_SLP_CLK_EN] = 0x01,
858 .reg_init_values[MSM_SPM_REG_SAW_SLP_HSFS_PRECLMP_EN] = 0x03,
859 .reg_init_values[MSM_SPM_REG_SAW_SLP_HSFS_POSTCLMP_EN] = 0x00,
860
861 .reg_init_values[MSM_SPM_REG_SAW_SLP_CLMP_EN] = 0x01,
862 .reg_init_values[MSM_SPM_REG_SAW_SLP_RST_EN] = 0x00,
863 .reg_init_values[MSM_SPM_REG_SAW_SPM_MPM_CFG] = 0x00,
864
865 .awake_vlevel = 0xF2,
866 .retention_vlevel = 0xE0,
867 .collapse_vlevel = 0x72,
868 .retention_mid_vlevel = 0xE0,
869 .collapse_mid_vlevel = 0xE0,
870};
871#endif
872
873static void __init fsm9xxx_init(void)
874{
875 if (socinfo_init() < 0)
876 pr_err("%s: socinfo_init() failed!\n",
877 __func__);
878
879 msm_acpu_clock_init(&fsm9xxx_clock_data);
880
881 regulator_has_full_constraints();
882
883 platform_add_devices(devices, ARRAY_SIZE(devices));
884
885#ifdef CONFIG_MSM_SPM
886 msm_spm_init(&msm_spm_data, 1);
887#endif
888 buses_init();
889 phy_init();
890 grfc_init();
Rohit Vaswani26512de2011-07-11 16:01:13 -0700[diff] [blame]891 user_gpios_init();
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]892
893#ifdef CONFIG_SERIAL_MSM_CONSOLE
894 fsm9xxx_init_uart1();
895#endif
896#ifdef CONFIG_I2C_SSBI
897 fsm9xxx_init_ssbi_gpio();
898 msm_device_ssbi1.dev.platform_data = &msm_i2c_ssbi1_pdata;
899 msm_device_ssbi2.dev.platform_data = &msm_i2c_ssbi2_pdata;
900 msm_device_ssbi3.dev.platform_data = &msm_i2c_ssbi3_pdata;
901#endif
902}
903
904static void __init fsm9xxx_map_io(void)
905{
906 msm_shared_ram_phys = 0x00100000;
907 msm_map_fsm9xxx_io();
908 msm_clock_init(msm_clocks_fsm9xxx, msm_num_clocks_fsm9xxx);
909}
910
911MACHINE_START(FSM9XXX_SURF, "QCT FSM9XXX")
912 .boot_params = PHYS_OFFSET + 0x100,
913 .map_io = fsm9xxx_map_io,
914 .init_irq = fsm9xxx_init_irq,
915 .init_machine = fsm9xxx_init,
916 .timer = &msm_timer,
917MACHINE_END