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Linus Torvalds1da177e2005-04-16 15:20:36 -07001menu "DMA support"
2
3config SH_DMA
4 bool "DMA controller (DMAC) support"
5 help
6 Selecting this option will provide same API as PC's Direct Memory
7 Access Controller(8237A) for SuperH DMAC.
8
9 If unsure, say N.
10
11config NR_ONCHIP_DMA_CHANNELS
12 depends on SH_DMA
13 int "Number of on-chip DMAC channels"
Paul Mundt5283ecb2006-09-27 15:59:17 +090014 default "8" if CPU_SUBTYPE_SH7750R || CPU_SUBTYPE_SH7751R
15 default "12" if CPU_SUBTYPE_SH7780
Linus Torvalds1da177e2005-04-16 15:20:36 -070016 default "4"
17 help
18 This allows you to specify the number of channels that the on-chip
19 DMAC supports. This will be 4 for SH7750/SH7751 and 8 for the
20 SH7750R/SH7751R.
21
22config NR_DMA_CHANNELS_BOOL
23 depends on SH_DMA
24 bool "Override default number of maximum DMA channels"
25 help
26 This allows you to forcibly update the maximum number of supported
27 DMA channels for a given board. If this is unset, this will default
28 to the number of channels that the on-chip DMAC has.
29
30config NR_DMA_CHANNELS
31 int "Maximum number of DMA channels"
32 depends on SH_DMA && NR_DMA_CHANNELS_BOOL
33 default NR_ONCHIP_DMA_CHANNELS
34 help
35 This allows you to specify the maximum number of DMA channels to
36 support. Setting this to a higher value allows for cascading DMACs
37 with additional channels.
38
39config DMA_PAGE_OPS
40 bool "Use DMAC for page copy/clear"
41 depends on SH_DMA && BROKEN
42 help
43 Selecting this option will use a dual-address mode configured channel
44 in the SH DMAC for copy_page()/clear_page(). Primarily a performance
45 hack.
46
47config DMA_PAGE_OPS_CHANNEL
48 depends on DMA_PAGE_OPS
49 int "DMA channel for sh memory-manager page copy/clear"
50 default "3"
51 help
52 This allows the specification of the dual address dma channel,
53 in case channel 3 is unavailable. On the SH4, channels 1,2, and 3
54 are dual-address capable.
55
56endmenu