blob: bbfc22a5f6dbaca149f6b440da2e0cf1e0d18777 [file] [log] [blame]
Michael Krufky59067f72008-01-02 01:58:26 -03001/*
2 tda18271-common.c - driver for the Philips / NXP TDA18271 silicon tuner
3
4 Copyright (C) 2007, 2008 Michael Krufky <mkrufky@linuxtv.org>
5
6 This program is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2 of the License, or
9 (at your option) any later version.
10
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
18 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
19*/
20
21#include "tda18271-priv.h"
22
23static int tda18271_i2c_gate_ctrl(struct dvb_frontend *fe, int enable)
24{
25 struct tda18271_priv *priv = fe->tuner_priv;
26 enum tda18271_i2c_gate gate;
27 int ret = 0;
28
29 switch (priv->gate) {
30 case TDA18271_GATE_DIGITAL:
31 case TDA18271_GATE_ANALOG:
32 gate = priv->gate;
33 break;
34 case TDA18271_GATE_AUTO:
35 default:
36 switch (priv->mode) {
37 case TDA18271_DIGITAL:
38 gate = TDA18271_GATE_DIGITAL;
39 break;
40 case TDA18271_ANALOG:
41 default:
42 gate = TDA18271_GATE_ANALOG;
43 break;
44 }
45 }
46
47 switch (gate) {
48 case TDA18271_GATE_ANALOG:
49 if (fe->ops.analog_ops.i2c_gate_ctrl)
50 ret = fe->ops.analog_ops.i2c_gate_ctrl(fe, enable);
51 break;
52 case TDA18271_GATE_DIGITAL:
53 if (fe->ops.i2c_gate_ctrl)
54 ret = fe->ops.i2c_gate_ctrl(fe, enable);
55 break;
56 default:
57 ret = -EINVAL;
58 break;
59 }
60
61 return ret;
62};
63
64/*---------------------------------------------------------------------*/
65
66static void tda18271_dump_regs(struct dvb_frontend *fe, int extended)
67{
68 struct tda18271_priv *priv = fe->tuner_priv;
69 unsigned char *regs = priv->tda18271_regs;
70
71 tda_reg("=== TDA18271 REG DUMP ===\n");
72 tda_reg("ID_BYTE = 0x%02x\n", 0xff & regs[R_ID]);
73 tda_reg("THERMO_BYTE = 0x%02x\n", 0xff & regs[R_TM]);
74 tda_reg("POWER_LEVEL_BYTE = 0x%02x\n", 0xff & regs[R_PL]);
75 tda_reg("EASY_PROG_BYTE_1 = 0x%02x\n", 0xff & regs[R_EP1]);
76 tda_reg("EASY_PROG_BYTE_2 = 0x%02x\n", 0xff & regs[R_EP2]);
77 tda_reg("EASY_PROG_BYTE_3 = 0x%02x\n", 0xff & regs[R_EP3]);
78 tda_reg("EASY_PROG_BYTE_4 = 0x%02x\n", 0xff & regs[R_EP4]);
79 tda_reg("EASY_PROG_BYTE_5 = 0x%02x\n", 0xff & regs[R_EP5]);
80 tda_reg("CAL_POST_DIV_BYTE = 0x%02x\n", 0xff & regs[R_CPD]);
81 tda_reg("CAL_DIV_BYTE_1 = 0x%02x\n", 0xff & regs[R_CD1]);
82 tda_reg("CAL_DIV_BYTE_2 = 0x%02x\n", 0xff & regs[R_CD2]);
83 tda_reg("CAL_DIV_BYTE_3 = 0x%02x\n", 0xff & regs[R_CD3]);
84 tda_reg("MAIN_POST_DIV_BYTE = 0x%02x\n", 0xff & regs[R_MPD]);
85 tda_reg("MAIN_DIV_BYTE_1 = 0x%02x\n", 0xff & regs[R_MD1]);
86 tda_reg("MAIN_DIV_BYTE_2 = 0x%02x\n", 0xff & regs[R_MD2]);
87 tda_reg("MAIN_DIV_BYTE_3 = 0x%02x\n", 0xff & regs[R_MD3]);
88
89 /* only dump extended regs if DBG_ADV is set */
90 if (!(tda18271_debug & DBG_ADV))
91 return;
92
93 /* W indicates write-only registers.
94 * Register dump for write-only registers shows last value written. */
95
96 tda_reg("EXTENDED_BYTE_1 = 0x%02x\n", 0xff & regs[R_EB1]);
97 tda_reg("EXTENDED_BYTE_2 = 0x%02x\n", 0xff & regs[R_EB2]);
98 tda_reg("EXTENDED_BYTE_3 = 0x%02x\n", 0xff & regs[R_EB3]);
99 tda_reg("EXTENDED_BYTE_4 = 0x%02x\n", 0xff & regs[R_EB4]);
100 tda_reg("EXTENDED_BYTE_5 = 0x%02x\n", 0xff & regs[R_EB5]);
101 tda_reg("EXTENDED_BYTE_6 = 0x%02x\n", 0xff & regs[R_EB6]);
102 tda_reg("EXTENDED_BYTE_7 = 0x%02x\n", 0xff & regs[R_EB7]);
103 tda_reg("EXTENDED_BYTE_8 = 0x%02x\n", 0xff & regs[R_EB8]);
104 tda_reg("EXTENDED_BYTE_9 W = 0x%02x\n", 0xff & regs[R_EB9]);
105 tda_reg("EXTENDED_BYTE_10 = 0x%02x\n", 0xff & regs[R_EB10]);
106 tda_reg("EXTENDED_BYTE_11 = 0x%02x\n", 0xff & regs[R_EB11]);
107 tda_reg("EXTENDED_BYTE_12 = 0x%02x\n", 0xff & regs[R_EB12]);
108 tda_reg("EXTENDED_BYTE_13 = 0x%02x\n", 0xff & regs[R_EB13]);
109 tda_reg("EXTENDED_BYTE_14 = 0x%02x\n", 0xff & regs[R_EB14]);
110 tda_reg("EXTENDED_BYTE_15 = 0x%02x\n", 0xff & regs[R_EB15]);
111 tda_reg("EXTENDED_BYTE_16 W = 0x%02x\n", 0xff & regs[R_EB16]);
112 tda_reg("EXTENDED_BYTE_17 W = 0x%02x\n", 0xff & regs[R_EB17]);
113 tda_reg("EXTENDED_BYTE_18 = 0x%02x\n", 0xff & regs[R_EB18]);
114 tda_reg("EXTENDED_BYTE_19 W = 0x%02x\n", 0xff & regs[R_EB19]);
115 tda_reg("EXTENDED_BYTE_20 W = 0x%02x\n", 0xff & regs[R_EB20]);
116 tda_reg("EXTENDED_BYTE_21 = 0x%02x\n", 0xff & regs[R_EB21]);
117 tda_reg("EXTENDED_BYTE_22 = 0x%02x\n", 0xff & regs[R_EB22]);
118 tda_reg("EXTENDED_BYTE_23 = 0x%02x\n", 0xff & regs[R_EB23]);
119}
120
121int tda18271_read_regs(struct dvb_frontend *fe)
122{
123 struct tda18271_priv *priv = fe->tuner_priv;
124 unsigned char *regs = priv->tda18271_regs;
125 unsigned char buf = 0x00;
126 int ret;
127 struct i2c_msg msg[] = {
Michael Krufkyf9e315a2008-04-22 14:41:54 -0300128 { .addr = priv->i2c_props.addr, .flags = 0,
Michael Krufky59067f72008-01-02 01:58:26 -0300129 .buf = &buf, .len = 1 },
Michael Krufkyf9e315a2008-04-22 14:41:54 -0300130 { .addr = priv->i2c_props.addr, .flags = I2C_M_RD,
Michael Krufky59067f72008-01-02 01:58:26 -0300131 .buf = regs, .len = 16 }
132 };
133
134 tda18271_i2c_gate_ctrl(fe, 1);
135
136 /* read all registers */
Michael Krufkyf9e315a2008-04-22 14:41:54 -0300137 ret = i2c_transfer(priv->i2c_props.adap, msg, 2);
Michael Krufky59067f72008-01-02 01:58:26 -0300138
139 tda18271_i2c_gate_ctrl(fe, 0);
140
141 if (ret != 2)
142 tda_err("ERROR: i2c_transfer returned: %d\n", ret);
143
144 if (tda18271_debug & DBG_REG)
145 tda18271_dump_regs(fe, 0);
146
147 return (ret == 2 ? 0 : ret);
148}
149
150int tda18271_read_extended(struct dvb_frontend *fe)
151{
152 struct tda18271_priv *priv = fe->tuner_priv;
153 unsigned char *regs = priv->tda18271_regs;
154 unsigned char regdump[TDA18271_NUM_REGS];
155 unsigned char buf = 0x00;
156 int ret, i;
157 struct i2c_msg msg[] = {
Michael Krufkyf9e315a2008-04-22 14:41:54 -0300158 { .addr = priv->i2c_props.addr, .flags = 0,
Michael Krufky59067f72008-01-02 01:58:26 -0300159 .buf = &buf, .len = 1 },
Michael Krufkyf9e315a2008-04-22 14:41:54 -0300160 { .addr = priv->i2c_props.addr, .flags = I2C_M_RD,
Michael Krufky59067f72008-01-02 01:58:26 -0300161 .buf = regdump, .len = TDA18271_NUM_REGS }
162 };
163
164 tda18271_i2c_gate_ctrl(fe, 1);
165
166 /* read all registers */
Michael Krufkyf9e315a2008-04-22 14:41:54 -0300167 ret = i2c_transfer(priv->i2c_props.adap, msg, 2);
Michael Krufky59067f72008-01-02 01:58:26 -0300168
169 tda18271_i2c_gate_ctrl(fe, 0);
170
171 if (ret != 2)
172 tda_err("ERROR: i2c_transfer returned: %d\n", ret);
173
Adrian Bunk805d92d2008-01-28 22:12:41 -0300174 for (i = 0; i < TDA18271_NUM_REGS; i++) {
Michael Krufky59067f72008-01-02 01:58:26 -0300175 /* don't update write-only registers */
176 if ((i != R_EB9) &&
177 (i != R_EB16) &&
178 (i != R_EB17) &&
179 (i != R_EB19) &&
180 (i != R_EB20))
181 regs[i] = regdump[i];
182 }
183
184 if (tda18271_debug & DBG_REG)
185 tda18271_dump_regs(fe, 1);
186
187 return (ret == 2 ? 0 : ret);
188}
189
190int tda18271_write_regs(struct dvb_frontend *fe, int idx, int len)
191{
192 struct tda18271_priv *priv = fe->tuner_priv;
193 unsigned char *regs = priv->tda18271_regs;
194 unsigned char buf[TDA18271_NUM_REGS + 1];
Michael Krufkyf9e315a2008-04-22 14:41:54 -0300195 struct i2c_msg msg = { .addr = priv->i2c_props.addr, .flags = 0,
Michael Krufky59067f72008-01-02 01:58:26 -0300196 .buf = buf, .len = len + 1 };
197 int i, ret;
198
199 BUG_ON((len == 0) || (idx + len > sizeof(buf)));
200
201 buf[0] = idx;
202 for (i = 1; i <= len; i++)
203 buf[i] = regs[idx - 1 + i];
204
205 tda18271_i2c_gate_ctrl(fe, 1);
206
207 /* write registers */
Michael Krufkyf9e315a2008-04-22 14:41:54 -0300208 ret = i2c_transfer(priv->i2c_props.adap, &msg, 1);
Michael Krufky59067f72008-01-02 01:58:26 -0300209
210 tda18271_i2c_gate_ctrl(fe, 0);
211
212 if (ret != 1)
213 tda_err("ERROR: i2c_transfer returned: %d\n", ret);
214
215 return (ret == 1 ? 0 : ret);
216}
217
218/*---------------------------------------------------------------------*/
219
220int tda18271_init_regs(struct dvb_frontend *fe)
221{
222 struct tda18271_priv *priv = fe->tuner_priv;
223 unsigned char *regs = priv->tda18271_regs;
224
225 tda_dbg("initializing registers for device @ %d-%04x\n",
Michael Krufkyf9e315a2008-04-22 14:41:54 -0300226 i2c_adapter_id(priv->i2c_props.adap),
227 priv->i2c_props.addr);
Michael Krufky59067f72008-01-02 01:58:26 -0300228
229 /* initialize registers */
230 switch (priv->id) {
231 case TDA18271HDC1:
232 regs[R_ID] = 0x83;
233 break;
234 case TDA18271HDC2:
235 regs[R_ID] = 0x84;
236 break;
237 };
238
239 regs[R_TM] = 0x08;
240 regs[R_PL] = 0x80;
241 regs[R_EP1] = 0xc6;
242 regs[R_EP2] = 0xdf;
243 regs[R_EP3] = 0x16;
244 regs[R_EP4] = 0x60;
245 regs[R_EP5] = 0x80;
246 regs[R_CPD] = 0x80;
247 regs[R_CD1] = 0x00;
248 regs[R_CD2] = 0x00;
249 regs[R_CD3] = 0x00;
250 regs[R_MPD] = 0x00;
251 regs[R_MD1] = 0x00;
252 regs[R_MD2] = 0x00;
253 regs[R_MD3] = 0x00;
254
255 switch (priv->id) {
256 case TDA18271HDC1:
257 regs[R_EB1] = 0xff;
258 break;
259 case TDA18271HDC2:
260 regs[R_EB1] = 0xfc;
261 break;
262 };
263
264 regs[R_EB2] = 0x01;
265 regs[R_EB3] = 0x84;
266 regs[R_EB4] = 0x41;
267 regs[R_EB5] = 0x01;
268 regs[R_EB6] = 0x84;
269 regs[R_EB7] = 0x40;
270 regs[R_EB8] = 0x07;
271 regs[R_EB9] = 0x00;
272 regs[R_EB10] = 0x00;
273 regs[R_EB11] = 0x96;
274
275 switch (priv->id) {
276 case TDA18271HDC1:
277 regs[R_EB12] = 0x0f;
278 break;
279 case TDA18271HDC2:
280 regs[R_EB12] = 0x33;
281 break;
282 };
283
284 regs[R_EB13] = 0xc1;
285 regs[R_EB14] = 0x00;
286 regs[R_EB15] = 0x8f;
287 regs[R_EB16] = 0x00;
288 regs[R_EB17] = 0x00;
289
290 switch (priv->id) {
291 case TDA18271HDC1:
292 regs[R_EB18] = 0x00;
293 break;
294 case TDA18271HDC2:
295 regs[R_EB18] = 0x8c;
296 break;
297 };
298
299 regs[R_EB19] = 0x00;
300 regs[R_EB20] = 0x20;
301
302 switch (priv->id) {
303 case TDA18271HDC1:
304 regs[R_EB21] = 0x33;
305 break;
306 case TDA18271HDC2:
307 regs[R_EB21] = 0xb3;
308 break;
309 };
310
311 regs[R_EB22] = 0x48;
312 regs[R_EB23] = 0xb0;
313
Michael Krufky55553092008-04-22 14:46:06 -0300314 if (priv->small_i2c) {
315 tda18271_write_regs(fe, 0x00, 0x10);
316 tda18271_write_regs(fe, 0x10, 0x10);
317 tda18271_write_regs(fe, 0x20, 0x07);
318 } else
319 tda18271_write_regs(fe, 0x00, TDA18271_NUM_REGS);
Michael Krufky59067f72008-01-02 01:58:26 -0300320
321 /* setup agc1 gain */
322 regs[R_EB17] = 0x00;
323 tda18271_write_regs(fe, R_EB17, 1);
324 regs[R_EB17] = 0x03;
325 tda18271_write_regs(fe, R_EB17, 1);
326 regs[R_EB17] = 0x43;
327 tda18271_write_regs(fe, R_EB17, 1);
328 regs[R_EB17] = 0x4c;
329 tda18271_write_regs(fe, R_EB17, 1);
330
331 /* setup agc2 gain */
332 if ((priv->id) == TDA18271HDC1) {
333 regs[R_EB20] = 0xa0;
334 tda18271_write_regs(fe, R_EB20, 1);
335 regs[R_EB20] = 0xa7;
336 tda18271_write_regs(fe, R_EB20, 1);
337 regs[R_EB20] = 0xe7;
338 tda18271_write_regs(fe, R_EB20, 1);
339 regs[R_EB20] = 0xec;
340 tda18271_write_regs(fe, R_EB20, 1);
341 }
342
343 /* image rejection calibration */
344
345 /* low-band */
346 regs[R_EP3] = 0x1f;
347 regs[R_EP4] = 0x66;
348 regs[R_EP5] = 0x81;
349 regs[R_CPD] = 0xcc;
350 regs[R_CD1] = 0x6c;
351 regs[R_CD2] = 0x00;
352 regs[R_CD3] = 0x00;
353 regs[R_MPD] = 0xcd;
354 regs[R_MD1] = 0x77;
355 regs[R_MD2] = 0x08;
356 regs[R_MD3] = 0x00;
357
358 switch (priv->id) {
359 case TDA18271HDC1:
360 tda18271_write_regs(fe, R_EP3, 11);
361 break;
362 case TDA18271HDC2:
363 tda18271_write_regs(fe, R_EP3, 12);
364 break;
365 };
366
367 if ((priv->id) == TDA18271HDC2) {
368 /* main pll cp source on */
369 regs[R_EB4] = 0x61;
370 tda18271_write_regs(fe, R_EB4, 1);
371 msleep(1);
372
373 /* main pll cp source off */
374 regs[R_EB4] = 0x41;
375 tda18271_write_regs(fe, R_EB4, 1);
376 }
377
378 msleep(5); /* pll locking */
379
380 /* launch detector */
381 tda18271_write_regs(fe, R_EP1, 1);
382 msleep(5); /* wanted low measurement */
383
384 regs[R_EP5] = 0x85;
385 regs[R_CPD] = 0xcb;
386 regs[R_CD1] = 0x66;
387 regs[R_CD2] = 0x70;
388
389 tda18271_write_regs(fe, R_EP3, 7);
390 msleep(5); /* pll locking */
391
392 /* launch optimization algorithm */
393 tda18271_write_regs(fe, R_EP2, 1);
394 msleep(30); /* image low optimization completion */
395
396 /* mid-band */
397 regs[R_EP5] = 0x82;
398 regs[R_CPD] = 0xa8;
399 regs[R_CD2] = 0x00;
400 regs[R_MPD] = 0xa9;
401 regs[R_MD1] = 0x73;
402 regs[R_MD2] = 0x1a;
403
404 tda18271_write_regs(fe, R_EP3, 11);
405 msleep(5); /* pll locking */
406
407 tda18271_write_regs(fe, R_EP1, 1);
408 msleep(5); /* wanted mid measurement */
409
410 regs[R_EP5] = 0x86;
411 regs[R_CPD] = 0xa8;
412 regs[R_CD1] = 0x66;
413 regs[R_CD2] = 0xa0;
414
415 tda18271_write_regs(fe, R_EP3, 7);
416 msleep(5); /* pll locking */
417
418 /* launch optimization algorithm */
419 tda18271_write_regs(fe, R_EP2, 1);
420 msleep(30); /* image mid optimization completion */
421
422 /* high-band */
423 regs[R_EP5] = 0x83;
424 regs[R_CPD] = 0x98;
425 regs[R_CD1] = 0x65;
426 regs[R_CD2] = 0x00;
427 regs[R_MPD] = 0x99;
428 regs[R_MD1] = 0x71;
429 regs[R_MD2] = 0xcd;
430
431 tda18271_write_regs(fe, R_EP3, 11);
432 msleep(5); /* pll locking */
433
434 /* launch detector */
435 tda18271_write_regs(fe, R_EP1, 1);
436 msleep(5); /* wanted high measurement */
437
438 regs[R_EP5] = 0x87;
439 regs[R_CD1] = 0x65;
440 regs[R_CD2] = 0x50;
441
442 tda18271_write_regs(fe, R_EP3, 7);
443 msleep(5); /* pll locking */
444
445 /* launch optimization algorithm */
446 tda18271_write_regs(fe, R_EP2, 1);
447 msleep(30); /* image high optimization completion */
448
449 /* return to normal mode */
450 regs[R_EP4] = 0x64;
451 tda18271_write_regs(fe, R_EP4, 1);
452
453 /* synchronize */
454 tda18271_write_regs(fe, R_EP1, 1);
455
456 return 0;
457}
458
459/*---------------------------------------------------------------------*/
460
Michael Krufky518d8732008-01-13 17:01:01 -0300461/*
462 * Standby modes, EP3 [7:5]
463 *
464 * | SM || SM_LT || SM_XT || mode description
465 * |=====\\=======\\=======\\===================================
466 * | 0 || 0 || 0 || normal mode
467 * |-----||-------||-------||-----------------------------------
468 * | || || || standby mode w/ slave tuner output
469 * | 1 || 0 || 0 || & loop thru & xtal oscillator on
470 * |-----||-------||-------||-----------------------------------
471 * | 1 || 1 || 0 || standby mode w/ xtal oscillator on
472 * |-----||-------||-------||-----------------------------------
473 * | 1 || 1 || 1 || power off
474 *
475 */
476
477int tda18271_set_standby_mode(struct dvb_frontend *fe,
478 int sm, int sm_lt, int sm_xt)
479{
480 struct tda18271_priv *priv = fe->tuner_priv;
481 unsigned char *regs = priv->tda18271_regs;
482
483 tda_dbg("sm = %d, sm_lt = %d, sm_xt = %d\n", sm, sm_lt, sm_xt);
484
485 regs[R_EP3] &= ~0xe0; /* clear sm, sm_lt, sm_xt */
486 regs[R_EP3] |= sm ? (1 << 7) : 0 |
487 sm_lt ? (1 << 6) : 0 |
488 sm_xt ? (1 << 5) : 0;
489
490 tda18271_write_regs(fe, R_EP3, 1);
491
492 return 0;
493}
494
495/*---------------------------------------------------------------------*/
496
Michael Krufky59067f72008-01-02 01:58:26 -0300497int tda18271_calc_main_pll(struct dvb_frontend *fe, u32 freq)
498{
499 /* sets main post divider & divider bytes, but does not write them */
500 struct tda18271_priv *priv = fe->tuner_priv;
501 unsigned char *regs = priv->tda18271_regs;
502 u8 d, pd;
503 u32 div;
504
505 int ret = tda18271_lookup_pll_map(fe, MAIN_PLL, &freq, &pd, &d);
506 if (ret < 0)
507 goto fail;
508
509 regs[R_MPD] = (0x77 & pd);
510
511 switch (priv->mode) {
512 case TDA18271_ANALOG:
513 regs[R_MPD] &= ~0x08;
514 break;
515 case TDA18271_DIGITAL:
516 regs[R_MPD] |= 0x08;
517 break;
518 }
519
520 div = ((d * (freq / 1000)) << 7) / 125;
521
522 regs[R_MD1] = 0x7f & (div >> 16);
523 regs[R_MD2] = 0xff & (div >> 8);
524 regs[R_MD3] = 0xff & div;
525fail:
526 return ret;
527}
528
529int tda18271_calc_cal_pll(struct dvb_frontend *fe, u32 freq)
530{
531 /* sets cal post divider & divider bytes, but does not write them */
532 struct tda18271_priv *priv = fe->tuner_priv;
533 unsigned char *regs = priv->tda18271_regs;
534 u8 d, pd;
535 u32 div;
536
537 int ret = tda18271_lookup_pll_map(fe, CAL_PLL, &freq, &pd, &d);
538 if (ret < 0)
539 goto fail;
540
541 regs[R_CPD] = pd;
542
543 div = ((d * (freq / 1000)) << 7) / 125;
544
545 regs[R_CD1] = 0x7f & (div >> 16);
546 regs[R_CD2] = 0xff & (div >> 8);
547 regs[R_CD3] = 0xff & div;
548fail:
549 return ret;
550}
551
552/*---------------------------------------------------------------------*/
553
554int tda18271_calc_bp_filter(struct dvb_frontend *fe, u32 *freq)
555{
556 /* sets bp filter bits, but does not write them */
557 struct tda18271_priv *priv = fe->tuner_priv;
558 unsigned char *regs = priv->tda18271_regs;
559 u8 val;
560
561 int ret = tda18271_lookup_map(fe, BP_FILTER, freq, &val);
562 if (ret < 0)
563 goto fail;
564
565 regs[R_EP1] &= ~0x07; /* clear bp filter bits */
566 regs[R_EP1] |= (0x07 & val);
567fail:
568 return ret;
569}
570
571int tda18271_calc_km(struct dvb_frontend *fe, u32 *freq)
572{
573 /* sets K & M bits, but does not write them */
574 struct tda18271_priv *priv = fe->tuner_priv;
575 unsigned char *regs = priv->tda18271_regs;
576 u8 val;
577
578 int ret = tda18271_lookup_map(fe, RF_CAL_KMCO, freq, &val);
579 if (ret < 0)
580 goto fail;
581
582 regs[R_EB13] &= ~0x7c; /* clear k & m bits */
583 regs[R_EB13] |= (0x7c & val);
584fail:
585 return ret;
586}
587
588int tda18271_calc_rf_band(struct dvb_frontend *fe, u32 *freq)
589{
590 /* sets rf band bits, but does not write them */
591 struct tda18271_priv *priv = fe->tuner_priv;
592 unsigned char *regs = priv->tda18271_regs;
593 u8 val;
594
595 int ret = tda18271_lookup_map(fe, RF_BAND, freq, &val);
596 if (ret < 0)
597 goto fail;
598
599 regs[R_EP2] &= ~0xe0; /* clear rf band bits */
600 regs[R_EP2] |= (0xe0 & (val << 5));
601fail:
602 return ret;
603}
604
605int tda18271_calc_gain_taper(struct dvb_frontend *fe, u32 *freq)
606{
607 /* sets gain taper bits, but does not write them */
608 struct tda18271_priv *priv = fe->tuner_priv;
609 unsigned char *regs = priv->tda18271_regs;
610 u8 val;
611
612 int ret = tda18271_lookup_map(fe, GAIN_TAPER, freq, &val);
613 if (ret < 0)
614 goto fail;
615
616 regs[R_EP2] &= ~0x1f; /* clear gain taper bits */
617 regs[R_EP2] |= (0x1f & val);
618fail:
619 return ret;
620}
621
622int tda18271_calc_ir_measure(struct dvb_frontend *fe, u32 *freq)
623{
624 /* sets IR Meas bits, but does not write them */
625 struct tda18271_priv *priv = fe->tuner_priv;
626 unsigned char *regs = priv->tda18271_regs;
627 u8 val;
628
629 int ret = tda18271_lookup_map(fe, IR_MEASURE, freq, &val);
630 if (ret < 0)
631 goto fail;
632
633 regs[R_EP5] &= ~0x07;
634 regs[R_EP5] |= (0x07 & val);
635fail:
636 return ret;
637}
638
639int tda18271_calc_rf_cal(struct dvb_frontend *fe, u32 *freq)
640{
641 /* sets rf cal byte (RFC_Cprog), but does not write it */
642 struct tda18271_priv *priv = fe->tuner_priv;
643 unsigned char *regs = priv->tda18271_regs;
644 u8 val;
645
Michael Krufkyd2c932a2008-01-05 15:42:54 -0300646 tda18271_lookup_map(fe, RF_CAL, freq, &val);
Michael Krufky59067f72008-01-02 01:58:26 -0300647
648 regs[R_EB14] = val;
Michael Krufkyd2c932a2008-01-05 15:42:54 -0300649
650 return 0;
Michael Krufky59067f72008-01-02 01:58:26 -0300651}
652
653/*
654 * Overrides for Emacs so that we follow Linus's tabbing style.
655 * ---------------------------------------------------------------------------
656 * Local variables:
657 * c-basic-offset: 8
658 * End:
659 */