Kalle Valo | 2f01a1f | 2009-04-29 23:33:31 +0300 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of wl12xx |
| 3 | * |
| 4 | * Copyright (c) 1998-2007 Texas Instruments Incorporated |
| 5 | * Copyright (C) 2008-2009 Nokia Corporation |
| 6 | * |
| 7 | * Contact: Kalle Valo <kalle.valo@nokia.com> |
| 8 | * |
| 9 | * This program is free software; you can redistribute it and/or |
| 10 | * modify it under the terms of the GNU General Public License |
| 11 | * version 2 as published by the Free Software Foundation. |
| 12 | * |
| 13 | * This program is distributed in the hope that it will be useful, but |
| 14 | * WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
| 16 | * General Public License for more details. |
| 17 | * |
| 18 | * You should have received a copy of the GNU General Public License |
| 19 | * along with this program; if not, write to the Free Software |
| 20 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA |
| 21 | * 02110-1301 USA |
| 22 | * |
| 23 | */ |
| 24 | |
| 25 | #ifndef __WL12XX_H__ |
| 26 | #define __WL12XX_H__ |
| 27 | |
| 28 | #include <linux/mutex.h> |
| 29 | #include <linux/list.h> |
| 30 | #include <linux/bitops.h> |
| 31 | #include <net/mac80211.h> |
| 32 | |
| 33 | #define DRIVER_NAME "wl12xx" |
| 34 | #define DRIVER_PREFIX DRIVER_NAME ": " |
| 35 | |
| 36 | enum { |
| 37 | DEBUG_NONE = 0, |
| 38 | DEBUG_IRQ = BIT(0), |
| 39 | DEBUG_SPI = BIT(1), |
| 40 | DEBUG_BOOT = BIT(2), |
| 41 | DEBUG_MAILBOX = BIT(3), |
| 42 | DEBUG_NETLINK = BIT(4), |
| 43 | DEBUG_EVENT = BIT(5), |
| 44 | DEBUG_TX = BIT(6), |
| 45 | DEBUG_RX = BIT(7), |
| 46 | DEBUG_SCAN = BIT(8), |
| 47 | DEBUG_CRYPT = BIT(9), |
| 48 | DEBUG_PSM = BIT(10), |
| 49 | DEBUG_MAC80211 = BIT(11), |
| 50 | DEBUG_CMD = BIT(12), |
| 51 | DEBUG_ACX = BIT(13), |
| 52 | DEBUG_ALL = ~0, |
| 53 | }; |
| 54 | |
| 55 | #define DEBUG_LEVEL (DEBUG_NONE) |
| 56 | |
| 57 | #define DEBUG_DUMP_LIMIT 1024 |
| 58 | |
| 59 | #define wl12xx_error(fmt, arg...) \ |
| 60 | printk(KERN_ERR DRIVER_PREFIX "ERROR " fmt "\n", ##arg) |
| 61 | |
| 62 | #define wl12xx_warning(fmt, arg...) \ |
| 63 | printk(KERN_WARNING DRIVER_PREFIX "WARNING " fmt "\n", ##arg) |
| 64 | |
| 65 | #define wl12xx_notice(fmt, arg...) \ |
| 66 | printk(KERN_INFO DRIVER_PREFIX fmt "\n", ##arg) |
| 67 | |
| 68 | #define wl12xx_info(fmt, arg...) \ |
| 69 | printk(KERN_DEBUG DRIVER_PREFIX fmt "\n", ##arg) |
| 70 | |
| 71 | #define wl12xx_debug(level, fmt, arg...) \ |
| 72 | do { \ |
| 73 | if (level & DEBUG_LEVEL) \ |
| 74 | printk(KERN_DEBUG DRIVER_PREFIX fmt "\n", ##arg); \ |
| 75 | } while (0) |
| 76 | |
| 77 | #define wl12xx_dump(level, prefix, buf, len) \ |
| 78 | do { \ |
| 79 | if (level & DEBUG_LEVEL) \ |
| 80 | print_hex_dump(KERN_DEBUG, DRIVER_PREFIX prefix, \ |
| 81 | DUMP_PREFIX_OFFSET, 16, 1, \ |
| 82 | buf, \ |
| 83 | min_t(size_t, len, DEBUG_DUMP_LIMIT), \ |
| 84 | 0); \ |
| 85 | } while (0) |
| 86 | |
| 87 | #define wl12xx_dump_ascii(level, prefix, buf, len) \ |
| 88 | do { \ |
| 89 | if (level & DEBUG_LEVEL) \ |
| 90 | print_hex_dump(KERN_DEBUG, DRIVER_PREFIX prefix, \ |
| 91 | DUMP_PREFIX_OFFSET, 16, 1, \ |
| 92 | buf, \ |
| 93 | min_t(size_t, len, DEBUG_DUMP_LIMIT), \ |
| 94 | true); \ |
| 95 | } while (0) |
| 96 | |
| 97 | #define WL12XX_DEFAULT_RX_CONFIG (CFG_UNI_FILTER_EN | \ |
| 98 | CFG_BSSID_FILTER_EN) |
| 99 | |
| 100 | #define WL12XX_DEFAULT_RX_FILTER (CFG_RX_PRSP_EN | \ |
| 101 | CFG_RX_MGMT_EN | \ |
| 102 | CFG_RX_DATA_EN | \ |
| 103 | CFG_RX_CTL_EN | \ |
| 104 | CFG_RX_BCN_EN | \ |
| 105 | CFG_RX_AUTH_EN | \ |
| 106 | CFG_RX_ASSOC_EN) |
| 107 | |
| 108 | |
| 109 | struct boot_attr { |
| 110 | u32 radio_type; |
| 111 | u8 mac_clock; |
| 112 | u8 arm_clock; |
| 113 | int firmware_debug; |
| 114 | u32 minor; |
| 115 | u32 major; |
| 116 | u32 bugfix; |
| 117 | }; |
| 118 | |
| 119 | enum wl12xx_state { |
| 120 | WL12XX_STATE_OFF, |
| 121 | WL12XX_STATE_ON, |
| 122 | WL12XX_STATE_PLT, |
| 123 | }; |
| 124 | |
| 125 | enum wl12xx_partition_type { |
| 126 | PART_DOWN, |
| 127 | PART_WORK, |
| 128 | PART_DRPW, |
| 129 | |
| 130 | PART_TABLE_LEN |
| 131 | }; |
| 132 | |
| 133 | struct wl12xx_partition { |
| 134 | u32 size; |
| 135 | u32 start; |
| 136 | }; |
| 137 | |
| 138 | struct wl12xx_partition_set { |
| 139 | struct wl12xx_partition mem; |
| 140 | struct wl12xx_partition reg; |
| 141 | }; |
| 142 | |
| 143 | struct wl12xx; |
| 144 | |
| 145 | /* FIXME: I'm not sure about this structure name */ |
| 146 | struct wl12xx_chip { |
| 147 | u32 id; |
| 148 | |
| 149 | const char *fw_filename; |
| 150 | const char *nvs_filename; |
| 151 | |
| 152 | char fw_ver[21]; |
| 153 | |
| 154 | unsigned int power_on_sleep; |
| 155 | int intr_cmd_complete; |
| 156 | int intr_init_complete; |
| 157 | |
| 158 | int (*op_upload_fw)(struct wl12xx *wl); |
| 159 | int (*op_upload_nvs)(struct wl12xx *wl); |
| 160 | int (*op_boot)(struct wl12xx *wl); |
| 161 | void (*op_set_ecpu_ctrl)(struct wl12xx *wl, u32 flag); |
| 162 | void (*op_target_enable_interrupts)(struct wl12xx *wl); |
| 163 | int (*op_hw_init)(struct wl12xx *wl); |
| 164 | int (*op_plt_init)(struct wl12xx *wl); |
| 165 | |
| 166 | struct wl12xx_partition_set *p_table; |
| 167 | enum wl12xx_acx_int_reg *acx_reg_table; |
| 168 | }; |
| 169 | |
| 170 | struct wl12xx_stats { |
| 171 | struct acx_statistics *fw_stats; |
| 172 | unsigned long fw_stats_update; |
| 173 | |
| 174 | unsigned int retry_count; |
| 175 | unsigned int excessive_retries; |
| 176 | }; |
| 177 | |
| 178 | struct wl12xx_debugfs { |
| 179 | struct dentry *rootdir; |
| 180 | struct dentry *fw_statistics; |
| 181 | |
| 182 | struct dentry *tx_internal_desc_overflow; |
| 183 | |
| 184 | struct dentry *rx_out_of_mem; |
| 185 | struct dentry *rx_hdr_overflow; |
| 186 | struct dentry *rx_hw_stuck; |
| 187 | struct dentry *rx_dropped; |
| 188 | struct dentry *rx_fcs_err; |
| 189 | struct dentry *rx_xfr_hint_trig; |
| 190 | struct dentry *rx_path_reset; |
| 191 | struct dentry *rx_reset_counter; |
| 192 | |
| 193 | struct dentry *dma_rx_requested; |
| 194 | struct dentry *dma_rx_errors; |
| 195 | struct dentry *dma_tx_requested; |
| 196 | struct dentry *dma_tx_errors; |
| 197 | |
| 198 | struct dentry *isr_cmd_cmplt; |
| 199 | struct dentry *isr_fiqs; |
| 200 | struct dentry *isr_rx_headers; |
| 201 | struct dentry *isr_rx_mem_overflow; |
| 202 | struct dentry *isr_rx_rdys; |
| 203 | struct dentry *isr_irqs; |
| 204 | struct dentry *isr_tx_procs; |
| 205 | struct dentry *isr_decrypt_done; |
| 206 | struct dentry *isr_dma0_done; |
| 207 | struct dentry *isr_dma1_done; |
| 208 | struct dentry *isr_tx_exch_complete; |
| 209 | struct dentry *isr_commands; |
| 210 | struct dentry *isr_rx_procs; |
| 211 | struct dentry *isr_hw_pm_mode_changes; |
| 212 | struct dentry *isr_host_acknowledges; |
| 213 | struct dentry *isr_pci_pm; |
| 214 | struct dentry *isr_wakeups; |
| 215 | struct dentry *isr_low_rssi; |
| 216 | |
| 217 | struct dentry *wep_addr_key_count; |
| 218 | struct dentry *wep_default_key_count; |
| 219 | /* skipping wep.reserved */ |
| 220 | struct dentry *wep_key_not_found; |
| 221 | struct dentry *wep_decrypt_fail; |
| 222 | struct dentry *wep_packets; |
| 223 | struct dentry *wep_interrupt; |
| 224 | |
| 225 | struct dentry *pwr_ps_enter; |
| 226 | struct dentry *pwr_elp_enter; |
| 227 | struct dentry *pwr_missing_bcns; |
| 228 | struct dentry *pwr_wake_on_host; |
| 229 | struct dentry *pwr_wake_on_timer_exp; |
| 230 | struct dentry *pwr_tx_with_ps; |
| 231 | struct dentry *pwr_tx_without_ps; |
| 232 | struct dentry *pwr_rcvd_beacons; |
| 233 | struct dentry *pwr_power_save_off; |
| 234 | struct dentry *pwr_enable_ps; |
| 235 | struct dentry *pwr_disable_ps; |
| 236 | struct dentry *pwr_fix_tsf_ps; |
| 237 | /* skipping cont_miss_bcns_spread for now */ |
| 238 | struct dentry *pwr_rcvd_awake_beacons; |
| 239 | |
| 240 | struct dentry *mic_rx_pkts; |
| 241 | struct dentry *mic_calc_failure; |
| 242 | |
| 243 | struct dentry *aes_encrypt_fail; |
| 244 | struct dentry *aes_decrypt_fail; |
| 245 | struct dentry *aes_encrypt_packets; |
| 246 | struct dentry *aes_decrypt_packets; |
| 247 | struct dentry *aes_encrypt_interrupt; |
| 248 | struct dentry *aes_decrypt_interrupt; |
| 249 | |
| 250 | struct dentry *event_heart_beat; |
| 251 | struct dentry *event_calibration; |
| 252 | struct dentry *event_rx_mismatch; |
| 253 | struct dentry *event_rx_mem_empty; |
| 254 | struct dentry *event_rx_pool; |
| 255 | struct dentry *event_oom_late; |
| 256 | struct dentry *event_phy_transmit_error; |
| 257 | struct dentry *event_tx_stuck; |
| 258 | |
| 259 | struct dentry *ps_pspoll_timeouts; |
| 260 | struct dentry *ps_upsd_timeouts; |
| 261 | struct dentry *ps_upsd_max_sptime; |
| 262 | struct dentry *ps_upsd_max_apturn; |
| 263 | struct dentry *ps_pspoll_max_apturn; |
| 264 | struct dentry *ps_pspoll_utilization; |
| 265 | struct dentry *ps_upsd_utilization; |
| 266 | |
| 267 | struct dentry *rxpipe_rx_prep_beacon_drop; |
| 268 | struct dentry *rxpipe_descr_host_int_trig_rx_data; |
| 269 | struct dentry *rxpipe_beacon_buffer_thres_host_int_trig_rx_data; |
| 270 | struct dentry *rxpipe_missed_beacon_host_int_trig_rx_data; |
| 271 | struct dentry *rxpipe_tx_xfr_host_int_trig_rx_data; |
| 272 | |
| 273 | struct dentry *tx_queue_len; |
| 274 | |
| 275 | struct dentry *retry_count; |
| 276 | struct dentry *excessive_retries; |
| 277 | }; |
| 278 | |
| 279 | struct wl12xx { |
| 280 | struct ieee80211_hw *hw; |
| 281 | bool mac80211_registered; |
| 282 | |
| 283 | struct spi_device *spi; |
| 284 | |
| 285 | void (*set_power)(bool enable); |
| 286 | int irq; |
| 287 | |
| 288 | enum wl12xx_state state; |
| 289 | struct mutex mutex; |
| 290 | |
| 291 | int physical_mem_addr; |
| 292 | int physical_reg_addr; |
| 293 | int virtual_mem_addr; |
| 294 | int virtual_reg_addr; |
| 295 | |
| 296 | struct wl12xx_chip chip; |
| 297 | |
| 298 | int cmd_box_addr; |
| 299 | int event_box_addr; |
| 300 | struct boot_attr boot_attr; |
| 301 | |
| 302 | u8 *fw; |
| 303 | size_t fw_len; |
| 304 | u8 *nvs; |
| 305 | size_t nvs_len; |
| 306 | |
| 307 | u8 bssid[ETH_ALEN]; |
| 308 | u8 mac_addr[ETH_ALEN]; |
| 309 | u8 bss_type; |
| 310 | u8 listen_int; |
| 311 | int channel; |
| 312 | |
| 313 | void *target_mem_map; |
| 314 | struct acx_data_path_params_resp *data_path; |
| 315 | |
| 316 | /* Number of TX packets transferred to the FW, modulo 16 */ |
| 317 | u32 data_in_count; |
| 318 | |
| 319 | /* Frames scheduled for transmission, not handled yet */ |
| 320 | struct sk_buff_head tx_queue; |
| 321 | bool tx_queue_stopped; |
| 322 | |
| 323 | struct work_struct tx_work; |
| 324 | struct work_struct filter_work; |
| 325 | |
| 326 | /* Pending TX frames */ |
| 327 | struct sk_buff *tx_frames[16]; |
| 328 | |
| 329 | /* |
| 330 | * Index pointing to the next TX complete entry |
| 331 | * in the cyclic XT complete array we get from |
| 332 | * the FW. |
| 333 | */ |
| 334 | u32 next_tx_complete; |
| 335 | |
| 336 | /* FW Rx counter */ |
| 337 | u32 rx_counter; |
| 338 | |
| 339 | /* Rx frames handled */ |
| 340 | u32 rx_handled; |
| 341 | |
| 342 | /* Current double buffer */ |
| 343 | u32 rx_current_buffer; |
| 344 | u32 rx_last_id; |
| 345 | |
| 346 | /* The target interrupt mask */ |
| 347 | u32 intr_mask; |
| 348 | struct work_struct irq_work; |
| 349 | |
| 350 | /* The mbox event mask */ |
| 351 | u32 event_mask; |
| 352 | |
| 353 | /* Mailbox pointers */ |
| 354 | u32 mbox_ptr[2]; |
| 355 | |
| 356 | /* Are we currently scanning */ |
| 357 | bool scanning; |
| 358 | |
| 359 | /* Our association ID */ |
| 360 | u16 aid; |
| 361 | |
| 362 | /* Default key (for WEP) */ |
| 363 | u32 default_key; |
| 364 | |
| 365 | unsigned int tx_mgmt_frm_rate; |
| 366 | unsigned int tx_mgmt_frm_mod; |
| 367 | |
| 368 | unsigned int rx_config; |
| 369 | unsigned int rx_filter; |
| 370 | |
| 371 | /* is firmware in elp mode */ |
| 372 | bool elp; |
| 373 | |
| 374 | /* we can be in psm, but not in elp, we have to differentiate */ |
| 375 | bool psm; |
| 376 | |
| 377 | /* PSM mode requested */ |
| 378 | bool psm_requested; |
| 379 | |
| 380 | /* in dBm */ |
| 381 | int power_level; |
| 382 | |
| 383 | struct wl12xx_stats stats; |
| 384 | struct wl12xx_debugfs debugfs; |
Kalle Valo | 1d3b813 | 2009-06-12 14:14:28 +0300 | [diff] [blame] | 385 | |
| 386 | u32 buffer_32; |
Kalle Valo | 56343a3 | 2009-06-12 14:14:47 +0300 | [diff] [blame^] | 387 | u32 buffer_cmd; |
Kalle Valo | 2f01a1f | 2009-04-29 23:33:31 +0300 | [diff] [blame] | 388 | }; |
| 389 | |
| 390 | int wl12xx_plt_start(struct wl12xx *wl); |
| 391 | int wl12xx_plt_stop(struct wl12xx *wl); |
| 392 | |
| 393 | #define DEFAULT_HW_GEN_MODULATION_TYPE CCK_LONG /* Long Preamble */ |
| 394 | #define DEFAULT_HW_GEN_TX_RATE RATE_2MBPS |
| 395 | #define JOIN_TIMEOUT 5000 /* 5000 milliseconds to join */ |
| 396 | |
| 397 | #define WL12XX_DEFAULT_POWER_LEVEL 20 |
| 398 | |
| 399 | #define WL12XX_TX_QUEUE_MAX_LENGTH 20 |
| 400 | |
| 401 | /* Different chips need different sleep times after power on. WL1271 needs |
| 402 | * 200ms, WL1251 needs only 10ms. By default we use 200ms, but as soon as we |
| 403 | * know the chip ID, we change the sleep value in the wl12xx chip structure, |
| 404 | * so in subsequent power ons, we don't waste more time then needed. */ |
| 405 | #define WL12XX_DEFAULT_POWER_ON_SLEEP 200 |
| 406 | |
| 407 | #define CHIP_ID_1251_PG10 (0x7010101) |
| 408 | #define CHIP_ID_1251_PG11 (0x7020101) |
| 409 | #define CHIP_ID_1251_PG12 (0x7030101) |
| 410 | #define CHIP_ID_1271_PG10 (0x4030101) |
| 411 | |
| 412 | #endif |