blob: d16eb70bf5b55c0af92cee8e236a15648310608b [file] [log] [blame]
Tomi Valkeinen80c39712009-11-12 11:41:42 +02001/*
2 * linux/drivers/video/omap2/dss/dispc.c
3 *
4 * Copyright (C) 2009 Nokia Corporation
5 * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
6 *
7 * Some code and ideas taken from drivers/video/omap/ driver
8 * by Imre Deak.
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License version 2 as published by
12 * the Free Software Foundation.
13 *
14 * This program is distributed in the hope that it will be useful, but WITHOUT
15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17 * more details.
18 *
19 * You should have received a copy of the GNU General Public License along with
20 * this program. If not, see <http://www.gnu.org/licenses/>.
21 */
22
23#define DSS_SUBSYS_NAME "DISPC"
24
25#include <linux/kernel.h>
26#include <linux/dma-mapping.h>
27#include <linux/vmalloc.h>
28#include <linux/clk.h>
29#include <linux/io.h>
30#include <linux/jiffies.h>
31#include <linux/seq_file.h>
32#include <linux/delay.h>
33#include <linux/workqueue.h>
Tomi Valkeinenab83b142010-06-09 15:31:01 +030034#include <linux/hardirq.h>
archit tanejaaffe3602011-02-23 08:41:03 +000035#include <linux/interrupt.h>
Tomi Valkeinen80c39712009-11-12 11:41:42 +020036
37#include <plat/sram.h>
38#include <plat/clock.h>
39
Tomi Valkeinena0b38cc2011-05-11 14:05:07 +030040#include <video/omapdss.h>
Tomi Valkeinen80c39712009-11-12 11:41:42 +020041
42#include "dss.h"
Archit Tanejaa0acb552010-09-15 19:20:00 +053043#include "dss_features.h"
Archit Taneja9b372c22011-05-06 11:45:49 +053044#include "dispc.h"
Tomi Valkeinen80c39712009-11-12 11:41:42 +020045
46/* DISPC */
Sumit Semwal8613b002010-12-02 11:27:09 +000047#define DISPC_SZ_REGS SZ_4K
Tomi Valkeinen80c39712009-11-12 11:41:42 +020048
Tomi Valkeinen80c39712009-11-12 11:41:42 +020049#define DISPC_IRQ_MASK_ERROR (DISPC_IRQ_GFX_FIFO_UNDERFLOW | \
50 DISPC_IRQ_OCP_ERR | \
51 DISPC_IRQ_VID1_FIFO_UNDERFLOW | \
52 DISPC_IRQ_VID2_FIFO_UNDERFLOW | \
53 DISPC_IRQ_SYNC_LOST | \
54 DISPC_IRQ_SYNC_LOST_DIGIT)
55
56#define DISPC_MAX_NR_ISRS 8
57
58struct omap_dispc_isr_data {
59 omap_dispc_isr_t isr;
60 void *arg;
61 u32 mask;
62};
63
Grazvydas Ignotas66be8f62010-08-24 15:18:43 +020064struct dispc_h_coef {
65 s8 hc4;
66 s8 hc3;
67 u8 hc2;
68 s8 hc1;
69 s8 hc0;
70};
71
72struct dispc_v_coef {
73 s8 vc22;
74 s8 vc2;
75 u8 vc1;
76 s8 vc0;
77 s8 vc00;
78};
79
Tomi Valkeinen80c39712009-11-12 11:41:42 +020080#define REG_GET(idx, start, end) \
81 FLD_GET(dispc_read_reg(idx), start, end)
82
83#define REG_FLD_MOD(idx, val, start, end) \
84 dispc_write_reg(idx, FLD_MOD(dispc_read_reg(idx), val, start, end))
85
Tomi Valkeinendfc0fd82009-12-17 14:35:21 +020086struct dispc_irq_stats {
87 unsigned long last_reset;
88 unsigned irq_count;
89 unsigned irqs[32];
90};
91
Tomi Valkeinen80c39712009-11-12 11:41:42 +020092static struct {
Senthilvadivu Guruswamy060b6d92011-01-24 06:22:00 +000093 struct platform_device *pdev;
Tomi Valkeinen80c39712009-11-12 11:41:42 +020094 void __iomem *base;
archit tanejaaffe3602011-02-23 08:41:03 +000095 int irq;
Tomi Valkeinen80c39712009-11-12 11:41:42 +020096
97 u32 fifo_size[3];
98
99 spinlock_t irq_lock;
100 u32 irq_error_mask;
101 struct omap_dispc_isr_data registered_isr[DISPC_MAX_NR_ISRS];
102 u32 error_irqs;
103 struct work_struct error_work;
104
105 u32 ctx[DISPC_SZ_REGS / sizeof(u32)];
Tomi Valkeinendfc0fd82009-12-17 14:35:21 +0200106
107#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
108 spinlock_t irq_stats_lock;
109 struct dispc_irq_stats irq_stats;
110#endif
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200111} dispc;
112
113static void _omap_dispc_set_irqs(void);
114
Archit Taneja55978cc2011-05-06 11:45:51 +0530115static inline void dispc_write_reg(const u16 idx, u32 val)
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200116{
Archit Taneja55978cc2011-05-06 11:45:51 +0530117 __raw_writel(val, dispc.base + idx);
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200118}
119
Archit Taneja55978cc2011-05-06 11:45:51 +0530120static inline u32 dispc_read_reg(const u16 idx)
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200121{
Archit Taneja55978cc2011-05-06 11:45:51 +0530122 return __raw_readl(dispc.base + idx);
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200123}
124
125#define SR(reg) \
Archit Taneja55978cc2011-05-06 11:45:51 +0530126 dispc.ctx[DISPC_##reg / sizeof(u32)] = dispc_read_reg(DISPC_##reg)
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200127#define RR(reg) \
Archit Taneja55978cc2011-05-06 11:45:51 +0530128 dispc_write_reg(DISPC_##reg, dispc.ctx[DISPC_##reg / sizeof(u32)])
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200129
130void dispc_save_context(void)
131{
Amber Jain5719d352011-05-19 19:47:52 +0530132 int i;
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200133 if (cpu_is_omap24xx())
134 return;
135
136 SR(SYSCONFIG);
137 SR(IRQENABLE);
138 SR(CONTROL);
139 SR(CONFIG);
Archit Taneja702d1442011-05-06 11:45:50 +0530140 SR(DEFAULT_COLOR(OMAP_DSS_CHANNEL_LCD));
141 SR(DEFAULT_COLOR(OMAP_DSS_CHANNEL_DIGIT));
142 SR(TRANS_COLOR(OMAP_DSS_CHANNEL_LCD));
143 SR(TRANS_COLOR(OMAP_DSS_CHANNEL_DIGIT));
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200144 SR(LINE_NUMBER);
Archit Taneja702d1442011-05-06 11:45:50 +0530145 SR(TIMING_H(OMAP_DSS_CHANNEL_LCD));
146 SR(TIMING_V(OMAP_DSS_CHANNEL_LCD));
147 SR(POL_FREQ(OMAP_DSS_CHANNEL_LCD));
148 SR(DIVISORo(OMAP_DSS_CHANNEL_LCD));
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200149 SR(GLOBAL_ALPHA);
Archit Taneja702d1442011-05-06 11:45:50 +0530150 SR(SIZE_MGR(OMAP_DSS_CHANNEL_DIGIT));
151 SR(SIZE_MGR(OMAP_DSS_CHANNEL_LCD));
Sumit Semwal2a205f32010-12-02 11:27:12 +0000152 if (dss_has_feature(FEAT_MGR_LCD2)) {
153 SR(CONTROL2);
Archit Taneja702d1442011-05-06 11:45:50 +0530154 SR(DEFAULT_COLOR(OMAP_DSS_CHANNEL_LCD2));
155 SR(TRANS_COLOR(OMAP_DSS_CHANNEL_LCD2));
156 SR(SIZE_MGR(OMAP_DSS_CHANNEL_LCD2));
157 SR(TIMING_H(OMAP_DSS_CHANNEL_LCD2));
158 SR(TIMING_V(OMAP_DSS_CHANNEL_LCD2));
159 SR(POL_FREQ(OMAP_DSS_CHANNEL_LCD2));
160 SR(DIVISORo(OMAP_DSS_CHANNEL_LCD2));
Sumit Semwal2a205f32010-12-02 11:27:12 +0000161 SR(CONFIG2);
162 }
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200163
Archit Taneja9b372c22011-05-06 11:45:49 +0530164 SR(OVL_BA0(OMAP_DSS_GFX));
165 SR(OVL_BA1(OMAP_DSS_GFX));
166 SR(OVL_POSITION(OMAP_DSS_GFX));
167 SR(OVL_SIZE(OMAP_DSS_GFX));
168 SR(OVL_ATTRIBUTES(OMAP_DSS_GFX));
169 SR(OVL_FIFO_THRESHOLD(OMAP_DSS_GFX));
170 SR(OVL_ROW_INC(OMAP_DSS_GFX));
171 SR(OVL_PIXEL_INC(OMAP_DSS_GFX));
172 SR(OVL_WINDOW_SKIP(OMAP_DSS_GFX));
173 SR(OVL_TABLE_BA(OMAP_DSS_GFX));
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200174
Archit Taneja702d1442011-05-06 11:45:50 +0530175 SR(DATA_CYCLE1(OMAP_DSS_CHANNEL_LCD));
176 SR(DATA_CYCLE2(OMAP_DSS_CHANNEL_LCD));
177 SR(DATA_CYCLE3(OMAP_DSS_CHANNEL_LCD));
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200178
Archit Taneja702d1442011-05-06 11:45:50 +0530179 SR(CPR_COEF_R(OMAP_DSS_CHANNEL_LCD));
180 SR(CPR_COEF_G(OMAP_DSS_CHANNEL_LCD));
181 SR(CPR_COEF_B(OMAP_DSS_CHANNEL_LCD));
Sumit Semwal2a205f32010-12-02 11:27:12 +0000182 if (dss_has_feature(FEAT_MGR_LCD2)) {
Archit Taneja702d1442011-05-06 11:45:50 +0530183 SR(CPR_COEF_B(OMAP_DSS_CHANNEL_LCD2));
184 SR(CPR_COEF_G(OMAP_DSS_CHANNEL_LCD2));
185 SR(CPR_COEF_R(OMAP_DSS_CHANNEL_LCD2));
Sumit Semwal2a205f32010-12-02 11:27:12 +0000186
Archit Taneja702d1442011-05-06 11:45:50 +0530187 SR(DATA_CYCLE1(OMAP_DSS_CHANNEL_LCD2));
188 SR(DATA_CYCLE2(OMAP_DSS_CHANNEL_LCD2));
189 SR(DATA_CYCLE3(OMAP_DSS_CHANNEL_LCD2));
Sumit Semwal2a205f32010-12-02 11:27:12 +0000190 }
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200191
Archit Taneja9b372c22011-05-06 11:45:49 +0530192 SR(OVL_PRELOAD(OMAP_DSS_GFX));
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200193
194 /* VID1 */
Archit Taneja9b372c22011-05-06 11:45:49 +0530195 SR(OVL_BA0(OMAP_DSS_VIDEO1));
196 SR(OVL_BA1(OMAP_DSS_VIDEO1));
197 SR(OVL_POSITION(OMAP_DSS_VIDEO1));
198 SR(OVL_SIZE(OMAP_DSS_VIDEO1));
199 SR(OVL_ATTRIBUTES(OMAP_DSS_VIDEO1));
200 SR(OVL_FIFO_THRESHOLD(OMAP_DSS_VIDEO1));
201 SR(OVL_ROW_INC(OMAP_DSS_VIDEO1));
202 SR(OVL_PIXEL_INC(OMAP_DSS_VIDEO1));
203 SR(OVL_FIR(OMAP_DSS_VIDEO1));
204 SR(OVL_PICTURE_SIZE(OMAP_DSS_VIDEO1));
205 SR(OVL_ACCU0(OMAP_DSS_VIDEO1));
206 SR(OVL_ACCU1(OMAP_DSS_VIDEO1));
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200207
Amber Jain5719d352011-05-19 19:47:52 +0530208 for (i = 0; i < 8; i++)
209 SR(OVL_FIR_COEF_H(OMAP_DSS_VIDEO1, i));
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200210
Amber Jain5719d352011-05-19 19:47:52 +0530211 for (i = 0; i < 8; i++)
212 SR(OVL_FIR_COEF_HV(OMAP_DSS_VIDEO1, i));
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200213
Amber Jain5719d352011-05-19 19:47:52 +0530214 for (i = 0; i < 5; i++)
215 SR(OVL_CONV_COEF(OMAP_DSS_VIDEO1, i));
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200216
Amber Jain5719d352011-05-19 19:47:52 +0530217 for (i = 0; i < 8; i++)
218 SR(OVL_FIR_COEF_V(OMAP_DSS_VIDEO1, i));
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200219
Archit Taneja9b372c22011-05-06 11:45:49 +0530220 SR(OVL_PRELOAD(OMAP_DSS_VIDEO1));
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200221
222 /* VID2 */
Archit Taneja9b372c22011-05-06 11:45:49 +0530223 SR(OVL_BA0(OMAP_DSS_VIDEO2));
224 SR(OVL_BA1(OMAP_DSS_VIDEO2));
225 SR(OVL_POSITION(OMAP_DSS_VIDEO2));
226 SR(OVL_SIZE(OMAP_DSS_VIDEO2));
227 SR(OVL_ATTRIBUTES(OMAP_DSS_VIDEO2));
228 SR(OVL_FIFO_THRESHOLD(OMAP_DSS_VIDEO2));
229 SR(OVL_ROW_INC(OMAP_DSS_VIDEO2));
230 SR(OVL_PIXEL_INC(OMAP_DSS_VIDEO2));
231 SR(OVL_FIR(OMAP_DSS_VIDEO2));
232 SR(OVL_PICTURE_SIZE(OMAP_DSS_VIDEO2));
233 SR(OVL_ACCU0(OMAP_DSS_VIDEO2));
234 SR(OVL_ACCU1(OMAP_DSS_VIDEO2));
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200235
Amber Jain5719d352011-05-19 19:47:52 +0530236 for (i = 0; i < 8; i++)
237 SR(OVL_FIR_COEF_H(OMAP_DSS_VIDEO2, i));
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200238
Amber Jain5719d352011-05-19 19:47:52 +0530239 for (i = 0; i < 8; i++)
240 SR(OVL_FIR_COEF_HV(OMAP_DSS_VIDEO2, i));
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200241
Amber Jain5719d352011-05-19 19:47:52 +0530242 for (i = 0; i < 5; i++)
243 SR(OVL_CONV_COEF(OMAP_DSS_VIDEO2, i));
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200244
Amber Jain5719d352011-05-19 19:47:52 +0530245 for (i = 0; i < 8; i++)
246 SR(OVL_FIR_COEF_V(OMAP_DSS_VIDEO2, i));
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200247
Archit Taneja9b372c22011-05-06 11:45:49 +0530248 SR(OVL_PRELOAD(OMAP_DSS_VIDEO2));
Murthy, Raghuveer0cf35df2011-03-03 09:28:00 -0600249
250 if (dss_has_feature(FEAT_CORE_CLK_DIV))
251 SR(DIVISOR);
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200252}
253
254void dispc_restore_context(void)
255{
Amber Jain5719d352011-05-19 19:47:52 +0530256 int i;
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200257 RR(SYSCONFIG);
Ville Syrjälä75c7d592010-03-05 01:13:11 +0200258 /*RR(IRQENABLE);*/
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200259 /*RR(CONTROL);*/
260 RR(CONFIG);
Archit Taneja702d1442011-05-06 11:45:50 +0530261 RR(DEFAULT_COLOR(OMAP_DSS_CHANNEL_LCD));
262 RR(DEFAULT_COLOR(OMAP_DSS_CHANNEL_DIGIT));
263 RR(TRANS_COLOR(OMAP_DSS_CHANNEL_LCD));
264 RR(TRANS_COLOR(OMAP_DSS_CHANNEL_DIGIT));
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200265 RR(LINE_NUMBER);
Archit Taneja702d1442011-05-06 11:45:50 +0530266 RR(TIMING_H(OMAP_DSS_CHANNEL_LCD));
267 RR(TIMING_V(OMAP_DSS_CHANNEL_LCD));
268 RR(POL_FREQ(OMAP_DSS_CHANNEL_LCD));
269 RR(DIVISORo(OMAP_DSS_CHANNEL_LCD));
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200270 RR(GLOBAL_ALPHA);
Archit Taneja702d1442011-05-06 11:45:50 +0530271 RR(SIZE_MGR(OMAP_DSS_CHANNEL_DIGIT));
272 RR(SIZE_MGR(OMAP_DSS_CHANNEL_LCD));
Sumit Semwal2a205f32010-12-02 11:27:12 +0000273 if (dss_has_feature(FEAT_MGR_LCD2)) {
Archit Taneja702d1442011-05-06 11:45:50 +0530274 RR(DEFAULT_COLOR(OMAP_DSS_CHANNEL_LCD2));
275 RR(TRANS_COLOR(OMAP_DSS_CHANNEL_LCD2));
276 RR(SIZE_MGR(OMAP_DSS_CHANNEL_LCD2));
277 RR(TIMING_H(OMAP_DSS_CHANNEL_LCD2));
278 RR(TIMING_V(OMAP_DSS_CHANNEL_LCD2));
279 RR(POL_FREQ(OMAP_DSS_CHANNEL_LCD2));
280 RR(DIVISORo(OMAP_DSS_CHANNEL_LCD2));
Sumit Semwal2a205f32010-12-02 11:27:12 +0000281 RR(CONFIG2);
282 }
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200283
Archit Taneja9b372c22011-05-06 11:45:49 +0530284 RR(OVL_BA0(OMAP_DSS_GFX));
285 RR(OVL_BA1(OMAP_DSS_GFX));
286 RR(OVL_POSITION(OMAP_DSS_GFX));
287 RR(OVL_SIZE(OMAP_DSS_GFX));
288 RR(OVL_ATTRIBUTES(OMAP_DSS_GFX));
289 RR(OVL_FIFO_THRESHOLD(OMAP_DSS_GFX));
290 RR(OVL_ROW_INC(OMAP_DSS_GFX));
291 RR(OVL_PIXEL_INC(OMAP_DSS_GFX));
292 RR(OVL_WINDOW_SKIP(OMAP_DSS_GFX));
293 RR(OVL_TABLE_BA(OMAP_DSS_GFX));
294
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200295
Archit Taneja702d1442011-05-06 11:45:50 +0530296 RR(DATA_CYCLE1(OMAP_DSS_CHANNEL_LCD));
297 RR(DATA_CYCLE2(OMAP_DSS_CHANNEL_LCD));
298 RR(DATA_CYCLE3(OMAP_DSS_CHANNEL_LCD));
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200299
Archit Taneja702d1442011-05-06 11:45:50 +0530300 RR(CPR_COEF_R(OMAP_DSS_CHANNEL_LCD));
301 RR(CPR_COEF_G(OMAP_DSS_CHANNEL_LCD));
302 RR(CPR_COEF_B(OMAP_DSS_CHANNEL_LCD));
Sumit Semwal2a205f32010-12-02 11:27:12 +0000303 if (dss_has_feature(FEAT_MGR_LCD2)) {
Archit Taneja702d1442011-05-06 11:45:50 +0530304 RR(DATA_CYCLE1(OMAP_DSS_CHANNEL_LCD2));
305 RR(DATA_CYCLE2(OMAP_DSS_CHANNEL_LCD2));
306 RR(DATA_CYCLE3(OMAP_DSS_CHANNEL_LCD2));
Sumit Semwal2a205f32010-12-02 11:27:12 +0000307
Archit Taneja702d1442011-05-06 11:45:50 +0530308 RR(CPR_COEF_B(OMAP_DSS_CHANNEL_LCD2));
309 RR(CPR_COEF_G(OMAP_DSS_CHANNEL_LCD2));
310 RR(CPR_COEF_R(OMAP_DSS_CHANNEL_LCD2));
Sumit Semwal2a205f32010-12-02 11:27:12 +0000311 }
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200312
Archit Taneja9b372c22011-05-06 11:45:49 +0530313 RR(OVL_PRELOAD(OMAP_DSS_GFX));
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200314
315 /* VID1 */
Archit Taneja9b372c22011-05-06 11:45:49 +0530316 RR(OVL_BA0(OMAP_DSS_VIDEO1));
317 RR(OVL_BA1(OMAP_DSS_VIDEO1));
318 RR(OVL_POSITION(OMAP_DSS_VIDEO1));
319 RR(OVL_SIZE(OMAP_DSS_VIDEO1));
320 RR(OVL_ATTRIBUTES(OMAP_DSS_VIDEO1));
321 RR(OVL_FIFO_THRESHOLD(OMAP_DSS_VIDEO1));
322 RR(OVL_ROW_INC(OMAP_DSS_VIDEO1));
323 RR(OVL_PIXEL_INC(OMAP_DSS_VIDEO1));
324 RR(OVL_FIR(OMAP_DSS_VIDEO1));
325 RR(OVL_PICTURE_SIZE(OMAP_DSS_VIDEO1));
326 RR(OVL_ACCU0(OMAP_DSS_VIDEO1));
327 RR(OVL_ACCU1(OMAP_DSS_VIDEO1));
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200328
Amber Jain5719d352011-05-19 19:47:52 +0530329 for (i = 0; i < 8; i++)
330 RR(OVL_FIR_COEF_H(OMAP_DSS_VIDEO1, i));
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200331
Amber Jain5719d352011-05-19 19:47:52 +0530332 for (i = 0; i < 8; i++)
333 RR(OVL_FIR_COEF_HV(OMAP_DSS_VIDEO1, i));
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200334
Amber Jain5719d352011-05-19 19:47:52 +0530335 for (i = 0; i < 5; i++)
336 RR(OVL_CONV_COEF(OMAP_DSS_VIDEO1, i));
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200337
Amber Jain5719d352011-05-19 19:47:52 +0530338 for (i = 0; i < 8; i++)
339 RR(OVL_FIR_COEF_V(OMAP_DSS_VIDEO1, i));
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200340
Archit Taneja9b372c22011-05-06 11:45:49 +0530341 RR(OVL_PRELOAD(OMAP_DSS_VIDEO1));
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200342
343 /* VID2 */
Archit Taneja9b372c22011-05-06 11:45:49 +0530344 RR(OVL_BA0(OMAP_DSS_VIDEO2));
345 RR(OVL_BA1(OMAP_DSS_VIDEO2));
346 RR(OVL_POSITION(OMAP_DSS_VIDEO2));
347 RR(OVL_SIZE(OMAP_DSS_VIDEO2));
348 RR(OVL_ATTRIBUTES(OMAP_DSS_VIDEO2));
349 RR(OVL_FIFO_THRESHOLD(OMAP_DSS_VIDEO2));
350 RR(OVL_ROW_INC(OMAP_DSS_VIDEO2));
351 RR(OVL_PIXEL_INC(OMAP_DSS_VIDEO2));
352 RR(OVL_FIR(OMAP_DSS_VIDEO2));
353 RR(OVL_PICTURE_SIZE(OMAP_DSS_VIDEO2));
354 RR(OVL_ACCU0(OMAP_DSS_VIDEO2));
355 RR(OVL_ACCU1(OMAP_DSS_VIDEO2));
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200356
Amber Jain5719d352011-05-19 19:47:52 +0530357 for (i = 0; i < 8; i++)
358 RR(OVL_FIR_COEF_H(OMAP_DSS_VIDEO2, i));
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200359
Amber Jain5719d352011-05-19 19:47:52 +0530360 for (i = 0; i < 8; i++)
361 RR(OVL_FIR_COEF_HV(OMAP_DSS_VIDEO2, i));
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200362
Amber Jain5719d352011-05-19 19:47:52 +0530363 for (i = 0; i < 5; i++)
364 RR(OVL_CONV_COEF(OMAP_DSS_VIDEO2, i));
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200365
Amber Jain5719d352011-05-19 19:47:52 +0530366 for (i = 0; i < 8; i++)
367 RR(OVL_FIR_COEF_V(OMAP_DSS_VIDEO2, i));
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200368
Archit Taneja9b372c22011-05-06 11:45:49 +0530369 RR(OVL_PRELOAD(OMAP_DSS_VIDEO2));
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200370
Murthy, Raghuveer0cf35df2011-03-03 09:28:00 -0600371 if (dss_has_feature(FEAT_CORE_CLK_DIV))
372 RR(DIVISOR);
373
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200374 /* enable last, because LCD & DIGIT enable are here */
375 RR(CONTROL);
Sumit Semwal2a205f32010-12-02 11:27:12 +0000376 if (dss_has_feature(FEAT_MGR_LCD2))
377 RR(CONTROL2);
Ville Syrjälä75c7d592010-03-05 01:13:11 +0200378 /* clear spurious SYNC_LOST_DIGIT interrupts */
379 dispc_write_reg(DISPC_IRQSTATUS, DISPC_IRQ_SYNC_LOST_DIGIT);
380
381 /*
382 * enable last so IRQs won't trigger before
383 * the context is fully restored
384 */
385 RR(IRQENABLE);
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200386}
387
388#undef SR
389#undef RR
390
391static inline void enable_clocks(bool enable)
392{
393 if (enable)
Archit Taneja6af9cd12011-01-31 16:27:44 +0000394 dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK);
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200395 else
Archit Taneja6af9cd12011-01-31 16:27:44 +0000396 dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK);
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200397}
398
399bool dispc_go_busy(enum omap_channel channel)
400{
401 int bit;
402
Sumit Semwal2a205f32010-12-02 11:27:12 +0000403 if (channel == OMAP_DSS_CHANNEL_LCD ||
404 channel == OMAP_DSS_CHANNEL_LCD2)
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200405 bit = 5; /* GOLCD */
406 else
407 bit = 6; /* GODIGIT */
408
Sumit Semwal2a205f32010-12-02 11:27:12 +0000409 if (channel == OMAP_DSS_CHANNEL_LCD2)
410 return REG_GET(DISPC_CONTROL2, bit, bit) == 1;
411 else
412 return REG_GET(DISPC_CONTROL, bit, bit) == 1;
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200413}
414
415void dispc_go(enum omap_channel channel)
416{
417 int bit;
Sumit Semwal2a205f32010-12-02 11:27:12 +0000418 bool enable_bit, go_bit;
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200419
420 enable_clocks(1);
421
Sumit Semwal2a205f32010-12-02 11:27:12 +0000422 if (channel == OMAP_DSS_CHANNEL_LCD ||
423 channel == OMAP_DSS_CHANNEL_LCD2)
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200424 bit = 0; /* LCDENABLE */
425 else
426 bit = 1; /* DIGITALENABLE */
427
428 /* if the channel is not enabled, we don't need GO */
Sumit Semwal2a205f32010-12-02 11:27:12 +0000429 if (channel == OMAP_DSS_CHANNEL_LCD2)
430 enable_bit = REG_GET(DISPC_CONTROL2, bit, bit) == 1;
431 else
432 enable_bit = REG_GET(DISPC_CONTROL, bit, bit) == 1;
433
434 if (!enable_bit)
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200435 goto end;
436
Sumit Semwal2a205f32010-12-02 11:27:12 +0000437 if (channel == OMAP_DSS_CHANNEL_LCD ||
438 channel == OMAP_DSS_CHANNEL_LCD2)
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200439 bit = 5; /* GOLCD */
440 else
441 bit = 6; /* GODIGIT */
442
Sumit Semwal2a205f32010-12-02 11:27:12 +0000443 if (channel == OMAP_DSS_CHANNEL_LCD2)
444 go_bit = REG_GET(DISPC_CONTROL2, bit, bit) == 1;
445 else
446 go_bit = REG_GET(DISPC_CONTROL, bit, bit) == 1;
447
448 if (go_bit) {
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200449 DSSERR("GO bit not down for channel %d\n", channel);
450 goto end;
451 }
452
Sumit Semwal2a205f32010-12-02 11:27:12 +0000453 DSSDBG("GO %s\n", channel == OMAP_DSS_CHANNEL_LCD ? "LCD" :
454 (channel == OMAP_DSS_CHANNEL_LCD2 ? "LCD2" : "DIGIT"));
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200455
Sumit Semwal2a205f32010-12-02 11:27:12 +0000456 if (channel == OMAP_DSS_CHANNEL_LCD2)
457 REG_FLD_MOD(DISPC_CONTROL2, 1, bit, bit);
458 else
459 REG_FLD_MOD(DISPC_CONTROL, 1, bit, bit);
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200460end:
461 enable_clocks(0);
462}
463
464static void _dispc_write_firh_reg(enum omap_plane plane, int reg, u32 value)
465{
Archit Taneja9b372c22011-05-06 11:45:49 +0530466 dispc_write_reg(DISPC_OVL_FIR_COEF_H(plane, reg), value);
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200467}
468
469static void _dispc_write_firhv_reg(enum omap_plane plane, int reg, u32 value)
470{
Archit Taneja9b372c22011-05-06 11:45:49 +0530471 dispc_write_reg(DISPC_OVL_FIR_COEF_HV(plane, reg), value);
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200472}
473
474static void _dispc_write_firv_reg(enum omap_plane plane, int reg, u32 value)
475{
Archit Taneja9b372c22011-05-06 11:45:49 +0530476 dispc_write_reg(DISPC_OVL_FIR_COEF_V(plane, reg), value);
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200477}
478
479static void _dispc_set_scale_coef(enum omap_plane plane, int hscaleup,
480 int vscaleup, int five_taps)
481{
482 /* Coefficients for horizontal up-sampling */
Grazvydas Ignotas66be8f62010-08-24 15:18:43 +0200483 static const struct dispc_h_coef coef_hup[8] = {
484 { 0, 0, 128, 0, 0 },
485 { -1, 13, 124, -8, 0 },
486 { -2, 30, 112, -11, -1 },
487 { -5, 51, 95, -11, -2 },
488 { 0, -9, 73, 73, -9 },
489 { -2, -11, 95, 51, -5 },
490 { -1, -11, 112, 30, -2 },
491 { 0, -8, 124, 13, -1 },
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200492 };
493
494 /* Coefficients for vertical up-sampling */
Grazvydas Ignotas66be8f62010-08-24 15:18:43 +0200495 static const struct dispc_v_coef coef_vup_3tap[8] = {
496 { 0, 0, 128, 0, 0 },
497 { 0, 3, 123, 2, 0 },
498 { 0, 12, 111, 5, 0 },
499 { 0, 32, 89, 7, 0 },
500 { 0, 0, 64, 64, 0 },
501 { 0, 7, 89, 32, 0 },
502 { 0, 5, 111, 12, 0 },
503 { 0, 2, 123, 3, 0 },
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200504 };
505
Grazvydas Ignotas66be8f62010-08-24 15:18:43 +0200506 static const struct dispc_v_coef coef_vup_5tap[8] = {
507 { 0, 0, 128, 0, 0 },
508 { -1, 13, 124, -8, 0 },
509 { -2, 30, 112, -11, -1 },
510 { -5, 51, 95, -11, -2 },
511 { 0, -9, 73, 73, -9 },
512 { -2, -11, 95, 51, -5 },
513 { -1, -11, 112, 30, -2 },
514 { 0, -8, 124, 13, -1 },
515 };
516
517 /* Coefficients for horizontal down-sampling */
518 static const struct dispc_h_coef coef_hdown[8] = {
519 { 0, 36, 56, 36, 0 },
520 { 4, 40, 55, 31, -2 },
521 { 8, 44, 54, 27, -5 },
522 { 12, 48, 53, 22, -7 },
523 { -9, 17, 52, 51, 17 },
524 { -7, 22, 53, 48, 12 },
525 { -5, 27, 54, 44, 8 },
526 { -2, 31, 55, 40, 4 },
527 };
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200528
529 /* Coefficients for vertical down-sampling */
Grazvydas Ignotas66be8f62010-08-24 15:18:43 +0200530 static const struct dispc_v_coef coef_vdown_3tap[8] = {
531 { 0, 36, 56, 36, 0 },
532 { 0, 40, 57, 31, 0 },
533 { 0, 45, 56, 27, 0 },
534 { 0, 50, 55, 23, 0 },
535 { 0, 18, 55, 55, 0 },
536 { 0, 23, 55, 50, 0 },
537 { 0, 27, 56, 45, 0 },
538 { 0, 31, 57, 40, 0 },
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200539 };
540
Grazvydas Ignotas66be8f62010-08-24 15:18:43 +0200541 static const struct dispc_v_coef coef_vdown_5tap[8] = {
542 { 0, 36, 56, 36, 0 },
543 { 4, 40, 55, 31, -2 },
544 { 8, 44, 54, 27, -5 },
545 { 12, 48, 53, 22, -7 },
546 { -9, 17, 52, 51, 17 },
547 { -7, 22, 53, 48, 12 },
548 { -5, 27, 54, 44, 8 },
549 { -2, 31, 55, 40, 4 },
550 };
551
552 const struct dispc_h_coef *h_coef;
553 const struct dispc_v_coef *v_coef;
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200554 int i;
555
556 if (hscaleup)
557 h_coef = coef_hup;
558 else
559 h_coef = coef_hdown;
560
Grazvydas Ignotas66be8f62010-08-24 15:18:43 +0200561 if (vscaleup)
562 v_coef = five_taps ? coef_vup_5tap : coef_vup_3tap;
563 else
564 v_coef = five_taps ? coef_vdown_5tap : coef_vdown_3tap;
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200565
566 for (i = 0; i < 8; i++) {
567 u32 h, hv;
568
Grazvydas Ignotas66be8f62010-08-24 15:18:43 +0200569 h = FLD_VAL(h_coef[i].hc0, 7, 0)
570 | FLD_VAL(h_coef[i].hc1, 15, 8)
571 | FLD_VAL(h_coef[i].hc2, 23, 16)
572 | FLD_VAL(h_coef[i].hc3, 31, 24);
573 hv = FLD_VAL(h_coef[i].hc4, 7, 0)
574 | FLD_VAL(v_coef[i].vc0, 15, 8)
575 | FLD_VAL(v_coef[i].vc1, 23, 16)
576 | FLD_VAL(v_coef[i].vc2, 31, 24);
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200577
578 _dispc_write_firh_reg(plane, i, h);
579 _dispc_write_firhv_reg(plane, i, hv);
580 }
581
Grazvydas Ignotas66be8f62010-08-24 15:18:43 +0200582 if (five_taps) {
583 for (i = 0; i < 8; i++) {
584 u32 v;
585 v = FLD_VAL(v_coef[i].vc00, 7, 0)
586 | FLD_VAL(v_coef[i].vc22, 15, 8);
587 _dispc_write_firv_reg(plane, i, v);
588 }
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200589 }
590}
591
592static void _dispc_setup_color_conv_coef(void)
593{
594 const struct color_conv_coef {
595 int ry, rcr, rcb, gy, gcr, gcb, by, bcr, bcb;
596 int full_range;
597 } ctbl_bt601_5 = {
598 298, 409, 0, 298, -208, -100, 298, 0, 517, 0,
599 };
600
601 const struct color_conv_coef *ct;
602
603#define CVAL(x, y) (FLD_VAL(x, 26, 16) | FLD_VAL(y, 10, 0))
604
605 ct = &ctbl_bt601_5;
606
Archit Taneja9b372c22011-05-06 11:45:49 +0530607 dispc_write_reg(DISPC_OVL_CONV_COEF(OMAP_DSS_VIDEO1, 0),
608 CVAL(ct->rcr, ct->ry));
609 dispc_write_reg(DISPC_OVL_CONV_COEF(OMAP_DSS_VIDEO1, 1),
610 CVAL(ct->gy, ct->rcb));
611 dispc_write_reg(DISPC_OVL_CONV_COEF(OMAP_DSS_VIDEO1, 2),
612 CVAL(ct->gcb, ct->gcr));
613 dispc_write_reg(DISPC_OVL_CONV_COEF(OMAP_DSS_VIDEO1, 3),
614 CVAL(ct->bcr, ct->by));
615 dispc_write_reg(DISPC_OVL_CONV_COEF(OMAP_DSS_VIDEO1, 4),
616 CVAL(0, ct->bcb));
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200617
Archit Taneja9b372c22011-05-06 11:45:49 +0530618 dispc_write_reg(DISPC_OVL_CONV_COEF(OMAP_DSS_VIDEO2, 0),
619 CVAL(ct->rcr, ct->ry));
620 dispc_write_reg(DISPC_OVL_CONV_COEF(OMAP_DSS_VIDEO2, 1),
621 CVAL(ct->gy, ct->rcb));
622 dispc_write_reg(DISPC_OVL_CONV_COEF(OMAP_DSS_VIDEO2, 2),
623 CVAL(ct->gcb, ct->gcr));
624 dispc_write_reg(DISPC_OVL_CONV_COEF(OMAP_DSS_VIDEO2, 3),
625 CVAL(ct->bcr, ct->by));
626 dispc_write_reg(DISPC_OVL_CONV_COEF(OMAP_DSS_VIDEO2, 4),
627 CVAL(0, ct->bcb));
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200628
629#undef CVAL
630
Archit Taneja9b372c22011-05-06 11:45:49 +0530631 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(OMAP_DSS_VIDEO1),
632 ct->full_range, 11, 11);
633 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(OMAP_DSS_VIDEO2),
634 ct->full_range, 11, 11);
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200635}
636
637
638static void _dispc_set_plane_ba0(enum omap_plane plane, u32 paddr)
639{
Archit Taneja9b372c22011-05-06 11:45:49 +0530640 dispc_write_reg(DISPC_OVL_BA0(plane), paddr);
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200641}
642
643static void _dispc_set_plane_ba1(enum omap_plane plane, u32 paddr)
644{
Archit Taneja9b372c22011-05-06 11:45:49 +0530645 dispc_write_reg(DISPC_OVL_BA1(plane), paddr);
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200646}
647
648static void _dispc_set_plane_pos(enum omap_plane plane, int x, int y)
649{
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200650 u32 val = FLD_VAL(y, 26, 16) | FLD_VAL(x, 10, 0);
Archit Taneja9b372c22011-05-06 11:45:49 +0530651
652 dispc_write_reg(DISPC_OVL_POSITION(plane), val);
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200653}
654
655static void _dispc_set_pic_size(enum omap_plane plane, int width, int height)
656{
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200657 u32 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
Archit Taneja9b372c22011-05-06 11:45:49 +0530658
659 if (plane == OMAP_DSS_GFX)
660 dispc_write_reg(DISPC_OVL_SIZE(plane), val);
661 else
662 dispc_write_reg(DISPC_OVL_PICTURE_SIZE(plane), val);
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200663}
664
665static void _dispc_set_vid_size(enum omap_plane plane, int width, int height)
666{
667 u32 val;
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200668
669 BUG_ON(plane == OMAP_DSS_GFX);
670
671 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
Archit Taneja9b372c22011-05-06 11:45:49 +0530672
673 dispc_write_reg(DISPC_OVL_SIZE(plane), val);
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200674}
675
Rajkumar Nfd28a392010-11-04 12:28:42 +0100676static void _dispc_set_pre_mult_alpha(enum omap_plane plane, bool enable)
677{
678 if (!dss_has_feature(FEAT_PRE_MULT_ALPHA))
679 return;
680
681 if (!dss_has_feature(FEAT_GLOBAL_ALPHA_VID1) &&
682 plane == OMAP_DSS_VIDEO1)
683 return;
684
Archit Taneja9b372c22011-05-06 11:45:49 +0530685 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable ? 1 : 0, 28, 28);
Rajkumar Nfd28a392010-11-04 12:28:42 +0100686}
687
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200688static void _dispc_setup_global_alpha(enum omap_plane plane, u8 global_alpha)
689{
Archit Tanejaa0acb552010-09-15 19:20:00 +0530690 if (!dss_has_feature(FEAT_GLOBAL_ALPHA))
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200691 return;
692
Rajkumar Nfd28a392010-11-04 12:28:42 +0100693 if (!dss_has_feature(FEAT_GLOBAL_ALPHA_VID1) &&
694 plane == OMAP_DSS_VIDEO1)
695 return;
Archit Tanejaa0acb552010-09-15 19:20:00 +0530696
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200697 if (plane == OMAP_DSS_GFX)
698 REG_FLD_MOD(DISPC_GLOBAL_ALPHA, global_alpha, 7, 0);
699 else if (plane == OMAP_DSS_VIDEO2)
700 REG_FLD_MOD(DISPC_GLOBAL_ALPHA, global_alpha, 23, 16);
701}
702
703static void _dispc_set_pix_inc(enum omap_plane plane, s32 inc)
704{
Archit Taneja9b372c22011-05-06 11:45:49 +0530705 dispc_write_reg(DISPC_OVL_PIXEL_INC(plane), inc);
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200706}
707
708static void _dispc_set_row_inc(enum omap_plane plane, s32 inc)
709{
Archit Taneja9b372c22011-05-06 11:45:49 +0530710 dispc_write_reg(DISPC_OVL_ROW_INC(plane), inc);
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200711}
712
713static void _dispc_set_color_mode(enum omap_plane plane,
714 enum omap_color_mode color_mode)
715{
716 u32 m = 0;
Amber Jainf20e4222011-05-19 19:47:50 +0530717 if (plane != OMAP_DSS_GFX) {
718 switch (color_mode) {
719 case OMAP_DSS_COLOR_NV12:
720 m = 0x0; break;
721 case OMAP_DSS_COLOR_RGB12U:
722 m = 0x1; break;
723 case OMAP_DSS_COLOR_RGBA16:
724 m = 0x2; break;
725 case OMAP_DSS_COLOR_RGBX16:
726 m = 0x4; break;
727 case OMAP_DSS_COLOR_ARGB16:
728 m = 0x5; break;
729 case OMAP_DSS_COLOR_RGB16:
730 m = 0x6; break;
731 case OMAP_DSS_COLOR_ARGB16_1555:
732 m = 0x7; break;
733 case OMAP_DSS_COLOR_RGB24U:
734 m = 0x8; break;
735 case OMAP_DSS_COLOR_RGB24P:
736 m = 0x9; break;
737 case OMAP_DSS_COLOR_YUV2:
738 m = 0xa; break;
739 case OMAP_DSS_COLOR_UYVY:
740 m = 0xb; break;
741 case OMAP_DSS_COLOR_ARGB32:
742 m = 0xc; break;
743 case OMAP_DSS_COLOR_RGBA32:
744 m = 0xd; break;
745 case OMAP_DSS_COLOR_RGBX32:
746 m = 0xe; break;
747 case OMAP_DSS_COLOR_XRGB16_1555:
748 m = 0xf; break;
749 default:
750 BUG(); break;
751 }
752 } else {
753 switch (color_mode) {
754 case OMAP_DSS_COLOR_CLUT1:
755 m = 0x0; break;
756 case OMAP_DSS_COLOR_CLUT2:
757 m = 0x1; break;
758 case OMAP_DSS_COLOR_CLUT4:
759 m = 0x2; break;
760 case OMAP_DSS_COLOR_CLUT8:
761 m = 0x3; break;
762 case OMAP_DSS_COLOR_RGB12U:
763 m = 0x4; break;
764 case OMAP_DSS_COLOR_ARGB16:
765 m = 0x5; break;
766 case OMAP_DSS_COLOR_RGB16:
767 m = 0x6; break;
768 case OMAP_DSS_COLOR_ARGB16_1555:
769 m = 0x7; break;
770 case OMAP_DSS_COLOR_RGB24U:
771 m = 0x8; break;
772 case OMAP_DSS_COLOR_RGB24P:
773 m = 0x9; break;
774 case OMAP_DSS_COLOR_YUV2:
775 m = 0xa; break;
776 case OMAP_DSS_COLOR_UYVY:
777 m = 0xb; break;
778 case OMAP_DSS_COLOR_ARGB32:
779 m = 0xc; break;
780 case OMAP_DSS_COLOR_RGBA32:
781 m = 0xd; break;
782 case OMAP_DSS_COLOR_RGBX32:
783 m = 0xe; break;
784 case OMAP_DSS_COLOR_XRGB16_1555:
785 m = 0xf; break;
786 default:
787 BUG(); break;
788 }
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200789 }
790
Archit Taneja9b372c22011-05-06 11:45:49 +0530791 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), m, 4, 1);
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200792}
793
794static void _dispc_set_channel_out(enum omap_plane plane,
795 enum omap_channel channel)
796{
797 int shift;
798 u32 val;
Sumit Semwal2a205f32010-12-02 11:27:12 +0000799 int chan = 0, chan2 = 0;
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200800
801 switch (plane) {
802 case OMAP_DSS_GFX:
803 shift = 8;
804 break;
805 case OMAP_DSS_VIDEO1:
806 case OMAP_DSS_VIDEO2:
807 shift = 16;
808 break;
809 default:
810 BUG();
811 return;
812 }
813
Archit Taneja9b372c22011-05-06 11:45:49 +0530814 val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
Sumit Semwal2a205f32010-12-02 11:27:12 +0000815 if (dss_has_feature(FEAT_MGR_LCD2)) {
816 switch (channel) {
817 case OMAP_DSS_CHANNEL_LCD:
818 chan = 0;
819 chan2 = 0;
820 break;
821 case OMAP_DSS_CHANNEL_DIGIT:
822 chan = 1;
823 chan2 = 0;
824 break;
825 case OMAP_DSS_CHANNEL_LCD2:
826 chan = 0;
827 chan2 = 1;
828 break;
829 default:
830 BUG();
831 }
832
833 val = FLD_MOD(val, chan, shift, shift);
834 val = FLD_MOD(val, chan2, 31, 30);
835 } else {
836 val = FLD_MOD(val, channel, shift, shift);
837 }
Archit Taneja9b372c22011-05-06 11:45:49 +0530838 dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), val);
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200839}
840
841void dispc_set_burst_size(enum omap_plane plane,
842 enum omap_burst_size burst_size)
843{
844 int shift;
845 u32 val;
846
847 enable_clocks(1);
848
849 switch (plane) {
850 case OMAP_DSS_GFX:
851 shift = 6;
852 break;
853 case OMAP_DSS_VIDEO1:
854 case OMAP_DSS_VIDEO2:
855 shift = 14;
856 break;
857 default:
858 BUG();
859 return;
860 }
861
Archit Taneja9b372c22011-05-06 11:45:49 +0530862 val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200863 val = FLD_MOD(val, burst_size, shift+1, shift);
Archit Taneja9b372c22011-05-06 11:45:49 +0530864 dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), val);
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200865
866 enable_clocks(0);
867}
868
Mythri P Kd3862612011-03-11 18:02:49 +0530869void dispc_enable_gamma_table(bool enable)
870{
871 /*
872 * This is partially implemented to support only disabling of
873 * the gamma table.
874 */
875 if (enable) {
876 DSSWARN("Gamma table enabling for TV not yet supported");
877 return;
878 }
879
880 REG_FLD_MOD(DISPC_CONFIG, enable, 9, 9);
881}
882
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200883static void _dispc_set_vid_color_conv(enum omap_plane plane, bool enable)
884{
885 u32 val;
886
887 BUG_ON(plane == OMAP_DSS_GFX);
888
Archit Taneja9b372c22011-05-06 11:45:49 +0530889 val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200890 val = FLD_MOD(val, enable, 9, 9);
Archit Taneja9b372c22011-05-06 11:45:49 +0530891 dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), val);
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200892}
893
894void dispc_enable_replication(enum omap_plane plane, bool enable)
895{
896 int bit;
897
898 if (plane == OMAP_DSS_GFX)
899 bit = 5;
900 else
901 bit = 10;
902
903 enable_clocks(1);
Archit Taneja9b372c22011-05-06 11:45:49 +0530904 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable, bit, bit);
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200905 enable_clocks(0);
906}
907
Sumit Semwal64ba4f72010-12-02 11:27:10 +0000908void dispc_set_lcd_size(enum omap_channel channel, u16 width, u16 height)
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200909{
910 u32 val;
911 BUG_ON((width > (1 << 11)) || (height > (1 << 11)));
912 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
913 enable_clocks(1);
Archit Taneja702d1442011-05-06 11:45:50 +0530914 dispc_write_reg(DISPC_SIZE_MGR(channel), val);
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200915 enable_clocks(0);
916}
917
918void dispc_set_digit_size(u16 width, u16 height)
919{
920 u32 val;
921 BUG_ON((width > (1 << 11)) || (height > (1 << 11)));
922 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
923 enable_clocks(1);
Archit Taneja702d1442011-05-06 11:45:50 +0530924 dispc_write_reg(DISPC_SIZE_MGR(OMAP_DSS_CHANNEL_DIGIT), val);
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200925 enable_clocks(0);
926}
927
928static void dispc_read_plane_fifo_sizes(void)
929{
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200930 u32 size;
931 int plane;
Archit Tanejaa0acb552010-09-15 19:20:00 +0530932 u8 start, end;
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200933
934 enable_clocks(1);
935
Archit Tanejaa0acb552010-09-15 19:20:00 +0530936 dss_feat_get_reg_field(FEAT_REG_FIFOSIZE, &start, &end);
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200937
Archit Tanejaa0acb552010-09-15 19:20:00 +0530938 for (plane = 0; plane < ARRAY_SIZE(dispc.fifo_size); ++plane) {
Archit Taneja9b372c22011-05-06 11:45:49 +0530939 size = FLD_GET(dispc_read_reg(DISPC_OVL_FIFO_SIZE_STATUS(plane)),
940 start, end);
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200941 dispc.fifo_size[plane] = size;
942 }
943
944 enable_clocks(0);
945}
946
947u32 dispc_get_plane_fifo_size(enum omap_plane plane)
948{
949 return dispc.fifo_size[plane];
950}
951
952void dispc_setup_plane_fifo(enum omap_plane plane, u32 low, u32 high)
953{
Archit Tanejaa0acb552010-09-15 19:20:00 +0530954 u8 hi_start, hi_end, lo_start, lo_end;
955
Archit Taneja9b372c22011-05-06 11:45:49 +0530956 dss_feat_get_reg_field(FEAT_REG_FIFOHIGHTHRESHOLD, &hi_start, &hi_end);
957 dss_feat_get_reg_field(FEAT_REG_FIFOLOWTHRESHOLD, &lo_start, &lo_end);
958
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200959 enable_clocks(1);
960
961 DSSDBG("fifo(%d) low/high old %u/%u, new %u/%u\n",
962 plane,
Archit Taneja9b372c22011-05-06 11:45:49 +0530963 REG_GET(DISPC_OVL_FIFO_THRESHOLD(plane),
964 lo_start, lo_end),
965 REG_GET(DISPC_OVL_FIFO_THRESHOLD(plane),
966 hi_start, hi_end),
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200967 low, high);
968
Archit Taneja9b372c22011-05-06 11:45:49 +0530969 dispc_write_reg(DISPC_OVL_FIFO_THRESHOLD(plane),
Archit Tanejaa0acb552010-09-15 19:20:00 +0530970 FLD_VAL(high, hi_start, hi_end) |
971 FLD_VAL(low, lo_start, lo_end));
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200972
973 enable_clocks(0);
974}
975
976void dispc_enable_fifomerge(bool enable)
977{
978 enable_clocks(1);
979
980 DSSDBG("FIFO merge %s\n", enable ? "enabled" : "disabled");
981 REG_FLD_MOD(DISPC_CONFIG, enable ? 1 : 0, 14, 14);
982
983 enable_clocks(0);
984}
985
986static void _dispc_set_fir(enum omap_plane plane, int hinc, int vinc)
987{
988 u32 val;
Archit Tanejaa0acb552010-09-15 19:20:00 +0530989 u8 hinc_start, hinc_end, vinc_start, vinc_end;
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200990
Archit Tanejaa0acb552010-09-15 19:20:00 +0530991 dss_feat_get_reg_field(FEAT_REG_FIRHINC, &hinc_start, &hinc_end);
992 dss_feat_get_reg_field(FEAT_REG_FIRVINC, &vinc_start, &vinc_end);
993
994 val = FLD_VAL(vinc, vinc_start, vinc_end) |
995 FLD_VAL(hinc, hinc_start, hinc_end);
996
Archit Taneja9b372c22011-05-06 11:45:49 +0530997 dispc_write_reg(DISPC_OVL_FIR(plane), val);
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200998}
999
1000static void _dispc_set_vid_accu0(enum omap_plane plane, int haccu, int vaccu)
1001{
1002 u32 val;
Archit Taneja87a74842011-03-02 11:19:50 +05301003 u8 hor_start, hor_end, vert_start, vert_end;
Tomi Valkeinen80c39712009-11-12 11:41:42 +02001004
Archit Taneja87a74842011-03-02 11:19:50 +05301005 dss_feat_get_reg_field(FEAT_REG_HORIZONTALACCU, &hor_start, &hor_end);
1006 dss_feat_get_reg_field(FEAT_REG_VERTICALACCU, &vert_start, &vert_end);
1007
1008 val = FLD_VAL(vaccu, vert_start, vert_end) |
1009 FLD_VAL(haccu, hor_start, hor_end);
1010
Archit Taneja9b372c22011-05-06 11:45:49 +05301011 dispc_write_reg(DISPC_OVL_ACCU0(plane), val);
Tomi Valkeinen80c39712009-11-12 11:41:42 +02001012}
1013
1014static void _dispc_set_vid_accu1(enum omap_plane plane, int haccu, int vaccu)
1015{
1016 u32 val;
Archit Taneja87a74842011-03-02 11:19:50 +05301017 u8 hor_start, hor_end, vert_start, vert_end;
Tomi Valkeinen80c39712009-11-12 11:41:42 +02001018
Archit Taneja87a74842011-03-02 11:19:50 +05301019 dss_feat_get_reg_field(FEAT_REG_HORIZONTALACCU, &hor_start, &hor_end);
1020 dss_feat_get_reg_field(FEAT_REG_VERTICALACCU, &vert_start, &vert_end);
1021
1022 val = FLD_VAL(vaccu, vert_start, vert_end) |
1023 FLD_VAL(haccu, hor_start, hor_end);
1024
Archit Taneja9b372c22011-05-06 11:45:49 +05301025 dispc_write_reg(DISPC_OVL_ACCU1(plane), val);
Tomi Valkeinen80c39712009-11-12 11:41:42 +02001026}
1027
1028
1029static void _dispc_set_scaling(enum omap_plane plane,
1030 u16 orig_width, u16 orig_height,
1031 u16 out_width, u16 out_height,
1032 bool ilace, bool five_taps,
1033 bool fieldmode)
1034{
1035 int fir_hinc;
1036 int fir_vinc;
1037 int hscaleup, vscaleup;
1038 int accu0 = 0;
1039 int accu1 = 0;
1040 u32 l;
1041
1042 BUG_ON(plane == OMAP_DSS_GFX);
1043
1044 hscaleup = orig_width <= out_width;
1045 vscaleup = orig_height <= out_height;
1046
1047 _dispc_set_scale_coef(plane, hscaleup, vscaleup, five_taps);
1048
Amber Jained14a3c2011-05-19 19:47:51 +05301049 fir_hinc = 1024 * orig_width / out_width;
1050 fir_vinc = 1024 * orig_height / out_height;
Tomi Valkeinen80c39712009-11-12 11:41:42 +02001051
1052 _dispc_set_fir(plane, fir_hinc, fir_vinc);
1053
Archit Taneja9b372c22011-05-06 11:45:49 +05301054 l = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
Tomi Valkeinen80c39712009-11-12 11:41:42 +02001055
Archit Taneja87a74842011-03-02 11:19:50 +05301056 /* RESIZEENABLE and VERTICALTAPS */
1057 l &= ~((0x3 << 5) | (0x1 << 21));
Amber Jained14a3c2011-05-19 19:47:51 +05301058 l |= (orig_width != out_width) ? (1 << 5) : 0;
1059 l |= (orig_height != out_height) ? (1 << 6) : 0;
Tomi Valkeinen80c39712009-11-12 11:41:42 +02001060 l |= five_taps ? (1 << 21) : 0;
Archit Taneja87a74842011-03-02 11:19:50 +05301061
1062 /* VRESIZECONF and HRESIZECONF */
1063 if (dss_has_feature(FEAT_RESIZECONF)) {
1064 l &= ~(0x3 << 7);
1065 l |= hscaleup ? 0 : (1 << 7);
1066 l |= vscaleup ? 0 : (1 << 8);
1067 }
1068
1069 /* LINEBUFFERSPLIT */
1070 if (dss_has_feature(FEAT_LINEBUFFERSPLIT)) {
1071 l &= ~(0x1 << 22);
1072 l |= five_taps ? (1 << 22) : 0;
1073 }
Tomi Valkeinen80c39712009-11-12 11:41:42 +02001074
Archit Taneja9b372c22011-05-06 11:45:49 +05301075 dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), l);
Tomi Valkeinen80c39712009-11-12 11:41:42 +02001076
1077 /*
1078 * field 0 = even field = bottom field
1079 * field 1 = odd field = top field
1080 */
1081 if (ilace && !fieldmode) {
1082 accu1 = 0;
1083 accu0 = (fir_vinc / 2) & 0x3ff;
1084 if (accu0 >= 1024/2) {
1085 accu1 = 1024/2;
1086 accu0 -= accu1;
1087 }
1088 }
1089
1090 _dispc_set_vid_accu0(plane, 0, accu0);
1091 _dispc_set_vid_accu1(plane, 0, accu1);
1092}
1093
1094static void _dispc_set_rotation_attrs(enum omap_plane plane, u8 rotation,
1095 bool mirroring, enum omap_color_mode color_mode)
1096{
Archit Taneja87a74842011-03-02 11:19:50 +05301097 bool row_repeat = false;
1098 int vidrot = 0;
1099
Tomi Valkeinen80c39712009-11-12 11:41:42 +02001100 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1101 color_mode == OMAP_DSS_COLOR_UYVY) {
Tomi Valkeinen80c39712009-11-12 11:41:42 +02001102
1103 if (mirroring) {
1104 switch (rotation) {
1105 case OMAP_DSS_ROT_0:
1106 vidrot = 2;
1107 break;
1108 case OMAP_DSS_ROT_90:
1109 vidrot = 1;
1110 break;
1111 case OMAP_DSS_ROT_180:
1112 vidrot = 0;
1113 break;
1114 case OMAP_DSS_ROT_270:
1115 vidrot = 3;
1116 break;
1117 }
1118 } else {
1119 switch (rotation) {
1120 case OMAP_DSS_ROT_0:
1121 vidrot = 0;
1122 break;
1123 case OMAP_DSS_ROT_90:
1124 vidrot = 1;
1125 break;
1126 case OMAP_DSS_ROT_180:
1127 vidrot = 2;
1128 break;
1129 case OMAP_DSS_ROT_270:
1130 vidrot = 3;
1131 break;
1132 }
1133 }
1134
Tomi Valkeinen80c39712009-11-12 11:41:42 +02001135 if (rotation == OMAP_DSS_ROT_90 || rotation == OMAP_DSS_ROT_270)
Archit Taneja87a74842011-03-02 11:19:50 +05301136 row_repeat = true;
Tomi Valkeinen80c39712009-11-12 11:41:42 +02001137 else
Archit Taneja87a74842011-03-02 11:19:50 +05301138 row_repeat = false;
Tomi Valkeinen80c39712009-11-12 11:41:42 +02001139 }
Archit Taneja87a74842011-03-02 11:19:50 +05301140
Archit Taneja9b372c22011-05-06 11:45:49 +05301141 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), vidrot, 13, 12);
Archit Taneja87a74842011-03-02 11:19:50 +05301142 if (dss_has_feature(FEAT_ROWREPEATENABLE))
Archit Taneja9b372c22011-05-06 11:45:49 +05301143 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane),
1144 row_repeat ? 1 : 0, 18, 18);
Tomi Valkeinen80c39712009-11-12 11:41:42 +02001145}
1146
1147static int color_mode_to_bpp(enum omap_color_mode color_mode)
1148{
1149 switch (color_mode) {
1150 case OMAP_DSS_COLOR_CLUT1:
1151 return 1;
1152 case OMAP_DSS_COLOR_CLUT2:
1153 return 2;
1154 case OMAP_DSS_COLOR_CLUT4:
1155 return 4;
1156 case OMAP_DSS_COLOR_CLUT8:
Amber Jainf20e4222011-05-19 19:47:50 +05301157 case OMAP_DSS_COLOR_NV12:
Tomi Valkeinen80c39712009-11-12 11:41:42 +02001158 return 8;
1159 case OMAP_DSS_COLOR_RGB12U:
1160 case OMAP_DSS_COLOR_RGB16:
1161 case OMAP_DSS_COLOR_ARGB16:
1162 case OMAP_DSS_COLOR_YUV2:
1163 case OMAP_DSS_COLOR_UYVY:
Amber Jainf20e4222011-05-19 19:47:50 +05301164 case OMAP_DSS_COLOR_RGBA16:
1165 case OMAP_DSS_COLOR_RGBX16:
1166 case OMAP_DSS_COLOR_ARGB16_1555:
1167 case OMAP_DSS_COLOR_XRGB16_1555:
Tomi Valkeinen80c39712009-11-12 11:41:42 +02001168 return 16;
1169 case OMAP_DSS_COLOR_RGB24P:
1170 return 24;
1171 case OMAP_DSS_COLOR_RGB24U:
1172 case OMAP_DSS_COLOR_ARGB32:
1173 case OMAP_DSS_COLOR_RGBA32:
1174 case OMAP_DSS_COLOR_RGBX32:
1175 return 32;
1176 default:
1177 BUG();
1178 }
1179}
1180
1181static s32 pixinc(int pixels, u8 ps)
1182{
1183 if (pixels == 1)
1184 return 1;
1185 else if (pixels > 1)
1186 return 1 + (pixels - 1) * ps;
1187 else if (pixels < 0)
1188 return 1 - (-pixels + 1) * ps;
1189 else
1190 BUG();
1191}
1192
1193static void calc_vrfb_rotation_offset(u8 rotation, bool mirror,
1194 u16 screen_width,
1195 u16 width, u16 height,
1196 enum omap_color_mode color_mode, bool fieldmode,
1197 unsigned int field_offset,
1198 unsigned *offset0, unsigned *offset1,
1199 s32 *row_inc, s32 *pix_inc)
1200{
1201 u8 ps;
1202
1203 /* FIXME CLUT formats */
1204 switch (color_mode) {
1205 case OMAP_DSS_COLOR_CLUT1:
1206 case OMAP_DSS_COLOR_CLUT2:
1207 case OMAP_DSS_COLOR_CLUT4:
1208 case OMAP_DSS_COLOR_CLUT8:
1209 BUG();
1210 return;
1211 case OMAP_DSS_COLOR_YUV2:
1212 case OMAP_DSS_COLOR_UYVY:
1213 ps = 4;
1214 break;
1215 default:
1216 ps = color_mode_to_bpp(color_mode) / 8;
1217 break;
1218 }
1219
1220 DSSDBG("calc_rot(%d): scrw %d, %dx%d\n", rotation, screen_width,
1221 width, height);
1222
1223 /*
1224 * field 0 = even field = bottom field
1225 * field 1 = odd field = top field
1226 */
1227 switch (rotation + mirror * 4) {
1228 case OMAP_DSS_ROT_0:
1229 case OMAP_DSS_ROT_180:
1230 /*
1231 * If the pixel format is YUV or UYVY divide the width
1232 * of the image by 2 for 0 and 180 degree rotation.
1233 */
1234 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1235 color_mode == OMAP_DSS_COLOR_UYVY)
1236 width = width >> 1;
1237 case OMAP_DSS_ROT_90:
1238 case OMAP_DSS_ROT_270:
1239 *offset1 = 0;
1240 if (field_offset)
1241 *offset0 = field_offset * screen_width * ps;
1242 else
1243 *offset0 = 0;
1244
1245 *row_inc = pixinc(1 + (screen_width - width) +
1246 (fieldmode ? screen_width : 0),
1247 ps);
1248 *pix_inc = pixinc(1, ps);
1249 break;
1250
1251 case OMAP_DSS_ROT_0 + 4:
1252 case OMAP_DSS_ROT_180 + 4:
1253 /* If the pixel format is YUV or UYVY divide the width
1254 * of the image by 2 for 0 degree and 180 degree
1255 */
1256 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1257 color_mode == OMAP_DSS_COLOR_UYVY)
1258 width = width >> 1;
1259 case OMAP_DSS_ROT_90 + 4:
1260 case OMAP_DSS_ROT_270 + 4:
1261 *offset1 = 0;
1262 if (field_offset)
1263 *offset0 = field_offset * screen_width * ps;
1264 else
1265 *offset0 = 0;
1266 *row_inc = pixinc(1 - (screen_width + width) -
1267 (fieldmode ? screen_width : 0),
1268 ps);
1269 *pix_inc = pixinc(1, ps);
1270 break;
1271
1272 default:
1273 BUG();
1274 }
1275}
1276
1277static void calc_dma_rotation_offset(u8 rotation, bool mirror,
1278 u16 screen_width,
1279 u16 width, u16 height,
1280 enum omap_color_mode color_mode, bool fieldmode,
1281 unsigned int field_offset,
1282 unsigned *offset0, unsigned *offset1,
1283 s32 *row_inc, s32 *pix_inc)
1284{
1285 u8 ps;
1286 u16 fbw, fbh;
1287
1288 /* FIXME CLUT formats */
1289 switch (color_mode) {
1290 case OMAP_DSS_COLOR_CLUT1:
1291 case OMAP_DSS_COLOR_CLUT2:
1292 case OMAP_DSS_COLOR_CLUT4:
1293 case OMAP_DSS_COLOR_CLUT8:
1294 BUG();
1295 return;
1296 default:
1297 ps = color_mode_to_bpp(color_mode) / 8;
1298 break;
1299 }
1300
1301 DSSDBG("calc_rot(%d): scrw %d, %dx%d\n", rotation, screen_width,
1302 width, height);
1303
1304 /* width & height are overlay sizes, convert to fb sizes */
1305
1306 if (rotation == OMAP_DSS_ROT_0 || rotation == OMAP_DSS_ROT_180) {
1307 fbw = width;
1308 fbh = height;
1309 } else {
1310 fbw = height;
1311 fbh = width;
1312 }
1313
1314 /*
1315 * field 0 = even field = bottom field
1316 * field 1 = odd field = top field
1317 */
1318 switch (rotation + mirror * 4) {
1319 case OMAP_DSS_ROT_0:
1320 *offset1 = 0;
1321 if (field_offset)
1322 *offset0 = *offset1 + field_offset * screen_width * ps;
1323 else
1324 *offset0 = *offset1;
1325 *row_inc = pixinc(1 + (screen_width - fbw) +
1326 (fieldmode ? screen_width : 0),
1327 ps);
1328 *pix_inc = pixinc(1, ps);
1329 break;
1330 case OMAP_DSS_ROT_90:
1331 *offset1 = screen_width * (fbh - 1) * ps;
1332 if (field_offset)
1333 *offset0 = *offset1 + field_offset * ps;
1334 else
1335 *offset0 = *offset1;
1336 *row_inc = pixinc(screen_width * (fbh - 1) + 1 +
1337 (fieldmode ? 1 : 0), ps);
1338 *pix_inc = pixinc(-screen_width, ps);
1339 break;
1340 case OMAP_DSS_ROT_180:
1341 *offset1 = (screen_width * (fbh - 1) + fbw - 1) * ps;
1342 if (field_offset)
1343 *offset0 = *offset1 - field_offset * screen_width * ps;
1344 else
1345 *offset0 = *offset1;
1346 *row_inc = pixinc(-1 -
1347 (screen_width - fbw) -
1348 (fieldmode ? screen_width : 0),
1349 ps);
1350 *pix_inc = pixinc(-1, ps);
1351 break;
1352 case OMAP_DSS_ROT_270:
1353 *offset1 = (fbw - 1) * ps;
1354 if (field_offset)
1355 *offset0 = *offset1 - field_offset * ps;
1356 else
1357 *offset0 = *offset1;
1358 *row_inc = pixinc(-screen_width * (fbh - 1) - 1 -
1359 (fieldmode ? 1 : 0), ps);
1360 *pix_inc = pixinc(screen_width, ps);
1361 break;
1362
1363 /* mirroring */
1364 case OMAP_DSS_ROT_0 + 4:
1365 *offset1 = (fbw - 1) * ps;
1366 if (field_offset)
1367 *offset0 = *offset1 + field_offset * screen_width * ps;
1368 else
1369 *offset0 = *offset1;
1370 *row_inc = pixinc(screen_width * 2 - 1 +
1371 (fieldmode ? screen_width : 0),
1372 ps);
1373 *pix_inc = pixinc(-1, ps);
1374 break;
1375
1376 case OMAP_DSS_ROT_90 + 4:
1377 *offset1 = 0;
1378 if (field_offset)
1379 *offset0 = *offset1 + field_offset * ps;
1380 else
1381 *offset0 = *offset1;
1382 *row_inc = pixinc(-screen_width * (fbh - 1) + 1 +
1383 (fieldmode ? 1 : 0),
1384 ps);
1385 *pix_inc = pixinc(screen_width, ps);
1386 break;
1387
1388 case OMAP_DSS_ROT_180 + 4:
1389 *offset1 = screen_width * (fbh - 1) * ps;
1390 if (field_offset)
1391 *offset0 = *offset1 - field_offset * screen_width * ps;
1392 else
1393 *offset0 = *offset1;
1394 *row_inc = pixinc(1 - screen_width * 2 -
1395 (fieldmode ? screen_width : 0),
1396 ps);
1397 *pix_inc = pixinc(1, ps);
1398 break;
1399
1400 case OMAP_DSS_ROT_270 + 4:
1401 *offset1 = (screen_width * (fbh - 1) + fbw - 1) * ps;
1402 if (field_offset)
1403 *offset0 = *offset1 - field_offset * ps;
1404 else
1405 *offset0 = *offset1;
1406 *row_inc = pixinc(screen_width * (fbh - 1) - 1 -
1407 (fieldmode ? 1 : 0),
1408 ps);
1409 *pix_inc = pixinc(-screen_width, ps);
1410 break;
1411
1412 default:
1413 BUG();
1414 }
1415}
1416
Sumit Semwalff1b2cd2010-12-02 11:27:11 +00001417static unsigned long calc_fclk_five_taps(enum omap_channel channel, u16 width,
1418 u16 height, u16 out_width, u16 out_height,
1419 enum omap_color_mode color_mode)
Tomi Valkeinen80c39712009-11-12 11:41:42 +02001420{
1421 u32 fclk = 0;
1422 /* FIXME venc pclk? */
Sumit Semwalff1b2cd2010-12-02 11:27:11 +00001423 u64 tmp, pclk = dispc_pclk_rate(channel);
Tomi Valkeinen80c39712009-11-12 11:41:42 +02001424
1425 if (height > out_height) {
1426 /* FIXME get real display PPL */
1427 unsigned int ppl = 800;
1428
1429 tmp = pclk * height * out_width;
1430 do_div(tmp, 2 * out_height * ppl);
1431 fclk = tmp;
1432
Ville Syrjälä2d9c5592010-01-08 11:56:41 +02001433 if (height > 2 * out_height) {
1434 if (ppl == out_width)
1435 return 0;
1436
Tomi Valkeinen80c39712009-11-12 11:41:42 +02001437 tmp = pclk * (height - 2 * out_height) * out_width;
1438 do_div(tmp, 2 * out_height * (ppl - out_width));
1439 fclk = max(fclk, (u32) tmp);
1440 }
1441 }
1442
1443 if (width > out_width) {
1444 tmp = pclk * width;
1445 do_div(tmp, out_width);
1446 fclk = max(fclk, (u32) tmp);
1447
1448 if (color_mode == OMAP_DSS_COLOR_RGB24U)
1449 fclk <<= 1;
1450 }
1451
1452 return fclk;
1453}
1454
Sumit Semwalff1b2cd2010-12-02 11:27:11 +00001455static unsigned long calc_fclk(enum omap_channel channel, u16 width,
1456 u16 height, u16 out_width, u16 out_height)
Tomi Valkeinen80c39712009-11-12 11:41:42 +02001457{
1458 unsigned int hf, vf;
1459
1460 /*
1461 * FIXME how to determine the 'A' factor
1462 * for the no downscaling case ?
1463 */
1464
1465 if (width > 3 * out_width)
1466 hf = 4;
1467 else if (width > 2 * out_width)
1468 hf = 3;
1469 else if (width > out_width)
1470 hf = 2;
1471 else
1472 hf = 1;
1473
1474 if (height > out_height)
1475 vf = 2;
1476 else
1477 vf = 1;
1478
1479 /* FIXME venc pclk? */
Sumit Semwalff1b2cd2010-12-02 11:27:11 +00001480 return dispc_pclk_rate(channel) * vf * hf;
Tomi Valkeinen80c39712009-11-12 11:41:42 +02001481}
1482
1483void dispc_set_channel_out(enum omap_plane plane, enum omap_channel channel_out)
1484{
1485 enable_clocks(1);
1486 _dispc_set_channel_out(plane, channel_out);
1487 enable_clocks(0);
1488}
1489
1490static int _dispc_setup_plane(enum omap_plane plane,
1491 u32 paddr, u16 screen_width,
1492 u16 pos_x, u16 pos_y,
1493 u16 width, u16 height,
1494 u16 out_width, u16 out_height,
1495 enum omap_color_mode color_mode,
1496 bool ilace,
1497 enum omap_dss_rotation_type rotation_type,
1498 u8 rotation, int mirror,
Sumit Semwal18faa1b2010-12-02 11:27:14 +00001499 u8 global_alpha, u8 pre_mult_alpha,
1500 enum omap_channel channel)
Tomi Valkeinen80c39712009-11-12 11:41:42 +02001501{
1502 const int maxdownscale = cpu_is_omap34xx() ? 4 : 2;
1503 bool five_taps = 0;
1504 bool fieldmode = 0;
1505 int cconv = 0;
1506 unsigned offset0, offset1;
1507 s32 row_inc;
1508 s32 pix_inc;
1509 u16 frame_height = height;
1510 unsigned int field_offset = 0;
1511
1512 if (paddr == 0)
1513 return -EINVAL;
1514
1515 if (ilace && height == out_height)
1516 fieldmode = 1;
1517
1518 if (ilace) {
1519 if (fieldmode)
1520 height /= 2;
1521 pos_y /= 2;
1522 out_height /= 2;
1523
1524 DSSDBG("adjusting for ilace: height %d, pos_y %d, "
1525 "out_height %d\n",
1526 height, pos_y, out_height);
1527 }
1528
Archit Taneja8dad2ab2010-11-25 17:58:10 +05301529 if (!dss_feat_color_mode_supported(plane, color_mode))
1530 return -EINVAL;
1531
Tomi Valkeinen80c39712009-11-12 11:41:42 +02001532 if (plane == OMAP_DSS_GFX) {
1533 if (width != out_width || height != out_height)
1534 return -EINVAL;
Tomi Valkeinen80c39712009-11-12 11:41:42 +02001535 } else {
1536 /* video plane */
1537
1538 unsigned long fclk = 0;
1539
1540 if (out_width < width / maxdownscale ||
1541 out_width > width * 8)
1542 return -EINVAL;
1543
1544 if (out_height < height / maxdownscale ||
1545 out_height > height * 8)
1546 return -EINVAL;
1547
Archit Taneja8dad2ab2010-11-25 17:58:10 +05301548 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1549 color_mode == OMAP_DSS_COLOR_UYVY)
Tomi Valkeinen80c39712009-11-12 11:41:42 +02001550 cconv = 1;
Tomi Valkeinen80c39712009-11-12 11:41:42 +02001551
1552 /* Must use 5-tap filter? */
1553 five_taps = height > out_height * 2;
1554
1555 if (!five_taps) {
Sumit Semwal18faa1b2010-12-02 11:27:14 +00001556 fclk = calc_fclk(channel, width, height, out_width,
1557 out_height);
Tomi Valkeinen80c39712009-11-12 11:41:42 +02001558
1559 /* Try 5-tap filter if 3-tap fclk is too high */
1560 if (cpu_is_omap34xx() && height > out_height &&
1561 fclk > dispc_fclk_rate())
1562 five_taps = true;
1563 }
1564
1565 if (width > (2048 >> five_taps)) {
1566 DSSERR("failed to set up scaling, fclk too low\n");
1567 return -EINVAL;
1568 }
1569
1570 if (five_taps)
Sumit Semwal18faa1b2010-12-02 11:27:14 +00001571 fclk = calc_fclk_five_taps(channel, width, height,
1572 out_width, out_height, color_mode);
Tomi Valkeinen80c39712009-11-12 11:41:42 +02001573
1574 DSSDBG("required fclk rate = %lu Hz\n", fclk);
1575 DSSDBG("current fclk rate = %lu Hz\n", dispc_fclk_rate());
1576
Ville Syrjälä2d9c5592010-01-08 11:56:41 +02001577 if (!fclk || fclk > dispc_fclk_rate()) {
Tomi Valkeinen80c39712009-11-12 11:41:42 +02001578 DSSERR("failed to set up scaling, "
1579 "required fclk rate = %lu Hz, "
1580 "current fclk rate = %lu Hz\n",
1581 fclk, dispc_fclk_rate());
1582 return -EINVAL;
1583 }
1584 }
1585
1586 if (ilace && !fieldmode) {
1587 /*
1588 * when downscaling the bottom field may have to start several
1589 * source lines below the top field. Unfortunately ACCUI
1590 * registers will only hold the fractional part of the offset
1591 * so the integer part must be added to the base address of the
1592 * bottom field.
1593 */
1594 if (!height || height == out_height)
1595 field_offset = 0;
1596 else
1597 field_offset = height / out_height / 2;
1598 }
1599
1600 /* Fields are independent but interleaved in memory. */
1601 if (fieldmode)
1602 field_offset = 1;
1603
1604 if (rotation_type == OMAP_DSS_ROT_DMA)
1605 calc_dma_rotation_offset(rotation, mirror,
1606 screen_width, width, frame_height, color_mode,
1607 fieldmode, field_offset,
1608 &offset0, &offset1, &row_inc, &pix_inc);
1609 else
1610 calc_vrfb_rotation_offset(rotation, mirror,
1611 screen_width, width, frame_height, color_mode,
1612 fieldmode, field_offset,
1613 &offset0, &offset1, &row_inc, &pix_inc);
1614
1615 DSSDBG("offset0 %u, offset1 %u, row_inc %d, pix_inc %d\n",
1616 offset0, offset1, row_inc, pix_inc);
1617
1618 _dispc_set_color_mode(plane, color_mode);
1619
1620 _dispc_set_plane_ba0(plane, paddr + offset0);
1621 _dispc_set_plane_ba1(plane, paddr + offset1);
1622
1623 _dispc_set_row_inc(plane, row_inc);
1624 _dispc_set_pix_inc(plane, pix_inc);
1625
1626 DSSDBG("%d,%d %dx%d -> %dx%d\n", pos_x, pos_y, width, height,
1627 out_width, out_height);
1628
1629 _dispc_set_plane_pos(plane, pos_x, pos_y);
1630
1631 _dispc_set_pic_size(plane, width, height);
1632
1633 if (plane != OMAP_DSS_GFX) {
1634 _dispc_set_scaling(plane, width, height,
1635 out_width, out_height,
1636 ilace, five_taps, fieldmode);
1637 _dispc_set_vid_size(plane, out_width, out_height);
1638 _dispc_set_vid_color_conv(plane, cconv);
1639 }
1640
1641 _dispc_set_rotation_attrs(plane, rotation, mirror, color_mode);
1642
Rajkumar Nfd28a392010-11-04 12:28:42 +01001643 _dispc_set_pre_mult_alpha(plane, pre_mult_alpha);
1644 _dispc_setup_global_alpha(plane, global_alpha);
Tomi Valkeinen80c39712009-11-12 11:41:42 +02001645
1646 return 0;
1647}
1648
1649static void _dispc_enable_plane(enum omap_plane plane, bool enable)
1650{
Archit Taneja9b372c22011-05-06 11:45:49 +05301651 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable ? 1 : 0, 0, 0);
Tomi Valkeinen80c39712009-11-12 11:41:42 +02001652}
1653
1654static void dispc_disable_isr(void *data, u32 mask)
1655{
1656 struct completion *compl = data;
1657 complete(compl);
1658}
1659
Sumit Semwal2a205f32010-12-02 11:27:12 +00001660static void _enable_lcd_out(enum omap_channel channel, bool enable)
Tomi Valkeinen80c39712009-11-12 11:41:42 +02001661{
Sumit Semwal2a205f32010-12-02 11:27:12 +00001662 if (channel == OMAP_DSS_CHANNEL_LCD2)
1663 REG_FLD_MOD(DISPC_CONTROL2, enable ? 1 : 0, 0, 0);
1664 else
1665 REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 0, 0);
Tomi Valkeinen80c39712009-11-12 11:41:42 +02001666}
1667
Sumit Semwal2a205f32010-12-02 11:27:12 +00001668static void dispc_enable_lcd_out(enum omap_channel channel, bool enable)
Tomi Valkeinen80c39712009-11-12 11:41:42 +02001669{
1670 struct completion frame_done_completion;
1671 bool is_on;
1672 int r;
Sumit Semwal2a205f32010-12-02 11:27:12 +00001673 u32 irq;
Tomi Valkeinen80c39712009-11-12 11:41:42 +02001674
1675 enable_clocks(1);
1676
1677 /* When we disable LCD output, we need to wait until frame is done.
1678 * Otherwise the DSS is still working, and turning off the clocks
1679 * prevents DSS from going to OFF mode */
Sumit Semwal2a205f32010-12-02 11:27:12 +00001680 is_on = channel == OMAP_DSS_CHANNEL_LCD2 ?
1681 REG_GET(DISPC_CONTROL2, 0, 0) :
1682 REG_GET(DISPC_CONTROL, 0, 0);
1683
1684 irq = channel == OMAP_DSS_CHANNEL_LCD2 ? DISPC_IRQ_FRAMEDONE2 :
1685 DISPC_IRQ_FRAMEDONE;
Tomi Valkeinen80c39712009-11-12 11:41:42 +02001686
1687 if (!enable && is_on) {
1688 init_completion(&frame_done_completion);
1689
1690 r = omap_dispc_register_isr(dispc_disable_isr,
Sumit Semwal2a205f32010-12-02 11:27:12 +00001691 &frame_done_completion, irq);
Tomi Valkeinen80c39712009-11-12 11:41:42 +02001692
1693 if (r)
1694 DSSERR("failed to register FRAMEDONE isr\n");
1695 }
1696
Sumit Semwal2a205f32010-12-02 11:27:12 +00001697 _enable_lcd_out(channel, enable);
Tomi Valkeinen80c39712009-11-12 11:41:42 +02001698
1699 if (!enable && is_on) {
1700 if (!wait_for_completion_timeout(&frame_done_completion,
1701 msecs_to_jiffies(100)))
1702 DSSERR("timeout waiting for FRAME DONE\n");
1703
1704 r = omap_dispc_unregister_isr(dispc_disable_isr,
Sumit Semwal2a205f32010-12-02 11:27:12 +00001705 &frame_done_completion, irq);
Tomi Valkeinen80c39712009-11-12 11:41:42 +02001706
1707 if (r)
1708 DSSERR("failed to unregister FRAMEDONE isr\n");
1709 }
1710
1711 enable_clocks(0);
1712}
1713
1714static void _enable_digit_out(bool enable)
1715{
1716 REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 1, 1);
1717}
1718
Tomi Valkeinena2faee82010-01-08 17:14:53 +02001719static void dispc_enable_digit_out(bool enable)
Tomi Valkeinen80c39712009-11-12 11:41:42 +02001720{
1721 struct completion frame_done_completion;
1722 int r;
1723
1724 enable_clocks(1);
1725
1726 if (REG_GET(DISPC_CONTROL, 1, 1) == enable) {
1727 enable_clocks(0);
1728 return;
1729 }
1730
1731 if (enable) {
1732 unsigned long flags;
1733 /* When we enable digit output, we'll get an extra digit
1734 * sync lost interrupt, that we need to ignore */
1735 spin_lock_irqsave(&dispc.irq_lock, flags);
1736 dispc.irq_error_mask &= ~DISPC_IRQ_SYNC_LOST_DIGIT;
1737 _omap_dispc_set_irqs();
1738 spin_unlock_irqrestore(&dispc.irq_lock, flags);
1739 }
1740
1741 /* When we disable digit output, we need to wait until fields are done.
1742 * Otherwise the DSS is still working, and turning off the clocks
1743 * prevents DSS from going to OFF mode. And when enabling, we need to
1744 * wait for the extra sync losts */
1745 init_completion(&frame_done_completion);
1746
1747 r = omap_dispc_register_isr(dispc_disable_isr, &frame_done_completion,
1748 DISPC_IRQ_EVSYNC_EVEN | DISPC_IRQ_EVSYNC_ODD);
1749 if (r)
1750 DSSERR("failed to register EVSYNC isr\n");
1751
1752 _enable_digit_out(enable);
1753
1754 /* XXX I understand from TRM that we should only wait for the
1755 * current field to complete. But it seems we have to wait
1756 * for both fields */
1757 if (!wait_for_completion_timeout(&frame_done_completion,
1758 msecs_to_jiffies(100)))
1759 DSSERR("timeout waiting for EVSYNC\n");
1760
1761 if (!wait_for_completion_timeout(&frame_done_completion,
1762 msecs_to_jiffies(100)))
1763 DSSERR("timeout waiting for EVSYNC\n");
1764
1765 r = omap_dispc_unregister_isr(dispc_disable_isr,
1766 &frame_done_completion,
1767 DISPC_IRQ_EVSYNC_EVEN | DISPC_IRQ_EVSYNC_ODD);
1768 if (r)
1769 DSSERR("failed to unregister EVSYNC isr\n");
1770
1771 if (enable) {
1772 unsigned long flags;
1773 spin_lock_irqsave(&dispc.irq_lock, flags);
1774 dispc.irq_error_mask = DISPC_IRQ_MASK_ERROR;
Sumit Semwal2a205f32010-12-02 11:27:12 +00001775 if (dss_has_feature(FEAT_MGR_LCD2))
1776 dispc.irq_error_mask |= DISPC_IRQ_SYNC_LOST2;
Tomi Valkeinen80c39712009-11-12 11:41:42 +02001777 dispc_write_reg(DISPC_IRQSTATUS, DISPC_IRQ_SYNC_LOST_DIGIT);
1778 _omap_dispc_set_irqs();
1779 spin_unlock_irqrestore(&dispc.irq_lock, flags);
1780 }
1781
1782 enable_clocks(0);
1783}
1784
Tomi Valkeinena2faee82010-01-08 17:14:53 +02001785bool dispc_is_channel_enabled(enum omap_channel channel)
1786{
1787 if (channel == OMAP_DSS_CHANNEL_LCD)
1788 return !!REG_GET(DISPC_CONTROL, 0, 0);
1789 else if (channel == OMAP_DSS_CHANNEL_DIGIT)
1790 return !!REG_GET(DISPC_CONTROL, 1, 1);
Sumit Semwal2a205f32010-12-02 11:27:12 +00001791 else if (channel == OMAP_DSS_CHANNEL_LCD2)
1792 return !!REG_GET(DISPC_CONTROL2, 0, 0);
Tomi Valkeinena2faee82010-01-08 17:14:53 +02001793 else
1794 BUG();
1795}
1796
1797void dispc_enable_channel(enum omap_channel channel, bool enable)
1798{
Sumit Semwal2a205f32010-12-02 11:27:12 +00001799 if (channel == OMAP_DSS_CHANNEL_LCD ||
1800 channel == OMAP_DSS_CHANNEL_LCD2)
1801 dispc_enable_lcd_out(channel, enable);
Tomi Valkeinena2faee82010-01-08 17:14:53 +02001802 else if (channel == OMAP_DSS_CHANNEL_DIGIT)
1803 dispc_enable_digit_out(enable);
1804 else
1805 BUG();
1806}
1807
Tomi Valkeinen80c39712009-11-12 11:41:42 +02001808void dispc_lcd_enable_signal_polarity(bool act_high)
1809{
Archit Taneja6ced40b2010-12-02 11:27:13 +00001810 if (!dss_has_feature(FEAT_LCDENABLEPOL))
1811 return;
1812
Tomi Valkeinen80c39712009-11-12 11:41:42 +02001813 enable_clocks(1);
1814 REG_FLD_MOD(DISPC_CONTROL, act_high ? 1 : 0, 29, 29);
1815 enable_clocks(0);
1816}
1817
1818void dispc_lcd_enable_signal(bool enable)
1819{
Archit Taneja6ced40b2010-12-02 11:27:13 +00001820 if (!dss_has_feature(FEAT_LCDENABLESIGNAL))
1821 return;
1822
Tomi Valkeinen80c39712009-11-12 11:41:42 +02001823 enable_clocks(1);
1824 REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 28, 28);
1825 enable_clocks(0);
1826}
1827
1828void dispc_pck_free_enable(bool enable)
1829{
Archit Taneja6ced40b2010-12-02 11:27:13 +00001830 if (!dss_has_feature(FEAT_PCKFREEENABLE))
1831 return;
1832
Tomi Valkeinen80c39712009-11-12 11:41:42 +02001833 enable_clocks(1);
1834 REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 27, 27);
1835 enable_clocks(0);
1836}
1837
Sumit Semwal64ba4f72010-12-02 11:27:10 +00001838void dispc_enable_fifohandcheck(enum omap_channel channel, bool enable)
Tomi Valkeinen80c39712009-11-12 11:41:42 +02001839{
1840 enable_clocks(1);
Sumit Semwal2a205f32010-12-02 11:27:12 +00001841 if (channel == OMAP_DSS_CHANNEL_LCD2)
1842 REG_FLD_MOD(DISPC_CONFIG2, enable ? 1 : 0, 16, 16);
1843 else
1844 REG_FLD_MOD(DISPC_CONFIG, enable ? 1 : 0, 16, 16);
Tomi Valkeinen80c39712009-11-12 11:41:42 +02001845 enable_clocks(0);
1846}
1847
1848
Sumit Semwal64ba4f72010-12-02 11:27:10 +00001849void dispc_set_lcd_display_type(enum omap_channel channel,
1850 enum omap_lcd_display_type type)
Tomi Valkeinen80c39712009-11-12 11:41:42 +02001851{
1852 int mode;
1853
1854 switch (type) {
1855 case OMAP_DSS_LCD_DISPLAY_STN:
1856 mode = 0;
1857 break;
1858
1859 case OMAP_DSS_LCD_DISPLAY_TFT:
1860 mode = 1;
1861 break;
1862
1863 default:
1864 BUG();
1865 return;
1866 }
1867
1868 enable_clocks(1);
Sumit Semwal2a205f32010-12-02 11:27:12 +00001869 if (channel == OMAP_DSS_CHANNEL_LCD2)
1870 REG_FLD_MOD(DISPC_CONTROL2, mode, 3, 3);
1871 else
1872 REG_FLD_MOD(DISPC_CONTROL, mode, 3, 3);
Tomi Valkeinen80c39712009-11-12 11:41:42 +02001873 enable_clocks(0);
1874}
1875
1876void dispc_set_loadmode(enum omap_dss_load_mode mode)
1877{
1878 enable_clocks(1);
1879 REG_FLD_MOD(DISPC_CONFIG, mode, 2, 1);
1880 enable_clocks(0);
1881}
1882
1883
1884void dispc_set_default_color(enum omap_channel channel, u32 color)
1885{
Tomi Valkeinen80c39712009-11-12 11:41:42 +02001886 enable_clocks(1);
Sumit Semwal8613b002010-12-02 11:27:09 +00001887 dispc_write_reg(DISPC_DEFAULT_COLOR(channel), color);
Tomi Valkeinen80c39712009-11-12 11:41:42 +02001888 enable_clocks(0);
1889}
1890
1891u32 dispc_get_default_color(enum omap_channel channel)
1892{
Tomi Valkeinen80c39712009-11-12 11:41:42 +02001893 u32 l;
1894
1895 BUG_ON(channel != OMAP_DSS_CHANNEL_DIGIT &&
Sumit Semwal2a205f32010-12-02 11:27:12 +00001896 channel != OMAP_DSS_CHANNEL_LCD &&
1897 channel != OMAP_DSS_CHANNEL_LCD2);
Tomi Valkeinen80c39712009-11-12 11:41:42 +02001898
1899 enable_clocks(1);
Sumit Semwal8613b002010-12-02 11:27:09 +00001900 l = dispc_read_reg(DISPC_DEFAULT_COLOR(channel));
Tomi Valkeinen80c39712009-11-12 11:41:42 +02001901 enable_clocks(0);
1902
1903 return l;
1904}
1905
1906void dispc_set_trans_key(enum omap_channel ch,
1907 enum omap_dss_trans_key_type type,
1908 u32 trans_key)
1909{
Tomi Valkeinen80c39712009-11-12 11:41:42 +02001910 enable_clocks(1);
1911 if (ch == OMAP_DSS_CHANNEL_LCD)
1912 REG_FLD_MOD(DISPC_CONFIG, type, 11, 11);
Sumit Semwal2a205f32010-12-02 11:27:12 +00001913 else if (ch == OMAP_DSS_CHANNEL_DIGIT)
Tomi Valkeinen80c39712009-11-12 11:41:42 +02001914 REG_FLD_MOD(DISPC_CONFIG, type, 13, 13);
Sumit Semwal2a205f32010-12-02 11:27:12 +00001915 else /* OMAP_DSS_CHANNEL_LCD2 */
1916 REG_FLD_MOD(DISPC_CONFIG2, type, 11, 11);
Tomi Valkeinen80c39712009-11-12 11:41:42 +02001917
Sumit Semwal8613b002010-12-02 11:27:09 +00001918 dispc_write_reg(DISPC_TRANS_COLOR(ch), trans_key);
Tomi Valkeinen80c39712009-11-12 11:41:42 +02001919 enable_clocks(0);
1920}
1921
1922void dispc_get_trans_key(enum omap_channel ch,
1923 enum omap_dss_trans_key_type *type,
1924 u32 *trans_key)
1925{
Tomi Valkeinen80c39712009-11-12 11:41:42 +02001926 enable_clocks(1);
1927 if (type) {
1928 if (ch == OMAP_DSS_CHANNEL_LCD)
1929 *type = REG_GET(DISPC_CONFIG, 11, 11);
1930 else if (ch == OMAP_DSS_CHANNEL_DIGIT)
1931 *type = REG_GET(DISPC_CONFIG, 13, 13);
Sumit Semwal2a205f32010-12-02 11:27:12 +00001932 else if (ch == OMAP_DSS_CHANNEL_LCD2)
1933 *type = REG_GET(DISPC_CONFIG2, 11, 11);
Tomi Valkeinen80c39712009-11-12 11:41:42 +02001934 else
1935 BUG();
1936 }
1937
1938 if (trans_key)
Sumit Semwal8613b002010-12-02 11:27:09 +00001939 *trans_key = dispc_read_reg(DISPC_TRANS_COLOR(ch));
Tomi Valkeinen80c39712009-11-12 11:41:42 +02001940 enable_clocks(0);
1941}
1942
1943void dispc_enable_trans_key(enum omap_channel ch, bool enable)
1944{
1945 enable_clocks(1);
1946 if (ch == OMAP_DSS_CHANNEL_LCD)
1947 REG_FLD_MOD(DISPC_CONFIG, enable, 10, 10);
Sumit Semwal2a205f32010-12-02 11:27:12 +00001948 else if (ch == OMAP_DSS_CHANNEL_DIGIT)
Tomi Valkeinen80c39712009-11-12 11:41:42 +02001949 REG_FLD_MOD(DISPC_CONFIG, enable, 12, 12);
Sumit Semwal2a205f32010-12-02 11:27:12 +00001950 else /* OMAP_DSS_CHANNEL_LCD2 */
1951 REG_FLD_MOD(DISPC_CONFIG2, enable, 10, 10);
Tomi Valkeinen80c39712009-11-12 11:41:42 +02001952 enable_clocks(0);
1953}
1954void dispc_enable_alpha_blending(enum omap_channel ch, bool enable)
1955{
Archit Tanejaa0acb552010-09-15 19:20:00 +05301956 if (!dss_has_feature(FEAT_GLOBAL_ALPHA))
Tomi Valkeinen80c39712009-11-12 11:41:42 +02001957 return;
1958
1959 enable_clocks(1);
1960 if (ch == OMAP_DSS_CHANNEL_LCD)
1961 REG_FLD_MOD(DISPC_CONFIG, enable, 18, 18);
Sumit Semwal2a205f32010-12-02 11:27:12 +00001962 else if (ch == OMAP_DSS_CHANNEL_DIGIT)
Tomi Valkeinen80c39712009-11-12 11:41:42 +02001963 REG_FLD_MOD(DISPC_CONFIG, enable, 19, 19);
Sumit Semwal2a205f32010-12-02 11:27:12 +00001964 else /* OMAP_DSS_CHANNEL_LCD2 */
1965 REG_FLD_MOD(DISPC_CONFIG2, enable, 18, 18);
Tomi Valkeinen80c39712009-11-12 11:41:42 +02001966 enable_clocks(0);
1967}
1968bool dispc_alpha_blending_enabled(enum omap_channel ch)
1969{
1970 bool enabled;
1971
Archit Tanejaa0acb552010-09-15 19:20:00 +05301972 if (!dss_has_feature(FEAT_GLOBAL_ALPHA))
Tomi Valkeinen80c39712009-11-12 11:41:42 +02001973 return false;
1974
1975 enable_clocks(1);
1976 if (ch == OMAP_DSS_CHANNEL_LCD)
1977 enabled = REG_GET(DISPC_CONFIG, 18, 18);
1978 else if (ch == OMAP_DSS_CHANNEL_DIGIT)
Archit Taneja712247a2010-11-08 12:56:21 +01001979 enabled = REG_GET(DISPC_CONFIG, 19, 19);
Sumit Semwal2a205f32010-12-02 11:27:12 +00001980 else if (ch == OMAP_DSS_CHANNEL_LCD2)
1981 enabled = REG_GET(DISPC_CONFIG2, 18, 18);
Tomi Valkeinen80c39712009-11-12 11:41:42 +02001982 else
1983 BUG();
1984 enable_clocks(0);
1985
1986 return enabled;
Tomi Valkeinen80c39712009-11-12 11:41:42 +02001987}
1988
1989
1990bool dispc_trans_key_enabled(enum omap_channel ch)
1991{
1992 bool enabled;
1993
1994 enable_clocks(1);
1995 if (ch == OMAP_DSS_CHANNEL_LCD)
1996 enabled = REG_GET(DISPC_CONFIG, 10, 10);
1997 else if (ch == OMAP_DSS_CHANNEL_DIGIT)
1998 enabled = REG_GET(DISPC_CONFIG, 12, 12);
Sumit Semwal2a205f32010-12-02 11:27:12 +00001999 else if (ch == OMAP_DSS_CHANNEL_LCD2)
2000 enabled = REG_GET(DISPC_CONFIG2, 10, 10);
Tomi Valkeinen80c39712009-11-12 11:41:42 +02002001 else
2002 BUG();
2003 enable_clocks(0);
2004
2005 return enabled;
2006}
2007
2008
Sumit Semwal64ba4f72010-12-02 11:27:10 +00002009void dispc_set_tft_data_lines(enum omap_channel channel, u8 data_lines)
Tomi Valkeinen80c39712009-11-12 11:41:42 +02002010{
2011 int code;
2012
2013 switch (data_lines) {
2014 case 12:
2015 code = 0;
2016 break;
2017 case 16:
2018 code = 1;
2019 break;
2020 case 18:
2021 code = 2;
2022 break;
2023 case 24:
2024 code = 3;
2025 break;
2026 default:
2027 BUG();
2028 return;
2029 }
2030
2031 enable_clocks(1);
Sumit Semwal2a205f32010-12-02 11:27:12 +00002032 if (channel == OMAP_DSS_CHANNEL_LCD2)
2033 REG_FLD_MOD(DISPC_CONTROL2, code, 9, 8);
2034 else
2035 REG_FLD_MOD(DISPC_CONTROL, code, 9, 8);
Tomi Valkeinen80c39712009-11-12 11:41:42 +02002036 enable_clocks(0);
2037}
2038
Sumit Semwal64ba4f72010-12-02 11:27:10 +00002039void dispc_set_parallel_interface_mode(enum omap_channel channel,
2040 enum omap_parallel_interface_mode mode)
Tomi Valkeinen80c39712009-11-12 11:41:42 +02002041{
2042 u32 l;
2043 int stallmode;
2044 int gpout0 = 1;
2045 int gpout1;
2046
2047 switch (mode) {
2048 case OMAP_DSS_PARALLELMODE_BYPASS:
2049 stallmode = 0;
2050 gpout1 = 1;
2051 break;
2052
2053 case OMAP_DSS_PARALLELMODE_RFBI:
2054 stallmode = 1;
2055 gpout1 = 0;
2056 break;
2057
2058 case OMAP_DSS_PARALLELMODE_DSI:
2059 stallmode = 1;
2060 gpout1 = 1;
2061 break;
2062
2063 default:
2064 BUG();
2065 return;
2066 }
2067
2068 enable_clocks(1);
2069
Sumit Semwal2a205f32010-12-02 11:27:12 +00002070 if (channel == OMAP_DSS_CHANNEL_LCD2) {
2071 l = dispc_read_reg(DISPC_CONTROL2);
2072 l = FLD_MOD(l, stallmode, 11, 11);
2073 dispc_write_reg(DISPC_CONTROL2, l);
2074 } else {
2075 l = dispc_read_reg(DISPC_CONTROL);
2076 l = FLD_MOD(l, stallmode, 11, 11);
Sumit Semwal64ba4f72010-12-02 11:27:10 +00002077 l = FLD_MOD(l, gpout0, 15, 15);
2078 l = FLD_MOD(l, gpout1, 16, 16);
Sumit Semwal2a205f32010-12-02 11:27:12 +00002079 dispc_write_reg(DISPC_CONTROL, l);
Sumit Semwal64ba4f72010-12-02 11:27:10 +00002080 }
Tomi Valkeinen80c39712009-11-12 11:41:42 +02002081
2082 enable_clocks(0);
2083}
2084
2085static bool _dispc_lcd_timings_ok(int hsw, int hfp, int hbp,
2086 int vsw, int vfp, int vbp)
2087{
2088 if (cpu_is_omap24xx() || omap_rev() < OMAP3430_REV_ES3_0) {
2089 if (hsw < 1 || hsw > 64 ||
2090 hfp < 1 || hfp > 256 ||
2091 hbp < 1 || hbp > 256 ||
2092 vsw < 1 || vsw > 64 ||
2093 vfp < 0 || vfp > 255 ||
2094 vbp < 0 || vbp > 255)
2095 return false;
2096 } else {
2097 if (hsw < 1 || hsw > 256 ||
2098 hfp < 1 || hfp > 4096 ||
2099 hbp < 1 || hbp > 4096 ||
2100 vsw < 1 || vsw > 256 ||
2101 vfp < 0 || vfp > 4095 ||
2102 vbp < 0 || vbp > 4095)
2103 return false;
2104 }
2105
2106 return true;
2107}
2108
2109bool dispc_lcd_timings_ok(struct omap_video_timings *timings)
2110{
2111 return _dispc_lcd_timings_ok(timings->hsw, timings->hfp,
2112 timings->hbp, timings->vsw,
2113 timings->vfp, timings->vbp);
2114}
2115
Sumit Semwal64ba4f72010-12-02 11:27:10 +00002116static void _dispc_set_lcd_timings(enum omap_channel channel, int hsw,
2117 int hfp, int hbp, int vsw, int vfp, int vbp)
Tomi Valkeinen80c39712009-11-12 11:41:42 +02002118{
2119 u32 timing_h, timing_v;
2120
2121 if (cpu_is_omap24xx() || omap_rev() < OMAP3430_REV_ES3_0) {
2122 timing_h = FLD_VAL(hsw-1, 5, 0) | FLD_VAL(hfp-1, 15, 8) |
2123 FLD_VAL(hbp-1, 27, 20);
2124
2125 timing_v = FLD_VAL(vsw-1, 5, 0) | FLD_VAL(vfp, 15, 8) |
2126 FLD_VAL(vbp, 27, 20);
2127 } else {
2128 timing_h = FLD_VAL(hsw-1, 7, 0) | FLD_VAL(hfp-1, 19, 8) |
2129 FLD_VAL(hbp-1, 31, 20);
2130
2131 timing_v = FLD_VAL(vsw-1, 7, 0) | FLD_VAL(vfp, 19, 8) |
2132 FLD_VAL(vbp, 31, 20);
2133 }
2134
2135 enable_clocks(1);
Sumit Semwal64ba4f72010-12-02 11:27:10 +00002136 dispc_write_reg(DISPC_TIMING_H(channel), timing_h);
2137 dispc_write_reg(DISPC_TIMING_V(channel), timing_v);
Tomi Valkeinen80c39712009-11-12 11:41:42 +02002138 enable_clocks(0);
2139}
2140
2141/* change name to mode? */
Sumit Semwal64ba4f72010-12-02 11:27:10 +00002142void dispc_set_lcd_timings(enum omap_channel channel,
2143 struct omap_video_timings *timings)
Tomi Valkeinen80c39712009-11-12 11:41:42 +02002144{
2145 unsigned xtot, ytot;
2146 unsigned long ht, vt;
2147
2148 if (!_dispc_lcd_timings_ok(timings->hsw, timings->hfp,
2149 timings->hbp, timings->vsw,
2150 timings->vfp, timings->vbp))
2151 BUG();
2152
Sumit Semwal64ba4f72010-12-02 11:27:10 +00002153 _dispc_set_lcd_timings(channel, timings->hsw, timings->hfp,
2154 timings->hbp, timings->vsw, timings->vfp,
2155 timings->vbp);
Tomi Valkeinen80c39712009-11-12 11:41:42 +02002156
Sumit Semwal64ba4f72010-12-02 11:27:10 +00002157 dispc_set_lcd_size(channel, timings->x_res, timings->y_res);
Tomi Valkeinen80c39712009-11-12 11:41:42 +02002158
2159 xtot = timings->x_res + timings->hfp + timings->hsw + timings->hbp;
2160 ytot = timings->y_res + timings->vfp + timings->vsw + timings->vbp;
2161
2162 ht = (timings->pixel_clock * 1000) / xtot;
2163 vt = (timings->pixel_clock * 1000) / xtot / ytot;
2164
Sumit Semwal2a205f32010-12-02 11:27:12 +00002165 DSSDBG("channel %d xres %u yres %u\n", channel, timings->x_res,
2166 timings->y_res);
Tomi Valkeinen80c39712009-11-12 11:41:42 +02002167 DSSDBG("pck %u\n", timings->pixel_clock);
2168 DSSDBG("hsw %d hfp %d hbp %d vsw %d vfp %d vbp %d\n",
2169 timings->hsw, timings->hfp, timings->hbp,
2170 timings->vsw, timings->vfp, timings->vbp);
2171
2172 DSSDBG("hsync %luHz, vsync %luHz\n", ht, vt);
2173}
2174
Sumit Semwalff1b2cd2010-12-02 11:27:11 +00002175static void dispc_set_lcd_divisor(enum omap_channel channel, u16 lck_div,
2176 u16 pck_div)
Tomi Valkeinen80c39712009-11-12 11:41:42 +02002177{
2178 BUG_ON(lck_div < 1);
2179 BUG_ON(pck_div < 2);
2180
2181 enable_clocks(1);
Murthy, Raghuveerce7fa5e2011-03-03 09:27:59 -06002182 dispc_write_reg(DISPC_DIVISORo(channel),
Tomi Valkeinen80c39712009-11-12 11:41:42 +02002183 FLD_VAL(lck_div, 23, 16) | FLD_VAL(pck_div, 7, 0));
2184 enable_clocks(0);
2185}
2186
Sumit Semwal2a205f32010-12-02 11:27:12 +00002187static void dispc_get_lcd_divisor(enum omap_channel channel, int *lck_div,
2188 int *pck_div)
Tomi Valkeinen80c39712009-11-12 11:41:42 +02002189{
2190 u32 l;
Murthy, Raghuveerce7fa5e2011-03-03 09:27:59 -06002191 l = dispc_read_reg(DISPC_DIVISORo(channel));
Tomi Valkeinen80c39712009-11-12 11:41:42 +02002192 *lck_div = FLD_GET(l, 23, 16);
2193 *pck_div = FLD_GET(l, 7, 0);
2194}
2195
2196unsigned long dispc_fclk_rate(void)
2197{
Archit Tanejaa72b64b2011-05-12 17:26:26 +05302198 struct platform_device *dsidev;
Tomi Valkeinen80c39712009-11-12 11:41:42 +02002199 unsigned long r = 0;
2200
Taneja, Archit66534e82011-03-08 05:50:34 -06002201 switch (dss_get_dispc_clk_source()) {
Archit Taneja89a35e52011-04-12 13:52:23 +05302202 case OMAP_DSS_CLK_SRC_FCK:
Archit Taneja6af9cd12011-01-31 16:27:44 +00002203 r = dss_clk_get_rate(DSS_CLK_FCK);
Taneja, Archit66534e82011-03-08 05:50:34 -06002204 break;
Archit Taneja89a35e52011-04-12 13:52:23 +05302205 case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC:
Archit Tanejaa72b64b2011-05-12 17:26:26 +05302206 dsidev = dsi_get_dsidev_from_id(0);
2207 r = dsi_get_pll_hsdiv_dispc_rate(dsidev);
Taneja, Archit66534e82011-03-08 05:50:34 -06002208 break;
Archit Taneja5a8b5722011-05-12 17:26:29 +05302209 case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC:
2210 dsidev = dsi_get_dsidev_from_id(1);
2211 r = dsi_get_pll_hsdiv_dispc_rate(dsidev);
2212 break;
Taneja, Archit66534e82011-03-08 05:50:34 -06002213 default:
2214 BUG();
2215 }
2216
Tomi Valkeinen80c39712009-11-12 11:41:42 +02002217 return r;
2218}
2219
Sumit Semwalff1b2cd2010-12-02 11:27:11 +00002220unsigned long dispc_lclk_rate(enum omap_channel channel)
Tomi Valkeinen80c39712009-11-12 11:41:42 +02002221{
Archit Tanejaa72b64b2011-05-12 17:26:26 +05302222 struct platform_device *dsidev;
Tomi Valkeinen80c39712009-11-12 11:41:42 +02002223 int lcd;
2224 unsigned long r;
2225 u32 l;
2226
Murthy, Raghuveerce7fa5e2011-03-03 09:27:59 -06002227 l = dispc_read_reg(DISPC_DIVISORo(channel));
Tomi Valkeinen80c39712009-11-12 11:41:42 +02002228
2229 lcd = FLD_GET(l, 23, 16);
2230
Taneja, Architea751592011-03-08 05:50:35 -06002231 switch (dss_get_lcd_clk_source(channel)) {
Archit Taneja89a35e52011-04-12 13:52:23 +05302232 case OMAP_DSS_CLK_SRC_FCK:
Taneja, Architea751592011-03-08 05:50:35 -06002233 r = dss_clk_get_rate(DSS_CLK_FCK);
2234 break;
Archit Taneja89a35e52011-04-12 13:52:23 +05302235 case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC:
Archit Tanejaa72b64b2011-05-12 17:26:26 +05302236 dsidev = dsi_get_dsidev_from_id(0);
2237 r = dsi_get_pll_hsdiv_dispc_rate(dsidev);
Taneja, Architea751592011-03-08 05:50:35 -06002238 break;
Archit Taneja5a8b5722011-05-12 17:26:29 +05302239 case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC:
2240 dsidev = dsi_get_dsidev_from_id(1);
2241 r = dsi_get_pll_hsdiv_dispc_rate(dsidev);
2242 break;
Taneja, Architea751592011-03-08 05:50:35 -06002243 default:
2244 BUG();
2245 }
Tomi Valkeinen80c39712009-11-12 11:41:42 +02002246
2247 return r / lcd;
2248}
2249
Sumit Semwalff1b2cd2010-12-02 11:27:11 +00002250unsigned long dispc_pclk_rate(enum omap_channel channel)
Tomi Valkeinen80c39712009-11-12 11:41:42 +02002251{
Taneja, Architea751592011-03-08 05:50:35 -06002252 int pcd;
Tomi Valkeinen80c39712009-11-12 11:41:42 +02002253 unsigned long r;
2254 u32 l;
2255
Murthy, Raghuveerce7fa5e2011-03-03 09:27:59 -06002256 l = dispc_read_reg(DISPC_DIVISORo(channel));
Tomi Valkeinen80c39712009-11-12 11:41:42 +02002257
Tomi Valkeinen80c39712009-11-12 11:41:42 +02002258 pcd = FLD_GET(l, 7, 0);
2259
Taneja, Architea751592011-03-08 05:50:35 -06002260 r = dispc_lclk_rate(channel);
Tomi Valkeinen80c39712009-11-12 11:41:42 +02002261
Taneja, Architea751592011-03-08 05:50:35 -06002262 return r / pcd;
Tomi Valkeinen80c39712009-11-12 11:41:42 +02002263}
2264
2265void dispc_dump_clocks(struct seq_file *s)
2266{
2267 int lcd, pcd;
Murthy, Raghuveer0cf35df2011-03-03 09:28:00 -06002268 u32 l;
Archit Taneja89a35e52011-04-12 13:52:23 +05302269 enum omap_dss_clk_source dispc_clk_src = dss_get_dispc_clk_source();
2270 enum omap_dss_clk_source lcd_clk_src;
Tomi Valkeinen80c39712009-11-12 11:41:42 +02002271
2272 enable_clocks(1);
2273
Tomi Valkeinen80c39712009-11-12 11:41:42 +02002274 seq_printf(s, "- DISPC -\n");
2275
Archit Taneja067a57e2011-03-02 11:57:25 +05302276 seq_printf(s, "dispc fclk source = %s (%s)\n",
2277 dss_get_generic_clk_source_name(dispc_clk_src),
2278 dss_feat_get_clk_source_name(dispc_clk_src));
Tomi Valkeinen80c39712009-11-12 11:41:42 +02002279
2280 seq_printf(s, "fck\t\t%-16lu\n", dispc_fclk_rate());
Sumit Semwal2a205f32010-12-02 11:27:12 +00002281
Murthy, Raghuveer0cf35df2011-03-03 09:28:00 -06002282 if (dss_has_feature(FEAT_CORE_CLK_DIV)) {
2283 seq_printf(s, "- DISPC-CORE-CLK -\n");
2284 l = dispc_read_reg(DISPC_DIVISOR);
2285 lcd = FLD_GET(l, 23, 16);
2286
2287 seq_printf(s, "lck\t\t%-16lulck div\t%u\n",
2288 (dispc_fclk_rate()/lcd), lcd);
2289 }
Sumit Semwal2a205f32010-12-02 11:27:12 +00002290 seq_printf(s, "- LCD1 -\n");
2291
Taneja, Architea751592011-03-08 05:50:35 -06002292 lcd_clk_src = dss_get_lcd_clk_source(OMAP_DSS_CHANNEL_LCD);
2293
2294 seq_printf(s, "lcd1_clk source = %s (%s)\n",
2295 dss_get_generic_clk_source_name(lcd_clk_src),
2296 dss_feat_get_clk_source_name(lcd_clk_src));
2297
Sumit Semwal2a205f32010-12-02 11:27:12 +00002298 dispc_get_lcd_divisor(OMAP_DSS_CHANNEL_LCD, &lcd, &pcd);
2299
Sumit Semwalff1b2cd2010-12-02 11:27:11 +00002300 seq_printf(s, "lck\t\t%-16lulck div\t%u\n",
2301 dispc_lclk_rate(OMAP_DSS_CHANNEL_LCD), lcd);
2302 seq_printf(s, "pck\t\t%-16lupck div\t%u\n",
2303 dispc_pclk_rate(OMAP_DSS_CHANNEL_LCD), pcd);
Sumit Semwal2a205f32010-12-02 11:27:12 +00002304 if (dss_has_feature(FEAT_MGR_LCD2)) {
2305 seq_printf(s, "- LCD2 -\n");
Tomi Valkeinen80c39712009-11-12 11:41:42 +02002306
Taneja, Architea751592011-03-08 05:50:35 -06002307 lcd_clk_src = dss_get_lcd_clk_source(OMAP_DSS_CHANNEL_LCD2);
2308
2309 seq_printf(s, "lcd2_clk source = %s (%s)\n",
2310 dss_get_generic_clk_source_name(lcd_clk_src),
2311 dss_feat_get_clk_source_name(lcd_clk_src));
2312
Sumit Semwal2a205f32010-12-02 11:27:12 +00002313 dispc_get_lcd_divisor(OMAP_DSS_CHANNEL_LCD2, &lcd, &pcd);
2314
2315 seq_printf(s, "lck\t\t%-16lulck div\t%u\n",
2316 dispc_lclk_rate(OMAP_DSS_CHANNEL_LCD2), lcd);
2317 seq_printf(s, "pck\t\t%-16lupck div\t%u\n",
2318 dispc_pclk_rate(OMAP_DSS_CHANNEL_LCD2), pcd);
2319 }
Tomi Valkeinen80c39712009-11-12 11:41:42 +02002320 enable_clocks(0);
2321}
2322
Tomi Valkeinendfc0fd82009-12-17 14:35:21 +02002323#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
2324void dispc_dump_irqs(struct seq_file *s)
2325{
2326 unsigned long flags;
2327 struct dispc_irq_stats stats;
2328
2329 spin_lock_irqsave(&dispc.irq_stats_lock, flags);
2330
2331 stats = dispc.irq_stats;
2332 memset(&dispc.irq_stats, 0, sizeof(dispc.irq_stats));
2333 dispc.irq_stats.last_reset = jiffies;
2334
2335 spin_unlock_irqrestore(&dispc.irq_stats_lock, flags);
2336
2337 seq_printf(s, "period %u ms\n",
2338 jiffies_to_msecs(jiffies - stats.last_reset));
2339
2340 seq_printf(s, "irqs %d\n", stats.irq_count);
2341#define PIS(x) \
2342 seq_printf(s, "%-20s %10d\n", #x, stats.irqs[ffs(DISPC_IRQ_##x)-1]);
2343
2344 PIS(FRAMEDONE);
2345 PIS(VSYNC);
2346 PIS(EVSYNC_EVEN);
2347 PIS(EVSYNC_ODD);
2348 PIS(ACBIAS_COUNT_STAT);
2349 PIS(PROG_LINE_NUM);
2350 PIS(GFX_FIFO_UNDERFLOW);
2351 PIS(GFX_END_WIN);
2352 PIS(PAL_GAMMA_MASK);
2353 PIS(OCP_ERR);
2354 PIS(VID1_FIFO_UNDERFLOW);
2355 PIS(VID1_END_WIN);
2356 PIS(VID2_FIFO_UNDERFLOW);
2357 PIS(VID2_END_WIN);
2358 PIS(SYNC_LOST);
2359 PIS(SYNC_LOST_DIGIT);
2360 PIS(WAKEUP);
Sumit Semwal2a205f32010-12-02 11:27:12 +00002361 if (dss_has_feature(FEAT_MGR_LCD2)) {
2362 PIS(FRAMEDONE2);
2363 PIS(VSYNC2);
2364 PIS(ACBIAS_COUNT_STAT2);
2365 PIS(SYNC_LOST2);
2366 }
Tomi Valkeinendfc0fd82009-12-17 14:35:21 +02002367#undef PIS
2368}
Tomi Valkeinendfc0fd82009-12-17 14:35:21 +02002369#endif
2370
Tomi Valkeinen80c39712009-11-12 11:41:42 +02002371void dispc_dump_regs(struct seq_file *s)
2372{
Archit Taneja9b372c22011-05-06 11:45:49 +05302373#define DUMPREG(r) seq_printf(s, "%-50s %08x\n", #r, dispc_read_reg(r))
Tomi Valkeinen80c39712009-11-12 11:41:42 +02002374
Archit Taneja6af9cd12011-01-31 16:27:44 +00002375 dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK);
Tomi Valkeinen80c39712009-11-12 11:41:42 +02002376
2377 DUMPREG(DISPC_REVISION);
2378 DUMPREG(DISPC_SYSCONFIG);
2379 DUMPREG(DISPC_SYSSTATUS);
2380 DUMPREG(DISPC_IRQSTATUS);
2381 DUMPREG(DISPC_IRQENABLE);
2382 DUMPREG(DISPC_CONTROL);
2383 DUMPREG(DISPC_CONFIG);
2384 DUMPREG(DISPC_CAPABLE);
Archit Taneja702d1442011-05-06 11:45:50 +05302385 DUMPREG(DISPC_DEFAULT_COLOR(OMAP_DSS_CHANNEL_LCD));
2386 DUMPREG(DISPC_DEFAULT_COLOR(OMAP_DSS_CHANNEL_DIGIT));
2387 DUMPREG(DISPC_TRANS_COLOR(OMAP_DSS_CHANNEL_LCD));
2388 DUMPREG(DISPC_TRANS_COLOR(OMAP_DSS_CHANNEL_DIGIT));
Tomi Valkeinen80c39712009-11-12 11:41:42 +02002389 DUMPREG(DISPC_LINE_STATUS);
2390 DUMPREG(DISPC_LINE_NUMBER);
Archit Taneja702d1442011-05-06 11:45:50 +05302391 DUMPREG(DISPC_TIMING_H(OMAP_DSS_CHANNEL_LCD));
2392 DUMPREG(DISPC_TIMING_V(OMAP_DSS_CHANNEL_LCD));
2393 DUMPREG(DISPC_POL_FREQ(OMAP_DSS_CHANNEL_LCD));
2394 DUMPREG(DISPC_DIVISORo(OMAP_DSS_CHANNEL_LCD));
Tomi Valkeinen80c39712009-11-12 11:41:42 +02002395 DUMPREG(DISPC_GLOBAL_ALPHA);
Archit Taneja702d1442011-05-06 11:45:50 +05302396 DUMPREG(DISPC_SIZE_MGR(OMAP_DSS_CHANNEL_DIGIT));
2397 DUMPREG(DISPC_SIZE_MGR(OMAP_DSS_CHANNEL_LCD));
Sumit Semwal2a205f32010-12-02 11:27:12 +00002398 if (dss_has_feature(FEAT_MGR_LCD2)) {
2399 DUMPREG(DISPC_CONTROL2);
2400 DUMPREG(DISPC_CONFIG2);
Archit Taneja702d1442011-05-06 11:45:50 +05302401 DUMPREG(DISPC_DEFAULT_COLOR(OMAP_DSS_CHANNEL_LCD2));
2402 DUMPREG(DISPC_TRANS_COLOR(OMAP_DSS_CHANNEL_LCD2));
2403 DUMPREG(DISPC_TIMING_H(OMAP_DSS_CHANNEL_LCD2));
2404 DUMPREG(DISPC_TIMING_V(OMAP_DSS_CHANNEL_LCD2));
2405 DUMPREG(DISPC_POL_FREQ(OMAP_DSS_CHANNEL_LCD2));
2406 DUMPREG(DISPC_DIVISORo(OMAP_DSS_CHANNEL_LCD2));
2407 DUMPREG(DISPC_SIZE_MGR(OMAP_DSS_CHANNEL_LCD2));
Sumit Semwal2a205f32010-12-02 11:27:12 +00002408 }
Tomi Valkeinen80c39712009-11-12 11:41:42 +02002409
Archit Taneja9b372c22011-05-06 11:45:49 +05302410 DUMPREG(DISPC_OVL_BA0(OMAP_DSS_GFX));
2411 DUMPREG(DISPC_OVL_BA1(OMAP_DSS_GFX));
2412 DUMPREG(DISPC_OVL_POSITION(OMAP_DSS_GFX));
2413 DUMPREG(DISPC_OVL_SIZE(OMAP_DSS_GFX));
2414 DUMPREG(DISPC_OVL_ATTRIBUTES(OMAP_DSS_GFX));
2415 DUMPREG(DISPC_OVL_FIFO_THRESHOLD(OMAP_DSS_GFX));
2416 DUMPREG(DISPC_OVL_FIFO_SIZE_STATUS(OMAP_DSS_GFX));
2417 DUMPREG(DISPC_OVL_ROW_INC(OMAP_DSS_GFX));
2418 DUMPREG(DISPC_OVL_PIXEL_INC(OMAP_DSS_GFX));
2419 DUMPREG(DISPC_OVL_WINDOW_SKIP(OMAP_DSS_GFX));
2420 DUMPREG(DISPC_OVL_TABLE_BA(OMAP_DSS_GFX));
Tomi Valkeinen80c39712009-11-12 11:41:42 +02002421
Archit Taneja702d1442011-05-06 11:45:50 +05302422 DUMPREG(DISPC_DATA_CYCLE1(OMAP_DSS_CHANNEL_LCD));
2423 DUMPREG(DISPC_DATA_CYCLE2(OMAP_DSS_CHANNEL_LCD));
2424 DUMPREG(DISPC_DATA_CYCLE3(OMAP_DSS_CHANNEL_LCD));
Tomi Valkeinen80c39712009-11-12 11:41:42 +02002425
Archit Taneja702d1442011-05-06 11:45:50 +05302426 DUMPREG(DISPC_CPR_COEF_R(OMAP_DSS_CHANNEL_LCD));
2427 DUMPREG(DISPC_CPR_COEF_G(OMAP_DSS_CHANNEL_LCD));
2428 DUMPREG(DISPC_CPR_COEF_B(OMAP_DSS_CHANNEL_LCD));
Sumit Semwal2a205f32010-12-02 11:27:12 +00002429 if (dss_has_feature(FEAT_MGR_LCD2)) {
Archit Taneja702d1442011-05-06 11:45:50 +05302430 DUMPREG(DISPC_DATA_CYCLE1(OMAP_DSS_CHANNEL_LCD2));
2431 DUMPREG(DISPC_DATA_CYCLE2(OMAP_DSS_CHANNEL_LCD2));
2432 DUMPREG(DISPC_DATA_CYCLE3(OMAP_DSS_CHANNEL_LCD2));
Sumit Semwal2a205f32010-12-02 11:27:12 +00002433
Archit Taneja702d1442011-05-06 11:45:50 +05302434 DUMPREG(DISPC_CPR_COEF_R(OMAP_DSS_CHANNEL_LCD2));
2435 DUMPREG(DISPC_CPR_COEF_G(OMAP_DSS_CHANNEL_LCD2));
2436 DUMPREG(DISPC_CPR_COEF_B(OMAP_DSS_CHANNEL_LCD2));
Sumit Semwal2a205f32010-12-02 11:27:12 +00002437 }
Tomi Valkeinen80c39712009-11-12 11:41:42 +02002438
Archit Taneja9b372c22011-05-06 11:45:49 +05302439 DUMPREG(DISPC_OVL_PRELOAD(OMAP_DSS_GFX));
Tomi Valkeinen80c39712009-11-12 11:41:42 +02002440
Archit Taneja9b372c22011-05-06 11:45:49 +05302441 DUMPREG(DISPC_OVL_BA0(OMAP_DSS_VIDEO1));
2442 DUMPREG(DISPC_OVL_BA1(OMAP_DSS_VIDEO1));
2443 DUMPREG(DISPC_OVL_POSITION(OMAP_DSS_VIDEO1));
2444 DUMPREG(DISPC_OVL_SIZE(OMAP_DSS_VIDEO1));
2445 DUMPREG(DISPC_OVL_ATTRIBUTES(OMAP_DSS_VIDEO1));
2446 DUMPREG(DISPC_OVL_FIFO_THRESHOLD(OMAP_DSS_VIDEO1));
2447 DUMPREG(DISPC_OVL_FIFO_SIZE_STATUS(OMAP_DSS_VIDEO1));
2448 DUMPREG(DISPC_OVL_ROW_INC(OMAP_DSS_VIDEO1));
2449 DUMPREG(DISPC_OVL_PIXEL_INC(OMAP_DSS_VIDEO1));
2450 DUMPREG(DISPC_OVL_FIR(OMAP_DSS_VIDEO1));
2451 DUMPREG(DISPC_OVL_PICTURE_SIZE(OMAP_DSS_VIDEO1));
2452 DUMPREG(DISPC_OVL_ACCU0(OMAP_DSS_VIDEO1));
2453 DUMPREG(DISPC_OVL_ACCU1(OMAP_DSS_VIDEO1));
Tomi Valkeinen80c39712009-11-12 11:41:42 +02002454
Archit Taneja9b372c22011-05-06 11:45:49 +05302455 DUMPREG(DISPC_OVL_BA0(OMAP_DSS_VIDEO2));
2456 DUMPREG(DISPC_OVL_BA1(OMAP_DSS_VIDEO2));
2457 DUMPREG(DISPC_OVL_POSITION(OMAP_DSS_VIDEO2));
2458 DUMPREG(DISPC_OVL_SIZE(OMAP_DSS_VIDEO2));
2459 DUMPREG(DISPC_OVL_ATTRIBUTES(OMAP_DSS_VIDEO2));
2460 DUMPREG(DISPC_OVL_FIFO_THRESHOLD(OMAP_DSS_VIDEO2));
2461 DUMPREG(DISPC_OVL_FIFO_SIZE_STATUS(OMAP_DSS_VIDEO2));
2462 DUMPREG(DISPC_OVL_ROW_INC(OMAP_DSS_VIDEO2));
2463 DUMPREG(DISPC_OVL_PIXEL_INC(OMAP_DSS_VIDEO2));
2464 DUMPREG(DISPC_OVL_FIR(OMAP_DSS_VIDEO2));
2465 DUMPREG(DISPC_OVL_PICTURE_SIZE(OMAP_DSS_VIDEO2));
2466 DUMPREG(DISPC_OVL_ACCU0(OMAP_DSS_VIDEO2));
2467 DUMPREG(DISPC_OVL_ACCU1(OMAP_DSS_VIDEO2));
Tomi Valkeinen80c39712009-11-12 11:41:42 +02002468
Archit Taneja9b372c22011-05-06 11:45:49 +05302469 DUMPREG(DISPC_OVL_FIR_COEF_H(OMAP_DSS_VIDEO1, 0));
2470 DUMPREG(DISPC_OVL_FIR_COEF_H(OMAP_DSS_VIDEO1, 1));
2471 DUMPREG(DISPC_OVL_FIR_COEF_H(OMAP_DSS_VIDEO1, 2));
2472 DUMPREG(DISPC_OVL_FIR_COEF_H(OMAP_DSS_VIDEO1, 3));
2473 DUMPREG(DISPC_OVL_FIR_COEF_H(OMAP_DSS_VIDEO1, 4));
2474 DUMPREG(DISPC_OVL_FIR_COEF_H(OMAP_DSS_VIDEO1, 5));
2475 DUMPREG(DISPC_OVL_FIR_COEF_H(OMAP_DSS_VIDEO1, 6));
2476 DUMPREG(DISPC_OVL_FIR_COEF_H(OMAP_DSS_VIDEO1, 7));
2477 DUMPREG(DISPC_OVL_FIR_COEF_HV(OMAP_DSS_VIDEO1, 0));
2478 DUMPREG(DISPC_OVL_FIR_COEF_HV(OMAP_DSS_VIDEO1, 1));
2479 DUMPREG(DISPC_OVL_FIR_COEF_HV(OMAP_DSS_VIDEO1, 2));
2480 DUMPREG(DISPC_OVL_FIR_COEF_HV(OMAP_DSS_VIDEO1, 3));
2481 DUMPREG(DISPC_OVL_FIR_COEF_HV(OMAP_DSS_VIDEO1, 4));
2482 DUMPREG(DISPC_OVL_FIR_COEF_HV(OMAP_DSS_VIDEO1, 5));
2483 DUMPREG(DISPC_OVL_FIR_COEF_HV(OMAP_DSS_VIDEO1, 6));
2484 DUMPREG(DISPC_OVL_FIR_COEF_HV(OMAP_DSS_VIDEO1, 7));
2485 DUMPREG(DISPC_OVL_CONV_COEF(OMAP_DSS_VIDEO1, 0));
2486 DUMPREG(DISPC_OVL_CONV_COEF(OMAP_DSS_VIDEO1, 1));
2487 DUMPREG(DISPC_OVL_CONV_COEF(OMAP_DSS_VIDEO1, 2));
2488 DUMPREG(DISPC_OVL_CONV_COEF(OMAP_DSS_VIDEO1, 3));
2489 DUMPREG(DISPC_OVL_CONV_COEF(OMAP_DSS_VIDEO1, 4));
2490 DUMPREG(DISPC_OVL_FIR_COEF_V(OMAP_DSS_VIDEO1, 0));
2491 DUMPREG(DISPC_OVL_FIR_COEF_V(OMAP_DSS_VIDEO1, 1));
2492 DUMPREG(DISPC_OVL_FIR_COEF_V(OMAP_DSS_VIDEO1, 2));
2493 DUMPREG(DISPC_OVL_FIR_COEF_V(OMAP_DSS_VIDEO1, 3));
2494 DUMPREG(DISPC_OVL_FIR_COEF_V(OMAP_DSS_VIDEO1, 4));
2495 DUMPREG(DISPC_OVL_FIR_COEF_V(OMAP_DSS_VIDEO1, 5));
2496 DUMPREG(DISPC_OVL_FIR_COEF_V(OMAP_DSS_VIDEO1, 6));
2497 DUMPREG(DISPC_OVL_FIR_COEF_V(OMAP_DSS_VIDEO1, 7));
Tomi Valkeinen80c39712009-11-12 11:41:42 +02002498
Archit Taneja9b372c22011-05-06 11:45:49 +05302499 DUMPREG(DISPC_OVL_FIR_COEF_H(OMAP_DSS_VIDEO2, 0));
2500 DUMPREG(DISPC_OVL_FIR_COEF_H(OMAP_DSS_VIDEO2, 1));
2501 DUMPREG(DISPC_OVL_FIR_COEF_H(OMAP_DSS_VIDEO2, 2));
2502 DUMPREG(DISPC_OVL_FIR_COEF_H(OMAP_DSS_VIDEO2, 3));
2503 DUMPREG(DISPC_OVL_FIR_COEF_H(OMAP_DSS_VIDEO2, 4));
2504 DUMPREG(DISPC_OVL_FIR_COEF_H(OMAP_DSS_VIDEO2, 5));
2505 DUMPREG(DISPC_OVL_FIR_COEF_H(OMAP_DSS_VIDEO2, 6));
2506 DUMPREG(DISPC_OVL_FIR_COEF_H(OMAP_DSS_VIDEO2, 7));
2507 DUMPREG(DISPC_OVL_FIR_COEF_HV(OMAP_DSS_VIDEO2, 0));
2508 DUMPREG(DISPC_OVL_FIR_COEF_HV(OMAP_DSS_VIDEO2, 1));
2509 DUMPREG(DISPC_OVL_FIR_COEF_HV(OMAP_DSS_VIDEO2, 2));
2510 DUMPREG(DISPC_OVL_FIR_COEF_HV(OMAP_DSS_VIDEO2, 3));
2511 DUMPREG(DISPC_OVL_FIR_COEF_HV(OMAP_DSS_VIDEO2, 4));
2512 DUMPREG(DISPC_OVL_FIR_COEF_HV(OMAP_DSS_VIDEO2, 5));
2513 DUMPREG(DISPC_OVL_FIR_COEF_HV(OMAP_DSS_VIDEO2, 6));
2514 DUMPREG(DISPC_OVL_FIR_COEF_HV(OMAP_DSS_VIDEO2, 7));
2515 DUMPREG(DISPC_OVL_CONV_COEF(OMAP_DSS_VIDEO2, 0));
2516 DUMPREG(DISPC_OVL_CONV_COEF(OMAP_DSS_VIDEO2, 1));
2517 DUMPREG(DISPC_OVL_CONV_COEF(OMAP_DSS_VIDEO2, 2));
2518 DUMPREG(DISPC_OVL_CONV_COEF(OMAP_DSS_VIDEO2, 3));
2519 DUMPREG(DISPC_OVL_CONV_COEF(OMAP_DSS_VIDEO2, 4));
2520 DUMPREG(DISPC_OVL_FIR_COEF_V(OMAP_DSS_VIDEO2, 0));
2521 DUMPREG(DISPC_OVL_FIR_COEF_V(OMAP_DSS_VIDEO2, 1));
2522 DUMPREG(DISPC_OVL_FIR_COEF_V(OMAP_DSS_VIDEO2, 2));
2523 DUMPREG(DISPC_OVL_FIR_COEF_V(OMAP_DSS_VIDEO2, 3));
2524 DUMPREG(DISPC_OVL_FIR_COEF_V(OMAP_DSS_VIDEO2, 4));
2525 DUMPREG(DISPC_OVL_FIR_COEF_V(OMAP_DSS_VIDEO2, 5));
2526 DUMPREG(DISPC_OVL_FIR_COEF_V(OMAP_DSS_VIDEO2, 6));
2527 DUMPREG(DISPC_OVL_FIR_COEF_V(OMAP_DSS_VIDEO2, 7));
Tomi Valkeinen80c39712009-11-12 11:41:42 +02002528
Archit Taneja9b372c22011-05-06 11:45:49 +05302529 DUMPREG(DISPC_OVL_PRELOAD(OMAP_DSS_VIDEO1));
2530 DUMPREG(DISPC_OVL_PRELOAD(OMAP_DSS_VIDEO2));
Tomi Valkeinen80c39712009-11-12 11:41:42 +02002531
Archit Taneja6af9cd12011-01-31 16:27:44 +00002532 dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK);
Tomi Valkeinen80c39712009-11-12 11:41:42 +02002533#undef DUMPREG
2534}
2535
Sumit Semwalff1b2cd2010-12-02 11:27:11 +00002536static void _dispc_set_pol_freq(enum omap_channel channel, bool onoff, bool rf,
2537 bool ieo, bool ipc, bool ihs, bool ivs, u8 acbi, u8 acb)
Tomi Valkeinen80c39712009-11-12 11:41:42 +02002538{
2539 u32 l = 0;
2540
2541 DSSDBG("onoff %d rf %d ieo %d ipc %d ihs %d ivs %d acbi %d acb %d\n",
2542 onoff, rf, ieo, ipc, ihs, ivs, acbi, acb);
2543
2544 l |= FLD_VAL(onoff, 17, 17);
2545 l |= FLD_VAL(rf, 16, 16);
2546 l |= FLD_VAL(ieo, 15, 15);
2547 l |= FLD_VAL(ipc, 14, 14);
2548 l |= FLD_VAL(ihs, 13, 13);
2549 l |= FLD_VAL(ivs, 12, 12);
2550 l |= FLD_VAL(acbi, 11, 8);
2551 l |= FLD_VAL(acb, 7, 0);
2552
2553 enable_clocks(1);
Sumit Semwalff1b2cd2010-12-02 11:27:11 +00002554 dispc_write_reg(DISPC_POL_FREQ(channel), l);
Tomi Valkeinen80c39712009-11-12 11:41:42 +02002555 enable_clocks(0);
2556}
2557
Sumit Semwalff1b2cd2010-12-02 11:27:11 +00002558void dispc_set_pol_freq(enum omap_channel channel,
2559 enum omap_panel_config config, u8 acbi, u8 acb)
Tomi Valkeinen80c39712009-11-12 11:41:42 +02002560{
Sumit Semwalff1b2cd2010-12-02 11:27:11 +00002561 _dispc_set_pol_freq(channel, (config & OMAP_DSS_LCD_ONOFF) != 0,
Tomi Valkeinen80c39712009-11-12 11:41:42 +02002562 (config & OMAP_DSS_LCD_RF) != 0,
2563 (config & OMAP_DSS_LCD_IEO) != 0,
2564 (config & OMAP_DSS_LCD_IPC) != 0,
2565 (config & OMAP_DSS_LCD_IHS) != 0,
2566 (config & OMAP_DSS_LCD_IVS) != 0,
2567 acbi, acb);
2568}
2569
2570/* with fck as input clock rate, find dispc dividers that produce req_pck */
2571void dispc_find_clk_divs(bool is_tft, unsigned long req_pck, unsigned long fck,
2572 struct dispc_clock_info *cinfo)
2573{
2574 u16 pcd_min = is_tft ? 2 : 3;
2575 unsigned long best_pck;
2576 u16 best_ld, cur_ld;
2577 u16 best_pd, cur_pd;
2578
2579 best_pck = 0;
2580 best_ld = 0;
2581 best_pd = 0;
2582
2583 for (cur_ld = 1; cur_ld <= 255; ++cur_ld) {
2584 unsigned long lck = fck / cur_ld;
2585
2586 for (cur_pd = pcd_min; cur_pd <= 255; ++cur_pd) {
2587 unsigned long pck = lck / cur_pd;
2588 long old_delta = abs(best_pck - req_pck);
2589 long new_delta = abs(pck - req_pck);
2590
2591 if (best_pck == 0 || new_delta < old_delta) {
2592 best_pck = pck;
2593 best_ld = cur_ld;
2594 best_pd = cur_pd;
2595
2596 if (pck == req_pck)
2597 goto found;
2598 }
2599
2600 if (pck < req_pck)
2601 break;
2602 }
2603
2604 if (lck / pcd_min < req_pck)
2605 break;
2606 }
2607
2608found:
2609 cinfo->lck_div = best_ld;
2610 cinfo->pck_div = best_pd;
2611 cinfo->lck = fck / cinfo->lck_div;
2612 cinfo->pck = cinfo->lck / cinfo->pck_div;
2613}
2614
2615/* calculate clock rates using dividers in cinfo */
2616int dispc_calc_clock_rates(unsigned long dispc_fclk_rate,
2617 struct dispc_clock_info *cinfo)
2618{
2619 if (cinfo->lck_div > 255 || cinfo->lck_div == 0)
2620 return -EINVAL;
2621 if (cinfo->pck_div < 2 || cinfo->pck_div > 255)
2622 return -EINVAL;
2623
2624 cinfo->lck = dispc_fclk_rate / cinfo->lck_div;
2625 cinfo->pck = cinfo->lck / cinfo->pck_div;
2626
2627 return 0;
2628}
2629
Sumit Semwalff1b2cd2010-12-02 11:27:11 +00002630int dispc_set_clock_div(enum omap_channel channel,
2631 struct dispc_clock_info *cinfo)
Tomi Valkeinen80c39712009-11-12 11:41:42 +02002632{
2633 DSSDBG("lck = %lu (%u)\n", cinfo->lck, cinfo->lck_div);
2634 DSSDBG("pck = %lu (%u)\n", cinfo->pck, cinfo->pck_div);
2635
Sumit Semwalff1b2cd2010-12-02 11:27:11 +00002636 dispc_set_lcd_divisor(channel, cinfo->lck_div, cinfo->pck_div);
Tomi Valkeinen80c39712009-11-12 11:41:42 +02002637
2638 return 0;
2639}
2640
Sumit Semwalff1b2cd2010-12-02 11:27:11 +00002641int dispc_get_clock_div(enum omap_channel channel,
2642 struct dispc_clock_info *cinfo)
Tomi Valkeinen80c39712009-11-12 11:41:42 +02002643{
2644 unsigned long fck;
2645
2646 fck = dispc_fclk_rate();
2647
Murthy, Raghuveerce7fa5e2011-03-03 09:27:59 -06002648 cinfo->lck_div = REG_GET(DISPC_DIVISORo(channel), 23, 16);
2649 cinfo->pck_div = REG_GET(DISPC_DIVISORo(channel), 7, 0);
Tomi Valkeinen80c39712009-11-12 11:41:42 +02002650
2651 cinfo->lck = fck / cinfo->lck_div;
2652 cinfo->pck = cinfo->lck / cinfo->pck_div;
2653
2654 return 0;
2655}
2656
2657/* dispc.irq_lock has to be locked by the caller */
2658static void _omap_dispc_set_irqs(void)
2659{
2660 u32 mask;
2661 u32 old_mask;
2662 int i;
2663 struct omap_dispc_isr_data *isr_data;
2664
2665 mask = dispc.irq_error_mask;
2666
2667 for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
2668 isr_data = &dispc.registered_isr[i];
2669
2670 if (isr_data->isr == NULL)
2671 continue;
2672
2673 mask |= isr_data->mask;
2674 }
2675
2676 enable_clocks(1);
2677
2678 old_mask = dispc_read_reg(DISPC_IRQENABLE);
2679 /* clear the irqstatus for newly enabled irqs */
2680 dispc_write_reg(DISPC_IRQSTATUS, (mask ^ old_mask) & mask);
2681
2682 dispc_write_reg(DISPC_IRQENABLE, mask);
2683
2684 enable_clocks(0);
2685}
2686
2687int omap_dispc_register_isr(omap_dispc_isr_t isr, void *arg, u32 mask)
2688{
2689 int i;
2690 int ret;
2691 unsigned long flags;
2692 struct omap_dispc_isr_data *isr_data;
2693
2694 if (isr == NULL)
2695 return -EINVAL;
2696
2697 spin_lock_irqsave(&dispc.irq_lock, flags);
2698
2699 /* check for duplicate entry */
2700 for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
2701 isr_data = &dispc.registered_isr[i];
2702 if (isr_data->isr == isr && isr_data->arg == arg &&
2703 isr_data->mask == mask) {
2704 ret = -EINVAL;
2705 goto err;
2706 }
2707 }
2708
2709 isr_data = NULL;
2710 ret = -EBUSY;
2711
2712 for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
2713 isr_data = &dispc.registered_isr[i];
2714
2715 if (isr_data->isr != NULL)
2716 continue;
2717
2718 isr_data->isr = isr;
2719 isr_data->arg = arg;
2720 isr_data->mask = mask;
2721 ret = 0;
2722
2723 break;
2724 }
2725
Tomi Valkeinenb9cb0982011-03-04 18:19:54 +02002726 if (ret)
2727 goto err;
2728
Tomi Valkeinen80c39712009-11-12 11:41:42 +02002729 _omap_dispc_set_irqs();
2730
2731 spin_unlock_irqrestore(&dispc.irq_lock, flags);
2732
2733 return 0;
2734err:
2735 spin_unlock_irqrestore(&dispc.irq_lock, flags);
2736
2737 return ret;
2738}
2739EXPORT_SYMBOL(omap_dispc_register_isr);
2740
2741int omap_dispc_unregister_isr(omap_dispc_isr_t isr, void *arg, u32 mask)
2742{
2743 int i;
2744 unsigned long flags;
2745 int ret = -EINVAL;
2746 struct omap_dispc_isr_data *isr_data;
2747
2748 spin_lock_irqsave(&dispc.irq_lock, flags);
2749
2750 for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
2751 isr_data = &dispc.registered_isr[i];
2752 if (isr_data->isr != isr || isr_data->arg != arg ||
2753 isr_data->mask != mask)
2754 continue;
2755
2756 /* found the correct isr */
2757
2758 isr_data->isr = NULL;
2759 isr_data->arg = NULL;
2760 isr_data->mask = 0;
2761
2762 ret = 0;
2763 break;
2764 }
2765
2766 if (ret == 0)
2767 _omap_dispc_set_irqs();
2768
2769 spin_unlock_irqrestore(&dispc.irq_lock, flags);
2770
2771 return ret;
2772}
2773EXPORT_SYMBOL(omap_dispc_unregister_isr);
2774
2775#ifdef DEBUG
2776static void print_irq_status(u32 status)
2777{
2778 if ((status & dispc.irq_error_mask) == 0)
2779 return;
2780
2781 printk(KERN_DEBUG "DISPC IRQ: 0x%x: ", status);
2782
2783#define PIS(x) \
2784 if (status & DISPC_IRQ_##x) \
2785 printk(#x " ");
2786 PIS(GFX_FIFO_UNDERFLOW);
2787 PIS(OCP_ERR);
2788 PIS(VID1_FIFO_UNDERFLOW);
2789 PIS(VID2_FIFO_UNDERFLOW);
2790 PIS(SYNC_LOST);
2791 PIS(SYNC_LOST_DIGIT);
Sumit Semwal2a205f32010-12-02 11:27:12 +00002792 if (dss_has_feature(FEAT_MGR_LCD2))
2793 PIS(SYNC_LOST2);
Tomi Valkeinen80c39712009-11-12 11:41:42 +02002794#undef PIS
2795
2796 printk("\n");
2797}
2798#endif
2799
2800/* Called from dss.c. Note that we don't touch clocks here,
2801 * but we presume they are on because we got an IRQ. However,
2802 * an irq handler may turn the clocks off, so we may not have
2803 * clock later in the function. */
archit tanejaaffe3602011-02-23 08:41:03 +00002804static irqreturn_t omap_dispc_irq_handler(int irq, void *arg)
Tomi Valkeinen80c39712009-11-12 11:41:42 +02002805{
2806 int i;
archit tanejaaffe3602011-02-23 08:41:03 +00002807 u32 irqstatus, irqenable;
Tomi Valkeinen80c39712009-11-12 11:41:42 +02002808 u32 handledirqs = 0;
2809 u32 unhandled_errors;
2810 struct omap_dispc_isr_data *isr_data;
2811 struct omap_dispc_isr_data registered_isr[DISPC_MAX_NR_ISRS];
2812
2813 spin_lock(&dispc.irq_lock);
2814
2815 irqstatus = dispc_read_reg(DISPC_IRQSTATUS);
archit tanejaaffe3602011-02-23 08:41:03 +00002816 irqenable = dispc_read_reg(DISPC_IRQENABLE);
2817
2818 /* IRQ is not for us */
2819 if (!(irqstatus & irqenable)) {
2820 spin_unlock(&dispc.irq_lock);
2821 return IRQ_NONE;
2822 }
Tomi Valkeinen80c39712009-11-12 11:41:42 +02002823
Tomi Valkeinendfc0fd82009-12-17 14:35:21 +02002824#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
2825 spin_lock(&dispc.irq_stats_lock);
2826 dispc.irq_stats.irq_count++;
2827 dss_collect_irq_stats(irqstatus, dispc.irq_stats.irqs);
2828 spin_unlock(&dispc.irq_stats_lock);
2829#endif
2830
Tomi Valkeinen80c39712009-11-12 11:41:42 +02002831#ifdef DEBUG
2832 if (dss_debug)
2833 print_irq_status(irqstatus);
2834#endif
2835 /* Ack the interrupt. Do it here before clocks are possibly turned
2836 * off */
2837 dispc_write_reg(DISPC_IRQSTATUS, irqstatus);
2838 /* flush posted write */
2839 dispc_read_reg(DISPC_IRQSTATUS);
2840
2841 /* make a copy and unlock, so that isrs can unregister
2842 * themselves */
2843 memcpy(registered_isr, dispc.registered_isr,
2844 sizeof(registered_isr));
2845
2846 spin_unlock(&dispc.irq_lock);
2847
2848 for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
2849 isr_data = &registered_isr[i];
2850
2851 if (!isr_data->isr)
2852 continue;
2853
2854 if (isr_data->mask & irqstatus) {
2855 isr_data->isr(isr_data->arg, irqstatus);
2856 handledirqs |= isr_data->mask;
2857 }
2858 }
2859
2860 spin_lock(&dispc.irq_lock);
2861
2862 unhandled_errors = irqstatus & ~handledirqs & dispc.irq_error_mask;
2863
2864 if (unhandled_errors) {
2865 dispc.error_irqs |= unhandled_errors;
2866
2867 dispc.irq_error_mask &= ~unhandled_errors;
2868 _omap_dispc_set_irqs();
2869
2870 schedule_work(&dispc.error_work);
2871 }
2872
2873 spin_unlock(&dispc.irq_lock);
archit tanejaaffe3602011-02-23 08:41:03 +00002874
2875 return IRQ_HANDLED;
Tomi Valkeinen80c39712009-11-12 11:41:42 +02002876}
2877
2878static void dispc_error_worker(struct work_struct *work)
2879{
2880 int i;
2881 u32 errors;
2882 unsigned long flags;
2883
2884 spin_lock_irqsave(&dispc.irq_lock, flags);
2885 errors = dispc.error_irqs;
2886 dispc.error_irqs = 0;
2887 spin_unlock_irqrestore(&dispc.irq_lock, flags);
2888
2889 if (errors & DISPC_IRQ_GFX_FIFO_UNDERFLOW) {
2890 DSSERR("GFX_FIFO_UNDERFLOW, disabling GFX\n");
2891 for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
2892 struct omap_overlay *ovl;
2893 ovl = omap_dss_get_overlay(i);
2894
2895 if (!(ovl->caps & OMAP_DSS_OVL_CAP_DISPC))
2896 continue;
2897
2898 if (ovl->id == 0) {
2899 dispc_enable_plane(ovl->id, 0);
2900 dispc_go(ovl->manager->id);
2901 mdelay(50);
2902 break;
2903 }
2904 }
2905 }
2906
2907 if (errors & DISPC_IRQ_VID1_FIFO_UNDERFLOW) {
2908 DSSERR("VID1_FIFO_UNDERFLOW, disabling VID1\n");
2909 for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
2910 struct omap_overlay *ovl;
2911 ovl = omap_dss_get_overlay(i);
2912
2913 if (!(ovl->caps & OMAP_DSS_OVL_CAP_DISPC))
2914 continue;
2915
2916 if (ovl->id == 1) {
2917 dispc_enable_plane(ovl->id, 0);
2918 dispc_go(ovl->manager->id);
2919 mdelay(50);
2920 break;
2921 }
2922 }
2923 }
2924
2925 if (errors & DISPC_IRQ_VID2_FIFO_UNDERFLOW) {
2926 DSSERR("VID2_FIFO_UNDERFLOW, disabling VID2\n");
2927 for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
2928 struct omap_overlay *ovl;
2929 ovl = omap_dss_get_overlay(i);
2930
2931 if (!(ovl->caps & OMAP_DSS_OVL_CAP_DISPC))
2932 continue;
2933
2934 if (ovl->id == 2) {
2935 dispc_enable_plane(ovl->id, 0);
2936 dispc_go(ovl->manager->id);
2937 mdelay(50);
2938 break;
2939 }
2940 }
2941 }
2942
2943 if (errors & DISPC_IRQ_SYNC_LOST) {
2944 struct omap_overlay_manager *manager = NULL;
2945 bool enable = false;
2946
2947 DSSERR("SYNC_LOST, disabling LCD\n");
2948
2949 for (i = 0; i < omap_dss_get_num_overlay_managers(); ++i) {
2950 struct omap_overlay_manager *mgr;
2951 mgr = omap_dss_get_overlay_manager(i);
2952
2953 if (mgr->id == OMAP_DSS_CHANNEL_LCD) {
2954 manager = mgr;
2955 enable = mgr->device->state ==
2956 OMAP_DSS_DISPLAY_ACTIVE;
Tomi Valkeinen37ac60e2010-01-12 15:12:07 +02002957 mgr->device->driver->disable(mgr->device);
Tomi Valkeinen80c39712009-11-12 11:41:42 +02002958 break;
2959 }
2960 }
2961
2962 if (manager) {
Tomi Valkeinen37ac60e2010-01-12 15:12:07 +02002963 struct omap_dss_device *dssdev = manager->device;
Tomi Valkeinen80c39712009-11-12 11:41:42 +02002964 for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
2965 struct omap_overlay *ovl;
2966 ovl = omap_dss_get_overlay(i);
2967
2968 if (!(ovl->caps & OMAP_DSS_OVL_CAP_DISPC))
2969 continue;
2970
2971 if (ovl->id != 0 && ovl->manager == manager)
2972 dispc_enable_plane(ovl->id, 0);
2973 }
2974
2975 dispc_go(manager->id);
2976 mdelay(50);
2977 if (enable)
Tomi Valkeinen37ac60e2010-01-12 15:12:07 +02002978 dssdev->driver->enable(dssdev);
Tomi Valkeinen80c39712009-11-12 11:41:42 +02002979 }
2980 }
2981
2982 if (errors & DISPC_IRQ_SYNC_LOST_DIGIT) {
2983 struct omap_overlay_manager *manager = NULL;
2984 bool enable = false;
2985
2986 DSSERR("SYNC_LOST_DIGIT, disabling TV\n");
2987
2988 for (i = 0; i < omap_dss_get_num_overlay_managers(); ++i) {
2989 struct omap_overlay_manager *mgr;
2990 mgr = omap_dss_get_overlay_manager(i);
2991
2992 if (mgr->id == OMAP_DSS_CHANNEL_DIGIT) {
2993 manager = mgr;
2994 enable = mgr->device->state ==
2995 OMAP_DSS_DISPLAY_ACTIVE;
Tomi Valkeinen37ac60e2010-01-12 15:12:07 +02002996 mgr->device->driver->disable(mgr->device);
Tomi Valkeinen80c39712009-11-12 11:41:42 +02002997 break;
2998 }
2999 }
3000
3001 if (manager) {
Tomi Valkeinen37ac60e2010-01-12 15:12:07 +02003002 struct omap_dss_device *dssdev = manager->device;
Tomi Valkeinen80c39712009-11-12 11:41:42 +02003003 for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
3004 struct omap_overlay *ovl;
3005 ovl = omap_dss_get_overlay(i);
3006
3007 if (!(ovl->caps & OMAP_DSS_OVL_CAP_DISPC))
3008 continue;
3009
3010 if (ovl->id != 0 && ovl->manager == manager)
3011 dispc_enable_plane(ovl->id, 0);
3012 }
3013
3014 dispc_go(manager->id);
3015 mdelay(50);
3016 if (enable)
Tomi Valkeinen37ac60e2010-01-12 15:12:07 +02003017 dssdev->driver->enable(dssdev);
Tomi Valkeinen80c39712009-11-12 11:41:42 +02003018 }
3019 }
3020
Sumit Semwal2a205f32010-12-02 11:27:12 +00003021 if (errors & DISPC_IRQ_SYNC_LOST2) {
3022 struct omap_overlay_manager *manager = NULL;
3023 bool enable = false;
3024
3025 DSSERR("SYNC_LOST for LCD2, disabling LCD2\n");
3026
3027 for (i = 0; i < omap_dss_get_num_overlay_managers(); ++i) {
3028 struct omap_overlay_manager *mgr;
3029 mgr = omap_dss_get_overlay_manager(i);
3030
3031 if (mgr->id == OMAP_DSS_CHANNEL_LCD2) {
3032 manager = mgr;
3033 enable = mgr->device->state ==
3034 OMAP_DSS_DISPLAY_ACTIVE;
3035 mgr->device->driver->disable(mgr->device);
3036 break;
3037 }
3038 }
3039
3040 if (manager) {
3041 struct omap_dss_device *dssdev = manager->device;
3042 for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
3043 struct omap_overlay *ovl;
3044 ovl = omap_dss_get_overlay(i);
3045
3046 if (!(ovl->caps & OMAP_DSS_OVL_CAP_DISPC))
3047 continue;
3048
3049 if (ovl->id != 0 && ovl->manager == manager)
3050 dispc_enable_plane(ovl->id, 0);
3051 }
3052
3053 dispc_go(manager->id);
3054 mdelay(50);
3055 if (enable)
3056 dssdev->driver->enable(dssdev);
3057 }
3058 }
3059
Tomi Valkeinen80c39712009-11-12 11:41:42 +02003060 if (errors & DISPC_IRQ_OCP_ERR) {
3061 DSSERR("OCP_ERR\n");
3062 for (i = 0; i < omap_dss_get_num_overlay_managers(); ++i) {
3063 struct omap_overlay_manager *mgr;
3064 mgr = omap_dss_get_overlay_manager(i);
3065
3066 if (mgr->caps & OMAP_DSS_OVL_CAP_DISPC)
Tomi Valkeinen37ac60e2010-01-12 15:12:07 +02003067 mgr->device->driver->disable(mgr->device);
Tomi Valkeinen80c39712009-11-12 11:41:42 +02003068 }
3069 }
3070
3071 spin_lock_irqsave(&dispc.irq_lock, flags);
3072 dispc.irq_error_mask |= errors;
3073 _omap_dispc_set_irqs();
3074 spin_unlock_irqrestore(&dispc.irq_lock, flags);
3075}
3076
3077int omap_dispc_wait_for_irq_timeout(u32 irqmask, unsigned long timeout)
3078{
3079 void dispc_irq_wait_handler(void *data, u32 mask)
3080 {
3081 complete((struct completion *)data);
3082 }
3083
3084 int r;
3085 DECLARE_COMPLETION_ONSTACK(completion);
3086
3087 r = omap_dispc_register_isr(dispc_irq_wait_handler, &completion,
3088 irqmask);
3089
3090 if (r)
3091 return r;
3092
3093 timeout = wait_for_completion_timeout(&completion, timeout);
3094
3095 omap_dispc_unregister_isr(dispc_irq_wait_handler, &completion, irqmask);
3096
3097 if (timeout == 0)
3098 return -ETIMEDOUT;
3099
3100 if (timeout == -ERESTARTSYS)
3101 return -ERESTARTSYS;
3102
3103 return 0;
3104}
3105
3106int omap_dispc_wait_for_irq_interruptible_timeout(u32 irqmask,
3107 unsigned long timeout)
3108{
3109 void dispc_irq_wait_handler(void *data, u32 mask)
3110 {
3111 complete((struct completion *)data);
3112 }
3113
3114 int r;
3115 DECLARE_COMPLETION_ONSTACK(completion);
3116
3117 r = omap_dispc_register_isr(dispc_irq_wait_handler, &completion,
3118 irqmask);
3119
3120 if (r)
3121 return r;
3122
3123 timeout = wait_for_completion_interruptible_timeout(&completion,
3124 timeout);
3125
3126 omap_dispc_unregister_isr(dispc_irq_wait_handler, &completion, irqmask);
3127
3128 if (timeout == 0)
3129 return -ETIMEDOUT;
3130
3131 if (timeout == -ERESTARTSYS)
3132 return -ERESTARTSYS;
3133
3134 return 0;
3135}
3136
3137#ifdef CONFIG_OMAP2_DSS_FAKE_VSYNC
3138void dispc_fake_vsync_irq(void)
3139{
3140 u32 irqstatus = DISPC_IRQ_VSYNC;
3141 int i;
3142
Tomi Valkeinenab83b142010-06-09 15:31:01 +03003143 WARN_ON(!in_interrupt());
Tomi Valkeinen80c39712009-11-12 11:41:42 +02003144
3145 for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
3146 struct omap_dispc_isr_data *isr_data;
3147 isr_data = &dispc.registered_isr[i];
3148
3149 if (!isr_data->isr)
3150 continue;
3151
3152 if (isr_data->mask & irqstatus)
3153 isr_data->isr(isr_data->arg, irqstatus);
3154 }
Tomi Valkeinen80c39712009-11-12 11:41:42 +02003155}
3156#endif
3157
3158static void _omap_dispc_initialize_irq(void)
3159{
3160 unsigned long flags;
3161
3162 spin_lock_irqsave(&dispc.irq_lock, flags);
3163
3164 memset(dispc.registered_isr, 0, sizeof(dispc.registered_isr));
3165
3166 dispc.irq_error_mask = DISPC_IRQ_MASK_ERROR;
Sumit Semwal2a205f32010-12-02 11:27:12 +00003167 if (dss_has_feature(FEAT_MGR_LCD2))
3168 dispc.irq_error_mask |= DISPC_IRQ_SYNC_LOST2;
Tomi Valkeinen80c39712009-11-12 11:41:42 +02003169
3170 /* there's SYNC_LOST_DIGIT waiting after enabling the DSS,
3171 * so clear it */
3172 dispc_write_reg(DISPC_IRQSTATUS, dispc_read_reg(DISPC_IRQSTATUS));
3173
3174 _omap_dispc_set_irqs();
3175
3176 spin_unlock_irqrestore(&dispc.irq_lock, flags);
3177}
3178
3179void dispc_enable_sidle(void)
3180{
3181 REG_FLD_MOD(DISPC_SYSCONFIG, 2, 4, 3); /* SIDLEMODE: smart idle */
3182}
3183
3184void dispc_disable_sidle(void)
3185{
3186 REG_FLD_MOD(DISPC_SYSCONFIG, 1, 4, 3); /* SIDLEMODE: no idle */
3187}
3188
3189static void _omap_dispc_initial_config(void)
3190{
3191 u32 l;
3192
3193 l = dispc_read_reg(DISPC_SYSCONFIG);
3194 l = FLD_MOD(l, 2, 13, 12); /* MIDLEMODE: smart standby */
3195 l = FLD_MOD(l, 2, 4, 3); /* SIDLEMODE: smart idle */
3196 l = FLD_MOD(l, 1, 2, 2); /* ENWAKEUP */
3197 l = FLD_MOD(l, 1, 0, 0); /* AUTOIDLE */
3198 dispc_write_reg(DISPC_SYSCONFIG, l);
3199
Murthy, Raghuveer0cf35df2011-03-03 09:28:00 -06003200 /* Exclusively enable DISPC_CORE_CLK and set divider to 1 */
3201 if (dss_has_feature(FEAT_CORE_CLK_DIV)) {
3202 l = dispc_read_reg(DISPC_DIVISOR);
3203 /* Use DISPC_DIVISOR.LCD, instead of DISPC_DIVISOR1.LCD */
3204 l = FLD_MOD(l, 1, 0, 0);
3205 l = FLD_MOD(l, 1, 23, 16);
3206 dispc_write_reg(DISPC_DIVISOR, l);
3207 }
3208
Tomi Valkeinen80c39712009-11-12 11:41:42 +02003209 /* FUNCGATED */
Archit Taneja6ced40b2010-12-02 11:27:13 +00003210 if (dss_has_feature(FEAT_FUNCGATED))
3211 REG_FLD_MOD(DISPC_CONFIG, 1, 9, 9);
Tomi Valkeinen80c39712009-11-12 11:41:42 +02003212
3213 /* L3 firewall setting: enable access to OCM RAM */
3214 /* XXX this should be somewhere in plat-omap */
3215 if (cpu_is_omap24xx())
3216 __raw_writel(0x402000b0, OMAP2_L3_IO_ADDRESS(0x680050a0));
3217
3218 _dispc_setup_color_conv_coef();
3219
3220 dispc_set_loadmode(OMAP_DSS_LOAD_FRAME_ONLY);
3221
3222 dispc_read_plane_fifo_sizes();
3223}
3224
Tomi Valkeinen80c39712009-11-12 11:41:42 +02003225int dispc_enable_plane(enum omap_plane plane, bool enable)
3226{
3227 DSSDBG("dispc_enable_plane %d, %d\n", plane, enable);
3228
3229 enable_clocks(1);
3230 _dispc_enable_plane(plane, enable);
3231 enable_clocks(0);
3232
3233 return 0;
3234}
3235
3236int dispc_setup_plane(enum omap_plane plane,
3237 u32 paddr, u16 screen_width,
3238 u16 pos_x, u16 pos_y,
3239 u16 width, u16 height,
3240 u16 out_width, u16 out_height,
3241 enum omap_color_mode color_mode,
3242 bool ilace,
3243 enum omap_dss_rotation_type rotation_type,
Rajkumar Nfd28a392010-11-04 12:28:42 +01003244 u8 rotation, bool mirror, u8 global_alpha,
Sumit Semwal18faa1b2010-12-02 11:27:14 +00003245 u8 pre_mult_alpha, enum omap_channel channel)
Tomi Valkeinen80c39712009-11-12 11:41:42 +02003246{
3247 int r = 0;
3248
3249 DSSDBG("dispc_setup_plane %d, pa %x, sw %d, %d,%d, %dx%d -> "
Sumit Semwal18faa1b2010-12-02 11:27:14 +00003250 "%dx%d, ilace %d, cmode %x, rot %d, mir %d chan %d\n",
Tomi Valkeinen80c39712009-11-12 11:41:42 +02003251 plane, paddr, screen_width, pos_x, pos_y,
3252 width, height,
3253 out_width, out_height,
3254 ilace, color_mode,
Sumit Semwal18faa1b2010-12-02 11:27:14 +00003255 rotation, mirror, channel);
Tomi Valkeinen80c39712009-11-12 11:41:42 +02003256
3257 enable_clocks(1);
3258
3259 r = _dispc_setup_plane(plane,
3260 paddr, screen_width,
3261 pos_x, pos_y,
3262 width, height,
3263 out_width, out_height,
3264 color_mode, ilace,
3265 rotation_type,
3266 rotation, mirror,
Rajkumar Nfd28a392010-11-04 12:28:42 +01003267 global_alpha,
Sumit Semwal18faa1b2010-12-02 11:27:14 +00003268 pre_mult_alpha, channel);
Tomi Valkeinen80c39712009-11-12 11:41:42 +02003269
3270 enable_clocks(0);
3271
3272 return r;
3273}
Senthilvadivu Guruswamy060b6d92011-01-24 06:22:00 +00003274
3275/* DISPC HW IP initialisation */
3276static int omap_dispchw_probe(struct platform_device *pdev)
3277{
3278 u32 rev;
archit tanejaaffe3602011-02-23 08:41:03 +00003279 int r = 0;
Senthilvadivu Guruswamyea9da362011-01-24 06:22:04 +00003280 struct resource *dispc_mem;
3281
Senthilvadivu Guruswamy060b6d92011-01-24 06:22:00 +00003282 dispc.pdev = pdev;
3283
3284 spin_lock_init(&dispc.irq_lock);
3285
3286#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
3287 spin_lock_init(&dispc.irq_stats_lock);
3288 dispc.irq_stats.last_reset = jiffies;
3289#endif
3290
3291 INIT_WORK(&dispc.error_work, dispc_error_worker);
3292
Senthilvadivu Guruswamyea9da362011-01-24 06:22:04 +00003293 dispc_mem = platform_get_resource(dispc.pdev, IORESOURCE_MEM, 0);
3294 if (!dispc_mem) {
3295 DSSERR("can't get IORESOURCE_MEM DISPC\n");
archit tanejaaffe3602011-02-23 08:41:03 +00003296 r = -EINVAL;
3297 goto fail0;
Senthilvadivu Guruswamyea9da362011-01-24 06:22:04 +00003298 }
3299 dispc.base = ioremap(dispc_mem->start, resource_size(dispc_mem));
Senthilvadivu Guruswamy060b6d92011-01-24 06:22:00 +00003300 if (!dispc.base) {
3301 DSSERR("can't ioremap DISPC\n");
archit tanejaaffe3602011-02-23 08:41:03 +00003302 r = -ENOMEM;
3303 goto fail0;
3304 }
3305 dispc.irq = platform_get_irq(dispc.pdev, 0);
3306 if (dispc.irq < 0) {
3307 DSSERR("platform_get_irq failed\n");
3308 r = -ENODEV;
3309 goto fail1;
3310 }
3311
3312 r = request_irq(dispc.irq, omap_dispc_irq_handler, IRQF_SHARED,
3313 "OMAP DISPC", dispc.pdev);
3314 if (r < 0) {
3315 DSSERR("request_irq failed\n");
3316 goto fail1;
Senthilvadivu Guruswamy060b6d92011-01-24 06:22:00 +00003317 }
3318
3319 enable_clocks(1);
3320
3321 _omap_dispc_initial_config();
3322
3323 _omap_dispc_initialize_irq();
3324
3325 dispc_save_context();
3326
3327 rev = dispc_read_reg(DISPC_REVISION);
Sumit Semwala06b62f2011-01-24 06:22:03 +00003328 dev_dbg(&pdev->dev, "OMAP DISPC rev %d.%d\n",
Senthilvadivu Guruswamy060b6d92011-01-24 06:22:00 +00003329 FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0));
3330
3331 enable_clocks(0);
3332
3333 return 0;
archit tanejaaffe3602011-02-23 08:41:03 +00003334fail1:
3335 iounmap(dispc.base);
3336fail0:
3337 return r;
Senthilvadivu Guruswamy060b6d92011-01-24 06:22:00 +00003338}
3339
3340static int omap_dispchw_remove(struct platform_device *pdev)
3341{
archit tanejaaffe3602011-02-23 08:41:03 +00003342 free_irq(dispc.irq, dispc.pdev);
Senthilvadivu Guruswamy060b6d92011-01-24 06:22:00 +00003343 iounmap(dispc.base);
3344 return 0;
3345}
3346
3347static struct platform_driver omap_dispchw_driver = {
3348 .probe = omap_dispchw_probe,
3349 .remove = omap_dispchw_remove,
3350 .driver = {
3351 .name = "omapdss_dispc",
3352 .owner = THIS_MODULE,
3353 },
3354};
3355
3356int dispc_init_platform_driver(void)
3357{
3358 return platform_driver_register(&omap_dispchw_driver);
3359}
3360
3361void dispc_uninit_platform_driver(void)
3362{
3363 return platform_driver_unregister(&omap_dispchw_driver);
3364}