blob: 53634398a56dd74ae4d01f78b0c3f5c8b4081e86 [file] [log] [blame]
Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * sc-rm7k.c: RM7000 cache management functions.
3 *
4 * Copyright (C) 1997, 2001, 2003, 2004 Ralf Baechle (ralf@linux-mips.org)
5 */
6
7#undef DEBUG
8
9#include <linux/init.h>
10#include <linux/kernel.h>
11#include <linux/mm.h>
Atsushi Nemoto37caa932006-02-15 18:25:48 +090012#include <linux/bitops.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070013
14#include <asm/addrspace.h>
15#include <asm/bcache.h>
16#include <asm/cacheops.h>
17#include <asm/mipsregs.h>
18#include <asm/processor.h>
Thiemo Seuferba5187d2005-04-25 16:36:23 +000019#include <asm/cacheflush.h> /* for run_uncached() */
Linus Torvalds1da177e2005-04-16 15:20:36 -070020
21/* Primary cache parameters. */
22#define sc_lsize 32
23#define tc_pagesize (32*128)
24
25/* Secondary cache parameters. */
26#define scache_size (256*1024) /* Fixed to 256KiB on RM7000 */
27
28extern unsigned long icache_way_size, dcache_way_size;
29
30#include <asm/r4kcache.h>
31
Dmitri Vorobiev12914172009-03-30 22:53:23 +030032static int rm7k_tcache_enabled;
Linus Torvalds1da177e2005-04-16 15:20:36 -070033
34/*
35 * Writeback and invalidate the primary cache dcache before DMA.
36 * (XXX These need to be fixed ...)
37 */
38static void rm7k_sc_wback_inv(unsigned long addr, unsigned long size)
39{
40 unsigned long end, a;
41
42 pr_debug("rm7k_sc_wback_inv[%08lx,%08lx]", addr, size);
43
44 /* Catch bad driver code */
45 BUG_ON(size == 0);
46
Atsushi Nemoto37caa932006-02-15 18:25:48 +090047 blast_scache_range(addr, addr + size);
Linus Torvalds1da177e2005-04-16 15:20:36 -070048
49 if (!rm7k_tcache_enabled)
50 return;
51
52 a = addr & ~(tc_pagesize - 1);
53 end = (addr + size - 1) & ~(tc_pagesize - 1);
54 while(1) {
55 invalidate_tcache_page(a); /* Page_Invalidate_T */
56 if (a == end)
57 break;
58 a += tc_pagesize;
59 }
60}
61
62static void rm7k_sc_inv(unsigned long addr, unsigned long size)
63{
64 unsigned long end, a;
65
66 pr_debug("rm7k_sc_inv[%08lx,%08lx]", addr, size);
67
68 /* Catch bad driver code */
69 BUG_ON(size == 0);
70
Atsushi Nemoto37caa932006-02-15 18:25:48 +090071 blast_inv_scache_range(addr, addr + size);
Linus Torvalds1da177e2005-04-16 15:20:36 -070072
73 if (!rm7k_tcache_enabled)
74 return;
75
76 a = addr & ~(tc_pagesize - 1);
77 end = (addr + size - 1) & ~(tc_pagesize - 1);
78 while(1) {
79 invalidate_tcache_page(a); /* Page_Invalidate_T */
80 if (a == end)
81 break;
82 a += tc_pagesize;
83 }
84}
85
86/*
Thiemo Seuferba5187d2005-04-25 16:36:23 +000087 * This function is executed in uncached address space.
Linus Torvalds1da177e2005-04-16 15:20:36 -070088 */
Shane McDonaldb32dfbb2008-07-05 17:19:42 -060089static __cpuinit void __rm7k_sc_enable(void)
Linus Torvalds1da177e2005-04-16 15:20:36 -070090{
91 int i;
92
Maciej W. Rozyckic6ad7b72005-06-20 13:09:49 +000093 set_c0_config(RM7K_CONF_SE);
Linus Torvalds1da177e2005-04-16 15:20:36 -070094
95 write_c0_taglo(0);
96 write_c0_taghi(0);
97
Ricardo Mendoza58a6d452010-07-19 04:59:59 +010098 for (i = 0; i < scache_size; i += sc_lsize)
99 cache_op(Index_Store_Tag_SD, CKSEG0ADDR(i));
Linus Torvalds1da177e2005-04-16 15:20:36 -0700100}
101
Shane McDonaldb32dfbb2008-07-05 17:19:42 -0600102static __cpuinit void rm7k_sc_enable(void)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700103{
Maciej W. Rozyckic6ad7b72005-06-20 13:09:49 +0000104 if (read_c0_config() & RM7K_CONF_SE)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700105 return;
106
Maciej W. Rozyckic6ad7b72005-06-20 13:09:49 +0000107 printk(KERN_INFO "Enabling secondary cache...\n");
Thiemo Seuferba5187d2005-04-25 16:36:23 +0000108 run_uncached(__rm7k_sc_enable);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700109}
110
111static void rm7k_sc_disable(void)
112{
Maciej W. Rozyckic6ad7b72005-06-20 13:09:49 +0000113 clear_c0_config(RM7K_CONF_SE);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700114}
115
Dmitri Vorobiev12914172009-03-30 22:53:23 +0300116static struct bcache_ops rm7k_sc_ops = {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700117 .bc_enable = rm7k_sc_enable,
118 .bc_disable = rm7k_sc_disable,
119 .bc_wback_inv = rm7k_sc_wback_inv,
120 .bc_inv = rm7k_sc_inv
121};
122
Ralf Baechle234fcd12008-03-08 09:56:28 +0000123void __cpuinit rm7k_sc_init(void)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700124{
Atsushi Nemoto37caa932006-02-15 18:25:48 +0900125 struct cpuinfo_mips *c = &current_cpu_data;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700126 unsigned int config = read_c0_config();
127
Maciej W. Rozyckic6ad7b72005-06-20 13:09:49 +0000128 if ((config & RM7K_CONF_SC))
Linus Torvalds1da177e2005-04-16 15:20:36 -0700129 return;
130
Atsushi Nemoto37caa932006-02-15 18:25:48 +0900131 c->scache.linesz = sc_lsize;
132 c->scache.ways = 4;
Atsushi Nemoto3c68da72006-04-08 01:33:31 +0900133 c->scache.waybit= __ffs(scache_size / c->scache.ways);
Atsushi Nemoto37caa932006-02-15 18:25:48 +0900134 c->scache.waysize = scache_size / c->scache.ways;
135 c->scache.sets = scache_size / (c->scache.linesz * c->scache.ways);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700136 printk(KERN_INFO "Secondary cache size %dK, linesize %d bytes.\n",
137 (scache_size >> 10), sc_lsize);
138
Maciej W. Rozyckic6ad7b72005-06-20 13:09:49 +0000139 if (!(config & RM7K_CONF_SE))
Linus Torvalds1da177e2005-04-16 15:20:36 -0700140 rm7k_sc_enable();
141
142 /*
143 * While we're at it let's deal with the tertiary cache.
144 */
Maciej W. Rozyckic6ad7b72005-06-20 13:09:49 +0000145 if (!(config & RM7K_CONF_TC)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700146
147 /*
148 * We can't enable the L3 cache yet. There may be board-specific
149 * magic necessary to turn it on, and blindly asking the CPU to
150 * start using it would may give cache errors.
151 *
152 * Also, board-specific knowledge may allow us to use the
153 * CACHE Flash_Invalidate_T instruction if the tag RAM supports
154 * it, and may specify the size of the L3 cache so we don't have
155 * to probe it.
156 */
157 printk(KERN_INFO "Tertiary cache present, %s enabled\n",
Maciej W. Rozyckic6ad7b72005-06-20 13:09:49 +0000158 (config & RM7K_CONF_TE) ? "already" : "not (yet)");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700159
Maciej W. Rozyckic6ad7b72005-06-20 13:09:49 +0000160 if ((config & RM7K_CONF_TE))
Linus Torvalds1da177e2005-04-16 15:20:36 -0700161 rm7k_tcache_enabled = 1;
162 }
163
164 bcops = &rm7k_sc_ops;
165}