| Paul Walmsley | 657ebfa | 2010-02-22 22:09:20 -0700 | [diff] [blame] | 1 | /* | 
|  | 2 | * OMAP3517/3505-specific clock framework functions | 
|  | 3 | * | 
|  | 4 | * Copyright (C) 2010 Texas Instruments, Inc. | 
|  | 5 | * Copyright (C) 2010 Nokia Corporation | 
|  | 6 | * | 
|  | 7 | * Ranjith Lohithakshan | 
|  | 8 | * Paul Walmsley | 
|  | 9 | * | 
|  | 10 | * Parts of this code are based on code written by | 
|  | 11 | * Richard Woodruff, Tony Lindgren, Tuukka Tikkanen, Karthik Dasu, | 
|  | 12 | * Russell King | 
|  | 13 | * | 
|  | 14 | * This program is free software; you can redistribute it and/or modify | 
|  | 15 | * it under the terms of the GNU General Public License version 2 as | 
|  | 16 | * published by the Free Software Foundation. | 
|  | 17 | */ | 
|  | 18 | #undef DEBUG | 
|  | 19 |  | 
|  | 20 | #include <linux/kernel.h> | 
|  | 21 | #include <linux/clk.h> | 
|  | 22 | #include <linux/io.h> | 
|  | 23 |  | 
|  | 24 | #include <plat/clock.h> | 
|  | 25 |  | 
|  | 26 | #include "clock.h" | 
|  | 27 | #include "clock3517.h" | 
|  | 28 | #include "cm.h" | 
|  | 29 | #include "cm-regbits-34xx.h" | 
|  | 30 |  | 
|  | 31 | /* | 
|  | 32 | * In AM35xx IPSS, the {ICK,FCK} enable bits for modules are exported | 
|  | 33 | * in the same register at a bit offset of 0x8. The EN_ACK for ICK is | 
|  | 34 | * at an offset of 4 from ICK enable bit. | 
|  | 35 | */ | 
|  | 36 | #define AM35XX_IPSS_ICK_MASK			0xF | 
|  | 37 | #define AM35XX_IPSS_ICK_EN_ACK_OFFSET 		0x4 | 
|  | 38 | #define AM35XX_IPSS_ICK_FCK_OFFSET		0x8 | 
|  | 39 | #define AM35XX_IPSS_CLK_IDLEST_VAL		0 | 
|  | 40 |  | 
|  | 41 | /** | 
|  | 42 | * am35xx_clk_find_idlest - return clock ACK info for AM35XX IPSS | 
|  | 43 | * @clk: struct clk * being enabled | 
|  | 44 | * @idlest_reg: void __iomem ** to store CM_IDLEST reg address into | 
|  | 45 | * @idlest_bit: pointer to a u8 to store the CM_IDLEST bit shift into | 
|  | 46 | * @idlest_val: pointer to a u8 to store the CM_IDLEST indicator | 
|  | 47 | * | 
|  | 48 | * The interface clocks on AM35xx IPSS reflects the clock idle status | 
|  | 49 | * in the enable register itsel at a bit offset of 4 from the enable | 
|  | 50 | * bit. A value of 1 indicates that clock is enabled. | 
|  | 51 | */ | 
|  | 52 | static void am35xx_clk_find_idlest(struct clk *clk, | 
|  | 53 | void __iomem **idlest_reg, | 
|  | 54 | u8 *idlest_bit, | 
|  | 55 | u8 *idlest_val) | 
|  | 56 | { | 
|  | 57 | *idlest_reg = (__force void __iomem *)(clk->enable_reg); | 
|  | 58 | *idlest_bit = clk->enable_bit + AM35XX_IPSS_ICK_EN_ACK_OFFSET; | 
|  | 59 | *idlest_val = AM35XX_IPSS_CLK_IDLEST_VAL; | 
|  | 60 | } | 
|  | 61 |  | 
|  | 62 | /** | 
|  | 63 | * am35xx_clk_find_companion - find companion clock to @clk | 
|  | 64 | * @clk: struct clk * to find the companion clock of | 
|  | 65 | * @other_reg: void __iomem ** to return the companion clock CM_*CLKEN va in | 
|  | 66 | * @other_bit: u8 ** to return the companion clock bit shift in | 
|  | 67 | * | 
|  | 68 | * Some clocks don't have companion clocks.  For example, modules with | 
|  | 69 | * only an interface clock (such as HECC) don't have a companion | 
|  | 70 | * clock.  Right now, this code relies on the hardware exporting a bit | 
|  | 71 | * in the correct companion register that indicates that the | 
|  | 72 | * nonexistent 'companion clock' is active.  Future patches will | 
|  | 73 | * associate this type of code with per-module data structures to | 
|  | 74 | * avoid this issue, and remove the casts.  No return value. | 
|  | 75 | */ | 
|  | 76 | static void am35xx_clk_find_companion(struct clk *clk, void __iomem **other_reg, | 
|  | 77 | u8 *other_bit) | 
|  | 78 | { | 
|  | 79 | *other_reg = (__force void __iomem *)(clk->enable_reg); | 
|  | 80 | if (clk->enable_bit & AM35XX_IPSS_ICK_MASK) | 
|  | 81 | *other_bit = clk->enable_bit + AM35XX_IPSS_ICK_FCK_OFFSET; | 
|  | 82 | else | 
|  | 83 | *other_bit = clk->enable_bit - AM35XX_IPSS_ICK_FCK_OFFSET; | 
|  | 84 | } | 
|  | 85 |  | 
|  | 86 | const struct clkops clkops_am35xx_ipss_module_wait = { | 
|  | 87 | .enable		= omap2_dflt_clk_enable, | 
|  | 88 | .disable	= omap2_dflt_clk_disable, | 
|  | 89 | .find_idlest	= am35xx_clk_find_idlest, | 
|  | 90 | .find_companion	= am35xx_clk_find_companion, | 
|  | 91 | }; | 
|  | 92 |  | 
|  | 93 | /** | 
|  | 94 | * am35xx_clk_ipss_find_idlest - return CM_IDLEST info for IPSS | 
|  | 95 | * @clk: struct clk * being enabled | 
|  | 96 | * @idlest_reg: void __iomem ** to store CM_IDLEST reg address into | 
|  | 97 | * @idlest_bit: pointer to a u8 to store the CM_IDLEST bit shift into | 
|  | 98 | * @idlest_val: pointer to a u8 to store the CM_IDLEST indicator | 
|  | 99 | * | 
|  | 100 | * The IPSS target CM_IDLEST bit is at a different shift from the | 
|  | 101 | * CM_{I,F}CLKEN bit.  Pass back the correct info via @idlest_reg | 
|  | 102 | * and @idlest_bit.  No return value. | 
|  | 103 | */ | 
|  | 104 | static void am35xx_clk_ipss_find_idlest(struct clk *clk, | 
|  | 105 | void __iomem **idlest_reg, | 
|  | 106 | u8 *idlest_bit, | 
|  | 107 | u8 *idlest_val) | 
|  | 108 | { | 
|  | 109 | u32 r; | 
|  | 110 |  | 
|  | 111 | r = (((__force u32)clk->enable_reg & ~0xf0) | 0x20); | 
|  | 112 | *idlest_reg = (__force void __iomem *)r; | 
|  | 113 | *idlest_bit = AM35XX_ST_IPSS_SHIFT; | 
|  | 114 | *idlest_val = OMAP34XX_CM_IDLEST_VAL; | 
|  | 115 | } | 
|  | 116 |  | 
|  | 117 | const struct clkops clkops_am35xx_ipss_wait = { | 
|  | 118 | .enable		= omap2_dflt_clk_enable, | 
|  | 119 | .disable	= omap2_dflt_clk_disable, | 
|  | 120 | .find_idlest	= am35xx_clk_ipss_find_idlest, | 
|  | 121 | .find_companion	= omap2_clk_dflt_find_companion, | 
|  | 122 | }; | 
|  | 123 |  | 
|  | 124 |  |