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review.evervolv.com / android_kernel_htc_msm8960 / 5af52b51f76d8f8dce0e5b2a33c20b2231c8046d / . / arch / arm / plat-s5pc1xx / clock.c
blob: 387f23190c3c99004a5bd59b39771f99cde01d88 [file] [log] [blame]
Kyungmin Parkff916f22009-11-17 08:41:13 +0100[diff] [blame]1/* linux/arch/arm/plat-s5pc1xx/clock.c
2 *
3 * Copyright 2009 Samsung Electronics Co.
4 *
5 * S5PC1XX Base clock support
6 *
7 * Based on plat-s3c64xx/clock.c
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12*/
13
14#include <linux/init.h>
15#include <linux/module.h>
16#include <linux/interrupt.h>
17#include <linux/ioport.h>
18#include <linux/clk.h>
19#include <linux/io.h>
20
21#include <mach/hardware.h>
22#include <mach/map.h>
23
24#include <plat/regs-clock.h>
25#include <plat/devs.h>
26#include <plat/clock.h>
27
28struct clk clk_27m = {
29 .name = "clk_27m",
30 .id = -1,
31 .rate = 27000000,
32};
33
34static int clk_48m_ctrl(struct clk *clk, int enable)
35{
36 unsigned long flags;
37 u32 val;
38
39 /* can't rely on clock lock, this register has other usages */
40 local_irq_save(flags);
41
42 val = __raw_readl(S5PC100_CLKSRC1);
43 if (enable)
44 val |= S5PC100_CLKSRC1_CLK48M_MASK;
45 else
46 val &= ~S5PC100_CLKSRC1_CLK48M_MASK;
47
48 __raw_writel(val, S5PC100_CLKSRC1);
49 local_irq_restore(flags);
50
51 return 0;
52}
53
54struct clk clk_48m = {
55 .name = "clk_48m",
56 .id = -1,
57 .rate = 48000000,
58 .enable = clk_48m_ctrl,
59};
60
61struct clk clk_54m = {
62 .name = "clk_54m",
63 .id = -1,
64 .rate = 54000000,
65};
66
Kyungmin Parkff916f22009-11-17 08:41:13 +0100[diff] [blame]67struct clk clk_hd0 = {
68 .name = "hclkd0",
69 .id = -1,
70 .rate = 0,
71 .parent = NULL,
72 .ctrlbit = 0,
Kukjin Kimed276842010-01-14 12:50:23 +0900[diff] [blame]73 .ops = &clk_ops_def_setrate,
Kyungmin Parkff916f22009-11-17 08:41:13 +0100[diff] [blame]74};
75
76struct clk clk_pd0 = {
77 .name = "pclkd0",
78 .id = -1,
79 .rate = 0,
80 .parent = NULL,
81 .ctrlbit = 0,
Kukjin Kimed276842010-01-14 12:50:23 +0900[diff] [blame]82 .ops = &clk_ops_def_setrate,
Kyungmin Parkff916f22009-11-17 08:41:13 +0100[diff] [blame]83};
84
85static int s5pc1xx_clk_gate(void __iomem *reg, struct clk *clk, int enable)
86{
87 unsigned int ctrlbit = clk->ctrlbit;
88 u32 con;
89
90 con = __raw_readl(reg);
91 if (enable)
92 con |= ctrlbit;
93 else
94 con &= ~ctrlbit;
95 __raw_writel(con, reg);
96
97 return 0;
98}
99
100static int s5pc100_clk_d00_ctrl(struct clk *clk, int enable)
101{
102 return s5pc1xx_clk_gate(S5PC100_CLKGATE_D00, clk, enable);
103}
104
105static int s5pc100_clk_d01_ctrl(struct clk *clk, int enable)
106{
107 return s5pc1xx_clk_gate(S5PC100_CLKGATE_D01, clk, enable);
108}
109
110static int s5pc100_clk_d02_ctrl(struct clk *clk, int enable)
111{
112 return s5pc1xx_clk_gate(S5PC100_CLKGATE_D02, clk, enable);
113}
114
115static int s5pc100_clk_d10_ctrl(struct clk *clk, int enable)
116{
117 return s5pc1xx_clk_gate(S5PC100_CLKGATE_D10, clk, enable);
118}
119
120static int s5pc100_clk_d11_ctrl(struct clk *clk, int enable)
121{
122 return s5pc1xx_clk_gate(S5PC100_CLKGATE_D11, clk, enable);
123}
124
125static int s5pc100_clk_d12_ctrl(struct clk *clk, int enable)
126{
127 return s5pc1xx_clk_gate(S5PC100_CLKGATE_D12, clk, enable);
128}
129
130static int s5pc100_clk_d13_ctrl(struct clk *clk, int enable)
131{
132 return s5pc1xx_clk_gate(S5PC100_CLKGATE_D13, clk, enable);
133}
134
135static int s5pc100_clk_d14_ctrl(struct clk *clk, int enable)
136{
137 return s5pc1xx_clk_gate(S5PC100_CLKGATE_D14, clk, enable);
138}
139
140static int s5pc100_clk_d15_ctrl(struct clk *clk, int enable)
141{
142 return s5pc1xx_clk_gate(S5PC100_CLKGATE_D15, clk, enable);
143}
144
145static int s5pc100_clk_d20_ctrl(struct clk *clk, int enable)
146{
147 return s5pc1xx_clk_gate(S5PC100_CLKGATE_D20, clk, enable);
148}
149
150int s5pc100_sclk0_ctrl(struct clk *clk, int enable)
151{
152 return s5pc1xx_clk_gate(S5PC100_SCLKGATE0, clk, enable);
153}
154
155int s5pc100_sclk1_ctrl(struct clk *clk, int enable)
156{
157 return s5pc1xx_clk_gate(S5PC100_SCLKGATE1, clk, enable);
158}
159
160static struct clk s5pc100_init_clocks_disable[] = {
161 {
162 .name = "dsi",
163 .id = -1,
164 .parent = &clk_p,
165 .enable = s5pc100_clk_d11_ctrl,
166 .ctrlbit = S5PC100_CLKGATE_D11_DSI,
167 }, {
168 .name = "csi",
169 .id = -1,
170 .parent = &clk_h,
171 .enable = s5pc100_clk_d11_ctrl,
172 .ctrlbit = S5PC100_CLKGATE_D11_CSI,
173 }, {
174 .name = "ccan",
175 .id = 0,
176 .parent = &clk_p,
177 .enable = s5pc100_clk_d14_ctrl,
178 .ctrlbit = S5PC100_CLKGATE_D14_CCAN0,
179 }, {
180 .name = "ccan",
181 .id = 1,
182 .parent = &clk_p,
183 .enable = s5pc100_clk_d14_ctrl,
184 .ctrlbit = S5PC100_CLKGATE_D14_CCAN1,
185 }, {
186 .name = "keypad",
187 .id = -1,
188 .parent = &clk_p,
189 .enable = s5pc100_clk_d15_ctrl,
190 .ctrlbit = S5PC100_CLKGATE_D15_KEYIF,
191 }, {
192 .name = "hclkd2",
193 .id = -1,
194 .parent = NULL,
195 .enable = s5pc100_clk_d20_ctrl,
196 .ctrlbit = S5PC100_CLKGATE_D20_HCLKD2,
197 }, {
198 .name = "iis-d2",
199 .id = -1,
200 .parent = NULL,
201 .enable = s5pc100_clk_d20_ctrl,
202 .ctrlbit = S5PC100_CLKGATE_D20_I2SD2,
203 },
204};
205
206static struct clk s5pc100_init_clocks[] = {
207 /* System1 (D0_0) devices */
208 {
209 .name = "intc",
210 .id = -1,
211 .parent = &clk_hd0,
212 .enable = s5pc100_clk_d00_ctrl,
213 .ctrlbit = S5PC100_CLKGATE_D00_INTC,
214 }, {
215 .name = "tzic",
216 .id = -1,
217 .parent = &clk_hd0,
218 .enable = s5pc100_clk_d00_ctrl,
219 .ctrlbit = S5PC100_CLKGATE_D00_TZIC,
220 }, {
221 .name = "cf-ata",
222 .id = -1,
223 .parent = &clk_hd0,
224 .enable = s5pc100_clk_d00_ctrl,
225 .ctrlbit = S5PC100_CLKGATE_D00_CFCON,
226 }, {
227 .name = "mdma",
228 .id = -1,
229 .parent = &clk_hd0,
230 .enable = s5pc100_clk_d00_ctrl,
231 .ctrlbit = S5PC100_CLKGATE_D00_MDMA,
232 }, {
233 .name = "g2d",
234 .id = -1,
235 .parent = &clk_hd0,
236 .enable = s5pc100_clk_d00_ctrl,
237 .ctrlbit = S5PC100_CLKGATE_D00_G2D,
238 }, {
239 .name = "secss",
240 .id = -1,
241 .parent = &clk_hd0,
242 .enable = s5pc100_clk_d00_ctrl,
243 .ctrlbit = S5PC100_CLKGATE_D00_SECSS,
244 }, {
245 .name = "cssys",
246 .id = -1,
247 .parent = &clk_hd0,
248 .enable = s5pc100_clk_d00_ctrl,
249 .ctrlbit = S5PC100_CLKGATE_D00_CSSYS,
250 },
251
252 /* Memory (D0_1) devices */
253 {
254 .name = "dmc",
255 .id = -1,
256 .parent = &clk_hd0,
257 .enable = s5pc100_clk_d01_ctrl,
258 .ctrlbit = S5PC100_CLKGATE_D01_DMC,
259 }, {
260 .name = "sromc",
261 .id = -1,
262 .parent = &clk_hd0,
263 .enable = s5pc100_clk_d01_ctrl,
264 .ctrlbit = S5PC100_CLKGATE_D01_SROMC,
265 }, {
266 .name = "onenand",
267 .id = -1,
268 .parent = &clk_hd0,
269 .enable = s5pc100_clk_d01_ctrl,
270 .ctrlbit = S5PC100_CLKGATE_D01_ONENAND,
271 }, {
272 .name = "nand",
273 .id = -1,
274 .parent = &clk_hd0,
275 .enable = s5pc100_clk_d01_ctrl,
276 .ctrlbit = S5PC100_CLKGATE_D01_NFCON,
277 }, {
278 .name = "intmem",
279 .id = -1,
280 .parent = &clk_hd0,
281 .enable = s5pc100_clk_d01_ctrl,
282 .ctrlbit = S5PC100_CLKGATE_D01_INTMEM,
283 }, {
284 .name = "ebi",
285 .id = -1,
286 .parent = &clk_hd0,
287 .enable = s5pc100_clk_d01_ctrl,
288 .ctrlbit = S5PC100_CLKGATE_D01_EBI,
289 },
290
291 /* System2 (D0_2) devices */
292 {
293 .name = "seckey",
294 .id = -1,
295 .parent = &clk_pd0,
296 .enable = s5pc100_clk_d02_ctrl,
297 .ctrlbit = S5PC100_CLKGATE_D02_SECKEY,
298 }, {
299 .name = "sdm",
300 .id = -1,
301 .parent = &clk_hd0,
302 .enable = s5pc100_clk_d02_ctrl,
303 .ctrlbit = S5PC100_CLKGATE_D02_SDM,
304 },
305
306 /* File (D1_0) devices */
307 {
308 .name = "pdma",
309 .id = 0,
310 .parent = &clk_h,
311 .enable = s5pc100_clk_d10_ctrl,
312 .ctrlbit = S5PC100_CLKGATE_D10_PDMA0,
313 }, {
314 .name = "pdma",
315 .id = 1,
316 .parent = &clk_h,
317 .enable = s5pc100_clk_d10_ctrl,
318 .ctrlbit = S5PC100_CLKGATE_D10_PDMA1,
319 }, {
320 .name = "usb-host",
321 .id = -1,
322 .parent = &clk_h,
323 .enable = s5pc100_clk_d10_ctrl,
324 .ctrlbit = S5PC100_CLKGATE_D10_USBHOST,
325 }, {
326 .name = "otg",
327 .id = -1,
328 .parent = &clk_h,
329 .enable = s5pc100_clk_d10_ctrl,
330 .ctrlbit = S5PC100_CLKGATE_D10_USBOTG,
331 }, {
332 .name = "modem",
333 .id = -1,
334 .parent = &clk_h,
335 .enable = s5pc100_clk_d10_ctrl,
336 .ctrlbit = S5PC100_CLKGATE_D10_MODEMIF,
337 }, {
338 .name = "hsmmc",
339 .id = 0,
340 .parent = &clk_48m,
341 .enable = s5pc100_clk_d10_ctrl,
342 .ctrlbit = S5PC100_CLKGATE_D10_HSMMC0,
343 }, {
344 .name = "hsmmc",
345 .id = 1,
346 .parent = &clk_48m,
347 .enable = s5pc100_clk_d10_ctrl,
348 .ctrlbit = S5PC100_CLKGATE_D10_HSMMC1,
349 }, {
350 .name = "hsmmc",
351 .id = 2,
352 .parent = &clk_48m,
353 .enable = s5pc100_clk_d10_ctrl,
354 .ctrlbit = S5PC100_CLKGATE_D10_HSMMC2,
355 },
356
357 /* Multimedia1 (D1_1) devices */
358 {
359 .name = "lcd",
360 .id = -1,
361 .parent = &clk_p,
362 .enable = s5pc100_clk_d11_ctrl,
363 .ctrlbit = S5PC100_CLKGATE_D11_LCD,
364 }, {
365 .name = "rotator",
366 .id = -1,
367 .parent = &clk_p,
368 .enable = s5pc100_clk_d11_ctrl,
369 .ctrlbit = S5PC100_CLKGATE_D11_ROTATOR,
370 }, {
371 .name = "fimc",
372 .id = -1,
373 .parent = &clk_p,
374 .enable = s5pc100_clk_d11_ctrl,
375 .ctrlbit = S5PC100_CLKGATE_D11_FIMC0,
376 }, {
377 .name = "fimc",
378 .id = -1,
379 .parent = &clk_p,
380 .enable = s5pc100_clk_d11_ctrl,
381 .ctrlbit = S5PC100_CLKGATE_D11_FIMC1,
382 }, {
383 .name = "fimc",
384 .id = -1,
385 .parent = &clk_p,
386 .enable = s5pc100_clk_d11_ctrl,
387 .ctrlbit = S5PC100_CLKGATE_D11_FIMC2,
388 }, {
389 .name = "jpeg",
390 .id = -1,
391 .parent = &clk_p,
392 .enable = s5pc100_clk_d11_ctrl,
393 .ctrlbit = S5PC100_CLKGATE_D11_JPEG,
394 }, {
395 .name = "g3d",
396 .id = -1,
397 .parent = &clk_p,
398 .enable = s5pc100_clk_d11_ctrl,
399 .ctrlbit = S5PC100_CLKGATE_D11_G3D,
400 },
401
402 /* Multimedia2 (D1_2) devices */
403 {
404 .name = "tv",
405 .id = -1,
406 .parent = &clk_p,
407 .enable = s5pc100_clk_d12_ctrl,
408 .ctrlbit = S5PC100_CLKGATE_D12_TV,
409 }, {
410 .name = "vp",
411 .id = -1,
412 .parent = &clk_p,
413 .enable = s5pc100_clk_d12_ctrl,
414 .ctrlbit = S5PC100_CLKGATE_D12_VP,
415 }, {
416 .name = "mixer",
417 .id = -1,
418 .parent = &clk_p,
419 .enable = s5pc100_clk_d12_ctrl,
420 .ctrlbit = S5PC100_CLKGATE_D12_MIXER,
421 }, {
422 .name = "hdmi",
423 .id = -1,
424 .parent = &clk_p,
425 .enable = s5pc100_clk_d12_ctrl,
426 .ctrlbit = S5PC100_CLKGATE_D12_HDMI,
427 }, {
428 .name = "mfc",
429 .id = -1,
430 .parent = &clk_p,
431 .enable = s5pc100_clk_d12_ctrl,
432 .ctrlbit = S5PC100_CLKGATE_D12_MFC,
433 },
434
435 /* System (D1_3) devices */
436 {
437 .name = "chipid",
438 .id = -1,
439 .parent = &clk_p,
440 .enable = s5pc100_clk_d13_ctrl,
441 .ctrlbit = S5PC100_CLKGATE_D13_CHIPID,
442 }, {
443 .name = "gpio",
444 .id = -1,
445 .parent = &clk_p,
446 .enable = s5pc100_clk_d13_ctrl,
447 .ctrlbit = S5PC100_CLKGATE_D13_GPIO,
448 }, {
449 .name = "apc",
450 .id = -1,
451 .parent = &clk_p,
452 .enable = s5pc100_clk_d13_ctrl,
453 .ctrlbit = S5PC100_CLKGATE_D13_APC,
454 }, {
455 .name = "iec",
456 .id = -1,
457 .parent = &clk_p,
458 .enable = s5pc100_clk_d13_ctrl,
459 .ctrlbit = S5PC100_CLKGATE_D13_IEC,
460 }, {
461 .name = "timers",
462 .id = -1,
463 .parent = &clk_p,
464 .enable = s5pc100_clk_d13_ctrl,
465 .ctrlbit = S5PC100_CLKGATE_D13_PWM,
466 }, {
467 .name = "systimer",
468 .id = -1,
469 .parent = &clk_p,
470 .enable = s5pc100_clk_d13_ctrl,
471 .ctrlbit = S5PC100_CLKGATE_D13_SYSTIMER,
472 }, {
473 .name = "watchdog",
474 .id = -1,
475 .parent = &clk_p,
476 .enable = s5pc100_clk_d13_ctrl,
477 .ctrlbit = S5PC100_CLKGATE_D13_WDT,
478 }, {
479 .name = "rtc",
480 .id = -1,
481 .parent = &clk_p,
482 .enable = s5pc100_clk_d13_ctrl,
483 .ctrlbit = S5PC100_CLKGATE_D13_RTC,
484 },
485
486 /* Connectivity (D1_4) devices */
487 {
488 .name = "uart",
489 .id = 0,
490 .parent = &clk_p,
491 .enable = s5pc100_clk_d14_ctrl,
492 .ctrlbit = S5PC100_CLKGATE_D14_UART0,
493 }, {
494 .name = "uart",
495 .id = 1,
496 .parent = &clk_p,
497 .enable = s5pc100_clk_d14_ctrl,
498 .ctrlbit = S5PC100_CLKGATE_D14_UART1,
499 }, {
500 .name = "uart",
501 .id = 2,
502 .parent = &clk_p,
503 .enable = s5pc100_clk_d14_ctrl,
504 .ctrlbit = S5PC100_CLKGATE_D14_UART2,
505 }, {
506 .name = "uart",
507 .id = 3,
508 .parent = &clk_p,
509 .enable = s5pc100_clk_d14_ctrl,
510 .ctrlbit = S5PC100_CLKGATE_D14_UART3,
511 }, {
512 .name = "i2c",
513 .id = -1,
514 .parent = &clk_p,
515 .enable = s5pc100_clk_d14_ctrl,
516 .ctrlbit = S5PC100_CLKGATE_D14_IIC,
517 }, {
518 .name = "hdmi-i2c",
519 .id = -1,
520 .parent = &clk_p,
521 .enable = s5pc100_clk_d14_ctrl,
522 .ctrlbit = S5PC100_CLKGATE_D14_HDMI_IIC,
523 }, {
524 .name = "spi",
525 .id = 0,
526 .parent = &clk_p,
527 .enable = s5pc100_clk_d14_ctrl,
528 .ctrlbit = S5PC100_CLKGATE_D14_SPI0,
529 }, {
530 .name = "spi",
531 .id = 1,
532 .parent = &clk_p,
533 .enable = s5pc100_clk_d14_ctrl,
534 .ctrlbit = S5PC100_CLKGATE_D14_SPI1,
535 }, {
536 .name = "spi",
537 .id = 2,
538 .parent = &clk_p,
539 .enable = s5pc100_clk_d14_ctrl,
540 .ctrlbit = S5PC100_CLKGATE_D14_SPI2,
541 }, {
542 .name = "irda",
543 .id = -1,
544 .parent = &clk_p,
545 .enable = s5pc100_clk_d14_ctrl,
546 .ctrlbit = S5PC100_CLKGATE_D14_IRDA,
547 }, {
548 .name = "hsitx",
549 .id = -1,
550 .parent = &clk_p,
551 .enable = s5pc100_clk_d14_ctrl,
552 .ctrlbit = S5PC100_CLKGATE_D14_HSITX,
553 }, {
554 .name = "hsirx",
555 .id = -1,
556 .parent = &clk_p,
557 .enable = s5pc100_clk_d14_ctrl,
558 .ctrlbit = S5PC100_CLKGATE_D14_HSIRX,
559 },
560
561 /* Audio (D1_5) devices */
562 {
563 .name = "iis",
564 .id = 0,
565 .parent = &clk_p,
566 .enable = s5pc100_clk_d15_ctrl,
567 .ctrlbit = S5PC100_CLKGATE_D15_IIS0,
568 }, {
569 .name = "iis",
570 .id = 1,
571 .parent = &clk_p,
572 .enable = s5pc100_clk_d15_ctrl,
573 .ctrlbit = S5PC100_CLKGATE_D15_IIS1,
574 }, {
575 .name = "iis",
576 .id = 2,
577 .parent = &clk_p,
578 .enable = s5pc100_clk_d15_ctrl,
579 .ctrlbit = S5PC100_CLKGATE_D15_IIS2,
580 }, {
581 .name = "ac97",
582 .id = -1,
583 .parent = &clk_p,
584 .enable = s5pc100_clk_d15_ctrl,
585 .ctrlbit = S5PC100_CLKGATE_D15_AC97,
586 }, {
587 .name = "pcm",
588 .id = 0,
589 .parent = &clk_p,
590 .enable = s5pc100_clk_d15_ctrl,
591 .ctrlbit = S5PC100_CLKGATE_D15_PCM0,
592 }, {
593 .name = "pcm",
594 .id = 1,
595 .parent = &clk_p,
596 .enable = s5pc100_clk_d15_ctrl,
597 .ctrlbit = S5PC100_CLKGATE_D15_PCM1,
598 }, {
599 .name = "spdif",
600 .id = -1,
601 .parent = &clk_p,
602 .enable = s5pc100_clk_d15_ctrl,
603 .ctrlbit = S5PC100_CLKGATE_D15_SPDIF,
604 }, {
605 .name = "adc",
606 .id = -1,
607 .parent = &clk_p,
608 .enable = s5pc100_clk_d15_ctrl,
609 .ctrlbit = S5PC100_CLKGATE_D15_TSADC,
610 }, {
611 .name = "cg",
612 .id = -1,
613 .parent = &clk_p,
614 .enable = s5pc100_clk_d15_ctrl,
615 .ctrlbit = S5PC100_CLKGATE_D15_CG,
616 },
617
618 /* Audio (D2_0) devices: all disabled */
619
620 /* Special Clocks 0 */
621 {
622 .name = "sclk_hpm",
623 .id = -1,
624 .parent = NULL,
625 .enable = s5pc100_sclk0_ctrl,
626 .ctrlbit = S5PC100_CLKGATE_SCLK0_HPM,
627 }, {
628 .name = "sclk_onenand",
629 .id = -1,
630 .parent = NULL,
631 .enable = s5pc100_sclk0_ctrl,
632 .ctrlbit = S5PC100_CLKGATE_SCLK0_ONENAND,
633 }, {
634 .name = "spi_48",
635 .id = 0,
636 .parent = &clk_48m,
637 .enable = s5pc100_sclk0_ctrl,
638 .ctrlbit = S5PC100_CLKGATE_SCLK0_SPI0_48,
639 }, {
640 .name = "spi_48",
641 .id = 1,
642 .parent = &clk_48m,
643 .enable = s5pc100_sclk0_ctrl,
644 .ctrlbit = S5PC100_CLKGATE_SCLK0_SPI1_48,
645 }, {
646 .name = "spi_48",
647 .id = 2,
648 .parent = &clk_48m,
649 .enable = s5pc100_sclk0_ctrl,
650 .ctrlbit = S5PC100_CLKGATE_SCLK0_SPI2_48,
651 }, {
652 .name = "mmc_48",
653 .id = 0,
654 .parent = &clk_48m,
655 .enable = s5pc100_sclk0_ctrl,
656 .ctrlbit = S5PC100_CLKGATE_SCLK0_MMC0_48,
657 }, {
658 .name = "mmc_48",
659 .id = 1,
660 .parent = &clk_48m,
661 .enable = s5pc100_sclk0_ctrl,
662 .ctrlbit = S5PC100_CLKGATE_SCLK0_MMC1_48,
663 }, {
664 .name = "mmc_48",
665 .id = 2,
666 .parent = &clk_48m,
667 .enable = s5pc100_sclk0_ctrl,
668 .ctrlbit = S5PC100_CLKGATE_SCLK0_MMC2_48,
669 },
670 /* Special Clocks 1 */
671};
672
673static struct clk *clks[] __initdata = {
674 &clk_ext,
675 &clk_epll,
Ben Dooksa0de2982010-01-18 13:24:01 +0900[diff] [blame]676 &clk_pd0,
677 &clk_hd0,
Kyungmin Parkff916f22009-11-17 08:41:13 +0100[diff] [blame]678 &clk_27m,
679 &clk_48m,
680 &clk_54m,
681};
682
683void __init s5pc1xx_register_clocks(void)
684{
685 struct clk *clkp;
686 int ret;
687 int ptr;
688 int size;
689
690 s3c24xx_register_clocks(clks, ARRAY_SIZE(clks));
691
Ben Dooks1d9f13c2010-01-06 01:21:38 +0900[diff] [blame]692 s3c_register_clocks(s5pc100_init_clocks,
693 ARRAY_SIZE(s5pc100_init_clocks));
Kyungmin Parkff916f22009-11-17 08:41:13 +0100[diff] [blame]694
695 clkp = s5pc100_init_clocks_disable;
696 size = ARRAY_SIZE(s5pc100_init_clocks_disable);
697
698 for (ptr = 0; ptr < size; ptr++, clkp++) {
699 ret = s3c24xx_register_clock(clkp);
700 if (ret < 0) {
701 printk(KERN_ERR "Failed to register clock %s (%d)\n",
702 clkp->name, ret);
703 }
704
705 (clkp->enable)(clkp, 0);
706 }
707
708 s3c_pwmclk_init();
709}