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review.evervolv.com / android_kernel_htc_msm8960 / 5b37b700f7c491a9320f4e29472bbaf23dded8fd / . / arch / ppc / syslib / mpc85xx_devices.c
blob: b30c57d4518f1d9847b1cc34be569b98f7012b8d [file] [log] [blame]
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]1/*
2 * arch/ppc/platforms/85xx/mpc85xx_devices.c
3 *
4 * MPC85xx Device descriptions
5 *
6 * Maintainer: Kumar Gala <kumar.gala@freescale.com>
7 *
8 * Copyright 2005 Freescale Semiconductor Inc.
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 */
15
16#include <linux/init.h>
17#include <linux/module.h>
18#include <linux/device.h>
19#include <linux/serial_8250.h>
20#include <linux/fsl_devices.h>
21#include <asm/mpc85xx.h>
22#include <asm/irq.h>
23#include <asm/ppc_sys.h>
24
25/* We use offsets for IORESOURCE_MEM since we do not know at compile time
26 * what CCSRBAR is, will get fixed up by mach_mpc85xx_fixup
27 */
28
29static struct gianfar_platform_data mpc85xx_tsec1_pdata = {
30 .device_flags = FSL_GIANFAR_DEV_HAS_GIGABIT |
31 FSL_GIANFAR_DEV_HAS_COALESCE | FSL_GIANFAR_DEV_HAS_RMON |
32 FSL_GIANFAR_DEV_HAS_MULTI_INTR,
33 .phy_reg_addr = MPC85xx_ENET1_OFFSET,
34};
35
36static struct gianfar_platform_data mpc85xx_tsec2_pdata = {
37 .device_flags = FSL_GIANFAR_DEV_HAS_GIGABIT |
38 FSL_GIANFAR_DEV_HAS_COALESCE | FSL_GIANFAR_DEV_HAS_RMON |
39 FSL_GIANFAR_DEV_HAS_MULTI_INTR,
40 .phy_reg_addr = MPC85xx_ENET1_OFFSET,
41};
42
Kumar Gala5b37b702005-06-21 17:15:18 -0700[diff] [blame^]43static struct gianfar_platform_data mpc85xx_etsec1_pdata = {
44 .device_flags = FSL_GIANFAR_DEV_HAS_GIGABIT |
45 FSL_GIANFAR_DEV_HAS_COALESCE | FSL_GIANFAR_DEV_HAS_RMON |
46 FSL_GIANFAR_DEV_HAS_MULTI_INTR |
47 FSL_GIANFAR_DEV_HAS_CSUM | FSL_GIANFAR_DEV_HAS_VLAN |
48 FSL_GIANFAR_DEV_HAS_EXTENDED_HASH,
49 .phy_reg_addr = MPC85xx_ENET1_OFFSET,
50};
51
52static struct gianfar_platform_data mpc85xx_etsec2_pdata = {
53 .device_flags = FSL_GIANFAR_DEV_HAS_GIGABIT |
54 FSL_GIANFAR_DEV_HAS_COALESCE | FSL_GIANFAR_DEV_HAS_RMON |
55 FSL_GIANFAR_DEV_HAS_MULTI_INTR |
56 FSL_GIANFAR_DEV_HAS_CSUM | FSL_GIANFAR_DEV_HAS_VLAN |
57 FSL_GIANFAR_DEV_HAS_EXTENDED_HASH,
58 .phy_reg_addr = MPC85xx_ENET1_OFFSET,
59};
60
61static struct gianfar_platform_data mpc85xx_etsec3_pdata = {
62 .device_flags = FSL_GIANFAR_DEV_HAS_GIGABIT |
63 FSL_GIANFAR_DEV_HAS_COALESCE | FSL_GIANFAR_DEV_HAS_RMON |
64 FSL_GIANFAR_DEV_HAS_MULTI_INTR |
65 FSL_GIANFAR_DEV_HAS_CSUM | FSL_GIANFAR_DEV_HAS_VLAN |
66 FSL_GIANFAR_DEV_HAS_EXTENDED_HASH,
67 .phy_reg_addr = MPC85xx_ENET1_OFFSET,
68};
69
70static struct gianfar_platform_data mpc85xx_etsec4_pdata = {
71 .device_flags = FSL_GIANFAR_DEV_HAS_GIGABIT |
72 FSL_GIANFAR_DEV_HAS_COALESCE | FSL_GIANFAR_DEV_HAS_RMON |
73 FSL_GIANFAR_DEV_HAS_MULTI_INTR |
74 FSL_GIANFAR_DEV_HAS_CSUM | FSL_GIANFAR_DEV_HAS_VLAN |
75 FSL_GIANFAR_DEV_HAS_EXTENDED_HASH,
76 .phy_reg_addr = MPC85xx_ENET1_OFFSET,
77};
78
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]79static struct gianfar_platform_data mpc85xx_fec_pdata = {
80 .phy_reg_addr = MPC85xx_ENET1_OFFSET,
81};
82
83static struct fsl_i2c_platform_data mpc85xx_fsl_i2c_pdata = {
84 .device_flags = FSL_I2C_DEV_SEPARATE_DFSRR,
85};
86
Kumar Gala5b37b702005-06-21 17:15:18 -0700[diff] [blame^]87static struct fsl_i2c_platform_data mpc85xx_fsl_i2c2_pdata = {
88 .device_flags = FSL_I2C_DEV_SEPARATE_DFSRR,
89};
90
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]91static struct plat_serial8250_port serial_platform_data[] = {
92 [0] = {
93 .mapbase = 0x4500,
94 .irq = MPC85xx_IRQ_DUART,
95 .iotype = UPIO_MEM,
96 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_SHARE_IRQ,
97 },
98 [1] = {
99 .mapbase = 0x4600,
100 .irq = MPC85xx_IRQ_DUART,
101 .iotype = UPIO_MEM,
102 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_SHARE_IRQ,
103 },
Kumar Gala7f8cd802005-05-20 13:59:13 -0700[diff] [blame]104 { },
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]105};
106
107struct platform_device ppc_sys_platform_devices[] = {
108 [MPC85xx_TSEC1] = {
109 .name = "fsl-gianfar",
110 .id = 1,
111 .dev.platform_data = &mpc85xx_tsec1_pdata,
112 .num_resources = 4,
113 .resource = (struct resource[]) {
114 {
115 .start = MPC85xx_ENET1_OFFSET,
116 .end = MPC85xx_ENET1_OFFSET +
117 MPC85xx_ENET1_SIZE - 1,
118 .flags = IORESOURCE_MEM,
119 },
120 {
121 .name = "tx",
122 .start = MPC85xx_IRQ_TSEC1_TX,
123 .end = MPC85xx_IRQ_TSEC1_TX,
124 .flags = IORESOURCE_IRQ,
125 },
126 {
127 .name = "rx",
128 .start = MPC85xx_IRQ_TSEC1_RX,
129 .end = MPC85xx_IRQ_TSEC1_RX,
130 .flags = IORESOURCE_IRQ,
131 },
132 {
133 .name = "error",
134 .start = MPC85xx_IRQ_TSEC1_ERROR,
135 .end = MPC85xx_IRQ_TSEC1_ERROR,
136 .flags = IORESOURCE_IRQ,
137 },
138 },
139 },
140 [MPC85xx_TSEC2] = {
141 .name = "fsl-gianfar",
142 .id = 2,
143 .dev.platform_data = &mpc85xx_tsec2_pdata,
144 .num_resources = 4,
145 .resource = (struct resource[]) {
146 {
147 .start = MPC85xx_ENET2_OFFSET,
148 .end = MPC85xx_ENET2_OFFSET +
149 MPC85xx_ENET2_SIZE - 1,
150 .flags = IORESOURCE_MEM,
151 },
152 {
153 .name = "tx",
154 .start = MPC85xx_IRQ_TSEC2_TX,
155 .end = MPC85xx_IRQ_TSEC2_TX,
156 .flags = IORESOURCE_IRQ,
157 },
158 {
159 .name = "rx",
160 .start = MPC85xx_IRQ_TSEC2_RX,
161 .end = MPC85xx_IRQ_TSEC2_RX,
162 .flags = IORESOURCE_IRQ,
163 },
164 {
165 .name = "error",
166 .start = MPC85xx_IRQ_TSEC2_ERROR,
167 .end = MPC85xx_IRQ_TSEC2_ERROR,
168 .flags = IORESOURCE_IRQ,
169 },
170 },
171 },
172 [MPC85xx_FEC] = {
173 .name = "fsl-gianfar",
174 .id = 3,
175 .dev.platform_data = &mpc85xx_fec_pdata,
176 .num_resources = 2,
177 .resource = (struct resource[]) {
178 {
179 .start = MPC85xx_ENET3_OFFSET,
180 .end = MPC85xx_ENET3_OFFSET +
181 MPC85xx_ENET3_SIZE - 1,
182 .flags = IORESOURCE_MEM,
183
184 },
185 {
186 .start = MPC85xx_IRQ_FEC,
187 .end = MPC85xx_IRQ_FEC,
188 .flags = IORESOURCE_IRQ,
189 },
190 },
191 },
192 [MPC85xx_IIC1] = {
193 .name = "fsl-i2c",
194 .id = 1,
195 .dev.platform_data = &mpc85xx_fsl_i2c_pdata,
196 .num_resources = 2,
197 .resource = (struct resource[]) {
198 {
199 .start = MPC85xx_IIC1_OFFSET,
200 .end = MPC85xx_IIC1_OFFSET +
201 MPC85xx_IIC1_SIZE - 1,
202 .flags = IORESOURCE_MEM,
203 },
204 {
205 .start = MPC85xx_IRQ_IIC1,
206 .end = MPC85xx_IRQ_IIC1,
207 .flags = IORESOURCE_IRQ,
208 },
209 },
210 },
211 [MPC85xx_DMA0] = {
212 .name = "fsl-dma",
213 .id = 0,
214 .num_resources = 2,
215 .resource = (struct resource[]) {
216 {
217 .start = MPC85xx_DMA0_OFFSET,
218 .end = MPC85xx_DMA0_OFFSET +
219 MPC85xx_DMA0_SIZE - 1,
220 .flags = IORESOURCE_MEM,
221 },
222 {
223 .start = MPC85xx_IRQ_DMA0,
224 .end = MPC85xx_IRQ_DMA0,
225 .flags = IORESOURCE_IRQ,
226 },
227 },
228 },
229 [MPC85xx_DMA1] = {
230 .name = "fsl-dma",
231 .id = 1,
232 .num_resources = 2,
233 .resource = (struct resource[]) {
234 {
235 .start = MPC85xx_DMA1_OFFSET,
236 .end = MPC85xx_DMA1_OFFSET +
237 MPC85xx_DMA1_SIZE - 1,
238 .flags = IORESOURCE_MEM,
239 },
240 {
241 .start = MPC85xx_IRQ_DMA1,
242 .end = MPC85xx_IRQ_DMA1,
243 .flags = IORESOURCE_IRQ,
244 },
245 },
246 },
247 [MPC85xx_DMA2] = {
248 .name = "fsl-dma",
249 .id = 2,
250 .num_resources = 2,
251 .resource = (struct resource[]) {
252 {
253 .start = MPC85xx_DMA2_OFFSET,
254 .end = MPC85xx_DMA2_OFFSET +
255 MPC85xx_DMA2_SIZE - 1,
256 .flags = IORESOURCE_MEM,
257 },
258 {
259 .start = MPC85xx_IRQ_DMA2,
260 .end = MPC85xx_IRQ_DMA2,
261 .flags = IORESOURCE_IRQ,
262 },
263 },
264 },
265 [MPC85xx_DMA3] = {
266 .name = "fsl-dma",
267 .id = 3,
268 .num_resources = 2,
269 .resource = (struct resource[]) {
270 {
271 .start = MPC85xx_DMA3_OFFSET,
272 .end = MPC85xx_DMA3_OFFSET +
273 MPC85xx_DMA3_SIZE - 1,
274 .flags = IORESOURCE_MEM,
275 },
276 {
277 .start = MPC85xx_IRQ_DMA3,
278 .end = MPC85xx_IRQ_DMA3,
279 .flags = IORESOURCE_IRQ,
280 },
281 },
282 },
283 [MPC85xx_DUART] = {
284 .name = "serial8250",
285 .id = 0,
286 .dev.platform_data = serial_platform_data,
287 },
288 [MPC85xx_PERFMON] = {
289 .name = "fsl-perfmon",
290 .id = 1,
291 .num_resources = 2,
292 .resource = (struct resource[]) {
293 {
294 .start = MPC85xx_PERFMON_OFFSET,
295 .end = MPC85xx_PERFMON_OFFSET +
296 MPC85xx_PERFMON_SIZE - 1,
297 .flags = IORESOURCE_MEM,
298 },
299 {
300 .start = MPC85xx_IRQ_PERFMON,
301 .end = MPC85xx_IRQ_PERFMON,
302 .flags = IORESOURCE_IRQ,
303 },
304 },
305 },
306 [MPC85xx_SEC2] = {
307 .name = "fsl-sec2",
308 .id = 1,
309 .num_resources = 2,
310 .resource = (struct resource[]) {
311 {
312 .start = MPC85xx_SEC2_OFFSET,
313 .end = MPC85xx_SEC2_OFFSET +
314 MPC85xx_SEC2_SIZE - 1,
315 .flags = IORESOURCE_MEM,
316 },
317 {
318 .start = MPC85xx_IRQ_SEC2,
319 .end = MPC85xx_IRQ_SEC2,
320 .flags = IORESOURCE_IRQ,
321 },
322 },
323 },
324#ifdef CONFIG_CPM2
325 [MPC85xx_CPM_FCC1] = {
326 .name = "fsl-cpm-fcc",
327 .id = 1,
328 .num_resources = 3,
329 .resource = (struct resource[]) {
330 {
331 .start = 0x91300,
332 .end = 0x9131F,
333 .flags = IORESOURCE_MEM,
334 },
335 {
336 .start = 0x91380,
337 .end = 0x9139F,
338 .flags = IORESOURCE_MEM,
339 },
340 {
341 .start = SIU_INT_FCC1,
342 .end = SIU_INT_FCC1,
343 .flags = IORESOURCE_IRQ,
344 },
345 },
346 },
347 [MPC85xx_CPM_FCC2] = {
348 .name = "fsl-cpm-fcc",
349 .id = 2,
350 .num_resources = 3,
351 .resource = (struct resource[]) {
352 {
353 .start = 0x91320,
354 .end = 0x9133F,
355 .flags = IORESOURCE_MEM,
356 },
357 {
358 .start = 0x913A0,
359 .end = 0x913CF,
360 .flags = IORESOURCE_MEM,
361 },
362 {
363 .start = SIU_INT_FCC2,
364 .end = SIU_INT_FCC2,
365 .flags = IORESOURCE_IRQ,
366 },
367 },
368 },
369 [MPC85xx_CPM_FCC3] = {
370 .name = "fsl-cpm-fcc",
371 .id = 3,
372 .num_resources = 3,
373 .resource = (struct resource[]) {
374 {
375 .start = 0x91340,
376 .end = 0x9135F,
377 .flags = IORESOURCE_MEM,
378 },
379 {
380 .start = 0x913D0,
381 .end = 0x913FF,
382 .flags = IORESOURCE_MEM,
383 },
384 {
385 .start = SIU_INT_FCC3,
386 .end = SIU_INT_FCC3,
387 .flags = IORESOURCE_IRQ,
388 },
389 },
390 },
391 [MPC85xx_CPM_I2C] = {
392 .name = "fsl-cpm-i2c",
393 .id = 1,
394 .num_resources = 2,
395 .resource = (struct resource[]) {
396 {
397 .start = 0x91860,
398 .end = 0x918BF,
399 .flags = IORESOURCE_MEM,
400 },
401 {
402 .start = SIU_INT_I2C,
403 .end = SIU_INT_I2C,
404 .flags = IORESOURCE_IRQ,
405 },
406 },
407 },
408 [MPC85xx_CPM_SCC1] = {
409 .name = "fsl-cpm-scc",
410 .id = 1,
411 .num_resources = 2,
412 .resource = (struct resource[]) {
413 {
414 .start = 0x91A00,
415 .end = 0x91A1F,
416 .flags = IORESOURCE_MEM,
417 },
418 {
419 .start = SIU_INT_SCC1,
420 .end = SIU_INT_SCC1,
421 .flags = IORESOURCE_IRQ,
422 },
423 },
424 },
425 [MPC85xx_CPM_SCC2] = {
426 .name = "fsl-cpm-scc",
427 .id = 2,
428 .num_resources = 2,
429 .resource = (struct resource[]) {
430 {
431 .start = 0x91A20,
432 .end = 0x91A3F,
433 .flags = IORESOURCE_MEM,
434 },
435 {
436 .start = SIU_INT_SCC2,
437 .end = SIU_INT_SCC2,
438 .flags = IORESOURCE_IRQ,
439 },
440 },
441 },
442 [MPC85xx_CPM_SCC3] = {
443 .name = "fsl-cpm-scc",
444 .id = 3,
445 .num_resources = 2,
446 .resource = (struct resource[]) {
447 {
448 .start = 0x91A40,
449 .end = 0x91A5F,
450 .flags = IORESOURCE_MEM,
451 },
452 {
453 .start = SIU_INT_SCC3,
454 .end = SIU_INT_SCC3,
455 .flags = IORESOURCE_IRQ,
456 },
457 },
458 },
459 [MPC85xx_CPM_SCC4] = {
460 .name = "fsl-cpm-scc",
461 .id = 4,
462 .num_resources = 2,
463 .resource = (struct resource[]) {
464 {
465 .start = 0x91A60,
466 .end = 0x91A7F,
467 .flags = IORESOURCE_MEM,
468 },
469 {
470 .start = SIU_INT_SCC4,
471 .end = SIU_INT_SCC4,
472 .flags = IORESOURCE_IRQ,
473 },
474 },
475 },
476 [MPC85xx_CPM_SPI] = {
477 .name = "fsl-cpm-spi",
478 .id = 1,
479 .num_resources = 2,
480 .resource = (struct resource[]) {
481 {
482 .start = 0x91AA0,
483 .end = 0x91AFF,
484 .flags = IORESOURCE_MEM,
485 },
486 {
487 .start = SIU_INT_SPI,
488 .end = SIU_INT_SPI,
489 .flags = IORESOURCE_IRQ,
490 },
491 },
492 },
493 [MPC85xx_CPM_MCC1] = {
494 .name = "fsl-cpm-mcc",
495 .id = 1,
496 .num_resources = 2,
497 .resource = (struct resource[]) {
498 {
499 .start = 0x91B30,
500 .end = 0x91B3F,
501 .flags = IORESOURCE_MEM,
502 },
503 {
504 .start = SIU_INT_MCC1,
505 .end = SIU_INT_MCC1,
506 .flags = IORESOURCE_IRQ,
507 },
508 },
509 },
510 [MPC85xx_CPM_MCC2] = {
511 .name = "fsl-cpm-mcc",
512 .id = 2,
513 .num_resources = 2,
514 .resource = (struct resource[]) {
515 {
516 .start = 0x91B50,
517 .end = 0x91B5F,
518 .flags = IORESOURCE_MEM,
519 },
520 {
521 .start = SIU_INT_MCC2,
522 .end = SIU_INT_MCC2,
523 .flags = IORESOURCE_IRQ,
524 },
525 },
526 },
527 [MPC85xx_CPM_SMC1] = {
528 .name = "fsl-cpm-smc",
529 .id = 1,
530 .num_resources = 2,
531 .resource = (struct resource[]) {
532 {
533 .start = 0x91A80,
534 .end = 0x91A8F,
535 .flags = IORESOURCE_MEM,
536 },
537 {
538 .start = SIU_INT_SMC1,
539 .end = SIU_INT_SMC1,
540 .flags = IORESOURCE_IRQ,
541 },
542 },
543 },
544 [MPC85xx_CPM_SMC2] = {
545 .name = "fsl-cpm-smc",
546 .id = 2,
547 .num_resources = 2,
548 .resource = (struct resource[]) {
549 {
550 .start = 0x91A90,
551 .end = 0x91A9F,
552 .flags = IORESOURCE_MEM,
553 },
554 {
555 .start = SIU_INT_SMC2,
556 .end = SIU_INT_SMC2,
557 .flags = IORESOURCE_IRQ,
558 },
559 },
560 },
561 [MPC85xx_CPM_USB] = {
562 .name = "fsl-cpm-usb",
563 .id = 2,
564 .num_resources = 2,
565 .resource = (struct resource[]) {
566 {
567 .start = 0x91B60,
568 .end = 0x91B7F,
569 .flags = IORESOURCE_MEM,
570 },
571 {
572 .start = SIU_INT_USB,
573 .end = SIU_INT_USB,
574 .flags = IORESOURCE_IRQ,
575 },
576 },
577 },
578#endif /* CONFIG_CPM2 */
Kumar Gala5b37b702005-06-21 17:15:18 -0700[diff] [blame^]579 [MPC85xx_eTSEC1] = {
580 .name = "fsl-gianfar",
581 .id = 1,
582 .dev.platform_data = &mpc85xx_etsec1_pdata,
583 .num_resources = 4,
584 .resource = (struct resource[]) {
585 {
586 .start = MPC85xx_ENET1_OFFSET,
587 .end = MPC85xx_ENET1_OFFSET +
588 MPC85xx_ENET1_SIZE - 1,
589 .flags = IORESOURCE_MEM,
590 },
591 {
592 .name = "tx",
593 .start = MPC85xx_IRQ_TSEC1_TX,
594 .end = MPC85xx_IRQ_TSEC1_TX,
595 .flags = IORESOURCE_IRQ,
596 },
597 {
598 .name = "rx",
599 .start = MPC85xx_IRQ_TSEC1_RX,
600 .end = MPC85xx_IRQ_TSEC1_RX,
601 .flags = IORESOURCE_IRQ,
602 },
603 {
604 .name = "error",
605 .start = MPC85xx_IRQ_TSEC1_ERROR,
606 .end = MPC85xx_IRQ_TSEC1_ERROR,
607 .flags = IORESOURCE_IRQ,
608 },
609 },
610 },
611 [MPC85xx_eTSEC2] = {
612 .name = "fsl-gianfar",
613 .id = 2,
614 .dev.platform_data = &mpc85xx_etsec2_pdata,
615 .num_resources = 4,
616 .resource = (struct resource[]) {
617 {
618 .start = MPC85xx_ENET2_OFFSET,
619 .end = MPC85xx_ENET2_OFFSET +
620 MPC85xx_ENET2_SIZE - 1,
621 .flags = IORESOURCE_MEM,
622 },
623 {
624 .name = "tx",
625 .start = MPC85xx_IRQ_TSEC2_TX,
626 .end = MPC85xx_IRQ_TSEC2_TX,
627 .flags = IORESOURCE_IRQ,
628 },
629 {
630 .name = "rx",
631 .start = MPC85xx_IRQ_TSEC2_RX,
632 .end = MPC85xx_IRQ_TSEC2_RX,
633 .flags = IORESOURCE_IRQ,
634 },
635 {
636 .name = "error",
637 .start = MPC85xx_IRQ_TSEC2_ERROR,
638 .end = MPC85xx_IRQ_TSEC2_ERROR,
639 .flags = IORESOURCE_IRQ,
640 },
641 },
642 },
643 [MPC85xx_eTSEC3] = {
644 .name = "fsl-gianfar",
645 .id = 3,
646 .dev.platform_data = &mpc85xx_etsec3_pdata,
647 .num_resources = 4,
648 .resource = (struct resource[]) {
649 {
650 .start = MPC85xx_ENET3_OFFSET,
651 .end = MPC85xx_ENET3_OFFSET +
652 MPC85xx_ENET3_SIZE - 1,
653 .flags = IORESOURCE_MEM,
654 },
655 {
656 .name = "tx",
657 .start = MPC85xx_IRQ_TSEC3_TX,
658 .end = MPC85xx_IRQ_TSEC3_TX,
659 .flags = IORESOURCE_IRQ,
660 },
661 {
662 .name = "rx",
663 .start = MPC85xx_IRQ_TSEC3_RX,
664 .end = MPC85xx_IRQ_TSEC3_RX,
665 .flags = IORESOURCE_IRQ,
666 },
667 {
668 .name = "error",
669 .start = MPC85xx_IRQ_TSEC3_ERROR,
670 .end = MPC85xx_IRQ_TSEC3_ERROR,
671 .flags = IORESOURCE_IRQ,
672 },
673 },
674 },
675 [MPC85xx_eTSEC4] = {
676 .name = "fsl-gianfar",
677 .id = 4,
678 .dev.platform_data = &mpc85xx_etsec4_pdata,
679 .num_resources = 4,
680 .resource = (struct resource[]) {
681 {
682 .start = 0x27000,
683 .end = 0x27fff,
684 .flags = IORESOURCE_MEM,
685 },
686 {
687 .name = "tx",
688 .start = MPC85xx_IRQ_TSEC4_TX,
689 .end = MPC85xx_IRQ_TSEC4_TX,
690 .flags = IORESOURCE_IRQ,
691 },
692 {
693 .name = "rx",
694 .start = MPC85xx_IRQ_TSEC4_RX,
695 .end = MPC85xx_IRQ_TSEC4_RX,
696 .flags = IORESOURCE_IRQ,
697 },
698 {
699 .name = "error",
700 .start = MPC85xx_IRQ_TSEC4_ERROR,
701 .end = MPC85xx_IRQ_TSEC4_ERROR,
702 .flags = IORESOURCE_IRQ,
703 },
704 },
705 },
706 [MPC85xx_IIC2] = {
707 .name = "fsl-i2c",
708 .id = 2,
709 .dev.platform_data = &mpc85xx_fsl_i2c2_pdata,
710 .num_resources = 2,
711 .resource = (struct resource[]) {
712 {
713 .start = 0x03100,
714 .end = 0x031ff,
715 .flags = IORESOURCE_MEM,
716 },
717 {
718 .start = MPC85xx_IRQ_IIC1,
719 .end = MPC85xx_IRQ_IIC1,
720 .flags = IORESOURCE_IRQ,
721 },
722 },
723 },
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]724};
725
726static int __init mach_mpc85xx_fixup(struct platform_device *pdev)
727{
728 ppc_sys_fixup_mem_resource(pdev, CCSRBAR);
729 return 0;
730}
731
732static int __init mach_mpc85xx_init(void)
733{
734 ppc_sys_device_fixup = mach_mpc85xx_fixup;
735 return 0;
736}
737
738postcore_initcall(mach_mpc85xx_init);