blob: ab9e70c0572f5f63530815ef95da185a2514ce34 [file] [log] [blame]
Kiran Kumar H Ndd128472011-12-01 09:35:34 -08001/* Copyright (c) 2011-2012, Code Aurora Forum. All rights reserved.
2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 *
12 */
Shuzhen Wangce650862011-08-17 15:27:01 -070013#ifndef __MSM_ISP_H__
14#define __MSM_ISP_H__
15
Kiran Kumar H Ndd128472011-12-01 09:35:34 -080016#define BIT(nr) (1UL << (nr))
17
Shuzhen Wangce650862011-08-17 15:27:01 -070018/* ISP message IDs */
19#define MSG_ID_RESET_ACK 0
20#define MSG_ID_START_ACK 1
21#define MSG_ID_STOP_ACK 2
22#define MSG_ID_UPDATE_ACK 3
23#define MSG_ID_OUTPUT_P 4
24#define MSG_ID_OUTPUT_T 5
25#define MSG_ID_OUTPUT_S 6
26#define MSG_ID_OUTPUT_V 7
27#define MSG_ID_SNAPSHOT_DONE 8
28#define MSG_ID_STATS_AEC 9
29#define MSG_ID_STATS_AF 10
30#define MSG_ID_STATS_AWB 11
31#define MSG_ID_STATS_RS 12
32#define MSG_ID_STATS_CS 13
33#define MSG_ID_STATS_IHIST 14
34#define MSG_ID_STATS_SKIN 15
35#define MSG_ID_EPOCH1 16
36#define MSG_ID_EPOCH2 17
37#define MSG_ID_SYNC_TIMER0_DONE 18
38#define MSG_ID_SYNC_TIMER1_DONE 19
39#define MSG_ID_SYNC_TIMER2_DONE 20
40#define MSG_ID_ASYNC_TIMER0_DONE 21
41#define MSG_ID_ASYNC_TIMER1_DONE 22
42#define MSG_ID_ASYNC_TIMER2_DONE 23
43#define MSG_ID_ASYNC_TIMER3_DONE 24
44#define MSG_ID_AE_OVERFLOW 25
45#define MSG_ID_AF_OVERFLOW 26
46#define MSG_ID_AWB_OVERFLOW 27
47#define MSG_ID_RS_OVERFLOW 28
48#define MSG_ID_CS_OVERFLOW 29
49#define MSG_ID_IHIST_OVERFLOW 30
50#define MSG_ID_SKIN_OVERFLOW 31
51#define MSG_ID_AXI_ERROR 32
52#define MSG_ID_CAMIF_OVERFLOW 33
53#define MSG_ID_VIOLATION 34
54#define MSG_ID_CAMIF_ERROR 35
55#define MSG_ID_BUS_OVERFLOW 36
56#define MSG_ID_SOF_ACK 37
57#define MSG_ID_STOP_REC_ACK 38
Suresh Vankadara055cb8e2012-01-18 00:50:04 +053058#define MSG_ID_STATS_AWB_AEC 39
Kiran Kumar H Ndd128472011-12-01 09:35:34 -080059#define MSG_ID_OUTPUT_PRIMARY 40
60#define MSG_ID_OUTPUT_SECONDARY 41
Shuzhen Wang74768242011-09-02 17:38:01 -070061#define MSG_ID_STATS_COMPOSITE 42
Nishant Pandit28feb3d2012-04-26 23:56:22 +053062#define MSG_ID_OUTPUT_TERTIARY1 43
Kiran Kumar H N1bc7b222012-06-23 16:28:11 -070063#define MSG_ID_STOP_LS_ACK 44
Nishant Pandit5dd54422012-06-26 22:52:44 +053064#define MSG_ID_OUTPUT_TERTIARY2 45
Lakshmi Narayana Kalavalabc315ea2012-07-24 09:55:48 -070065#define MSG_ID_STATS_BG 46
66#define MSG_ID_STATS_BF 47
67#define MSG_ID_STATS_BHIST 48
68
Shuzhen Wangce650862011-08-17 15:27:01 -070069
70/* ISP command IDs */
71#define VFE_CMD_DUMMY_0 0
72#define VFE_CMD_SET_CLK 1
73#define VFE_CMD_RESET 2
74#define VFE_CMD_START 3
75#define VFE_CMD_TEST_GEN_START 4
76#define VFE_CMD_OPERATION_CFG 5
77#define VFE_CMD_AXI_OUT_CFG 6
78#define VFE_CMD_CAMIF_CFG 7
79#define VFE_CMD_AXI_INPUT_CFG 8
80#define VFE_CMD_BLACK_LEVEL_CFG 9
Ujwal Pateledcbdcc2011-08-24 09:14:14 -070081#define VFE_CMD_MESH_ROLL_OFF_CFG 10
Shuzhen Wangce650862011-08-17 15:27:01 -070082#define VFE_CMD_DEMUX_CFG 11
83#define VFE_CMD_FOV_CFG 12
84#define VFE_CMD_MAIN_SCALER_CFG 13
85#define VFE_CMD_WB_CFG 14
86#define VFE_CMD_COLOR_COR_CFG 15
87#define VFE_CMD_RGB_G_CFG 16
88#define VFE_CMD_LA_CFG 17
89#define VFE_CMD_CHROMA_EN_CFG 18
90#define VFE_CMD_CHROMA_SUP_CFG 19
91#define VFE_CMD_MCE_CFG 20
92#define VFE_CMD_SK_ENHAN_CFG 21
93#define VFE_CMD_ASF_CFG 22
94#define VFE_CMD_S2Y_CFG 23
95#define VFE_CMD_S2CbCr_CFG 24
96#define VFE_CMD_CHROMA_SUBS_CFG 25
97#define VFE_CMD_OUT_CLAMP_CFG 26
98#define VFE_CMD_FRAME_SKIP_CFG 27
99#define VFE_CMD_DUMMY_1 28
100#define VFE_CMD_DUMMY_2 29
101#define VFE_CMD_DUMMY_3 30
102#define VFE_CMD_UPDATE 31
103#define VFE_CMD_BL_LVL_UPDATE 32
104#define VFE_CMD_DEMUX_UPDATE 33
105#define VFE_CMD_FOV_UPDATE 34
106#define VFE_CMD_MAIN_SCALER_UPDATE 35
107#define VFE_CMD_WB_UPDATE 36
108#define VFE_CMD_COLOR_COR_UPDATE 37
109#define VFE_CMD_RGB_G_UPDATE 38
110#define VFE_CMD_LA_UPDATE 39
111#define VFE_CMD_CHROMA_EN_UPDATE 40
112#define VFE_CMD_CHROMA_SUP_UPDATE 41
113#define VFE_CMD_MCE_UPDATE 42
114#define VFE_CMD_SK_ENHAN_UPDATE 43
115#define VFE_CMD_S2CbCr_UPDATE 44
116#define VFE_CMD_S2Y_UPDATE 45
117#define VFE_CMD_ASF_UPDATE 46
118#define VFE_CMD_FRAME_SKIP_UPDATE 47
119#define VFE_CMD_CAMIF_FRAME_UPDATE 48
120#define VFE_CMD_STATS_AF_UPDATE 49
121#define VFE_CMD_STATS_AE_UPDATE 50
122#define VFE_CMD_STATS_AWB_UPDATE 51
123#define VFE_CMD_STATS_RS_UPDATE 52
124#define VFE_CMD_STATS_CS_UPDATE 53
125#define VFE_CMD_STATS_SKIN_UPDATE 54
126#define VFE_CMD_STATS_IHIST_UPDATE 55
127#define VFE_CMD_DUMMY_4 56
128#define VFE_CMD_EPOCH1_ACK 57
129#define VFE_CMD_EPOCH2_ACK 58
130#define VFE_CMD_START_RECORDING 59
131#define VFE_CMD_STOP_RECORDING 60
132#define VFE_CMD_DUMMY_5 61
133#define VFE_CMD_DUMMY_6 62
134#define VFE_CMD_CAPTURE 63
135#define VFE_CMD_DUMMY_7 64
136#define VFE_CMD_STOP 65
137#define VFE_CMD_GET_HW_VERSION 66
138#define VFE_CMD_GET_FRAME_SKIP_COUNTS 67
139#define VFE_CMD_OUTPUT1_BUFFER_ENQ 68
140#define VFE_CMD_OUTPUT2_BUFFER_ENQ 69
141#define VFE_CMD_OUTPUT3_BUFFER_ENQ 70
142#define VFE_CMD_JPEG_OUT_BUF_ENQ 71
143#define VFE_CMD_RAW_OUT_BUF_ENQ 72
144#define VFE_CMD_RAW_IN_BUF_ENQ 73
145#define VFE_CMD_STATS_AF_ENQ 74
146#define VFE_CMD_STATS_AE_ENQ 75
147#define VFE_CMD_STATS_AWB_ENQ 76
148#define VFE_CMD_STATS_RS_ENQ 77
149#define VFE_CMD_STATS_CS_ENQ 78
150#define VFE_CMD_STATS_SKIN_ENQ 79
151#define VFE_CMD_STATS_IHIST_ENQ 80
152#define VFE_CMD_DUMMY_8 81
153#define VFE_CMD_JPEG_ENC_CFG 82
154#define VFE_CMD_DUMMY_9 83
155#define VFE_CMD_STATS_AF_START 84
156#define VFE_CMD_STATS_AF_STOP 85
157#define VFE_CMD_STATS_AE_START 86
158#define VFE_CMD_STATS_AE_STOP 87
159#define VFE_CMD_STATS_AWB_START 88
160#define VFE_CMD_STATS_AWB_STOP 89
161#define VFE_CMD_STATS_RS_START 90
162#define VFE_CMD_STATS_RS_STOP 91
163#define VFE_CMD_STATS_CS_START 92
164#define VFE_CMD_STATS_CS_STOP 93
165#define VFE_CMD_STATS_SKIN_START 94
166#define VFE_CMD_STATS_SKIN_STOP 95
167#define VFE_CMD_STATS_IHIST_START 96
168#define VFE_CMD_STATS_IHIST_STOP 97
169#define VFE_CMD_DUMMY_10 98
170#define VFE_CMD_SYNC_TIMER_SETTING 99
171#define VFE_CMD_ASYNC_TIMER_SETTING 100
172#define VFE_CMD_LIVESHOT 101
173#define VFE_CMD_LA_SETUP 102
174#define VFE_CMD_LINEARIZATION_CFG 103
175#define VFE_CMD_DEMOSAICV3 104
176#define VFE_CMD_DEMOSAICV3_ABCC_CFG 105
177#define VFE_CMD_DEMOSAICV3_DBCC_CFG 106
178#define VFE_CMD_DEMOSAICV3_DBPC_CFG 107
179#define VFE_CMD_DEMOSAICV3_ABF_CFG 108
180#define VFE_CMD_DEMOSAICV3_ABCC_UPDATE 109
181#define VFE_CMD_DEMOSAICV3_DBCC_UPDATE 110
182#define VFE_CMD_DEMOSAICV3_DBPC_UPDATE 111
183#define VFE_CMD_XBAR_CFG 112
Ujwal Patel1fe4c9c2011-10-07 12:19:52 -0700184#define VFE_CMD_MODULE_CFG 113
Shuzhen Wangce650862011-08-17 15:27:01 -0700185#define VFE_CMD_ZSL 114
186#define VFE_CMD_LINEARIZATION_UPDATE 115
187#define VFE_CMD_DEMOSAICV3_ABF_UPDATE 116
188#define VFE_CMD_CLF_CFG 117
189#define VFE_CMD_CLF_LUMA_UPDATE 118
190#define VFE_CMD_CLF_CHROMA_UPDATE 119
Ujwal Pateledcbdcc2011-08-24 09:14:14 -0700191#define VFE_CMD_PCA_ROLL_OFF_CFG 120
192#define VFE_CMD_PCA_ROLL_OFF_UPDATE 121
Ujwal Patel6e4308d2011-10-25 11:24:52 -0700193#define VFE_CMD_GET_REG_DUMP 122
194#define VFE_CMD_GET_LINEARIZATON_TABLE 123
195#define VFE_CMD_GET_MESH_ROLLOFF_TABLE 124
196#define VFE_CMD_GET_PCA_ROLLOFF_TABLE 125
197#define VFE_CMD_GET_RGB_G_TABLE 126
198#define VFE_CMD_GET_LA_TABLE 127
Azam Sadiq Pasha Kapatrala Syed5156dd42011-10-27 19:30:13 -0700199#define VFE_CMD_DEMOSAICV3_UPDATE 128
Suresh Vankadara055cb8e2012-01-18 00:50:04 +0530200#define VFE_CMD_ACTIVE_REGION_CFG 129
201#define VFE_CMD_COLOR_PROCESSING_CONFIG 130
202#define VFE_CMD_STATS_WB_AEC_CONFIG 131
203#define VFE_CMD_STATS_WB_AEC_UPDATE 132
204#define VFE_CMD_Y_GAMMA_CONFIG 133
205#define VFE_CMD_SCALE_OUTPUT1_CONFIG 134
206#define VFE_CMD_SCALE_OUTPUT2_CONFIG 135
Kiran Kumar H Ndd128472011-12-01 09:35:34 -0800207#define VFE_CMD_CAPTURE_RAW 136
208#define VFE_CMD_STOP_LIVESHOT 137
Sandeep Kodimelac6f78672012-03-07 10:44:04 +0530209#define VFE_CMD_RECONFIG_VFE 138
Lakshmi Narayana Kalavala2db33842012-06-26 22:41:32 -0700210#define VFE_CMD_STATS_REQBUF 139
211#define VFE_CMD_STATS_ENQUEUEBUF 140
212#define VFE_CMD_STATS_FLUSH_BUFQ 141
Lakshmi Narayana Kalavala58243db2012-07-24 00:06:27 -0700213#define VFE_CMD_STATS_UNREGBUF 142
Lakshmi Narayana Kalavalabc315ea2012-07-24 09:55:48 -0700214#define VFE_CMD_STATS_BG_START 143
215#define VFE_CMD_STATS_BG_STOP 144
216#define VFE_CMD_STATS_BF_START 145
217#define VFE_CMD_STATS_BF_STOP 146
218#define VFE_CMD_STATS_BHIST_START 147
219#define VFE_CMD_STATS_BHIST_STOP 148
Shuzhen Wang5c190ad2012-07-09 16:30:51 -0700220#define VFE_CMD_RESET_2 149
Shuzhen Wangce650862011-08-17 15:27:01 -0700221
Shuzhen Wang6b0f3322011-08-26 12:14:43 -0700222struct msm_isp_cmd {
223 int32_t id;
224 uint16_t length;
225 void *value;
226};
227
Mingcheng Zhu8e9f99e2011-08-26 16:33:32 -0700228#define VPE_CMD_DUMMY_0 0
229#define VPE_CMD_INIT 1
230#define VPE_CMD_DEINIT 2
231#define VPE_CMD_ENABLE 3
232#define VPE_CMD_DISABLE 4
233#define VPE_CMD_RESET 5
234#define VPE_CMD_FLUSH 6
235#define VPE_CMD_OPERATION_MODE_CFG 7
236#define VPE_CMD_INPUT_PLANE_CFG 8
237#define VPE_CMD_OUTPUT_PLANE_CFG 9
238#define VPE_CMD_INPUT_PLANE_UPDATE 10
239#define VPE_CMD_SCALE_CFG_TYPE 11
Mingcheng Zhu8e9f99e2011-08-26 16:33:32 -0700240#define VPE_CMD_ZOOM 13
Kevin Chan318d7cb2011-11-29 14:24:26 -0800241#define VPE_CMD_MAX 14
Mingcheng Zhu8e9f99e2011-08-26 16:33:32 -0700242
243#define MSM_PP_CMD_TYPE_NOT_USED 0 /* not used */
244#define MSM_PP_CMD_TYPE_VPE 1 /* VPE cmd */
245#define MSM_PP_CMD_TYPE_MCTL 2 /* MCTL cmd */
246
247#define MCTL_CMD_DUMMY_0 0 /* not used */
248#define MCTL_CMD_GET_FRAME_BUFFER 1 /* reserve a free frame buffer */
249#define MCTL_CMD_PUT_FRAME_BUFFER 2 /* return the free frame buffer */
250#define MCTL_CMD_DIVERT_FRAME_PP_PATH 3 /* divert frame for pp */
Mingcheng Zhu8e9f99e2011-08-26 16:33:32 -0700251
252/* event typese sending to MCTL PP module */
253#define MCTL_PP_EVENT_NOTUSED 0
254#define MCTL_PP_EVENT_CMD_ACK 1
255
Kiran Kumar H N8f68c592012-01-06 15:11:47 -0800256#define VPE_OPERATION_MODE_CFG_LEN 4
Mingcheng Zhu8e9f99e2011-08-26 16:33:32 -0700257#define VPE_INPUT_PLANE_CFG_LEN 24
Kiran Kumar H N8f68c592012-01-06 15:11:47 -0800258#define VPE_OUTPUT_PLANE_CFG_LEN 20
Mingcheng Zhu8e9f99e2011-08-26 16:33:32 -0700259#define VPE_INPUT_PLANE_UPDATE_LEN 12
260#define VPE_SCALER_CONFIG_LEN 260
261#define VPE_DIS_OFFSET_CFG_LEN 12
262
Jignesh Mehtabde84242012-02-16 13:21:22 -0800263
264#define CAPTURE_WIDTH 1280
265#define IMEM_Y_SIZE (CAPTURE_WIDTH*16)
266#define IMEM_CBCR_SIZE (CAPTURE_WIDTH*8)
267
268#define IMEM_Y_PING_OFFSET 0x2E000000
269#define IMEM_CBCR_PING_OFFSET (IMEM_Y_PING_OFFSET + IMEM_Y_SIZE)
270
271#define IMEM_Y_PONG_OFFSET (IMEM_CBCR_PING_OFFSET + IMEM_CBCR_SIZE)
272#define IMEM_CBCR_PONG_OFFSET (IMEM_Y_PONG_OFFSET + IMEM_Y_SIZE)
273
Jignesh Mehta6cf8a742012-02-04 23:40:50 -0800274
Mingcheng Zhu8e9f99e2011-08-26 16:33:32 -0700275struct msm_vpe_op_mode_cfg {
276 uint8_t op_mode_cfg[VPE_OPERATION_MODE_CFG_LEN];
277};
278
279struct msm_vpe_input_plane_cfg {
280 uint8_t input_plane_cfg[VPE_INPUT_PLANE_CFG_LEN];
281};
282
283struct msm_vpe_output_plane_cfg {
284 uint8_t output_plane_cfg[VPE_OUTPUT_PLANE_CFG_LEN];
285};
286
287struct msm_vpe_input_plane_update_cfg {
288 uint8_t input_plane_update_cfg[VPE_INPUT_PLANE_UPDATE_LEN];
289};
290
291struct msm_vpe_scaler_cfg {
292 uint8_t scaler_cfg[VPE_SCALER_CONFIG_LEN];
293};
294
Mingcheng Zhu8e9f99e2011-08-26 16:33:32 -0700295struct msm_vpe_flush_frame_buffer {
296 uint32_t src_buf_handle;
297 uint32_t dest_buf_handle;
298 int path;
299};
300
301struct msm_mctl_pp_frame_buffer {
302 uint32_t buf_handle;
303 int path;
304};
305struct msm_mctl_pp_divert_pp {
306 int path;
Mingcheng Zhu8feaa3f2011-11-23 11:33:52 -0800307 int enable;
Mingcheng Zhu8e9f99e2011-08-26 16:33:32 -0700308};
309struct msm_vpe_clock_rate {
310 uint32_t rate;
311};
312struct msm_pp_crop {
313 uint32_t src_x;
314 uint32_t src_y;
315 uint32_t src_w;
316 uint32_t src_h;
317 uint32_t dst_x;
318 uint32_t dst_y;
319 uint32_t dst_w;
320 uint32_t dst_h;
321 uint8_t update_flag;
322};
323#define MSM_MCTL_PP_VPE_FRAME_ACK (1<<0)
324#define MSM_MCTL_PP_VPE_FRAME_TO_APP (1<<1)
325
326struct msm_mctl_pp_frame_cmd {
327 uint32_t cookie;
328 uint8_t vpe_output_action;
329 uint32_t src_buf_handle;
330 uint32_t dest_buf_handle;
331 struct msm_pp_crop crop;
332 int path;
333 /* TBD: 3D related */
334};
335
Nishant Pandit5dd54422012-06-26 22:52:44 +0530336#define VFE_OUTPUTS_MAIN_AND_PREVIEW BIT(0)
337#define VFE_OUTPUTS_MAIN_AND_VIDEO BIT(1)
338#define VFE_OUTPUTS_MAIN_AND_THUMB BIT(2)
339#define VFE_OUTPUTS_THUMB_AND_MAIN BIT(3)
340#define VFE_OUTPUTS_PREVIEW_AND_VIDEO BIT(4)
341#define VFE_OUTPUTS_VIDEO_AND_PREVIEW BIT(5)
342#define VFE_OUTPUTS_PREVIEW BIT(6)
343#define VFE_OUTPUTS_VIDEO BIT(7)
344#define VFE_OUTPUTS_RAW BIT(8)
345#define VFE_OUTPUTS_JPEG_AND_THUMB BIT(9)
346#define VFE_OUTPUTS_THUMB_AND_JPEG BIT(10)
347#define VFE_OUTPUTS_RDI0 BIT(11)
348#define VFE_OUTPUTS_RDI1 BIT(12)
Kiran Kumar H Ndd128472011-12-01 09:35:34 -0800349
Kevin Chan2df27e62012-06-15 00:06:54 -0700350struct msm_frame_info {
Kiran Kumar H N90785902012-07-05 13:59:38 -0700351 uint32_t inst_handle;
Kevin Chan2df27e62012-06-15 00:06:54 -0700352 uint32_t path;
353};
354
Mingcheng Zhu8e9f99e2011-08-26 16:33:32 -0700355#endif /*__MSM_ISP_H__*/
356