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review.evervolv.com / android_kernel_htc_msm8960 / 5e4d9871b42b57100761ac20dc3fad14a2ae5e37 / . / drivers / mtd / devices / msm_nand.c
blob: 29b44dfbec16e7dd84a4bc07813f43ade09dc58f [file] [log] [blame]
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]1/*
2 * Copyright (C) 2007 Google, Inc.
3 * Copyright (c) 2008-2011, Code Aurora Forum. All rights reserved.
4 *
5 * This software is licensed under the terms of the GNU General Public
6 * License version 2, as published by the Free Software Foundation, and
7 * may be copied, distributed, and modified under those terms.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 */
15
16#include <linux/slab.h>
17#include <linux/kernel.h>
18#include <linux/module.h>
19#include <linux/mtd/mtd.h>
20#include <linux/mtd/nand.h>
21#include <linux/mtd/partitions.h>
22#include <linux/platform_device.h>
23#include <linux/sched.h>
24#include <linux/dma-mapping.h>
25#include <linux/io.h>
26#include <linux/crc16.h>
27#include <linux/bitrev.h>
28
29#include <asm/dma.h>
30#include <asm/mach/flash.h>
31
32#include <mach/dma.h>
33
34#include "msm_nand.h"
35
36unsigned long msm_nand_phys;
37unsigned long msm_nandc01_phys;
38unsigned long msm_nandc10_phys;
39unsigned long msm_nandc11_phys;
40unsigned long ebi2_register_base;
41uint32_t dual_nand_ctlr_present;
42uint32_t interleave_enable;
43uint32_t enable_bch_ecc;
44unsigned crci_mask;
45
46#define MSM_NAND_DMA_BUFFER_SIZE SZ_8K
47#define MSM_NAND_DMA_BUFFER_SLOTS \
48 (MSM_NAND_DMA_BUFFER_SIZE / (sizeof(((atomic_t *)0)->counter) * 8))
49
50#define MSM_NAND_CFG0_RAW_ONFI_IDENTIFIER 0x88000800
51#define MSM_NAND_CFG0_RAW_ONFI_PARAM_INFO 0x88040000
52#define MSM_NAND_CFG1_RAW_ONFI_IDENTIFIER 0x0005045d
53#define MSM_NAND_CFG1_RAW_ONFI_PARAM_INFO 0x0005045d
54
55#define ONFI_IDENTIFIER_LENGTH 0x0004
56#define ONFI_PARAM_INFO_LENGTH 0x0200
57#define ONFI_PARAM_PAGE_LENGTH 0x0100
58
59#define ONFI_PARAMETER_PAGE_SIGNATURE 0x49464E4F
60
61#define FLASH_READ_ONFI_IDENTIFIER_COMMAND 0x90
62#define FLASH_READ_ONFI_IDENTIFIER_ADDRESS 0x20
63#define FLASH_READ_ONFI_PARAMETERS_COMMAND 0xEC
64#define FLASH_READ_ONFI_PARAMETERS_ADDRESS 0x00
65
66#define VERBOSE 0
67
68struct msm_nand_chip {
69 struct device *dev;
70 wait_queue_head_t wait_queue;
71 atomic_t dma_buffer_busy;
72 unsigned dma_channel;
73 uint8_t *dma_buffer;
74 dma_addr_t dma_addr;
75 unsigned CFG0, CFG1, CFG0_RAW, CFG1_RAW;
76 uint32_t ecc_buf_cfg;
77 uint32_t ecc_bch_cfg;
78 uint32_t ecc_parity_bytes;
79 unsigned cw_size;
80};
81
82#define CFG1_WIDE_FLASH (1U << 1)
83
84/* TODO: move datamover code out */
85
86#define SRC_CRCI_NAND_CMD CMD_SRC_CRCI(DMOV_NAND_CRCI_CMD)
87#define DST_CRCI_NAND_CMD CMD_DST_CRCI(DMOV_NAND_CRCI_CMD)
88#define SRC_CRCI_NAND_DATA CMD_SRC_CRCI(DMOV_NAND_CRCI_DATA)
89#define DST_CRCI_NAND_DATA CMD_DST_CRCI(DMOV_NAND_CRCI_DATA)
90
91#define msm_virt_to_dma(chip, vaddr) \
92 ((chip)->dma_addr + \
93 ((uint8_t *)(vaddr) - (chip)->dma_buffer))
94
95/**
96 * msm_nand_oob_64 - oob info for 2KB page
97 */
98static struct nand_ecclayout msm_nand_oob_64 = {
99 .eccbytes = 40,
100 .eccpos = {
101 0, 1, 2, 3, 4, 5, 6, 7, 8, 9,
102 10, 11, 12, 13, 14, 15, 16, 17, 18, 19,
103 20, 21, 22, 23, 24, 25, 26, 27, 28, 29,
104 46, 47, 48, 49, 50, 51, 52, 53, 54, 55,
105 },
106 .oobavail = 16,
107 .oobfree = {
108 {30, 16},
109 }
110};
111
112/**
113 * msm_nand_oob_128 - oob info for 4KB page
114 */
115static struct nand_ecclayout msm_nand_oob_128 = {
116 .eccbytes = 80,
117 .eccpos = {
118 0, 1, 2, 3, 4, 5, 6, 7, 8, 9,
119 10, 11, 12, 13, 14, 15, 16, 17, 18, 19,
120 20, 21, 22, 23, 24, 25, 26, 27, 28, 29,
121 30, 31, 32, 33, 34, 35, 36, 37, 38, 39,
122 40, 41, 42, 43, 44, 45, 46, 47, 48, 49,
123 50, 51, 52, 53, 54, 55, 56, 57, 58, 59,
124 60, 61, 62, 63, 64, 65, 66, 67, 68, 69,
125 102, 103, 104, 105, 106, 107, 108, 109, 110, 111,
126 },
127 .oobavail = 32,
128 .oobfree = {
129 {70, 32},
130 }
131};
132
133/**
134 * msm_nand_oob_224 - oob info for 4KB page 8Bit interface
135 */
136static struct nand_ecclayout msm_nand_oob_224_x8 = {
137 .eccbytes = 104,
138 .eccpos = {
139 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12,
140 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25,
141 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38,
142 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51,
143 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64,
144 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77,
145 78, 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90,
146 123, 124, 125, 126, 127, 128, 129, 130, 131, 132, 133, 134, 135,
147 },
148 .oobavail = 32,
149 .oobfree = {
150 {91, 32},
151 }
152};
153
154/**
155 * msm_nand_oob_224 - oob info for 4KB page 16Bit interface
156 */
157static struct nand_ecclayout msm_nand_oob_224_x16 = {
158 .eccbytes = 112,
159 .eccpos = {
160 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13,
161 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27,
162 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41,
163 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55,
164 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69,
165 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 82, 83,
166 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, 97,
167 130, 131, 132, 133, 134, 135, 136, 137, 138, 139, 140, 141, 142, 143,
168 },
169 .oobavail = 32,
170 .oobfree = {
171 {98, 32},
172 }
173};
174
175/**
176 * msm_nand_oob_256 - oob info for 8KB page
177 */
178static struct nand_ecclayout msm_nand_oob_256 = {
179 .eccbytes = 160,
180 .eccpos = {
181 0, 1, 2, 3, 4, 5, 6, 7, 8, 9,
182 10, 11, 12, 13, 14, 15, 16, 17, 18, 19,
183 20, 21, 22, 23, 24, 25, 26, 27, 28, 29,
184 30, 31, 32, 33, 34, 35, 36, 37, 38, 39,
185 40, 41, 42, 43, 44, 45, 46, 47, 48, 49,
186 50, 51, 52, 53, 54, 55, 56, 57, 58, 59,
187 60, 61, 62, 63, 64, 65, 66, 67, 68, 69,
188 70, 71, 72, 73, 74, 75, 76, 77, 78, 79,
189 80, 81, 82, 83, 84, 85, 86, 87, 88, 89,
190 90, 91, 92, 93, 94, 96, 97, 98 , 99, 100,
191 101, 102, 103, 104, 105, 106, 107, 108, 109, 110,
192 111, 112, 113, 114, 115, 116, 117, 118, 119, 120,
193 121, 122, 123, 124, 125, 126, 127, 128, 129, 130,
194 131, 132, 133, 134, 135, 136, 137, 138, 139, 140,
195 141, 142, 143, 144, 145, 146, 147, 148, 149, 150,
196 215, 216, 217, 218, 219, 220, 221, 222, 223, 224,
197 },
198 .oobavail = 64,
199 .oobfree = {
200 {151, 64},
201 }
202};
203
204/**
205 * msm_onenand_oob_64 - oob info for large (2KB) page
206 */
207static struct nand_ecclayout msm_onenand_oob_64 = {
208 .eccbytes = 20,
209 .eccpos = {
210 8, 9, 10, 11, 12,
211 24, 25, 26, 27, 28,
212 40, 41, 42, 43, 44,
213 56, 57, 58, 59, 60,
214 },
215 .oobavail = 20,
216 .oobfree = {
217 {2, 3}, {14, 2}, {18, 3}, {30, 2},
218 {34, 3}, {46, 2}, {50, 3}, {62, 2}
219 }
220};
221
222static void *msm_nand_get_dma_buffer(struct msm_nand_chip *chip, size_t size)
223{
224 unsigned int bitmask, free_bitmask, old_bitmask;
225 unsigned int need_mask, current_need_mask;
226 int free_index;
227
228 need_mask = (1UL << DIV_ROUND_UP(size, MSM_NAND_DMA_BUFFER_SLOTS)) - 1;
229 bitmask = atomic_read(&chip->dma_buffer_busy);
230 free_bitmask = ~bitmask;
231 do {
232 free_index = __ffs(free_bitmask);
233 current_need_mask = need_mask << free_index;
234
235 if (size + free_index * MSM_NAND_DMA_BUFFER_SLOTS >=
236 MSM_NAND_DMA_BUFFER_SIZE)
237 return NULL;
238
239 if ((bitmask & current_need_mask) == 0) {
240 old_bitmask =
241 atomic_cmpxchg(&chip->dma_buffer_busy,
242 bitmask,
243 bitmask | current_need_mask);
244 if (old_bitmask == bitmask)
245 return chip->dma_buffer +
246 free_index * MSM_NAND_DMA_BUFFER_SLOTS;
247 free_bitmask = 0; /* force return */
248 }
249 /* current free range was too small, clear all free bits */
250 /* below the top busy bit within current_need_mask */
251 free_bitmask &=
252 ~(~0U >> (32 - fls(bitmask & current_need_mask)));
253 } while (free_bitmask);
254
255 return NULL;
256}
257
258static void msm_nand_release_dma_buffer(struct msm_nand_chip *chip,
259 void *buffer, size_t size)
260{
261 int index;
262 unsigned int used_mask;
263
264 used_mask = (1UL << DIV_ROUND_UP(size, MSM_NAND_DMA_BUFFER_SLOTS)) - 1;
265 index = ((uint8_t *)buffer - chip->dma_buffer) /
266 MSM_NAND_DMA_BUFFER_SLOTS;
267 atomic_sub(used_mask << index, &chip->dma_buffer_busy);
268
269 wake_up(&chip->wait_queue);
270}
271
272
273unsigned flash_rd_reg(struct msm_nand_chip *chip, unsigned addr)
274{
275 struct {
276 dmov_s cmd;
277 unsigned cmdptr;
278 unsigned data;
279 } *dma_buffer;
280 unsigned rv;
281
282 wait_event(chip->wait_queue,
283 (dma_buffer = msm_nand_get_dma_buffer(
284 chip, sizeof(*dma_buffer))));
285
286 dma_buffer->cmd.cmd = CMD_LC | CMD_OCB | CMD_OCU;
287 dma_buffer->cmd.src = addr;
288 dma_buffer->cmd.dst = msm_virt_to_dma(chip, &dma_buffer->data);
289 dma_buffer->cmd.len = 4;
290
291 dma_buffer->cmdptr =
292 (msm_virt_to_dma(chip, &dma_buffer->cmd) >> 3) | CMD_PTR_LP;
293 dma_buffer->data = 0xeeeeeeee;
294
295 mb();
296 msm_dmov_exec_cmd(
297 chip->dma_channel, crci_mask, DMOV_CMD_PTR_LIST |
298 DMOV_CMD_ADDR(msm_virt_to_dma(chip, &dma_buffer->cmdptr)));
299 mb();
300
301 rv = dma_buffer->data;
302
303 msm_nand_release_dma_buffer(chip, dma_buffer, sizeof(*dma_buffer));
304
305 return rv;
306}
307
308void flash_wr_reg(struct msm_nand_chip *chip, unsigned addr, unsigned val)
309{
310 struct {
311 dmov_s cmd;
312 unsigned cmdptr;
313 unsigned data;
314 } *dma_buffer;
315
316 wait_event(chip->wait_queue,
317 (dma_buffer = msm_nand_get_dma_buffer(
318 chip, sizeof(*dma_buffer))));
319
320 dma_buffer->cmd.cmd = CMD_LC | CMD_OCB | CMD_OCU;
321 dma_buffer->cmd.src = msm_virt_to_dma(chip, &dma_buffer->data);
322 dma_buffer->cmd.dst = addr;
323 dma_buffer->cmd.len = 4;
324
325 dma_buffer->cmdptr =
326 (msm_virt_to_dma(chip, &dma_buffer->cmd) >> 3) | CMD_PTR_LP;
327 dma_buffer->data = val;
328
329 mb();
330 msm_dmov_exec_cmd(
331 chip->dma_channel, crci_mask, DMOV_CMD_PTR_LIST |
332 DMOV_CMD_ADDR(msm_virt_to_dma(chip, &dma_buffer->cmdptr)));
333 mb();
334
335 msm_nand_release_dma_buffer(chip, dma_buffer, sizeof(*dma_buffer));
336}
337
338static dma_addr_t
339msm_nand_dma_map(struct device *dev, void *addr, size_t size,
340 enum dma_data_direction dir)
341{
342 struct page *page;
343 unsigned long offset = (unsigned long)addr & ~PAGE_MASK;
344 if (virt_addr_valid(addr))
345 page = virt_to_page(addr);
346 else {
347 if (WARN_ON(size + offset > PAGE_SIZE))
348 return ~0;
349 page = vmalloc_to_page(addr);
350 }
351 return dma_map_page(dev, page, offset, size, dir);
352}
353
354uint32_t flash_read_id(struct msm_nand_chip *chip)
355{
356 struct {
357 dmov_s cmd[7];
358 unsigned cmdptr;
359 unsigned data[7];
360 } *dma_buffer;
361 uint32_t rv;
362
363 wait_event(chip->wait_queue, (dma_buffer = msm_nand_get_dma_buffer
364 (chip, sizeof(*dma_buffer))));
365
366 dma_buffer->data[0] = 0 | 4;
367 dma_buffer->data[1] = MSM_NAND_CMD_FETCH_ID;
368 dma_buffer->data[2] = 1;
369 dma_buffer->data[3] = 0xeeeeeeee;
370 dma_buffer->data[4] = 0xeeeeeeee;
371 dma_buffer->data[5] = flash_rd_reg(chip, MSM_NAND_SFLASHC_BURST_CFG);
372 dma_buffer->data[6] = 0x00000000;
373 BUILD_BUG_ON(6 != ARRAY_SIZE(dma_buffer->data) - 1);
374
375 dma_buffer->cmd[0].cmd = 0 | CMD_OCB;
376 dma_buffer->cmd[0].src = msm_virt_to_dma(chip, &dma_buffer->data[6]);
377 dma_buffer->cmd[0].dst = MSM_NAND_SFLASHC_BURST_CFG;
378 dma_buffer->cmd[0].len = 4;
379
380 dma_buffer->cmd[1].cmd = 0;
381 dma_buffer->cmd[1].src = msm_virt_to_dma(chip, &dma_buffer->data[0]);
382 dma_buffer->cmd[1].dst = MSM_NAND_FLASH_CHIP_SELECT;
383 dma_buffer->cmd[1].len = 4;
384
385 dma_buffer->cmd[2].cmd = DST_CRCI_NAND_CMD;
386 dma_buffer->cmd[2].src = msm_virt_to_dma(chip, &dma_buffer->data[1]);
387 dma_buffer->cmd[2].dst = MSM_NAND_FLASH_CMD;
388 dma_buffer->cmd[2].len = 4;
389
390 dma_buffer->cmd[3].cmd = 0;
391 dma_buffer->cmd[3].src = msm_virt_to_dma(chip, &dma_buffer->data[2]);
392 dma_buffer->cmd[3].dst = MSM_NAND_EXEC_CMD;
393 dma_buffer->cmd[3].len = 4;
394
395 dma_buffer->cmd[4].cmd = SRC_CRCI_NAND_DATA;
396 dma_buffer->cmd[4].src = MSM_NAND_FLASH_STATUS;
397 dma_buffer->cmd[4].dst = msm_virt_to_dma(chip, &dma_buffer->data[3]);
398 dma_buffer->cmd[4].len = 4;
399
400 dma_buffer->cmd[5].cmd = 0;
401 dma_buffer->cmd[5].src = MSM_NAND_READ_ID;
402 dma_buffer->cmd[5].dst = msm_virt_to_dma(chip, &dma_buffer->data[4]);
403 dma_buffer->cmd[5].len = 4;
404
405 dma_buffer->cmd[6].cmd = CMD_OCU | CMD_LC;
406 dma_buffer->cmd[6].src = msm_virt_to_dma(chip, &dma_buffer->data[5]);
407 dma_buffer->cmd[6].dst = MSM_NAND_SFLASHC_BURST_CFG;
408 dma_buffer->cmd[6].len = 4;
409
410 BUILD_BUG_ON(6 != ARRAY_SIZE(dma_buffer->cmd) - 1);
411
412 dma_buffer->cmdptr = (msm_virt_to_dma(chip, dma_buffer->cmd) >> 3
413 ) | CMD_PTR_LP;
414
415 mb();
416 msm_dmov_exec_cmd(chip->dma_channel, crci_mask, DMOV_CMD_PTR_LIST |
417 DMOV_CMD_ADDR(msm_virt_to_dma(chip, &dma_buffer->cmdptr)));
418 mb();
419
420 pr_info("status: %x\n", dma_buffer->data[3]);
421 pr_info("nandid: %x maker %02x device %02x\n",
422 dma_buffer->data[4], dma_buffer->data[4] & 0xff,
423 (dma_buffer->data[4] >> 8) & 0xff);
424 rv = dma_buffer->data[4];
425 msm_nand_release_dma_buffer(chip, dma_buffer, sizeof(*dma_buffer));
426 return rv;
427}
428
429struct flash_identification {
430 uint32_t flash_id;
431 uint32_t density;
432 uint32_t widebus;
433 uint32_t pagesize;
434 uint32_t blksize;
435 uint32_t oobsize;
436 uint32_t ecc_correctability;
437} supported_flash;
438
439uint16_t flash_onfi_crc_check(uint8_t *buffer, uint16_t count)
440{
441 int i;
442 uint16_t result;
443
444 for (i = 0; i < count; i++)
445 buffer[i] = bitrev8(buffer[i]);
446
447 result = bitrev16(crc16(bitrev16(0x4f4e), buffer, count));
448
449 for (i = 0; i < count; i++)
450 buffer[i] = bitrev8(buffer[i]);
451
452 return result;
453}
454
455
456uint32_t flash_onfi_probe(struct msm_nand_chip *chip)
457{
458 struct onfi_param_page {
459 uint32_t parameter_page_signature;
460 uint16_t revision_number;
461 uint16_t features_supported;
462 uint16_t optional_commands_supported;
463 uint8_t reserved0[22];
464 uint8_t device_manufacturer[12];
465 uint8_t device_model[20];
466 uint8_t jedec_manufacturer_id;
467 uint16_t date_code;
468 uint8_t reserved1[13];
469 uint32_t number_of_data_bytes_per_page;
470 uint16_t number_of_spare_bytes_per_page;
471 uint32_t number_of_data_bytes_per_partial_page;
472 uint16_t number_of_spare_bytes_per_partial_page;
473 uint32_t number_of_pages_per_block;
474 uint32_t number_of_blocks_per_logical_unit;
475 uint8_t number_of_logical_units;
476 uint8_t number_of_address_cycles;
477 uint8_t number_of_bits_per_cell;
478 uint16_t maximum_bad_blocks_per_logical_unit;
479 uint16_t block_endurance;
480 uint8_t guaranteed_valid_begin_blocks;
481 uint16_t guaranteed_valid_begin_blocks_endurance;
482 uint8_t number_of_programs_per_page;
483 uint8_t partial_program_attributes;
484 uint8_t number_of_bits_ecc_correctability;
485 uint8_t number_of_interleaved_address_bits;
486 uint8_t interleaved_operation_attributes;
487 uint8_t reserved2[13];
488 uint8_t io_pin_capacitance;
489 uint16_t timing_mode_support;
490 uint16_t program_cache_timing_mode_support;
491 uint16_t maximum_page_programming_time;
492 uint16_t maximum_block_erase_time;
493 uint16_t maximum_page_read_time;
494 uint16_t maximum_change_column_setup_time;
495 uint8_t reserved3[23];
496 uint16_t vendor_specific_revision_number;
497 uint8_t vendor_specific[88];
498 uint16_t integrity_crc;
499
500 } __attribute__((__packed__));
501
502 struct onfi_param_page *onfi_param_page_ptr;
503 uint8_t *onfi_identifier_buf = NULL;
504 uint8_t *onfi_param_info_buf = NULL;
505
506 struct {
507 dmov_s cmd[11];
508 unsigned cmdptr;
509 struct {
510 uint32_t cmd;
511 uint32_t addr0;
512 uint32_t addr1;
513 uint32_t cfg0;
514 uint32_t cfg1;
515 uint32_t exec;
516 uint32_t flash_status;
517 uint32_t devcmd1_orig;
518 uint32_t devcmdvld_orig;
519 uint32_t devcmd1_mod;
520 uint32_t devcmdvld_mod;
521 uint32_t sflash_bcfg_orig;
522 uint32_t sflash_bcfg_mod;
523 } data;
524 } *dma_buffer;
525 dmov_s *cmd;
526
527 unsigned page_address = 0;
528 int err = 0;
529 dma_addr_t dma_addr_param_info = 0;
530 dma_addr_t dma_addr_identifier = 0;
531 unsigned cmd_set_count = 2;
532 unsigned crc_chk_count = 0;
533
534 if (msm_nand_data.nr_parts) {
535 page_address = ((msm_nand_data.parts[0]).offset << 6);
536 } else {
537 pr_err("flash_onfi_probe: "
538 "No partition info available\n");
539 err = -EIO;
540 return err;
541 }
542
543 wait_event(chip->wait_queue, (onfi_identifier_buf =
544 msm_nand_get_dma_buffer(chip, ONFI_IDENTIFIER_LENGTH)));
545 dma_addr_identifier = msm_virt_to_dma(chip, onfi_identifier_buf);
546
547 wait_event(chip->wait_queue, (onfi_param_info_buf =
548 msm_nand_get_dma_buffer(chip, ONFI_PARAM_INFO_LENGTH)));
549 dma_addr_param_info = msm_virt_to_dma(chip, onfi_param_info_buf);
550
551 wait_event(chip->wait_queue, (dma_buffer = msm_nand_get_dma_buffer
552 (chip, sizeof(*dma_buffer))));
553
554 dma_buffer->data.sflash_bcfg_orig = flash_rd_reg
555 (chip, MSM_NAND_SFLASHC_BURST_CFG);
556 dma_buffer->data.devcmd1_orig = flash_rd_reg(chip, MSM_NAND_DEV_CMD1);
557 dma_buffer->data.devcmdvld_orig = flash_rd_reg(chip,
558 MSM_NAND_DEV_CMD_VLD);
559
560 while (cmd_set_count-- > 0) {
561 cmd = dma_buffer->cmd;
562
563 dma_buffer->data.devcmd1_mod = (dma_buffer->data.devcmd1_orig &
564 0xFFFFFF00) | (cmd_set_count
565 ? FLASH_READ_ONFI_IDENTIFIER_COMMAND
566 : FLASH_READ_ONFI_PARAMETERS_COMMAND);
567 dma_buffer->data.cmd = MSM_NAND_CMD_PAGE_READ;
568 dma_buffer->data.addr0 = (page_address << 16) | (cmd_set_count
569 ? FLASH_READ_ONFI_IDENTIFIER_ADDRESS
570 : FLASH_READ_ONFI_PARAMETERS_ADDRESS);
571 dma_buffer->data.addr1 = (page_address >> 16) & 0xFF;
572 dma_buffer->data.cfg0 = (cmd_set_count
573 ? MSM_NAND_CFG0_RAW_ONFI_IDENTIFIER
574 : MSM_NAND_CFG0_RAW_ONFI_PARAM_INFO);
575 dma_buffer->data.cfg1 = (cmd_set_count
576 ? MSM_NAND_CFG1_RAW_ONFI_IDENTIFIER
577 : MSM_NAND_CFG1_RAW_ONFI_PARAM_INFO);
578 dma_buffer->data.sflash_bcfg_mod = 0x00000000;
579 dma_buffer->data.devcmdvld_mod = (dma_buffer->
580 data.devcmdvld_orig & 0xFFFFFFFE);
581 dma_buffer->data.exec = 1;
582 dma_buffer->data.flash_status = 0xeeeeeeee;
583
584 /* Put the Nand ctlr in Async mode and disable SFlash ctlr */
585 cmd->cmd = 0;
586 cmd->src = msm_virt_to_dma(chip,
587 &dma_buffer->data.sflash_bcfg_mod);
588 cmd->dst = MSM_NAND_SFLASHC_BURST_CFG;
589 cmd->len = 4;
590 cmd++;
591
592 /* Block on cmd ready, & write CMD,ADDR0,ADDR1,CHIPSEL regs */
593 cmd->cmd = DST_CRCI_NAND_CMD;
594 cmd->src = msm_virt_to_dma(chip, &dma_buffer->data.cmd);
595 cmd->dst = MSM_NAND_FLASH_CMD;
596 cmd->len = 12;
597 cmd++;
598
599 /* Configure the CFG0 and CFG1 registers */
600 cmd->cmd = 0;
601 cmd->src = msm_virt_to_dma(chip,
602 &dma_buffer->data.cfg0);
603 cmd->dst = MSM_NAND_DEV0_CFG0;
604 cmd->len = 8;
605 cmd++;
606
607 /* Configure the DEV_CMD_VLD register */
608 cmd->cmd = 0;
609 cmd->src = msm_virt_to_dma(chip,
610 &dma_buffer->data.devcmdvld_mod);
611 cmd->dst = MSM_NAND_DEV_CMD_VLD;
612 cmd->len = 4;
613 cmd++;
614
615 /* Configure the DEV_CMD1 register */
616 cmd->cmd = 0;
617 cmd->src = msm_virt_to_dma(chip,
618 &dma_buffer->data.devcmd1_mod);
619 cmd->dst = MSM_NAND_DEV_CMD1;
620 cmd->len = 4;
621 cmd++;
622
623 /* Kick the execute command */
624 cmd->cmd = 0;
625 cmd->src = msm_virt_to_dma(chip,
626 &dma_buffer->data.exec);
627 cmd->dst = MSM_NAND_EXEC_CMD;
628 cmd->len = 4;
629 cmd++;
630
631 /* Block on data ready, and read the two status registers */
632 cmd->cmd = SRC_CRCI_NAND_DATA;
633 cmd->src = MSM_NAND_FLASH_STATUS;
634 cmd->dst = msm_virt_to_dma(chip,
635 &dma_buffer->data.flash_status);
636 cmd->len = 4;
637 cmd++;
638
639 /* Read data block - valid only if status says success */
640 cmd->cmd = 0;
641 cmd->src = MSM_NAND_FLASH_BUFFER;
642 cmd->dst = (cmd_set_count ? dma_addr_identifier :
643 dma_addr_param_info);
644 cmd->len = (cmd_set_count ? ONFI_IDENTIFIER_LENGTH :
645 ONFI_PARAM_INFO_LENGTH);
646 cmd++;
647
648 /* Restore the DEV_CMD1 register */
649 cmd->cmd = 0 ;
650 cmd->src = msm_virt_to_dma(chip,
651 &dma_buffer->data.devcmd1_orig);
652 cmd->dst = MSM_NAND_DEV_CMD1;
653 cmd->len = 4;
654 cmd++;
655
656 /* Restore the DEV_CMD_VLD register */
657 cmd->cmd = 0;
658 cmd->src = msm_virt_to_dma(chip,
659 &dma_buffer->data.devcmdvld_orig);
660 cmd->dst = MSM_NAND_DEV_CMD_VLD;
661 cmd->len = 4;
662 cmd++;
663
664 /* Restore the SFLASH_BURST_CONFIG register */
665 cmd->cmd = 0;
666 cmd->src = msm_virt_to_dma(chip,
667 &dma_buffer->data.sflash_bcfg_orig);
668 cmd->dst = MSM_NAND_SFLASHC_BURST_CFG;
669 cmd->len = 4;
670 cmd++;
671
672 BUILD_BUG_ON(11 != ARRAY_SIZE(dma_buffer->cmd));
673 BUG_ON(cmd - dma_buffer->cmd > ARRAY_SIZE(dma_buffer->cmd));
674 dma_buffer->cmd[0].cmd |= CMD_OCB;
675 cmd[-1].cmd |= CMD_OCU | CMD_LC;
676
677 dma_buffer->cmdptr = (msm_virt_to_dma(chip, dma_buffer->cmd)
678 >> 3) | CMD_PTR_LP;
679
680 mb();
681 msm_dmov_exec_cmd(chip->dma_channel, crci_mask,
682 DMOV_CMD_PTR_LIST | DMOV_CMD_ADDR(msm_virt_to_dma(chip,
683 &dma_buffer->cmdptr)));
684 mb();
685
686 /* Check for errors, protection violations etc */
687 if (dma_buffer->data.flash_status & 0x110) {
688 pr_info("MPU/OP error (0x%x) during "
689 "ONFI probe\n",
690 dma_buffer->data.flash_status);
691 err = -EIO;
692 break;
693 }
694
695 if (cmd_set_count) {
696 onfi_param_page_ptr = (struct onfi_param_page *)
697 (&(onfi_identifier_buf[0]));
698 if (onfi_param_page_ptr->parameter_page_signature !=
699 ONFI_PARAMETER_PAGE_SIGNATURE) {
700 pr_info("ONFI probe : Found a non"
701 "ONFI Compliant device \n");
702 err = -EIO;
703 break;
704 }
705 } else {
706 for (crc_chk_count = 0; crc_chk_count <
707 ONFI_PARAM_INFO_LENGTH
708 / ONFI_PARAM_PAGE_LENGTH;
709 crc_chk_count++) {
710 onfi_param_page_ptr =
711 (struct onfi_param_page *)
712 (&(onfi_param_info_buf
713 [ONFI_PARAM_PAGE_LENGTH *
714 crc_chk_count]));
715 if (flash_onfi_crc_check(
716 (uint8_t *)onfi_param_page_ptr,
717 ONFI_PARAM_PAGE_LENGTH - 2) ==
718 onfi_param_page_ptr->integrity_crc) {
719 break;
720 }
721 }
722 if (crc_chk_count >= ONFI_PARAM_INFO_LENGTH
723 / ONFI_PARAM_PAGE_LENGTH) {
724 pr_info("ONFI probe : CRC Check "
725 "failed on ONFI Parameter "
726 "data \n");
727 err = -EIO;
728 break;
729 } else {
730 supported_flash.flash_id =
731 flash_read_id(chip);
732 supported_flash.widebus =
733 onfi_param_page_ptr->
734 features_supported & 0x01;
735 supported_flash.pagesize =
736 onfi_param_page_ptr->
737 number_of_data_bytes_per_page;
738 supported_flash.blksize =
739 onfi_param_page_ptr->
740 number_of_pages_per_block *
741 supported_flash.pagesize;
742 supported_flash.oobsize =
743 onfi_param_page_ptr->
744 number_of_spare_bytes_per_page;
745 supported_flash.density =
746 onfi_param_page_ptr->
747 number_of_blocks_per_logical_unit
748 * supported_flash.blksize;
749 supported_flash.ecc_correctability =
750 onfi_param_page_ptr->
751 number_of_bits_ecc_correctability;
752
753 pr_info("ONFI probe : Found an ONFI "
754 "compliant device %s\n",
755 onfi_param_page_ptr->device_model);
756
757 /* Temporary hack for MT29F4G08ABC device.
758 * Since the device is not properly adhering
759 * to ONFi specification it is reporting
760 * as 16 bit device though it is 8 bit device!!!
761 */
762 if (!strncmp(onfi_param_page_ptr->device_model,
763 "MT29F4G08ABC", 12))
764 supported_flash.widebus = 0;
765 }
766 }
767 }
768
769 msm_nand_release_dma_buffer(chip, dma_buffer, sizeof(*dma_buffer));
770 msm_nand_release_dma_buffer(chip, onfi_param_info_buf,
771 ONFI_PARAM_INFO_LENGTH);
772 msm_nand_release_dma_buffer(chip, onfi_identifier_buf,
773 ONFI_IDENTIFIER_LENGTH);
774
775 return err;
776}
777
778static int msm_nand_read_oob(struct mtd_info *mtd, loff_t from,
779 struct mtd_oob_ops *ops)
780{
781 struct msm_nand_chip *chip = mtd->priv;
782
783 struct {
784 dmov_s cmd[8 * 5 + 2];
785 unsigned cmdptr;
786 struct {
787 uint32_t cmd;
788 uint32_t addr0;
789 uint32_t addr1;
790 uint32_t chipsel;
791 uint32_t cfg0;
792 uint32_t cfg1;
793 uint32_t eccbchcfg;
794 uint32_t exec;
795 uint32_t ecccfg;
796 struct {
797 uint32_t flash_status;
798 uint32_t buffer_status;
799 } result[8];
800 } data;
801 } *dma_buffer;
802 dmov_s *cmd;
803 unsigned n;
804 unsigned page = 0;
805 uint32_t oob_len;
806 uint32_t sectordatasize;
807 uint32_t sectoroobsize;
808 int err, pageerr, rawerr;
809 dma_addr_t data_dma_addr = 0;
810 dma_addr_t oob_dma_addr = 0;
811 dma_addr_t data_dma_addr_curr = 0;
812 dma_addr_t oob_dma_addr_curr = 0;
813 uint32_t oob_col = 0;
814 unsigned page_count;
815 unsigned pages_read = 0;
816 unsigned start_sector = 0;
817 uint32_t ecc_errors;
818 uint32_t total_ecc_errors = 0;
819 unsigned cwperpage;
820#if VERBOSE
821 pr_info("================================================="
822 "================\n");
823 pr_info("%s:\nfrom 0x%llx mode %d\ndatbuf 0x%p datlen 0x%x"
824 "\noobbuf 0x%p ooblen 0x%x\n",
825 __func__, from, ops->mode, ops->datbuf, ops->len,
826 ops->oobbuf, ops->ooblen);
827#endif
828
829 if (mtd->writesize == 2048)
830 page = from >> 11;
831
832 if (mtd->writesize == 4096)
833 page = from >> 12;
834
835 oob_len = ops->ooblen;
836 cwperpage = (mtd->writesize >> 9);
837
838 if (from & (mtd->writesize - 1)) {
839 pr_err("%s: unsupported from, 0x%llx\n",
840 __func__, from);
841 return -EINVAL;
842 }
843 if (ops->mode != MTD_OOB_RAW) {
844 if (ops->datbuf != NULL && (ops->len % mtd->writesize) != 0) {
845 /* when ops->datbuf is NULL, ops->len can be ooblen */
846 pr_err("%s: unsupported ops->len, %d\n",
847 __func__, ops->len);
848 return -EINVAL;
849 }
850 } else {
851 if (ops->datbuf != NULL &&
852 (ops->len % (mtd->writesize + mtd->oobsize)) != 0) {
853 pr_err("%s: unsupported ops->len,"
854 " %d for MTD_OOB_RAW\n", __func__, ops->len);
855 return -EINVAL;
856 }
857 }
858
859 if (ops->mode != MTD_OOB_RAW && ops->ooblen != 0 && ops->ooboffs != 0) {
860 pr_err("%s: unsupported ops->ooboffs, %d\n",
861 __func__, ops->ooboffs);
862 return -EINVAL;
863 }
864
865 if (ops->oobbuf && !ops->datbuf && ops->mode == MTD_OOB_AUTO)
866 start_sector = cwperpage - 1;
867
868 if (ops->oobbuf && !ops->datbuf) {
869 page_count = ops->ooblen / ((ops->mode == MTD_OOB_AUTO) ?
870 mtd->oobavail : mtd->oobsize);
871 if ((page_count == 0) && (ops->ooblen))
872 page_count = 1;
873 } else if (ops->mode != MTD_OOB_RAW)
874 page_count = ops->len / mtd->writesize;
875 else
876 page_count = ops->len / (mtd->writesize + mtd->oobsize);
877
878 if (ops->datbuf) {
879 data_dma_addr_curr = data_dma_addr =
880 msm_nand_dma_map(chip->dev, ops->datbuf, ops->len,
881 DMA_FROM_DEVICE);
882 if (dma_mapping_error(chip->dev, data_dma_addr)) {
883 pr_err("msm_nand_read_oob: failed to get dma addr "
884 "for %p\n", ops->datbuf);
885 return -EIO;
886 }
887 }
888 if (ops->oobbuf) {
889 memset(ops->oobbuf, 0xff, ops->ooblen);
890 oob_dma_addr_curr = oob_dma_addr =
891 msm_nand_dma_map(chip->dev, ops->oobbuf,
892 ops->ooblen, DMA_BIDIRECTIONAL);
893 if (dma_mapping_error(chip->dev, oob_dma_addr)) {
894 pr_err("msm_nand_read_oob: failed to get dma addr "
895 "for %p\n", ops->oobbuf);
896 err = -EIO;
897 goto err_dma_map_oobbuf_failed;
898 }
899 }
900
901 wait_event(chip->wait_queue,
902 (dma_buffer = msm_nand_get_dma_buffer(
903 chip, sizeof(*dma_buffer))));
904
905 oob_col = start_sector * chip->cw_size;
906 if (chip->CFG1 & CFG1_WIDE_FLASH)
907 oob_col >>= 1;
908
909 err = 0;
910 while (page_count-- > 0) {
911 cmd = dma_buffer->cmd;
912
913 /* CMD / ADDR0 / ADDR1 / CHIPSEL program values */
914 if (ops->mode != MTD_OOB_RAW) {
915 dma_buffer->data.cmd = MSM_NAND_CMD_PAGE_READ_ECC;
916 dma_buffer->data.cfg0 =
917 (chip->CFG0 & ~(7U << 6))
918 | (((cwperpage-1) - start_sector) << 6);
919 dma_buffer->data.cfg1 = chip->CFG1;
920 if (enable_bch_ecc)
921 dma_buffer->data.eccbchcfg = chip->ecc_bch_cfg;
922 } else {
923 dma_buffer->data.cmd = MSM_NAND_CMD_PAGE_READ;
924 dma_buffer->data.cfg0 = (chip->CFG0_RAW
925 & ~(7U << 6)) | ((cwperpage-1) << 6);
926 dma_buffer->data.cfg1 = chip->CFG1_RAW |
927 (chip->CFG1 & CFG1_WIDE_FLASH);
928 }
929
930 dma_buffer->data.addr0 = (page << 16) | oob_col;
931 dma_buffer->data.addr1 = (page >> 16) & 0xff;
932 /* chipsel_0 + enable DM interface */
933 dma_buffer->data.chipsel = 0 | 4;
934
935
936 /* GO bit for the EXEC register */
937 dma_buffer->data.exec = 1;
938
939
940 BUILD_BUG_ON(8 != ARRAY_SIZE(dma_buffer->data.result));
941
942 for (n = start_sector; n < cwperpage; n++) {
943 /* flash + buffer status return words */
944 dma_buffer->data.result[n].flash_status = 0xeeeeeeee;
945 dma_buffer->data.result[n].buffer_status = 0xeeeeeeee;
946
947 /* block on cmd ready, then
948 * write CMD / ADDR0 / ADDR1 / CHIPSEL
949 * regs in a burst
950 */
951 cmd->cmd = DST_CRCI_NAND_CMD;
952 cmd->src = msm_virt_to_dma(chip, &dma_buffer->data.cmd);
953 cmd->dst = MSM_NAND_FLASH_CMD;
954 if (n == start_sector)
955 cmd->len = 16;
956 else
957 cmd->len = 4;
958 cmd++;
959
960 if (n == start_sector) {
961 cmd->cmd = 0;
962 cmd->src = msm_virt_to_dma(chip,
963 &dma_buffer->data.cfg0);
964 cmd->dst = MSM_NAND_DEV0_CFG0;
965 if (enable_bch_ecc)
966 cmd->len = 12;
967 else
968 cmd->len = 8;
969 cmd++;
970
971 dma_buffer->data.ecccfg = chip->ecc_buf_cfg;
972 cmd->cmd = 0;
973 cmd->src = msm_virt_to_dma(chip,
974 &dma_buffer->data.ecccfg);
975 cmd->dst = MSM_NAND_EBI2_ECC_BUF_CFG;
976 cmd->len = 4;
977 cmd++;
978 }
979
980 /* kick the execute register */
981 cmd->cmd = 0;
982 cmd->src =
983 msm_virt_to_dma(chip, &dma_buffer->data.exec);
984 cmd->dst = MSM_NAND_EXEC_CMD;
985 cmd->len = 4;
986 cmd++;
987
988 /* block on data ready, then
989 * read the status register
990 */
991 cmd->cmd = SRC_CRCI_NAND_DATA;
992 cmd->src = MSM_NAND_FLASH_STATUS;
993 cmd->dst = msm_virt_to_dma(chip,
994 &dma_buffer->data.result[n]);
995 /* MSM_NAND_FLASH_STATUS + MSM_NAND_BUFFER_STATUS */
996 cmd->len = 8;
997 cmd++;
998
999 /* read data block
1000 * (only valid if status says success)
1001 */
1002 if (ops->datbuf) {
1003 if (ops->mode != MTD_OOB_RAW)
1004 sectordatasize = (n < (cwperpage - 1))
1005 ? 516 : (512 - ((cwperpage - 1) << 2));
1006 else
1007 sectordatasize = chip->cw_size;
1008
1009 cmd->cmd = 0;
1010 cmd->src = MSM_NAND_FLASH_BUFFER;
1011 cmd->dst = data_dma_addr_curr;
1012 data_dma_addr_curr += sectordatasize;
1013 cmd->len = sectordatasize;
1014 cmd++;
1015 }
1016
1017 if (ops->oobbuf && (n == (cwperpage - 1)
1018 || ops->mode != MTD_OOB_AUTO)) {
1019 cmd->cmd = 0;
1020 if (n == (cwperpage - 1)) {
1021 cmd->src = MSM_NAND_FLASH_BUFFER +
1022 (512 - ((cwperpage - 1) << 2));
1023 sectoroobsize = (cwperpage << 2);
1024 if (ops->mode != MTD_OOB_AUTO)
1025 sectoroobsize +=
1026 chip->ecc_parity_bytes;
1027 } else {
1028 cmd->src = MSM_NAND_FLASH_BUFFER + 516;
1029 sectoroobsize = chip->ecc_parity_bytes;
1030 }
1031
1032 cmd->dst = oob_dma_addr_curr;
1033 if (sectoroobsize < oob_len)
1034 cmd->len = sectoroobsize;
1035 else
1036 cmd->len = oob_len;
1037 oob_dma_addr_curr += cmd->len;
1038 oob_len -= cmd->len;
1039 if (cmd->len > 0)
1040 cmd++;
1041 }
1042 }
1043
1044 BUILD_BUG_ON(8 * 5 + 2 != ARRAY_SIZE(dma_buffer->cmd));
1045 BUG_ON(cmd - dma_buffer->cmd > ARRAY_SIZE(dma_buffer->cmd));
1046 dma_buffer->cmd[0].cmd |= CMD_OCB;
1047 cmd[-1].cmd |= CMD_OCU | CMD_LC;
1048
1049 dma_buffer->cmdptr =
1050 (msm_virt_to_dma(chip, dma_buffer->cmd) >> 3)
1051 | CMD_PTR_LP;
1052
1053 mb();
1054 msm_dmov_exec_cmd(chip->dma_channel, crci_mask,
1055 DMOV_CMD_PTR_LIST | DMOV_CMD_ADDR(msm_virt_to_dma(chip,
1056 &dma_buffer->cmdptr)));
1057 mb();
1058
1059 /* if any of the writes failed (0x10), or there
1060 * was a protection violation (0x100), we lose
1061 */
1062 pageerr = rawerr = 0;
1063 for (n = start_sector; n < cwperpage; n++) {
1064 if (dma_buffer->data.result[n].flash_status & 0x110) {
1065 rawerr = -EIO;
1066 break;
1067 }
1068 }
1069 if (rawerr) {
1070 if (ops->datbuf && ops->mode != MTD_OOB_RAW) {
1071 uint8_t *datbuf = ops->datbuf +
1072 pages_read * mtd->writesize;
1073
1074 dma_sync_single_for_cpu(chip->dev,
1075 data_dma_addr_curr-mtd->writesize,
1076 mtd->writesize, DMA_BIDIRECTIONAL);
1077
1078 for (n = 0; n < mtd->writesize; n++) {
1079 /* empty blocks read 0x54 at
1080 * these offsets
1081 */
1082 if ((n % 516 == 3 || n % 516 == 175)
1083 && datbuf[n] == 0x54)
1084 datbuf[n] = 0xff;
1085 if (datbuf[n] != 0xff) {
1086 pageerr = rawerr;
1087 break;
1088 }
1089 }
1090
1091 dma_sync_single_for_device(chip->dev,
1092 data_dma_addr_curr-mtd->writesize,
1093 mtd->writesize, DMA_BIDIRECTIONAL);
1094
1095 }
1096 if (ops->oobbuf) {
1097 dma_sync_single_for_cpu(chip->dev,
1098 oob_dma_addr_curr - (ops->ooblen - oob_len),
1099 ops->ooblen - oob_len, DMA_BIDIRECTIONAL);
1100
1101 for (n = 0; n < ops->ooblen; n++) {
1102 if (ops->oobbuf[n] != 0xff) {
1103 pageerr = rawerr;
1104 break;
1105 }
1106 }
1107
1108 dma_sync_single_for_device(chip->dev,
1109 oob_dma_addr_curr - (ops->ooblen - oob_len),
1110 ops->ooblen - oob_len, DMA_BIDIRECTIONAL);
1111 }
1112 }
1113 if (pageerr) {
1114 for (n = start_sector; n < cwperpage; n++) {
1115 if (enable_bch_ecc ?
1116 (dma_buffer->data.result[n].buffer_status & 0x10) :
1117 (dma_buffer->data.result[n].buffer_status & 0x8)) {
1118 /* not thread safe */
1119 mtd->ecc_stats.failed++;
1120 pageerr = -EBADMSG;
1121 break;
1122 }
1123 }
1124 }
1125 if (!rawerr) { /* check for corretable errors */
1126 for (n = start_sector; n < cwperpage; n++) {
1127 ecc_errors = enable_bch_ecc ?
1128 (dma_buffer->data.result[n].buffer_status & 0xF) :
1129 (dma_buffer->data.result[n].buffer_status & 0x7);
1130 if (ecc_errors) {
1131 total_ecc_errors += ecc_errors;
1132 /* not thread safe */
1133 mtd->ecc_stats.corrected += ecc_errors;
1134 if (ecc_errors > 1)
1135 pageerr = -EUCLEAN;
1136 }
1137 }
1138 }
1139 if (pageerr && (pageerr != -EUCLEAN || err == 0))
1140 err = pageerr;
1141
1142#if VERBOSE
1143 if (rawerr && !pageerr) {
1144 pr_err("msm_nand_read_oob %llx %x %x empty page\n",
1145 (loff_t)page * mtd->writesize, ops->len,
1146 ops->ooblen);
1147 } else {
1148 for (n = start_sector; n < cwperpage; n++)
1149 pr_info("flash_status[%d] = %x,\
1150 buffr_status[%d] = %x\n",
1151 n, dma_buffer->data.result[n].flash_status,
1152 n, dma_buffer->data.result[n].buffer_status);
1153 }
1154#endif
1155 if (err && err != -EUCLEAN && err != -EBADMSG)
1156 break;
1157 pages_read++;
1158 page++;
1159 }
1160 msm_nand_release_dma_buffer(chip, dma_buffer, sizeof(*dma_buffer));
1161
1162 if (ops->oobbuf) {
1163 dma_unmap_page(chip->dev, oob_dma_addr,
1164 ops->ooblen, DMA_FROM_DEVICE);
1165 }
1166err_dma_map_oobbuf_failed:
1167 if (ops->datbuf) {
1168 dma_unmap_page(chip->dev, data_dma_addr,
1169 ops->len, DMA_BIDIRECTIONAL);
1170 }
1171
1172 if (ops->mode != MTD_OOB_RAW)
1173 ops->retlen = mtd->writesize * pages_read;
1174 else
1175 ops->retlen = (mtd->writesize + mtd->oobsize) *
1176 pages_read;
1177 ops->oobretlen = ops->ooblen - oob_len;
1178 if (err)
1179 pr_err("msm_nand_read_oob %llx %x %x failed %d, corrected %d\n",
1180 from, ops->datbuf ? ops->len : 0, ops->ooblen, err,
1181 total_ecc_errors);
1182#if VERBOSE
1183 pr_info("\n%s: ret %d, retlen %d oobretlen %d\n",
1184 __func__, err, ops->retlen, ops->oobretlen);
1185
1186 pr_info("==================================================="
1187 "==============\n");
1188#endif
1189 return err;
1190}
1191
1192static int msm_nand_read_oob_dualnandc(struct mtd_info *mtd, loff_t from,
1193 struct mtd_oob_ops *ops)
1194{
1195 struct msm_nand_chip *chip = mtd->priv;
1196
1197 struct {
1198 dmov_s cmd[16 * 6 + 20];
1199 unsigned cmdptr;
1200 struct {
1201 uint32_t cmd;
1202 uint32_t nandc01_addr0;
1203 uint32_t nandc10_addr0;
1204 uint32_t nandc11_addr1;
1205 uint32_t chipsel_cs0;
1206 uint32_t chipsel_cs1;
1207 uint32_t cfg0;
1208 uint32_t cfg1;
1209 uint32_t eccbchcfg;
1210 uint32_t exec;
1211 uint32_t ecccfg;
1212 uint32_t ebi2_chip_select_cfg0;
1213 uint32_t adm_mux_data_ack_req_nc01;
1214 uint32_t adm_mux_cmd_ack_req_nc01;
1215 uint32_t adm_mux_data_ack_req_nc10;
1216 uint32_t adm_mux_cmd_ack_req_nc10;
1217 uint32_t adm_default_mux;
1218 uint32_t default_ebi2_chip_select_cfg0;
1219 uint32_t nc10_flash_dev_cmd_vld;
1220 uint32_t nc10_flash_dev_cmd1;
1221 uint32_t nc10_flash_dev_cmd_vld_default;
1222 uint32_t nc10_flash_dev_cmd1_default;
1223 struct {
1224 uint32_t flash_status;
1225 uint32_t buffer_status;
1226 } result[16];
1227 } data;
1228 } *dma_buffer;
1229 dmov_s *cmd;
1230 unsigned n;
1231 unsigned page = 0;
1232 uint32_t oob_len;
1233 uint32_t sectordatasize;
1234 uint32_t sectoroobsize;
1235 int err, pageerr, rawerr;
1236 dma_addr_t data_dma_addr = 0;
1237 dma_addr_t oob_dma_addr = 0;
1238 dma_addr_t data_dma_addr_curr = 0;
1239 dma_addr_t oob_dma_addr_curr = 0;
1240 uint32_t oob_col = 0;
1241 unsigned page_count;
1242 unsigned pages_read = 0;
1243 unsigned start_sector = 0;
1244 uint32_t ecc_errors;
1245 uint32_t total_ecc_errors = 0;
1246 unsigned cwperpage;
1247 unsigned cw_offset = chip->cw_size;
1248#if VERBOSE
1249 pr_info("================================================="
1250 "============\n");
1251 pr_info("%s:\nfrom 0x%llx mode %d\ndatbuf 0x%p datlen 0x%x"
1252 "\noobbuf 0x%p ooblen 0x%x\n\n",
1253 __func__, from, ops->mode, ops->datbuf,
1254 ops->len, ops->oobbuf, ops->ooblen);
1255#endif
1256
1257 if (mtd->writesize == 2048)
1258 page = from >> 11;
1259
1260 if (mtd->writesize == 4096)
1261 page = from >> 12;
1262
1263 if (interleave_enable)
1264 page = (from >> 1) >> 12;
1265
1266 oob_len = ops->ooblen;
1267 cwperpage = (mtd->writesize >> 9);
1268
1269 if (from & (mtd->writesize - 1)) {
1270 pr_err("%s: unsupported from, 0x%llx\n",
1271 __func__, from);
1272 return -EINVAL;
1273 }
1274 if (ops->mode != MTD_OOB_RAW) {
1275 if (ops->datbuf != NULL && (ops->len % mtd->writesize) != 0) {
1276 pr_err("%s: unsupported ops->len, %d\n",
1277 __func__, ops->len);
1278 return -EINVAL;
1279 }
1280 } else {
1281 if (ops->datbuf != NULL &&
1282 (ops->len % (mtd->writesize + mtd->oobsize)) != 0) {
1283 pr_err("%s: unsupported ops->len,"
1284 " %d for MTD_OOB_RAW\n", __func__, ops->len);
1285 return -EINVAL;
1286 }
1287 }
1288
1289 if (ops->mode != MTD_OOB_RAW && ops->ooblen != 0 && ops->ooboffs != 0) {
1290 pr_err("%s: unsupported ops->ooboffs, %d\n",
1291 __func__, ops->ooboffs);
1292 return -EINVAL;
1293 }
1294
1295 if (ops->oobbuf && !ops->datbuf && ops->mode == MTD_OOB_AUTO)
1296 start_sector = cwperpage - 1;
1297
1298 if (ops->oobbuf && !ops->datbuf) {
1299 page_count = ops->ooblen / ((ops->mode == MTD_OOB_AUTO) ?
1300 mtd->oobavail : mtd->oobsize);
1301 if ((page_count == 0) && (ops->ooblen))
1302 page_count = 1;
1303 } else if (ops->mode != MTD_OOB_RAW)
1304 page_count = ops->len / mtd->writesize;
1305 else
1306 page_count = ops->len / (mtd->writesize + mtd->oobsize);
1307
1308 if (ops->datbuf) {
1309 data_dma_addr_curr = data_dma_addr =
1310 msm_nand_dma_map(chip->dev, ops->datbuf, ops->len,
1311 DMA_FROM_DEVICE);
1312 if (dma_mapping_error(chip->dev, data_dma_addr)) {
1313 pr_err("msm_nand_read_oob_dualnandc: "
1314 "failed to get dma addr for %p\n",
1315 ops->datbuf);
1316 return -EIO;
1317 }
1318 }
1319 if (ops->oobbuf) {
1320 memset(ops->oobbuf, 0xff, ops->ooblen);
1321 oob_dma_addr_curr = oob_dma_addr =
1322 msm_nand_dma_map(chip->dev, ops->oobbuf,
1323 ops->ooblen, DMA_BIDIRECTIONAL);
1324 if (dma_mapping_error(chip->dev, oob_dma_addr)) {
1325 pr_err("msm_nand_read_oob_dualnandc: "
1326 "failed to get dma addr for %p\n",
1327 ops->oobbuf);
1328 err = -EIO;
1329 goto err_dma_map_oobbuf_failed;
1330 }
1331 }
1332
1333 wait_event(chip->wait_queue,
1334 (dma_buffer = msm_nand_get_dma_buffer(
1335 chip, sizeof(*dma_buffer))));
1336
1337 oob_col = start_sector * chip->cw_size;
1338 if (chip->CFG1 & CFG1_WIDE_FLASH) {
1339 oob_col >>= 1;
1340 cw_offset >>= 1;
1341 }
1342
1343 err = 0;
1344 while (page_count-- > 0) {
1345 cmd = dma_buffer->cmd;
1346
1347 if (ops->mode != MTD_OOB_RAW) {
1348 dma_buffer->data.cmd = MSM_NAND_CMD_PAGE_READ_ECC;
1349 if (start_sector == (cwperpage - 1)) {
1350 dma_buffer->data.cfg0 = (chip->CFG0 &
1351 ~(7U << 6));
1352 } else {
1353 dma_buffer->data.cfg0 = (chip->CFG0 &
1354 ~(7U << 6))
1355 | (((cwperpage >> 1)-1) << 6);
1356 }
1357 dma_buffer->data.cfg1 = chip->CFG1;
1358 if (enable_bch_ecc)
1359 dma_buffer->data.eccbchcfg = chip->ecc_bch_cfg;
1360 } else {
1361 dma_buffer->data.cmd = MSM_NAND_CMD_PAGE_READ;
1362 dma_buffer->data.cfg0 = ((chip->CFG0_RAW &
1363 ~(7U << 6)) | ((((cwperpage >> 1)-1) << 6)));
1364 dma_buffer->data.cfg1 = chip->CFG1_RAW |
1365 (chip->CFG1 & CFG1_WIDE_FLASH);
1366 }
1367
1368 if (!interleave_enable) {
1369 if (start_sector == (cwperpage - 1)) {
1370 dma_buffer->data.nandc10_addr0 =
1371 (page << 16) | oob_col;
1372 dma_buffer->data.nc10_flash_dev_cmd_vld = 0xD;
1373 dma_buffer->data.nc10_flash_dev_cmd1 =
1374 0xF00F3000;
1375 } else {
1376 dma_buffer->data.nandc01_addr0 = page << 16;
1377 /* NC10 ADDR0 points to the next code word */
1378 dma_buffer->data.nandc10_addr0 = (page << 16) |
1379 cw_offset;
1380 dma_buffer->data.nc10_flash_dev_cmd_vld = 0x1D;
1381 dma_buffer->data.nc10_flash_dev_cmd1 =
1382 0xF00FE005;
1383 }
1384 } else {
1385 dma_buffer->data.nandc01_addr0 =
1386 dma_buffer->data.nandc10_addr0 =
1387 (page << 16) | oob_col;
1388 }
1389 /* ADDR1 */
1390 dma_buffer->data.nandc11_addr1 = (page >> 16) & 0xff;
1391
1392 dma_buffer->data.adm_mux_data_ack_req_nc01 = 0x00000A3C;
1393 dma_buffer->data.adm_mux_cmd_ack_req_nc01 = 0x0000053C;
1394 dma_buffer->data.adm_mux_data_ack_req_nc10 = 0x00000F28;
1395 dma_buffer->data.adm_mux_cmd_ack_req_nc10 = 0x00000F14;
1396 dma_buffer->data.adm_default_mux = 0x00000FC0;
1397 dma_buffer->data.nc10_flash_dev_cmd_vld_default = 0x1D;
1398 dma_buffer->data.nc10_flash_dev_cmd1_default = 0xF00F3000;
1399
1400 dma_buffer->data.ebi2_chip_select_cfg0 = 0x00000805;
1401 dma_buffer->data.default_ebi2_chip_select_cfg0 = 0x00000801;
1402
1403 /* chipsel_0 + enable DM interface */
1404 dma_buffer->data.chipsel_cs0 = (1<<4) | 4;
1405 /* chipsel_1 + enable DM interface */
1406 dma_buffer->data.chipsel_cs1 = (1<<4) | 5;
1407
1408 /* GO bit for the EXEC register */
1409 dma_buffer->data.exec = 1;
1410
1411 BUILD_BUG_ON(16 != ARRAY_SIZE(dma_buffer->data.result));
1412
1413 for (n = start_sector; n < cwperpage; n++) {
1414 /* flash + buffer status return words */
1415 dma_buffer->data.result[n].flash_status = 0xeeeeeeee;
1416 dma_buffer->data.result[n].buffer_status = 0xeeeeeeee;
1417
1418 if (n == start_sector) {
1419 if (!interleave_enable) {
1420 cmd->cmd = 0;
1421 cmd->src = msm_virt_to_dma(chip,
1422 &dma_buffer->
1423 data.nc10_flash_dev_cmd_vld);
1424 cmd->dst = NC10(MSM_NAND_DEV_CMD_VLD);
1425 cmd->len = 4;
1426 cmd++;
1427
1428 cmd->cmd = 0;
1429 cmd->src = msm_virt_to_dma(chip,
1430 &dma_buffer->data.nc10_flash_dev_cmd1);
1431 cmd->dst = NC10(MSM_NAND_DEV_CMD1);
1432 cmd->len = 4;
1433 cmd++;
1434
1435 /* NC01, NC10 --> ADDR1 */
1436 cmd->cmd = 0;
1437 cmd->src = msm_virt_to_dma(chip,
1438 &dma_buffer->data.nandc11_addr1);
1439 cmd->dst = NC11(MSM_NAND_ADDR1);
1440 cmd->len = 8;
1441 cmd++;
1442
1443 cmd->cmd = 0;
1444 cmd->src = msm_virt_to_dma(chip,
1445 &dma_buffer->data.cfg0);
1446 cmd->dst = NC11(MSM_NAND_DEV0_CFG0);
1447 if (enable_bch_ecc)
1448 cmd->len = 12;
1449 else
1450 cmd->len = 8;
1451 cmd++;
1452 } else {
1453 /* enable CS0 & CS1 */
1454 cmd->cmd = 0;
1455 cmd->src = msm_virt_to_dma(chip,
1456 &dma_buffer->
1457 data.ebi2_chip_select_cfg0);
1458 cmd->dst = EBI2_CHIP_SELECT_CFG0;
1459 cmd->len = 4;
1460 cmd++;
1461
1462 /* NC01, NC10 --> ADDR1 */
1463 cmd->cmd = 0;
1464 cmd->src = msm_virt_to_dma(chip,
1465 &dma_buffer->data.nandc11_addr1);
1466 cmd->dst = NC11(MSM_NAND_ADDR1);
1467 cmd->len = 4;
1468 cmd++;
1469
1470 /* Enable CS0 for NC01 */
1471 cmd->cmd = 0;
1472 cmd->src = msm_virt_to_dma(chip,
1473 &dma_buffer->data.chipsel_cs0);
1474 cmd->dst =
1475 NC01(MSM_NAND_FLASH_CHIP_SELECT);
1476 cmd->len = 4;
1477 cmd++;
1478
1479 /* Enable CS1 for NC10 */
1480 cmd->cmd = 0;
1481 cmd->src = msm_virt_to_dma(chip,
1482 &dma_buffer->data.chipsel_cs1);
1483 cmd->dst =
1484 NC10(MSM_NAND_FLASH_CHIP_SELECT);
1485 cmd->len = 4;
1486 cmd++;
1487
1488 /* config DEV0_CFG0 & CFG1 for CS0 */
1489 cmd->cmd = 0;
1490 cmd->src = msm_virt_to_dma(chip,
1491 &dma_buffer->data.cfg0);
1492 cmd->dst = NC01(MSM_NAND_DEV0_CFG0);
1493 cmd->len = 8;
1494 cmd++;
1495
1496 /* config DEV1_CFG0 & CFG1 for CS1 */
1497 cmd->cmd = 0;
1498 cmd->src = msm_virt_to_dma(chip,
1499 &dma_buffer->data.cfg0);
1500 cmd->dst = NC10(MSM_NAND_DEV1_CFG0);
1501 cmd->len = 8;
1502 cmd++;
1503 }
1504
1505 dma_buffer->data.ecccfg = chip->ecc_buf_cfg;
1506 cmd->cmd = 0;
1507 cmd->src = msm_virt_to_dma(chip,
1508 &dma_buffer->data.ecccfg);
1509 cmd->dst = NC11(MSM_NAND_EBI2_ECC_BUF_CFG);
1510 cmd->len = 4;
1511 cmd++;
1512
1513 /* if 'only' the last code word */
1514 if (n == cwperpage - 1) {
1515 /* MASK CMD ACK/REQ --> NC01 (0x53C)*/
1516 cmd->cmd = 0;
1517 cmd->src = msm_virt_to_dma(chip,
1518 &dma_buffer->
1519 data.adm_mux_cmd_ack_req_nc01);
1520 cmd->dst = EBI2_NAND_ADM_MUX;
1521 cmd->len = 4;
1522 cmd++;
1523
1524 /* CMD */
1525 cmd->cmd = DST_CRCI_NAND_CMD;
1526 cmd->src = msm_virt_to_dma(chip,
1527 &dma_buffer->data.cmd);
1528 cmd->dst = NC10(MSM_NAND_FLASH_CMD);
1529 cmd->len = 4;
1530 cmd++;
1531
1532 /* NC10 --> ADDR0 ( 0x0 ) */
1533 cmd->cmd = 0;
1534 cmd->src = msm_virt_to_dma(chip,
1535 &dma_buffer->data.nandc10_addr0);
1536 cmd->dst = NC10(MSM_NAND_ADDR0);
1537 cmd->len = 4;
1538 cmd++;
1539
1540 /* kick the execute reg for NC10 */
1541 cmd->cmd = 0;
1542 cmd->src = msm_virt_to_dma(chip,
1543 &dma_buffer->data.exec);
1544 cmd->dst = NC10(MSM_NAND_EXEC_CMD);
1545 cmd->len = 4;
1546 cmd++;
1547
1548 /* MASK DATA ACK/REQ --> NC01 (0xA3C)*/
1549 cmd->cmd = 0;
1550 cmd->src = msm_virt_to_dma(chip,
1551 &dma_buffer->
1552 data.adm_mux_data_ack_req_nc01);
1553 cmd->dst = EBI2_NAND_ADM_MUX;
1554 cmd->len = 4;
1555 cmd++;
1556
1557 /* block on data ready from NC10, then
1558 * read the status register
1559 */
1560 cmd->cmd = SRC_CRCI_NAND_DATA;
1561 cmd->src = NC10(MSM_NAND_FLASH_STATUS);
1562 cmd->dst = msm_virt_to_dma(chip,
1563 &dma_buffer->data.result[n]);
1564 /* MSM_NAND_FLASH_STATUS +
1565 * MSM_NAND_BUFFER_STATUS
1566 */
1567 cmd->len = 8;
1568 cmd++;
1569 } else {
1570 /* NC01 --> ADDR0 */
1571 cmd->cmd = 0;
1572 cmd->src = msm_virt_to_dma(chip,
1573 &dma_buffer->data.nandc01_addr0);
1574 cmd->dst = NC01(MSM_NAND_ADDR0);
1575 cmd->len = 4;
1576 cmd++;
1577
1578 /* NC10 --> ADDR1 */
1579 cmd->cmd = 0;
1580 cmd->src = msm_virt_to_dma(chip,
1581 &dma_buffer->data.nandc10_addr0);
1582 cmd->dst = NC10(MSM_NAND_ADDR0);
1583 cmd->len = 4;
1584 cmd++;
1585
1586 /* MASK CMD ACK/REQ --> NC10 (0xF14)*/
1587 cmd->cmd = 0;
1588 cmd->src = msm_virt_to_dma(chip,
1589 &dma_buffer->
1590 data.adm_mux_cmd_ack_req_nc10);
1591 cmd->dst = EBI2_NAND_ADM_MUX;
1592 cmd->len = 4;
1593 cmd++;
1594
1595 /* CMD */
1596 cmd->cmd = DST_CRCI_NAND_CMD;
1597 cmd->src = msm_virt_to_dma(chip,
1598 &dma_buffer->data.cmd);
1599 cmd->dst = NC01(MSM_NAND_FLASH_CMD);
1600 cmd->len = 4;
1601 cmd++;
1602
1603 /* kick the execute register for NC01*/
1604 cmd->cmd = 0;
1605 cmd->src = msm_virt_to_dma(chip,
1606 &dma_buffer->data.exec);
1607 cmd->dst = NC01(MSM_NAND_EXEC_CMD);
1608 cmd->len = 4;
1609 cmd++;
1610 }
1611 }
1612
1613 /* read data block
1614 * (only valid if status says success)
1615 */
1616 if (ops->datbuf || (ops->oobbuf &&
1617 ops->mode != MTD_OOB_AUTO)) {
1618 if (ops->mode != MTD_OOB_RAW)
1619 sectordatasize = (n < (cwperpage - 1))
1620 ? 516 : (512 - ((cwperpage - 1) << 2));
1621 else
1622 sectordatasize = chip->cw_size;
1623
1624 if (n % 2 == 0) {
1625 /* MASK DATA ACK/REQ --> NC10 (0xF28)*/
1626 cmd->cmd = 0;
1627 cmd->src = msm_virt_to_dma(chip,
1628 &dma_buffer->
1629 data.adm_mux_data_ack_req_nc10);
1630 cmd->dst = EBI2_NAND_ADM_MUX;
1631 cmd->len = 4;
1632 cmd++;
1633
1634 /* block on data ready from NC01, then
1635 * read the status register
1636 */
1637 cmd->cmd = SRC_CRCI_NAND_DATA;
1638 cmd->src = NC01(MSM_NAND_FLASH_STATUS);
1639 cmd->dst = msm_virt_to_dma(chip,
1640 &dma_buffer->data.result[n]);
1641 /* MSM_NAND_FLASH_STATUS +
1642 * MSM_NAND_BUFFER_STATUS
1643 */
1644 cmd->len = 8;
1645 cmd++;
1646
1647 /* MASK CMD ACK/REQ --> NC01 (0x53C)*/
1648 cmd->cmd = 0;
1649 cmd->src = msm_virt_to_dma(chip,
1650 &dma_buffer->
1651 data.adm_mux_cmd_ack_req_nc01);
1652 cmd->dst = EBI2_NAND_ADM_MUX;
1653 cmd->len = 4;
1654 cmd++;
1655
1656 /* CMD */
1657 cmd->cmd = DST_CRCI_NAND_CMD;
1658 cmd->src = msm_virt_to_dma(chip,
1659 &dma_buffer->data.cmd);
1660 cmd->dst = NC10(MSM_NAND_FLASH_CMD);
1661 cmd->len = 4;
1662 cmd++;
1663
1664 /* kick the execute register for NC10 */
1665 cmd->cmd = 0;
1666 cmd->src = msm_virt_to_dma(chip,
1667 &dma_buffer->data.exec);
1668 cmd->dst = NC10(MSM_NAND_EXEC_CMD);
1669 cmd->len = 4;
1670 cmd++;
1671
1672 /* Read only when there is data
1673 * buffer
1674 */
1675 if (ops->datbuf) {
1676 cmd->cmd = 0;
1677 cmd->src =
1678 NC01(MSM_NAND_FLASH_BUFFER);
1679 cmd->dst = data_dma_addr_curr;
1680 data_dma_addr_curr +=
1681 sectordatasize;
1682 cmd->len = sectordatasize;
1683 cmd++;
1684 }
1685 } else {
1686 /* MASK DATA ACK/REQ -->
1687 * NC01 (0xA3C)
1688 */
1689 cmd->cmd = 0;
1690 cmd->src = msm_virt_to_dma(chip,
1691 &dma_buffer->
1692 data.adm_mux_data_ack_req_nc01);
1693 cmd->dst = EBI2_NAND_ADM_MUX;
1694 cmd->len = 4;
1695 cmd++;
1696
1697 /* block on data ready from NC10
1698 * then read the status register
1699 */
1700 cmd->cmd = SRC_CRCI_NAND_DATA;
1701 cmd->src =
1702 NC10(MSM_NAND_FLASH_STATUS);
1703 cmd->dst = msm_virt_to_dma(chip,
1704 &dma_buffer->data.result[n]);
1705 /* MSM_NAND_FLASH_STATUS +
1706 * MSM_NAND_BUFFER_STATUS
1707 */
1708 cmd->len = 8;
1709 cmd++;
1710 if (n != cwperpage - 1) {
1711 /* MASK CMD ACK/REQ -->
1712 * NC10 (0xF14)
1713 */
1714 cmd->cmd = 0;
1715 cmd->src =
1716 msm_virt_to_dma(chip,
1717 &dma_buffer->
1718 data.adm_mux_cmd_ack_req_nc10);
1719 cmd->dst = EBI2_NAND_ADM_MUX;
1720 cmd->len = 4;
1721 cmd++;
1722
1723 /* CMD */
1724 cmd->cmd = DST_CRCI_NAND_CMD;
1725 cmd->src = msm_virt_to_dma(chip,
1726 &dma_buffer->data.cmd);
1727 cmd->dst =
1728 NC01(MSM_NAND_FLASH_CMD);
1729 cmd->len = 4;
1730 cmd++;
1731
1732 /* EXEC */
1733 cmd->cmd = 0;
1734 cmd->src = msm_virt_to_dma(chip,
1735 &dma_buffer->data.exec);
1736 cmd->dst =
1737 NC01(MSM_NAND_EXEC_CMD);
1738 cmd->len = 4;
1739 cmd++;
1740 }
1741
1742 /* Read only when there is data
1743 * buffer
1744 */
1745 if (ops->datbuf) {
1746 cmd->cmd = 0;
1747 cmd->src =
1748 NC10(MSM_NAND_FLASH_BUFFER);
1749 cmd->dst = data_dma_addr_curr;
1750 data_dma_addr_curr +=
1751 sectordatasize;
1752 cmd->len = sectordatasize;
1753 cmd++;
1754 }
1755 }
1756 }
1757
1758 if (ops->oobbuf && (n == (cwperpage - 1)
1759 || ops->mode != MTD_OOB_AUTO)) {
1760 cmd->cmd = 0;
1761 if (n == (cwperpage - 1)) {
1762 /* Use NC10 for reading the
1763 * last codeword!!!
1764 */
1765 cmd->src = NC10(MSM_NAND_FLASH_BUFFER) +
1766 (512 - ((cwperpage - 1) << 2));
1767 sectoroobsize = (cwperpage << 2);
1768 if (ops->mode != MTD_OOB_AUTO)
1769 sectoroobsize +=
1770 chip->ecc_parity_bytes;
1771 } else {
1772 if (n % 2 == 0)
1773 cmd->src =
1774 NC01(MSM_NAND_FLASH_BUFFER)
1775 + 516;
1776 else
1777 cmd->src =
1778 NC10(MSM_NAND_FLASH_BUFFER)
1779 + 516;
1780 sectoroobsize = chip->ecc_parity_bytes;
1781 }
1782 cmd->dst = oob_dma_addr_curr;
1783 if (sectoroobsize < oob_len)
1784 cmd->len = sectoroobsize;
1785 else
1786 cmd->len = oob_len;
1787 oob_dma_addr_curr += cmd->len;
1788 oob_len -= cmd->len;
1789 if (cmd->len > 0)
1790 cmd++;
1791 }
1792 }
1793 /* ADM --> Default mux state (0xFC0) */
1794 cmd->cmd = 0;
1795 cmd->src = msm_virt_to_dma(chip,
1796 &dma_buffer->data.adm_default_mux);
1797 cmd->dst = EBI2_NAND_ADM_MUX;
1798 cmd->len = 4;
1799 cmd++;
1800
1801 if (!interleave_enable) {
1802 cmd->cmd = 0;
1803 cmd->src = msm_virt_to_dma(chip,
1804 &dma_buffer->data.nc10_flash_dev_cmd_vld_default);
1805 cmd->dst = NC10(MSM_NAND_DEV_CMD_VLD);
1806 cmd->len = 4;
1807 cmd++;
1808
1809 cmd->cmd = 0;
1810 cmd->src = msm_virt_to_dma(chip,
1811 &dma_buffer->data.nc10_flash_dev_cmd1_default);
1812 cmd->dst = NC10(MSM_NAND_DEV_CMD1);
1813 cmd->len = 4;
1814 cmd++;
1815 } else {
1816 /* disable CS1 */
1817 cmd->cmd = 0;
1818 cmd->src = msm_virt_to_dma(chip,
1819 &dma_buffer->data.default_ebi2_chip_select_cfg0);
1820 cmd->dst = EBI2_CHIP_SELECT_CFG0;
1821 cmd->len = 4;
1822 cmd++;
1823 }
1824
1825 BUILD_BUG_ON(16 * 6 + 20 != ARRAY_SIZE(dma_buffer->cmd));
1826 BUG_ON(cmd - dma_buffer->cmd > ARRAY_SIZE(dma_buffer->cmd));
1827 dma_buffer->cmd[0].cmd |= CMD_OCB;
1828 cmd[-1].cmd |= CMD_OCU | CMD_LC;
1829
1830 dma_buffer->cmdptr =
1831 (msm_virt_to_dma(chip, dma_buffer->cmd) >> 3)
1832 | CMD_PTR_LP;
1833
1834 mb();
1835 msm_dmov_exec_cmd(chip->dma_channel, crci_mask,
1836 DMOV_CMD_PTR_LIST | DMOV_CMD_ADDR(msm_virt_to_dma(chip,
1837 &dma_buffer->cmdptr)));
1838 mb();
1839
1840 /* if any of the writes failed (0x10), or there
1841 * was a protection violation (0x100), we lose
1842 */
1843 pageerr = rawerr = 0;
1844 for (n = start_sector; n < cwperpage; n++) {
1845 if (dma_buffer->data.result[n].flash_status & 0x110) {
1846 rawerr = -EIO;
1847 break;
1848 }
1849 }
1850 if (rawerr) {
1851 if (ops->datbuf && ops->mode != MTD_OOB_RAW) {
1852 uint8_t *datbuf = ops->datbuf +
1853 pages_read * mtd->writesize;
1854
1855 dma_sync_single_for_cpu(chip->dev,
1856 data_dma_addr_curr-mtd->writesize,
1857 mtd->writesize, DMA_BIDIRECTIONAL);
1858
1859 for (n = 0; n < mtd->writesize; n++) {
1860 /* empty blocks read 0x54 at
1861 * these offsets
1862 */
1863 if ((n % 516 == 3 || n % 516 == 175)
1864 && datbuf[n] == 0x54)
1865 datbuf[n] = 0xff;
1866 if (datbuf[n] != 0xff) {
1867 pageerr = rawerr;
1868 break;
1869 }
1870 }
1871
1872 dma_sync_single_for_device(chip->dev,
1873 data_dma_addr_curr-mtd->writesize,
1874 mtd->writesize, DMA_BIDIRECTIONAL);
1875
1876 }
1877 if (ops->oobbuf) {
1878 dma_sync_single_for_cpu(chip->dev,
1879 oob_dma_addr_curr - (ops->ooblen - oob_len),
1880 ops->ooblen - oob_len, DMA_BIDIRECTIONAL);
1881
1882 for (n = 0; n < ops->ooblen; n++) {
1883 if (ops->oobbuf[n] != 0xff) {
1884 pageerr = rawerr;
1885 break;
1886 }
1887 }
1888
1889 dma_sync_single_for_device(chip->dev,
1890 oob_dma_addr_curr - (ops->ooblen - oob_len),
1891 ops->ooblen - oob_len, DMA_BIDIRECTIONAL);
1892 }
1893 }
1894 if (pageerr) {
1895 for (n = start_sector; n < cwperpage; n++) {
1896 if (dma_buffer->data.result[n].buffer_status
1897 & MSM_NAND_BUF_STAT_UNCRCTBL_ERR) {
1898 /* not thread safe */
1899 mtd->ecc_stats.failed++;
1900 pageerr = -EBADMSG;
1901 break;
1902 }
1903 }
1904 }
1905 if (!rawerr) { /* check for corretable errors */
1906 for (n = start_sector; n < cwperpage; n++) {
1907 ecc_errors = dma_buffer->data.
1908 result[n].buffer_status
1909 & MSM_NAND_BUF_STAT_NUM_ERR_MASK;
1910 if (ecc_errors) {
1911 total_ecc_errors += ecc_errors;
1912 /* not thread safe */
1913 mtd->ecc_stats.corrected += ecc_errors;
1914 if (ecc_errors > 1)
1915 pageerr = -EUCLEAN;
1916 }
1917 }
1918 }
1919 if (pageerr && (pageerr != -EUCLEAN || err == 0))
1920 err = pageerr;
1921
1922#if VERBOSE
1923 if (rawerr && !pageerr) {
1924 pr_err("msm_nand_read_oob_dualnandc "
1925 "%llx %x %x empty page\n",
1926 (loff_t)page * mtd->writesize, ops->len,
1927 ops->ooblen);
1928 } else {
1929 for (n = start_sector; n < cwperpage; n++) {
1930 if (n%2) {
1931 pr_info("NC10: flash_status[%d] = %x, "
1932 "buffr_status[%d] = %x\n",
1933 n, dma_buffer->
1934 data.result[n].flash_status,
1935 n, dma_buffer->
1936 data.result[n].buffer_status);
1937 } else {
1938 pr_info("NC01: flash_status[%d] = %x, "
1939 "buffr_status[%d] = %x\n",
1940 n, dma_buffer->
1941 data.result[n].flash_status,
1942 n, dma_buffer->
1943 data.result[n].buffer_status);
1944 }
1945 }
1946 }
1947#endif
1948 if (err && err != -EUCLEAN && err != -EBADMSG)
1949 break;
1950 pages_read++;
1951 page++;
1952 }
1953
1954 msm_nand_release_dma_buffer(chip, dma_buffer, sizeof(*dma_buffer));
1955
1956 if (ops->oobbuf) {
1957 dma_unmap_page(chip->dev, oob_dma_addr,
1958 ops->ooblen, DMA_FROM_DEVICE);
1959 }
1960err_dma_map_oobbuf_failed:
1961 if (ops->datbuf) {
1962 dma_unmap_page(chip->dev, data_dma_addr,
1963 ops->len, DMA_BIDIRECTIONAL);
1964 }
1965
1966 if (ops->mode != MTD_OOB_RAW)
1967 ops->retlen = mtd->writesize * pages_read;
1968 else
1969 ops->retlen = (mtd->writesize + mtd->oobsize) *
1970 pages_read;
1971 ops->oobretlen = ops->ooblen - oob_len;
1972 if (err)
1973 pr_err("msm_nand_read_oob_dualnandc "
1974 "%llx %x %x failed %d, corrected %d\n",
1975 from, ops->datbuf ? ops->len : 0, ops->ooblen, err,
1976 total_ecc_errors);
1977#if VERBOSE
1978 pr_info("\n%s: ret %d, retlen %d oobretlen %d\n",
1979 __func__, err, ops->retlen, ops->oobretlen);
1980
1981 pr_info("==================================================="
1982 "==========\n");
1983#endif
1984 return err;
1985}
1986
1987static int
1988msm_nand_read(struct mtd_info *mtd, loff_t from, size_t len,
1989 size_t *retlen, u_char *buf)
1990{
1991 int ret;
1992 struct mtd_oob_ops ops;
1993
1994 /* printk("msm_nand_read %llx %x\n", from, len); */
1995
1996 ops.mode = MTD_OOB_PLACE;
1997 ops.len = len;
1998 ops.retlen = 0;
1999 ops.ooblen = 0;
2000 ops.datbuf = buf;
2001 ops.oobbuf = NULL;
2002 if (!dual_nand_ctlr_present)
2003 ret = msm_nand_read_oob(mtd, from, &ops);
2004 else
2005 ret = msm_nand_read_oob_dualnandc(mtd, from, &ops);
2006 *retlen = ops.retlen;
2007 return ret;
2008}
2009
2010static int
2011msm_nand_write_oob(struct mtd_info *mtd, loff_t to, struct mtd_oob_ops *ops)
2012{
2013 struct msm_nand_chip *chip = mtd->priv;
2014 struct {
2015 dmov_s cmd[8 * 7 + 2];
2016 unsigned cmdptr;
2017 struct {
2018 uint32_t cmd;
2019 uint32_t addr0;
2020 uint32_t addr1;
2021 uint32_t chipsel;
2022 uint32_t cfg0;
2023 uint32_t cfg1;
2024 uint32_t eccbchcfg;
2025 uint32_t exec;
2026 uint32_t ecccfg;
2027 uint32_t clrfstatus;
2028 uint32_t clrrstatus;
2029 uint32_t flash_status[8];
2030 } data;
2031 } *dma_buffer;
2032 dmov_s *cmd;
2033 unsigned n;
2034 unsigned page = 0;
2035 uint32_t oob_len;
2036 uint32_t sectordatawritesize;
2037 int err = 0;
2038 dma_addr_t data_dma_addr = 0;
2039 dma_addr_t oob_dma_addr = 0;
2040 dma_addr_t data_dma_addr_curr = 0;
2041 dma_addr_t oob_dma_addr_curr = 0;
2042 unsigned page_count;
2043 unsigned pages_written = 0;
2044 unsigned cwperpage;
2045#if VERBOSE
2046 pr_info("================================================="
2047 "================\n");
2048 pr_info("%s:\nto 0x%llx mode %d\ndatbuf 0x%p datlen 0x%x"
2049 "\noobbuf 0x%p ooblen 0x%x\n",
2050 __func__, to, ops->mode, ops->datbuf, ops->len,
2051 ops->oobbuf, ops->ooblen);
2052#endif
2053
2054 if (mtd->writesize == 2048)
2055 page = to >> 11;
2056
2057 if (mtd->writesize == 4096)
2058 page = to >> 12;
2059
2060 oob_len = ops->ooblen;
2061 cwperpage = (mtd->writesize >> 9);
2062
2063 if (to & (mtd->writesize - 1)) {
2064 pr_err("%s: unsupported to, 0x%llx\n", __func__, to);
2065 return -EINVAL;
2066 }
2067
2068 if (ops->mode != MTD_OOB_RAW) {
2069 if (ops->ooblen != 0 && ops->mode != MTD_OOB_AUTO) {
2070 pr_err("%s: unsupported ops->mode,%d\n",
2071 __func__, ops->mode);
2072 return -EINVAL;
2073 }
2074 if ((ops->len % mtd->writesize) != 0) {
2075 pr_err("%s: unsupported ops->len, %d\n",
2076 __func__, ops->len);
2077 return -EINVAL;
2078 }
2079 } else {
2080 if ((ops->len % (mtd->writesize + mtd->oobsize)) != 0) {
2081 pr_err("%s: unsupported ops->len, "
2082 "%d for MTD_OOB_RAW mode\n",
2083 __func__, ops->len);
2084 return -EINVAL;
2085 }
2086 }
2087
2088 if (ops->datbuf == NULL) {
2089 pr_err("%s: unsupported ops->datbuf == NULL\n", __func__);
2090 return -EINVAL;
2091 }
2092 if (ops->mode != MTD_OOB_RAW && ops->ooblen != 0 && ops->ooboffs != 0) {
2093 pr_err("%s: unsupported ops->ooboffs, %d\n",
2094 __func__, ops->ooboffs);
2095 return -EINVAL;
2096 }
2097
2098 if (ops->datbuf) {
2099 data_dma_addr_curr = data_dma_addr =
2100 msm_nand_dma_map(chip->dev, ops->datbuf,
2101 ops->len, DMA_TO_DEVICE);
2102 if (dma_mapping_error(chip->dev, data_dma_addr)) {
2103 pr_err("msm_nand_write_oob: failed to get dma addr "
2104 "for %p\n", ops->datbuf);
2105 return -EIO;
2106 }
2107 }
2108 if (ops->oobbuf) {
2109 oob_dma_addr_curr = oob_dma_addr =
2110 msm_nand_dma_map(chip->dev, ops->oobbuf,
2111 ops->ooblen, DMA_TO_DEVICE);
2112 if (dma_mapping_error(chip->dev, oob_dma_addr)) {
2113 pr_err("msm_nand_write_oob: failed to get dma addr "
2114 "for %p\n", ops->oobbuf);
2115 err = -EIO;
2116 goto err_dma_map_oobbuf_failed;
2117 }
2118 }
2119 if (ops->mode != MTD_OOB_RAW)
2120 page_count = ops->len / mtd->writesize;
2121 else
2122 page_count = ops->len / (mtd->writesize + mtd->oobsize);
2123
2124 wait_event(chip->wait_queue, (dma_buffer =
2125 msm_nand_get_dma_buffer(chip, sizeof(*dma_buffer))));
2126
2127 while (page_count-- > 0) {
2128 cmd = dma_buffer->cmd;
2129
2130 if (ops->mode != MTD_OOB_RAW) {
2131 dma_buffer->data.cfg0 = chip->CFG0;
2132 dma_buffer->data.cfg1 = chip->CFG1;
2133 if (enable_bch_ecc)
2134 dma_buffer->data.eccbchcfg = chip->ecc_bch_cfg;
2135 } else {
2136 dma_buffer->data.cfg0 = (chip->CFG0_RAW &
2137 ~(7U << 6)) | ((cwperpage-1) << 6);
2138 dma_buffer->data.cfg1 = chip->CFG1_RAW |
2139 (chip->CFG1 & CFG1_WIDE_FLASH);
2140 }
2141
2142 /* CMD / ADDR0 / ADDR1 / CHIPSEL program values */
2143 dma_buffer->data.cmd = MSM_NAND_CMD_PRG_PAGE;
2144 dma_buffer->data.addr0 = page << 16;
2145 dma_buffer->data.addr1 = (page >> 16) & 0xff;
2146 /* chipsel_0 + enable DM interface */
2147 dma_buffer->data.chipsel = 0 | 4;
2148
2149
2150 /* GO bit for the EXEC register */
2151 dma_buffer->data.exec = 1;
2152 dma_buffer->data.clrfstatus = 0x00000020;
2153 dma_buffer->data.clrrstatus = 0x000000C0;
2154
2155 BUILD_BUG_ON(8 != ARRAY_SIZE(dma_buffer->data.flash_status));
2156
2157 for (n = 0; n < cwperpage ; n++) {
2158 /* status return words */
2159 dma_buffer->data.flash_status[n] = 0xeeeeeeee;
2160 /* block on cmd ready, then
2161 * write CMD / ADDR0 / ADDR1 / CHIPSEL regs in a burst
2162 */
2163 cmd->cmd = DST_CRCI_NAND_CMD;
2164 cmd->src =
2165 msm_virt_to_dma(chip, &dma_buffer->data.cmd);
2166 cmd->dst = MSM_NAND_FLASH_CMD;
2167 if (n == 0)
2168 cmd->len = 16;
2169 else
2170 cmd->len = 4;
2171 cmd++;
2172
2173 if (n == 0) {
2174 cmd->cmd = 0;
2175 cmd->src = msm_virt_to_dma(chip,
2176 &dma_buffer->data.cfg0);
2177 cmd->dst = MSM_NAND_DEV0_CFG0;
2178 if (enable_bch_ecc)
2179 cmd->len = 12;
2180 else
2181 cmd->len = 8;
2182 cmd++;
2183
2184 dma_buffer->data.ecccfg = chip->ecc_buf_cfg;
2185 cmd->cmd = 0;
2186 cmd->src = msm_virt_to_dma(chip,
2187 &dma_buffer->data.ecccfg);
2188 cmd->dst = MSM_NAND_EBI2_ECC_BUF_CFG;
2189 cmd->len = 4;
2190 cmd++;
2191 }
2192
2193 /* write data block */
2194 if (ops->mode != MTD_OOB_RAW)
2195 sectordatawritesize = (n < (cwperpage - 1)) ?
2196 516 : (512 - ((cwperpage - 1) << 2));
2197 else
2198 sectordatawritesize = chip->cw_size;
2199
2200 cmd->cmd = 0;
2201 cmd->src = data_dma_addr_curr;
2202 data_dma_addr_curr += sectordatawritesize;
2203 cmd->dst = MSM_NAND_FLASH_BUFFER;
2204 cmd->len = sectordatawritesize;
2205 cmd++;
2206
2207 if (ops->oobbuf) {
2208 if (n == (cwperpage - 1)) {
2209 cmd->cmd = 0;
2210 cmd->src = oob_dma_addr_curr;
2211 cmd->dst = MSM_NAND_FLASH_BUFFER +
2212 (512 - ((cwperpage - 1) << 2));
2213 if ((cwperpage << 2) < oob_len)
2214 cmd->len = (cwperpage << 2);
2215 else
2216 cmd->len = oob_len;
2217 oob_dma_addr_curr += cmd->len;
2218 oob_len -= cmd->len;
2219 if (cmd->len > 0)
2220 cmd++;
2221 }
2222 if (ops->mode != MTD_OOB_AUTO) {
2223 /* skip ecc bytes in oobbuf */
2224 if (oob_len < chip->ecc_parity_bytes) {
2225 oob_dma_addr_curr +=
2226 chip->ecc_parity_bytes;
2227 oob_len -=
2228 chip->ecc_parity_bytes;
2229 } else {
2230 oob_dma_addr_curr += oob_len;
2231 oob_len = 0;
2232 }
2233 }
2234 }
2235
2236 /* kick the execute register */
2237 cmd->cmd = 0;
2238 cmd->src =
2239 msm_virt_to_dma(chip, &dma_buffer->data.exec);
2240 cmd->dst = MSM_NAND_EXEC_CMD;
2241 cmd->len = 4;
2242 cmd++;
2243
2244 /* block on data ready, then
2245 * read the status register
2246 */
2247 cmd->cmd = SRC_CRCI_NAND_DATA;
2248 cmd->src = MSM_NAND_FLASH_STATUS;
2249 cmd->dst = msm_virt_to_dma(chip,
2250 &dma_buffer->data.flash_status[n]);
2251 cmd->len = 4;
2252 cmd++;
2253
2254 cmd->cmd = 0;
2255 cmd->src = msm_virt_to_dma(chip,
2256 &dma_buffer->data.clrfstatus);
2257 cmd->dst = MSM_NAND_FLASH_STATUS;
2258 cmd->len = 4;
2259 cmd++;
2260
2261 cmd->cmd = 0;
2262 cmd->src = msm_virt_to_dma(chip,
2263 &dma_buffer->data.clrrstatus);
2264 cmd->dst = MSM_NAND_READ_STATUS;
2265 cmd->len = 4;
2266 cmd++;
2267
2268 }
2269
2270 dma_buffer->cmd[0].cmd |= CMD_OCB;
2271 cmd[-1].cmd |= CMD_OCU | CMD_LC;
2272 BUILD_BUG_ON(8 * 7 + 2 != ARRAY_SIZE(dma_buffer->cmd));
2273 BUG_ON(cmd - dma_buffer->cmd > ARRAY_SIZE(dma_buffer->cmd));
2274 dma_buffer->cmdptr =
2275 (msm_virt_to_dma(chip, dma_buffer->cmd) >> 3) |
2276 CMD_PTR_LP;
2277
2278 mb();
2279 msm_dmov_exec_cmd(chip->dma_channel, crci_mask,
2280 DMOV_CMD_PTR_LIST | DMOV_CMD_ADDR(
2281 msm_virt_to_dma(chip, &dma_buffer->cmdptr)));
2282 mb();
2283
2284 /* if any of the writes failed (0x10), or there was a
2285 * protection violation (0x100), or the program success
2286 * bit (0x80) is unset, we lose
2287 */
2288 err = 0;
2289 for (n = 0; n < cwperpage; n++) {
2290 if (dma_buffer->data.flash_status[n] & 0x110) {
2291 err = -EIO;
2292 break;
2293 }
2294 if (!(dma_buffer->data.flash_status[n] & 0x80)) {
2295 err = -EIO;
2296 break;
2297 }
2298 }
2299
2300#if VERBOSE
2301 for (n = 0; n < cwperpage; n++)
2302 pr_info("write pg %d: flash_status[%d] = %x\n", page,
2303 n, dma_buffer->data.flash_status[n]);
2304
2305#endif
2306 if (err)
2307 break;
2308 pages_written++;
2309 page++;
2310 }
2311 if (ops->mode != MTD_OOB_RAW)
2312 ops->retlen = mtd->writesize * pages_written;
2313 else
2314 ops->retlen = (mtd->writesize + mtd->oobsize) * pages_written;
2315
2316 ops->oobretlen = ops->ooblen - oob_len;
2317
2318 msm_nand_release_dma_buffer(chip, dma_buffer, sizeof(*dma_buffer));
2319
2320 if (ops->oobbuf)
2321 dma_unmap_page(chip->dev, oob_dma_addr,
2322 ops->ooblen, DMA_TO_DEVICE);
2323err_dma_map_oobbuf_failed:
2324 if (ops->datbuf)
2325 dma_unmap_page(chip->dev, data_dma_addr, ops->len,
2326 DMA_TO_DEVICE);
2327 if (err)
2328 pr_err("msm_nand_write_oob %llx %x %x failed %d\n",
2329 to, ops->len, ops->ooblen, err);
2330
2331#if VERBOSE
2332 pr_info("\n%s: ret %d, retlen %d oobretlen %d\n",
2333 __func__, err, ops->retlen, ops->oobretlen);
2334
2335 pr_info("==================================================="
2336 "==============\n");
2337#endif
2338 return err;
2339}
2340
2341static int
2342msm_nand_write_oob_dualnandc(struct mtd_info *mtd, loff_t to,
2343 struct mtd_oob_ops *ops)
2344{
2345 struct msm_nand_chip *chip = mtd->priv;
2346 struct {
2347 dmov_s cmd[16 * 6 + 18];
2348 unsigned cmdptr;
2349 struct {
2350 uint32_t cmd;
2351 uint32_t nandc01_addr0;
2352 uint32_t nandc10_addr0;
2353 uint32_t nandc11_addr1;
2354 uint32_t chipsel_cs0;
2355 uint32_t chipsel_cs1;
2356 uint32_t cfg0;
2357 uint32_t cfg1;
2358 uint32_t eccbchcfg;
2359 uint32_t exec;
2360 uint32_t ecccfg;
2361 uint32_t cfg0_nc01;
2362 uint32_t ebi2_chip_select_cfg0;
2363 uint32_t adm_mux_data_ack_req_nc01;
2364 uint32_t adm_mux_cmd_ack_req_nc01;
2365 uint32_t adm_mux_data_ack_req_nc10;
2366 uint32_t adm_mux_cmd_ack_req_nc10;
2367 uint32_t adm_default_mux;
2368 uint32_t default_ebi2_chip_select_cfg0;
2369 uint32_t nc01_flash_dev_cmd_vld;
2370 uint32_t nc10_flash_dev_cmd0;
2371 uint32_t nc01_flash_dev_cmd_vld_default;
2372 uint32_t nc10_flash_dev_cmd0_default;
2373 uint32_t flash_status[16];
2374 uint32_t clrfstatus;
2375 uint32_t clrrstatus;
2376 } data;
2377 } *dma_buffer;
2378 dmov_s *cmd;
2379 unsigned n;
2380 unsigned page = 0;
2381 uint32_t oob_len;
2382 uint32_t sectordatawritesize;
2383 int err = 0;
2384 dma_addr_t data_dma_addr = 0;
2385 dma_addr_t oob_dma_addr = 0;
2386 dma_addr_t data_dma_addr_curr = 0;
2387 dma_addr_t oob_dma_addr_curr = 0;
2388 unsigned page_count;
2389 unsigned pages_written = 0;
2390 unsigned cwperpage;
2391 unsigned cw_offset = chip->cw_size;
2392#if VERBOSE
2393 pr_info("================================================="
2394 "============\n");
2395 pr_info("%s:\nto 0x%llx mode %d\ndatbuf 0x%p datlen 0x%x"
2396 "\noobbuf 0x%p ooblen 0x%x\n\n",
2397 __func__, to, ops->mode, ops->datbuf, ops->len,
2398 ops->oobbuf, ops->ooblen);
2399#endif
2400
2401 if (mtd->writesize == 2048)
2402 page = to >> 11;
2403
2404 if (mtd->writesize == 4096)
2405 page = to >> 12;
2406
2407 if (interleave_enable)
2408 page = (to >> 1) >> 12;
2409
2410 oob_len = ops->ooblen;
2411 cwperpage = (mtd->writesize >> 9);
2412
2413 if (to & (mtd->writesize - 1)) {
2414 pr_err("%s: unsupported to, 0x%llx\n", __func__, to);
2415 return -EINVAL;
2416 }
2417
2418 if (ops->mode != MTD_OOB_RAW) {
2419 if (ops->ooblen != 0 && ops->mode != MTD_OOB_AUTO) {
2420 pr_err("%s: unsupported ops->mode,%d\n",
2421 __func__, ops->mode);
2422 return -EINVAL;
2423 }
2424 if ((ops->len % mtd->writesize) != 0) {
2425 pr_err("%s: unsupported ops->len, %d\n",
2426 __func__, ops->len);
2427 return -EINVAL;
2428 }
2429 } else {
2430 if ((ops->len % (mtd->writesize + mtd->oobsize)) != 0) {
2431 pr_err("%s: unsupported ops->len, "
2432 "%d for MTD_OOB_RAW mode\n",
2433 __func__, ops->len);
2434 return -EINVAL;
2435 }
2436 }
2437
2438 if (ops->datbuf == NULL) {
2439 pr_err("%s: unsupported ops->datbuf == NULL\n", __func__);
2440 return -EINVAL;
2441 }
2442
2443 if (ops->mode != MTD_OOB_RAW && ops->ooblen != 0 && ops->ooboffs != 0) {
2444 pr_err("%s: unsupported ops->ooboffs, %d\n",
2445 __func__, ops->ooboffs);
2446 return -EINVAL;
2447 }
2448
2449 if (ops->datbuf) {
2450 data_dma_addr_curr = data_dma_addr =
2451 msm_nand_dma_map(chip->dev, ops->datbuf,
2452 ops->len, DMA_TO_DEVICE);
2453 if (dma_mapping_error(chip->dev, data_dma_addr)) {
2454 pr_err("msm_nand_write_oob_dualnandc:"
2455 "failed to get dma addr "
2456 "for %p\n", ops->datbuf);
2457 return -EIO;
2458 }
2459 }
2460 if (ops->oobbuf) {
2461 oob_dma_addr_curr = oob_dma_addr =
2462 msm_nand_dma_map(chip->dev, ops->oobbuf,
2463 ops->ooblen, DMA_TO_DEVICE);
2464 if (dma_mapping_error(chip->dev, oob_dma_addr)) {
2465 pr_err("msm_nand_write_oob_dualnandc:"
2466 "failed to get dma addr "
2467 "for %p\n", ops->oobbuf);
2468 err = -EIO;
2469 goto err_dma_map_oobbuf_failed;
2470 }
2471 }
2472 if (ops->mode != MTD_OOB_RAW)
2473 page_count = ops->len / mtd->writesize;
2474 else
2475 page_count = ops->len / (mtd->writesize + mtd->oobsize);
2476
2477 wait_event(chip->wait_queue, (dma_buffer =
2478 msm_nand_get_dma_buffer(chip, sizeof(*dma_buffer))));
2479
2480 if (chip->CFG1 & CFG1_WIDE_FLASH)
2481 cw_offset >>= 1;
2482
2483 dma_buffer->data.ebi2_chip_select_cfg0 = 0x00000805;
2484 dma_buffer->data.adm_mux_data_ack_req_nc01 = 0x00000A3C;
2485 dma_buffer->data.adm_mux_cmd_ack_req_nc01 = 0x0000053C;
2486 dma_buffer->data.adm_mux_data_ack_req_nc10 = 0x00000F28;
2487 dma_buffer->data.adm_mux_cmd_ack_req_nc10 = 0x00000F14;
2488 dma_buffer->data.adm_default_mux = 0x00000FC0;
2489 dma_buffer->data.default_ebi2_chip_select_cfg0 = 0x00000801;
2490 dma_buffer->data.nc01_flash_dev_cmd_vld = 0x9;
2491 dma_buffer->data.nc10_flash_dev_cmd0 = 0x1085D060;
2492 dma_buffer->data.nc01_flash_dev_cmd_vld_default = 0x1D;
2493 dma_buffer->data.nc10_flash_dev_cmd0_default = 0x1080D060;
2494 dma_buffer->data.clrfstatus = 0x00000020;
2495 dma_buffer->data.clrrstatus = 0x000000C0;
2496
2497 while (page_count-- > 0) {
2498 cmd = dma_buffer->cmd;
2499
2500 if (ops->mode != MTD_OOB_RAW) {
2501 dma_buffer->data.cfg0 = ((chip->CFG0 & ~(7U << 6))
2502 & ~(1 << 4)) | ((((cwperpage >> 1)-1)) << 6);
2503 dma_buffer->data.cfg1 = chip->CFG1;
2504 if (enable_bch_ecc)
2505 dma_buffer->data.eccbchcfg = chip->ecc_bch_cfg;
2506 } else {
2507 dma_buffer->data.cfg0 = ((chip->CFG0_RAW &
2508 ~(7U << 6)) & ~(1 << 4)) | (((cwperpage >> 1)-1) << 6);
2509 dma_buffer->data.cfg1 = chip->CFG1_RAW |
2510 (chip->CFG1 & CFG1_WIDE_FLASH);
2511 }
2512
2513 /* Disables the automatic issuing of the read
2514 * status command for first NAND controller.
2515 */
2516 if (!interleave_enable)
2517 dma_buffer->data.cfg0_nc01 = dma_buffer->data.cfg0
2518 | (1 << 4);
2519 else
2520 dma_buffer->data.cfg0 |= (1 << 4);
2521
2522 dma_buffer->data.cmd = MSM_NAND_CMD_PRG_PAGE;
2523 dma_buffer->data.chipsel_cs0 = (1<<4) | 4;
2524 dma_buffer->data.chipsel_cs1 = (1<<4) | 5;
2525
2526 /* GO bit for the EXEC register */
2527 dma_buffer->data.exec = 1;
2528
2529 if (!interleave_enable) {
2530 dma_buffer->data.nandc01_addr0 = (page << 16) | 0x0;
2531 /* NC10 ADDR0 points to the next code word */
2532 dma_buffer->data.nandc10_addr0 =
2533 (page << 16) | cw_offset;
2534 } else {
2535 dma_buffer->data.nandc01_addr0 =
2536 dma_buffer->data.nandc10_addr0 = (page << 16) | 0x0;
2537 }
2538 /* ADDR1 */
2539 dma_buffer->data.nandc11_addr1 = (page >> 16) & 0xff;
2540
2541 BUILD_BUG_ON(16 != ARRAY_SIZE(dma_buffer->data.flash_status));
2542
2543 for (n = 0; n < cwperpage; n++) {
2544 /* status return words */
2545 dma_buffer->data.flash_status[n] = 0xeeeeeeee;
2546
2547 if (n == 0) {
2548 if (!interleave_enable) {
2549 cmd->cmd = 0;
2550 cmd->src = msm_virt_to_dma(chip,
2551 &dma_buffer->
2552 data.nc01_flash_dev_cmd_vld);
2553 cmd->dst = NC01(MSM_NAND_DEV_CMD_VLD);
2554 cmd->len = 4;
2555 cmd++;
2556
2557 cmd->cmd = 0;
2558 cmd->src = msm_virt_to_dma(chip,
2559 &dma_buffer->data.nc10_flash_dev_cmd0);
2560 cmd->dst = NC10(MSM_NAND_DEV_CMD0);
2561 cmd->len = 4;
2562 cmd++;
2563
2564 /* common settings for both NC01 & NC10
2565 * NC01, NC10 --> ADDR1 / CHIPSEL
2566 */
2567 cmd->cmd = 0;
2568 cmd->src = msm_virt_to_dma(chip,
2569 &dma_buffer->data.nandc11_addr1);
2570 cmd->dst = NC11(MSM_NAND_ADDR1);
2571 cmd->len = 8;
2572 cmd++;
2573
2574 /* Disables the automatic issue of the
2575 * read status command after the write
2576 * operation.
2577 */
2578 cmd->cmd = 0;
2579 cmd->src = msm_virt_to_dma(chip,
2580 &dma_buffer->data.cfg0_nc01);
2581 cmd->dst = NC01(MSM_NAND_DEV0_CFG0);
2582 cmd->len = 4;
2583 cmd++;
2584
2585 cmd->cmd = 0;
2586 cmd->src = msm_virt_to_dma(chip,
2587 &dma_buffer->data.cfg0);
2588 cmd->dst = NC10(MSM_NAND_DEV0_CFG0);
2589 cmd->len = 4;
2590 cmd++;
2591
2592 cmd->cmd = 0;
2593 cmd->src = msm_virt_to_dma(chip,
2594 &dma_buffer->data.cfg1);
2595 cmd->dst = NC11(MSM_NAND_DEV0_CFG1);
2596 if (enable_bch_ecc)
2597 cmd->len = 8;
2598 else
2599 cmd->len = 4;
2600 cmd++;
2601 } else {
2602 /* enable CS1 */
2603 cmd->cmd = 0;
2604 cmd->src = msm_virt_to_dma(chip,
2605 &dma_buffer->
2606 data.ebi2_chip_select_cfg0);
2607 cmd->dst = EBI2_CHIP_SELECT_CFG0;
2608 cmd->len = 4;
2609 cmd++;
2610
2611 /* NC11 --> ADDR1 */
2612 cmd->cmd = 0;
2613 cmd->src = msm_virt_to_dma(chip,
2614 &dma_buffer->data.nandc11_addr1);
2615 cmd->dst = NC11(MSM_NAND_ADDR1);
2616 cmd->len = 4;
2617 cmd++;
2618
2619 /* Enable CS0 for NC01 */
2620 cmd->cmd = 0;
2621 cmd->src = msm_virt_to_dma(chip,
2622 &dma_buffer->data.chipsel_cs0);
2623 cmd->dst =
2624 NC01(MSM_NAND_FLASH_CHIP_SELECT);
2625 cmd->len = 4;
2626 cmd++;
2627
2628 /* Enable CS1 for NC10 */
2629 cmd->cmd = 0;
2630 cmd->src = msm_virt_to_dma(chip,
2631 &dma_buffer->data.chipsel_cs1);
2632 cmd->dst =
2633 NC10(MSM_NAND_FLASH_CHIP_SELECT);
2634 cmd->len = 4;
2635 cmd++;
2636
2637 /* config DEV0_CFG0 & CFG1 for CS0 */
2638 cmd->cmd = 0;
2639 cmd->src = msm_virt_to_dma(chip,
2640 &dma_buffer->data.cfg0);
2641 cmd->dst = NC01(MSM_NAND_DEV0_CFG0);
2642 cmd->len = 8;
2643 cmd++;
2644
2645 /* config DEV1_CFG0 & CFG1 for CS1 */
2646 cmd->cmd = 0;
2647 cmd->src = msm_virt_to_dma(chip,
2648 &dma_buffer->data.cfg0);
2649 cmd->dst = NC10(MSM_NAND_DEV1_CFG0);
2650 cmd->len = 8;
2651 cmd++;
2652 }
2653
2654 dma_buffer->data.ecccfg = chip->ecc_buf_cfg;
2655 cmd->cmd = 0;
2656 cmd->src = msm_virt_to_dma(chip,
2657 &dma_buffer->data.ecccfg);
2658 cmd->dst = NC11(MSM_NAND_EBI2_ECC_BUF_CFG);
2659 cmd->len = 4;
2660 cmd++;
2661
2662 /* NC01 --> ADDR0 */
2663 cmd->cmd = 0;
2664 cmd->src = msm_virt_to_dma(chip,
2665 &dma_buffer->data.nandc01_addr0);
2666 cmd->dst = NC01(MSM_NAND_ADDR0);
2667 cmd->len = 4;
2668 cmd++;
2669
2670 /* NC10 --> ADDR0 */
2671 cmd->cmd = 0;
2672 cmd->src = msm_virt_to_dma(chip,
2673 &dma_buffer->data.nandc10_addr0);
2674 cmd->dst = NC10(MSM_NAND_ADDR0);
2675 cmd->len = 4;
2676 cmd++;
2677 }
2678
2679 if (n % 2 == 0) {
2680 /* MASK CMD ACK/REQ --> NC10 (0xF14)*/
2681 cmd->cmd = 0;
2682 cmd->src = msm_virt_to_dma(chip,
2683 &dma_buffer->data.adm_mux_cmd_ack_req_nc10);
2684 cmd->dst = EBI2_NAND_ADM_MUX;
2685 cmd->len = 4;
2686 cmd++;
2687
2688 /* CMD */
2689 cmd->cmd = DST_CRCI_NAND_CMD;
2690 cmd->src = msm_virt_to_dma(chip,
2691 &dma_buffer->data.cmd);
2692 cmd->dst = NC01(MSM_NAND_FLASH_CMD);
2693 cmd->len = 4;
2694 cmd++;
2695 } else {
2696 /* MASK CMD ACK/REQ --> NC01 (0x53C)*/
2697 cmd->cmd = 0;
2698 cmd->src = msm_virt_to_dma(chip,
2699 &dma_buffer->data.adm_mux_cmd_ack_req_nc01);
2700 cmd->dst = EBI2_NAND_ADM_MUX;
2701 cmd->len = 4;
2702 cmd++;
2703
2704 /* CMD */
2705 cmd->cmd = DST_CRCI_NAND_CMD;
2706 cmd->src = msm_virt_to_dma(chip,
2707 &dma_buffer->data.cmd);
2708 cmd->dst = NC10(MSM_NAND_FLASH_CMD);
2709 cmd->len = 4;
2710 cmd++;
2711 }
2712
2713 if (ops->mode != MTD_OOB_RAW)
2714 sectordatawritesize = (n < (cwperpage - 1)) ?
2715 516 : (512 - ((cwperpage - 1) << 2));
2716 else
2717 sectordatawritesize = chip->cw_size;
2718
2719 cmd->cmd = 0;
2720 cmd->src = data_dma_addr_curr;
2721 data_dma_addr_curr += sectordatawritesize;
2722
2723 if (n % 2 == 0)
2724 cmd->dst = NC01(MSM_NAND_FLASH_BUFFER);
2725 else
2726 cmd->dst = NC10(MSM_NAND_FLASH_BUFFER);
2727 cmd->len = sectordatawritesize;
2728 cmd++;
2729
2730 if (ops->oobbuf) {
2731 if (n == (cwperpage - 1)) {
2732 cmd->cmd = 0;
2733 cmd->src = oob_dma_addr_curr;
2734 cmd->dst = NC10(MSM_NAND_FLASH_BUFFER) +
2735 (512 - ((cwperpage - 1) << 2));
2736 if ((cwperpage << 2) < oob_len)
2737 cmd->len = (cwperpage << 2);
2738 else
2739 cmd->len = oob_len;
2740 oob_dma_addr_curr += cmd->len;
2741 oob_len -= cmd->len;
2742 if (cmd->len > 0)
2743 cmd++;
2744 }
2745 if (ops->mode != MTD_OOB_AUTO) {
2746 /* skip ecc bytes in oobbuf */
2747 if (oob_len < chip->ecc_parity_bytes) {
2748 oob_dma_addr_curr +=
2749 chip->ecc_parity_bytes;
2750 oob_len -=
2751 chip->ecc_parity_bytes;
2752 } else {
2753 oob_dma_addr_curr += oob_len;
2754 oob_len = 0;
2755 }
2756 }
2757 }
2758
2759 if (n % 2 == 0) {
2760 if (n != 0) {
2761 /* MASK DATA ACK/REQ --> NC01 (0xA3C)*/
2762 cmd->cmd = 0;
2763 cmd->src = msm_virt_to_dma(chip,
2764 &dma_buffer->
2765 data.adm_mux_data_ack_req_nc01);
2766 cmd->dst = EBI2_NAND_ADM_MUX;
2767 cmd->len = 4;
2768 cmd++;
2769
2770 /* block on data ready from NC10, then
2771 * read the status register
2772 */
2773 cmd->cmd = SRC_CRCI_NAND_DATA;
2774 cmd->src = NC10(MSM_NAND_FLASH_STATUS);
2775 cmd->dst = msm_virt_to_dma(chip,
2776 &dma_buffer->data.flash_status[n-1]);
2777 cmd->len = 4;
2778 cmd++;
2779 }
2780 /* kick the NC01 execute register */
2781 cmd->cmd = 0;
2782 cmd->src = msm_virt_to_dma(chip,
2783 &dma_buffer->data.exec);
2784 cmd->dst = NC01(MSM_NAND_EXEC_CMD);
2785 cmd->len = 4;
2786 cmd++;
2787 } else {
2788 /* MASK DATA ACK/REQ --> NC10 (0xF28)*/
2789 cmd->cmd = 0;
2790 cmd->src = msm_virt_to_dma(chip,
2791 &dma_buffer->data.adm_mux_data_ack_req_nc10);
2792 cmd->dst = EBI2_NAND_ADM_MUX;
2793 cmd->len = 4;
2794 cmd++;
2795
2796 /* block on data ready from NC01, then
2797 * read the status register
2798 */
2799 cmd->cmd = SRC_CRCI_NAND_DATA;
2800 cmd->src = NC01(MSM_NAND_FLASH_STATUS);
2801 cmd->dst = msm_virt_to_dma(chip,
2802 &dma_buffer->data.flash_status[n-1]);
2803 cmd->len = 4;
2804 cmd++;
2805
2806 /* kick the execute register */
2807 cmd->cmd = 0;
2808 cmd->src =
2809 msm_virt_to_dma(chip, &dma_buffer->data.exec);
2810 cmd->dst = NC10(MSM_NAND_EXEC_CMD);
2811 cmd->len = 4;
2812 cmd++;
2813 }
2814 }
2815
2816 /* MASK DATA ACK/REQ --> NC01 (0xA3C)*/
2817 cmd->cmd = 0;
2818 cmd->src = msm_virt_to_dma(chip,
2819 &dma_buffer->data.adm_mux_data_ack_req_nc01);
2820 cmd->dst = EBI2_NAND_ADM_MUX;
2821 cmd->len = 4;
2822 cmd++;
2823
2824 /* we should process outstanding request */
2825 /* block on data ready, then
2826 * read the status register
2827 */
2828 cmd->cmd = SRC_CRCI_NAND_DATA;
2829 cmd->src = NC10(MSM_NAND_FLASH_STATUS);
2830 cmd->dst = msm_virt_to_dma(chip,
2831 &dma_buffer->data.flash_status[n-1]);
2832 cmd->len = 4;
2833 cmd++;
2834
2835 cmd->cmd = 0;
2836 cmd->src = msm_virt_to_dma(chip, &dma_buffer->data.clrfstatus);
2837 cmd->dst = NC11(MSM_NAND_FLASH_STATUS);
2838 cmd->len = 4;
2839 cmd++;
2840
2841 cmd->cmd = 0;
2842 cmd->src = msm_virt_to_dma(chip, &dma_buffer->data.clrrstatus);
2843 cmd->dst = NC11(MSM_NAND_READ_STATUS);
2844 cmd->len = 4;
2845 cmd++;
2846
2847 /* MASK DATA ACK/REQ --> NC01 (0xFC0)*/
2848 cmd->cmd = 0;
2849 cmd->src = msm_virt_to_dma(chip,
2850 &dma_buffer->data.adm_default_mux);
2851 cmd->dst = EBI2_NAND_ADM_MUX;
2852 cmd->len = 4;
2853 cmd++;
2854
2855 if (!interleave_enable) {
2856 /* setting to defalut values back */
2857 cmd->cmd = 0;
2858 cmd->src = msm_virt_to_dma(chip,
2859 &dma_buffer->data.nc01_flash_dev_cmd_vld_default);
2860 cmd->dst = NC01(MSM_NAND_DEV_CMD_VLD);
2861 cmd->len = 4;
2862 cmd++;
2863
2864 cmd->cmd = 0;
2865 cmd->src = msm_virt_to_dma(chip,
2866 &dma_buffer->data.nc10_flash_dev_cmd0_default);
2867 cmd->dst = NC10(MSM_NAND_DEV_CMD0);
2868 cmd->len = 4;
2869 cmd++;
2870 } else {
2871 /* disable CS1 */
2872 cmd->cmd = 0;
2873 cmd->src = msm_virt_to_dma(chip,
2874 &dma_buffer->data.default_ebi2_chip_select_cfg0);
2875 cmd->dst = EBI2_CHIP_SELECT_CFG0;
2876 cmd->len = 4;
2877 cmd++;
2878 }
2879
2880 dma_buffer->cmd[0].cmd |= CMD_OCB;
2881 cmd[-1].cmd |= CMD_OCU | CMD_LC;
2882 BUILD_BUG_ON(16 * 6 + 18 != ARRAY_SIZE(dma_buffer->cmd));
2883 BUG_ON(cmd - dma_buffer->cmd > ARRAY_SIZE(dma_buffer->cmd));
2884 dma_buffer->cmdptr =
2885 ((msm_virt_to_dma(chip, dma_buffer->cmd) >> 3) | CMD_PTR_LP);
2886
2887 mb();
2888 msm_dmov_exec_cmd(chip->dma_channel, crci_mask,
2889 DMOV_CMD_PTR_LIST | DMOV_CMD_ADDR(
2890 msm_virt_to_dma(chip, &dma_buffer->cmdptr)));
2891 mb();
2892
2893 /* if any of the writes failed (0x10), or there was a
2894 * protection violation (0x100), or the program success
2895 * bit (0x80) is unset, we lose
2896 */
2897 err = 0;
2898 for (n = 0; n < cwperpage; n++) {
2899 if (dma_buffer->data.flash_status[n] & 0x110) {
2900 err = -EIO;
2901 break;
2902 }
2903 if (!(dma_buffer->data.flash_status[n] & 0x80)) {
2904 err = -EIO;
2905 break;
2906 }
2907 }
2908 /* check for flash status busy for the last codeword */
2909 if (!interleave_enable)
2910 if (!(dma_buffer->data.flash_status[cwperpage - 1]
2911 & 0x20)) {
2912 err = -EIO;
2913 break;
2914 }
2915#if VERBOSE
2916 for (n = 0; n < cwperpage; n++) {
2917 if (n%2) {
2918 pr_info("NC10: write pg %d: flash_status[%d] = %x\n",
2919 page, n, dma_buffer->data.flash_status[n]);
2920 } else {
2921 pr_info("NC01: write pg %d: flash_status[%d] = %x\n",
2922 page, n, dma_buffer->data.flash_status[n]);
2923 }
2924 }
2925#endif
2926 if (err)
2927 break;
2928 pages_written++;
2929 page++;
2930 }
2931 if (ops->mode != MTD_OOB_RAW)
2932 ops->retlen = mtd->writesize * pages_written;
2933 else
2934 ops->retlen = (mtd->writesize + mtd->oobsize) * pages_written;
2935
2936 ops->oobretlen = ops->ooblen - oob_len;
2937
2938 msm_nand_release_dma_buffer(chip, dma_buffer, sizeof(*dma_buffer));
2939
2940 if (ops->oobbuf)
2941 dma_unmap_page(chip->dev, oob_dma_addr,
2942 ops->ooblen, DMA_TO_DEVICE);
2943err_dma_map_oobbuf_failed:
2944 if (ops->datbuf)
2945 dma_unmap_page(chip->dev, data_dma_addr, ops->len,
2946 DMA_TO_DEVICE);
2947 if (err)
2948 pr_err("msm_nand_write_oob_dualnandc %llx %x %x failed %d\n",
2949 to, ops->len, ops->ooblen, err);
2950
2951#if VERBOSE
2952 pr_info("\n%s: ret %d, retlen %d oobretlen %d\n",
2953 __func__, err, ops->retlen, ops->oobretlen);
2954
2955 pr_info("==================================================="
2956 "==========\n");
2957#endif
2958 return err;
2959}
2960
2961static int msm_nand_write(struct mtd_info *mtd, loff_t to, size_t len,
2962 size_t *retlen, const u_char *buf)
2963{
2964 int ret;
2965 struct mtd_oob_ops ops;
2966
2967 ops.mode = MTD_OOB_PLACE;
2968 ops.len = len;
2969 ops.retlen = 0;
2970 ops.ooblen = 0;
2971 ops.datbuf = (uint8_t *)buf;
2972 ops.oobbuf = NULL;
2973 if (!dual_nand_ctlr_present)
2974 ret = msm_nand_write_oob(mtd, to, &ops);
2975 else
2976 ret = msm_nand_write_oob_dualnandc(mtd, to, &ops);
2977 *retlen = ops.retlen;
2978 return ret;
2979}
2980
2981static int
2982msm_nand_erase(struct mtd_info *mtd, struct erase_info *instr)
2983{
2984 int err;
2985 struct msm_nand_chip *chip = mtd->priv;
2986 struct {
2987 dmov_s cmd[6];
2988 unsigned cmdptr;
2989 struct {
2990 uint32_t cmd;
2991 uint32_t addr0;
2992 uint32_t addr1;
2993 uint32_t chipsel;
2994 uint32_t cfg0;
2995 uint32_t cfg1;
2996 uint32_t exec;
2997 uint32_t flash_status;
2998 uint32_t clrfstatus;
2999 uint32_t clrrstatus;
3000 } data;
3001 } *dma_buffer;
3002 dmov_s *cmd;
3003 unsigned page = 0;
3004
3005 if (mtd->writesize == 2048)
3006 page = instr->addr >> 11;
3007
3008 if (mtd->writesize == 4096)
3009 page = instr->addr >> 12;
3010
3011 if (instr->addr & (mtd->erasesize - 1)) {
3012 pr_err("%s: unsupported erase address, 0x%llx\n",
3013 __func__, instr->addr);
3014 return -EINVAL;
3015 }
3016 if (instr->len != mtd->erasesize) {
3017 pr_err("%s: unsupported erase len, %lld\n",
3018 __func__, instr->len);
3019 return -EINVAL;
3020 }
3021
3022 wait_event(chip->wait_queue,
3023 (dma_buffer = msm_nand_get_dma_buffer(
3024 chip, sizeof(*dma_buffer))));
3025
3026 cmd = dma_buffer->cmd;
3027
3028 dma_buffer->data.cmd = MSM_NAND_CMD_BLOCK_ERASE;
3029 dma_buffer->data.addr0 = page;
3030 dma_buffer->data.addr1 = 0;
3031 dma_buffer->data.chipsel = 0 | 4;
3032 dma_buffer->data.exec = 1;
3033 dma_buffer->data.flash_status = 0xeeeeeeee;
3034 dma_buffer->data.cfg0 = chip->CFG0 & (~(7 << 6)); /* CW_PER_PAGE = 0 */
3035 dma_buffer->data.cfg1 = chip->CFG1;
3036 dma_buffer->data.clrfstatus = 0x00000020;
3037 dma_buffer->data.clrrstatus = 0x000000C0;
3038
3039 cmd->cmd = DST_CRCI_NAND_CMD | CMD_OCB;
3040 cmd->src = msm_virt_to_dma(chip, &dma_buffer->data.cmd);
3041 cmd->dst = MSM_NAND_FLASH_CMD;
3042 cmd->len = 16;
3043 cmd++;
3044
3045 cmd->cmd = 0;
3046 cmd->src = msm_virt_to_dma(chip, &dma_buffer->data.cfg0);
3047 cmd->dst = MSM_NAND_DEV0_CFG0;
3048 cmd->len = 8;
3049 cmd++;
3050
3051 cmd->cmd = 0;
3052 cmd->src = msm_virt_to_dma(chip, &dma_buffer->data.exec);
3053 cmd->dst = MSM_NAND_EXEC_CMD;
3054 cmd->len = 4;
3055 cmd++;
3056
3057 cmd->cmd = SRC_CRCI_NAND_DATA;
3058 cmd->src = MSM_NAND_FLASH_STATUS;
3059 cmd->dst = msm_virt_to_dma(chip, &dma_buffer->data.flash_status);
3060 cmd->len = 4;
3061 cmd++;
3062
3063 cmd->cmd = 0;
3064 cmd->src = msm_virt_to_dma(chip, &dma_buffer->data.clrfstatus);
3065 cmd->dst = MSM_NAND_FLASH_STATUS;
3066 cmd->len = 4;
3067 cmd++;
3068
3069 cmd->cmd = CMD_OCU | CMD_LC;
3070 cmd->src = msm_virt_to_dma(chip, &dma_buffer->data.clrrstatus);
3071 cmd->dst = MSM_NAND_READ_STATUS;
3072 cmd->len = 4;
3073 cmd++;
3074
3075 BUILD_BUG_ON(5 != ARRAY_SIZE(dma_buffer->cmd) - 1);
3076 BUG_ON(cmd - dma_buffer->cmd > ARRAY_SIZE(dma_buffer->cmd));
3077 dma_buffer->cmdptr =
3078 (msm_virt_to_dma(chip, dma_buffer->cmd) >> 3) | CMD_PTR_LP;
3079
3080 mb();
3081 msm_dmov_exec_cmd(
3082 chip->dma_channel, crci_mask, DMOV_CMD_PTR_LIST |
3083 DMOV_CMD_ADDR(msm_virt_to_dma(chip, &dma_buffer->cmdptr)));
3084 mb();
3085
3086 /* we fail if there was an operation error, a mpu error, or the
3087 * erase success bit was not set.
3088 */
3089
3090 if (dma_buffer->data.flash_status & 0x110 ||
3091 !(dma_buffer->data.flash_status & 0x80))
3092 err = -EIO;
3093 else
3094 err = 0;
3095
3096 msm_nand_release_dma_buffer(chip, dma_buffer, sizeof(*dma_buffer));
3097 if (err) {
3098 pr_err("%s: erase failed, 0x%llx\n", __func__, instr->addr);
3099 instr->fail_addr = instr->addr;
3100 instr->state = MTD_ERASE_FAILED;
3101 } else {
3102 instr->state = MTD_ERASE_DONE;
3103 instr->fail_addr = 0xffffffff;
3104 mtd_erase_callback(instr);
3105 }
3106 return err;
3107}
3108
3109static int
3110msm_nand_erase_dualnandc(struct mtd_info *mtd, struct erase_info *instr)
3111{
3112 int err;
3113 struct msm_nand_chip *chip = mtd->priv;
3114 struct {
3115 dmov_s cmd[18];
3116 unsigned cmdptr;
3117 struct {
3118 uint32_t cmd;
3119 uint32_t addr0;
3120 uint32_t addr1;
3121 uint32_t chipsel_cs0;
3122 uint32_t chipsel_cs1;
3123 uint32_t cfg0;
3124 uint32_t cfg1;
3125 uint32_t exec;
3126 uint32_t ecccfg;
3127 uint32_t ebi2_chip_select_cfg0;
3128 uint32_t adm_mux_data_ack_req_nc01;
3129 uint32_t adm_mux_cmd_ack_req_nc01;
3130 uint32_t adm_mux_data_ack_req_nc10;
3131 uint32_t adm_mux_cmd_ack_req_nc10;
3132 uint32_t adm_default_mux;
3133 uint32_t default_ebi2_chip_select_cfg0;
3134 uint32_t nc01_flash_dev_cmd0;
3135 uint32_t nc01_flash_dev_cmd0_default;
3136 uint32_t flash_status[2];
3137 uint32_t clrfstatus;
3138 uint32_t clrrstatus;
3139 } data;
3140 } *dma_buffer;
3141 dmov_s *cmd;
3142 unsigned page = 0;
3143
3144 if (mtd->writesize == 2048)
3145 page = instr->addr >> 11;
3146
3147 if (mtd->writesize == 4096)
3148 page = instr->addr >> 12;
3149
3150 if (mtd->writesize == 8192)
3151 page = (instr->addr >> 1) >> 12;
3152
3153 if (instr->addr & (mtd->erasesize - 1)) {
3154 pr_err("%s: unsupported erase address, 0x%llx\n",
3155 __func__, instr->addr);
3156 return -EINVAL;
3157 }
3158 if (instr->len != mtd->erasesize) {
3159 pr_err("%s: unsupported erase len, %lld\n",
3160 __func__, instr->len);
3161 return -EINVAL;
3162 }
3163
3164 wait_event(chip->wait_queue,
3165 (dma_buffer = msm_nand_get_dma_buffer(
3166 chip, sizeof(*dma_buffer))));
3167
3168 cmd = dma_buffer->cmd;
3169
3170 dma_buffer->data.cmd = MSM_NAND_CMD_BLOCK_ERASE;
3171 dma_buffer->data.addr0 = page;
3172 dma_buffer->data.addr1 = 0;
3173 dma_buffer->data.chipsel_cs0 = (1<<4) | 4;
3174 dma_buffer->data.chipsel_cs1 = (1<<4) | 5;
3175 dma_buffer->data.exec = 1;
3176 dma_buffer->data.flash_status[0] = 0xeeeeeeee;
3177 dma_buffer->data.flash_status[1] = 0xeeeeeeee;
3178 dma_buffer->data.cfg0 = chip->CFG0 & (~(7 << 6)); /* CW_PER_PAGE = 0 */
3179 dma_buffer->data.cfg1 = chip->CFG1;
3180 dma_buffer->data.clrfstatus = 0x00000020;
3181 dma_buffer->data.clrrstatus = 0x000000C0;
3182
3183 dma_buffer->data.ebi2_chip_select_cfg0 = 0x00000805;
3184 dma_buffer->data.adm_mux_data_ack_req_nc01 = 0x00000A3C;
3185 dma_buffer->data.adm_mux_cmd_ack_req_nc01 = 0x0000053C;
3186 dma_buffer->data.adm_mux_data_ack_req_nc10 = 0x00000F28;
3187 dma_buffer->data.adm_mux_cmd_ack_req_nc10 = 0x00000F14;
3188 dma_buffer->data.adm_default_mux = 0x00000FC0;
3189 dma_buffer->data.default_ebi2_chip_select_cfg0 = 0x00000801;
3190
3191 /* enable CS1 */
3192 cmd->cmd = 0 | CMD_OCB;
3193 cmd->src = msm_virt_to_dma(chip,
3194 &dma_buffer->data.ebi2_chip_select_cfg0);
3195 cmd->dst = EBI2_CHIP_SELECT_CFG0;
3196 cmd->len = 4;
3197 cmd++;
3198
3199 /* erase CS0 block now !!! */
3200 /* 0xF14 */
3201 cmd->cmd = 0;
3202 cmd->src = msm_virt_to_dma(chip,
3203 &dma_buffer->data.adm_mux_cmd_ack_req_nc10);
3204 cmd->dst = EBI2_NAND_ADM_MUX;
3205 cmd->len = 4;
3206 cmd++;
3207
3208 cmd->cmd = DST_CRCI_NAND_CMD;
3209 cmd->src = msm_virt_to_dma(chip, &dma_buffer->data.cmd);
3210 cmd->dst = NC01(MSM_NAND_FLASH_CMD);
3211 cmd->len = 16;
3212 cmd++;
3213
3214 cmd->cmd = 0;
3215 cmd->src = msm_virt_to_dma(chip, &dma_buffer->data.cfg0);
3216 cmd->dst = NC01(MSM_NAND_DEV0_CFG0);
3217 cmd->len = 8;
3218 cmd++;
3219
3220 cmd->cmd = 0;
3221 cmd->src = msm_virt_to_dma(chip, &dma_buffer->data.exec);
3222 cmd->dst = NC01(MSM_NAND_EXEC_CMD);
3223 cmd->len = 4;
3224 cmd++;
3225
3226 /* 0xF28 */
3227 cmd->cmd = 0;
3228 cmd->src = msm_virt_to_dma(chip,
3229 &dma_buffer->data.adm_mux_data_ack_req_nc10);
3230 cmd->dst = EBI2_NAND_ADM_MUX;
3231 cmd->len = 4;
3232 cmd++;
3233
3234 cmd->cmd = SRC_CRCI_NAND_DATA;
3235 cmd->src = NC01(MSM_NAND_FLASH_STATUS);
3236 cmd->dst = msm_virt_to_dma(chip, &dma_buffer->data.flash_status[0]);
3237 cmd->len = 4;
3238 cmd++;
3239
3240 /* erase CS1 block now !!! */
3241 /* 0x53C */
3242 cmd->cmd = 0;
3243 cmd->src = msm_virt_to_dma(chip,
3244 &dma_buffer->data.adm_mux_cmd_ack_req_nc01);
3245 cmd->dst = EBI2_NAND_ADM_MUX;
3246 cmd->len = 4;
3247 cmd++;
3248
3249 cmd->cmd = DST_CRCI_NAND_CMD;
3250 cmd->src = msm_virt_to_dma(chip, &dma_buffer->data.cmd);
3251 cmd->dst = NC10(MSM_NAND_FLASH_CMD);
3252 cmd->len = 12;
3253 cmd++;
3254
3255 cmd->cmd = 0;
3256 cmd->src = msm_virt_to_dma(chip, &dma_buffer->data.chipsel_cs1);
3257 cmd->dst = NC10(MSM_NAND_FLASH_CHIP_SELECT);
3258 cmd->len = 4;
3259 cmd++;
3260
3261 cmd->cmd = 0;
3262 cmd->src = msm_virt_to_dma(chip, &dma_buffer->data.cfg0);
3263 cmd->dst = NC10(MSM_NAND_DEV1_CFG0);
3264 cmd->len = 8;
3265
3266 cmd->cmd = 0;
3267 cmd->src = msm_virt_to_dma(chip, &dma_buffer->data.exec);
3268 cmd->dst = NC10(MSM_NAND_EXEC_CMD);
3269 cmd->len = 4;
3270 cmd++;
3271
3272 /* 0xA3C */
3273 cmd->cmd = 0;
3274 cmd->src = msm_virt_to_dma(chip,
3275 &dma_buffer->data.adm_mux_data_ack_req_nc01);
3276 cmd->dst = EBI2_NAND_ADM_MUX;
3277 cmd->len = 4;
3278 cmd++;
3279
3280 cmd->cmd = SRC_CRCI_NAND_DATA;
3281 cmd->src = NC10(MSM_NAND_FLASH_STATUS);
3282 cmd->dst = msm_virt_to_dma(chip, &dma_buffer->data.flash_status[1]);
3283 cmd->len = 4;
3284 cmd++;
3285
3286 cmd->cmd = 0;
3287 cmd->src = msm_virt_to_dma(chip, &dma_buffer->data.clrfstatus);
3288 cmd->dst = NC11(MSM_NAND_FLASH_STATUS);
3289 cmd->len = 4;
3290 cmd++;
3291
3292 cmd->cmd = 0;
3293 cmd->src = msm_virt_to_dma(chip, &dma_buffer->data.clrrstatus);
3294 cmd->dst = NC11(MSM_NAND_READ_STATUS);
3295 cmd->len = 4;
3296 cmd++;
3297
3298 cmd->cmd = 0;
3299 cmd->src = msm_virt_to_dma(chip,
3300 &dma_buffer->data.adm_default_mux);
3301 cmd->dst = EBI2_NAND_ADM_MUX;
3302 cmd->len = 4;
3303 cmd++;
3304
3305 /* disable CS1 */
3306 cmd->cmd = CMD_OCU | CMD_LC;
3307 cmd->src = msm_virt_to_dma(chip,
3308 &dma_buffer->data.default_ebi2_chip_select_cfg0);
3309 cmd->dst = EBI2_CHIP_SELECT_CFG0;
3310 cmd->len = 4;
3311 cmd++;
3312
3313 BUILD_BUG_ON(17 != ARRAY_SIZE(dma_buffer->cmd) - 1);
3314 BUG_ON(cmd - dma_buffer->cmd > ARRAY_SIZE(dma_buffer->cmd));
3315
3316 dma_buffer->cmdptr =
3317 (msm_virt_to_dma(chip, dma_buffer->cmd) >> 3) | CMD_PTR_LP;
3318
3319 mb();
3320 msm_dmov_exec_cmd(
3321 chip->dma_channel, crci_mask, DMOV_CMD_PTR_LIST |
3322 DMOV_CMD_ADDR(msm_virt_to_dma(chip, &dma_buffer->cmdptr)));
3323 mb();
3324
3325 /* we fail if there was an operation error, a mpu error, or the
3326 * erase success bit was not set.
3327 */
3328
3329 if (dma_buffer->data.flash_status[0] & 0x110 ||
3330 !(dma_buffer->data.flash_status[0] & 0x80) ||
3331 dma_buffer->data.flash_status[1] & 0x110 ||
3332 !(dma_buffer->data.flash_status[1] & 0x80))
3333 err = -EIO;
3334 else
3335 err = 0;
3336
3337 msm_nand_release_dma_buffer(chip, dma_buffer, sizeof(*dma_buffer));
3338 if (err) {
3339 pr_err("%s: erase failed, 0x%llx\n", __func__, instr->addr);
3340 instr->fail_addr = instr->addr;
3341 instr->state = MTD_ERASE_FAILED;
3342 } else {
3343 instr->state = MTD_ERASE_DONE;
3344 instr->fail_addr = 0xffffffff;
3345 mtd_erase_callback(instr);
3346 }
3347 return err;
3348}
3349
3350static int
3351msm_nand_block_isbad(struct mtd_info *mtd, loff_t ofs)
3352{
3353 struct msm_nand_chip *chip = mtd->priv;
3354 int ret;
3355 struct {
3356 dmov_s cmd[5];
3357 unsigned cmdptr;
3358 struct {
3359 uint32_t cmd;
3360 uint32_t addr0;
3361 uint32_t addr1;
3362 uint32_t chipsel;
3363 uint32_t cfg0;
3364 uint32_t cfg1;
3365 uint32_t eccbchcfg;
3366 uint32_t exec;
3367 uint32_t ecccfg;
3368 struct {
3369 uint32_t flash_status;
3370 uint32_t buffer_status;
3371 } result;
3372 } data;
3373 } *dma_buffer;
3374 dmov_s *cmd;
3375 uint8_t *buf;
3376 unsigned page = 0;
3377 unsigned cwperpage;
3378
3379 if (mtd->writesize == 2048)
3380 page = ofs >> 11;
3381
3382 if (mtd->writesize == 4096)
3383 page = ofs >> 12;
3384
3385 cwperpage = (mtd->writesize >> 9);
3386
3387 /* Check for invalid offset */
3388 if (ofs > mtd->size)
3389 return -EINVAL;
3390 if (ofs & (mtd->erasesize - 1)) {
3391 pr_err("%s: unsupported block address, 0x%x\n",
3392 __func__, (uint32_t)ofs);
3393 return -EINVAL;
3394 }
3395
3396 wait_event(chip->wait_queue,
3397 (dma_buffer = msm_nand_get_dma_buffer(chip ,
3398 sizeof(*dma_buffer) + 4)));
3399 buf = (uint8_t *)dma_buffer + sizeof(*dma_buffer);
3400
3401 /* Read 4 bytes starting from the bad block marker location
3402 * in the last code word of the page
3403 */
3404
3405 cmd = dma_buffer->cmd;
3406
3407 dma_buffer->data.cmd = MSM_NAND_CMD_PAGE_READ;
3408 dma_buffer->data.cfg0 = chip->CFG0_RAW & ~(7U << 6);
3409 dma_buffer->data.cfg1 = chip->CFG1_RAW |
3410 (chip->CFG1 & CFG1_WIDE_FLASH);
3411 if (enable_bch_ecc)
3412 dma_buffer->data.eccbchcfg = chip->ecc_bch_cfg;
3413
3414 if (chip->CFG1 & CFG1_WIDE_FLASH)
3415 dma_buffer->data.addr0 = (page << 16) |
3416 ((chip->cw_size * (cwperpage-1)) >> 1);
3417 else
3418 dma_buffer->data.addr0 = (page << 16) |
3419 (chip->cw_size * (cwperpage-1));
3420
3421 dma_buffer->data.addr1 = (page >> 16) & 0xff;
3422 dma_buffer->data.chipsel = 0 | 4;
3423
3424 dma_buffer->data.exec = 1;
3425
3426 dma_buffer->data.result.flash_status = 0xeeeeeeee;
3427 dma_buffer->data.result.buffer_status = 0xeeeeeeee;
3428
3429 cmd->cmd = DST_CRCI_NAND_CMD;
3430 cmd->src = msm_virt_to_dma(chip, &dma_buffer->data.cmd);
3431 cmd->dst = MSM_NAND_FLASH_CMD;
3432 cmd->len = 16;
3433 cmd++;
3434
3435 cmd->cmd = 0;
3436 cmd->src = msm_virt_to_dma(chip, &dma_buffer->data.cfg0);
3437 cmd->dst = MSM_NAND_DEV0_CFG0;
3438 if (enable_bch_ecc)
3439 cmd->len = 12;
3440 else
3441 cmd->len = 8;
3442 cmd++;
3443
3444 cmd->cmd = 0;
3445 cmd->src = msm_virt_to_dma(chip, &dma_buffer->data.exec);
3446 cmd->dst = MSM_NAND_EXEC_CMD;
3447 cmd->len = 4;
3448 cmd++;
3449
3450 cmd->cmd = SRC_CRCI_NAND_DATA;
3451 cmd->src = MSM_NAND_FLASH_STATUS;
3452 cmd->dst = msm_virt_to_dma(chip, &dma_buffer->data.result);
3453 cmd->len = 8;
3454 cmd++;
3455
3456 cmd->cmd = 0;
3457 cmd->src = MSM_NAND_FLASH_BUFFER +
3458 (mtd->writesize - (chip->cw_size * (cwperpage-1)));
3459 cmd->dst = msm_virt_to_dma(chip, buf);
3460 cmd->len = 4;
3461 cmd++;
3462
3463 BUILD_BUG_ON(5 != ARRAY_SIZE(dma_buffer->cmd));
3464 BUG_ON(cmd - dma_buffer->cmd > ARRAY_SIZE(dma_buffer->cmd));
3465 dma_buffer->cmd[0].cmd |= CMD_OCB;
3466 cmd[-1].cmd |= CMD_OCU | CMD_LC;
3467
3468 dma_buffer->cmdptr = (msm_virt_to_dma(chip,
3469 dma_buffer->cmd) >> 3) | CMD_PTR_LP;
3470
3471 mb();
3472 msm_dmov_exec_cmd(chip->dma_channel, crci_mask, DMOV_CMD_PTR_LIST |
3473 DMOV_CMD_ADDR(msm_virt_to_dma(chip, &dma_buffer->cmdptr)));
3474 mb();
3475
3476 ret = 0;
3477 if (dma_buffer->data.result.flash_status & 0x110)
3478 ret = -EIO;
3479
3480 if (!ret) {
3481 /* Check for bad block marker byte */
3482 if (chip->CFG1 & CFG1_WIDE_FLASH) {
3483 if (buf[0] != 0xFF || buf[1] != 0xFF)
3484 ret = 1;
3485 } else {
3486 if (buf[0] != 0xFF)
3487 ret = 1;
3488 }
3489 }
3490
3491 msm_nand_release_dma_buffer(chip, dma_buffer, sizeof(*dma_buffer) + 4);
3492 return ret;
3493}
3494
3495static int
3496msm_nand_block_isbad_dualnandc(struct mtd_info *mtd, loff_t ofs)
3497{
3498 struct msm_nand_chip *chip = mtd->priv;
3499 int ret;
3500 struct {
3501 dmov_s cmd[18];
3502 unsigned cmdptr;
3503 struct {
3504 uint32_t cmd;
3505 uint32_t addr0;
3506 uint32_t addr1;
3507 uint32_t chipsel_cs0;
3508 uint32_t chipsel_cs1;
3509 uint32_t cfg0;
3510 uint32_t cfg1;
3511 uint32_t exec;
3512 uint32_t ecccfg;
3513 uint32_t ebi2_chip_select_cfg0;
3514 uint32_t adm_mux_data_ack_req_nc01;
3515 uint32_t adm_mux_cmd_ack_req_nc01;
3516 uint32_t adm_mux_data_ack_req_nc10;
3517 uint32_t adm_mux_cmd_ack_req_nc10;
3518 uint32_t adm_default_mux;
3519 uint32_t default_ebi2_chip_select_cfg0;
3520 struct {
3521 uint32_t flash_status;
3522 uint32_t buffer_status;
3523 } result[2];
3524 } data;
3525 } *dma_buffer;
3526 dmov_s *cmd;
3527 uint8_t *buf01;
3528 uint8_t *buf10;
3529 unsigned page = 0;
3530 unsigned cwperpage;
3531
3532 if (mtd->writesize == 2048)
3533 page = ofs >> 11;
3534
3535 if (mtd->writesize == 4096)
3536 page = ofs >> 12;
3537
3538 if (mtd->writesize == 8192)
3539 page = (ofs >> 1) >> 12;
3540
3541 cwperpage = ((mtd->writesize >> 1) >> 9);
3542
3543 /* Check for invalid offset */
3544 if (ofs > mtd->size)
3545 return -EINVAL;
3546 if (ofs & (mtd->erasesize - 1)) {
3547 pr_err("%s: unsupported block address, 0x%x\n",
3548 __func__, (uint32_t)ofs);
3549 return -EINVAL;
3550 }
3551
3552 wait_event(chip->wait_queue,
3553 (dma_buffer = msm_nand_get_dma_buffer(chip ,
3554 sizeof(*dma_buffer) + 8)));
3555 buf01 = (uint8_t *)dma_buffer + sizeof(*dma_buffer);
3556 buf10 = buf01 + 4;
3557
3558 /* Read 4 bytes starting from the bad block marker location
3559 * in the last code word of the page
3560 */
3561 cmd = dma_buffer->cmd;
3562
3563 dma_buffer->data.cmd = MSM_NAND_CMD_PAGE_READ;
3564 dma_buffer->data.cfg0 = chip->CFG0_RAW & ~(7U << 6);
3565 dma_buffer->data.cfg1 = chip->CFG1_RAW |
3566 (chip->CFG1 & CFG1_WIDE_FLASH);
3567
3568 if (chip->CFG1 & CFG1_WIDE_FLASH)
3569 dma_buffer->data.addr0 = (page << 16) |
3570 ((528*(cwperpage-1)) >> 1);
3571 else
3572 dma_buffer->data.addr0 = (page << 16) |
3573 (528*(cwperpage-1));
3574
3575 dma_buffer->data.addr1 = (page >> 16) & 0xff;
3576 dma_buffer->data.chipsel_cs0 = (1<<4) | 4;
3577 dma_buffer->data.chipsel_cs1 = (1<<4) | 5;
3578
3579 dma_buffer->data.exec = 1;
3580
3581 dma_buffer->data.result[0].flash_status = 0xeeeeeeee;
3582 dma_buffer->data.result[0].buffer_status = 0xeeeeeeee;
3583 dma_buffer->data.result[1].flash_status = 0xeeeeeeee;
3584 dma_buffer->data.result[1].buffer_status = 0xeeeeeeee;
3585
3586 dma_buffer->data.ebi2_chip_select_cfg0 = 0x00000805;
3587 dma_buffer->data.adm_mux_data_ack_req_nc01 = 0x00000A3C;
3588 dma_buffer->data.adm_mux_cmd_ack_req_nc01 = 0x0000053C;
3589 dma_buffer->data.adm_mux_data_ack_req_nc10 = 0x00000F28;
3590 dma_buffer->data.adm_mux_cmd_ack_req_nc10 = 0x00000F14;
3591 dma_buffer->data.adm_default_mux = 0x00000FC0;
3592 dma_buffer->data.default_ebi2_chip_select_cfg0 = 0x00000801;
3593
3594 /* Reading last code word from NC01 */
3595 /* enable CS1 */
3596 cmd->cmd = 0;
3597 cmd->src = msm_virt_to_dma(chip,
3598 &dma_buffer->data.ebi2_chip_select_cfg0);
3599 cmd->dst = EBI2_CHIP_SELECT_CFG0;
3600 cmd->len = 4;
3601 cmd++;
3602
3603 /* 0xF14 */
3604 cmd->cmd = 0;
3605 cmd->src = msm_virt_to_dma(chip,
3606 &dma_buffer->data.adm_mux_cmd_ack_req_nc10);
3607 cmd->dst = EBI2_NAND_ADM_MUX;
3608 cmd->len = 4;
3609 cmd++;
3610
3611 cmd->cmd = DST_CRCI_NAND_CMD;
3612 cmd->src = msm_virt_to_dma(chip, &dma_buffer->data.cmd);
3613 cmd->dst = NC01(MSM_NAND_FLASH_CMD);
3614 cmd->len = 16;
3615 cmd++;
3616
3617 cmd->cmd = 0;
3618 cmd->src = msm_virt_to_dma(chip, &dma_buffer->data.cfg0);
3619 cmd->dst = NC01(MSM_NAND_DEV0_CFG0);
3620 cmd->len = 8;
3621 cmd++;
3622
3623 cmd->cmd = 0;
3624 cmd->src = msm_virt_to_dma(chip, &dma_buffer->data.exec);
3625 cmd->dst = NC01(MSM_NAND_EXEC_CMD);
3626 cmd->len = 4;
3627 cmd++;
3628
3629 /* 0xF28 */
3630 cmd->cmd = 0;
3631 cmd->src = msm_virt_to_dma(chip,
3632 &dma_buffer->data.adm_mux_data_ack_req_nc10);
3633 cmd->dst = EBI2_NAND_ADM_MUX;
3634 cmd->len = 4;
3635 cmd++;
3636
3637 cmd->cmd = SRC_CRCI_NAND_DATA;
3638 cmd->src = NC01(MSM_NAND_FLASH_STATUS);
3639 cmd->dst = msm_virt_to_dma(chip, &dma_buffer->data.result[0]);
3640 cmd->len = 8;
3641 cmd++;
3642
3643 cmd->cmd = 0;
3644 cmd->src = NC01(MSM_NAND_FLASH_BUFFER) + ((mtd->writesize >> 1) -
3645 (528*(cwperpage-1)));
3646 cmd->dst = msm_virt_to_dma(chip, buf01);
3647 cmd->len = 4;
3648 cmd++;
3649
3650 /* Reading last code word from NC10 */
3651 /* 0x53C */
3652 cmd->cmd = 0;
3653 cmd->src = msm_virt_to_dma(chip,
3654 &dma_buffer->data.adm_mux_cmd_ack_req_nc01);
3655 cmd->dst = EBI2_NAND_ADM_MUX;
3656 cmd->len = 4;
3657 cmd++;
3658
3659 cmd->cmd = DST_CRCI_NAND_CMD;
3660 cmd->src = msm_virt_to_dma(chip, &dma_buffer->data.cmd);
3661 cmd->dst = NC10(MSM_NAND_FLASH_CMD);
3662 cmd->len = 12;
3663 cmd++;
3664
3665 cmd->cmd = 0;
3666 cmd->src = msm_virt_to_dma(chip, &dma_buffer->data.chipsel_cs1);
3667 cmd->dst = NC10(MSM_NAND_FLASH_CHIP_SELECT);
3668 cmd->len = 4;
3669 cmd++;
3670
3671 cmd->cmd = 0;
3672 cmd->src = msm_virt_to_dma(chip, &dma_buffer->data.cfg0);
3673 cmd->dst = NC10(MSM_NAND_DEV1_CFG0);
3674 cmd->len = 8;
3675 cmd++;
3676
3677 cmd->cmd = 0;
3678 cmd->src = msm_virt_to_dma(chip, &dma_buffer->data.exec);
3679 cmd->dst = NC10(MSM_NAND_EXEC_CMD);
3680 cmd->len = 4;
3681 cmd++;
3682
3683 /* A3C */
3684 cmd->cmd = 0;
3685 cmd->src = msm_virt_to_dma(chip,
3686 &dma_buffer->data.adm_mux_data_ack_req_nc01);
3687 cmd->dst = EBI2_NAND_ADM_MUX;
3688 cmd->len = 4;
3689 cmd++;
3690
3691 cmd->cmd = SRC_CRCI_NAND_DATA;
3692 cmd->src = NC10(MSM_NAND_FLASH_STATUS);
3693 cmd->dst = msm_virt_to_dma(chip, &dma_buffer->data.result[1]);
3694 cmd->len = 8;
3695 cmd++;
3696
3697 cmd->cmd = 0;
3698 cmd->src = NC10(MSM_NAND_FLASH_BUFFER) + ((mtd->writesize >> 1) -
3699 (528*(cwperpage-1)));
3700 cmd->dst = msm_virt_to_dma(chip, buf10);
3701 cmd->len = 4;
3702 cmd++;
3703
3704 /* FC0 */
3705 cmd->cmd = 0;
3706 cmd->src = msm_virt_to_dma(chip,
3707 &dma_buffer->data.adm_default_mux);
3708 cmd->dst = EBI2_NAND_ADM_MUX;
3709 cmd->len = 4;
3710 cmd++;
3711
3712 /* disble CS1 */
3713 cmd->cmd = 0;
3714 cmd->src = msm_virt_to_dma(chip,
3715 &dma_buffer->data.ebi2_chip_select_cfg0);
3716 cmd->dst = EBI2_CHIP_SELECT_CFG0;
3717 cmd->len = 4;
3718 cmd++;
3719
3720 BUILD_BUG_ON(18 != ARRAY_SIZE(dma_buffer->cmd));
3721 BUG_ON(cmd - dma_buffer->cmd > ARRAY_SIZE(dma_buffer->cmd));
3722 dma_buffer->cmd[0].cmd |= CMD_OCB;
3723 cmd[-1].cmd |= CMD_OCU | CMD_LC;
3724
3725 dma_buffer->cmdptr = (msm_virt_to_dma(chip,
3726 dma_buffer->cmd) >> 3) | CMD_PTR_LP;
3727
3728 mb();
3729 msm_dmov_exec_cmd(chip->dma_channel, crci_mask, DMOV_CMD_PTR_LIST |
3730 DMOV_CMD_ADDR(msm_virt_to_dma(chip, &dma_buffer->cmdptr)));
3731 mb();
3732
3733 ret = 0;
3734 if ((dma_buffer->data.result[0].flash_status & 0x110) ||
3735 (dma_buffer->data.result[1].flash_status & 0x110))
3736 ret = -EIO;
3737
3738 if (!ret) {
3739 /* Check for bad block marker byte for NC01 & NC10 */
3740 if (chip->CFG1 & CFG1_WIDE_FLASH) {
3741 if ((buf01[0] != 0xFF || buf01[1] != 0xFF) ||
3742 (buf10[0] != 0xFF || buf10[1] != 0xFF))
3743 ret = 1;
3744 } else {
3745 if (buf01[0] != 0xFF || buf10[0] != 0xFF)
3746 ret = 1;
3747 }
3748 }
3749
3750 msm_nand_release_dma_buffer(chip, dma_buffer, sizeof(*dma_buffer) + 8);
3751 return ret;
3752}
3753
3754static int
3755msm_nand_block_markbad(struct mtd_info *mtd, loff_t ofs)
3756{
3757 struct mtd_oob_ops ops;
3758 int ret;
3759 uint8_t *buf;
3760
3761 /* Check for invalid offset */
3762 if (ofs > mtd->size)
3763 return -EINVAL;
3764 if (ofs & (mtd->erasesize - 1)) {
3765 pr_err("%s: unsupported block address, 0x%x\n",
3766 __func__, (uint32_t)ofs);
3767 return -EINVAL;
3768 }
3769
3770 /*
3771 Write all 0s to the first page
3772 This will set the BB marker to 0
3773 */
3774 buf = page_address(ZERO_PAGE());
3775
3776 ops.mode = MTD_OOB_RAW;
3777 ops.len = mtd->writesize + mtd->oobsize;
3778 ops.retlen = 0;
3779 ops.ooblen = 0;
3780 ops.datbuf = buf;
3781 ops.oobbuf = NULL;
3782 if (!interleave_enable)
3783 ret = msm_nand_write_oob(mtd, ofs, &ops);
3784 else
3785 ret = msm_nand_write_oob_dualnandc(mtd, ofs, &ops);
3786
3787 return ret;
3788}
3789
3790/**
3791 * msm_nand_suspend - [MTD Interface] Suspend the msm_nand flash
3792 * @param mtd MTD device structure
3793 */
3794static int msm_nand_suspend(struct mtd_info *mtd)
3795{
3796 return 0;
3797}
3798
3799/**
3800 * msm_nand_resume - [MTD Interface] Resume the msm_nand flash
3801 * @param mtd MTD device structure
3802 */
3803static void msm_nand_resume(struct mtd_info *mtd)
3804{
3805}
3806
3807struct onenand_information {
3808 uint16_t manufacturer_id;
3809 uint16_t device_id;
3810 uint16_t version_id;
3811 uint16_t data_buf_size;
3812 uint16_t boot_buf_size;
3813 uint16_t num_of_buffers;
3814 uint16_t technology;
3815};
3816
3817static struct onenand_information onenand_info;
3818static uint32_t nand_sfcmd_mode;
3819
3820uint32_t flash_onenand_probe(struct msm_nand_chip *chip)
3821{
3822 struct {
3823 dmov_s cmd[7];
3824 unsigned cmdptr;
3825 struct {
3826 uint32_t bcfg;
3827 uint32_t cmd;
3828 uint32_t exec;
3829 uint32_t status;
3830 uint32_t addr0;
3831 uint32_t addr1;
3832 uint32_t addr2;
3833 uint32_t addr3;
3834 uint32_t addr4;
3835 uint32_t addr5;
3836 uint32_t addr6;
3837 uint32_t data0;
3838 uint32_t data1;
3839 uint32_t data2;
3840 uint32_t data3;
3841 uint32_t data4;
3842 uint32_t data5;
3843 uint32_t data6;
3844 } data;
3845 } *dma_buffer;
3846 dmov_s *cmd;
3847
3848 int err = 0;
3849 uint32_t initialsflashcmd = 0;
3850
3851 initialsflashcmd = flash_rd_reg(chip, MSM_NAND_SFLASHC_CMD);
3852
3853 if ((initialsflashcmd & 0x10) == 0x10)
3854 nand_sfcmd_mode = MSM_NAND_SFCMD_ASYNC;
3855 else
3856 nand_sfcmd_mode = MSM_NAND_SFCMD_BURST;
3857
3858 printk(KERN_INFO "SFLASHC Async Mode bit: %x \n", nand_sfcmd_mode);
3859
3860 wait_event(chip->wait_queue, (dma_buffer = msm_nand_get_dma_buffer
3861 (chip, sizeof(*dma_buffer))));
3862
3863 cmd = dma_buffer->cmd;
3864
3865 dma_buffer->data.bcfg = SFLASH_BCFG |
3866 (nand_sfcmd_mode ? 0 : (1 << 24));
3867 dma_buffer->data.cmd = SFLASH_PREPCMD(7, 0, 0,
3868 MSM_NAND_SFCMD_DATXS,
3869 nand_sfcmd_mode,
3870 MSM_NAND_SFCMD_REGRD);
3871 dma_buffer->data.exec = 1;
3872 dma_buffer->data.status = CLEAN_DATA_32;
3873 dma_buffer->data.addr0 = (ONENAND_DEVICE_ID << 16) |
3874 (ONENAND_MANUFACTURER_ID);
3875 dma_buffer->data.addr1 = (ONENAND_DATA_BUFFER_SIZE << 16) |
3876 (ONENAND_VERSION_ID);
3877 dma_buffer->data.addr2 = (ONENAND_AMOUNT_OF_BUFFERS << 16) |
3878 (ONENAND_BOOT_BUFFER_SIZE);
3879 dma_buffer->data.addr3 = (CLEAN_DATA_16 << 16) |
3880 (ONENAND_TECHNOLOGY << 0);
3881 dma_buffer->data.data0 = CLEAN_DATA_32;
3882 dma_buffer->data.data1 = CLEAN_DATA_32;
3883 dma_buffer->data.data2 = CLEAN_DATA_32;
3884 dma_buffer->data.data3 = CLEAN_DATA_32;
3885
3886 /* Enable and configure the SFlash controller */
3887 cmd->cmd = 0;
3888 cmd->src = msm_virt_to_dma(chip, &dma_buffer->data.bcfg);
3889 cmd->dst = MSM_NAND_SFLASHC_BURST_CFG;
3890 cmd->len = 4;
3891 cmd++;
3892
3893 /* Block on cmd ready and write CMD register */
3894 cmd->cmd = DST_CRCI_NAND_CMD;
3895 cmd->src = msm_virt_to_dma(chip, &dma_buffer->data.cmd);
3896 cmd->dst = MSM_NAND_SFLASHC_CMD;
3897 cmd->len = 4;
3898 cmd++;
3899
3900 /* Configure the ADDR0 and ADDR1 registers */
3901 cmd->cmd = 0;
3902 cmd->src = msm_virt_to_dma(chip, &dma_buffer->data.addr0);
3903 cmd->dst = MSM_NAND_ADDR0;
3904 cmd->len = 8;
3905 cmd++;
3906
3907 /* Configure the ADDR2 and ADDR3 registers */
3908 cmd->cmd = 0;
3909 cmd->src = msm_virt_to_dma(chip, &dma_buffer->data.addr2);
3910 cmd->dst = MSM_NAND_ADDR2;
3911 cmd->len = 8;
3912 cmd++;
3913
3914 /* Kick the execute command */
3915 cmd->cmd = 0;
3916 cmd->src = msm_virt_to_dma(chip, &dma_buffer->data.exec);
3917 cmd->dst = MSM_NAND_SFLASHC_EXEC_CMD;
3918 cmd->len = 4;
3919 cmd++;
3920
3921 /* Block on data ready, and read the two status registers */
3922 cmd->cmd = SRC_CRCI_NAND_DATA;
3923 cmd->src = MSM_NAND_SFLASHC_STATUS;
3924 cmd->dst = msm_virt_to_dma(chip, &dma_buffer->data.status);
3925 cmd->len = 4;
3926 cmd++;
3927
3928 /* Read data registers - valid only if status says success */
3929 cmd->cmd = 0;
3930 cmd->src = MSM_NAND_GENP_REG0;
3931 cmd->dst = msm_virt_to_dma(chip, &dma_buffer->data.data0);
3932 cmd->len = 16;
3933 cmd++;
3934
3935 BUILD_BUG_ON(7 != ARRAY_SIZE(dma_buffer->cmd));
3936 BUG_ON(cmd - dma_buffer->cmd > ARRAY_SIZE(dma_buffer->cmd));
3937 dma_buffer->cmd[0].cmd |= CMD_OCB;
3938 cmd[-1].cmd |= CMD_OCU | CMD_LC;
3939
3940 dma_buffer->cmdptr = (msm_virt_to_dma(chip, dma_buffer->cmd)
3941 >> 3) | CMD_PTR_LP;
3942
3943 mb();
3944 msm_dmov_exec_cmd(chip->dma_channel, crci_mask, DMOV_CMD_PTR_LIST
3945 | DMOV_CMD_ADDR(msm_virt_to_dma(chip,
3946 &dma_buffer->cmdptr)));
3947 mb();
3948
3949 /* Check for errors, protection violations etc */
3950 if (dma_buffer->data.status & 0x110) {
3951 pr_info("%s: MPU/OP error"
3952 "(0x%x) during Onenand probe\n",
3953 __func__, dma_buffer->data.status);
3954 err = -EIO;
3955 } else {
3956
3957 onenand_info.manufacturer_id =
3958 (dma_buffer->data.data0 >> 0) & 0x0000FFFF;
3959 onenand_info.device_id =
3960 (dma_buffer->data.data0 >> 16) & 0x0000FFFF;
3961 onenand_info.version_id =
3962 (dma_buffer->data.data1 >> 0) & 0x0000FFFF;
3963 onenand_info.data_buf_size =
3964 (dma_buffer->data.data1 >> 16) & 0x0000FFFF;
3965 onenand_info.boot_buf_size =
3966 (dma_buffer->data.data2 >> 0) & 0x0000FFFF;
3967 onenand_info.num_of_buffers =
3968 (dma_buffer->data.data2 >> 16) & 0x0000FFFF;
3969 onenand_info.technology =
3970 (dma_buffer->data.data3 >> 0) & 0x0000FFFF;
3971
3972
3973 pr_info("======================================="
3974 "==========================\n");
3975
3976 pr_info("%s: manufacturer_id = 0x%x\n"
3977 , __func__, onenand_info.manufacturer_id);
3978 pr_info("%s: device_id = 0x%x\n"
3979 , __func__, onenand_info.device_id);
3980 pr_info("%s: version_id = 0x%x\n"
3981 , __func__, onenand_info.version_id);
3982 pr_info("%s: data_buf_size = 0x%x\n"
3983 , __func__, onenand_info.data_buf_size);
3984 pr_info("%s: boot_buf_size = 0x%x\n"
3985 , __func__, onenand_info.boot_buf_size);
3986 pr_info("%s: num_of_buffers = 0x%x\n"
3987 , __func__, onenand_info.num_of_buffers);
3988 pr_info("%s: technology = 0x%x\n"
3989 , __func__, onenand_info.technology);
3990
3991 pr_info("======================================="
3992 "==========================\n");
3993
3994 if ((onenand_info.manufacturer_id != 0x00EC)
3995 || ((onenand_info.device_id & 0x0040) != 0x0040)
3996 || (onenand_info.data_buf_size != 0x0800)
3997 || (onenand_info.boot_buf_size != 0x0200)
3998 || (onenand_info.num_of_buffers != 0x0201)
3999 || (onenand_info.technology != 0)) {
4000
4001 pr_info("%s: Detected an unsupported device\n"
4002 , __func__);
4003 err = -EIO;
4004 }
4005 }
4006
4007 msm_nand_release_dma_buffer(chip, dma_buffer, sizeof(*dma_buffer));
4008
4009 return err;
4010}
4011
4012int msm_onenand_read_oob(struct mtd_info *mtd,
4013 loff_t from, struct mtd_oob_ops *ops)
4014{
4015 struct msm_nand_chip *chip = mtd->priv;
4016
4017 struct {
4018 dmov_s cmd[53];
4019 unsigned cmdptr;
4020 struct {
4021 uint32_t sfbcfg;
4022 uint32_t sfcmd[9];
4023 uint32_t sfexec;
4024 uint32_t sfstat[9];
4025 uint32_t addr0;
4026 uint32_t addr1;
4027 uint32_t addr2;
4028 uint32_t addr3;
4029 uint32_t addr4;
4030 uint32_t addr5;
4031 uint32_t addr6;
4032 uint32_t data0;
4033 uint32_t data1;
4034 uint32_t data2;
4035 uint32_t data3;
4036 uint32_t data4;
4037 uint32_t data5;
4038 uint32_t data6;
4039 uint32_t macro[5];
4040 } data;
4041 } *dma_buffer;
4042 dmov_s *cmd;
4043
4044 int err = 0;
4045 int i;
4046 dma_addr_t data_dma_addr = 0;
4047 dma_addr_t oob_dma_addr = 0;
4048 dma_addr_t data_dma_addr_curr = 0;
4049 dma_addr_t oob_dma_addr_curr = 0;
4050
4051 loff_t from_curr = 0;
4052 unsigned page_count;
4053 unsigned pages_read = 0;
4054
4055 uint16_t onenand_startaddr1;
4056 uint16_t onenand_startaddr8;
4057 uint16_t onenand_startaddr2;
4058 uint16_t onenand_startbuffer;
4059 uint16_t onenand_sysconfig1;
4060 uint16_t controller_status;
4061 uint16_t interrupt_status;
4062 uint16_t ecc_status;
4063#if VERBOSE
4064 pr_info("================================================="
4065 "================\n");
4066 pr_info("%s: from 0x%llx mode %d \ndatbuf 0x%p datlen 0x%x"
4067 "\noobbuf 0x%p ooblen 0x%x\n",
4068 __func__, from, ops->mode, ops->datbuf, ops->len,
4069 ops->oobbuf, ops->ooblen);
4070#endif
4071 if (!mtd) {
4072 pr_err("%s: invalid mtd pointer, 0x%x\n", __func__,
4073 (uint32_t)mtd);
4074 return -EINVAL;
4075 }
4076 if (from & (mtd->writesize - 1)) {
4077 pr_err("%s: unsupported from, 0x%llx\n", __func__,
4078 from);
4079 return -EINVAL;
4080 }
4081
4082 if ((ops->mode != MTD_OOB_PLACE) && (ops->mode != MTD_OOB_AUTO) &&
4083 (ops->mode != MTD_OOB_RAW)) {
4084 pr_err("%s: unsupported ops->mode, %d\n", __func__,
4085 ops->mode);
4086 return -EINVAL;
4087 }
4088
4089 if (((ops->datbuf == NULL) || (ops->len == 0)) &&
4090 ((ops->oobbuf == NULL) || (ops->ooblen == 0))) {
4091 pr_err("%s: incorrect ops fields - nothing to do\n",
4092 __func__);
4093 return -EINVAL;
4094 }
4095
4096 if ((ops->datbuf != NULL) && (ops->len == 0)) {
4097 pr_err("%s: data buffer passed but length 0\n",
4098 __func__);
4099 return -EINVAL;
4100 }
4101
4102 if ((ops->oobbuf != NULL) && (ops->ooblen == 0)) {
4103 pr_err("%s: oob buffer passed but length 0\n",
4104 __func__);
4105 return -EINVAL;
4106 }
4107
4108 if (ops->mode != MTD_OOB_RAW) {
4109 if (ops->datbuf != NULL && (ops->len % mtd->writesize) != 0) {
4110 /* when ops->datbuf is NULL, ops->len can be ooblen */
4111 pr_err("%s: unsupported ops->len, %d\n", __func__,
4112 ops->len);
4113 return -EINVAL;
4114 }
4115 } else {
4116 if (ops->datbuf != NULL &&
4117 (ops->len % (mtd->writesize + mtd->oobsize)) != 0) {
4118 pr_err("%s: unsupported ops->len,"
4119 " %d for MTD_OOB_RAW\n", __func__, ops->len);
4120 return -EINVAL;
4121 }
4122 }
4123
4124 if ((ops->mode == MTD_OOB_RAW) && (ops->oobbuf)) {
4125 pr_err("%s: unsupported operation, oobbuf pointer "
4126 "passed in for RAW mode, %x\n", __func__,
4127 (uint32_t)ops->oobbuf);
4128 return -EINVAL;
4129 }
4130
4131 if (ops->oobbuf && !ops->datbuf) {
4132 page_count = ops->ooblen / ((ops->mode == MTD_OOB_AUTO) ?
4133 mtd->oobavail : mtd->oobsize);
4134 if ((page_count == 0) && (ops->ooblen))
4135 page_count = 1;
4136 } else if (ops->mode != MTD_OOB_RAW)
4137 page_count = ops->len / mtd->writesize;
4138 else
4139 page_count = ops->len / (mtd->writesize + mtd->oobsize);
4140
4141 if ((ops->mode == MTD_OOB_PLACE) && (ops->oobbuf != NULL)) {
4142 if (page_count * mtd->oobsize > ops->ooblen) {
4143 pr_err("%s: unsupported ops->ooblen for "
4144 "PLACE, %d\n", __func__, ops->ooblen);
4145 return -EINVAL;
4146 }
4147 }
4148
4149 if ((ops->mode == MTD_OOB_PLACE) && (ops->ooblen != 0) &&
4150 (ops->ooboffs != 0)) {
4151 pr_err("%s: unsupported ops->ooboffs, %d\n", __func__,
4152 ops->ooboffs);
4153 return -EINVAL;
4154 }
4155
4156 if (ops->datbuf) {
4157 memset(ops->datbuf, 0x55, ops->len);
4158 data_dma_addr_curr = data_dma_addr = msm_nand_dma_map(chip->dev,
4159 ops->datbuf, ops->len, DMA_FROM_DEVICE);
4160 if (dma_mapping_error(chip->dev, data_dma_addr)) {
4161 pr_err("%s: failed to get dma addr for %p\n",
4162 __func__, ops->datbuf);
4163 return -EIO;
4164 }
4165 }
4166 if (ops->oobbuf) {
4167 memset(ops->oobbuf, 0x55, ops->ooblen);
4168 oob_dma_addr_curr = oob_dma_addr = msm_nand_dma_map(chip->dev,
4169 ops->oobbuf, ops->ooblen, DMA_FROM_DEVICE);
4170 if (dma_mapping_error(chip->dev, oob_dma_addr)) {
4171 pr_err("%s: failed to get dma addr for %p\n",
4172 __func__, ops->oobbuf);
4173 err = -EIO;
4174 goto err_dma_map_oobbuf_failed;
4175 }
4176 }
4177
4178 wait_event(chip->wait_queue, (dma_buffer = msm_nand_get_dma_buffer
4179 (chip, sizeof(*dma_buffer))));
4180
4181 from_curr = from;
4182
4183 while (page_count-- > 0) {
4184
4185 cmd = dma_buffer->cmd;
4186
4187 if ((onenand_info.device_id & ONENAND_DEVICE_IS_DDP)
4188 && (from_curr >= (mtd->size>>1))) { /* DDP Device */
4189 onenand_startaddr1 = DEVICE_FLASHCORE_1 |
4190 (((uint32_t)(from_curr-(mtd->size>>1))
4191 / mtd->erasesize));
4192 onenand_startaddr2 = DEVICE_BUFFERRAM_1;
4193 } else {
4194 onenand_startaddr1 = DEVICE_FLASHCORE_0 |
4195 ((uint32_t)from_curr / mtd->erasesize) ;
4196 onenand_startaddr2 = DEVICE_BUFFERRAM_0;
4197 }
4198
4199 onenand_startaddr8 = (((uint32_t)from_curr &
4200 (mtd->erasesize - 1)) / mtd->writesize) << 2;
4201 onenand_startbuffer = DATARAM0_0 << 8;
4202 onenand_sysconfig1 = (ops->mode == MTD_OOB_RAW) ?
4203 ONENAND_SYSCFG1_ECCDIS(nand_sfcmd_mode) :
4204 ONENAND_SYSCFG1_ECCENA(nand_sfcmd_mode);
4205
4206 dma_buffer->data.sfbcfg = SFLASH_BCFG |
4207 (nand_sfcmd_mode ? 0 : (1 << 24));
4208 dma_buffer->data.sfcmd[0] = SFLASH_PREPCMD(7, 0, 0,
4209 MSM_NAND_SFCMD_CMDXS,
4210 nand_sfcmd_mode,
4211 MSM_NAND_SFCMD_REGWR);
4212 dma_buffer->data.sfcmd[1] = SFLASH_PREPCMD(0, 0, 32,
4213 MSM_NAND_SFCMD_CMDXS,
4214 nand_sfcmd_mode,
4215 MSM_NAND_SFCMD_INTHI);
4216 dma_buffer->data.sfcmd[2] = SFLASH_PREPCMD(3, 7, 0,
4217 MSM_NAND_SFCMD_DATXS,
4218 nand_sfcmd_mode,
4219 MSM_NAND_SFCMD_REGRD);
4220 dma_buffer->data.sfcmd[3] = SFLASH_PREPCMD(256, 0, 0,
4221 MSM_NAND_SFCMD_DATXS,
4222 nand_sfcmd_mode,
4223 MSM_NAND_SFCMD_DATRD);
4224 dma_buffer->data.sfcmd[4] = SFLASH_PREPCMD(256, 0, 0,
4225 MSM_NAND_SFCMD_DATXS,
4226 nand_sfcmd_mode,
4227 MSM_NAND_SFCMD_DATRD);
4228 dma_buffer->data.sfcmd[5] = SFLASH_PREPCMD(256, 0, 0,
4229 MSM_NAND_SFCMD_DATXS,
4230 nand_sfcmd_mode,
4231 MSM_NAND_SFCMD_DATRD);
4232 dma_buffer->data.sfcmd[6] = SFLASH_PREPCMD(256, 0, 0,
4233 MSM_NAND_SFCMD_DATXS,
4234 nand_sfcmd_mode,
4235 MSM_NAND_SFCMD_DATRD);
4236 dma_buffer->data.sfcmd[7] = SFLASH_PREPCMD(32, 0, 0,
4237 MSM_NAND_SFCMD_DATXS,
4238 nand_sfcmd_mode,
4239 MSM_NAND_SFCMD_DATRD);
4240 dma_buffer->data.sfcmd[8] = SFLASH_PREPCMD(4, 10, 0,
4241 MSM_NAND_SFCMD_CMDXS,
4242 nand_sfcmd_mode,
4243 MSM_NAND_SFCMD_REGWR);
4244 dma_buffer->data.sfexec = 1;
4245 dma_buffer->data.sfstat[0] = CLEAN_DATA_32;
4246 dma_buffer->data.sfstat[1] = CLEAN_DATA_32;
4247 dma_buffer->data.sfstat[2] = CLEAN_DATA_32;
4248 dma_buffer->data.sfstat[3] = CLEAN_DATA_32;
4249 dma_buffer->data.sfstat[4] = CLEAN_DATA_32;
4250 dma_buffer->data.sfstat[5] = CLEAN_DATA_32;
4251 dma_buffer->data.sfstat[6] = CLEAN_DATA_32;
4252 dma_buffer->data.sfstat[7] = CLEAN_DATA_32;
4253 dma_buffer->data.sfstat[8] = CLEAN_DATA_32;
4254 dma_buffer->data.addr0 = (ONENAND_INTERRUPT_STATUS << 16) |
4255 (ONENAND_SYSTEM_CONFIG_1);
4256 dma_buffer->data.addr1 = (ONENAND_START_ADDRESS_8 << 16) |
4257 (ONENAND_START_ADDRESS_1);
4258 dma_buffer->data.addr2 = (ONENAND_START_BUFFER << 16) |
4259 (ONENAND_START_ADDRESS_2);
4260 dma_buffer->data.addr3 = (ONENAND_ECC_STATUS << 16) |
4261 (ONENAND_COMMAND);
4262 dma_buffer->data.addr4 = (ONENAND_CONTROLLER_STATUS << 16) |
4263 (ONENAND_INTERRUPT_STATUS);
4264 dma_buffer->data.addr5 = (ONENAND_INTERRUPT_STATUS << 16) |
4265 (ONENAND_SYSTEM_CONFIG_1);
4266 dma_buffer->data.addr6 = (ONENAND_START_ADDRESS_3 << 16) |
4267 (ONENAND_START_ADDRESS_1);
4268 dma_buffer->data.data0 = (ONENAND_CLRINTR << 16) |
4269 (onenand_sysconfig1);
4270 dma_buffer->data.data1 = (onenand_startaddr8 << 16) |
4271 (onenand_startaddr1);
4272 dma_buffer->data.data2 = (onenand_startbuffer << 16) |
4273 (onenand_startaddr2);
4274 dma_buffer->data.data3 = (CLEAN_DATA_16 << 16) |
4275 (ONENAND_CMDLOADSPARE);
4276 dma_buffer->data.data4 = (CLEAN_DATA_16 << 16) |
4277 (CLEAN_DATA_16);
4278 dma_buffer->data.data5 = (ONENAND_CLRINTR << 16) |
4279 (ONENAND_SYSCFG1_ECCENA(nand_sfcmd_mode));
4280 dma_buffer->data.data6 = (ONENAND_STARTADDR3_RES << 16) |
4281 (ONENAND_STARTADDR1_RES);
4282 dma_buffer->data.macro[0] = 0x0200;
4283 dma_buffer->data.macro[1] = 0x0300;
4284 dma_buffer->data.macro[2] = 0x0400;
4285 dma_buffer->data.macro[3] = 0x0500;
4286 dma_buffer->data.macro[4] = 0x8010;
4287
4288 /*************************************************************/
4289 /* Write necessary address registers in the onenand device */
4290 /*************************************************************/
4291
4292 /* Enable and configure the SFlash controller */
4293 cmd->cmd = 0;
4294 cmd->src = msm_virt_to_dma(chip, &dma_buffer->data.sfbcfg);
4295 cmd->dst = MSM_NAND_SFLASHC_BURST_CFG;
4296 cmd->len = 4;
4297 cmd++;
4298
4299 /* Block on cmd ready and write CMD register */
4300 cmd->cmd = DST_CRCI_NAND_CMD;
4301 cmd->src = msm_virt_to_dma(chip, &dma_buffer->data.sfcmd[0]);
4302 cmd->dst = MSM_NAND_SFLASHC_CMD;
4303 cmd->len = 4;
4304 cmd++;
4305
4306 /* Write the ADDR0 and ADDR1 registers */
4307 cmd->cmd = 0;
4308 cmd->src = msm_virt_to_dma(chip, &dma_buffer->data.addr0);
4309 cmd->dst = MSM_NAND_ADDR0;
4310 cmd->len = 8;
4311 cmd++;
4312
4313 /* Write the ADDR2 ADDR3 ADDR4 ADDR5 registers */
4314 cmd->cmd = 0;
4315 cmd->src = msm_virt_to_dma(chip, &dma_buffer->data.addr2);
4316 cmd->dst = MSM_NAND_ADDR2;
4317 cmd->len = 16;
4318 cmd++;
4319
4320 /* Write the ADDR6 registers */
4321 cmd->cmd = 0;
4322 cmd->src = msm_virt_to_dma(chip, &dma_buffer->data.addr6);
4323 cmd->dst = MSM_NAND_ADDR6;
4324 cmd->len = 4;
4325 cmd++;
4326
4327 /* Write the GENP0, GENP1, GENP2, GENP3 registers */
4328 cmd->cmd = 0;
4329 cmd->src = msm_virt_to_dma(chip, &dma_buffer->data.data0);
4330 cmd->dst = MSM_NAND_GENP_REG0;
4331 cmd->len = 16;
4332 cmd++;
4333
4334 /* Write the FLASH_DEV_CMD4,5,6 registers */
4335 cmd->cmd = 0;
4336 cmd->src = msm_virt_to_dma(chip, &dma_buffer->data.data4);
4337 cmd->dst = MSM_NAND_DEV_CMD4;
4338 cmd->len = 12;
4339 cmd++;
4340
4341 /* Kick the execute command */
4342 cmd->cmd = 0;
4343 cmd->src = msm_virt_to_dma(chip, &dma_buffer->data.sfexec);
4344 cmd->dst = MSM_NAND_SFLASHC_EXEC_CMD;
4345 cmd->len = 4;
4346 cmd++;
4347
4348 /* Block on data ready, and read the status register */
4349 cmd->cmd = SRC_CRCI_NAND_DATA;
4350 cmd->src = MSM_NAND_SFLASHC_STATUS;
4351 cmd->dst = msm_virt_to_dma(chip, &dma_buffer->data.sfstat[0]);
4352 cmd->len = 4;
4353 cmd++;
4354
4355 /*************************************************************/
4356 /* Wait for the interrupt from the Onenand device controller */
4357 /*************************************************************/
4358
4359 /* Block on cmd ready and write CMD register */
4360 cmd->cmd = DST_CRCI_NAND_CMD;
4361 cmd->src = msm_virt_to_dma(chip, &dma_buffer->data.sfcmd[1]);
4362 cmd->dst = MSM_NAND_SFLASHC_CMD;
4363 cmd->len = 4;
4364 cmd++;
4365
4366 /* Kick the execute command */
4367 cmd->cmd = 0;
4368 cmd->src = msm_virt_to_dma(chip, &dma_buffer->data.sfexec);
4369 cmd->dst = MSM_NAND_SFLASHC_EXEC_CMD;
4370 cmd->len = 4;
4371 cmd++;
4372
4373 /* Block on data ready, and read the status register */
4374 cmd->cmd = SRC_CRCI_NAND_DATA;
4375 cmd->src = MSM_NAND_SFLASHC_STATUS;
4376 cmd->dst = msm_virt_to_dma(chip, &dma_buffer->data.sfstat[1]);
4377 cmd->len = 4;
4378 cmd++;
4379
4380 /*************************************************************/
4381 /* Read necessary status registers from the onenand device */
4382 /*************************************************************/
4383
4384 /* Block on cmd ready and write CMD register */
4385 cmd->cmd = DST_CRCI_NAND_CMD;
4386 cmd->src = msm_virt_to_dma(chip, &dma_buffer->data.sfcmd[2]);
4387 cmd->dst = MSM_NAND_SFLASHC_CMD;
4388 cmd->len = 4;
4389 cmd++;
4390
4391 /* Kick the execute command */
4392 cmd->cmd = 0;
4393 cmd->src = msm_virt_to_dma(chip, &dma_buffer->data.sfexec);
4394 cmd->dst = MSM_NAND_SFLASHC_EXEC_CMD;
4395 cmd->len = 4;
4396 cmd++;
4397
4398 /* Block on data ready, and read the status register */
4399 cmd->cmd = SRC_CRCI_NAND_DATA;
4400 cmd->src = MSM_NAND_SFLASHC_STATUS;
4401 cmd->dst = msm_virt_to_dma(chip, &dma_buffer->data.sfstat[2]);
4402 cmd->len = 4;
4403 cmd++;
4404
4405 /* Read the GENP3 register */
4406 cmd->cmd = 0;
4407 cmd->src = MSM_NAND_GENP_REG3;
4408 cmd->dst = msm_virt_to_dma(chip, &dma_buffer->data.data3);
4409 cmd->len = 4;
4410 cmd++;
4411
4412 /* Read the DEVCMD4 register */
4413 cmd->cmd = 0;
4414 cmd->src = MSM_NAND_DEV_CMD4;
4415 cmd->dst = msm_virt_to_dma(chip, &dma_buffer->data.data4);
4416 cmd->len = 4;
4417 cmd++;
4418
4419 /*************************************************************/
4420 /* Read the data ram area from the onenand buffer ram */
4421 /*************************************************************/
4422
4423 if (ops->datbuf) {
4424
4425 dma_buffer->data.data3 = (CLEAN_DATA_16 << 16) |
4426 (ONENAND_CMDLOAD);
4427
4428 for (i = 0; i < 4; i++) {
4429
4430 /* Block on cmd ready and write CMD register */
4431 cmd->cmd = DST_CRCI_NAND_CMD;
4432 cmd->src = msm_virt_to_dma(chip,
4433 &dma_buffer->data.sfcmd[3+i]);
4434 cmd->dst = MSM_NAND_SFLASHC_CMD;
4435 cmd->len = 4;
4436 cmd++;
4437
4438 /* Write the MACRO1 register */
4439 cmd->cmd = 0;
4440 cmd->src = msm_virt_to_dma(chip,
4441 &dma_buffer->data.macro[i]);
4442 cmd->dst = MSM_NAND_MACRO1_REG;
4443 cmd->len = 4;
4444 cmd++;
4445
4446 /* Kick the execute command */
4447 cmd->cmd = 0;
4448 cmd->src = msm_virt_to_dma(chip,
4449 &dma_buffer->data.sfexec);
4450 cmd->dst = MSM_NAND_SFLASHC_EXEC_CMD;
4451 cmd->len = 4;
4452 cmd++;
4453
4454 /* Block on data rdy, & read status register */
4455 cmd->cmd = SRC_CRCI_NAND_DATA;
4456 cmd->src = MSM_NAND_SFLASHC_STATUS;
4457 cmd->dst = msm_virt_to_dma(chip,
4458 &dma_buffer->data.sfstat[3+i]);
4459 cmd->len = 4;
4460 cmd++;
4461
4462 /* Transfer nand ctlr buf contents to usr buf */
4463 cmd->cmd = 0;
4464 cmd->src = MSM_NAND_FLASH_BUFFER;
4465 cmd->dst = data_dma_addr_curr;
4466 cmd->len = 512;
4467 data_dma_addr_curr += 512;
4468 cmd++;
4469 }
4470 }
4471
4472 if ((ops->oobbuf) || (ops->mode == MTD_OOB_RAW)) {
4473
4474 /* Block on cmd ready and write CMD register */
4475 cmd->cmd = DST_CRCI_NAND_CMD;
4476 cmd->src = msm_virt_to_dma(chip,
4477 &dma_buffer->data.sfcmd[7]);
4478 cmd->dst = MSM_NAND_SFLASHC_CMD;
4479 cmd->len = 4;
4480 cmd++;
4481
4482 /* Write the MACRO1 register */
4483 cmd->cmd = 0;
4484 cmd->src = msm_virt_to_dma(chip,
4485 &dma_buffer->data.macro[4]);
4486 cmd->dst = MSM_NAND_MACRO1_REG;
4487 cmd->len = 4;
4488 cmd++;
4489
4490 /* Kick the execute command */
4491 cmd->cmd = 0;
4492 cmd->src = msm_virt_to_dma(chip,
4493 &dma_buffer->data.sfexec);
4494 cmd->dst = MSM_NAND_SFLASHC_EXEC_CMD;
4495 cmd->len = 4;
4496 cmd++;
4497
4498 /* Block on data ready, and read status register */
4499 cmd->cmd = SRC_CRCI_NAND_DATA;
4500 cmd->src = MSM_NAND_SFLASHC_STATUS;
4501 cmd->dst = msm_virt_to_dma(chip,
4502 &dma_buffer->data.sfstat[7]);
4503 cmd->len = 4;
4504 cmd++;
4505
4506 /* Transfer nand ctlr buffer contents into usr buf */
4507 if (ops->mode == MTD_OOB_AUTO) {
4508 for (i = 0; i < MTD_MAX_OOBFREE_ENTRIES; i++) {
4509 cmd->cmd = 0;
4510 cmd->src = MSM_NAND_FLASH_BUFFER +
4511 mtd->ecclayout->oobfree[i].offset;
4512 cmd->dst = oob_dma_addr_curr;
4513 cmd->len =
4514 mtd->ecclayout->oobfree[i].length;
4515 oob_dma_addr_curr +=
4516 mtd->ecclayout->oobfree[i].length;
4517 cmd++;
4518 }
4519 }
4520 if (ops->mode == MTD_OOB_PLACE) {
4521 cmd->cmd = 0;
4522 cmd->src = MSM_NAND_FLASH_BUFFER;
4523 cmd->dst = oob_dma_addr_curr;
4524 cmd->len = mtd->oobsize;
4525 oob_dma_addr_curr += mtd->oobsize;
4526 cmd++;
4527 }
4528 if (ops->mode == MTD_OOB_RAW) {
4529 cmd->cmd = 0;
4530 cmd->src = MSM_NAND_FLASH_BUFFER;
4531 cmd->dst = data_dma_addr_curr;
4532 cmd->len = mtd->oobsize;
4533 data_dma_addr_curr += mtd->oobsize;
4534 cmd++;
4535 }
4536 }
4537
4538 /*************************************************************/
4539 /* Restore the necessary registers to proper values */
4540 /*************************************************************/
4541
4542 /* Block on cmd ready and write CMD register */
4543 cmd->cmd = DST_CRCI_NAND_CMD;
4544 cmd->src = msm_virt_to_dma(chip, &dma_buffer->data.sfcmd[8]);
4545 cmd->dst = MSM_NAND_SFLASHC_CMD;
4546 cmd->len = 4;
4547 cmd++;
4548
4549 /* Kick the execute command */
4550 cmd->cmd = 0;
4551 cmd->src = msm_virt_to_dma(chip, &dma_buffer->data.sfexec);
4552 cmd->dst = MSM_NAND_SFLASHC_EXEC_CMD;
4553 cmd->len = 4;
4554 cmd++;
4555
4556 /* Block on data ready, and read the status register */
4557 cmd->cmd = SRC_CRCI_NAND_DATA;
4558 cmd->src = MSM_NAND_SFLASHC_STATUS;
4559 cmd->dst = msm_virt_to_dma(chip, &dma_buffer->data.sfstat[8]);
4560 cmd->len = 4;
4561 cmd++;
4562
4563
4564 BUILD_BUG_ON(53 != ARRAY_SIZE(dma_buffer->cmd));
4565 BUG_ON(cmd - dma_buffer->cmd > ARRAY_SIZE(dma_buffer->cmd));
4566 dma_buffer->cmd[0].cmd |= CMD_OCB;
4567 cmd[-1].cmd |= CMD_OCU | CMD_LC;
4568
4569 dma_buffer->cmdptr = (msm_virt_to_dma(chip, dma_buffer->cmd)
4570 >> 3) | CMD_PTR_LP;
4571
4572 mb();
4573 msm_dmov_exec_cmd(chip->dma_channel, crci_mask,
4574 DMOV_CMD_PTR_LIST | DMOV_CMD_ADDR(msm_virt_to_dma(chip,
4575 &dma_buffer->cmdptr)));
4576 mb();
4577
4578 ecc_status = (dma_buffer->data.data3 >> 16) &
4579 0x0000FFFF;
4580 interrupt_status = (dma_buffer->data.data4 >> 0) &
4581 0x0000FFFF;
4582 controller_status = (dma_buffer->data.data4 >> 16) &
4583 0x0000FFFF;
4584
4585#if VERBOSE
4586 pr_info("\n%s: sflash status %x %x %x %x %x %x %x"
4587 "%x %x\n", __func__,
4588 dma_buffer->data.sfstat[0],
4589 dma_buffer->data.sfstat[1],
4590 dma_buffer->data.sfstat[2],
4591 dma_buffer->data.sfstat[3],
4592 dma_buffer->data.sfstat[4],
4593 dma_buffer->data.sfstat[5],
4594 dma_buffer->data.sfstat[6],
4595 dma_buffer->data.sfstat[7],
4596 dma_buffer->data.sfstat[8]);
4597
4598 pr_info("%s: controller_status = %x\n", __func__,
4599 controller_status);
4600 pr_info("%s: interrupt_status = %x\n", __func__,
4601 interrupt_status);
4602 pr_info("%s: ecc_status = %x\n", __func__,
4603 ecc_status);
4604#endif
4605 /* Check for errors, protection violations etc */
4606 if ((controller_status != 0)
4607 || (dma_buffer->data.sfstat[0] & 0x110)
4608 || (dma_buffer->data.sfstat[1] & 0x110)
4609 || (dma_buffer->data.sfstat[2] & 0x110)
4610 || (dma_buffer->data.sfstat[8] & 0x110)
4611 || ((dma_buffer->data.sfstat[3] & 0x110) &&
4612 (ops->datbuf))
4613 || ((dma_buffer->data.sfstat[4] & 0x110) &&
4614 (ops->datbuf))
4615 || ((dma_buffer->data.sfstat[5] & 0x110) &&
4616 (ops->datbuf))
4617 || ((dma_buffer->data.sfstat[6] & 0x110) &&
4618 (ops->datbuf))
4619 || ((dma_buffer->data.sfstat[7] & 0x110) &&
4620 ((ops->oobbuf)
4621 || (ops->mode == MTD_OOB_RAW)))) {
4622 pr_info("%s: ECC/MPU/OP error\n", __func__);
4623 err = -EIO;
4624 }
4625
4626 if (err)
4627 break;
4628 pages_read++;
4629 from_curr += mtd->writesize;
4630 }
4631
4632 msm_nand_release_dma_buffer(chip, dma_buffer, sizeof(*dma_buffer));
4633
4634 if (ops->oobbuf) {
4635 dma_unmap_page(chip->dev, oob_dma_addr, ops->ooblen,
4636 DMA_FROM_DEVICE);
4637 }
4638err_dma_map_oobbuf_failed:
4639 if (ops->datbuf) {
4640 dma_unmap_page(chip->dev, data_dma_addr, ops->len,
4641 DMA_FROM_DEVICE);
4642 }
4643
4644 if (err) {
4645 pr_err("%s: %llx %x %x failed\n", __func__, from_curr,
4646 ops->datbuf ? ops->len : 0, ops->ooblen);
4647 } else {
4648 ops->retlen = ops->oobretlen = 0;
4649 if (ops->datbuf != NULL) {
4650 if (ops->mode != MTD_OOB_RAW)
4651 ops->retlen = mtd->writesize * pages_read;
4652 else
4653 ops->retlen = (mtd->writesize + mtd->oobsize)
4654 * pages_read;
4655 }
4656 if (ops->oobbuf != NULL) {
4657 if (ops->mode == MTD_OOB_AUTO)
4658 ops->oobretlen = mtd->oobavail * pages_read;
4659 else
4660 ops->oobretlen = mtd->oobsize * pages_read;
4661 }
4662 }
4663
4664#if VERBOSE
4665 pr_info("\n%s: ret %d, retlen %d oobretlen %d\n",
4666 __func__, err, ops->retlen, ops->oobretlen);
4667
4668 pr_info("==================================================="
4669 "==============\n");
4670#endif
4671 return err;
4672}
4673
4674int msm_onenand_read(struct mtd_info *mtd, loff_t from, size_t len,
4675 size_t *retlen, u_char *buf)
4676{
4677 int ret;
4678 struct mtd_oob_ops ops;
4679
4680 ops.mode = MTD_OOB_PLACE;
4681 ops.datbuf = buf;
4682 ops.len = len;
4683 ops.retlen = 0;
4684 ops.oobbuf = NULL;
4685 ops.ooblen = 0;
4686 ops.oobretlen = 0;
4687 ret = msm_onenand_read_oob(mtd, from, &ops);
4688 *retlen = ops.retlen;
4689
4690 return ret;
4691}
4692
4693static int msm_onenand_write_oob(struct mtd_info *mtd, loff_t to,
4694 struct mtd_oob_ops *ops)
4695{
4696 struct msm_nand_chip *chip = mtd->priv;
4697
4698 struct {
4699 dmov_s cmd[53];
4700 unsigned cmdptr;
4701 struct {
4702 uint32_t sfbcfg;
4703 uint32_t sfcmd[10];
4704 uint32_t sfexec;
4705 uint32_t sfstat[10];
4706 uint32_t addr0;
4707 uint32_t addr1;
4708 uint32_t addr2;
4709 uint32_t addr3;
4710 uint32_t addr4;
4711 uint32_t addr5;
4712 uint32_t addr6;
4713 uint32_t data0;
4714 uint32_t data1;
4715 uint32_t data2;
4716 uint32_t data3;
4717 uint32_t data4;
4718 uint32_t data5;
4719 uint32_t data6;
4720 uint32_t macro[5];
4721 } data;
4722 } *dma_buffer;
4723 dmov_s *cmd;
4724
4725 int err = 0;
4726 int i, j, k;
4727 dma_addr_t data_dma_addr = 0;
4728 dma_addr_t oob_dma_addr = 0;
4729 dma_addr_t init_dma_addr = 0;
4730 dma_addr_t data_dma_addr_curr = 0;
4731 dma_addr_t oob_dma_addr_curr = 0;
4732 uint8_t *init_spare_bytes;
4733
4734 loff_t to_curr = 0;
4735 unsigned page_count;
4736 unsigned pages_written = 0;
4737
4738 uint16_t onenand_startaddr1;
4739 uint16_t onenand_startaddr8;
4740 uint16_t onenand_startaddr2;
4741 uint16_t onenand_startbuffer;
4742 uint16_t onenand_sysconfig1;
4743
4744 uint16_t controller_status;
4745 uint16_t interrupt_status;
4746 uint16_t ecc_status;
4747
4748#if VERBOSE
4749 pr_info("================================================="
4750 "================\n");
4751 pr_info("%s: to 0x%llx mode %d \ndatbuf 0x%p datlen 0x%x"
4752 "\noobbuf 0x%p ooblen 0x%x\n",
4753 __func__, to, ops->mode, ops->datbuf, ops->len,
4754 ops->oobbuf, ops->ooblen);
4755#endif
4756 if (!mtd) {
4757 pr_err("%s: invalid mtd pointer, 0x%x\n", __func__,
4758 (uint32_t)mtd);
4759 return -EINVAL;
4760 }
4761 if (to & (mtd->writesize - 1)) {
4762 pr_err("%s: unsupported to, 0x%llx\n", __func__, to);
4763 return -EINVAL;
4764 }
4765
4766 if ((ops->mode != MTD_OOB_PLACE) && (ops->mode != MTD_OOB_AUTO) &&
4767 (ops->mode != MTD_OOB_RAW)) {
4768 pr_err("%s: unsupported ops->mode, %d\n", __func__,
4769 ops->mode);
4770 return -EINVAL;
4771 }
4772
4773 if (((ops->datbuf == NULL) || (ops->len == 0)) &&
4774 ((ops->oobbuf == NULL) || (ops->ooblen == 0))) {
4775 pr_err("%s: incorrect ops fields - nothing to do\n",
4776 __func__);
4777 return -EINVAL;
4778 }
4779
4780 if ((ops->datbuf != NULL) && (ops->len == 0)) {
4781 pr_err("%s: data buffer passed but length 0\n",
4782 __func__);
4783 return -EINVAL;
4784 }
4785
4786 if ((ops->oobbuf != NULL) && (ops->ooblen == 0)) {
4787 pr_err("%s: oob buffer passed but length 0\n",
4788 __func__);
4789 return -EINVAL;
4790 }
4791
4792 if (ops->mode != MTD_OOB_RAW) {
4793 if (ops->datbuf != NULL && (ops->len % mtd->writesize) != 0) {
4794 /* when ops->datbuf is NULL, ops->len can be ooblen */
4795 pr_err("%s: unsupported ops->len, %d\n", __func__,
4796 ops->len);
4797 return -EINVAL;
4798 }
4799 } else {
4800 if (ops->datbuf != NULL &&
4801 (ops->len % (mtd->writesize + mtd->oobsize)) != 0) {
4802 pr_err("%s: unsupported ops->len,"
4803 " %d for MTD_OOB_RAW\n", __func__, ops->len);
4804 return -EINVAL;
4805 }
4806 }
4807
4808 if ((ops->mode == MTD_OOB_RAW) && (ops->oobbuf)) {
4809 pr_err("%s: unsupported operation, oobbuf pointer "
4810 "passed in for RAW mode, %x\n", __func__,
4811 (uint32_t)ops->oobbuf);
4812 return -EINVAL;
4813 }
4814
4815 if (ops->oobbuf && !ops->datbuf) {
4816 page_count = ops->ooblen / ((ops->mode == MTD_OOB_AUTO) ?
4817 mtd->oobavail : mtd->oobsize);
4818 if ((page_count == 0) && (ops->ooblen))
4819 page_count = 1;
4820 } else if (ops->mode != MTD_OOB_RAW)
4821 page_count = ops->len / mtd->writesize;
4822 else
4823 page_count = ops->len / (mtd->writesize + mtd->oobsize);
4824
4825 if ((ops->mode == MTD_OOB_AUTO) && (ops->oobbuf != NULL)) {
4826 if (page_count > 1) {
4827 pr_err("%s: unsupported ops->ooblen for"
4828 "AUTO, %d\n", __func__, ops->ooblen);
4829 return -EINVAL;
4830 }
4831 }
4832
4833 if ((ops->mode == MTD_OOB_PLACE) && (ops->oobbuf != NULL)) {
4834 if (page_count * mtd->oobsize > ops->ooblen) {
4835 pr_err("%s: unsupported ops->ooblen for"
4836 "PLACE, %d\n", __func__, ops->ooblen);
4837 return -EINVAL;
4838 }
4839 }
4840
4841 if ((ops->mode == MTD_OOB_PLACE) && (ops->ooblen != 0) &&
4842 (ops->ooboffs != 0)) {
4843 pr_err("%s: unsupported ops->ooboffs, %d\n",
4844 __func__, ops->ooboffs);
4845 return -EINVAL;
4846 }
4847
4848 init_spare_bytes = kmalloc(64, GFP_KERNEL);
4849 if (!init_spare_bytes) {
4850 pr_err("%s: failed to alloc init_spare_bytes buffer\n",
4851 __func__);
4852 return -ENOMEM;
4853 }
4854 for (i = 0; i < 64; i++)
4855 init_spare_bytes[i] = 0xFF;
4856
4857 if ((ops->oobbuf) && (ops->mode == MTD_OOB_AUTO)) {
4858 for (i = 0, k = 0; i < MTD_MAX_OOBFREE_ENTRIES; i++)
4859 for (j = 0; j < mtd->ecclayout->oobfree[i].length;
4860 j++) {
4861 init_spare_bytes[j +
4862 mtd->ecclayout->oobfree[i].offset]
4863 = (ops->oobbuf)[k];
4864 k++;
4865 }
4866 }
4867
4868 if (ops->datbuf) {
4869 data_dma_addr_curr = data_dma_addr = msm_nand_dma_map(chip->dev,
4870 ops->datbuf, ops->len, DMA_TO_DEVICE);
4871 if (dma_mapping_error(chip->dev, data_dma_addr)) {
4872 pr_err("%s: failed to get dma addr for %p\n",
4873 __func__, ops->datbuf);
4874 return -EIO;
4875 }
4876 }
4877 if (ops->oobbuf) {
4878 oob_dma_addr_curr = oob_dma_addr = msm_nand_dma_map(chip->dev,
4879 ops->oobbuf, ops->ooblen, DMA_TO_DEVICE);
4880 if (dma_mapping_error(chip->dev, oob_dma_addr)) {
4881 pr_err("%s: failed to get dma addr for %p\n",
4882 __func__, ops->oobbuf);
4883 err = -EIO;
4884 goto err_dma_map_oobbuf_failed;
4885 }
4886 }
4887
4888 init_dma_addr = msm_nand_dma_map(chip->dev, init_spare_bytes, 64,
4889 DMA_TO_DEVICE);
4890 if (dma_mapping_error(chip->dev, init_dma_addr)) {
4891 pr_err("%s: failed to get dma addr for %p\n",
4892 __func__, init_spare_bytes);
4893 err = -EIO;
4894 goto err_dma_map_initbuf_failed;
4895 }
4896
4897
4898 wait_event(chip->wait_queue, (dma_buffer = msm_nand_get_dma_buffer
4899 (chip, sizeof(*dma_buffer))));
4900
4901 to_curr = to;
4902
4903 while (page_count-- > 0) {
4904 cmd = dma_buffer->cmd;
4905
4906 if ((onenand_info.device_id & ONENAND_DEVICE_IS_DDP)
4907 && (to_curr >= (mtd->size>>1))) { /* DDP Device */
4908 onenand_startaddr1 = DEVICE_FLASHCORE_1 |
4909 (((uint32_t)(to_curr-(mtd->size>>1))
4910 / mtd->erasesize));
4911 onenand_startaddr2 = DEVICE_BUFFERRAM_1;
4912 } else {
4913 onenand_startaddr1 = DEVICE_FLASHCORE_0 |
4914 ((uint32_t)to_curr / mtd->erasesize) ;
4915 onenand_startaddr2 = DEVICE_BUFFERRAM_0;
4916 }
4917
4918 onenand_startaddr8 = (((uint32_t)to_curr &
4919 (mtd->erasesize - 1)) / mtd->writesize) << 2;
4920 onenand_startbuffer = DATARAM0_0 << 8;
4921 onenand_sysconfig1 = (ops->mode == MTD_OOB_RAW) ?
4922 ONENAND_SYSCFG1_ECCDIS(nand_sfcmd_mode) :
4923 ONENAND_SYSCFG1_ECCENA(nand_sfcmd_mode);
4924
4925 dma_buffer->data.sfbcfg = SFLASH_BCFG |
4926 (nand_sfcmd_mode ? 0 : (1 << 24));
4927 dma_buffer->data.sfcmd[0] = SFLASH_PREPCMD(6, 0, 0,
4928 MSM_NAND_SFCMD_CMDXS,
4929 nand_sfcmd_mode,
4930 MSM_NAND_SFCMD_REGWR);
4931 dma_buffer->data.sfcmd[1] = SFLASH_PREPCMD(256, 0, 0,
4932 MSM_NAND_SFCMD_CMDXS,
4933 nand_sfcmd_mode,
4934 MSM_NAND_SFCMD_DATWR);
4935 dma_buffer->data.sfcmd[2] = SFLASH_PREPCMD(256, 0, 0,
4936 MSM_NAND_SFCMD_CMDXS,
4937 nand_sfcmd_mode,
4938 MSM_NAND_SFCMD_DATWR);
4939 dma_buffer->data.sfcmd[3] = SFLASH_PREPCMD(256, 0, 0,
4940 MSM_NAND_SFCMD_CMDXS,
4941 nand_sfcmd_mode,
4942 MSM_NAND_SFCMD_DATWR);
4943 dma_buffer->data.sfcmd[4] = SFLASH_PREPCMD(256, 0, 0,
4944 MSM_NAND_SFCMD_CMDXS,
4945 nand_sfcmd_mode,
4946 MSM_NAND_SFCMD_DATWR);
4947 dma_buffer->data.sfcmd[5] = SFLASH_PREPCMD(32, 0, 0,
4948 MSM_NAND_SFCMD_CMDXS,
4949 nand_sfcmd_mode,
4950 MSM_NAND_SFCMD_DATWR);
4951 dma_buffer->data.sfcmd[6] = SFLASH_PREPCMD(1, 6, 0,
4952 MSM_NAND_SFCMD_CMDXS,
4953 nand_sfcmd_mode,
4954 MSM_NAND_SFCMD_REGWR);
4955 dma_buffer->data.sfcmd[7] = SFLASH_PREPCMD(0, 0, 32,
4956 MSM_NAND_SFCMD_CMDXS,
4957 nand_sfcmd_mode,
4958 MSM_NAND_SFCMD_INTHI);
4959 dma_buffer->data.sfcmd[8] = SFLASH_PREPCMD(3, 7, 0,
4960 MSM_NAND_SFCMD_DATXS,
4961 nand_sfcmd_mode,
4962 MSM_NAND_SFCMD_REGRD);
4963 dma_buffer->data.sfcmd[9] = SFLASH_PREPCMD(4, 10, 0,
4964 MSM_NAND_SFCMD_CMDXS,
4965 nand_sfcmd_mode,
4966 MSM_NAND_SFCMD_REGWR);
4967 dma_buffer->data.sfexec = 1;
4968 dma_buffer->data.sfstat[0] = CLEAN_DATA_32;
4969 dma_buffer->data.sfstat[1] = CLEAN_DATA_32;
4970 dma_buffer->data.sfstat[2] = CLEAN_DATA_32;
4971 dma_buffer->data.sfstat[3] = CLEAN_DATA_32;
4972 dma_buffer->data.sfstat[4] = CLEAN_DATA_32;
4973 dma_buffer->data.sfstat[5] = CLEAN_DATA_32;
4974 dma_buffer->data.sfstat[6] = CLEAN_DATA_32;
4975 dma_buffer->data.sfstat[7] = CLEAN_DATA_32;
4976 dma_buffer->data.sfstat[8] = CLEAN_DATA_32;
4977 dma_buffer->data.sfstat[9] = CLEAN_DATA_32;
4978 dma_buffer->data.addr0 = (ONENAND_INTERRUPT_STATUS << 16) |
4979 (ONENAND_SYSTEM_CONFIG_1);
4980 dma_buffer->data.addr1 = (ONENAND_START_ADDRESS_8 << 16) |
4981 (ONENAND_START_ADDRESS_1);
4982 dma_buffer->data.addr2 = (ONENAND_START_BUFFER << 16) |
4983 (ONENAND_START_ADDRESS_2);
4984 dma_buffer->data.addr3 = (ONENAND_ECC_STATUS << 16) |
4985 (ONENAND_COMMAND);
4986 dma_buffer->data.addr4 = (ONENAND_CONTROLLER_STATUS << 16) |
4987 (ONENAND_INTERRUPT_STATUS);
4988 dma_buffer->data.addr5 = (ONENAND_INTERRUPT_STATUS << 16) |
4989 (ONENAND_SYSTEM_CONFIG_1);
4990 dma_buffer->data.addr6 = (ONENAND_START_ADDRESS_3 << 16) |
4991 (ONENAND_START_ADDRESS_1);
4992 dma_buffer->data.data0 = (ONENAND_CLRINTR << 16) |
4993 (onenand_sysconfig1);
4994 dma_buffer->data.data1 = (onenand_startaddr8 << 16) |
4995 (onenand_startaddr1);
4996 dma_buffer->data.data2 = (onenand_startbuffer << 16) |
4997 (onenand_startaddr2);
4998 dma_buffer->data.data3 = (CLEAN_DATA_16 << 16) |
4999 (ONENAND_CMDPROGSPARE);
5000 dma_buffer->data.data4 = (CLEAN_DATA_16 << 16) |
5001 (CLEAN_DATA_16);
5002 dma_buffer->data.data5 = (ONENAND_CLRINTR << 16) |
5003 (ONENAND_SYSCFG1_ECCENA(nand_sfcmd_mode));
5004 dma_buffer->data.data6 = (ONENAND_STARTADDR3_RES << 16) |
5005 (ONENAND_STARTADDR1_RES);
5006 dma_buffer->data.macro[0] = 0x0200;
5007 dma_buffer->data.macro[1] = 0x0300;
5008 dma_buffer->data.macro[2] = 0x0400;
5009 dma_buffer->data.macro[3] = 0x0500;
5010 dma_buffer->data.macro[4] = 0x8010;
5011
5012
5013 /*************************************************************/
5014 /* Write necessary address registers in the onenand device */
5015 /*************************************************************/
5016
5017 /* Enable and configure the SFlash controller */
5018 cmd->cmd = 0;
5019 cmd->src = msm_virt_to_dma(chip, &dma_buffer->data.sfbcfg);
5020 cmd->dst = MSM_NAND_SFLASHC_BURST_CFG;
5021 cmd->len = 4;
5022 cmd++;
5023
5024 /* Block on cmd ready and write CMD register */
5025 cmd->cmd = DST_CRCI_NAND_CMD;
5026 cmd->src = msm_virt_to_dma(chip, &dma_buffer->data.sfcmd[0]);
5027 cmd->dst = MSM_NAND_SFLASHC_CMD;
5028 cmd->len = 4;
5029 cmd++;
5030
5031 /* Write the ADDR0 and ADDR1 registers */
5032 cmd->cmd = 0;
5033 cmd->src = msm_virt_to_dma(chip, &dma_buffer->data.addr0);
5034 cmd->dst = MSM_NAND_ADDR0;
5035 cmd->len = 8;
5036 cmd++;
5037
5038 /* Write the ADDR2 ADDR3 ADDR4 ADDR5 registers */
5039 cmd->cmd = 0;
5040 cmd->src = msm_virt_to_dma(chip, &dma_buffer->data.addr2);
5041 cmd->dst = MSM_NAND_ADDR2;
5042 cmd->len = 16;
5043 cmd++;
5044
5045 /* Write the ADDR6 registers */
5046 cmd->cmd = 0;
5047 cmd->src = msm_virt_to_dma(chip, &dma_buffer->data.addr6);
5048 cmd->dst = MSM_NAND_ADDR6;
5049 cmd->len = 4;
5050 cmd++;
5051
5052 /* Write the GENP0, GENP1, GENP2, GENP3 registers */
5053 cmd->cmd = 0;
5054 cmd->src = msm_virt_to_dma(chip, &dma_buffer->data.data0);
5055 cmd->dst = MSM_NAND_GENP_REG0;
5056 cmd->len = 16;
5057 cmd++;
5058
5059 /* Write the FLASH_DEV_CMD4,5,6 registers */
5060 cmd->cmd = 0;
5061 cmd->src = msm_virt_to_dma(chip, &dma_buffer->data.data4);
5062 cmd->dst = MSM_NAND_DEV_CMD4;
5063 cmd->len = 12;
5064 cmd++;
5065
5066 /* Kick the execute command */
5067 cmd->cmd = 0;
5068 cmd->src = msm_virt_to_dma(chip, &dma_buffer->data.sfexec);
5069 cmd->dst = MSM_NAND_SFLASHC_EXEC_CMD;
5070 cmd->len = 4;
5071 cmd++;
5072
5073 /* Block on data ready, and read the status register */
5074 cmd->cmd = SRC_CRCI_NAND_DATA;
5075 cmd->src = MSM_NAND_SFLASHC_STATUS;
5076 cmd->dst = msm_virt_to_dma(chip, &dma_buffer->data.sfstat[0]);
5077 cmd->len = 4;
5078 cmd++;
5079
5080 /*************************************************************/
5081 /* Write the data ram area in the onenand buffer ram */
5082 /*************************************************************/
5083
5084 if (ops->datbuf) {
5085 dma_buffer->data.data3 = (CLEAN_DATA_16 << 16) |
5086 (ONENAND_CMDPROG);
5087
5088 for (i = 0; i < 4; i++) {
5089
5090 /* Block on cmd ready and write CMD register */
5091 cmd->cmd = DST_CRCI_NAND_CMD;
5092 cmd->src = msm_virt_to_dma(chip,
5093 &dma_buffer->data.sfcmd[1+i]);
5094 cmd->dst = MSM_NAND_SFLASHC_CMD;
5095 cmd->len = 4;
5096 cmd++;
5097
5098 /* Trnsfr usr buf contents to nand ctlr buf */
5099 cmd->cmd = 0;
5100 cmd->src = data_dma_addr_curr;
5101 cmd->dst = MSM_NAND_FLASH_BUFFER;
5102 cmd->len = 512;
5103 data_dma_addr_curr += 512;
5104 cmd++;
5105
5106 /* Write the MACRO1 register */
5107 cmd->cmd = 0;
5108 cmd->src = msm_virt_to_dma(chip,
5109 &dma_buffer->data.macro[i]);
5110 cmd->dst = MSM_NAND_MACRO1_REG;
5111 cmd->len = 4;
5112 cmd++;
5113
5114 /* Kick the execute command */
5115 cmd->cmd = 0;
5116 cmd->src = msm_virt_to_dma(chip,
5117 &dma_buffer->data.sfexec);
5118 cmd->dst = MSM_NAND_SFLASHC_EXEC_CMD;
5119 cmd->len = 4;
5120 cmd++;
5121
5122 /* Block on data rdy, & read status register */
5123 cmd->cmd = SRC_CRCI_NAND_DATA;
5124 cmd->src = MSM_NAND_SFLASHC_STATUS;
5125 cmd->dst = msm_virt_to_dma(chip,
5126 &dma_buffer->data.sfstat[1+i]);
5127 cmd->len = 4;
5128 cmd++;
5129
5130 }
5131 }
5132
5133 /* Block on cmd ready and write CMD register */
5134 cmd->cmd = DST_CRCI_NAND_CMD;
5135 cmd->src = msm_virt_to_dma(chip, &dma_buffer->data.sfcmd[5]);
5136 cmd->dst = MSM_NAND_SFLASHC_CMD;
5137 cmd->len = 4;
5138 cmd++;
5139
5140 if ((ops->oobbuf) || (ops->mode == MTD_OOB_RAW)) {
5141
5142 /* Transfer user buf contents into nand ctlr buffer */
5143 if (ops->mode == MTD_OOB_AUTO) {
5144 cmd->cmd = 0;
5145 cmd->src = init_dma_addr;
5146 cmd->dst = MSM_NAND_FLASH_BUFFER;
5147 cmd->len = mtd->oobsize;
5148 cmd++;
5149 }
5150 if (ops->mode == MTD_OOB_PLACE) {
5151 cmd->cmd = 0;
5152 cmd->src = oob_dma_addr_curr;
5153 cmd->dst = MSM_NAND_FLASH_BUFFER;
5154 cmd->len = mtd->oobsize;
5155 oob_dma_addr_curr += mtd->oobsize;
5156 cmd++;
5157 }
5158 if (ops->mode == MTD_OOB_RAW) {
5159 cmd->cmd = 0;
5160 cmd->src = data_dma_addr_curr;
5161 cmd->dst = MSM_NAND_FLASH_BUFFER;
5162 cmd->len = mtd->oobsize;
5163 data_dma_addr_curr += mtd->oobsize;
5164 cmd++;
5165 }
5166 } else {
5167 cmd->cmd = 0;
5168 cmd->src = init_dma_addr;
5169 cmd->dst = MSM_NAND_FLASH_BUFFER;
5170 cmd->len = mtd->oobsize;
5171 cmd++;
5172 }
5173
5174 /* Write the MACRO1 register */
5175 cmd->cmd = 0;
5176 cmd->src = msm_virt_to_dma(chip, &dma_buffer->data.macro[4]);
5177 cmd->dst = MSM_NAND_MACRO1_REG;
5178 cmd->len = 4;
5179 cmd++;
5180
5181 /* Kick the execute command */
5182 cmd->cmd = 0;
5183 cmd->src = msm_virt_to_dma(chip, &dma_buffer->data.sfexec);
5184 cmd->dst = MSM_NAND_SFLASHC_EXEC_CMD;
5185 cmd->len = 4;
5186 cmd++;
5187
5188 /* Block on data ready, and read the status register */
5189 cmd->cmd = SRC_CRCI_NAND_DATA;
5190 cmd->src = MSM_NAND_SFLASHC_STATUS;
5191 cmd->dst = msm_virt_to_dma(chip, &dma_buffer->data.sfstat[5]);
5192 cmd->len = 4;
5193 cmd++;
5194
5195 /*********************************************************/
5196 /* Issuing write command */
5197 /*********************************************************/
5198
5199 /* Block on cmd ready and write CMD register */
5200 cmd->cmd = DST_CRCI_NAND_CMD;
5201 cmd->src = msm_virt_to_dma(chip, &dma_buffer->data.sfcmd[6]);
5202 cmd->dst = MSM_NAND_SFLASHC_CMD;
5203 cmd->len = 4;
5204 cmd++;
5205
5206 /* Kick the execute command */
5207 cmd->cmd = 0;
5208 cmd->src = msm_virt_to_dma(chip, &dma_buffer->data.sfexec);
5209 cmd->dst = MSM_NAND_SFLASHC_EXEC_CMD;
5210 cmd->len = 4;
5211 cmd++;
5212
5213 /* Block on data ready, and read the status register */
5214 cmd->cmd = SRC_CRCI_NAND_DATA;
5215 cmd->src = MSM_NAND_SFLASHC_STATUS;
5216 cmd->dst = msm_virt_to_dma(chip, &dma_buffer->data.sfstat[6]);
5217 cmd->len = 4;
5218 cmd++;
5219
5220 /*************************************************************/
5221 /* Wait for the interrupt from the Onenand device controller */
5222 /*************************************************************/
5223
5224 /* Block on cmd ready and write CMD register */
5225 cmd->cmd = DST_CRCI_NAND_CMD;
5226 cmd->src = msm_virt_to_dma(chip, &dma_buffer->data.sfcmd[7]);
5227 cmd->dst = MSM_NAND_SFLASHC_CMD;
5228 cmd->len = 4;
5229 cmd++;
5230
5231 /* Kick the execute command */
5232 cmd->cmd = 0;
5233 cmd->src = msm_virt_to_dma(chip, &dma_buffer->data.sfexec);
5234 cmd->dst = MSM_NAND_SFLASHC_EXEC_CMD;
5235 cmd->len = 4;
5236 cmd++;
5237
5238 /* Block on data ready, and read the status register */
5239 cmd->cmd = SRC_CRCI_NAND_DATA;
5240 cmd->src = MSM_NAND_SFLASHC_STATUS;
5241 cmd->dst = msm_virt_to_dma(chip, &dma_buffer->data.sfstat[7]);
5242 cmd->len = 4;
5243 cmd++;
5244
5245 /*************************************************************/
5246 /* Read necessary status registers from the onenand device */
5247 /*************************************************************/
5248
5249 /* Block on cmd ready and write CMD register */
5250 cmd->cmd = DST_CRCI_NAND_CMD;
5251 cmd->src = msm_virt_to_dma(chip, &dma_buffer->data.sfcmd[8]);
5252 cmd->dst = MSM_NAND_SFLASHC_CMD;
5253 cmd->len = 4;
5254 cmd++;
5255
5256 /* Kick the execute command */
5257 cmd->cmd = 0;
5258 cmd->src = msm_virt_to_dma(chip, &dma_buffer->data.sfexec);
5259 cmd->dst = MSM_NAND_SFLASHC_EXEC_CMD;
5260 cmd->len = 4;
5261 cmd++;
5262
5263 /* Block on data ready, and read the status register */
5264 cmd->cmd = SRC_CRCI_NAND_DATA;
5265 cmd->src = MSM_NAND_SFLASHC_STATUS;
5266 cmd->dst = msm_virt_to_dma(chip, &dma_buffer->data.sfstat[8]);
5267 cmd->len = 4;
5268 cmd++;
5269
5270 /* Read the GENP3 register */
5271 cmd->cmd = 0;
5272 cmd->src = MSM_NAND_GENP_REG3;
5273 cmd->dst = msm_virt_to_dma(chip, &dma_buffer->data.data3);
5274 cmd->len = 4;
5275 cmd++;
5276
5277 /* Read the DEVCMD4 register */
5278 cmd->cmd = 0;
5279 cmd->src = MSM_NAND_DEV_CMD4;
5280 cmd->dst = msm_virt_to_dma(chip, &dma_buffer->data.data4);
5281 cmd->len = 4;
5282 cmd++;
5283
5284 /*************************************************************/
5285 /* Restore the necessary registers to proper values */
5286 /*************************************************************/
5287
5288 /* Block on cmd ready and write CMD register */
5289 cmd->cmd = DST_CRCI_NAND_CMD;
5290 cmd->src = msm_virt_to_dma(chip, &dma_buffer->data.sfcmd[9]);
5291 cmd->dst = MSM_NAND_SFLASHC_CMD;
5292 cmd->len = 4;
5293 cmd++;
5294
5295 /* Kick the execute command */
5296 cmd->cmd = 0;
5297 cmd->src = msm_virt_to_dma(chip, &dma_buffer->data.sfexec);
5298 cmd->dst = MSM_NAND_SFLASHC_EXEC_CMD;
5299 cmd->len = 4;
5300 cmd++;
5301
5302 /* Block on data ready, and read the status register */
5303 cmd->cmd = SRC_CRCI_NAND_DATA;
5304 cmd->src = MSM_NAND_SFLASHC_STATUS;
5305 cmd->dst = msm_virt_to_dma(chip, &dma_buffer->data.sfstat[9]);
5306 cmd->len = 4;
5307 cmd++;
5308
5309
5310 BUILD_BUG_ON(53 != ARRAY_SIZE(dma_buffer->cmd));
5311 BUG_ON(cmd - dma_buffer->cmd > ARRAY_SIZE(dma_buffer->cmd));
5312 dma_buffer->cmd[0].cmd |= CMD_OCB;
5313 cmd[-1].cmd |= CMD_OCU | CMD_LC;
5314
5315 dma_buffer->cmdptr = (msm_virt_to_dma(chip, dma_buffer->cmd)
5316 >> 3) | CMD_PTR_LP;
5317
5318 mb();
5319 msm_dmov_exec_cmd(chip->dma_channel, crci_mask,
5320 DMOV_CMD_PTR_LIST | DMOV_CMD_ADDR(msm_virt_to_dma(chip,
5321 &dma_buffer->cmdptr)));
5322 mb();
5323
5324 ecc_status = (dma_buffer->data.data3 >> 16) & 0x0000FFFF;
5325 interrupt_status = (dma_buffer->data.data4 >> 0)&0x0000FFFF;
5326 controller_status = (dma_buffer->data.data4 >> 16)&0x0000FFFF;
5327
5328#if VERBOSE
5329 pr_info("\n%s: sflash status %x %x %x %x %x %x %x"
5330 " %x %x %x\n", __func__,
5331 dma_buffer->data.sfstat[0],
5332 dma_buffer->data.sfstat[1],
5333 dma_buffer->data.sfstat[2],
5334 dma_buffer->data.sfstat[3],
5335 dma_buffer->data.sfstat[4],
5336 dma_buffer->data.sfstat[5],
5337 dma_buffer->data.sfstat[6],
5338 dma_buffer->data.sfstat[7],
5339 dma_buffer->data.sfstat[8],
5340 dma_buffer->data.sfstat[9]);
5341
5342 pr_info("%s: controller_status = %x\n", __func__,
5343 controller_status);
5344 pr_info("%s: interrupt_status = %x\n", __func__,
5345 interrupt_status);
5346 pr_info("%s: ecc_status = %x\n", __func__,
5347 ecc_status);
5348#endif
5349 /* Check for errors, protection violations etc */
5350 if ((controller_status != 0)
5351 || (dma_buffer->data.sfstat[0] & 0x110)
5352 || (dma_buffer->data.sfstat[6] & 0x110)
5353 || (dma_buffer->data.sfstat[7] & 0x110)
5354 || (dma_buffer->data.sfstat[8] & 0x110)
5355 || (dma_buffer->data.sfstat[9] & 0x110)
5356 || ((dma_buffer->data.sfstat[1] & 0x110) &&
5357 (ops->datbuf))
5358 || ((dma_buffer->data.sfstat[2] & 0x110) &&
5359 (ops->datbuf))
5360 || ((dma_buffer->data.sfstat[3] & 0x110) &&
5361 (ops->datbuf))
5362 || ((dma_buffer->data.sfstat[4] & 0x110) &&
5363 (ops->datbuf))
5364 || ((dma_buffer->data.sfstat[5] & 0x110) &&
5365 ((ops->oobbuf)
5366 || (ops->mode == MTD_OOB_RAW)))) {
5367 pr_info("%s: ECC/MPU/OP error\n", __func__);
5368 err = -EIO;
5369 }
5370
5371 if (err)
5372 break;
5373 pages_written++;
5374 to_curr += mtd->writesize;
5375 }
5376
5377 msm_nand_release_dma_buffer(chip, dma_buffer, sizeof(*dma_buffer));
5378
5379 dma_unmap_page(chip->dev, init_dma_addr, 64, DMA_TO_DEVICE);
5380
5381err_dma_map_initbuf_failed:
5382 if (ops->oobbuf) {
5383 dma_unmap_page(chip->dev, oob_dma_addr, ops->ooblen,
5384 DMA_TO_DEVICE);
5385 }
5386err_dma_map_oobbuf_failed:
5387 if (ops->datbuf) {
5388 dma_unmap_page(chip->dev, data_dma_addr, ops->len,
5389 DMA_TO_DEVICE);
5390 }
5391
5392 if (err) {
5393 pr_err("%s: %llx %x %x failed\n", __func__, to_curr,
5394 ops->datbuf ? ops->len : 0, ops->ooblen);
5395 } else {
5396 ops->retlen = ops->oobretlen = 0;
5397 if (ops->datbuf != NULL) {
5398 if (ops->mode != MTD_OOB_RAW)
5399 ops->retlen = mtd->writesize * pages_written;
5400 else
5401 ops->retlen = (mtd->writesize + mtd->oobsize)
5402 * pages_written;
5403 }
5404 if (ops->oobbuf != NULL) {
5405 if (ops->mode == MTD_OOB_AUTO)
5406 ops->oobretlen = mtd->oobavail * pages_written;
5407 else
5408 ops->oobretlen = mtd->oobsize * pages_written;
5409 }
5410 }
5411
5412#if VERBOSE
5413 pr_info("\n%s: ret %d, retlen %d oobretlen %d\n",
5414 __func__, err, ops->retlen, ops->oobretlen);
5415
5416 pr_info("================================================="
5417 "================\n");
5418#endif
5419 kfree(init_spare_bytes);
5420 return err;
5421}
5422
5423static int msm_onenand_write(struct mtd_info *mtd, loff_t to, size_t len,
5424 size_t *retlen, const u_char *buf)
5425{
5426 int ret;
5427 struct mtd_oob_ops ops;
5428
5429 ops.mode = MTD_OOB_PLACE;
5430 ops.datbuf = (uint8_t *)buf;
5431 ops.len = len;
5432 ops.retlen = 0;
5433 ops.oobbuf = NULL;
5434 ops.ooblen = 0;
5435 ops.oobretlen = 0;
5436 ret = msm_onenand_write_oob(mtd, to, &ops);
5437 *retlen = ops.retlen;
5438
5439 return ret;
5440}
5441
5442static int msm_onenand_erase(struct mtd_info *mtd, struct erase_info *instr)
5443{
5444 struct msm_nand_chip *chip = mtd->priv;
5445
5446 struct {
5447 dmov_s cmd[20];
5448 unsigned cmdptr;
5449 struct {
5450 uint32_t sfbcfg;
5451 uint32_t sfcmd[4];
5452 uint32_t sfexec;
5453 uint32_t sfstat[4];
5454 uint32_t addr0;
5455 uint32_t addr1;
5456 uint32_t addr2;
5457 uint32_t addr3;
5458 uint32_t addr4;
5459 uint32_t addr5;
5460 uint32_t addr6;
5461 uint32_t data0;
5462 uint32_t data1;
5463 uint32_t data2;
5464 uint32_t data3;
5465 uint32_t data4;
5466 uint32_t data5;
5467 uint32_t data6;
5468 } data;
5469 } *dma_buffer;
5470 dmov_s *cmd;
5471
5472 int err = 0;
5473
5474 uint16_t onenand_startaddr1;
5475 uint16_t onenand_startaddr8;
5476 uint16_t onenand_startaddr2;
5477 uint16_t onenand_startbuffer;
5478
5479 uint16_t controller_status;
5480 uint16_t interrupt_status;
5481 uint16_t ecc_status;
5482
5483 uint64_t temp;
5484
5485#if VERBOSE
5486 pr_info("================================================="
5487 "================\n");
5488 pr_info("%s: addr 0x%llx len 0x%llx\n",
5489 __func__, instr->addr, instr->len);
5490#endif
5491 if (instr->addr & (mtd->erasesize - 1)) {
5492 pr_err("%s: Unsupported erase address, 0x%llx\n",
5493 __func__, instr->addr);
5494 return -EINVAL;
5495 }
5496 if (instr->len != mtd->erasesize) {
5497 pr_err("%s: Unsupported erase len, %lld\n",
5498 __func__, instr->len);
5499 return -EINVAL;
5500 }
5501
5502 wait_event(chip->wait_queue, (dma_buffer = msm_nand_get_dma_buffer
5503 (chip, sizeof(*dma_buffer))));
5504
5505 cmd = dma_buffer->cmd;
5506
5507 temp = instr->addr;
5508
5509 if ((onenand_info.device_id & ONENAND_DEVICE_IS_DDP)
5510 && (temp >= (mtd->size>>1))) { /* DDP Device */
5511 onenand_startaddr1 = DEVICE_FLASHCORE_1 |
5512 (((uint32_t)(temp-(mtd->size>>1))
5513 / mtd->erasesize));
5514 onenand_startaddr2 = DEVICE_BUFFERRAM_1;
5515 } else {
5516 onenand_startaddr1 = DEVICE_FLASHCORE_0 |
5517 ((uint32_t)temp / mtd->erasesize) ;
5518 onenand_startaddr2 = DEVICE_BUFFERRAM_0;
5519 }
5520
5521 onenand_startaddr8 = 0x0000;
5522 onenand_startbuffer = DATARAM0_0 << 8;
5523
5524 dma_buffer->data.sfbcfg = SFLASH_BCFG |
5525 (nand_sfcmd_mode ? 0 : (1 << 24));
5526 dma_buffer->data.sfcmd[0] = SFLASH_PREPCMD(7, 0, 0,
5527 MSM_NAND_SFCMD_CMDXS,
5528 nand_sfcmd_mode,
5529 MSM_NAND_SFCMD_REGWR);
5530 dma_buffer->data.sfcmd[1] = SFLASH_PREPCMD(0, 0, 32,
5531 MSM_NAND_SFCMD_CMDXS,
5532 nand_sfcmd_mode,
5533 MSM_NAND_SFCMD_INTHI);
5534 dma_buffer->data.sfcmd[2] = SFLASH_PREPCMD(3, 7, 0,
5535 MSM_NAND_SFCMD_DATXS,
5536 nand_sfcmd_mode,
5537 MSM_NAND_SFCMD_REGRD);
5538 dma_buffer->data.sfcmd[3] = SFLASH_PREPCMD(4, 10, 0,
5539 MSM_NAND_SFCMD_CMDXS,
5540 nand_sfcmd_mode,
5541 MSM_NAND_SFCMD_REGWR);
5542 dma_buffer->data.sfexec = 1;
5543 dma_buffer->data.sfstat[0] = CLEAN_DATA_32;
5544 dma_buffer->data.sfstat[1] = CLEAN_DATA_32;
5545 dma_buffer->data.sfstat[2] = CLEAN_DATA_32;
5546 dma_buffer->data.sfstat[3] = CLEAN_DATA_32;
5547 dma_buffer->data.addr0 = (ONENAND_INTERRUPT_STATUS << 16) |
5548 (ONENAND_SYSTEM_CONFIG_1);
5549 dma_buffer->data.addr1 = (ONENAND_START_ADDRESS_8 << 16) |
5550 (ONENAND_START_ADDRESS_1);
5551 dma_buffer->data.addr2 = (ONENAND_START_BUFFER << 16) |
5552 (ONENAND_START_ADDRESS_2);
5553 dma_buffer->data.addr3 = (ONENAND_ECC_STATUS << 16) |
5554 (ONENAND_COMMAND);
5555 dma_buffer->data.addr4 = (ONENAND_CONTROLLER_STATUS << 16) |
5556 (ONENAND_INTERRUPT_STATUS);
5557 dma_buffer->data.addr5 = (ONENAND_INTERRUPT_STATUS << 16) |
5558 (ONENAND_SYSTEM_CONFIG_1);
5559 dma_buffer->data.addr6 = (ONENAND_START_ADDRESS_3 << 16) |
5560 (ONENAND_START_ADDRESS_1);
5561 dma_buffer->data.data0 = (ONENAND_CLRINTR << 16) |
5562 (ONENAND_SYSCFG1_ECCENA(nand_sfcmd_mode));
5563 dma_buffer->data.data1 = (onenand_startaddr8 << 16) |
5564 (onenand_startaddr1);
5565 dma_buffer->data.data2 = (onenand_startbuffer << 16) |
5566 (onenand_startaddr2);
5567 dma_buffer->data.data3 = (CLEAN_DATA_16 << 16) |
5568 (ONENAND_CMDERAS);
5569 dma_buffer->data.data4 = (CLEAN_DATA_16 << 16) |
5570 (CLEAN_DATA_16);
5571 dma_buffer->data.data5 = (ONENAND_CLRINTR << 16) |
5572 (ONENAND_SYSCFG1_ECCENA(nand_sfcmd_mode));
5573 dma_buffer->data.data6 = (ONENAND_STARTADDR3_RES << 16) |
5574 (ONENAND_STARTADDR1_RES);
5575
5576 /***************************************************************/
5577 /* Write the necessary address registers in the onenand device */
5578 /***************************************************************/
5579
5580 /* Enable and configure the SFlash controller */
5581 cmd->cmd = 0;
5582 cmd->src = msm_virt_to_dma(chip, &dma_buffer->data.sfbcfg);
5583 cmd->dst = MSM_NAND_SFLASHC_BURST_CFG;
5584 cmd->len = 4;
5585 cmd++;
5586
5587 /* Block on cmd ready and write CMD register */
5588 cmd->cmd = DST_CRCI_NAND_CMD;
5589 cmd->src = msm_virt_to_dma(chip, &dma_buffer->data.sfcmd[0]);
5590 cmd->dst = MSM_NAND_SFLASHC_CMD;
5591 cmd->len = 4;
5592 cmd++;
5593
5594 /* Write the ADDR0 and ADDR1 registers */
5595 cmd->cmd = 0;
5596 cmd->src = msm_virt_to_dma(chip, &dma_buffer->data.addr0);
5597 cmd->dst = MSM_NAND_ADDR0;
5598 cmd->len = 8;
5599 cmd++;
5600
5601 /* Write the ADDR2 ADDR3 ADDR4 ADDR5 registers */
5602 cmd->cmd = 0;
5603 cmd->src = msm_virt_to_dma(chip, &dma_buffer->data.addr2);
5604 cmd->dst = MSM_NAND_ADDR2;
5605 cmd->len = 16;
5606 cmd++;
5607
5608 /* Write the ADDR6 registers */
5609 cmd->cmd = 0;
5610 cmd->src = msm_virt_to_dma(chip, &dma_buffer->data.addr6);
5611 cmd->dst = MSM_NAND_ADDR6;
5612 cmd->len = 4;
5613 cmd++;
5614
5615 /* Write the GENP0, GENP1, GENP2, GENP3, GENP4 registers */
5616 cmd->cmd = 0;
5617 cmd->src = msm_virt_to_dma(chip, &dma_buffer->data.data0);
5618 cmd->dst = MSM_NAND_GENP_REG0;
5619 cmd->len = 16;
5620 cmd++;
5621
5622 /* Write the FLASH_DEV_CMD4,5,6 registers */
5623 cmd->cmd = 0;
5624 cmd->src = msm_virt_to_dma(chip, &dma_buffer->data.data4);
5625 cmd->dst = MSM_NAND_DEV_CMD4;
5626 cmd->len = 12;
5627 cmd++;
5628
5629 /* Kick the execute command */
5630 cmd->cmd = 0;
5631 cmd->src = msm_virt_to_dma(chip, &dma_buffer->data.sfexec);
5632 cmd->dst = MSM_NAND_SFLASHC_EXEC_CMD;
5633 cmd->len = 4;
5634 cmd++;
5635
5636 /* Block on data ready, and read the status register */
5637 cmd->cmd = SRC_CRCI_NAND_DATA;
5638 cmd->src = MSM_NAND_SFLASHC_STATUS;
5639 cmd->dst = msm_virt_to_dma(chip, &dma_buffer->data.sfstat[0]);
5640 cmd->len = 4;
5641 cmd++;
5642
5643 /***************************************************************/
5644 /* Wait for the interrupt from the Onenand device controller */
5645 /***************************************************************/
5646
5647 /* Block on cmd ready and write CMD register */
5648 cmd->cmd = DST_CRCI_NAND_CMD;
5649 cmd->src = msm_virt_to_dma(chip, &dma_buffer->data.sfcmd[1]);
5650 cmd->dst = MSM_NAND_SFLASHC_CMD;
5651 cmd->len = 4;
5652 cmd++;
5653
5654 /* Kick the execute command */
5655 cmd->cmd = 0;
5656 cmd->src = msm_virt_to_dma(chip, &dma_buffer->data.sfexec);
5657 cmd->dst = MSM_NAND_SFLASHC_EXEC_CMD;
5658 cmd->len = 4;
5659 cmd++;
5660
5661 /* Block on data ready, and read the status register */
5662 cmd->cmd = SRC_CRCI_NAND_DATA;
5663 cmd->src = MSM_NAND_SFLASHC_STATUS;
5664 cmd->dst = msm_virt_to_dma(chip, &dma_buffer->data.sfstat[1]);
5665 cmd->len = 4;
5666 cmd++;
5667
5668 /***************************************************************/
5669 /* Read the necessary status registers from the onenand device */
5670 /***************************************************************/
5671
5672 /* Block on cmd ready and write CMD register */
5673 cmd->cmd = DST_CRCI_NAND_CMD;
5674 cmd->src = msm_virt_to_dma(chip, &dma_buffer->data.sfcmd[2]);
5675 cmd->dst = MSM_NAND_SFLASHC_CMD;
5676 cmd->len = 4;
5677 cmd++;
5678
5679 /* Kick the execute command */
5680 cmd->cmd = 0;
5681 cmd->src = msm_virt_to_dma(chip, &dma_buffer->data.sfexec);
5682 cmd->dst = MSM_NAND_SFLASHC_EXEC_CMD;
5683 cmd->len = 4;
5684 cmd++;
5685
5686 /* Block on data ready, and read the status register */
5687 cmd->cmd = SRC_CRCI_NAND_DATA;
5688 cmd->src = MSM_NAND_SFLASHC_STATUS;
5689 cmd->dst = msm_virt_to_dma(chip, &dma_buffer->data.sfstat[2]);
5690 cmd->len = 4;
5691 cmd++;
5692
5693 /* Read the GENP3 register */
5694 cmd->cmd = 0;
5695 cmd->src = MSM_NAND_GENP_REG3;
5696 cmd->dst = msm_virt_to_dma(chip, &dma_buffer->data.data3);
5697 cmd->len = 4;
5698 cmd++;
5699
5700 /* Read the DEVCMD4 register */
5701 cmd->cmd = 0;
5702 cmd->src = MSM_NAND_DEV_CMD4;
5703 cmd->dst = msm_virt_to_dma(chip, &dma_buffer->data.data4);
5704 cmd->len = 4;
5705 cmd++;
5706
5707 /***************************************************************/
5708 /* Restore the necessary registers to proper values */
5709 /***************************************************************/
5710
5711 /* Block on cmd ready and write CMD register */
5712 cmd->cmd = DST_CRCI_NAND_CMD;
5713 cmd->src = msm_virt_to_dma(chip, &dma_buffer->data.sfcmd[3]);
5714 cmd->dst = MSM_NAND_SFLASHC_CMD;
5715 cmd->len = 4;
5716 cmd++;
5717
5718 /* Kick the execute command */
5719 cmd->cmd = 0;
5720 cmd->src = msm_virt_to_dma(chip, &dma_buffer->data.sfexec);
5721 cmd->dst = MSM_NAND_SFLASHC_EXEC_CMD;
5722 cmd->len = 4;
5723 cmd++;
5724
5725 /* Block on data ready, and read the status register */
5726 cmd->cmd = SRC_CRCI_NAND_DATA;
5727 cmd->src = MSM_NAND_SFLASHC_STATUS;
5728 cmd->dst = msm_virt_to_dma(chip, &dma_buffer->data.sfstat[3]);
5729 cmd->len = 4;
5730 cmd++;
5731
5732
5733 BUILD_BUG_ON(20 != ARRAY_SIZE(dma_buffer->cmd));
5734 BUG_ON(cmd - dma_buffer->cmd > ARRAY_SIZE(dma_buffer->cmd));
5735 dma_buffer->cmd[0].cmd |= CMD_OCB;
5736 cmd[-1].cmd |= CMD_OCU | CMD_LC;
5737
5738 dma_buffer->cmdptr = (msm_virt_to_dma(chip, dma_buffer->cmd)
5739 >> 3) | CMD_PTR_LP;
5740
5741 mb();
5742 msm_dmov_exec_cmd(chip->dma_channel, crci_mask, DMOV_CMD_PTR_LIST
5743 | DMOV_CMD_ADDR(msm_virt_to_dma(chip,
5744 &dma_buffer->cmdptr)));
5745 mb();
5746
5747 ecc_status = (dma_buffer->data.data3 >> 16) & 0x0000FFFF;
5748 interrupt_status = (dma_buffer->data.data4 >> 0) & 0x0000FFFF;
5749 controller_status = (dma_buffer->data.data4 >> 16) & 0x0000FFFF;
5750
5751#if VERBOSE
5752 pr_info("\n%s: sflash status %x %x %x %x\n", __func__,
5753 dma_buffer->data.sfstat[0],
5754 dma_buffer->data.sfstat[1],
5755 dma_buffer->data.sfstat[2],
5756 dma_buffer->data.sfstat[3]);
5757
5758 pr_info("%s: controller_status = %x\n", __func__,
5759 controller_status);
5760 pr_info("%s: interrupt_status = %x\n", __func__,
5761 interrupt_status);
5762 pr_info("%s: ecc_status = %x\n", __func__,
5763 ecc_status);
5764#endif
5765 /* Check for errors, protection violations etc */
5766 if ((controller_status != 0)
5767 || (dma_buffer->data.sfstat[0] & 0x110)
5768 || (dma_buffer->data.sfstat[1] & 0x110)
5769 || (dma_buffer->data.sfstat[2] & 0x110)
5770 || (dma_buffer->data.sfstat[3] & 0x110)) {
5771 pr_err("%s: ECC/MPU/OP error\n", __func__);
5772 err = -EIO;
5773 }
5774
5775 msm_nand_release_dma_buffer(chip, dma_buffer, sizeof(*dma_buffer));
5776
5777 if (err) {
5778 pr_err("%s: Erase failed, 0x%llx\n", __func__,
5779 instr->addr);
5780 instr->fail_addr = instr->addr;
5781 instr->state = MTD_ERASE_FAILED;
5782 } else {
5783 instr->state = MTD_ERASE_DONE;
5784 instr->fail_addr = 0xffffffff;
5785 mtd_erase_callback(instr);
5786 }
5787
5788#if VERBOSE
5789 pr_info("\n%s: ret %d\n", __func__, err);
5790 pr_info("===================================================="
5791 "=============\n");
5792#endif
5793 return err;
5794}
5795
5796static int msm_onenand_block_isbad(struct mtd_info *mtd, loff_t ofs)
5797{
5798 struct mtd_oob_ops ops;
5799 int rval, i;
5800 int ret = 0;
5801 uint8_t *buffer;
5802 uint8_t *oobptr;
5803
5804 if ((ofs > mtd->size) || (ofs & (mtd->erasesize - 1))) {
5805 pr_err("%s: unsupported block address, 0x%x\n",
5806 __func__, (uint32_t)ofs);
5807 return -EINVAL;
5808 }
5809
5810 buffer = kmalloc(2112, GFP_KERNEL|GFP_DMA);
5811 if (buffer == 0) {
5812 pr_err("%s: Could not kmalloc for buffer\n",
5813 __func__);
5814 return -ENOMEM;
5815 }
5816
5817 memset(buffer, 0x00, 2112);
5818 oobptr = &(buffer[2048]);
5819
5820 ops.mode = MTD_OOB_RAW;
5821 ops.len = 2112;
5822 ops.retlen = 0;
5823 ops.ooblen = 0;
5824 ops.oobretlen = 0;
5825 ops.ooboffs = 0;
5826 ops.datbuf = buffer;
5827 ops.oobbuf = NULL;
5828
5829 for (i = 0; i < 2; i++) {
5830 ofs = ofs + i*mtd->writesize;
5831 rval = msm_onenand_read_oob(mtd, ofs, &ops);
5832 if (rval) {
5833 pr_err("%s: Error in reading bad blk info\n",
5834 __func__);
5835 ret = rval;
5836 break;
5837 }
5838 if ((oobptr[0] != 0xFF) || (oobptr[1] != 0xFF) ||
5839 (oobptr[16] != 0xFF) || (oobptr[17] != 0xFF) ||
5840 (oobptr[32] != 0xFF) || (oobptr[33] != 0xFF) ||
5841 (oobptr[48] != 0xFF) || (oobptr[49] != 0xFF)
5842 ) {
5843 ret = 1;
5844 break;
5845 }
5846 }
5847
5848 kfree(buffer);
5849
5850#if VERBOSE
5851 if (ret == 1)
5852 pr_info("%s : Block containing 0x%x is bad\n",
5853 __func__, (unsigned int)ofs);
5854#endif
5855 return ret;
5856}
5857
5858static int msm_onenand_block_markbad(struct mtd_info *mtd, loff_t ofs)
5859{
5860 struct mtd_oob_ops ops;
5861 int rval, i;
5862 int ret = 0;
5863 uint8_t *buffer;
5864
5865 if ((ofs > mtd->size) || (ofs & (mtd->erasesize - 1))) {
5866 pr_err("%s: unsupported block address, 0x%x\n",
5867 __func__, (uint32_t)ofs);
5868 return -EINVAL;
5869 }
5870
5871 buffer = page_address(ZERO_PAGE());
5872
5873 ops.mode = MTD_OOB_RAW;
5874 ops.len = 2112;
5875 ops.retlen = 0;
5876 ops.ooblen = 0;
5877 ops.oobretlen = 0;
5878 ops.ooboffs = 0;
5879 ops.datbuf = buffer;
5880 ops.oobbuf = NULL;
5881
5882 for (i = 0; i < 2; i++) {
5883 ofs = ofs + i*mtd->writesize;
5884 rval = msm_onenand_write_oob(mtd, ofs, &ops);
5885 if (rval) {
5886 pr_err("%s: Error in writing bad blk info\n",
5887 __func__);
5888 ret = rval;
5889 break;
5890 }
5891 }
5892
5893 return ret;
5894}
5895
5896static int msm_onenand_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
5897{
5898 struct msm_nand_chip *chip = mtd->priv;
5899
5900 struct {
5901 dmov_s cmd[20];
5902 unsigned cmdptr;
5903 struct {
5904 uint32_t sfbcfg;
5905 uint32_t sfcmd[4];
5906 uint32_t sfexec;
5907 uint32_t sfstat[4];
5908 uint32_t addr0;
5909 uint32_t addr1;
5910 uint32_t addr2;
5911 uint32_t addr3;
5912 uint32_t addr4;
5913 uint32_t addr5;
5914 uint32_t addr6;
5915 uint32_t data0;
5916 uint32_t data1;
5917 uint32_t data2;
5918 uint32_t data3;
5919 uint32_t data4;
5920 uint32_t data5;
5921 uint32_t data6;
5922 } data;
5923 } *dma_buffer;
5924 dmov_s *cmd;
5925
5926 int err = 0;
5927
5928 uint16_t onenand_startaddr1;
5929 uint16_t onenand_startaddr8;
5930 uint16_t onenand_startaddr2;
5931 uint16_t onenand_startblock;
5932
5933 uint16_t controller_status;
5934 uint16_t interrupt_status;
5935 uint16_t write_prot_status;
5936
5937 uint64_t start_ofs;
5938
5939#if VERBOSE
5940 pr_info("===================================================="
5941 "=============\n");
5942 pr_info("%s: ofs 0x%llx len %lld\n", __func__, ofs, len);
5943#endif
5944 /* 'ofs' & 'len' should align to block size */
5945 if (ofs&(mtd->erasesize - 1)) {
5946 pr_err("%s: Unsupported ofs address, 0x%llx\n",
5947 __func__, ofs);
5948 return -EINVAL;
5949 }
5950
5951 if (len&(mtd->erasesize - 1)) {
5952 pr_err("%s: Unsupported len, %lld\n",
5953 __func__, len);
5954 return -EINVAL;
5955 }
5956
5957 if (ofs+len > mtd->size) {
5958 pr_err("%s: Maximum chip size exceeded\n", __func__);
5959 return -EINVAL;
5960 }
5961
5962 wait_event(chip->wait_queue, (dma_buffer = msm_nand_get_dma_buffer
5963 (chip, sizeof(*dma_buffer))));
5964
5965 for (start_ofs = ofs; ofs < start_ofs+len; ofs = ofs+mtd->erasesize) {
5966#if VERBOSE
5967 pr_info("%s: ofs 0x%llx len %lld\n", __func__, ofs, len);
5968#endif
5969
5970 cmd = dma_buffer->cmd;
5971 if ((onenand_info.device_id & ONENAND_DEVICE_IS_DDP)
5972 && (ofs >= (mtd->size>>1))) { /* DDP Device */
5973 onenand_startaddr1 = DEVICE_FLASHCORE_1 |
5974 (((uint32_t)(ofs - (mtd->size>>1))
5975 / mtd->erasesize));
5976 onenand_startaddr2 = DEVICE_BUFFERRAM_1;
5977 onenand_startblock = ((uint32_t)(ofs - (mtd->size>>1))
5978 / mtd->erasesize);
5979 } else {
5980 onenand_startaddr1 = DEVICE_FLASHCORE_0 |
5981 ((uint32_t)ofs / mtd->erasesize) ;
5982 onenand_startaddr2 = DEVICE_BUFFERRAM_0;
5983 onenand_startblock = ((uint32_t)ofs
5984 / mtd->erasesize);
5985 }
5986
5987 onenand_startaddr8 = 0x0000;
5988 dma_buffer->data.sfbcfg = SFLASH_BCFG |
5989 (nand_sfcmd_mode ? 0 : (1 << 24));
5990 dma_buffer->data.sfcmd[0] = SFLASH_PREPCMD(7, 0, 0,
5991 MSM_NAND_SFCMD_CMDXS,
5992 nand_sfcmd_mode,
5993 MSM_NAND_SFCMD_REGWR);
5994 dma_buffer->data.sfcmd[1] = SFLASH_PREPCMD(0, 0, 32,
5995 MSM_NAND_SFCMD_CMDXS,
5996 nand_sfcmd_mode,
5997 MSM_NAND_SFCMD_INTHI);
5998 dma_buffer->data.sfcmd[2] = SFLASH_PREPCMD(3, 7, 0,
5999 MSM_NAND_SFCMD_DATXS,
6000 nand_sfcmd_mode,
6001 MSM_NAND_SFCMD_REGRD);
6002 dma_buffer->data.sfcmd[3] = SFLASH_PREPCMD(4, 10, 0,
6003 MSM_NAND_SFCMD_CMDXS,
6004 nand_sfcmd_mode,
6005 MSM_NAND_SFCMD_REGWR);
6006 dma_buffer->data.sfexec = 1;
6007 dma_buffer->data.sfstat[0] = CLEAN_DATA_32;
6008 dma_buffer->data.sfstat[1] = CLEAN_DATA_32;
6009 dma_buffer->data.sfstat[2] = CLEAN_DATA_32;
6010 dma_buffer->data.sfstat[3] = CLEAN_DATA_32;
6011 dma_buffer->data.addr0 = (ONENAND_INTERRUPT_STATUS << 16) |
6012 (ONENAND_SYSTEM_CONFIG_1);
6013 dma_buffer->data.addr1 = (ONENAND_START_ADDRESS_8 << 16) |
6014 (ONENAND_START_ADDRESS_1);
6015 dma_buffer->data.addr2 = (ONENAND_START_BLOCK_ADDRESS << 16) |
6016 (ONENAND_START_ADDRESS_2);
6017 dma_buffer->data.addr3 = (ONENAND_WRITE_PROT_STATUS << 16) |
6018 (ONENAND_COMMAND);
6019 dma_buffer->data.addr4 = (ONENAND_CONTROLLER_STATUS << 16) |
6020 (ONENAND_INTERRUPT_STATUS);
6021 dma_buffer->data.addr5 = (ONENAND_INTERRUPT_STATUS << 16) |
6022 (ONENAND_SYSTEM_CONFIG_1);
6023 dma_buffer->data.addr6 = (ONENAND_START_ADDRESS_3 << 16) |
6024 (ONENAND_START_ADDRESS_1);
6025 dma_buffer->data.data0 = (ONENAND_CLRINTR << 16) |
6026 (ONENAND_SYSCFG1_ECCENA(nand_sfcmd_mode));
6027 dma_buffer->data.data1 = (onenand_startaddr8 << 16) |
6028 (onenand_startaddr1);
6029 dma_buffer->data.data2 = (onenand_startblock << 16) |
6030 (onenand_startaddr2);
6031 dma_buffer->data.data3 = (CLEAN_DATA_16 << 16) |
6032 (ONENAND_CMD_UNLOCK);
6033 dma_buffer->data.data4 = (CLEAN_DATA_16 << 16) |
6034 (CLEAN_DATA_16);
6035 dma_buffer->data.data5 = (ONENAND_CLRINTR << 16) |
6036 (ONENAND_SYSCFG1_ECCENA(nand_sfcmd_mode));
6037 dma_buffer->data.data6 = (ONENAND_STARTADDR3_RES << 16) |
6038 (ONENAND_STARTADDR1_RES);
6039
6040 /*************************************************************/
6041 /* Write the necessary address reg in the onenand device */
6042 /*************************************************************/
6043
6044 /* Enable and configure the SFlash controller */
6045 cmd->cmd = 0;
6046 cmd->src = msm_virt_to_dma(chip, &dma_buffer->data.sfbcfg);
6047 cmd->dst = MSM_NAND_SFLASHC_BURST_CFG;
6048 cmd->len = 4;
6049 cmd++;
6050
6051 /* Block on cmd ready and write CMD register */
6052 cmd->cmd = DST_CRCI_NAND_CMD;
6053 cmd->src = msm_virt_to_dma(chip, &dma_buffer->data.sfcmd[0]);
6054 cmd->dst = MSM_NAND_SFLASHC_CMD;
6055 cmd->len = 4;
6056 cmd++;
6057
6058 /* Write the ADDR0 and ADDR1 registers */
6059 cmd->cmd = 0;
6060 cmd->src = msm_virt_to_dma(chip, &dma_buffer->data.addr0);
6061 cmd->dst = MSM_NAND_ADDR0;
6062 cmd->len = 8;
6063 cmd++;
6064
6065 /* Write the ADDR2 ADDR3 ADDR4 ADDR5 registers */
6066 cmd->cmd = 0;
6067 cmd->src = msm_virt_to_dma(chip, &dma_buffer->data.addr2);
6068 cmd->dst = MSM_NAND_ADDR2;
6069 cmd->len = 16;
6070 cmd++;
6071
6072 /* Write the ADDR6 registers */
6073 cmd->cmd = 0;
6074 cmd->src = msm_virt_to_dma(chip, &dma_buffer->data.addr6);
6075 cmd->dst = MSM_NAND_ADDR6;
6076 cmd->len = 4;
6077 cmd++;
6078
6079 /* Write the GENP0, GENP1, GENP2, GENP3, GENP4 registers */
6080 cmd->cmd = 0;
6081 cmd->src = msm_virt_to_dma(chip, &dma_buffer->data.data0);
6082 cmd->dst = MSM_NAND_GENP_REG0;
6083 cmd->len = 16;
6084 cmd++;
6085
6086 /* Write the FLASH_DEV_CMD4,5,6 registers */
6087 cmd->cmd = 0;
6088 cmd->src = msm_virt_to_dma(chip, &dma_buffer->data.data4);
6089 cmd->dst = MSM_NAND_DEV_CMD4;
6090 cmd->len = 12;
6091 cmd++;
6092
6093 /* Kick the execute command */
6094 cmd->cmd = 0;
6095 cmd->src = msm_virt_to_dma(chip, &dma_buffer->data.sfexec);
6096 cmd->dst = MSM_NAND_SFLASHC_EXEC_CMD;
6097 cmd->len = 4;
6098 cmd++;
6099
6100 /* Block on data ready, and read the status register */
6101 cmd->cmd = SRC_CRCI_NAND_DATA;
6102 cmd->src = MSM_NAND_SFLASHC_STATUS;
6103 cmd->dst = msm_virt_to_dma(chip, &dma_buffer->data.sfstat[0]);
6104 cmd->len = 4;
6105 cmd++;
6106
6107 /*************************************************************/
6108 /* Wait for the interrupt from the Onenand device controller */
6109 /*************************************************************/
6110
6111 /* Block on cmd ready and write CMD register */
6112 cmd->cmd = DST_CRCI_NAND_CMD;
6113 cmd->src = msm_virt_to_dma(chip, &dma_buffer->data.sfcmd[1]);
6114 cmd->dst = MSM_NAND_SFLASHC_CMD;
6115 cmd->len = 4;
6116 cmd++;
6117
6118 /* Kick the execute command */
6119 cmd->cmd = 0;
6120 cmd->src = msm_virt_to_dma(chip, &dma_buffer->data.sfexec);
6121 cmd->dst = MSM_NAND_SFLASHC_EXEC_CMD;
6122 cmd->len = 4;
6123 cmd++;
6124
6125 /* Block on data ready, and read the status register */
6126 cmd->cmd = SRC_CRCI_NAND_DATA;
6127 cmd->src = MSM_NAND_SFLASHC_STATUS;
6128 cmd->dst = msm_virt_to_dma(chip, &dma_buffer->data.sfstat[1]);
6129 cmd->len = 4;
6130 cmd++;
6131
6132 /*********************************************************/
6133 /* Read the necessary status reg from the onenand device */
6134 /*********************************************************/
6135
6136 /* Block on cmd ready and write CMD register */
6137 cmd->cmd = DST_CRCI_NAND_CMD;
6138 cmd->src = msm_virt_to_dma(chip, &dma_buffer->data.sfcmd[2]);
6139 cmd->dst = MSM_NAND_SFLASHC_CMD;
6140 cmd->len = 4;
6141 cmd++;
6142
6143 /* Kick the execute command */
6144 cmd->cmd = 0;
6145 cmd->src = msm_virt_to_dma(chip, &dma_buffer->data.sfexec);
6146 cmd->dst = MSM_NAND_SFLASHC_EXEC_CMD;
6147 cmd->len = 4;
6148 cmd++;
6149
6150 /* Block on data ready, and read the status register */
6151 cmd->cmd = SRC_CRCI_NAND_DATA;
6152 cmd->src = MSM_NAND_SFLASHC_STATUS;
6153 cmd->dst = msm_virt_to_dma(chip, &dma_buffer->data.sfstat[2]);
6154 cmd->len = 4;
6155 cmd++;
6156
6157 /* Read the GENP3 register */
6158 cmd->cmd = 0;
6159 cmd->src = MSM_NAND_GENP_REG3;
6160 cmd->dst = msm_virt_to_dma(chip, &dma_buffer->data.data3);
6161 cmd->len = 4;
6162 cmd++;
6163
6164 /* Read the DEVCMD4 register */
6165 cmd->cmd = 0;
6166 cmd->src = MSM_NAND_DEV_CMD4;
6167 cmd->dst = msm_virt_to_dma(chip, &dma_buffer->data.data4);
6168 cmd->len = 4;
6169 cmd++;
6170
6171 /************************************************************/
6172 /* Restore the necessary registers to proper values */
6173 /************************************************************/
6174
6175 /* Block on cmd ready and write CMD register */
6176 cmd->cmd = DST_CRCI_NAND_CMD;
6177 cmd->src = msm_virt_to_dma(chip, &dma_buffer->data.sfcmd[3]);
6178 cmd->dst = MSM_NAND_SFLASHC_CMD;
6179 cmd->len = 4;
6180 cmd++;
6181
6182 /* Kick the execute command */
6183 cmd->cmd = 0;
6184 cmd->src = msm_virt_to_dma(chip, &dma_buffer->data.sfexec);
6185 cmd->dst = MSM_NAND_SFLASHC_EXEC_CMD;
6186 cmd->len = 4;
6187 cmd++;
6188
6189 /* Block on data ready, and read the status register */
6190 cmd->cmd = SRC_CRCI_NAND_DATA;
6191 cmd->src = MSM_NAND_SFLASHC_STATUS;
6192 cmd->dst = msm_virt_to_dma(chip, &dma_buffer->data.sfstat[3]);
6193 cmd->len = 4;
6194 cmd++;
6195
6196
6197 BUILD_BUG_ON(20 != ARRAY_SIZE(dma_buffer->cmd));
6198 BUG_ON(cmd - dma_buffer->cmd > ARRAY_SIZE(dma_buffer->cmd));
6199 dma_buffer->cmd[0].cmd |= CMD_OCB;
6200 cmd[-1].cmd |= CMD_OCU | CMD_LC;
6201
6202 dma_buffer->cmdptr = (msm_virt_to_dma(chip, dma_buffer->cmd)
6203 >> 3) | CMD_PTR_LP;
6204
6205 mb();
6206 msm_dmov_exec_cmd(chip->dma_channel, crci_mask,
6207 DMOV_CMD_PTR_LIST | DMOV_CMD_ADDR(msm_virt_to_dma(chip,
6208 &dma_buffer->cmdptr)));
6209 mb();
6210
6211 write_prot_status = (dma_buffer->data.data3 >> 16) & 0x0000FFFF;
6212 interrupt_status = (dma_buffer->data.data4 >> 0) & 0x0000FFFF;
6213 controller_status = (dma_buffer->data.data4 >> 16) & 0x0000FFFF;
6214
6215#if VERBOSE
6216 pr_info("\n%s: sflash status %x %x %x %x\n", __func__,
6217 dma_buffer->data.sfstat[0],
6218 dma_buffer->data.sfstat[1],
6219 dma_buffer->data.sfstat[2],
6220 dma_buffer->data.sfstat[3]);
6221
6222 pr_info("%s: controller_status = %x\n", __func__,
6223 controller_status);
6224 pr_info("%s: interrupt_status = %x\n", __func__,
6225 interrupt_status);
6226 pr_info("%s: write_prot_status = %x\n", __func__,
6227 write_prot_status);
6228#endif
6229 /* Check for errors, protection violations etc */
6230 if ((controller_status != 0)
6231 || (dma_buffer->data.sfstat[0] & 0x110)
6232 || (dma_buffer->data.sfstat[1] & 0x110)
6233 || (dma_buffer->data.sfstat[2] & 0x110)
6234 || (dma_buffer->data.sfstat[3] & 0x110)) {
6235 pr_err("%s: ECC/MPU/OP error\n", __func__);
6236 err = -EIO;
6237 }
6238
6239 if (!(write_prot_status & ONENAND_WP_US)) {
6240 pr_err("%s: Unexpected status ofs = 0x%llx,"
6241 "wp_status = %x\n",
6242 __func__, ofs, write_prot_status);
6243 err = -EIO;
6244 }
6245
6246 if (err)
6247 break;
6248 }
6249
6250 msm_nand_release_dma_buffer(chip, dma_buffer, sizeof(*dma_buffer));
6251
6252#if VERBOSE
6253 pr_info("\n%s: ret %d\n", __func__, err);
6254 pr_info("===================================================="
6255 "=============\n");
6256#endif
6257 return err;
6258}
6259
6260static int msm_onenand_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
6261{
6262 struct msm_nand_chip *chip = mtd->priv;
6263
6264 struct {
6265 dmov_s cmd[20];
6266 unsigned cmdptr;
6267 struct {
6268 uint32_t sfbcfg;
6269 uint32_t sfcmd[4];
6270 uint32_t sfexec;
6271 uint32_t sfstat[4];
6272 uint32_t addr0;
6273 uint32_t addr1;
6274 uint32_t addr2;
6275 uint32_t addr3;
6276 uint32_t addr4;
6277 uint32_t addr5;
6278 uint32_t addr6;
6279 uint32_t data0;
6280 uint32_t data1;
6281 uint32_t data2;
6282 uint32_t data3;
6283 uint32_t data4;
6284 uint32_t data5;
6285 uint32_t data6;
6286 } data;
6287 } *dma_buffer;
6288 dmov_s *cmd;
6289
6290 int err = 0;
6291
6292 uint16_t onenand_startaddr1;
6293 uint16_t onenand_startaddr8;
6294 uint16_t onenand_startaddr2;
6295 uint16_t onenand_startblock;
6296
6297 uint16_t controller_status;
6298 uint16_t interrupt_status;
6299 uint16_t write_prot_status;
6300
6301 uint64_t start_ofs;
6302
6303#if VERBOSE
6304 pr_info("===================================================="
6305 "=============\n");
6306 pr_info("%s: ofs 0x%llx len %lld\n", __func__, ofs, len);
6307#endif
6308 /* 'ofs' & 'len' should align to block size */
6309 if (ofs&(mtd->erasesize - 1)) {
6310 pr_err("%s: Unsupported ofs address, 0x%llx\n",
6311 __func__, ofs);
6312 return -EINVAL;
6313 }
6314
6315 if (len&(mtd->erasesize - 1)) {
6316 pr_err("%s: Unsupported len, %lld\n",
6317 __func__, len);
6318 return -EINVAL;
6319 }
6320
6321 if (ofs+len > mtd->size) {
6322 pr_err("%s: Maximum chip size exceeded\n", __func__);
6323 return -EINVAL;
6324 }
6325
6326 wait_event(chip->wait_queue, (dma_buffer = msm_nand_get_dma_buffer
6327 (chip, sizeof(*dma_buffer))));
6328
6329 for (start_ofs = ofs; ofs < start_ofs+len; ofs = ofs+mtd->erasesize) {
6330#if VERBOSE
6331 pr_info("%s: ofs 0x%llx len %lld\n", __func__, ofs, len);
6332#endif
6333
6334 cmd = dma_buffer->cmd;
6335 if ((onenand_info.device_id & ONENAND_DEVICE_IS_DDP)
6336 && (ofs >= (mtd->size>>1))) { /* DDP Device */
6337 onenand_startaddr1 = DEVICE_FLASHCORE_1 |
6338 (((uint32_t)(ofs - (mtd->size>>1))
6339 / mtd->erasesize));
6340 onenand_startaddr2 = DEVICE_BUFFERRAM_1;
6341 onenand_startblock = ((uint32_t)(ofs - (mtd->size>>1))
6342 / mtd->erasesize);
6343 } else {
6344 onenand_startaddr1 = DEVICE_FLASHCORE_0 |
6345 ((uint32_t)ofs / mtd->erasesize) ;
6346 onenand_startaddr2 = DEVICE_BUFFERRAM_0;
6347 onenand_startblock = ((uint32_t)ofs
6348 / mtd->erasesize);
6349 }
6350
6351 onenand_startaddr8 = 0x0000;
6352 dma_buffer->data.sfbcfg = SFLASH_BCFG |
6353 (nand_sfcmd_mode ? 0 : (1 << 24));
6354 dma_buffer->data.sfcmd[0] = SFLASH_PREPCMD(7, 0, 0,
6355 MSM_NAND_SFCMD_CMDXS,
6356 nand_sfcmd_mode,
6357 MSM_NAND_SFCMD_REGWR);
6358 dma_buffer->data.sfcmd[1] = SFLASH_PREPCMD(0, 0, 32,
6359 MSM_NAND_SFCMD_CMDXS,
6360 nand_sfcmd_mode,
6361 MSM_NAND_SFCMD_INTHI);
6362 dma_buffer->data.sfcmd[2] = SFLASH_PREPCMD(3, 7, 0,
6363 MSM_NAND_SFCMD_DATXS,
6364 nand_sfcmd_mode,
6365 MSM_NAND_SFCMD_REGRD);
6366 dma_buffer->data.sfcmd[3] = SFLASH_PREPCMD(4, 10, 0,
6367 MSM_NAND_SFCMD_CMDXS,
6368 nand_sfcmd_mode,
6369 MSM_NAND_SFCMD_REGWR);
6370 dma_buffer->data.sfexec = 1;
6371 dma_buffer->data.sfstat[0] = CLEAN_DATA_32;
6372 dma_buffer->data.sfstat[1] = CLEAN_DATA_32;
6373 dma_buffer->data.sfstat[2] = CLEAN_DATA_32;
6374 dma_buffer->data.sfstat[3] = CLEAN_DATA_32;
6375 dma_buffer->data.addr0 = (ONENAND_INTERRUPT_STATUS << 16) |
6376 (ONENAND_SYSTEM_CONFIG_1);
6377 dma_buffer->data.addr1 = (ONENAND_START_ADDRESS_8 << 16) |
6378 (ONENAND_START_ADDRESS_1);
6379 dma_buffer->data.addr2 = (ONENAND_START_BLOCK_ADDRESS << 16) |
6380 (ONENAND_START_ADDRESS_2);
6381 dma_buffer->data.addr3 = (ONENAND_WRITE_PROT_STATUS << 16) |
6382 (ONENAND_COMMAND);
6383 dma_buffer->data.addr4 = (ONENAND_CONTROLLER_STATUS << 16) |
6384 (ONENAND_INTERRUPT_STATUS);
6385 dma_buffer->data.addr5 = (ONENAND_INTERRUPT_STATUS << 16) |
6386 (ONENAND_SYSTEM_CONFIG_1);
6387 dma_buffer->data.addr6 = (ONENAND_START_ADDRESS_3 << 16) |
6388 (ONENAND_START_ADDRESS_1);
6389 dma_buffer->data.data0 = (ONENAND_CLRINTR << 16) |
6390 (ONENAND_SYSCFG1_ECCENA(nand_sfcmd_mode));
6391 dma_buffer->data.data1 = (onenand_startaddr8 << 16) |
6392 (onenand_startaddr1);
6393 dma_buffer->data.data2 = (onenand_startblock << 16) |
6394 (onenand_startaddr2);
6395 dma_buffer->data.data3 = (CLEAN_DATA_16 << 16) |
6396 (ONENAND_CMD_LOCK);
6397 dma_buffer->data.data4 = (CLEAN_DATA_16 << 16) |
6398 (CLEAN_DATA_16);
6399 dma_buffer->data.data5 = (ONENAND_CLRINTR << 16) |
6400 (ONENAND_SYSCFG1_ECCENA(nand_sfcmd_mode));
6401 dma_buffer->data.data6 = (ONENAND_STARTADDR3_RES << 16) |
6402 (ONENAND_STARTADDR1_RES);
6403
6404 /*************************************************************/
6405 /* Write the necessary address reg in the onenand device */
6406 /*************************************************************/
6407
6408 /* Enable and configure the SFlash controller */
6409 cmd->cmd = 0;
6410 cmd->src = msm_virt_to_dma(chip, &dma_buffer->data.sfbcfg);
6411 cmd->dst = MSM_NAND_SFLASHC_BURST_CFG;
6412 cmd->len = 4;
6413 cmd++;
6414
6415 /* Block on cmd ready and write CMD register */
6416 cmd->cmd = DST_CRCI_NAND_CMD;
6417 cmd->src = msm_virt_to_dma(chip, &dma_buffer->data.sfcmd[0]);
6418 cmd->dst = MSM_NAND_SFLASHC_CMD;
6419 cmd->len = 4;
6420 cmd++;
6421
6422 /* Write the ADDR0 and ADDR1 registers */
6423 cmd->cmd = 0;
6424 cmd->src = msm_virt_to_dma(chip, &dma_buffer->data.addr0);
6425 cmd->dst = MSM_NAND_ADDR0;
6426 cmd->len = 8;
6427 cmd++;
6428
6429 /* Write the ADDR2 ADDR3 ADDR4 ADDR5 registers */
6430 cmd->cmd = 0;
6431 cmd->src = msm_virt_to_dma(chip, &dma_buffer->data.addr2);
6432 cmd->dst = MSM_NAND_ADDR2;
6433 cmd->len = 16;
6434 cmd++;
6435
6436 /* Write the ADDR6 registers */
6437 cmd->cmd = 0;
6438 cmd->src = msm_virt_to_dma(chip, &dma_buffer->data.addr6);
6439 cmd->dst = MSM_NAND_ADDR6;
6440 cmd->len = 4;
6441 cmd++;
6442
6443 /* Write the GENP0, GENP1, GENP2, GENP3, GENP4 registers */
6444 cmd->cmd = 0;
6445 cmd->src = msm_virt_to_dma(chip, &dma_buffer->data.data0);
6446 cmd->dst = MSM_NAND_GENP_REG0;
6447 cmd->len = 16;
6448 cmd++;
6449
6450 /* Write the FLASH_DEV_CMD4,5,6 registers */
6451 cmd->cmd = 0;
6452 cmd->src = msm_virt_to_dma(chip, &dma_buffer->data.data4);
6453 cmd->dst = MSM_NAND_DEV_CMD4;
6454 cmd->len = 12;
6455 cmd++;
6456
6457 /* Kick the execute command */
6458 cmd->cmd = 0;
6459 cmd->src = msm_virt_to_dma(chip, &dma_buffer->data.sfexec);
6460 cmd->dst = MSM_NAND_SFLASHC_EXEC_CMD;
6461 cmd->len = 4;
6462 cmd++;
6463
6464 /* Block on data ready, and read the status register */
6465 cmd->cmd = SRC_CRCI_NAND_DATA;
6466 cmd->src = MSM_NAND_SFLASHC_STATUS;
6467 cmd->dst = msm_virt_to_dma(chip, &dma_buffer->data.sfstat[0]);
6468 cmd->len = 4;
6469 cmd++;
6470
6471 /*************************************************************/
6472 /* Wait for the interrupt from the Onenand device controller */
6473 /*************************************************************/
6474
6475 /* Block on cmd ready and write CMD register */
6476 cmd->cmd = DST_CRCI_NAND_CMD;
6477 cmd->src = msm_virt_to_dma(chip, &dma_buffer->data.sfcmd[1]);
6478 cmd->dst = MSM_NAND_SFLASHC_CMD;
6479 cmd->len = 4;
6480 cmd++;
6481
6482 /* Kick the execute command */
6483 cmd->cmd = 0;
6484 cmd->src = msm_virt_to_dma(chip, &dma_buffer->data.sfexec);
6485 cmd->dst = MSM_NAND_SFLASHC_EXEC_CMD;
6486 cmd->len = 4;
6487 cmd++;
6488
6489 /* Block on data ready, and read the status register */
6490 cmd->cmd = SRC_CRCI_NAND_DATA;
6491 cmd->src = MSM_NAND_SFLASHC_STATUS;
6492 cmd->dst = msm_virt_to_dma(chip, &dma_buffer->data.sfstat[1]);
6493 cmd->len = 4;
6494 cmd++;
6495
6496 /*********************************************************/
6497 /* Read the necessary status reg from the onenand device */
6498 /*********************************************************/
6499
6500 /* Block on cmd ready and write CMD register */
6501 cmd->cmd = DST_CRCI_NAND_CMD;
6502 cmd->src = msm_virt_to_dma(chip, &dma_buffer->data.sfcmd[2]);
6503 cmd->dst = MSM_NAND_SFLASHC_CMD;
6504 cmd->len = 4;
6505 cmd++;
6506
6507 /* Kick the execute command */
6508 cmd->cmd = 0;
6509 cmd->src = msm_virt_to_dma(chip, &dma_buffer->data.sfexec);
6510 cmd->dst = MSM_NAND_SFLASHC_EXEC_CMD;
6511 cmd->len = 4;
6512 cmd++;
6513
6514 /* Block on data ready, and read the status register */
6515 cmd->cmd = SRC_CRCI_NAND_DATA;
6516 cmd->src = MSM_NAND_SFLASHC_STATUS;
6517 cmd->dst = msm_virt_to_dma(chip, &dma_buffer->data.sfstat[2]);
6518 cmd->len = 4;
6519 cmd++;
6520
6521 /* Read the GENP3 register */
6522 cmd->cmd = 0;
6523 cmd->src = MSM_NAND_GENP_REG3;
6524 cmd->dst = msm_virt_to_dma(chip, &dma_buffer->data.data3);
6525 cmd->len = 4;
6526 cmd++;
6527
6528 /* Read the DEVCMD4 register */
6529 cmd->cmd = 0;
6530 cmd->src = MSM_NAND_DEV_CMD4;
6531 cmd->dst = msm_virt_to_dma(chip, &dma_buffer->data.data4);
6532 cmd->len = 4;
6533 cmd++;
6534
6535 /************************************************************/
6536 /* Restore the necessary registers to proper values */
6537 /************************************************************/
6538
6539 /* Block on cmd ready and write CMD register */
6540 cmd->cmd = DST_CRCI_NAND_CMD;
6541 cmd->src = msm_virt_to_dma(chip, &dma_buffer->data.sfcmd[3]);
6542 cmd->dst = MSM_NAND_SFLASHC_CMD;
6543 cmd->len = 4;
6544 cmd++;
6545
6546 /* Kick the execute command */
6547 cmd->cmd = 0;
6548 cmd->src = msm_virt_to_dma(chip, &dma_buffer->data.sfexec);
6549 cmd->dst = MSM_NAND_SFLASHC_EXEC_CMD;
6550 cmd->len = 4;
6551 cmd++;
6552
6553 /* Block on data ready, and read the status register */
6554 cmd->cmd = SRC_CRCI_NAND_DATA;
6555 cmd->src = MSM_NAND_SFLASHC_STATUS;
6556 cmd->dst = msm_virt_to_dma(chip, &dma_buffer->data.sfstat[3]);
6557 cmd->len = 4;
6558 cmd++;
6559
6560
6561 BUILD_BUG_ON(20 != ARRAY_SIZE(dma_buffer->cmd));
6562 BUG_ON(cmd - dma_buffer->cmd > ARRAY_SIZE(dma_buffer->cmd));
6563 dma_buffer->cmd[0].cmd |= CMD_OCB;
6564 cmd[-1].cmd |= CMD_OCU | CMD_LC;
6565
6566 dma_buffer->cmdptr = (msm_virt_to_dma(chip, dma_buffer->cmd)
6567 >> 3) | CMD_PTR_LP;
6568
6569 mb();
6570 msm_dmov_exec_cmd(chip->dma_channel, crci_mask,
6571 DMOV_CMD_PTR_LIST | DMOV_CMD_ADDR(msm_virt_to_dma(chip,
6572 &dma_buffer->cmdptr)));
6573 mb();
6574
6575 write_prot_status = (dma_buffer->data.data3 >> 16) & 0x0000FFFF;
6576 interrupt_status = (dma_buffer->data.data4 >> 0) & 0x0000FFFF;
6577 controller_status = (dma_buffer->data.data4 >> 16) & 0x0000FFFF;
6578
6579#if VERBOSE
6580 pr_info("\n%s: sflash status %x %x %x %x\n", __func__,
6581 dma_buffer->data.sfstat[0],
6582 dma_buffer->data.sfstat[1],
6583 dma_buffer->data.sfstat[2],
6584 dma_buffer->data.sfstat[3]);
6585
6586 pr_info("%s: controller_status = %x\n", __func__,
6587 controller_status);
6588 pr_info("%s: interrupt_status = %x\n", __func__,
6589 interrupt_status);
6590 pr_info("%s: write_prot_status = %x\n", __func__,
6591 write_prot_status);
6592#endif
6593 /* Check for errors, protection violations etc */
6594 if ((controller_status != 0)
6595 || (dma_buffer->data.sfstat[0] & 0x110)
6596 || (dma_buffer->data.sfstat[1] & 0x110)
6597 || (dma_buffer->data.sfstat[2] & 0x110)
6598 || (dma_buffer->data.sfstat[3] & 0x110)) {
6599 pr_err("%s: ECC/MPU/OP error\n", __func__);
6600 err = -EIO;
6601 }
6602
6603 if (!(write_prot_status & ONENAND_WP_LS)) {
6604 pr_err("%s: Unexpected status ofs = 0x%llx,"
6605 "wp_status = %x\n",
6606 __func__, ofs, write_prot_status);
6607 err = -EIO;
6608 }
6609
6610 if (err)
6611 break;
6612 }
6613
6614 msm_nand_release_dma_buffer(chip, dma_buffer, sizeof(*dma_buffer));
6615
6616#if VERBOSE
6617 pr_info("\n%s: ret %d\n", __func__, err);
6618 pr_info("===================================================="
6619 "=============\n");
6620#endif
6621 return err;
6622}
6623
6624static int msm_onenand_suspend(struct mtd_info *mtd)
6625{
6626 return 0;
6627}
6628
6629static void msm_onenand_resume(struct mtd_info *mtd)
6630{
6631}
6632
6633int msm_onenand_scan(struct mtd_info *mtd, int maxchips)
6634{
6635 struct msm_nand_chip *chip = mtd->priv;
6636
6637 /* Probe and check whether onenand device is present */
6638 if (flash_onenand_probe(chip))
6639 return -ENODEV;
6640
6641 mtd->size = 0x1000000 << ((onenand_info.device_id & 0xF0) >> 4);
6642 mtd->writesize = onenand_info.data_buf_size;
6643 mtd->oobsize = mtd->writesize >> 5;
6644 mtd->erasesize = mtd->writesize << 6;
6645 mtd->oobavail = msm_onenand_oob_64.oobavail;
6646 mtd->ecclayout = &msm_onenand_oob_64;
6647
6648 mtd->type = MTD_NANDFLASH;
6649 mtd->flags = MTD_CAP_NANDFLASH;
6650 mtd->erase = msm_onenand_erase;
6651 mtd->point = NULL;
6652 mtd->unpoint = NULL;
6653 mtd->read = msm_onenand_read;
6654 mtd->write = msm_onenand_write;
6655 mtd->read_oob = msm_onenand_read_oob;
6656 mtd->write_oob = msm_onenand_write_oob;
6657 mtd->lock = msm_onenand_lock;
6658 mtd->unlock = msm_onenand_unlock;
6659 mtd->suspend = msm_onenand_suspend;
6660 mtd->resume = msm_onenand_resume;
6661 mtd->block_isbad = msm_onenand_block_isbad;
6662 mtd->block_markbad = msm_onenand_block_markbad;
6663 mtd->owner = THIS_MODULE;
6664
6665 pr_info("Found a supported onenand device\n");
6666
6667 return 0;
6668}
6669
6670/**
6671 * msm_nand_scan - [msm_nand Interface] Scan for the msm_nand device
6672 * @param mtd MTD device structure
6673 * @param maxchips Number of chips to scan for
6674 *
6675 * This fills out all the not initialized function pointers
6676 * with the defaults.
6677 * The flash ID is read and the mtd/chip structures are
6678 * filled with the appropriate values.
6679 */
6680int msm_nand_scan(struct mtd_info *mtd, int maxchips)
6681{
6682 struct msm_nand_chip *chip = mtd->priv;
6683 uint32_t flash_id = 0, i, mtd_writesize;
6684 uint8_t dev_found = 0;
6685 uint8_t wide_bus;
6686 uint32_t manid;
6687 uint32_t devid;
6688 uint32_t devcfg;
6689 struct nand_flash_dev *flashdev = NULL;
6690 struct nand_manufacturers *flashman = NULL;
6691
6692 /* Probe the Flash device for ONFI compliance */
6693 if (!flash_onfi_probe(chip)) {
6694 dev_found = 1;
6695 } else {
6696 /* Read the Flash ID from the Nand Flash Device */
6697 flash_id = flash_read_id(chip);
6698 manid = flash_id & 0xFF;
6699 devid = (flash_id >> 8) & 0xFF;
6700 devcfg = (flash_id >> 24) & 0xFF;
6701
6702 for (i = 0; !flashman && nand_manuf_ids[i].id; ++i)
6703 if (nand_manuf_ids[i].id == manid)
6704 flashman = &nand_manuf_ids[i];
6705 for (i = 0; !flashdev && nand_flash_ids[i].id; ++i)
6706 if (nand_flash_ids[i].id == devid)
6707 flashdev = &nand_flash_ids[i];
6708 if (!flashdev || !flashman) {
6709 pr_err("ERROR: unknown nand device manuf=%x devid=%x\n",
6710 manid, devid);
6711 return -ENOENT;
6712 } else
6713 dev_found = 1;
6714
6715 if (!flashdev->pagesize) {
6716 supported_flash.flash_id = flash_id;
6717 supported_flash.density = flashdev->chipsize << 20;
6718 supported_flash.widebus = devcfg & (1 << 6) ? 1 : 0;
6719 supported_flash.pagesize = 1024 << (devcfg & 0x3);
6720 supported_flash.blksize = (64 * 1024) <<
6721 ((devcfg >> 4) & 0x3);
6722 supported_flash.oobsize = (8 << ((devcfg >> 2) & 1)) *
6723 (supported_flash.pagesize >> 9);
6724 } else {
6725 supported_flash.flash_id = flash_id;
6726 supported_flash.density = flashdev->chipsize << 20;
6727 supported_flash.widebus = flashdev->options &
6728 NAND_BUSWIDTH_16 ? 1 : 0;
6729 supported_flash.pagesize = flashdev->pagesize;
6730 supported_flash.blksize = flashdev->erasesize;
6731 supported_flash.oobsize = flashdev->pagesize >> 5;
6732 }
6733 }
6734
6735 if (dev_found) {
6736 (!interleave_enable) ? (i = 1) : (i = 2);
6737 wide_bus = supported_flash.widebus;
6738 mtd->size = supported_flash.density * i;
6739 mtd->writesize = supported_flash.pagesize * i;
6740 mtd->oobsize = supported_flash.oobsize * i;
6741 mtd->erasesize = supported_flash.blksize * i;
6742
6743 if (!interleave_enable)
6744 mtd_writesize = mtd->writesize;
6745 else
6746 mtd_writesize = mtd->writesize >> 1;
6747
6748 /* Check whether controller and NAND device support 8bit ECC*/
6749 if ((flash_rd_reg(chip, MSM_NAND_HW_INFO) == 0x307)
6750 && (supported_flash.ecc_correctability >= 8)) {
6751 pr_info("Found supported NAND device for %dbit ECC\n",
6752 supported_flash.ecc_correctability);
6753 enable_bch_ecc = 1;
6754 } else {
6755 pr_info("Found a supported NAND device\n");
6756 }
6757 pr_info("NAND Id : 0x%x\n", supported_flash.flash_id);
6758 pr_info("Buswidth : %d Bits\n", (wide_bus) ? 16 : 8);
6759 pr_info("Density : %lld MByte\n", (mtd->size>>20));
6760 pr_info("Pagesize : %d Bytes\n", mtd->writesize);
6761 pr_info("Erasesize: %d Bytes\n", mtd->erasesize);
6762 pr_info("Oobsize : %d Bytes\n", mtd->oobsize);
6763 } else {
6764 pr_err("Unsupported Nand,Id: 0x%x \n", flash_id);
6765 return -ENODEV;
6766 }
6767
6768 /* Size of each codeword is 532Bytes incase of 8bit BCH ECC*/
6769 chip->cw_size = enable_bch_ecc ? 532 : 528;
6770 chip->CFG0 = (((mtd_writesize >> 9)-1) << 6) /* 4/8 cw/pg for 2/4k */
6771 | (516 << 9) /* 516 user data bytes */
6772 | (10 << 19) /* 10 parity bytes */
6773 | (5 << 27) /* 5 address cycles */
6774 | (0 << 30) /* Do not read status before data */
6775 | (1 << 31) /* Send read cmd */
6776 /* 0 spare bytes for 16 bit nand or 1/2 spare bytes for 8 bit */
6777 | (wide_bus ? 0 << 23 : (enable_bch_ecc ? 2 << 23 : 1 << 23));
6778
6779 chip->CFG1 = (0 << 0) /* Enable ecc */
6780 | (7 << 2) /* 8 recovery cycles */
6781 | (0 << 5) /* Allow CS deassertion */
6782 /* Bad block marker location */
6783 | ((mtd_writesize - (chip->cw_size * (
6784 (mtd_writesize >> 9) - 1)) + 1) << 6)
6785 | (0 << 16) /* Bad block in user data area */
6786 | (2 << 17) /* 6 cycle tWB/tRB */
6787 | ((wide_bus) ? CFG1_WIDE_FLASH : 0); /* Wide flash bit */
6788
6789 chip->ecc_buf_cfg = 0x203;
6790 chip->CFG0_RAW = 0xA80420C0;
6791 chip->CFG1_RAW = 0x5045D;
6792
6793 if (enable_bch_ecc) {
6794 chip->CFG1 |= (1 << 27); /* Enable BCH engine */
6795 chip->ecc_bch_cfg = (0 << 0) /* Enable ECC*/
6796 | (0 << 1) /* Enable/Disable SW reset of ECC engine */
6797 | (1 << 4) /* 8bit ecc*/
6798 | ((wide_bus) ? (14 << 8) : (13 << 8))/*parity bytes*/
6799 | (516 << 16) /* 516 user data bytes */
6800 | (1 << 30); /* Turn on ECC engine clocks always */
6801 chip->CFG0_RAW = 0xA80428C0; /* CW size is increased to 532B */
6802 }
6803
6804 /*
6805 * For 4bit RS ECC (default ECC), parity bytes = 10 (for x8 and x16 I/O)
6806 * For 8bit BCH ECC, parity bytes = 13 (x8) or 14 (x16 I/O).
6807 */
6808 chip->ecc_parity_bytes = enable_bch_ecc ? (wide_bus ? 14 : 13) : 10;
6809
6810 pr_info("CFG0 Init : 0x%08x\n", chip->CFG0);
6811 pr_info("CFG1 Init : 0x%08x\n", chip->CFG1);
6812 pr_info("ECCBUFCFG : 0x%08x\n", chip->ecc_buf_cfg);
6813
6814 if (mtd->oobsize == 64) {
6815 mtd->oobavail = msm_nand_oob_64.oobavail;
6816 mtd->ecclayout = &msm_nand_oob_64;
6817 } else if (mtd->oobsize == 128) {
6818 mtd->oobavail = msm_nand_oob_128.oobavail;
6819 mtd->ecclayout = &msm_nand_oob_128;
6820 } else if (mtd->oobsize == 224) {
6821 mtd->oobavail = wide_bus ? msm_nand_oob_224_x16.oobavail :
6822 msm_nand_oob_224_x8.oobavail;
6823 mtd->ecclayout = wide_bus ? &msm_nand_oob_224_x16 :
6824 &msm_nand_oob_224_x8;
6825 } else if (mtd->oobsize == 256) {
6826 mtd->oobavail = msm_nand_oob_256.oobavail;
6827 mtd->ecclayout = &msm_nand_oob_256;
6828 } else {
6829 pr_err("Unsupported Nand, oobsize: 0x%x \n",
6830 mtd->oobsize);
6831 return -ENODEV;
6832 }
6833
6834 /* Fill in remaining MTD driver data */
6835 mtd->type = MTD_NANDFLASH;
6836 mtd->flags = MTD_CAP_NANDFLASH;
6837 /* mtd->ecctype = MTD_ECC_SW; */
6838 mtd->erase = msm_nand_erase;
6839 mtd->block_isbad = msm_nand_block_isbad;
6840 mtd->block_markbad = msm_nand_block_markbad;
6841 mtd->point = NULL;
6842 mtd->unpoint = NULL;
6843 mtd->read = msm_nand_read;
6844 mtd->write = msm_nand_write;
6845 mtd->read_oob = msm_nand_read_oob;
6846 mtd->write_oob = msm_nand_write_oob;
6847 if (dual_nand_ctlr_present) {
6848 mtd->read_oob = msm_nand_read_oob_dualnandc;
6849 mtd->write_oob = msm_nand_write_oob_dualnandc;
6850 if (interleave_enable) {
6851 mtd->erase = msm_nand_erase_dualnandc;
6852 mtd->block_isbad = msm_nand_block_isbad_dualnandc;
6853 }
6854 }
6855
6856 /* mtd->sync = msm_nand_sync; */
6857 mtd->lock = NULL;
6858 /* mtd->unlock = msm_nand_unlock; */
6859 mtd->suspend = msm_nand_suspend;
6860 mtd->resume = msm_nand_resume;
6861 mtd->owner = THIS_MODULE;
6862
6863 /* Unlock whole block */
6864 /* msm_nand_unlock_all(mtd); */
6865
6866 /* return this->scan_bbt(mtd); */
6867 return 0;
6868}
6869EXPORT_SYMBOL_GPL(msm_nand_scan);
6870
6871/**
6872 * msm_nand_release - [msm_nand Interface] Free resources held by the msm_nand device
6873 * @param mtd MTD device structure
6874 */
6875void msm_nand_release(struct mtd_info *mtd)
6876{
6877 /* struct msm_nand_chip *this = mtd->priv; */
6878
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]6879 /* Deregister the device */
6880 mtd_device_unregister(mtd);
6881}
6882EXPORT_SYMBOL_GPL(msm_nand_release);
6883
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]6884struct msm_nand_info {
6885 struct mtd_info mtd;
6886 struct mtd_partition *parts;
6887 struct msm_nand_chip msm_nand;
6888};
6889
6890/* duplicating the NC01 XFR contents to NC10 */
6891static int msm_nand_nc10_xfr_settings(struct mtd_info *mtd)
6892{
6893 struct msm_nand_chip *chip = mtd->priv;
6894
6895 struct {
6896 dmov_s cmd[2];
6897 unsigned cmdptr;
6898 } *dma_buffer;
6899 dmov_s *cmd;
6900
6901 wait_event(chip->wait_queue,
6902 (dma_buffer = msm_nand_get_dma_buffer(
6903 chip, sizeof(*dma_buffer))));
6904
6905 cmd = dma_buffer->cmd;
6906
6907 /* Copying XFR register contents from NC01 --> NC10 */
6908 cmd->cmd = 0;
6909 cmd->src = NC01(MSM_NAND_XFR_STEP1);
6910 cmd->dst = NC10(MSM_NAND_XFR_STEP1);
6911 cmd->len = 28;
6912 cmd++;
6913
6914 BUILD_BUG_ON(2 != ARRAY_SIZE(dma_buffer->cmd));
6915 BUG_ON(cmd - dma_buffer->cmd > ARRAY_SIZE(dma_buffer->cmd));
6916 dma_buffer->cmd[0].cmd |= CMD_OCB;
6917 cmd[-1].cmd |= CMD_OCU | CMD_LC;
6918 dma_buffer->cmdptr = (msm_virt_to_dma(chip, dma_buffer->cmd) >> 3)
6919 | CMD_PTR_LP;
6920
6921 mb();
6922 msm_dmov_exec_cmd(chip->dma_channel, crci_mask, DMOV_CMD_PTR_LIST
6923 | DMOV_CMD_ADDR(msm_virt_to_dma(chip,
6924 &dma_buffer->cmdptr)));
6925 mb();
6926 msm_nand_release_dma_buffer(chip, dma_buffer, sizeof(*dma_buffer));
6927 return 0;
6928}
6929
Sujith Reddy Thumma5e4d9872011-08-24 09:07:55 +0530[diff] [blame^]6930static int setup_mtd_device(struct platform_device *pdev,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]6931 struct msm_nand_info *info)
6932{
Sujith Reddy Thumma5e4d9872011-08-24 09:07:55 +0530[diff] [blame^]6933 int i, err;
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]6934 struct flash_platform_data *pdata = pdev->dev.platform_data;
6935
Sujith Reddy Thumma5e4d9872011-08-24 09:07:55 +0530[diff] [blame^]6936 if (pdata) {
6937 for (i = 0; i < pdata->nr_parts; i++) {
6938 pdata->parts[i].offset = pdata->parts[i].offset
6939 * info->mtd.erasesize;
6940 pdata->parts[i].size = pdata->parts[i].size
6941 * info->mtd.erasesize;
6942 }
6943 err = mtd_device_register(&info->mtd, pdata->parts,
6944 pdata->nr_parts);
6945 } else {
6946 err = mtd_device_register(&info->mtd, NULL, 0);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]6947 }
Sujith Reddy Thumma5e4d9872011-08-24 09:07:55 +0530[diff] [blame^]6948 return err;
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]6949}
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]6950
6951static int __devinit msm_nand_probe(struct platform_device *pdev)
6952{
6953 struct msm_nand_info *info;
6954 struct resource *res;
6955 int err;
6956 struct flash_platform_data *plat_data;
6957
6958 plat_data = pdev->dev.platform_data;
6959
6960 res = platform_get_resource_byname(pdev,
6961 IORESOURCE_MEM, "msm_nand_phys");
6962 if (!res || !res->start) {
6963 pr_err("%s: msm_nand_phys resource invalid/absent\n",
6964 __func__);
6965 return -ENODEV;
6966 }
6967 msm_nand_phys = res->start;
6968 pr_info("%s: phys addr 0x%lx \n", __func__, msm_nand_phys);
6969
6970 res = platform_get_resource_byname(pdev,
6971 IORESOURCE_MEM, "msm_nandc01_phys");
6972 if (!res || !res->start)
6973 goto no_dual_nand_ctlr_support;
6974 msm_nandc01_phys = res->start;
6975
6976 res = platform_get_resource_byname(pdev,
6977 IORESOURCE_MEM, "msm_nandc10_phys");
6978 if (!res || !res->start)
6979 goto no_dual_nand_ctlr_support;
6980 msm_nandc10_phys = res->start;
6981
6982 res = platform_get_resource_byname(pdev,
6983 IORESOURCE_MEM, "msm_nandc11_phys");
6984 if (!res || !res->start)
6985 goto no_dual_nand_ctlr_support;
6986 msm_nandc11_phys = res->start;
6987
6988 res = platform_get_resource_byname(pdev,
6989 IORESOURCE_MEM, "ebi2_reg_base");
6990 if (!res || !res->start)
6991 goto no_dual_nand_ctlr_support;
6992 ebi2_register_base = res->start;
6993
6994 dual_nand_ctlr_present = 1;
6995 if (plat_data != NULL)
6996 interleave_enable = plat_data->interleave;
6997 else
6998 interleave_enable = 0;
6999
7000 if (!interleave_enable)
7001 pr_info("%s: Dual Nand Ctrl in ping-pong mode\n", __func__);
7002 else
7003 pr_info("%s: Dual Nand Ctrl in interleave mode\n", __func__);
7004
7005no_dual_nand_ctlr_support:
7006 res = platform_get_resource_byname(pdev,
7007 IORESOURCE_DMA, "msm_nand_dmac");
7008 if (!res || !res->start) {
7009 pr_err("%s: invalid msm_nand_dmac resource\n", __func__);
7010 return -ENODEV;
7011 }
7012
7013 info = kzalloc(sizeof(struct msm_nand_info), GFP_KERNEL);
7014 if (!info) {
7015 pr_err("%s: No memory for msm_nand_info\n", __func__);
7016 return -ENOMEM;
7017 }
7018
7019 info->msm_nand.dev = &pdev->dev;
7020
7021 init_waitqueue_head(&info->msm_nand.wait_queue);
7022
7023 info->msm_nand.dma_channel = res->start;
7024 pr_info("%s: dmac 0x%x\n", __func__, info->msm_nand.dma_channel);
7025
7026 /* this currently fails if dev is passed in */
7027 info->msm_nand.dma_buffer =
7028 dma_alloc_coherent(/*dev*/ NULL, MSM_NAND_DMA_BUFFER_SIZE,
7029 &info->msm_nand.dma_addr, GFP_KERNEL);
7030 if (info->msm_nand.dma_buffer == NULL) {
7031 pr_err("%s: No memory for msm_nand.dma_buffer\n", __func__);
7032 err = -ENOMEM;
7033 goto out_free_info;
7034 }
7035
7036 pr_info("%s: allocated dma buffer at %p, dma_addr %x\n",
7037 __func__, info->msm_nand.dma_buffer, info->msm_nand.dma_addr);
7038
7039 crci_mask = msm_dmov_build_crci_mask(2,
7040 DMOV_NAND_CRCI_DATA, DMOV_NAND_CRCI_CMD);
7041
7042 info->mtd.name = dev_name(&pdev->dev);
7043 info->mtd.priv = &info->msm_nand;
7044 info->mtd.owner = THIS_MODULE;
7045
7046 /* config ebi2_cfg register only for ping pong mode!!! */
7047 if (!interleave_enable && dual_nand_ctlr_present)
7048 flash_wr_reg(&info->msm_nand, EBI2_CFG_REG, 0x4010080);
7049
7050 if (dual_nand_ctlr_present)
7051 msm_nand_nc10_xfr_settings(&info->mtd);
7052
7053 if (msm_nand_scan(&info->mtd, 1))
7054 if (msm_onenand_scan(&info->mtd, 1)) {
7055 pr_err("%s: No nand device found\n", __func__);
7056 err = -ENXIO;
7057 goto out_free_dma_buffer;
7058 }
7059
Sujith Reddy Thumma5e4d9872011-08-24 09:07:55 +0530[diff] [blame^]7060 err = setup_mtd_device(pdev, info);
7061 if (err < 0) {
7062 pr_err("%s: setup_mtd_device failed with err=%d\n",
7063 __func__, err);
7064 goto out_free_dma_buffer;
7065 }
7066
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]7067 dev_set_drvdata(&pdev->dev, info);
7068
7069 return 0;
7070
7071out_free_dma_buffer:
7072 dma_free_coherent(NULL, MSM_NAND_DMA_BUFFER_SIZE,
7073 info->msm_nand.dma_buffer,
7074 info->msm_nand.dma_addr);
7075out_free_info:
7076 kfree(info);
7077
7078 return err;
7079}
7080
7081static int __devexit msm_nand_remove(struct platform_device *pdev)
7082{
7083 struct msm_nand_info *info = dev_get_drvdata(&pdev->dev);
7084
7085 dev_set_drvdata(&pdev->dev, NULL);
7086
7087 if (info) {
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]7088 msm_nand_release(&info->mtd);
7089 dma_free_coherent(NULL, MSM_NAND_DMA_BUFFER_SIZE,
7090 info->msm_nand.dma_buffer,
7091 info->msm_nand.dma_addr);
7092 kfree(info);
7093 }
7094
7095 return 0;
7096}
7097
7098#define DRIVER_NAME "msm_nand"
7099
7100static struct platform_driver msm_nand_driver = {
7101 .probe = msm_nand_probe,
7102 .remove = __devexit_p(msm_nand_remove),
7103 .driver = {
7104 .name = DRIVER_NAME,
7105 }
7106};
7107
7108MODULE_ALIAS(DRIVER_NAME);
7109
7110static int __init msm_nand_init(void)
7111{
7112 return platform_driver_register(&msm_nand_driver);
7113}
7114
7115static void __exit msm_nand_exit(void)
7116{
7117 platform_driver_unregister(&msm_nand_driver);
7118}
7119
7120module_init(msm_nand_init);
7121module_exit(msm_nand_exit);
7122
7123MODULE_LICENSE("GPL");
7124MODULE_DESCRIPTION("msm_nand flash driver code");