blob: 35de4d7a3e8969a7307b43d7fba67d55cf3030a7 [file] [log] [blame]
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001/* Copyright (c) 2009-2011, Code Aurora Forum. All rights reserved.
2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 *
12 */
13
14#include <linux/module.h>
15#include <linux/kernel.h>
16#include <linux/sched.h>
17#include <linux/time.h>
18#include <linux/init.h>
19#include <linux/interrupt.h>
20#include <linux/spinlock.h>
21#include <linux/hrtimer.h>
22#include <linux/clk.h>
23#include <mach/hardware.h>
24#include <linux/io.h>
25#include <linux/debugfs.h>
26#include <linux/fb.h>
27#include <linux/msm_mdp.h>
28#include <linux/file.h>
29#include <linux/android_pmem.h>
30#include <linux/major.h>
31#include <asm/system.h>
32#include <asm/mach-types.h>
33#include <linux/semaphore.h>
34#include <linux/uaccess.h>
35#include <linux/mutex.h>
36#include <linux/msm_kgsl.h>
37#include "mdp.h"
38#include "msm_fb.h"
39#include "mdp4.h"
40
41#define VERSION_KEY_MASK 0xFFFFFF00
42
43struct mdp4_overlay_ctrl {
44 struct mdp4_pipe_desc ov_pipe[OVERLAY_PIPE_MAX];/* 4 */
45 struct mdp4_overlay_pipe plist[MDP4_MAX_PIPE]; /* 4 + 2 */
kuogee hsieh405dc302011-07-21 15:06:59 -070046 struct mdp4_overlay_pipe *stage[MDP4_MAX_MIXER][MDP4_MIXER_STAGE_MAX];
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070047 uint32 panel_3d;
48 uint32 panel_mode;
49 uint32 mixer0_played;
50 uint32 mixer1_played;
51} mdp4_overlay_db = {
52 .ov_pipe = {
53 {
54 .share = 0, /* RGB 1 */
55 },
56 {
57 .share = 0, /* RGB 2 */
58 },
59 {
60 .share = 1, /* VG 1 */
61 },
62 {
63 .share = 1, /* VG 2 */
64 },
65 },
66 .plist = {
67 {
68 .pipe_type = OVERLAY_TYPE_RGB,
69 .pipe_num = OVERLAY_PIPE_RGB1,
70 .pipe_ndx = 1,
71 },
72 {
73 .pipe_type = OVERLAY_TYPE_RGB,
74 .pipe_num = OVERLAY_PIPE_RGB2,
75 .pipe_ndx = 2,
76 },
77 {
78 .pipe_type = OVERLAY_TYPE_RGB, /* shared */
79 .pipe_num = OVERLAY_PIPE_VG1,
80 .pipe_ndx = 3,
81 },
82 {
83 .pipe_type = OVERLAY_TYPE_RGB, /* shared */
84 .pipe_num = OVERLAY_PIPE_VG2,
85 .pipe_ndx = 4,
86 },
87 {
88 .pipe_type = OVERLAY_TYPE_VIDEO, /* shared */
89 .pipe_num = OVERLAY_PIPE_VG1,
90 .pipe_ndx = 5,
91 },
92 {
93 .pipe_type = OVERLAY_TYPE_VIDEO, /* shared */
94 .pipe_num = OVERLAY_PIPE_VG2,
95 .pipe_ndx = 6,
96 },
97 },
98};
99
100static struct mdp4_overlay_ctrl *ctrl = &mdp4_overlay_db;
kuogee hsieh9452ecb2011-08-01 18:26:23 -0700101static int new_perf_level;
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700102/* static array with index 0 for unset status and 1 for set status */
103static bool overlay_status[MDP4_OVERLAY_TYPE_MAX];
104
105void mdp4_overlay_status_write(enum mdp4_overlay_status type, bool val)
106{
107 overlay_status[type] = val;
108}
109
110bool mdp4_overlay_status_read(enum mdp4_overlay_status type)
111{
112 return overlay_status[type];
113}
114
115int mdp4_overlay_mixer_play(int mixer_num)
116{
117 if (mixer_num == MDP4_MIXER1)
118 return ctrl->mixer1_played;
119 else
120 return ctrl->mixer0_played;
121}
122
123void mdp4_overlay_panel_3d(int mixer_num, uint32 panel_3d)
124{
125 ctrl->panel_3d = panel_3d;
126}
127
128void mdp4_overlay_panel_mode(int mixer_num, uint32 mode)
129{
130 ctrl->panel_mode |= mode;
131}
132
133uint32 mdp4_overlay_panel_list(void)
134{
135 return ctrl->panel_mode;
136}
137
138void mdp4_overlay_dmae_cfg(struct msm_fb_data_type *mfd, int atv)
139{
140 uint32 dmae_cfg_reg;
141
142 if (atv)
143 dmae_cfg_reg = DMA_DEFLKR_EN;
144 else
145 dmae_cfg_reg = 0;
146
147 if (mfd->fb_imgType == MDP_BGR_565)
148 dmae_cfg_reg |= DMA_PACK_PATTERN_BGR;
149 else
150 dmae_cfg_reg |= DMA_PACK_PATTERN_RGB;
151
152
153 if (mfd->panel_info.bpp == 18) {
154 dmae_cfg_reg |= DMA_DSTC0G_6BITS | /* 666 18BPP */
155 DMA_DSTC1B_6BITS | DMA_DSTC2R_6BITS;
156 } else if (mfd->panel_info.bpp == 16) {
157 dmae_cfg_reg |= DMA_DSTC0G_6BITS | /* 565 16BPP */
158 DMA_DSTC1B_5BITS | DMA_DSTC2R_5BITS;
159 } else {
160 dmae_cfg_reg |= DMA_DSTC0G_8BITS | /* 888 16BPP */
161 DMA_DSTC1B_8BITS | DMA_DSTC2R_8BITS;
162 }
163
164 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
165
166 /* dma2 config register */
167 MDP_OUTP(MDP_BASE + 0xb0000, dmae_cfg_reg);
168 if (atv) {
169 MDP_OUTP(MDP_BASE + 0xb0070, 0xeb0010);
170 MDP_OUTP(MDP_BASE + 0xb0074, 0xf00010);
171 MDP_OUTP(MDP_BASE + 0xb0078, 0xf00010);
172 MDP_OUTP(MDP_BASE + 0xb3000, 0x80);
173 MDP_OUTP(MDP_BASE + 0xb3010, 0x1800040);
174 MDP_OUTP(MDP_BASE + 0xb3014, 0x1000080);
175 MDP_OUTP(MDP_BASE + 0xb4004, 0x67686970);
176 } else {
177 MDP_OUTP(MDP_BASE + 0xb0070, 0xff0000);
178 MDP_OUTP(MDP_BASE + 0xb0074, 0xff0000);
179 MDP_OUTP(MDP_BASE + 0xb0078, 0xff0000);
180 }
181
182 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
183}
184
Manoj Raob91fa712011-06-29 09:07:55 -0700185#ifdef CONFIG_FB_MSM_HDMI_3D
186void unfill_black_screen(void) { return; }
187#else
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700188void unfill_black_screen(void)
189{
190 uint32 temp_src_format;
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700191 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
192 /*
193 * VG2 Constant Color
194 */
195 temp_src_format = inpdw(MDP_BASE + 0x30050);
196 MDP_OUTP(MDP_BASE + 0x30050, temp_src_format&(~BIT(22)));
197 /*
198 * MDP_OVERLAY_REG_FLUSH
199 */
200 MDP_OUTP(MDP_BASE + 0x18000, BIT(3));
201 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
Manoj Raob91fa712011-06-29 09:07:55 -0700202 return;
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700203}
Manoj Raob91fa712011-06-29 09:07:55 -0700204#endif
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700205
Manoj Raob91fa712011-06-29 09:07:55 -0700206#ifdef CONFIG_FB_MSM_HDMI_3D
207void fill_black_screen(void) { return; }
208#else
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700209void fill_black_screen(void)
210{
211 /*Black color*/
212 uint32 color = 0x00000000;
213 uint32 temp_src_format;
214 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
215 /*
216 * VG2 Constant Color
217 */
218 MDP_OUTP(MDP_BASE + 0x31008, color);
219 /*
220 * MDP_VG2_SRC_FORMAT
221 */
222 temp_src_format = inpdw(MDP_BASE + 0x30050);
223 MDP_OUTP(MDP_BASE + 0x30050, temp_src_format | BIT(22));
224 /*
225 * MDP_OVERLAY_REG_FLUSH
226 */
227 MDP_OUTP(MDP_BASE + 0x18000, BIT(3));
228 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
Manoj Raob91fa712011-06-29 09:07:55 -0700229 return;
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700230}
Manoj Raob91fa712011-06-29 09:07:55 -0700231#endif
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700232
233void mdp4_overlay_dmae_xy(struct mdp4_overlay_pipe *pipe)
234{
235
236 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
237
238 /* dma_p source */
239 MDP_OUTP(MDP_BASE + 0xb0004,
240 (pipe->src_height << 16 | pipe->src_width));
241 MDP_OUTP(MDP_BASE + 0xb0008, pipe->srcp0_addr);
242 MDP_OUTP(MDP_BASE + 0xb000c, pipe->srcp0_ystride);
243
244 /* dma_p dest */
245 MDP_OUTP(MDP_BASE + 0xb0010, (pipe->dst_y << 16 | pipe->dst_x));
246
247 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
248}
249
250void mdp4_overlay_dmap_cfg(struct msm_fb_data_type *mfd, int lcdc)
251{
252 uint32 dma2_cfg_reg;
253
254 dma2_cfg_reg = DMA_DITHER_EN;
255#ifdef BLT_RGB565
256 /* RGB888 is 0 */
257 dma2_cfg_reg |= DMA_BUF_FORMAT_RGB565; /* blt only */
258#endif
259
260 if (mfd->fb_imgType == MDP_BGR_565)
261 dma2_cfg_reg |= DMA_PACK_PATTERN_BGR;
262 else
263 dma2_cfg_reg |= DMA_PACK_PATTERN_RGB;
264
265
266 if (mfd->panel_info.bpp == 18) {
267 dma2_cfg_reg |= DMA_DSTC0G_6BITS | /* 666 18BPP */
268 DMA_DSTC1B_6BITS | DMA_DSTC2R_6BITS;
269 } else if (mfd->panel_info.bpp == 16) {
270 dma2_cfg_reg |= DMA_DSTC0G_6BITS | /* 565 16BPP */
271 DMA_DSTC1B_5BITS | DMA_DSTC2R_5BITS;
272 } else {
273 dma2_cfg_reg |= DMA_DSTC0G_8BITS | /* 888 16BPP */
274 DMA_DSTC1B_8BITS | DMA_DSTC2R_8BITS;
275 }
276
277 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
278
279#ifndef CONFIG_FB_MSM_LCDC_CHIMEI_WXGA_PANEL
280 if (lcdc)
281 dma2_cfg_reg |= DMA_PACK_ALIGN_MSB;
282#endif
283
284 /* dma2 config register */
285 MDP_OUTP(MDP_BASE + 0x90000, dma2_cfg_reg);
286
287 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
288}
289
290/*
291 * mdp4_overlay_dmap_xy: called form baselayer only
292 */
293void mdp4_overlay_dmap_xy(struct mdp4_overlay_pipe *pipe)
294{
295 uint32 off, bpp;
296
297 if (mdp_is_in_isr == FALSE)
298 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
299
300 /* dma_p source */
301 MDP_OUTP(MDP_BASE + 0x90004,
302 (pipe->src_height << 16 | pipe->src_width));
303 if (pipe->blt_addr) {
304#ifdef BLT_RGB565
305 bpp = 2; /* overlay ouput is RGB565 */
306#else
307 bpp = 3; /* overlay ouput is RGB888 */
308#endif
309 off = 0;
310 if (pipe->dmap_cnt & 0x01)
311 off = pipe->src_height * pipe->src_width * bpp;
312 MDP_OUTP(MDP_BASE + 0x90008, pipe->blt_addr + off);
313 /* RGB888, output of overlay blending */
314 MDP_OUTP(MDP_BASE + 0x9000c, pipe->src_width * bpp);
315 } else {
316 MDP_OUTP(MDP_BASE + 0x90008, pipe->srcp0_addr);
317 MDP_OUTP(MDP_BASE + 0x9000c, pipe->srcp0_ystride);
318 }
319
320 /* dma_p dest */
321 MDP_OUTP(MDP_BASE + 0x90010, (pipe->dst_y << 16 | pipe->dst_x));
322
323 if (mdp_is_in_isr == FALSE)
324 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
325}
326
327#define MDP4_VG_PHASE_STEP_DEFAULT 0x20000000
328#define MDP4_VG_PHASE_STEP_SHIFT 29
329
330static int mdp4_leading_0(uint32 num)
331{
332 uint32 bit = 0x80000000;
333 int i;
334
335 for (i = 0; i < 32; i++) {
336 if (bit & num)
337 return i;
338 bit >>= 1;
339 }
340
341 return i;
342}
343
344static uint32 mdp4_scale_phase_step(int f_num, uint32 src, uint32 dst)
345{
346 uint32 val;
347 int n;
348
349 n = mdp4_leading_0(src);
350 if (n > f_num)
351 n = f_num;
352 val = src << n; /* maximum to reduce lose of resolution */
353 val /= dst;
354 if (n < f_num) {
355 n = f_num - n;
356 val <<= n;
357 }
358
359 return val;
360}
361
362static void mdp4_scale_setup(struct mdp4_overlay_pipe *pipe)
363{
364 int ptype;
365
366 pipe->phasex_step = MDP4_VG_PHASE_STEP_DEFAULT;
367 pipe->phasey_step = MDP4_VG_PHASE_STEP_DEFAULT;
368 ptype = mdp4_overlay_format2type(pipe->src_format);
369
370 if (pipe->dst_h && pipe->src_h != pipe->dst_h) {
371 if (pipe->dst_h > pipe->src_h * 8) /* too much */
372 return;
373 pipe->op_mode |= MDP4_OP_SCALEY_EN;
374
375 if (pipe->pipe_num >= OVERLAY_PIPE_VG1) {
376 if (pipe->dst_h <= (pipe->src_h / 4))
377 pipe->op_mode |= MDP4_OP_SCALEY_MN_PHASE;
378 else
379 pipe->op_mode |= MDP4_OP_SCALEY_FIR;
380 }
381
382 pipe->phasey_step = mdp4_scale_phase_step(29,
383 pipe->src_h, pipe->dst_h);
384 }
385
386 if (pipe->dst_w && pipe->src_w != pipe->dst_w) {
387 if (pipe->dst_w > pipe->src_w * 8) /* too much */
388 return;
389 pipe->op_mode |= MDP4_OP_SCALEX_EN;
390
391 if (pipe->pipe_num >= OVERLAY_PIPE_VG1) {
392 if (pipe->dst_w <= (pipe->src_w / 4))
393 pipe->op_mode |= MDP4_OP_SCALEX_MN_PHASE;
394 else
395 pipe->op_mode |= MDP4_OP_SCALEX_FIR;
396 }
397
398 pipe->phasex_step = mdp4_scale_phase_step(29,
399 pipe->src_w, pipe->dst_w);
400 }
401}
402
403void mdp4_overlay_rgb_setup(struct mdp4_overlay_pipe *pipe)
404{
405 char *rgb_base;
406 uint32 src_size, src_xy, dst_size, dst_xy;
407 uint32 format, pattern;
408
409 rgb_base = MDP_BASE + MDP4_RGB_BASE;
410 rgb_base += (MDP4_RGB_OFF * pipe->pipe_num);
411
412 src_size = ((pipe->src_h << 16) | pipe->src_w);
413 src_xy = ((pipe->src_y << 16) | pipe->src_x);
414 dst_size = ((pipe->dst_h << 16) | pipe->dst_w);
415 dst_xy = ((pipe->dst_y << 16) | pipe->dst_x);
416
417 format = mdp4_overlay_format(pipe);
418 pattern = mdp4_overlay_unpack_pattern(pipe);
419
420#ifdef MDP4_IGC_LUT_ENABLE
421 pipe->op_mode |= MDP4_OP_IGC_LUT_EN;
422#endif
423
424 mdp4_scale_setup(pipe);
425
426 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
427
428 outpdw(rgb_base + 0x0000, src_size); /* MDP_RGB_SRC_SIZE */
429 outpdw(rgb_base + 0x0004, src_xy); /* MDP_RGB_SRC_XY */
430 outpdw(rgb_base + 0x0008, dst_size); /* MDP_RGB_DST_SIZE */
431 outpdw(rgb_base + 0x000c, dst_xy); /* MDP_RGB_DST_XY */
432
433 outpdw(rgb_base + 0x0010, pipe->srcp0_addr);
434 outpdw(rgb_base + 0x0040, pipe->srcp0_ystride);
435
436 outpdw(rgb_base + 0x0050, format);/* MDP_RGB_SRC_FORMAT */
437 outpdw(rgb_base + 0x0054, pattern);/* MDP_RGB_SRC_UNPACK_PATTERN */
438 outpdw(rgb_base + 0x0058, pipe->op_mode);/* MDP_RGB_OP_MODE */
439 outpdw(rgb_base + 0x005c, pipe->phasex_step);
440 outpdw(rgb_base + 0x0060, pipe->phasey_step);
441
442 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
443
444 mdp4_stat.pipe[pipe->pipe_num]++;
445}
446
Ravishangar Kalyanam01d68282011-07-18 18:45:06 -0700447
448static void mdp4_overlay_vg_get_src_offset(struct mdp4_overlay_pipe *pipe,
449 char *vg_base, uint32 *luma_off, uint32 *chroma_off)
450{
451 uint32 src_xy;
452 *luma_off = 0;
453 *chroma_off = 0;
454
455 if (pipe->src_x) {
456 src_xy = (pipe->src_y << 16) | pipe->src_x;
457 src_xy &= 0xffff0000;
458 outpdw(vg_base + 0x0004, src_xy); /* MDP_RGB_SRC_XY */
459
460 switch (pipe->src_format) {
461 case MDP_Y_CR_CB_H2V2:
462 case MDP_Y_CB_CR_H2V2:
463 *luma_off = pipe->src_x;
464 *chroma_off = pipe->src_x/2;
465 break;
466
467 case MDP_Y_CBCR_H2V2_TILE:
468 case MDP_Y_CRCB_H2V2_TILE:
469 case MDP_Y_CBCR_H2V2:
470 case MDP_Y_CRCB_H2V2:
471 case MDP_Y_CRCB_H1V1:
472 case MDP_Y_CBCR_H1V1:
473 case MDP_Y_CRCB_H2V1:
474 case MDP_Y_CBCR_H2V1:
475 *luma_off = pipe->src_x;
476 *chroma_off = pipe->src_x;
477 break;
478
479 case MDP_YCRYCB_H2V1:
480 if (pipe->src_x & 0x1)
481 pipe->src_x += 1;
482 *luma_off += pipe->src_x * 2;
483 break;
484
485 case MDP_ARGB_8888:
486 case MDP_RGBA_8888:
487 case MDP_BGRA_8888:
488 case MDP_RGBX_8888:
489 case MDP_RGB_565:
490 case MDP_BGR_565:
491 case MDP_XRGB_8888:
492 case MDP_RGB_888:
493 *luma_off = pipe->src_x * pipe->bpp;
494 break;
495
496 default:
497 pr_err("Source format %u not supported for x offset adjustment\n",
498 pipe->src_format);
499 break;
500 }
501 }
502}
503
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700504void mdp4_overlay_vg_setup(struct mdp4_overlay_pipe *pipe)
505{
506 char *vg_base;
507 uint32 frame_size, src_size, src_xy, dst_size, dst_xy;
Ravishangar Kalyanam01d68282011-07-18 18:45:06 -0700508 uint32 format, pattern, luma_offset, chroma_offset;
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700509 int pnum;
510
511 pnum = pipe->pipe_num - OVERLAY_PIPE_VG1; /* start from 0 */
512 vg_base = MDP_BASE + MDP4_VIDEO_BASE;
513 vg_base += (MDP4_VIDEO_OFF * pnum);
514
515 frame_size = ((pipe->src_height << 16) | pipe->src_width);
516 src_size = ((pipe->src_h << 16) | pipe->src_w);
517 src_xy = ((pipe->src_y << 16) | pipe->src_x);
518 dst_size = ((pipe->dst_h << 16) | pipe->dst_w);
519 dst_xy = ((pipe->dst_y << 16) | pipe->dst_x);
520
521 format = mdp4_overlay_format(pipe);
522 pattern = mdp4_overlay_unpack_pattern(pipe);
523
524 /* not RGB use VG pipe, pure VG pipe */
525 if (pipe->pipe_type != OVERLAY_TYPE_RGB)
526#ifdef MDP4_IGC_LUT_ENABLE
527 pipe->op_mode |= (MDP4_OP_CSC_EN | MDP4_OP_SRC_DATA_YCBCR |
528 MDP4_OP_IGC_LUT_EN);
529#else
530 pipe->op_mode |= (MDP4_OP_CSC_EN | MDP4_OP_SRC_DATA_YCBCR);
531#endif
532
533 mdp4_scale_setup(pipe);
534
535 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
536
537 outpdw(vg_base + 0x0000, src_size); /* MDP_RGB_SRC_SIZE */
538 outpdw(vg_base + 0x0004, src_xy); /* MDP_RGB_SRC_XY */
539 outpdw(vg_base + 0x0008, dst_size); /* MDP_RGB_DST_SIZE */
540 outpdw(vg_base + 0x000c, dst_xy); /* MDP_RGB_DST_XY */
541 outpdw(vg_base + 0x0048, frame_size); /* TILE frame size */
542
Ravishangar Kalyanam01d68282011-07-18 18:45:06 -0700543 /*
544 * Adjust src X offset to avoid MDP from overfetching pixels
545 * present before the offset. This is required for video
546 * frames coming with unused green pixels along the left margin
547 */
548 mdp4_overlay_vg_get_src_offset(pipe, vg_base, &luma_offset,
549 &chroma_offset);
550
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700551 /* luma component plane */
Ravishangar Kalyanam01d68282011-07-18 18:45:06 -0700552 outpdw(vg_base + 0x0010, pipe->srcp0_addr + luma_offset);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700553
554 /* chroma component plane or planar color 1 */
Ravishangar Kalyanam01d68282011-07-18 18:45:06 -0700555 outpdw(vg_base + 0x0014, pipe->srcp1_addr + chroma_offset);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700556
557 /* planar color 2 */
Ravishangar Kalyanam01d68282011-07-18 18:45:06 -0700558 outpdw(vg_base + 0x0018, pipe->srcp2_addr + chroma_offset);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700559
560 outpdw(vg_base + 0x0040,
561 pipe->srcp1_ystride << 16 | pipe->srcp0_ystride);
562
563 outpdw(vg_base + 0x0044,
564 pipe->srcp3_ystride << 16 | pipe->srcp2_ystride);
565
566 outpdw(vg_base + 0x0050, format); /* MDP_RGB_SRC_FORMAT */
567 outpdw(vg_base + 0x0054, pattern); /* MDP_RGB_SRC_UNPACK_PATTERN */
568 outpdw(vg_base + 0x0058, pipe->op_mode);/* MDP_RGB_OP_MODE */
569 outpdw(vg_base + 0x005c, pipe->phasex_step);
570 outpdw(vg_base + 0x0060, pipe->phasey_step);
571
572 if (pipe->op_mode & MDP4_OP_DITHER_EN) {
573 outpdw(vg_base + 0x0068,
574 pipe->r_bit << 4 | pipe->b_bit << 2 | pipe->g_bit);
575 }
576
577 if (pipe->flags & MDP_SHARPENING) {
578 outpdw(vg_base + 0x8200,
579 mdp4_ss_table_value(pipe->req_data.dpp.sharp_strength,
580 0));
581 outpdw(vg_base + 0x8204,
582 mdp4_ss_table_value(pipe->req_data.dpp.sharp_strength,
583 1));
584 }
585
586 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
587
588 mdp4_stat.pipe[pipe->pipe_num]++;
589}
590
591int mdp4_overlay_format2type(uint32 format)
592{
593 switch (format) {
594 case MDP_RGB_565:
595 case MDP_RGB_888:
596 case MDP_BGR_565:
597 case MDP_XRGB_8888:
598 case MDP_ARGB_8888:
599 case MDP_RGBA_8888:
600 case MDP_BGRA_8888:
601 case MDP_RGBX_8888:
602 return OVERLAY_TYPE_RGB;
603 case MDP_YCRYCB_H2V1:
604 case MDP_Y_CRCB_H2V1:
605 case MDP_Y_CBCR_H2V1:
606 case MDP_Y_CRCB_H2V2:
607 case MDP_Y_CBCR_H2V2:
608 case MDP_Y_CBCR_H2V2_TILE:
609 case MDP_Y_CRCB_H2V2_TILE:
610 case MDP_Y_CR_CB_H2V2:
611 case MDP_Y_CB_CR_H2V2:
612 case MDP_Y_CRCB_H1V1:
613 case MDP_Y_CBCR_H1V1:
614 return OVERLAY_TYPE_VIDEO;
615 default:
616 mdp4_stat.err_format++;
617 return -ERANGE;
618 }
619
620}
621
622#define C3_ALPHA 3 /* alpha */
623#define C2_R_Cr 2 /* R/Cr */
624#define C1_B_Cb 1 /* B/Cb */
625#define C0_G_Y 0 /* G/luma */
626#define YUV_444_MAX_WIDTH 1280 /* Max width for YUV 444*/
627
628int mdp4_overlay_format2pipe(struct mdp4_overlay_pipe *pipe)
629{
630 switch (pipe->src_format) {
631 case MDP_RGB_565:
632 pipe->frame_format = MDP4_FRAME_FORMAT_LINEAR;
633 pipe->fetch_plane = OVERLAY_PLANE_INTERLEAVED;
634 pipe->a_bit = 0;
635 pipe->r_bit = 1; /* R, 5 bits */
636 pipe->b_bit = 1; /* B, 5 bits */
637 pipe->g_bit = 2; /* G, 6 bits */
638 pipe->alpha_enable = 0;
639 pipe->unpack_tight = 1;
640 pipe->unpack_align_msb = 0;
641 pipe->unpack_count = 2;
642 pipe->element2 = C2_R_Cr; /* R */
643 pipe->element1 = C0_G_Y; /* G */
644 pipe->element0 = C1_B_Cb; /* B */
645 pipe->bpp = 2; /* 2 bpp */
646 break;
647 case MDP_RGB_888:
648 pipe->frame_format = MDP4_FRAME_FORMAT_LINEAR;
649 pipe->fetch_plane = OVERLAY_PLANE_INTERLEAVED;
650 pipe->a_bit = 0;
651 pipe->r_bit = 3; /* R, 8 bits */
652 pipe->b_bit = 3; /* B, 8 bits */
653 pipe->g_bit = 3; /* G, 8 bits */
654 pipe->alpha_enable = 0;
655 pipe->unpack_tight = 1;
656 pipe->unpack_align_msb = 0;
657 pipe->unpack_count = 2;
658 pipe->element2 = C2_R_Cr; /* R */
659 pipe->element1 = C0_G_Y; /* G */
660 pipe->element0 = C1_B_Cb; /* B */
661 pipe->bpp = 3; /* 3 bpp */
662 break;
663 case MDP_BGR_565:
664 pipe->frame_format = MDP4_FRAME_FORMAT_LINEAR;
665 pipe->fetch_plane = OVERLAY_PLANE_INTERLEAVED;
666 pipe->a_bit = 0;
667 pipe->r_bit = 1; /* R, 5 bits */
668 pipe->b_bit = 1; /* B, 5 bits */
669 pipe->g_bit = 2; /* G, 6 bits */
670 pipe->alpha_enable = 0;
671 pipe->unpack_tight = 1;
672 pipe->unpack_align_msb = 0;
673 pipe->unpack_count = 2;
674 pipe->element2 = C1_B_Cb; /* B */
675 pipe->element1 = C0_G_Y; /* G */
676 pipe->element0 = C2_R_Cr; /* R */
677 pipe->bpp = 2; /* 2 bpp */
678 break;
679 case MDP_XRGB_8888:
680 pipe->frame_format = MDP4_FRAME_FORMAT_LINEAR;
681 pipe->fetch_plane = OVERLAY_PLANE_INTERLEAVED;
682 pipe->a_bit = 3; /* alpha, 4 bits */
683 pipe->r_bit = 3; /* R, 8 bits */
684 pipe->b_bit = 3; /* B, 8 bits */
685 pipe->g_bit = 3; /* G, 8 bits */
686 pipe->alpha_enable = 0;
687 pipe->unpack_tight = 1;
688 pipe->unpack_align_msb = 0;
689 pipe->unpack_count = 3;
690 pipe->element3 = C3_ALPHA; /* alpha */
691 pipe->element2 = C2_R_Cr; /* R */
692 pipe->element1 = C0_G_Y; /* G */
693 pipe->element0 = C1_B_Cb; /* B */
694 pipe->bpp = 4; /* 4 bpp */
695 break;
696 case MDP_ARGB_8888:
697 pipe->frame_format = MDP4_FRAME_FORMAT_LINEAR;
698 pipe->fetch_plane = OVERLAY_PLANE_INTERLEAVED;
699 pipe->a_bit = 3; /* alpha, 4 bits */
700 pipe->r_bit = 3; /* R, 8 bits */
701 pipe->b_bit = 3; /* B, 8 bits */
702 pipe->g_bit = 3; /* G, 8 bits */
703 pipe->alpha_enable = 1;
704 pipe->unpack_tight = 1;
705 pipe->unpack_align_msb = 0;
706 pipe->unpack_count = 3;
707 pipe->element3 = C3_ALPHA; /* alpha */
708 pipe->element2 = C2_R_Cr; /* R */
709 pipe->element1 = C0_G_Y; /* G */
710 pipe->element0 = C1_B_Cb; /* B */
711 pipe->bpp = 4; /* 4 bpp */
712 break;
713 case MDP_RGBA_8888:
714 pipe->frame_format = MDP4_FRAME_FORMAT_LINEAR;
715 pipe->fetch_plane = OVERLAY_PLANE_INTERLEAVED;
716 pipe->a_bit = 3; /* alpha, 4 bits */
717 pipe->r_bit = 3; /* R, 8 bits */
718 pipe->b_bit = 3; /* B, 8 bits */
719 pipe->g_bit = 3; /* G, 8 bits */
720 pipe->alpha_enable = 1;
721 pipe->unpack_tight = 1;
722 pipe->unpack_align_msb = 0;
723 pipe->unpack_count = 3;
724 pipe->element3 = C3_ALPHA; /* alpha */
725 pipe->element2 = C1_B_Cb; /* B */
726 pipe->element1 = C0_G_Y; /* G */
727 pipe->element0 = C2_R_Cr; /* R */
728 pipe->bpp = 4; /* 4 bpp */
729 break;
730 case MDP_RGBX_8888:
731 pipe->frame_format = MDP4_FRAME_FORMAT_LINEAR;
732 pipe->fetch_plane = OVERLAY_PLANE_INTERLEAVED;
733 pipe->a_bit = 3;
734 pipe->r_bit = 3; /* R, 8 bits */
735 pipe->b_bit = 3; /* B, 8 bits */
736 pipe->g_bit = 3; /* G, 8 bits */
737 pipe->alpha_enable = 0;
738 pipe->unpack_tight = 1;
739 pipe->unpack_align_msb = 0;
740 pipe->unpack_count = 3;
741 pipe->element3 = C3_ALPHA; /* alpha */
742 pipe->element2 = C1_B_Cb; /* B */
743 pipe->element1 = C0_G_Y; /* G */
744 pipe->element0 = C2_R_Cr; /* R */
745 pipe->bpp = 4; /* 4 bpp */
746 break;
747 case MDP_BGRA_8888:
748 pipe->frame_format = MDP4_FRAME_FORMAT_LINEAR;
749 pipe->fetch_plane = OVERLAY_PLANE_INTERLEAVED;
750 pipe->a_bit = 3; /* alpha, 4 bits */
751 pipe->r_bit = 3; /* R, 8 bits */
752 pipe->b_bit = 3; /* B, 8 bits */
753 pipe->g_bit = 3; /* G, 8 bits */
754 pipe->alpha_enable = 1;
755 pipe->unpack_tight = 1;
756 pipe->unpack_align_msb = 0;
757 pipe->unpack_count = 3;
758 pipe->element3 = C3_ALPHA; /* alpha */
759 pipe->element2 = C2_R_Cr; /* R */
760 pipe->element1 = C0_G_Y; /* G */
761 pipe->element0 = C1_B_Cb; /* B */
762 pipe->bpp = 4; /* 4 bpp */
763 break;
764 case MDP_YCRYCB_H2V1:
765 pipe->frame_format = MDP4_FRAME_FORMAT_LINEAR;
766 pipe->fetch_plane = OVERLAY_PLANE_INTERLEAVED;
767 pipe->a_bit = 0; /* alpha, 4 bits */
768 pipe->r_bit = 3; /* R, 8 bits */
769 pipe->b_bit = 3; /* B, 8 bits */
770 pipe->g_bit = 3; /* G, 8 bits */
771 pipe->alpha_enable = 0;
772 pipe->unpack_tight = 1;
773 pipe->unpack_align_msb = 0;
774 pipe->unpack_count = 3;
775 pipe->element3 = C0_G_Y; /* G */
776 pipe->element2 = C2_R_Cr; /* R */
777 pipe->element1 = C0_G_Y; /* G */
778 pipe->element0 = C1_B_Cb; /* B */
779 pipe->bpp = 2; /* 2 bpp */
780 pipe->chroma_sample = MDP4_CHROMA_H2V1;
781 break;
782 case MDP_Y_CRCB_H2V1:
783 case MDP_Y_CBCR_H2V1:
784 case MDP_Y_CRCB_H2V2:
785 case MDP_Y_CBCR_H2V2:
786 case MDP_Y_CRCB_H1V1:
787 case MDP_Y_CBCR_H1V1:
788 pipe->frame_format = MDP4_FRAME_FORMAT_LINEAR;
789 pipe->fetch_plane = OVERLAY_PLANE_PSEUDO_PLANAR;
790 pipe->a_bit = 0;
791 pipe->r_bit = 3; /* R, 8 bits */
792 pipe->b_bit = 3; /* B, 8 bits */
793 pipe->g_bit = 3; /* G, 8 bits */
794 pipe->alpha_enable = 0;
795 pipe->unpack_tight = 1;
796 pipe->unpack_align_msb = 0;
797 pipe->unpack_count = 1; /* 2 */
798 pipe->element3 = C0_G_Y; /* not used */
799 pipe->element2 = C0_G_Y; /* not used */
800 if (pipe->src_format == MDP_Y_CRCB_H2V1) {
801 pipe->element1 = C2_R_Cr; /* R */
802 pipe->element0 = C1_B_Cb; /* B */
803 pipe->chroma_sample = MDP4_CHROMA_H2V1;
804 } else if (pipe->src_format == MDP_Y_CRCB_H1V1) {
805 pipe->element1 = C2_R_Cr; /* R */
806 pipe->element0 = C1_B_Cb; /* B */
807 if (pipe->src_width > YUV_444_MAX_WIDTH)
808 pipe->chroma_sample = MDP4_CHROMA_H1V2;
809 else
810 pipe->chroma_sample = MDP4_CHROMA_RGB;
811 } else if (pipe->src_format == MDP_Y_CBCR_H2V1) {
812 pipe->element1 = C1_B_Cb; /* B */
813 pipe->element0 = C2_R_Cr; /* R */
814 pipe->chroma_sample = MDP4_CHROMA_H2V1;
815 } else if (pipe->src_format == MDP_Y_CBCR_H1V1) {
816 pipe->element1 = C1_B_Cb; /* B */
817 pipe->element0 = C2_R_Cr; /* R */
818 if (pipe->src_width > YUV_444_MAX_WIDTH)
819 pipe->chroma_sample = MDP4_CHROMA_H1V2;
820 else
821 pipe->chroma_sample = MDP4_CHROMA_RGB;
822 } else if (pipe->src_format == MDP_Y_CRCB_H2V2) {
823 pipe->element1 = C2_R_Cr; /* R */
824 pipe->element0 = C1_B_Cb; /* B */
825 pipe->chroma_sample = MDP4_CHROMA_420;
826 } else if (pipe->src_format == MDP_Y_CBCR_H2V2) {
827 pipe->element1 = C1_B_Cb; /* B */
828 pipe->element0 = C2_R_Cr; /* R */
829 pipe->chroma_sample = MDP4_CHROMA_420;
830 }
831 pipe->bpp = 2; /* 2 bpp */
832 break;
833 case MDP_Y_CBCR_H2V2_TILE:
834 case MDP_Y_CRCB_H2V2_TILE:
835 pipe->frame_format = MDP4_FRAME_FORMAT_VIDEO_SUPERTILE;
836 pipe->fetch_plane = OVERLAY_PLANE_PSEUDO_PLANAR;
837 pipe->a_bit = 0;
838 pipe->r_bit = 3; /* R, 8 bits */
839 pipe->b_bit = 3; /* B, 8 bits */
840 pipe->g_bit = 3; /* G, 8 bits */
841 pipe->alpha_enable = 0;
842 pipe->unpack_tight = 1;
843 pipe->unpack_align_msb = 0;
844 pipe->unpack_count = 1; /* 2 */
845 pipe->element3 = C0_G_Y; /* not used */
846 pipe->element2 = C0_G_Y; /* not used */
847 if (pipe->src_format == MDP_Y_CRCB_H2V2_TILE) {
848 pipe->element1 = C2_R_Cr; /* R */
849 pipe->element0 = C1_B_Cb; /* B */
850 pipe->chroma_sample = MDP4_CHROMA_420;
851 } else if (pipe->src_format == MDP_Y_CBCR_H2V2_TILE) {
852 pipe->element1 = C1_B_Cb; /* B */
853 pipe->element0 = C2_R_Cr; /* R */
854 pipe->chroma_sample = MDP4_CHROMA_420;
855 }
856 pipe->bpp = 2; /* 2 bpp */
857 break;
858 case MDP_Y_CR_CB_H2V2:
859 case MDP_Y_CB_CR_H2V2:
860 pipe->frame_format = MDP4_FRAME_FORMAT_LINEAR;
861 pipe->fetch_plane = OVERLAY_PLANE_PLANAR;
862 pipe->a_bit = 0;
863 pipe->r_bit = 3; /* R, 8 bits */
864 pipe->b_bit = 3; /* B, 8 bits */
865 pipe->g_bit = 3; /* G, 8 bits */
866 pipe->alpha_enable = 0;
Adrian Salido-Moreno33dc7b92011-08-18 16:16:12 -0700867 pipe->chroma_sample = MDP4_CHROMA_420;
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700868 pipe->bpp = 2; /* 2 bpp */
869 break;
870 default:
871 /* not likely */
872 mdp4_stat.err_format++;
873 return -ERANGE;
874 }
875
876 return 0;
877}
878
879/*
880 * color_key_convert: output with 12 bits color key
881 */
882static uint32 color_key_convert(int start, int num, uint32 color)
883{
884 uint32 data;
885
886 data = (color >> start) & ((1 << num) - 1);
887
888 /* convert to 8 bits */
889 if (num == 5)
890 data = ((data << 3) | (data >> 2));
891 else if (num == 6)
892 data = ((data << 2) | (data >> 4));
893
894 /* convert 8 bits to 12 bits */
895 data = (data << 4) | (data >> 4);
896
897 return data;
898}
899
900void transp_color_key(int format, uint32 transp,
901 uint32 *c0, uint32 *c1, uint32 *c2)
902{
903 int b_start, g_start, r_start;
904 int b_num, g_num, r_num;
905
906 switch (format) {
907 case MDP_RGB_565:
908 b_start = 0;
909 g_start = 5;
910 r_start = 11;
911 r_num = 5;
912 g_num = 6;
913 b_num = 5;
914 break;
915 case MDP_RGB_888:
916 case MDP_XRGB_8888:
917 case MDP_ARGB_8888:
918 case MDP_BGRA_8888:
919 b_start = 0;
920 g_start = 8;
921 r_start = 16;
922 r_num = 8;
923 g_num = 8;
924 b_num = 8;
925 break;
926 case MDP_RGBA_8888:
927 case MDP_RGBX_8888:
928 b_start = 16;
929 g_start = 8;
930 r_start = 0;
931 r_num = 8;
932 g_num = 8;
933 b_num = 8;
934 break;
935 case MDP_BGR_565:
936 b_start = 11;
937 g_start = 5;
938 r_start = 0;
939 r_num = 5;
940 g_num = 6;
941 b_num = 5;
942 break;
943 case MDP_Y_CB_CR_H2V2:
944 case MDP_Y_CBCR_H2V2:
945 case MDP_Y_CBCR_H2V1:
946 b_start = 8;
947 g_start = 16;
948 r_start = 0;
949 r_num = 8;
950 g_num = 8;
951 b_num = 8;
952 break;
953 case MDP_Y_CR_CB_H2V2:
954 case MDP_Y_CRCB_H2V2:
955 case MDP_Y_CRCB_H2V1:
956 case MDP_Y_CRCB_H1V1:
957 case MDP_Y_CBCR_H1V1:
958 b_start = 0;
959 g_start = 16;
960 r_start = 8;
961 r_num = 8;
962 g_num = 8;
963 b_num = 8;
964 break;
965 default:
966 b_start = 0;
967 g_start = 8;
968 r_start = 16;
969 r_num = 8;
970 g_num = 8;
971 b_num = 8;
972 break;
973 }
974
975 *c0 = color_key_convert(g_start, g_num, transp);
976 *c1 = color_key_convert(b_start, b_num, transp);
977 *c2 = color_key_convert(r_start, r_num, transp);
978}
979
980uint32 mdp4_overlay_format(struct mdp4_overlay_pipe *pipe)
981{
982 uint32 format;
983
984 format = 0;
985
986 if (pipe->solid_fill)
987 format |= MDP4_FORMAT_SOLID_FILL;
988
989 if (pipe->unpack_align_msb)
990 format |= MDP4_FORMAT_UNPACK_ALIGN_MSB;
991
992 if (pipe->unpack_tight)
993 format |= MDP4_FORMAT_UNPACK_TIGHT;
994
995 if (pipe->alpha_enable)
996 format |= MDP4_FORMAT_ALPHA_ENABLE;
997
998 if (pipe->flags & MDP_SOURCE_ROTATED_90)
999 format |= MDP4_FORMAT_90_ROTATED;
1000 format |= (pipe->unpack_count << 13);
1001 format |= ((pipe->bpp - 1) << 9);
1002 format |= (pipe->a_bit << 6);
1003 format |= (pipe->r_bit << 4);
1004 format |= (pipe->b_bit << 2);
1005 format |= pipe->g_bit;
1006
1007 format |= (pipe->frame_format << 29);
1008
1009 if (pipe->fetch_plane == OVERLAY_PLANE_PSEUDO_PLANAR ||
1010 pipe->fetch_plane == OVERLAY_PLANE_PLANAR) {
1011 /* video/graphic */
1012 format |= (pipe->fetch_plane << 19);
1013 format |= (pipe->chroma_site << 28);
1014 format |= (pipe->chroma_sample << 26);
1015 }
1016
1017 return format;
1018}
1019
1020uint32 mdp4_overlay_unpack_pattern(struct mdp4_overlay_pipe *pipe)
1021{
1022 return (pipe->element3 << 24) | (pipe->element2 << 16) |
1023 (pipe->element1 << 8) | pipe->element0;
1024}
1025
1026/*
1027 * mdp4_overlayproc_cfg: only be called from base layer
1028 */
1029void mdp4_overlayproc_cfg(struct mdp4_overlay_pipe *pipe)
1030{
1031 uint32 data, intf;
1032 char *overlay_base;
1033
1034 intf = 0;
1035 if (pipe->mixer_num == MDP4_MIXER1) {
1036 overlay_base = MDP_BASE + MDP4_OVERLAYPROC1_BASE;/* 0x18000 */
1037 intf = inpdw(MDP_BASE + 0x0038); /* MDP_DISP_INTF_SEL */
1038 intf >>= 4;
1039 intf &= 0x03;
1040 } else
1041 overlay_base = MDP_BASE + MDP4_OVERLAYPROC0_BASE;/* 0x10000 */
1042
1043 if (mdp_is_in_isr == FALSE)
1044 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
1045
1046 /*
1047 * BLT only siupport at primary display
1048 */
1049 if (pipe->mixer_num == MDP4_MIXER0 && pipe->blt_addr) {
1050 int off, bpp;
1051#ifdef BLT_RGB565
1052 bpp = 2; /* overlay ouput is RGB565 */
1053#else
1054 bpp = 3; /* overlay ouput is RGB888 */
1055#endif
1056 data = pipe->src_height;
1057 data <<= 16;
1058 data |= pipe->src_width;
1059 outpdw(overlay_base + 0x0008, data); /* ROI, height + width */
1060 if (ctrl->panel_mode & MDP4_PANEL_LCDC ||
1061 ctrl->panel_mode & MDP4_PANEL_DSI_VIDEO) {
1062 outpdw(overlay_base + 0x000c, pipe->blt_addr);
1063 outpdw(overlay_base + 0x0010, pipe->src_width * bpp);
1064 off = pipe->src_height * pipe->src_width * bpp;
1065 outpdw(overlay_base + 0x001c, pipe->blt_addr + off);
1066 /* LCDC - FRAME BUFFER + vsync rate */
kuogee hsieh4d3c7792011-07-25 11:02:24 -07001067 outpdw(overlay_base + 0x0004, 0x04);/* 30 refresh */
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001068 } else { /* MDDI */
1069 off = 0;
1070 if (pipe->ov_cnt & 0x01)
1071 off = pipe->src_height * pipe->src_width * bpp;
1072
1073 outpdw(overlay_base + 0x000c, pipe->blt_addr + off);
1074 /* overlay ouput is RGB888 */
1075 outpdw(overlay_base + 0x0010, pipe->src_width * bpp);
1076 outpdw(overlay_base + 0x001c, pipe->blt_addr + off);
1077 /* MDDI - BLT + on demand */
1078 outpdw(overlay_base + 0x0004, 0x08);
1079 }
1080#ifdef BLT_RGB565
1081 outpdw(overlay_base + 0x0014, 0x1); /* RGB565 */
1082#else
1083 outpdw(overlay_base + 0x0014, 0x0); /* RGB888 */
1084#endif
1085 } else {
1086 data = pipe->src_height;
1087 data <<= 16;
1088 data |= pipe->src_width;
1089 outpdw(overlay_base + 0x0008, data); /* ROI, height + width */
1090 outpdw(overlay_base + 0x000c, pipe->srcp0_addr);
1091 outpdw(overlay_base + 0x0010, pipe->srcp0_ystride);
1092 outpdw(overlay_base + 0x0004, 0x01); /* directout */
1093 }
1094
1095 if (pipe->mixer_num == MDP4_MIXER1) {
1096 if (intf == TV_INTF) {
1097 outpdw(overlay_base + 0x0014, 0x02); /* yuv422 */
1098 /* overlay1 CSC config */
1099 outpdw(overlay_base + 0x0200, 0x05); /* rgb->yuv */
1100 }
1101 }
1102
1103#ifdef MDP4_IGC_LUT_ENABLE
1104 outpdw(overlay_base + 0x0014, 0x4); /* GC_LUT_EN, 888 */
1105#endif
1106
1107 if (mdp_is_in_isr == FALSE)
1108 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
1109}
1110
1111int mdp4_overlay_pipe_staged(int mixer)
1112{
1113 uint32 data, mask, i;
1114 int p1, p2;
1115
1116 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
1117 data = inpdw(MDP_BASE + 0x10100);
1118 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
1119 p1 = 0;
1120 p2 = 0;
1121 for (i = 0; i < 8; i++) {
1122 mask = data & 0x0f;
1123 if (mask) {
1124 if (mask <= 4)
1125 p1++;
1126 else
1127 p2++;
1128 }
1129 data >>= 4;
1130 }
1131
1132 if (mixer)
1133 return p2;
1134 else
1135 return p1;
1136}
1137
kuogee hsieh405dc302011-07-21 15:06:59 -07001138int mdp4_mixer_info(int mixer_num, struct mdp_mixer_info *info)
1139{
1140
1141 int ndx, cnt;
1142 struct mdp4_overlay_pipe *pipe;
1143
1144 if (mixer_num > MDP4_MIXER_MAX)
1145 return -ENODEV;
1146
1147 cnt = 0;
1148 ndx = 1; /* ndx 0 if not used */
1149
1150 for ( ; ndx < MDP4_MIXER_STAGE_MAX; ndx++) {
1151 pipe = ctrl->stage[mixer_num][ndx];
1152 if (pipe == NULL)
1153 continue;
1154 info->z_order = pipe->mixer_stage - MDP4_MIXER_STAGE0;
1155 info->ptype = pipe->pipe_type;
1156 info->pnum = pipe->pipe_num;
1157 info->pndx = pipe->pipe_ndx;
1158 info->mixer_num = pipe->mixer_num;
1159 info++;
1160 cnt++;
1161 }
1162 return cnt;
1163}
1164
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001165void mdp4_mixer_stage_up(struct mdp4_overlay_pipe *pipe)
1166{
1167 uint32 data, mask, snum, stage, mixer, pnum;
1168
1169 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
1170
1171 stage = pipe->mixer_stage;
1172 mixer = pipe->mixer_num;
1173 pnum = pipe->pipe_num;
1174
1175 /* MDP_LAYERMIXER_IN_CFG, shard by both mixer 0 and 1 */
1176 data = inpdw(MDP_BASE + 0x10100);
1177
1178 if (mixer == MDP4_MIXER1)
1179 stage += 8;
1180
1181 if (pipe->pipe_num >= OVERLAY_PIPE_VG1) {/* VG1 and VG2 */
1182 pnum -= OVERLAY_PIPE_VG1; /* start from 0 */
1183 snum = 0;
1184 snum += (4 * pnum);
1185 } else {
1186 snum = 8;
1187 snum += (4 * pnum); /* RGB1 and RGB2 */
1188 }
1189
1190 mask = 0x0f;
1191 mask <<= snum;
1192 stage <<= snum;
1193 data &= ~mask; /* clear old bits */
1194
1195 data |= stage;
1196
1197 outpdw(MDP_BASE + 0x10100, data); /* MDP_LAYERMIXER_IN_CFG */
1198
1199 data = inpdw(MDP_BASE + 0x10100);
1200
1201 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
1202
1203 ctrl->stage[pipe->mixer_num][pipe->mixer_stage] = pipe; /* keep it */
1204}
1205
1206void mdp4_mixer_stage_down(struct mdp4_overlay_pipe *pipe)
1207{
1208 uint32 data, mask, snum, stage, mixer, pnum;
1209
1210 stage = pipe->mixer_stage;
1211 mixer = pipe->mixer_num;
1212 pnum = pipe->pipe_num;
1213
1214 if (pipe != ctrl->stage[mixer][stage]) /* not runing */
1215 return;
1216
1217 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
1218
1219 /* MDP_LAYERMIXER_IN_CFG, shard by both mixer 0 and 1 */
1220 data = inpdw(MDP_BASE + 0x10100);
1221
1222 if (mixer == MDP4_MIXER1)
1223 stage += 8;
1224
1225 if (pipe->pipe_num >= OVERLAY_PIPE_VG1) {/* VG1 and VG2 */
1226 pnum -= OVERLAY_PIPE_VG1; /* start from 0 */
1227 snum = 0;
1228 snum += (4 * pnum);
1229 } else {
1230 snum = 8;
1231 snum += (4 * pnum); /* RGB1 and RGB2 */
1232 }
1233
1234 mask = 0x0f;
1235 mask <<= snum;
1236 data &= ~mask; /* clear old bits */
1237
1238 outpdw(MDP_BASE + 0x10100, data); /* MDP_LAYERMIXER_IN_CFG */
1239
1240 data = inpdw(MDP_BASE + 0x10100);
1241
1242 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
1243
1244 ctrl->stage[pipe->mixer_num][pipe->mixer_stage] = NULL; /* clear it */
1245}
1246
1247void mdp4_mixer_blend_setup(struct mdp4_overlay_pipe *pipe)
1248{
1249 struct mdp4_overlay_pipe *bg_pipe;
1250 unsigned char *overlay_base, *rgb_base;
1251 uint32 c0, c1, c2, blend_op, constant_color = 0, rgb_src_format;
1252 int off;
1253
1254 if (pipe->mixer_num) /* mixer number, /dev/fb0, /dev/fb1 */
1255 overlay_base = MDP_BASE + MDP4_OVERLAYPROC1_BASE;/* 0x18000 */
1256 else
1257 overlay_base = MDP_BASE + MDP4_OVERLAYPROC0_BASE;/* 0x10000 */
1258
1259 /* stage 0 to stage 2 */
1260 off = 0x20 * (pipe->mixer_stage - MDP4_MIXER_STAGE0);
1261
1262 bg_pipe = mdp4_overlay_stage_pipe(pipe->mixer_num,
1263 MDP4_MIXER_STAGE_BASE);
1264 if (bg_pipe == NULL) {
1265 pr_err("%s: Error: no bg_pipe\n", __func__);
1266 return;
1267 }
1268
1269 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
1270
1271 blend_op = 0;
1272
1273 if (pipe->is_fg) {
1274 blend_op |= (MDP4_BLEND_FG_ALPHA_FG_CONST |
1275 MDP4_BLEND_BG_ALPHA_BG_CONST);
1276 outpdw(overlay_base + off + 0x108, pipe->alpha);
1277 outpdw(overlay_base + off + 0x10c, 0xff - pipe->alpha);
1278 if (pipe->alpha == 0xff) {
1279 rgb_base = MDP_BASE + MDP4_RGB_BASE;
1280 rgb_base += MDP4_RGB_OFF * bg_pipe->pipe_num;
1281 rgb_src_format = inpdw(rgb_base + 0x50);
1282 rgb_src_format |= MDP4_FORMAT_SOLID_FILL;
1283 outpdw(rgb_base + 0x50, rgb_src_format);
1284 outpdw(rgb_base + 0x1008, constant_color);
1285 }
1286 } else {
1287 if (bg_pipe->alpha_enable && pipe->alpha_enable) {
1288 /* both pipe have alpha */
1289 blend_op |= (MDP4_BLEND_FG_ALPHA_BG_PIXEL |
1290 MDP4_BLEND_FG_INV_ALPHA |
1291 MDP4_BLEND_BG_ALPHA_BG_PIXEL);
1292 } else if (bg_pipe->alpha_enable && pipe->alpha_enable == 0) {
1293 /* no alpha on both pipe */
1294 blend_op = (MDP4_BLEND_BG_ALPHA_BG_PIXEL |
1295 MDP4_BLEND_FG_ALPHA_BG_PIXEL |
1296 MDP4_BLEND_FG_INV_ALPHA);
1297 }
1298 }
1299
1300
1301 if (pipe->transp != MDP_TRANSP_NOP) {
1302 if (pipe->is_fg) {
1303 transp_color_key(pipe->src_format, pipe->transp,
1304 &c0, &c1, &c2);
1305 /* Fg blocked */
1306 blend_op |= MDP4_BLEND_FG_TRANSP_EN;
1307 /* lower limit */
1308 outpdw(overlay_base + off + 0x110,
1309 (c1 << 16 | c0));/* low */
1310 outpdw(overlay_base + off + 0x114, c2);/* low */
1311 /* upper limit */
1312 outpdw(overlay_base + off + 0x118,
1313 (c1 << 16 | c0));
1314 outpdw(overlay_base + off + 0x11c, c2);
1315 } else {
1316 transp_color_key(bg_pipe->src_format,
1317 pipe->transp, &c0, &c1, &c2);
1318 /* bg blocked */
1319 blend_op |= MDP4_BLEND_BG_TRANSP_EN;
1320 /* lower limit */
1321 outpdw(overlay_base + 0x180,
1322 (c1 << 16 | c0));/* low */
1323 outpdw(overlay_base + 0x184, c2);/* low */
1324 /* upper limit */
1325 outpdw(overlay_base + 0x188,
1326 (c1 << 16 | c0));/* high */
1327 outpdw(overlay_base + 0x18c, c2);/* high */
1328 }
1329 }
1330
1331 outpdw(overlay_base + off + 0x104, blend_op);
1332
1333 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
1334}
1335
1336void mdp4_overlay_reg_flush(struct mdp4_overlay_pipe *pipe, int all)
1337{
1338 struct mdp4_overlay_pipe *bg_pipe;
1339 uint32 bits = 0;
1340
1341 if (pipe->mixer_num == MDP4_MIXER1)
1342 bits |= 0x02;
1343 else
1344 bits |= 0x01;
1345
1346 if (all) {
1347 if (pipe->pipe_num <= OVERLAY_PIPE_RGB2) {
1348 if (pipe->pipe_num == OVERLAY_PIPE_RGB2)
1349 bits |= 0x20;
1350 else
1351 bits |= 0x10;
1352 } else {
1353 if (pipe->is_fg && pipe->alpha == 0xFF) {
1354 bg_pipe = mdp4_overlay_stage_pipe(
1355 pipe->mixer_num,
1356 MDP4_MIXER_STAGE_BASE);
1357 if (bg_pipe->pipe_num <= OVERLAY_PIPE_RGB2) {
1358 if (bg_pipe->pipe_num ==
1359 OVERLAY_PIPE_RGB2)
1360 bits |= 0x20;
1361 else
1362 bits |= 0x10;
1363 }
1364 }
1365 if (pipe->pipe_num == OVERLAY_PIPE_VG2)
1366 bits |= 0x08;
1367 else
1368 bits |= 0x04;
1369 }
1370 }
1371
1372 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
1373 outpdw(MDP_BASE + 0x18000, bits); /* MDP_OVERLAY_REG_FLUSH */
1374 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
1375}
1376
1377struct mdp4_overlay_pipe *mdp4_overlay_stage_pipe(int mixer, int stage)
1378{
1379 return ctrl->stage[mixer][stage];
1380}
1381
1382struct mdp4_overlay_pipe *mdp4_overlay_ndx2pipe(int ndx)
1383{
1384 struct mdp4_overlay_pipe *pipe;
1385
1386 if (ndx <= 0 || ndx > MDP4_MAX_PIPE)
1387 return NULL;
1388
1389 pipe = &ctrl->plist[ndx - 1]; /* ndx start from 1 */
1390
1391 if (pipe->pipe_used == 0)
1392 return NULL;
1393
1394 return pipe;
1395}
1396
1397struct mdp4_overlay_pipe *mdp4_overlay_pipe_alloc(
1398 int ptype, int mixer, int req_share)
1399{
1400 int i, j, ndx, found;
1401 struct mdp4_overlay_pipe *pipe, *opipe;
1402 struct mdp4_pipe_desc *pd;
1403
1404 found = 0;
1405 pipe = &ctrl->plist[0];
1406
1407 for (i = 0; i < MDP4_MAX_PIPE; i++) {
1408 if (pipe->pipe_type == ptype && pipe->pipe_used == 0) {
1409 pd = &ctrl->ov_pipe[pipe->pipe_num];
1410 if (pd->share) { /* pipe can be shared */
1411 if (pd->ref_cnt == 0) {
1412 /* not yet been used */
1413 found++;
1414 break;
1415 }
1416 /* pipe occupied already */
1417 if (req_share && pd->ref_cnt < MDP4_MAX_SHARE) {
1418 for (j = 0; j < MDP4_MAX_SHARE; j++) {
1419 ndx = pd->ndx_list[j];
1420 if (ndx != 0)
1421 break;
1422 }
1423 /* ndx satrt from 1 */
1424 opipe = &ctrl->plist[ndx - 1];
1425 /*
1426 * occupied pipe willing to share and
1427 * same mixer
1428 */
1429 if (opipe->pipe_share &&
1430 opipe->mixer_num == mixer) {
1431 found++;
1432 break;
1433 }
1434 }
1435 } else { /* not a shared pipe */
1436 if (req_share == 0 && pd->ref_cnt == 0) {
1437 found++;
1438 break;
1439 }
1440 }
1441 }
1442 pipe++;
1443 }
1444
1445 if (found) {
1446 init_completion(&pipe->comp);
1447 init_completion(&pipe->dmas_comp);
1448 pr_info("%s: pipe=%x ndx=%d num=%d share=%d cnt=%d\n",
1449 __func__, (int)pipe, pipe->pipe_ndx, pipe->pipe_num,
1450 pd->share, pd->ref_cnt);
1451 return pipe;
1452 }
1453
1454 pr_debug("%s: ptype=%d mixer=%d req_share=%d FAILED\n",
1455 __func__, ptype, mixer, req_share);
1456
1457 return NULL;
1458}
1459
1460
1461void mdp4_overlay_pipe_free(struct mdp4_overlay_pipe *pipe)
1462{
1463 int i;
1464 uint32 ptype, num, ndx;
1465 struct mdp4_pipe_desc *pd;
1466
1467 pr_debug("%s: pipe=%x ndx=%d\n", __func__,
1468 (int)pipe, pipe->pipe_ndx);
1469 pd = &ctrl->ov_pipe[pipe->pipe_num];
1470 if (pd->ref_cnt) {
1471 pd->ref_cnt--;
1472 for (i = 0; i < MDP4_MAX_SHARE; i++) {
1473 if (pd->ndx_list[i] == pipe->pipe_ndx) {
1474 pd->ndx_list[i] = 0;
1475 break;
1476 }
1477 }
1478 }
1479
1480 pd->player = NULL;
1481
1482 ptype = pipe->pipe_type;
1483 num = pipe->pipe_num;
1484 ndx = pipe->pipe_ndx;
1485
1486 memset(pipe, 0, sizeof(*pipe));
1487
1488 pipe->pipe_type = ptype;
1489 pipe->pipe_num = num;
1490 pipe->pipe_ndx = ndx;
1491}
1492
1493int mdp4_overlay_req_check(uint32 id, uint32 z_order, uint32 mixer)
1494{
1495 struct mdp4_overlay_pipe *pipe;
1496
1497 pipe = ctrl->stage[mixer][z_order];
1498
1499 if (pipe == NULL)
1500 return 0;
1501
1502 if (pipe->pipe_ndx == id) /* same req, recycle */
1503 return 0;
1504
1505 if (id == MSMFB_NEW_REQUEST) { /* new request */
1506 if (pipe->pipe_num >= OVERLAY_PIPE_VG1) /* share pipe */
1507 return 0;
1508 }
1509
1510 return -EPERM;
1511}
1512
1513static int mdp4_overlay_validate_downscale(struct mdp_overlay *req,
1514 struct msm_fb_data_type *mfd, uint32 perf_level, uint32 pclk_rate)
1515{
1516 __u32 panel_clk_khz, mdp_clk_khz;
1517 __u32 num_hsync_pix_clks, mdp_clks_per_hsync, src_wh;
1518 __u32 hsync_period_ps, mdp_period_ps, total_hsync_period_ps;
1519 unsigned long fill_rate_y_dir, fill_rate_x_dir;
1520 unsigned long fillratex100, mdp_pixels_produced;
1521 unsigned long mdp_clk_hz;
1522
1523 pr_debug("%s: LCDC Mode Downscale validation with MDP Core"
1524 " Clk rate\n", __func__);
1525 pr_debug("src_w %u, src_h %u, dst_w %u, dst_h %u\n",
1526 req->src_rect.w, req->src_rect.h, req->dst_rect.w,
1527 req->dst_rect.h);
1528
1529
1530 panel_clk_khz = pclk_rate/1000;
1531 mdp_clk_hz = mdp_perf_level2clk_rate(perf_level);
1532
1533 if (!mdp_clk_hz) {
1534 pr_debug("mdp_perf_level2clk_rate returned 0,"
1535 "Downscale Validation incomplete\n");
1536 return 0;
1537 }
1538
1539 mdp_clk_khz = mdp_clk_hz/1000;
1540
1541 num_hsync_pix_clks = mfd->panel_info.lcdc.h_back_porch +
1542 mfd->panel_info.lcdc.h_front_porch +
1543 mfd->panel_info.lcdc.h_pulse_width +
1544 mfd->panel_info.xres;
1545
1546 hsync_period_ps = 1000000000/panel_clk_khz;
1547 mdp_period_ps = 1000000000/mdp_clk_khz;
1548
1549 total_hsync_period_ps = num_hsync_pix_clks * hsync_period_ps;
1550 mdp_clks_per_hsync = total_hsync_period_ps/mdp_period_ps;
1551
1552 pr_debug("hsync_period_ps %u, mdp_period_ps %u,"
1553 "total_hsync_period_ps %u\n", hsync_period_ps,
1554 mdp_period_ps, total_hsync_period_ps);
1555
1556 src_wh = req->src_rect.w * req->src_rect.h;
1557 if (src_wh % req->dst_rect.h)
1558 fill_rate_y_dir = (src_wh / req->dst_rect.h) + 1;
1559 else
1560 fill_rate_y_dir = (src_wh / req->dst_rect.h);
1561
1562 fill_rate_x_dir = (mfd->panel_info.xres - req->dst_rect.w)
1563 + req->src_rect.w;
1564
1565 if (fill_rate_y_dir >= fill_rate_x_dir)
1566 fillratex100 = 100 * fill_rate_y_dir / mfd->panel_info.xres;
1567 else
1568 fillratex100 = 100 * fill_rate_x_dir / mfd->panel_info.xres;
1569
1570 pr_debug("mdp_clks_per_hsync %u, fill_rate_y_dir %lu,"
1571 "fill_rate_x_dir %lu\n", mdp_clks_per_hsync,
1572 fill_rate_y_dir, fill_rate_x_dir);
1573
1574 mdp_pixels_produced = 100 * mdp_clks_per_hsync/fillratex100;
1575 pr_debug("fillratex100 %lu, mdp_pixels_produced %lu\n",
1576 fillratex100, mdp_pixels_produced);
1577 if (mdp_pixels_produced <= mfd->panel_info.xres) {
1578 pr_err("%s(): LCDC underflow detected during downscale\n",
1579 __func__);
1580 return -ERANGE;
1581 }
1582
1583 return 0;
1584}
1585
1586static int mdp4_overlay_req2pipe(struct mdp_overlay *req, int mixer,
1587 struct mdp4_overlay_pipe **ppipe,
1588 struct msm_fb_data_type *mfd)
1589{
1590 struct mdp4_overlay_pipe *pipe;
1591 struct mdp4_pipe_desc *pd;
1592 int ret, ptype, req_share;
1593 int j;
1594
1595 if (mfd == NULL) {
1596 pr_err("%s: mfd == NULL, -ENODEV\n", __func__);
1597 return -ENODEV;
1598 }
1599
1600 if (mixer >= MDP4_MAX_MIXER) {
1601 pr_err("%s: mixer out of range!\n", __func__);
1602 mdp4_stat.err_mixer++;
1603 return -ERANGE;
1604 }
1605
1606 if (req->z_order < 0 || req->z_order > 2) {
1607 pr_err("%s: z_order=%d out of range!\n", __func__,
1608 req->z_order);
1609 mdp4_stat.err_zorder++;
1610 return -ERANGE;
1611 }
1612
1613 if (req->src_rect.h == 0 || req->src_rect.w == 0) {
1614 pr_err("%s: src img of zero size!\n", __func__);
1615 mdp4_stat.err_size++;
1616 return -EINVAL;
1617 }
1618
1619
1620 if (req->dst_rect.h > (req->src_rect.h * 8)) { /* too much */
1621 mdp4_stat.err_scale++;
1622 pr_err("%s: scale up, too much (h)!\n", __func__);
1623 return -ERANGE;
1624 }
1625
1626 if (req->src_rect.h > (req->dst_rect.h * 8)) { /* too little */
1627 mdp4_stat.err_scale++;
1628 pr_err("%s: scale down, too little (h)!\n", __func__);
1629 return -ERANGE;
1630 }
1631
1632 if (req->dst_rect.w > (req->src_rect.w * 8)) { /* too much */
1633 mdp4_stat.err_scale++;
1634 pr_err("%s: scale up, too much (w)!\n", __func__);
1635 return -ERANGE;
1636 }
1637
1638 if (req->src_rect.w > (req->dst_rect.w * 8)) { /* too little */
1639 mdp4_stat.err_scale++;
1640 pr_err("%s: scale down, too little (w)!\n", __func__);
1641 return -ERANGE;
1642 }
1643
1644 if (mdp_hw_revision == MDP4_REVISION_V1) {
1645 /* non integer down saceling ratio smaller than 1/4
1646 * is not supportted
1647 */
1648 if (req->src_rect.h > (req->dst_rect.h * 4)) {
1649 if (req->src_rect.h % req->dst_rect.h) {
1650 mdp4_stat.err_scale++;
1651 pr_err("%s: need integer (h)!\n", __func__);
1652 return -ERANGE;
1653 }
1654 }
1655
1656 if (req->src_rect.w > (req->dst_rect.w * 4)) {
1657 if (req->src_rect.w % req->dst_rect.w) {
1658 mdp4_stat.err_scale++;
1659 pr_err("%s: need integer (w)!\n", __func__);
1660 return -ERANGE;
1661 }
1662 }
1663 }
1664
1665 if (((req->src_rect.x + req->src_rect.w) > req->src.width) ||
1666 ((req->src_rect.y + req->src_rect.h) > req->src.height)) {
1667 mdp4_stat.err_size++;
1668 pr_err("%s invalid src rectangle\n", __func__);
1669 return -ERANGE;
1670 }
1671
1672 if (ctrl->panel_3d != MDP4_3D_SIDE_BY_SIDE) {
1673 int xres;
1674 int yres;
1675
1676 xres = mfd->panel_info.xres;
1677 yres = mfd->panel_info.yres;
1678
1679 if (((req->dst_rect.x + req->dst_rect.w) > xres) ||
1680 ((req->dst_rect.y + req->dst_rect.h) > yres)) {
1681 mdp4_stat.err_size++;
1682 pr_err("%s invalid dst rectangle\n", __func__);
1683 return -ERANGE;
1684 }
1685 }
1686
1687 ptype = mdp4_overlay_format2type(req->src.format);
1688 if (ptype < 0) {
1689 pr_err("%s: mdp4_overlay_format2type!\n", __func__);
1690 return ptype;
1691 }
1692
1693 req_share = (req->flags & MDP_OV_PIPE_SHARE);
1694
1695 if (req->id == MSMFB_NEW_REQUEST) /* new request */
1696 pipe = mdp4_overlay_pipe_alloc(ptype, mixer, req_share);
1697 else
1698 pipe = mdp4_overlay_ndx2pipe(req->id);
1699
1700 if (pipe == NULL) {
1701 pr_err("%s: pipe == NULL!\n", __func__);
1702 return -ENOMEM;
1703 }
1704
1705 /* no down scale at rgb pipe */
1706 if (pipe->pipe_num <= OVERLAY_PIPE_RGB2) {
1707 if ((req->src_rect.h > req->dst_rect.h) ||
1708 (req->src_rect.w > req->dst_rect.w)) {
1709 pr_err("%s: h>h || w>w!\n", __func__);
1710 return -ERANGE;
1711 }
1712 }
1713
1714 pipe->src_format = req->src.format;
1715 ret = mdp4_overlay_format2pipe(pipe);
1716 if (ret < 0) {
1717 pr_err("%s: mdp4_overlay_format2pipe!\n", __func__);
1718 return ret;
1719 }
1720
1721 /*
1722 * base layer == 1, reserved for frame buffer
1723 * zorder 0 == stage 0 == 2
1724 * zorder 1 == stage 1 == 3
1725 * zorder 2 == stage 2 == 4
1726 */
1727 if (req->id == MSMFB_NEW_REQUEST) { /* new request */
1728 pd = &ctrl->ov_pipe[pipe->pipe_num];
1729 for (j = 0; j < MDP4_MAX_SHARE; j++) {
1730 if (pd->ndx_list[j] == 0) {
1731 pd->ndx_list[j] = pipe->pipe_ndx;
1732 break;
1733 }
1734 }
1735 pipe->pipe_share = req_share;
1736 pd->ref_cnt++;
1737 pipe->pipe_used++;
1738 pipe->mixer_num = mixer;
1739 pipe->mixer_stage = req->z_order + MDP4_MIXER_STAGE0;
1740 pr_debug("%s: zorder=%d pipe ndx=%d num=%d\n", __func__,
1741 req->z_order, pipe->pipe_ndx, pipe->pipe_num);
1742
1743 }
1744
1745 pipe->src_width = req->src.width & 0x07ff; /* source img width */
1746 pipe->src_height = req->src.height & 0x07ff; /* source img height */
1747 pipe->src_h = req->src_rect.h & 0x07ff;
1748 pipe->src_w = req->src_rect.w & 0x07ff;
1749 pipe->src_y = req->src_rect.y & 0x07ff;
1750 pipe->src_x = req->src_rect.x & 0x07ff;
1751 pipe->dst_h = req->dst_rect.h & 0x07ff;
1752 pipe->dst_w = req->dst_rect.w & 0x07ff;
1753 pipe->dst_y = req->dst_rect.y & 0x07ff;
1754 pipe->dst_x = req->dst_rect.x & 0x07ff;
1755
1756 pipe->op_mode = 0;
1757
1758 if (req->flags & MDP_FLIP_LR)
1759 pipe->op_mode |= MDP4_OP_FLIP_LR;
1760
1761 if (req->flags & MDP_FLIP_UD)
1762 pipe->op_mode |= MDP4_OP_FLIP_UD;
1763
1764 if (req->flags & MDP_DITHER)
1765 pipe->op_mode |= MDP4_OP_DITHER_EN;
1766
1767 if (req->flags & MDP_DEINTERLACE)
1768 pipe->op_mode |= MDP4_OP_DEINT_EN;
1769
1770 if (req->flags & MDP_DEINTERLACE_ODD)
1771 pipe->op_mode |= MDP4_OP_DEINT_ODD_REF;
1772
1773 pipe->is_fg = req->is_fg;/* control alpha and color key */
1774
1775 pipe->alpha = req->alpha & 0x0ff;
1776
1777 pipe->transp = req->transp_mask;
1778
1779 *ppipe = pipe;
1780
1781 return 0;
1782}
1783
1784static int get_img(struct msmfb_data *img, struct fb_info *info,
1785 unsigned long *start, unsigned long *len, struct file **pp_file)
1786{
1787 int put_needed, ret = 0, fb_num;
1788 struct file *file;
1789#ifdef CONFIG_ANDROID_PMEM
1790 unsigned long vstart;
1791#endif
1792
1793 if (img->flags & MDP_BLIT_SRC_GEM) {
1794 *pp_file = NULL;
1795 return kgsl_gem_obj_addr(img->memory_id, (int) img->priv,
1796 start, len);
1797 }
1798
1799#ifdef CONFIG_ANDROID_PMEM
1800 if (!get_pmem_file(img->memory_id, start, &vstart, len, pp_file))
1801 return 0;
1802#endif
1803 file = fget_light(img->memory_id, &put_needed);
1804 if (file == NULL)
1805 return -1;
1806
1807 if (MAJOR(file->f_dentry->d_inode->i_rdev) == FB_MAJOR) {
1808 fb_num = MINOR(file->f_dentry->d_inode->i_rdev);
1809 if (get_fb_phys_info(start, len, fb_num))
1810 ret = -1;
1811 else
1812 *pp_file = file;
1813 } else
1814 ret = -1;
1815 if (ret)
1816 fput_light(file, put_needed);
1817 return ret;
1818}
1819
kuogee hsieh4aea2742011-07-06 11:05:05 -07001820#ifdef CONFIG_FB_MSM_MIPI_DSI
1821int mdp4_overlay_3d_sbys(struct fb_info *info, struct msmfb_overlay_3d *req)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001822{
1823 struct msm_fb_data_type *mfd = (struct msm_fb_data_type *)info->par;
1824 int ret = -EPERM;
1825
1826 if (mutex_lock_interruptible(&mfd->dma->ov_mutex))
1827 return -EINTR;
1828
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001829 if (ctrl->panel_mode & MDP4_PANEL_DSI_CMD) {
kuogee hsieh4aea2742011-07-06 11:05:05 -07001830 mdp4_dsi_cmd_3d_sbys(mfd, req);
1831 ret = 0;
1832 } else if (ctrl->panel_mode & MDP4_PANEL_DSI_VIDEO) {
1833 mdp4_dsi_video_3d_sbys(mfd, req);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001834 ret = 0;
1835 }
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001836 mutex_unlock(&mfd->dma->ov_mutex);
1837
1838 return ret;
1839}
kuogee hsieh4aea2742011-07-06 11:05:05 -07001840#else
1841int mdp4_overlay_3d_sbys(struct fb_info *info, struct msmfb_overlay_3d *req)
1842{
1843 /* do nothing */
1844 return -EPERM;
1845}
1846#endif
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001847
1848#ifdef CONFIG_FB_MSM_OVERLAY_WRITEBACK
1849int mdp4_overlay_blt(struct fb_info *info, struct msmfb_overlay_blt *req)
1850{
1851 struct msm_fb_data_type *mfd = (struct msm_fb_data_type *)info->par;
1852
1853 if (mfd == NULL)
1854 return -ENODEV;
1855
1856 if (mutex_lock_interruptible(&mfd->dma->ov_mutex))
1857 return -EINTR;
1858
1859 if (ctrl->panel_mode & MDP4_PANEL_DSI_CMD)
1860 mdp4_dsi_overlay_blt(mfd, req);
1861 else if (ctrl->panel_mode & MDP4_PANEL_DSI_VIDEO)
1862 mdp4_dsi_video_overlay_blt(mfd, req);
1863 else if (ctrl->panel_mode & MDP4_PANEL_LCDC)
1864 mdp4_lcdc_overlay_blt(mfd, req);
1865
1866 mutex_unlock(&mfd->dma->ov_mutex);
1867
1868 return 0;
1869}
1870
1871int mdp4_overlay_blt_offset(struct fb_info *info, struct msmfb_overlay_blt *req)
1872{
1873 int ret = 0;
1874
1875 struct msm_fb_data_type *mfd = (struct msm_fb_data_type *)info->par;
1876
1877 if (mutex_lock_interruptible(&mfd->dma->ov_mutex))
1878 return -EINTR;
1879
1880 if (ctrl->panel_mode & MDP4_PANEL_DSI_CMD)
1881 ret = mdp4_dsi_overlay_blt_offset(mfd, req);
1882 else if (ctrl->panel_mode & MDP4_PANEL_DSI_VIDEO)
1883 ret = mdp4_dsi_video_overlay_blt_offset(mfd, req);
1884 else if (ctrl->panel_mode & MDP4_PANEL_LCDC)
1885 ret = mdp4_lcdc_overlay_blt_offset(mfd, req);
1886
1887 mutex_unlock(&mfd->dma->ov_mutex);
1888
1889 return ret;
1890}
1891#endif
1892
1893int mdp4_overlay_get(struct fb_info *info, struct mdp_overlay *req)
1894{
1895 struct mdp4_overlay_pipe *pipe;
1896
1897 pipe = mdp4_overlay_ndx2pipe(req->id);
1898 if (pipe == NULL)
1899 return -ENODEV;
1900
1901 *req = pipe->req_data;
1902
1903 return 0;
1904}
1905
1906#define OVERLAY_VGA_SIZE 0x04B000
1907#define OVERLAY_720P_TILE_SIZE 0x0E6000
1908#define OVERLAY_WSVGA_SIZE 0x98000 /* 1024x608, align 600 to 32bit */
1909#define OVERLAY_PERF_LEVEL1 1
1910#define OVERLAY_PERF_LEVEL2 2
1911#define OVERLAY_PERF_LEVEL3 3
1912#define OVERLAY_PERF_LEVEL4 4
1913
1914#ifdef CONFIG_MSM_BUS_SCALING
1915#define OVERLAY_BUS_SCALE_TABLE_BASE 6
1916#endif
1917
1918static int mdp4_overlay_is_rgb_type(int format)
1919{
1920 switch (format) {
1921 case MDP_RGB_565:
1922 case MDP_RGB_888:
1923 case MDP_BGR_565:
1924 case MDP_XRGB_8888:
1925 case MDP_ARGB_8888:
1926 case MDP_RGBA_8888:
1927 case MDP_BGRA_8888:
1928 case MDP_RGBX_8888:
1929 return 1;
1930 default:
1931 return 0;
1932 }
1933}
1934
1935static uint32 mdp4_overlay_get_perf_level(struct mdp_overlay *req)
1936{
1937 int is_fg;
1938
1939 if (req->is_fg && ((req->alpha & 0x0ff) == 0xff))
1940 is_fg = 1;
1941
1942 if (req->flags & MDP_DEINTERLACE)
1943 return OVERLAY_PERF_LEVEL1;
1944
1945 if (mdp4_overlay_is_rgb_type(req->src.format) && is_fg &&
1946 ((req->src.width * req->src.height) <= OVERLAY_WSVGA_SIZE))
1947 return OVERLAY_PERF_LEVEL4;
1948 else if (mdp4_overlay_is_rgb_type(req->src.format))
1949 return OVERLAY_PERF_LEVEL1;
1950
1951 if (ctrl->ov_pipe[OVERLAY_PIPE_VG1].ref_cnt &&
1952 ctrl->ov_pipe[OVERLAY_PIPE_VG2].ref_cnt)
1953 return OVERLAY_PERF_LEVEL1;
1954
1955 if (req->src.width*req->src.height <= OVERLAY_VGA_SIZE)
1956 return OVERLAY_PERF_LEVEL3;
1957 else if (req->src.width*req->src.height <= OVERLAY_720P_TILE_SIZE)
1958 return OVERLAY_PERF_LEVEL2;
1959 else
1960 return OVERLAY_PERF_LEVEL1;
1961}
1962
kuogee hsiehc4b8b2f2011-07-12 13:32:14 -07001963void mdp4_set_perf_level(void)
1964{
1965 static int old_perf_level;
1966
1967 if (old_perf_level != new_perf_level) {
1968 mdp_set_core_clk(new_perf_level);
1969 old_perf_level = new_perf_level;
1970 }
1971}
1972
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001973int mdp4_overlay_set(struct fb_info *info, struct mdp_overlay *req)
1974{
1975 struct msm_fb_data_type *mfd = (struct msm_fb_data_type *)info->par;
kuogee hsiehc4b8b2f2011-07-12 13:32:14 -07001976 int ret, mixer, perf_level;
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001977 struct mdp4_overlay_pipe *pipe;
kuogee hsieh9452ecb2011-08-01 18:26:23 -07001978 uint32 flags;
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001979
1980 if (mfd == NULL) {
1981 pr_err("%s: mfd == NULL, -ENODEV\n", __func__);
1982 return -ENODEV;
1983 }
1984
1985 if (!mfd->panel_power_on) /* suspended */
1986 return -EPERM;
1987
1988 if (req->src.format == MDP_FB_FORMAT)
1989 req->src.format = mfd->fb_imgType;
1990
1991 if (mutex_lock_interruptible(&mfd->dma->ov_mutex)) {
1992 pr_err("%s: mutex_lock_interruptible, -EINTR\n", __func__);
1993 return -EINTR;
1994 }
1995
1996 perf_level = mdp4_overlay_get_perf_level(req);
1997
1998 if ((mfd->panel_info.type == LCDC_PANEL) &&
1999 (req->src_rect.h >
2000 req->dst_rect.h || req->src_rect.w > req->dst_rect.w)) {
2001 if (mdp4_overlay_validate_downscale(req, mfd,
2002 perf_level, mfd->panel_info.clk_rate)) {
2003 mutex_unlock(&mfd->dma->ov_mutex);
2004 return -ERANGE;
2005 }
2006 }
kuogee hsieh4d3c7792011-07-25 11:02:24 -07002007
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002008 if ((mfd->panel_info.type == MIPI_VIDEO_PANEL) &&
2009 (req->src_rect.h >
2010 req->dst_rect.h || req->src_rect.w > req->dst_rect.w)) {
2011 if (mdp4_overlay_validate_downscale(req, mfd,
kuogee hsieh4d3c7792011-07-25 11:02:24 -07002012 perf_level, (&mfd->panel_info.mipi)->dsi_pclk_rate))
2013 mdp4_dsi_video_blt_start(mfd);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002014 }
kuogee hsieh4d3c7792011-07-25 11:02:24 -07002015
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002016 mixer = mfd->panel_info.pdest; /* DISPLAY_1 or DISPLAY_2 */
2017
2018 ret = mdp4_overlay_req2pipe(req, mixer, &pipe, mfd);
2019 if (ret < 0) {
2020 mutex_unlock(&mfd->dma->ov_mutex);
2021 pr_err("%s: mdp4_overlay_req2pipe, ret=%d\n", __func__, ret);
2022 return ret;
2023 }
2024
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002025 /*
2026 * writeback (blt) mode to provide work around for
2027 * dsi cmd mode interface hardware bug.
2028 */
2029 if (ctrl->panel_mode & MDP4_PANEL_DSI_CMD) {
2030 if (mixer == MDP4_MIXER0 && req->dst_rect.x != 0) {
2031 mdp4_dsi_blt_dmap_busy_wait(mfd);
2032 mdp4_dsi_overlay_blt_start(mfd);
2033 }
2034 }
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002035
2036 /* return id back to user */
2037 req->id = pipe->pipe_ndx; /* pipe_ndx start from 1 */
2038 pipe->req_data = *req; /* keep original req */
2039
2040 pipe->flags = req->flags;
2041
2042 if (pipe->flags & MDP_SHARPENING) {
2043 bool test = ((pipe->req_data.dpp.sharp_strength > 0) &&
2044 ((req->src_rect.w > req->dst_rect.w) &&
2045 (req->src_rect.h > req->dst_rect.h)));
2046 if (test) {
2047 pr_warn("%s: No sharpening while downscaling.\n",
2048 __func__);
2049 pipe->flags &= ~MDP_SHARPENING;
2050 }
2051 }
2052
2053 mdp4_stat.overlay_set[pipe->mixer_num]++;
2054
2055 if (ctrl->panel_mode & MDP4_PANEL_MDDI) {
2056 if (mdp_hw_revision == MDP4_REVISION_V2_1 &&
2057 pipe->mixer_num == MDP4_MIXER0)
2058 mdp4_overlay_status_write(MDP4_OVERLAY_TYPE_SET, true);
2059 }
2060
kuogee hsiehc4b8b2f2011-07-12 13:32:14 -07002061
Adrian Salido-Moreno5e912032011-08-29 11:15:47 -07002062 if (new_perf_level != perf_level) {
2063 new_perf_level = perf_level;
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002064
Adrian Salido-Moreno5e912032011-08-29 11:15:47 -07002065 /* change clck base on perf level */
2066 flags = pipe->flags;
2067 pipe->flags &= ~MDP_OV_PLAY_NOWAIT;
2068 if (pipe->mixer_num == MDP4_MIXER0) {
2069 if (ctrl->panel_mode & MDP4_PANEL_DSI_VIDEO) {
2070 mdp4_overlay_dsi_video_vsync_push(mfd, pipe);
2071 } else if (ctrl->panel_mode & MDP4_PANEL_DSI_CMD) {
2072 mdp4_dsi_cmd_dma_busy_wait(mfd);
2073 mdp4_dsi_blt_dmap_busy_wait(mfd);
2074 mdp4_set_perf_level();
2075 } else if (ctrl->panel_mode & MDP4_PANEL_LCDC) {
2076 mdp4_overlay_lcdc_vsync_push(mfd, pipe);
2077 } else if (ctrl->panel_mode & MDP4_PANEL_MDDI) {
2078 mdp4_mddi_dma_busy_wait(mfd);
2079 mdp4_set_perf_level();
2080 }
2081 } else {
2082 if (ctrl->panel_mode & MDP4_PANEL_DTV)
2083 mdp4_overlay_dtv_vsync_push(mfd, pipe);
kuogee hsieh9452ecb2011-08-01 18:26:23 -07002084 }
Adrian Salido-Moreno5e912032011-08-29 11:15:47 -07002085 pipe->flags = flags;
kuogee hsieh9452ecb2011-08-01 18:26:23 -07002086 }
kuogee hsieh9452ecb2011-08-01 18:26:23 -07002087
2088 mutex_unlock(&mfd->dma->ov_mutex);
2089
2090
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002091#ifdef CONFIG_MSM_BUS_SCALING
2092 if (pipe->mixer_num == MDP4_MIXER0) {
2093 mdp_bus_scale_update_request(OVERLAY_BUS_SCALE_TABLE_BASE
2094 - perf_level);
2095 }
2096#endif
2097
2098 return 0;
2099}
2100
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002101int mdp4_overlay_unset(struct fb_info *info, int ndx)
2102{
2103 struct msm_fb_data_type *mfd = (struct msm_fb_data_type *)info->par;
2104 struct mdp4_overlay_pipe *pipe;
2105 uint32 flags;
2106
2107 if (mfd == NULL)
2108 return -ENODEV;
2109
2110 if (mutex_lock_interruptible(&mfd->dma->ov_mutex))
2111 return -EINTR;
2112
2113 pipe = mdp4_overlay_ndx2pipe(ndx);
2114
2115 if (pipe == NULL) {
2116 mutex_unlock(&mfd->dma->ov_mutex);
2117 return -ENODEV;
2118 }
2119
2120 if (pipe->mixer_num == MDP4_MIXER1)
2121 ctrl->mixer1_played = 0;
2122 else {
2123 /* mixer 0 */
2124 ctrl->mixer0_played = 0;
2125#ifdef CONFIG_FB_MSM_MIPI_DSI
2126 if (ctrl->panel_mode & MDP4_PANEL_DSI_CMD) {
2127 if (mfd->panel_power_on) {
2128 mdp4_dsi_blt_dmap_busy_wait(mfd);
2129 }
2130 }
2131#else
2132 if (ctrl->panel_mode & MDP4_PANEL_MDDI) {
2133 if (mfd->panel_power_on)
2134 mdp4_mddi_dma_busy_wait(mfd);
2135 }
2136#endif
2137 }
2138
2139 mdp4_mixer_stage_down(pipe);
2140
2141 if (pipe->mixer_num == MDP4_MIXER0) {
2142#ifdef CONFIG_FB_MSM_MIPI_DSI
2143 if (ctrl->panel_mode & MDP4_PANEL_DSI_CMD) {
2144 if (mfd->panel_power_on)
2145 if (mdp4_dsi_overlay_blt_stop(mfd) == 0)
2146 mdp4_dsi_cmd_overlay_restore();
2147 } else if (ctrl->panel_mode & MDP4_PANEL_DSI_VIDEO) {
2148 flags = pipe->flags;
2149 pipe->flags &= ~MDP_OV_PLAY_NOWAIT;
kuogee hsiehebca0c72011-07-14 13:30:33 -07002150 mdp4_overlay_reg_flush(pipe, 1);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002151 mdp4_overlay_dsi_video_vsync_push(mfd, pipe);
2152 pipe->flags = flags;
kuogee hsieh4d3c7792011-07-25 11:02:24 -07002153 mdp4_dsi_video_blt_stop(mfd);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002154 }
2155#else
2156 if (ctrl->panel_mode & MDP4_PANEL_MDDI) {
2157 if (mdp_hw_revision == MDP4_REVISION_V2_1)
2158 mdp4_overlay_status_write(
2159 MDP4_OVERLAY_TYPE_UNSET, true);
2160 if (mfd->panel_power_on)
2161 mdp4_mddi_overlay_restore();
2162 }
2163#endif
2164 else if (ctrl->panel_mode & MDP4_PANEL_LCDC) {
2165 flags = pipe->flags;
2166 pipe->flags &= ~MDP_OV_PLAY_NOWAIT;
kuogee hsiehebca0c72011-07-14 13:30:33 -07002167 mdp4_overlay_reg_flush(pipe, 1);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002168 mdp4_overlay_lcdc_vsync_push(mfd, pipe);
2169 pipe->flags = flags;
2170 }
2171 }
2172#ifdef CONFIG_FB_MSM_DTV
2173 else { /* mixer1, DTV, ATV */
kuogee hsieh9452ecb2011-08-01 18:26:23 -07002174 if (ctrl->panel_mode & MDP4_PANEL_DTV) {
2175 flags = pipe->flags;
2176 pipe->flags &= ~MDP_OV_PLAY_NOWAIT;
2177 mdp4_overlay_dtv_vsync_push(mfd, pipe);
2178 pipe->flags = flags;
2179 }
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002180 }
2181#endif
2182
2183 mdp4_stat.overlay_unset[pipe->mixer_num]++;
2184
2185 mdp4_overlay_pipe_free(pipe);
2186
2187 if (!(ctrl->ov_pipe[OVERLAY_PIPE_VG1].ref_cnt +
2188 ctrl->ov_pipe[OVERLAY_PIPE_VG2].ref_cnt))
kuogee hsiehc4b8b2f2011-07-12 13:32:14 -07002189 new_perf_level = OVERLAY_PERF_LEVEL4;
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002190
2191 mutex_unlock(&mfd->dma->ov_mutex);
2192
2193#ifdef CONFIG_MSM_BUS_SCALING
2194 if (pipe->mixer_num == MDP4_MIXER0)
2195 if (mfd->panel_power_on)
2196 mdp_bus_scale_update_request(2);
2197#endif
2198 return 0;
2199}
2200
2201struct tile_desc {
2202 uint32 width; /* tile's width */
2203 uint32 height; /* tile's height */
2204 uint32 row_tile_w; /* tiles per row's width */
2205 uint32 row_tile_h; /* tiles per row's height */
2206};
2207
2208void tile_samsung(struct tile_desc *tp)
2209{
2210 /*
2211 * each row of samsung tile consists of two tiles in height
2212 * and two tiles in width which means width should align to
2213 * 64 x 2 bytes and height should align to 32 x 2 bytes.
2214 * video decoder generate two tiles in width and one tile
2215 * in height which ends up height align to 32 X 1 bytes.
2216 */
2217 tp->width = 64; /* 64 bytes */
2218 tp->row_tile_w = 2; /* 2 tiles per row's width */
2219 tp->height = 32; /* 32 bytes */
2220 tp->row_tile_h = 1; /* 1 tiles per row's height */
2221}
2222
2223uint32 tile_mem_size(struct mdp4_overlay_pipe *pipe, struct tile_desc *tp)
2224{
2225 uint32 tile_w, tile_h;
2226 uint32 row_num_w, row_num_h;
2227
2228
2229 tile_w = tp->width * tp->row_tile_w;
2230 tile_h = tp->height * tp->row_tile_h;
2231
2232 row_num_w = (pipe->src_width + tile_w - 1) / tile_w;
2233 row_num_h = (pipe->src_height + tile_h - 1) / tile_h;
2234 return ((row_num_w * row_num_h * tile_w * tile_h) + 8191) & ~8191;
2235}
2236
2237int mdp4_overlay_play(struct fb_info *info, struct msmfb_overlay_data *req,
2238 struct file **pp_src_file, struct file **pp_src_plane1_file,
2239 struct file **pp_src_plane2_file)
2240{
2241 struct msm_fb_data_type *mfd = (struct msm_fb_data_type *)info->par;
2242 struct msmfb_data *img;
2243 struct mdp4_overlay_pipe *pipe;
2244 struct mdp4_pipe_desc *pd;
2245 ulong start, addr;
2246 ulong len = 0;
2247 struct file *p_src_file = 0;
2248 struct file *p_src_plane1_file = 0, *p_src_plane2_file = 0;
2249 uint32_t overlay_version = 0;
2250
2251 if (mfd == NULL)
2252 return -ENODEV;
2253
2254 if (!mfd->panel_power_on) /* suspended */
2255 return -EPERM;
2256
2257 pipe = mdp4_overlay_ndx2pipe(req->id);
2258 if (pipe == NULL) {
2259 pr_err("%s: req_id=%d Error\n", __func__, req->id);
2260 return -ENODEV;
2261 }
2262
2263 if (mutex_lock_interruptible(&mfd->dma->ov_mutex))
2264 return -EINTR;
2265
2266 pd = &ctrl->ov_pipe[pipe->pipe_num];
2267 if (pd->player && pipe != pd->player) {
2268 if (pipe->pipe_type == OVERLAY_TYPE_RGB) {
2269 mutex_unlock(&mfd->dma->ov_mutex);
2270 return 0; /* ignore it, kicked out already */
2271 }
2272 }
2273
2274 pd->player = pipe; /* keep */
2275
2276 img = &req->data;
2277 get_img(img, info, &start, &len, &p_src_file);
2278 if (len == 0) {
2279 mutex_unlock(&mfd->dma->ov_mutex);
2280 pr_err("%s: pmem Error\n", __func__);
2281 return -1;
2282 }
2283 *pp_src_file = p_src_file;
2284
2285 addr = start + img->offset;
2286 pipe->srcp0_addr = addr;
2287 pipe->srcp0_ystride = pipe->src_width * pipe->bpp;
2288
2289 if ((req->version_key & VERSION_KEY_MASK) == 0xF9E8D700)
2290 overlay_version = (req->version_key & ~VERSION_KEY_MASK);
2291
2292 if (pipe->fetch_plane == OVERLAY_PLANE_PSEUDO_PLANAR) {
2293 if (overlay_version > 0) {
2294 img = &req->plane1_data;
2295 get_img(img, info, &start, &len, &p_src_plane1_file);
2296 if (len == 0) {
2297 mutex_unlock(&mfd->dma->ov_mutex);
2298 pr_err("%s: Error to get plane1\n", __func__);
2299 return -EINVAL;
2300 }
2301 pipe->srcp1_addr = start + img->offset;
2302 *pp_src_plane1_file = p_src_plane1_file;
2303 } else if (pipe->frame_format ==
2304 MDP4_FRAME_FORMAT_VIDEO_SUPERTILE) {
2305 struct tile_desc tile;
2306
2307 tile_samsung(&tile);
2308 pipe->srcp1_addr = addr + tile_mem_size(pipe, &tile);
2309 } else {
2310 pipe->srcp1_addr = addr + (pipe->src_width *
2311 pipe->src_height);
2312 }
2313 pipe->srcp0_ystride = pipe->src_width;
2314 if ((pipe->src_format == MDP_Y_CRCB_H1V1) ||
2315 (pipe->src_format == MDP_Y_CBCR_H1V1)) {
2316 if (pipe->src_width > YUV_444_MAX_WIDTH)
2317 pipe->srcp1_ystride = pipe->src_width << 2;
2318 else
2319 pipe->srcp1_ystride = pipe->src_width << 1;
2320 } else
2321 pipe->srcp1_ystride = pipe->src_width;
2322
2323 } else if (pipe->fetch_plane == OVERLAY_PLANE_PLANAR) {
2324 if (overlay_version > 0) {
2325 img = &req->plane1_data;
2326 get_img(img, info, &start, &len, &p_src_plane1_file);
2327 if (len == 0) {
2328 mutex_unlock(&mfd->dma->ov_mutex);
2329 pr_err("%s: Error to get plane1\n", __func__);
2330 return -EINVAL;
2331 }
2332 pipe->srcp1_addr = start + img->offset;
2333 *pp_src_plane1_file = p_src_plane1_file;
2334
2335 img = &req->plane2_data;
2336 get_img(img, info, &start, &len, &p_src_plane2_file);
2337 if (len == 0) {
2338 mutex_unlock(&mfd->dma->ov_mutex);
2339 pr_err("%s: Error to get plane2\n", __func__);
2340 return -EINVAL;
2341 }
2342 pipe->srcp2_addr = start + img->offset;
2343 *pp_src_plane2_file = p_src_plane2_file;
2344 } else {
2345 addr += (pipe->src_width * pipe->src_height);
2346 pipe->srcp1_addr = addr;
2347 addr += ((pipe->src_width / 2) *
2348 (pipe->src_height / 2));
2349 pipe->srcp2_addr = addr;
2350 }
Adrian Salido-Moreno33dc7b92011-08-18 16:16:12 -07002351 /* mdp planar format expects Cb in srcp1 and Cr in p2 */
2352 if (pipe->src_format == MDP_Y_CR_CB_H2V2)
2353 swap(pipe->srcp1_addr, pipe->srcp2_addr);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002354 pipe->srcp0_ystride = pipe->src_width;
2355 pipe->srcp1_ystride = pipe->src_width / 2;
2356 pipe->srcp2_ystride = pipe->src_width / 2;
2357 }
2358
2359 if (pipe->pipe_num >= OVERLAY_PIPE_VG1)
2360 mdp4_overlay_vg_setup(pipe); /* video/graphic pipe */
2361 else {
2362 if (pipe->flags & MDP_SHARPENING) {
2363 pr_warn(
2364 "%s: Sharpening/Smoothing not supported on RGB pipe\n",
2365 __func__);
2366 pipe->flags &= ~MDP_SHARPENING;
2367 }
2368 mdp4_overlay_rgb_setup(pipe); /* rgb pipe */
2369 }
2370
2371 mdp4_mixer_blend_setup(pipe);
2372 mdp4_mixer_stage_up(pipe);
2373
2374 if (pipe->mixer_num == MDP4_MIXER1) {
2375 ctrl->mixer1_played++;
2376 /* enternal interface */
2377 if (ctrl->panel_mode & MDP4_PANEL_DTV)
2378#ifdef CONFIG_FB_MSM_DTV
2379 mdp4_overlay_dtv_ov_done_push(mfd, pipe);
2380#else
2381 mdp4_overlay_reg_flush(pipe, 1);
2382#endif
2383 else if (ctrl->panel_mode & MDP4_PANEL_ATV)
2384 mdp4_overlay_reg_flush(pipe, 1);
2385 } else {
2386 /* primary interface */
2387 ctrl->mixer0_played++;
kuogee hsieh3de11f32011-07-08 14:09:11 -07002388 if (ctrl->panel_mode & MDP4_PANEL_LCDC) {
2389 mdp4_overlay_reg_flush(pipe, 1);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002390 mdp4_overlay_lcdc_vsync_push(mfd, pipe);
kuogee hsieh3de11f32011-07-08 14:09:11 -07002391 }
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002392#ifdef CONFIG_FB_MSM_MIPI_DSI
kuogee hsieh3de11f32011-07-08 14:09:11 -07002393 else if (ctrl->panel_mode & MDP4_PANEL_DSI_VIDEO) {
2394 mdp4_overlay_reg_flush(pipe, 1);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002395 mdp4_overlay_dsi_video_vsync_push(mfd, pipe);
kuogee hsieh3de11f32011-07-08 14:09:11 -07002396 }
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002397#endif
2398 else {
2399 /* mddi & mipi dsi cmd mode */
2400 if (pipe->flags & MDP_OV_PLAY_NOWAIT) {
2401 mdp4_stat.overlay_play[pipe->mixer_num]++;
2402 mutex_unlock(&mfd->dma->ov_mutex);
2403 return 0;
2404 }
2405#ifdef CONFIG_FB_MSM_MIPI_DSI
2406 if (ctrl->panel_mode & MDP4_PANEL_DSI_CMD) {
2407 mdp4_dsi_cmd_dma_busy_wait(mfd);
2408 mdp4_dsi_cmd_kickoff_video(mfd, pipe);
2409 }
2410#else
2411 if (ctrl->panel_mode & MDP4_PANEL_MDDI) {
2412 mdp4_mddi_dma_busy_wait(mfd);
2413 mdp4_mddi_kickoff_video(mfd, pipe);
2414 }
2415#endif
2416 }
2417 }
2418
2419 mdp4_stat.overlay_play[pipe->mixer_num]++;
2420
2421 mutex_unlock(&mfd->dma->ov_mutex);
2422
2423 return 0;
2424}