blob: 250b0edd736538b3e92bda9ee29cda962b931a28 [file] [log] [blame]
Nicholas Beck4862ec02008-01-23 12:50:51 +09001/*
2 * arch/sh/drivers/pci/fixups-sdk7780.c
3 *
4 * PCI fixups for the SDK7780SE03
5 *
6 * Copyright (C) 2003 Lineo uSolutions, Inc.
7 * Copyright (C) 2004 - 2006 Paul Mundt
Paul Mundta6d377b2009-04-17 20:11:44 +09008 * Copyright (C) 2006 Nobuhiro Iwamatsu
Nicholas Beck4862ec02008-01-23 12:50:51 +09009 *
10 * This file is subject to the terms and conditions of the GNU General Public
11 * License. See the file "COPYING" in the main directory of this archive
12 * for more details.
13 */
14#include <linux/pci.h>
Paul Mundta6d377b2009-04-17 20:11:44 +090015#include <linux/io.h>
Nicholas Beck4862ec02008-01-23 12:50:51 +090016#include "pci-sh4.h"
Nicholas Beck4862ec02008-01-23 12:50:51 +090017
Paul Mundta6d377b2009-04-17 20:11:44 +090018/* IDSEL [16][17][18][19][20][21][22][23][24][25][26][27][28][29][30][31] */
19static char sdk7780_irq_tab[4][16] __initdata = {
20 /* INTA */
21 { 65, 68, 67, 68, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1 },
22 /* INTB */
23 { 66, 65, -1, 65, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1 },
24 /* INTC */
25 { 67, 66, -1, 66, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1 },
26 /* INTD */
27 { 68, 67, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1 },
28};
29
30int __init pcibios_map_platform_irq(struct pci_dev *pdev, u8 slot, u8 pin)
31{
32 return sdk7780_irq_tab[pin-1][slot];
33}
Magnus Dammb8b47bf2009-03-11 15:41:51 +090034int pci_fixup_pcic(struct pci_channel *chan)
Nicholas Beck4862ec02008-01-23 12:50:51 +090035{
Nicholas Beck4862ec02008-01-23 12:50:51 +090036 /* Enable all interrupts, so we know what to fix */
Magnus Dammb8b47bf2009-03-11 15:41:51 +090037 pci_write_reg(chan, 0x0000C3FF, SH7780_PCIIMR);
Nicholas Beck4862ec02008-01-23 12:50:51 +090038
39 /* Set up standard PCI config registers */
Magnus Dammb8b47bf2009-03-11 15:41:51 +090040 pci_write_reg(chan, 0x08000000, SH7780_PCIMBAR0); /* PCI */
Paul Mundt62c7ae82009-04-17 20:37:16 +090041 pci_write_reg(chan, 0x08000000, SH4_PCILAR0); /* SHwy */
42 pci_write_reg(chan, 0x07F00001, SH4_PCILSR0); /* size 128M w/ MBAR */
Nicholas Beck4862ec02008-01-23 12:50:51 +090043
Magnus Dammb8b47bf2009-03-11 15:41:51 +090044 pci_write_reg(chan, 0x00000000, SH7780_PCIMBAR1);
Paul Mundt62c7ae82009-04-17 20:37:16 +090045 pci_write_reg(chan, 0x00000000, SH4_PCILAR1);
46 pci_write_reg(chan, 0x00000000, SH4_PCILSR1);
Nicholas Beck4862ec02008-01-23 12:50:51 +090047
Magnus Dammb8b47bf2009-03-11 15:41:51 +090048 pci_write_reg(chan, 0xAB000801, SH7780_PCIIBAR);
Paul Mundt62c7ae82009-04-17 20:37:16 +090049 pci_write_reg(chan, 0xA5000C01, SH4_PCICR);
Nicholas Beck4862ec02008-01-23 12:50:51 +090050
51 return 0;
52}