blob: bec02131a6a0a35e1638ab41b308dae5413ebcda [file] [log] [blame]
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001/* Copyright (c) 2009-2011, Code Aurora Forum. All rights reserved.
Daniel Walker8d747cd2010-02-25 11:37:43 -08002 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 *
Daniel Walker8d747cd2010-02-25 11:37:43 -080012 */
13
14#include <linux/kernel.h>
15#include <linux/irq.h>
16#include <linux/gpio.h>
17#include <linux/platform_device.h>
18#include <linux/delay.h>
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070019#include <linux/bootmem.h>
Daniel Walker8d747cd2010-02-25 11:37:43 -080020#include <linux/io.h>
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070021#ifdef CONFIG_SPI_QSD
22#include <linux/spi/spi.h>
23#endif
24#include <linux/mfd/pmic8058.h>
25#include <linux/mfd/marimba.h>
26#include <linux/i2c.h>
27#include <linux/input.h>
Daniel Walker8d747cd2010-02-25 11:37:43 -080028#include <linux/smsc911x.h>
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070029#include <linux/ofn_atlab.h>
30#include <linux/power_supply.h>
31#include <linux/input/pmic8058-keypad.h>
32#include <linux/i2c/isa1200.h>
33#include <linux/pwm.h>
34#include <linux/pmic8058-pwm.h>
35#include <linux/i2c/tsc2007.h>
36#include <linux/input/kp_flip_switch.h>
37#include <linux/leds-pmic8058.h>
38#include <linux/input/cy8c_ts.h>
39#include <linux/msm_adc.h>
40#include <linux/dma-mapping.h>
Daniel Walker8d747cd2010-02-25 11:37:43 -080041
42#include <asm/mach-types.h>
43#include <asm/mach/arch.h>
44#include <asm/setup.h>
45
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070046#include <mach/mpp.h>
Daniel Walker8d747cd2010-02-25 11:37:43 -080047#include <mach/board.h>
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070048#include <mach/camera.h>
49#include <mach/memory.h>
Daniel Walker8d747cd2010-02-25 11:37:43 -080050#include <mach/msm_iomap.h>
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070051#include <mach/msm_hsusb.h>
52#include <mach/rpc_hsusb.h>
53#include <mach/msm_spi.h>
54#include <mach/qdsp5v2/msm_lpa.h>
Daniel Walker8d747cd2010-02-25 11:37:43 -080055#include <mach/dma.h>
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070056#include <linux/android_pmem.h>
57#include <linux/input/msm_ts.h>
58#include <mach/pmic.h>
59#include <mach/rpc_pmapp.h>
60#include <mach/qdsp5v2/aux_pcm.h>
61#include <mach/qdsp5v2/mi2s.h>
62#include <mach/qdsp5v2/audio_dev_ctl.h>
63#include <mach/msm_battery.h>
64#include <mach/rpc_server_handset.h>
65#include <mach/msm_tsif.h>
66#include <mach/socinfo.h>
67#include <mach/msm_memtypes.h>
68#include <linux/cyttsp.h>
Daniel Walker8d747cd2010-02-25 11:37:43 -080069
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070070#include <asm/mach/mmc.h>
71#include <asm/mach/flash.h>
Daniel Walker8d747cd2010-02-25 11:37:43 -080072#include <mach/vreg.h>
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070073#include <linux/platform_data/qcom_crypto_device.h>
74
Daniel Walker8d747cd2010-02-25 11:37:43 -080075#include "devices.h"
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070076#include "timer.h"
77#ifdef CONFIG_USB_G_ANDROID
78#include <linux/usb/android.h>
79#include <mach/usbdiag.h>
80#endif
81#include "pm.h"
82#include "spm.h"
83#include <mach/dal_axi.h>
84#include <mach/msm_serial_hs.h>
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070085#include <mach/qdsp5v2/mi2s.h>
86#include <mach/qdsp5v2/audio_dev_ctl.h>
87#include <mach/sdio_al.h>
88#include "smd_private.h"
89#include <linux/bma150.h>
Daniel Walker8d747cd2010-02-25 11:37:43 -080090
Justin Paupore637a25d2011-07-14 17:11:04 -070091#include "board-msm7x30-regulator.h"
92
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070093#define MSM_PMEM_SF_SIZE 0x1700000
94#ifdef CONFIG_FB_MSM_TRIPLE_BUFFER
95#define MSM_FB_SIZE 0x780000
96#else
97#define MSM_FB_SIZE 0x500000
98#endif
99#define MSM_PMEM_ADSP_SIZE 0x1E00000
100#define MSM_FLUID_PMEM_ADSP_SIZE 0x2800000
101#define PMEM_KERNEL_EBI0_SIZE 0x600000
102#define MSM_PMEM_AUDIO_SIZE 0x200000
Daniel Walker90e37c52010-05-12 14:24:15 -0700103
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700104#define PMIC_GPIO_INT 27
105#define PMIC_VREG_WLAN_LEVEL 2900
106#define PMIC_GPIO_SD_DET 36
107#define PMIC_GPIO_SDC4_EN_N 17 /* PMIC GPIO Number 18 */
108#define PMIC_GPIO_HDMI_5V_EN_V3 32 /* PMIC GPIO for V3 H/W */
109#define PMIC_GPIO_HDMI_5V_EN_V2 39 /* PMIC GPIO for V2 H/W */
110
111#define ADV7520_I2C_ADDR 0x39
112
113#define FPGA_SDCC_STATUS 0x8E0001A8
114
115#define FPGA_OPTNAV_GPIO_ADDR 0x8E000026
116#define OPTNAV_I2C_SLAVE_ADDR (0xB0 >> 1)
117#define OPTNAV_IRQ 20
118#define OPTNAV_CHIP_SELECT 19
119
120/* Macros assume PMIC GPIOs start at 0 */
121#define PM8058_GPIO_PM_TO_SYS(pm_gpio) (pm_gpio + NR_GPIO_IRQS)
122#define PM8058_GPIO_SYS_TO_PM(sys_gpio) (sys_gpio - NR_GPIO_IRQS)
123
124#define PMIC_GPIO_FLASH_BOOST_ENABLE 15 /* PMIC GPIO Number 16 */
125#define PMIC_GPIO_HAP_ENABLE 16 /* PMIC GPIO Number 17 */
126
127#define PMIC_GPIO_WLAN_EXT_POR 22 /* PMIC GPIO NUMBER 23 */
128
129#define BMA150_GPIO_INT 1
130
131#define HAP_LVL_SHFT_MSM_GPIO 24
132
133#define PMIC_GPIO_QUICKVX_CLK 37 /* PMIC GPIO 38 */
134
135#define PM_FLIP_MPP 5 /* PMIC MPP 06 */
136static int pm8058_gpios_init(void)
137{
138 int rc;
139 int pmic_gpio_hdmi_5v_en;
140
141#ifdef CONFIG_MMC_MSM_CARD_HW_DETECTION
142 struct pm8058_gpio sdcc_det = {
143 .direction = PM_GPIO_DIR_IN,
144 .pull = PM_GPIO_PULL_UP_1P5,
145 .vin_sel = 2,
146 .function = PM_GPIO_FUNC_NORMAL,
147 .inv_int_pol = 0,
148 };
149#endif
150 struct pm8058_gpio sdc4_en = {
151 .direction = PM_GPIO_DIR_OUT,
152 .pull = PM_GPIO_PULL_NO,
153 .vin_sel = PM_GPIO_VIN_L5,
154 .function = PM_GPIO_FUNC_NORMAL,
155 .inv_int_pol = 0,
156 .out_strength = PM_GPIO_STRENGTH_LOW,
157 .output_value = 0,
158 };
159
160 struct pm8058_gpio haptics_enable = {
161 .direction = PM_GPIO_DIR_OUT,
162 .pull = PM_GPIO_PULL_NO,
163 .out_strength = PM_GPIO_STRENGTH_HIGH,
164 .function = PM_GPIO_FUNC_NORMAL,
165 .inv_int_pol = 0,
166 .vin_sel = 2,
167 .output_buffer = PM_GPIO_OUT_BUF_CMOS,
168 .output_value = 0,
169 };
170
171 struct pm8058_gpio hdmi_5V_en = {
172 .direction = PM_GPIO_DIR_OUT,
173 .pull = PM_GPIO_PULL_NO,
174 .vin_sel = PM_GPIO_VIN_VPH,
175 .function = PM_GPIO_FUNC_NORMAL,
176 .out_strength = PM_GPIO_STRENGTH_LOW,
177 .output_value = 0,
178 };
179
180 struct pm8058_gpio flash_boost_enable = {
181 .direction = PM_GPIO_DIR_OUT,
182 .output_buffer = PM_GPIO_OUT_BUF_CMOS,
183 .output_value = 0,
184 .pull = PM_GPIO_PULL_NO,
185 .vin_sel = PM_GPIO_VIN_S3,
186 .out_strength = PM_GPIO_STRENGTH_HIGH,
187 .function = PM_GPIO_FUNC_2,
188 };
189
190 struct pm8058_gpio gpio23 = {
191 .direction = PM_GPIO_DIR_OUT,
192 .output_buffer = PM_GPIO_OUT_BUF_CMOS,
193 .output_value = 0,
194 .pull = PM_GPIO_PULL_NO,
195 .vin_sel = 2,
196 .out_strength = PM_GPIO_STRENGTH_LOW,
197 .function = PM_GPIO_FUNC_NORMAL,
198 };
199
200
201 if (machine_is_msm8x55_svlte_surf() || machine_is_msm8x55_svlte_ffa() ||
202 machine_is_msm7x30_fluid())
203 pmic_gpio_hdmi_5v_en = PMIC_GPIO_HDMI_5V_EN_V2 ;
204 else
205 pmic_gpio_hdmi_5v_en = PMIC_GPIO_HDMI_5V_EN_V3 ;
206
207 if (machine_is_msm7x30_fluid()) {
208 rc = pm8058_gpio_config(PMIC_GPIO_HAP_ENABLE, &haptics_enable);
209 if (rc) {
210 pr_err("%s: PMIC GPIO %d write failed\n", __func__,
211 (PMIC_GPIO_HAP_ENABLE + 1));
212 return rc;
213 }
214 rc = pm8058_gpio_config(PMIC_GPIO_FLASH_BOOST_ENABLE,
215 &flash_boost_enable);
216 if (rc) {
217 pr_err("%s: PMIC GPIO %d write failed\n", __func__,
218 (PMIC_GPIO_FLASH_BOOST_ENABLE + 1));
219 return rc;
220 }
221 }
222
223#ifdef CONFIG_MMC_MSM_CARD_HW_DETECTION
224 if (machine_is_msm7x30_fluid())
225 sdcc_det.inv_int_pol = 1;
226
227 rc = pm8058_gpio_config(PMIC_GPIO_SD_DET - 1, &sdcc_det);
228 if (rc) {
229 pr_err("%s PMIC_GPIO_SD_DET config failed\n", __func__);
230 return rc;
231 }
232#endif
233
234 rc = pm8058_gpio_config(pmic_gpio_hdmi_5v_en, &hdmi_5V_en);
235 if (rc) {
236 pr_err("%s PMIC_GPIO_HDMI_5V_EN config failed\n", __func__);
237 return rc;
238 }
239
240 /* Deassert GPIO#23 (source for Ext_POR on WLAN-Volans) */
241 rc = pm8058_gpio_config(PMIC_GPIO_WLAN_EXT_POR, &gpio23);
242 if (rc) {
243 pr_err("%s PMIC_GPIO_WLAN_EXT_POR config failed\n", __func__);
244 return rc;
245 }
246
247 if (machine_is_msm7x30_fluid()) {
248 rc = pm8058_gpio_config(PMIC_GPIO_SDC4_EN_N, &sdc4_en);
249 if (rc) {
250 pr_err("%s PMIC_GPIO_SDC4_EN_N config failed\n",
251 __func__);
252 return rc;
253 }
254 rc = gpio_request(PM8058_GPIO_PM_TO_SYS(PMIC_GPIO_SDC4_EN_N),
255 "sdc4_en");
256 if (rc) {
257 pr_err("%s PMIC_GPIO_SDC4_EN_N gpio_request failed\n",
258 __func__);
259 return rc;
260 }
261 gpio_set_value_cansleep(
262 PM8058_GPIO_PM_TO_SYS(PMIC_GPIO_SDC4_EN_N), 0);
263 }
264
265 return 0;
266}
267
Justin Paupore637a25d2011-07-14 17:11:04 -0700268/* Regulator API support */
269
270#ifdef CONFIG_MSM_PROC_COMM_REGULATOR
271static struct platform_device msm_proccomm_regulator_dev = {
272 .name = PROCCOMM_REGULATOR_DEV_NAME,
273 .id = -1,
274 .dev = {
275 .platform_data = &msm7x30_proccomm_regulator_data
276 }
277};
278#endif
279
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700280/*virtual key support */
281static ssize_t tma300_vkeys_show(struct kobject *kobj,
282 struct kobj_attribute *attr, char *buf)
283{
284 return sprintf(buf,
285 __stringify(EV_KEY) ":" __stringify(KEY_BACK) ":50:842:80:100"
286 ":" __stringify(EV_KEY) ":" __stringify(KEY_MENU) ":170:842:80:100"
287 ":" __stringify(EV_KEY) ":" __stringify(KEY_HOME) ":290:842:80:100"
288 ":" __stringify(EV_KEY) ":" __stringify(KEY_SEARCH) ":410:842:80:100"
289 "\n");
290}
291
292static struct kobj_attribute tma300_vkeys_attr = {
293 .attr = {
294 .mode = S_IRUGO,
295 },
296 .show = &tma300_vkeys_show,
Pavankumar Kondeti5155e2c2010-12-08 13:37:08 +0530297};
298
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700299static struct attribute *tma300_properties_attrs[] = {
300 &tma300_vkeys_attr.attr,
301 NULL
Pavankumar Kondeti5155e2c2010-12-08 13:37:08 +0530302};
303
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700304static struct attribute_group tma300_properties_attr_group = {
305 .attrs = tma300_properties_attrs,
306};
307
308static struct kobject *properties_kobj;
309
310#define CYTTSP_TS_GPIO_IRQ 150
311static int cyttsp_platform_init(struct i2c_client *client)
312{
313 int rc = -EINVAL;
314 struct vreg *vreg_ldo8, *vreg_ldo15;
315
316 vreg_ldo8 = vreg_get(NULL, "gp7");
317
318 if (!vreg_ldo8) {
319 pr_err("%s: VREG L8 get failed\n", __func__);
320 return rc;
321 }
322
323 rc = vreg_set_level(vreg_ldo8, 1800);
324 if (rc) {
325 pr_err("%s: VREG L8 set failed\n", __func__);
326 goto l8_put;
327 }
328
329 rc = vreg_enable(vreg_ldo8);
330 if (rc) {
331 pr_err("%s: VREG L8 enable failed\n", __func__);
332 goto l8_put;
333 }
334
335 vreg_ldo15 = vreg_get(NULL, "gp6");
336
337 if (!vreg_ldo15) {
338 pr_err("%s: VREG L15 get failed\n", __func__);
339 goto l8_disable;
340 }
341
342 rc = vreg_set_level(vreg_ldo15, 3050);
343 if (rc) {
344 pr_err("%s: VREG L15 set failed\n", __func__);
345 goto l8_disable;
346 }
347
348 rc = vreg_enable(vreg_ldo15);
349 if (rc) {
350 pr_err("%s: VREG L15 enable failed\n", __func__);
351 goto l8_disable;
352 }
353
354 /* check this device active by reading first byte/register */
355 rc = i2c_smbus_read_byte_data(client, 0x01);
356 if (rc < 0) {
357 pr_err("%s: i2c sanity check failed\n", __func__);
358 goto l8_disable;
359 }
360
361 rc = gpio_tlmm_config(GPIO_CFG(CYTTSP_TS_GPIO_IRQ, 0, GPIO_CFG_INPUT,
362 GPIO_CFG_PULL_UP, GPIO_CFG_6MA), GPIO_CFG_ENABLE);
363 if (rc) {
364 pr_err("%s: Could not configure gpio %d\n",
365 __func__, CYTTSP_TS_GPIO_IRQ);
366 goto l8_disable;
367 }
368
369 /* virtual keys */
370 tma300_vkeys_attr.attr.name = "virtualkeys.cyttsp-i2c";
371 properties_kobj = kobject_create_and_add("board_properties",
372 NULL);
373 if (properties_kobj)
374 rc = sysfs_create_group(properties_kobj,
375 &tma300_properties_attr_group);
376 if (!properties_kobj || rc)
377 pr_err("%s: failed to create board_properties\n",
378 __func__);
379
380 return CY_OK;
381
382l8_disable:
383 vreg_disable(vreg_ldo8);
384l8_put:
385 vreg_put(vreg_ldo8);
386 return rc;
387}
388
389static int cyttsp_platform_resume(struct i2c_client *client)
390{
391 /* add any special code to strobe a wakeup pin or chip reset */
392 mdelay(10);
393
394 return CY_OK;
395}
396
397static struct cyttsp_platform_data cyttsp_data = {
398 .fw_fname = "cyttsp_7630_fluid.hex",
399 .panel_maxx = 479,
400 .panel_maxy = 799,
401 .disp_maxx = 469,
402 .disp_maxy = 799,
403 .disp_minx = 10,
404 .disp_miny = 0,
405 .flags = 0,
406 .gen = CY_GEN3, /* or */
407 .use_st = CY_USE_ST,
408 .use_mt = CY_USE_MT,
409 .use_hndshk = CY_SEND_HNDSHK,
410 .use_trk_id = CY_USE_TRACKING_ID,
Anirudh Ghayal15187772011-06-22 17:39:41 +0530411 .use_sleep = CY_USE_DEEP_SLEEP_SEL | CY_USE_LOW_POWER_SEL,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700412 .use_gestures = CY_USE_GESTURES,
413 /* activate up to 4 groups
414 * and set active distance
415 */
416 .gest_set = CY_GEST_GRP1 | CY_GEST_GRP2 |
417 CY_GEST_GRP3 | CY_GEST_GRP4 |
418 CY_ACT_DIST,
419 /* change act_intrvl to customize the Active power state
420 * scanning/processing refresh interval for Operating mode
421 */
422 .act_intrvl = CY_ACT_INTRVL_DFLT,
423 /* change tch_tmout to customize the touch timeout for the
424 * Active power state for Operating mode
425 */
426 .tch_tmout = CY_TCH_TMOUT_DFLT,
427 /* change lp_intrvl to customize the Low Power power state
428 * scanning/processing refresh interval for Operating mode
429 */
430 .lp_intrvl = CY_LP_INTRVL_DFLT,
431 .resume = cyttsp_platform_resume,
432 .init = cyttsp_platform_init,
433 .sleep_gpio = -1,
434 .resout_gpio = -1,
435 .irq_gpio = CYTTSP_TS_GPIO_IRQ,
Mohan Pallaka49c37d62011-08-01 11:52:00 +0530436 .correct_fw_ver = 2,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700437};
438
439static int pm8058_pwm_config(struct pwm_device *pwm, int ch, int on)
440{
441 struct pm8058_gpio pwm_gpio_config = {
442 .direction = PM_GPIO_DIR_OUT,
443 .output_buffer = PM_GPIO_OUT_BUF_CMOS,
444 .output_value = 0,
445 .pull = PM_GPIO_PULL_NO,
446 .vin_sel = PM_GPIO_VIN_S3,
447 .out_strength = PM_GPIO_STRENGTH_HIGH,
448 .function = PM_GPIO_FUNC_2,
449 };
450 int rc = -EINVAL;
451 int id, mode, max_mA;
452
453 id = mode = max_mA = 0;
454 switch (ch) {
455 case 0:
456 case 1:
457 case 2:
458 if (on) {
459 id = 24 + ch;
460 rc = pm8058_gpio_config(id - 1, &pwm_gpio_config);
461 if (rc)
462 pr_err("%s: pm8058_gpio_config(%d): rc=%d\n",
463 __func__, id, rc);
464 }
465 break;
466
467 case 3:
468 id = PM_PWM_LED_KPD;
469 mode = PM_PWM_CONF_DTEST3;
470 max_mA = 200;
471 break;
472
473 case 4:
474 id = PM_PWM_LED_0;
475 mode = PM_PWM_CONF_PWM1;
476 max_mA = 40;
477 break;
478
479 case 5:
480 id = PM_PWM_LED_2;
481 mode = PM_PWM_CONF_PWM2;
482 max_mA = 40;
483 break;
484
485 case 6:
486 id = PM_PWM_LED_FLASH;
487 mode = PM_PWM_CONF_DTEST3;
488 max_mA = 200;
489 break;
490
491 default:
492 break;
493 }
494
495 if (ch >= 3 && ch <= 6) {
496 if (!on) {
497 mode = PM_PWM_CONF_NONE;
498 max_mA = 0;
499 }
500 rc = pm8058_pwm_config_led(pwm, id, mode, max_mA);
501 if (rc)
502 pr_err("%s: pm8058_pwm_config_led(ch=%d): rc=%d\n",
503 __func__, ch, rc);
504 }
505
506 return rc;
507}
508
509static int pm8058_pwm_enable(struct pwm_device *pwm, int ch, int on)
510{
511 int rc;
512
513 switch (ch) {
514 case 7:
515 rc = pm8058_pwm_set_dtest(pwm, on);
516 if (rc)
517 pr_err("%s: pwm_set_dtest(%d): rc=%d\n",
518 __func__, on, rc);
519 break;
520 default:
521 rc = -EINVAL;
522 break;
523 }
524 return rc;
525}
526
527static const unsigned int fluid_keymap[] = {
528 KEY(0, 0, KEY_7),
529 KEY(0, 1, KEY_ENTER),
530 KEY(0, 2, KEY_UP),
531 /* drop (0,3) as it always shows up in pair with(0,2) */
532 KEY(0, 4, KEY_DOWN),
533
534 KEY(1, 0, KEY_CAMERA_SNAPSHOT),
535 KEY(1, 1, KEY_SELECT),
536 KEY(1, 2, KEY_1),
537 KEY(1, 3, KEY_VOLUMEUP),
538 KEY(1, 4, KEY_VOLUMEDOWN),
539};
540
541static const unsigned int surf_keymap[] = {
542 KEY(0, 0, KEY_7),
543 KEY(0, 1, KEY_DOWN),
544 KEY(0, 2, KEY_UP),
545 KEY(0, 3, KEY_RIGHT),
546 KEY(0, 4, KEY_ENTER),
547 KEY(0, 5, KEY_L),
548 KEY(0, 6, KEY_BACK),
549 KEY(0, 7, KEY_M),
550
551 KEY(1, 0, KEY_LEFT),
552 KEY(1, 1, KEY_SEND),
553 KEY(1, 2, KEY_1),
554 KEY(1, 3, KEY_4),
555 KEY(1, 4, KEY_CLEAR),
556 KEY(1, 5, KEY_MSDOS),
557 KEY(1, 6, KEY_SPACE),
558 KEY(1, 7, KEY_COMMA),
559
560 KEY(2, 0, KEY_6),
561 KEY(2, 1, KEY_5),
562 KEY(2, 2, KEY_8),
563 KEY(2, 3, KEY_3),
564 KEY(2, 4, KEY_NUMERIC_STAR),
565 KEY(2, 5, KEY_UP),
566 KEY(2, 6, KEY_DOWN), /* SYN */
567 KEY(2, 7, KEY_LEFTSHIFT),
568
569 KEY(3, 0, KEY_9),
570 KEY(3, 1, KEY_NUMERIC_POUND),
571 KEY(3, 2, KEY_0),
572 KEY(3, 3, KEY_2),
573 KEY(3, 4, KEY_SLEEP),
574 KEY(3, 5, KEY_F1),
575 KEY(3, 6, KEY_F2),
576 KEY(3, 7, KEY_F3),
577
578 KEY(4, 0, KEY_BACK),
579 KEY(4, 1, KEY_HOME),
580 KEY(4, 2, KEY_MENU),
581 KEY(4, 3, KEY_VOLUMEUP),
582 KEY(4, 4, KEY_VOLUMEDOWN),
583 KEY(4, 5, KEY_F4),
584 KEY(4, 6, KEY_F5),
585 KEY(4, 7, KEY_F6),
586
587 KEY(5, 0, KEY_R),
588 KEY(5, 1, KEY_T),
589 KEY(5, 2, KEY_Y),
590 KEY(5, 3, KEY_LEFTALT),
591 KEY(5, 4, KEY_KPENTER),
592 KEY(5, 5, KEY_Q),
593 KEY(5, 6, KEY_W),
594 KEY(5, 7, KEY_E),
595
596 KEY(6, 0, KEY_F),
597 KEY(6, 1, KEY_G),
598 KEY(6, 2, KEY_H),
599 KEY(6, 3, KEY_CAPSLOCK),
600 KEY(6, 4, KEY_PAGEUP),
601 KEY(6, 5, KEY_A),
602 KEY(6, 6, KEY_S),
603 KEY(6, 7, KEY_D),
604
605 KEY(7, 0, KEY_V),
606 KEY(7, 1, KEY_B),
607 KEY(7, 2, KEY_N),
608 KEY(7, 3, KEY_MENU), /* REVISIT - SYM */
609 KEY(7, 4, KEY_PAGEDOWN),
610 KEY(7, 5, KEY_Z),
611 KEY(7, 6, KEY_X),
612 KEY(7, 7, KEY_C),
613
614 KEY(8, 0, KEY_P),
615 KEY(8, 1, KEY_J),
616 KEY(8, 2, KEY_K),
617 KEY(8, 3, KEY_INSERT),
618 KEY(8, 4, KEY_LINEFEED),
619 KEY(8, 5, KEY_U),
620 KEY(8, 6, KEY_I),
621 KEY(8, 7, KEY_O),
622
623 KEY(9, 0, KEY_4),
624 KEY(9, 1, KEY_5),
625 KEY(9, 2, KEY_6),
626 KEY(9, 3, KEY_7),
627 KEY(9, 4, KEY_8),
628 KEY(9, 5, KEY_1),
629 KEY(9, 6, KEY_2),
630 KEY(9, 7, KEY_3),
631
632 KEY(10, 0, KEY_F7),
633 KEY(10, 1, KEY_F8),
634 KEY(10, 2, KEY_F9),
635 KEY(10, 3, KEY_F10),
636 KEY(10, 4, KEY_FN),
637 KEY(10, 5, KEY_9),
638 KEY(10, 6, KEY_0),
639 KEY(10, 7, KEY_DOT),
640
641 KEY(11, 0, KEY_LEFTCTRL),
642 KEY(11, 1, KEY_F11), /* START */
643 KEY(11, 2, KEY_ENTER),
644 KEY(11, 3, KEY_SEARCH),
645 KEY(11, 4, KEY_DELETE),
646 KEY(11, 5, KEY_RIGHT),
647 KEY(11, 6, KEY_LEFT),
648 KEY(11, 7, KEY_RIGHTSHIFT),
649};
650
651static struct resource resources_keypad[] = {
652 {
653 .start = PM8058_KEYPAD_IRQ(PMIC8058_IRQ_BASE),
654 .end = PM8058_KEYPAD_IRQ(PMIC8058_IRQ_BASE),
655 .flags = IORESOURCE_IRQ,
Dima Zavinba5499e2011-01-10 11:00:30 -0800656 },
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700657 {
658 .start = PM8058_KEYSTUCK_IRQ(PMIC8058_IRQ_BASE),
659 .end = PM8058_KEYSTUCK_IRQ(PMIC8058_IRQ_BASE),
660 .flags = IORESOURCE_IRQ,
Dima Zavinba5499e2011-01-10 11:00:30 -0800661 },
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700662};
663
664static struct matrix_keymap_data surf_keymap_data = {
665 .keymap_size = ARRAY_SIZE(surf_keymap),
666 .keymap = surf_keymap,
667};
668
669
670static struct pmic8058_keypad_data surf_keypad_data = {
671 .input_name = "surf_keypad",
672 .input_phys_device = "surf_keypad/input0",
673 .num_rows = 12,
674 .num_cols = 8,
675 .rows_gpio_start = 8,
676 .cols_gpio_start = 0,
677 .debounce_ms = {8, 10},
678 .scan_delay_ms = 32,
679 .row_hold_ns = 91500,
680 .wakeup = 1,
681 .keymap_data = &surf_keymap_data,
682};
683
684static struct matrix_keymap_data fluid_keymap_data = {
685 .keymap_size = ARRAY_SIZE(fluid_keymap),
686 .keymap = fluid_keymap,
687};
688
689
690
691static struct pmic8058_keypad_data fluid_keypad_data = {
692 .input_name = "fluid-keypad",
693 .input_phys_device = "fluid-keypad/input0",
694 .num_rows = 5,
695 .num_cols = 5,
696 .rows_gpio_start = 8,
697 .cols_gpio_start = 0,
698 .debounce_ms = {8, 10},
699 .scan_delay_ms = 32,
700 .row_hold_ns = 91500,
701 .wakeup = 1,
702 .keymap_data = &fluid_keymap_data,
703};
704
705static struct pm8058_pwm_pdata pm8058_pwm_data = {
706 .config = pm8058_pwm_config,
707 .enable = pm8058_pwm_enable,
708};
709
710/* Put sub devices with fixed location first in sub_devices array */
711#define PM8058_SUBDEV_KPD 0
712#define PM8058_SUBDEV_LED 1
713
714static struct pm8058_gpio_platform_data pm8058_gpio_data = {
715 .gpio_base = PM8058_GPIO_PM_TO_SYS(0),
716 .irq_base = PM8058_GPIO_IRQ(PMIC8058_IRQ_BASE, 0),
717 .init = pm8058_gpios_init,
718};
719
720static struct pm8058_gpio_platform_data pm8058_mpp_data = {
721 .gpio_base = PM8058_GPIO_PM_TO_SYS(PM8058_GPIOS),
722 .irq_base = PM8058_MPP_IRQ(PMIC8058_IRQ_BASE, 0),
723};
724
725static struct pmic8058_led pmic8058_ffa_leds[] = {
726 [0] = {
727 .name = "keyboard-backlight",
728 .max_brightness = 15,
729 .id = PMIC8058_ID_LED_KB_LIGHT,
Dima Zavinba5499e2011-01-10 11:00:30 -0800730 },
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700731};
732
733static struct pmic8058_leds_platform_data pm8058_ffa_leds_data = {
734 .num_leds = ARRAY_SIZE(pmic8058_ffa_leds),
735 .leds = pmic8058_ffa_leds,
736};
737
738static struct pmic8058_led pmic8058_surf_leds[] = {
739 [0] = {
740 .name = "keyboard-backlight",
741 .max_brightness = 15,
742 .id = PMIC8058_ID_LED_KB_LIGHT,
743 },
744 [1] = {
745 .name = "voice:red",
746 .max_brightness = 20,
747 .id = PMIC8058_ID_LED_0,
748 },
749 [2] = {
750 .name = "wlan:green",
751 .max_brightness = 20,
752 .id = PMIC8058_ID_LED_2,
753 },
754};
755
756static struct mfd_cell pm8058_subdevs[] = {
757 { .name = "pm8058-keypad",
758 .id = -1,
759 .num_resources = ARRAY_SIZE(resources_keypad),
760 .resources = resources_keypad,
761 },
762 { .name = "pm8058-led",
763 .id = -1,
764 },
765 { .name = "pm8058-gpio",
766 .id = -1,
767 .platform_data = &pm8058_gpio_data,
768 .pdata_size = sizeof(pm8058_gpio_data),
769 },
770 { .name = "pm8058-mpp",
771 .id = -1,
772 .platform_data = &pm8058_mpp_data,
773 .pdata_size = sizeof(pm8058_mpp_data),
774 },
775 { .name = "pm8058-pwm",
776 .id = -1,
777 .platform_data = &pm8058_pwm_data,
778 .pdata_size = sizeof(pm8058_pwm_data),
779 },
780 { .name = "pm8058-nfc",
781 .id = -1,
782 },
783 { .name = "pm8058-upl",
784 .id = -1,
785 },
786};
787
788static struct pmic8058_leds_platform_data pm8058_surf_leds_data = {
789 .num_leds = ARRAY_SIZE(pmic8058_surf_leds),
790 .leds = pmic8058_surf_leds,
791};
792
793static struct pmic8058_led pmic8058_fluid_leds[] = {
794 [0] = {
795 .name = "keyboard-backlight",
796 .max_brightness = 15,
797 .id = PMIC8058_ID_LED_KB_LIGHT,
798 },
799 [1] = {
800 .name = "flash:led_0",
801 .max_brightness = 15,
802 .id = PMIC8058_ID_FLASH_LED_0,
803 },
804 [2] = {
805 .name = "flash:led_1",
806 .max_brightness = 15,
807 .id = PMIC8058_ID_FLASH_LED_1,
808 },
809};
810
811static struct pmic8058_leds_platform_data pm8058_fluid_leds_data = {
812 .num_leds = ARRAY_SIZE(pmic8058_fluid_leds),
813 .leds = pmic8058_fluid_leds,
814};
815
816static struct pm8058_platform_data pm8058_7x30_data = {
817 .irq_base = PMIC8058_IRQ_BASE,
818
819 .num_subdevs = ARRAY_SIZE(pm8058_subdevs),
820 .sub_devices = pm8058_subdevs,
821 .irq_trigger_flags = IRQF_TRIGGER_LOW,
822};
823
824static struct i2c_board_info pm8058_boardinfo[] __initdata = {
825 {
826 I2C_BOARD_INFO("pm8058-core", 0x55),
827 .irq = MSM_GPIO_TO_INT(PMIC_GPIO_INT),
828 .platform_data = &pm8058_7x30_data,
829 },
830};
831
832static struct i2c_board_info cy8info[] __initdata = {
833 {
834 I2C_BOARD_INFO(CY_I2C_NAME, 0x24),
835 .platform_data = &cyttsp_data,
836#ifndef CY_USE_TIMER
837 .irq = MSM_GPIO_TO_INT(CYTTSP_TS_GPIO_IRQ),
838#endif /* CY_USE_TIMER */
839 },
840};
841
842static struct i2c_board_info msm_camera_boardinfo[] __initdata = {
843#ifdef CONFIG_MT9D112
844 {
845 I2C_BOARD_INFO("mt9d112", 0x78 >> 1),
Dima Zavinba5499e2011-01-10 11:00:30 -0800846 },
847#endif
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700848#ifdef CONFIG_WEBCAM_OV9726
849 {
850 I2C_BOARD_INFO("ov9726", 0x10),
851 },
852#endif
853#ifdef CONFIG_S5K3E2FX
854 {
855 I2C_BOARD_INFO("s5k3e2fx", 0x20 >> 1),
856 },
857#endif
858#ifdef CONFIG_MT9P012
859 {
860 I2C_BOARD_INFO("mt9p012", 0x6C >> 1),
861 },
862#endif
863#ifdef CONFIG_VX6953
864 {
865 I2C_BOARD_INFO("vx6953", 0x20),
866 },
867#endif
868#ifdef CONFIG_MT9E013
869 {
870 I2C_BOARD_INFO("mt9e013", 0x6C >> 2),
871 },
872#endif
873#ifdef CONFIG_SN12M0PZ
874 {
875 I2C_BOARD_INFO("sn12m0pz", 0x34 >> 1),
876 },
877#endif
878#if defined(CONFIG_MT9T013) || defined(CONFIG_SENSORS_MT9T013)
879 {
880 I2C_BOARD_INFO("mt9t013", 0x6C),
881 },
882#endif
883
Dima Zavinba5499e2011-01-10 11:00:30 -0800884};
885
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700886#ifdef CONFIG_MSM_CAMERA
887#define CAM_STNDBY 143
888static uint32_t camera_off_vcm_gpio_table[] = {
889GPIO_CFG(1, 0, GPIO_CFG_OUTPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA), /* VCM */
890};
891
892static uint32_t camera_off_gpio_table[] = {
893 /* parallel CAMERA interfaces */
894 GPIO_CFG(0, 0, GPIO_CFG_OUTPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA), /* RST */
895 GPIO_CFG(2, 0, GPIO_CFG_INPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA), /* DAT2 */
896 GPIO_CFG(3, 0, GPIO_CFG_INPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA), /* DAT3 */
897 GPIO_CFG(4, 0, GPIO_CFG_INPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA), /* DAT4 */
898 GPIO_CFG(5, 0, GPIO_CFG_INPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA), /* DAT5 */
899 GPIO_CFG(6, 0, GPIO_CFG_INPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA), /* DAT6 */
900 GPIO_CFG(7, 0, GPIO_CFG_INPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA), /* DAT7 */
901 GPIO_CFG(8, 0, GPIO_CFG_INPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA), /* DAT8 */
902 GPIO_CFG(9, 0, GPIO_CFG_INPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA), /* DAT9 */
903 GPIO_CFG(10, 0, GPIO_CFG_INPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA), /* DAT10 */
904 GPIO_CFG(11, 0, GPIO_CFG_INPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA), /* DAT11 */
905 GPIO_CFG(12, 0, GPIO_CFG_INPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA), /* PCLK */
906 GPIO_CFG(13, 0, GPIO_CFG_INPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA), /* HSYNC_IN */
907 GPIO_CFG(14, 0, GPIO_CFG_INPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA), /* VSYNC_IN */
908 GPIO_CFG(15, 0, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), /* MCLK */
909};
910
911static uint32_t camera_on_vcm_gpio_table[] = {
912GPIO_CFG(1, 0, GPIO_CFG_OUTPUT, GPIO_CFG_PULL_UP, GPIO_CFG_2MA), /* VCM */
913};
914
915static uint32_t camera_on_gpio_table[] = {
916 /* parallel CAMERA interfaces */
917 GPIO_CFG(0, 0, GPIO_CFG_OUTPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA), /* RST */
918 GPIO_CFG(2, 1, GPIO_CFG_INPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA), /* DAT2 */
919 GPIO_CFG(3, 1, GPIO_CFG_INPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA), /* DAT3 */
920 GPIO_CFG(4, 1, GPIO_CFG_INPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA), /* DAT4 */
921 GPIO_CFG(5, 1, GPIO_CFG_INPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA), /* DAT5 */
922 GPIO_CFG(6, 1, GPIO_CFG_INPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA), /* DAT6 */
923 GPIO_CFG(7, 1, GPIO_CFG_INPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA), /* DAT7 */
924 GPIO_CFG(8, 1, GPIO_CFG_INPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA), /* DAT8 */
925 GPIO_CFG(9, 1, GPIO_CFG_INPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA), /* DAT9 */
926 GPIO_CFG(10, 1, GPIO_CFG_INPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA), /* DAT10 */
927 GPIO_CFG(11, 1, GPIO_CFG_INPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA), /* DAT11 */
928 GPIO_CFG(12, 1, GPIO_CFG_INPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA), /* PCLK */
929 GPIO_CFG(13, 1, GPIO_CFG_INPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA), /* HSYNC_IN */
930 GPIO_CFG(14, 1, GPIO_CFG_INPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA), /* VSYNC_IN */
931 GPIO_CFG(15, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), /* MCLK */
932};
933
934static uint32_t camera_off_gpio_fluid_table[] = {
935 /* FLUID: CAM_VGA_RST_N */
936 GPIO_CFG(31, 0, GPIO_CFG_OUTPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA),
937 /* FLUID: CAMIF_STANDBY */
938 GPIO_CFG(CAM_STNDBY, 0, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA)
939};
940
941static uint32_t camera_on_gpio_fluid_table[] = {
942 /* FLUID: CAM_VGA_RST_N */
943 GPIO_CFG(31, 0, GPIO_CFG_OUTPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA),
944 /* FLUID: CAMIF_STANDBY */
945 GPIO_CFG(CAM_STNDBY, 0, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA)
946};
947
948static void config_gpio_table(uint32_t *table, int len)
949{
950 int n, rc;
951 for (n = 0; n < len; n++) {
952 rc = gpio_tlmm_config(table[n], GPIO_CFG_ENABLE);
953 if (rc) {
954 pr_err("%s: gpio_tlmm_config(%#x)=%d\n",
955 __func__, table[n], rc);
956 break;
957 }
958 }
959}
960static int config_camera_on_gpios(void)
961{
962 config_gpio_table(camera_on_gpio_table,
963 ARRAY_SIZE(camera_on_gpio_table));
964
965 if (adie_get_detected_codec_type() != TIMPANI_ID)
966 /* GPIO1 is shared also used in Timpani RF card so
967 only configure it for non-Timpani RF card */
968 config_gpio_table(camera_on_vcm_gpio_table,
969 ARRAY_SIZE(camera_on_vcm_gpio_table));
970
971 if (machine_is_msm7x30_fluid()) {
972 config_gpio_table(camera_on_gpio_fluid_table,
973 ARRAY_SIZE(camera_on_gpio_fluid_table));
974 /* FLUID: turn on 5V booster */
975 gpio_set_value(
976 PM8058_GPIO_PM_TO_SYS(PMIC_GPIO_FLASH_BOOST_ENABLE), 1);
977 /* FLUID: drive high to put secondary sensor to STANDBY */
978 gpio_set_value(CAM_STNDBY, 1);
979 }
980 return 0;
981}
982
983static void config_camera_off_gpios(void)
984{
985 config_gpio_table(camera_off_gpio_table,
986 ARRAY_SIZE(camera_off_gpio_table));
987
988 if (adie_get_detected_codec_type() != TIMPANI_ID)
989 /* GPIO1 is shared also used in Timpani RF card so
990 only configure it for non-Timpani RF card */
991 config_gpio_table(camera_off_vcm_gpio_table,
992 ARRAY_SIZE(camera_off_vcm_gpio_table));
993
994 if (machine_is_msm7x30_fluid()) {
995 config_gpio_table(camera_off_gpio_fluid_table,
996 ARRAY_SIZE(camera_off_gpio_fluid_table));
997 /* FLUID: turn off 5V booster */
998 gpio_set_value(
999 PM8058_GPIO_PM_TO_SYS(PMIC_GPIO_FLASH_BOOST_ENABLE), 0);
1000 }
1001}
1002
1003struct resource msm_camera_resources[] = {
1004 {
1005 .start = 0xA6000000,
1006 .end = 0xA6000000 + SZ_1M - 1,
1007 .flags = IORESOURCE_MEM,
1008 },
1009 {
1010 .start = INT_VFE,
1011 .end = INT_VFE,
1012 .flags = IORESOURCE_IRQ,
1013 },
1014 {
1015 .flags = IORESOURCE_DMA,
1016 }
1017};
1018
1019struct msm_camera_device_platform_data msm_camera_device_data = {
1020 .camera_gpio_on = config_camera_on_gpios,
1021 .camera_gpio_off = config_camera_off_gpios,
1022 .ioext.camifpadphy = 0xAB000000,
1023 .ioext.camifpadsz = 0x00000400,
1024 .ioext.csiphy = 0xA6100000,
1025 .ioext.csisz = 0x00000400,
1026 .ioext.csiirq = INT_CSI,
1027 .ioclk.mclk_clk_rate = 24000000,
1028 .ioclk.vfe_clk_rate = 147456000,
1029};
1030
1031static struct msm_camera_sensor_flash_src msm_flash_src_pwm = {
1032 .flash_sr_type = MSM_CAMERA_FLASH_SRC_PWM,
1033 ._fsrc.pwm_src.freq = 1000,
1034 ._fsrc.pwm_src.max_load = 300,
1035 ._fsrc.pwm_src.low_load = 30,
1036 ._fsrc.pwm_src.high_load = 100,
1037 ._fsrc.pwm_src.channel = 7,
1038};
1039
1040#ifdef CONFIG_MT9D112
1041static struct msm_camera_sensor_flash_data flash_mt9d112 = {
1042 .flash_type = MSM_CAMERA_FLASH_LED,
1043 .flash_src = &msm_flash_src_pwm
1044};
1045
1046static struct msm_camera_sensor_info msm_camera_sensor_mt9d112_data = {
1047 .sensor_name = "mt9d112",
1048 .sensor_reset = 0,
1049 .sensor_pwd = 85,
1050 .vcm_pwd = 1,
1051 .vcm_enable = 0,
1052 .pdata = &msm_camera_device_data,
1053 .resource = msm_camera_resources,
1054 .num_resources = ARRAY_SIZE(msm_camera_resources),
1055 .flash_data = &flash_mt9d112,
1056 .csi_if = 0
1057};
1058
1059static struct platform_device msm_camera_sensor_mt9d112 = {
1060 .name = "msm_camera_mt9d112",
1061 .dev = {
1062 .platform_data = &msm_camera_sensor_mt9d112_data,
1063 },
1064};
1065#endif
1066
1067#ifdef CONFIG_WEBCAM_OV9726
1068
1069static struct msm_camera_sensor_platform_info ov9726_sensor_7630_info = {
1070 .mount_angle = 90
1071};
1072
1073static struct msm_camera_sensor_flash_data flash_ov9726 = {
1074 .flash_type = MSM_CAMERA_FLASH_LED,
1075 .flash_src = &msm_flash_src_pwm
1076};
1077static struct msm_camera_sensor_info msm_camera_sensor_ov9726_data = {
1078 .sensor_name = "ov9726",
1079 .sensor_reset = 0,
1080 .sensor_pwd = 85,
1081 .vcm_pwd = 1,
1082 .vcm_enable = 0,
1083 .pdata = &msm_camera_device_data,
1084 .resource = msm_camera_resources,
1085 .num_resources = ARRAY_SIZE(msm_camera_resources),
1086 .flash_data = &flash_ov9726,
1087 .sensor_platform_info = &ov9726_sensor_7630_info,
1088 .csi_if = 1
1089};
1090struct platform_device msm_camera_sensor_ov9726 = {
1091 .name = "msm_camera_ov9726",
1092 .dev = {
1093 .platform_data = &msm_camera_sensor_ov9726_data,
1094 },
1095};
1096#endif
1097
1098#ifdef CONFIG_S5K3E2FX
1099static struct msm_camera_sensor_flash_data flash_s5k3e2fx = {
1100 .flash_type = MSM_CAMERA_FLASH_LED,
1101 .flash_src = &msm_flash_src_pwm,
1102};
1103
1104static struct msm_camera_sensor_info msm_camera_sensor_s5k3e2fx_data = {
1105 .sensor_name = "s5k3e2fx",
1106 .sensor_reset = 0,
1107 .sensor_pwd = 85,
1108 .vcm_pwd = 1,
1109 .vcm_enable = 0,
1110 .pdata = &msm_camera_device_data,
1111 .resource = msm_camera_resources,
1112 .num_resources = ARRAY_SIZE(msm_camera_resources),
1113 .flash_data = &flash_s5k3e2fx,
1114 .csi_if = 0
1115};
1116
1117static struct platform_device msm_camera_sensor_s5k3e2fx = {
1118 .name = "msm_camera_s5k3e2fx",
1119 .dev = {
1120 .platform_data = &msm_camera_sensor_s5k3e2fx_data,
1121 },
1122};
1123#endif
1124
1125#ifdef CONFIG_MT9P012
1126static struct msm_camera_sensor_flash_data flash_mt9p012 = {
1127 .flash_type = MSM_CAMERA_FLASH_LED,
1128 .flash_src = &msm_flash_src_pwm
1129};
1130
1131static struct msm_camera_sensor_info msm_camera_sensor_mt9p012_data = {
1132 .sensor_name = "mt9p012",
1133 .sensor_reset = 0,
1134 .sensor_pwd = 85,
1135 .vcm_pwd = 1,
1136 .vcm_enable = 1,
1137 .pdata = &msm_camera_device_data,
1138 .resource = msm_camera_resources,
1139 .num_resources = ARRAY_SIZE(msm_camera_resources),
1140 .flash_data = &flash_mt9p012,
1141 .csi_if = 0
1142};
1143
1144static struct platform_device msm_camera_sensor_mt9p012 = {
1145 .name = "msm_camera_mt9p012",
1146 .dev = {
1147 .platform_data = &msm_camera_sensor_mt9p012_data,
1148 },
1149};
1150#endif
1151
1152#ifdef CONFIG_MT9E013
1153static struct msm_camera_sensor_platform_info mt9e013_sensor_7630_info = {
1154 .mount_angle = 0
1155};
1156
1157static struct msm_camera_sensor_flash_data flash_mt9e013 = {
1158 .flash_type = MSM_CAMERA_FLASH_LED,
1159 .flash_src = &msm_flash_src_pwm
1160};
1161
1162static struct msm_camera_sensor_info msm_camera_sensor_mt9e013_data = {
1163 .sensor_name = "mt9e013",
1164 .sensor_reset = 0,
1165 .sensor_pwd = 85,
1166 .vcm_pwd = 1,
1167 .vcm_enable = 1,
1168 .pdata = &msm_camera_device_data,
1169 .resource = msm_camera_resources,
1170 .num_resources = ARRAY_SIZE(msm_camera_resources),
1171 .flash_data = &flash_mt9e013,
1172 .sensor_platform_info = &mt9e013_sensor_7630_info,
1173 .csi_if = 1
1174};
1175
1176static struct platform_device msm_camera_sensor_mt9e013 = {
1177 .name = "msm_camera_mt9e013",
1178 .dev = {
1179 .platform_data = &msm_camera_sensor_mt9e013_data,
1180 },
1181};
1182#endif
1183
1184#ifdef CONFIG_VX6953
1185static struct msm_camera_sensor_flash_data flash_vx6953 = {
1186 .flash_type = MSM_CAMERA_FLASH_LED,
1187 .flash_src = &msm_flash_src_pwm
1188};
1189static struct msm_camera_sensor_info msm_camera_sensor_vx6953_data = {
1190 .sensor_name = "vx6953",
1191 .sensor_reset = 0,
1192 .sensor_pwd = 85,
1193 .vcm_pwd = 1,
1194 .vcm_enable = 0,
1195 .pdata = &msm_camera_device_data,
1196 .resource = msm_camera_resources,
1197 .num_resources = ARRAY_SIZE(msm_camera_resources),
1198 .flash_data = &flash_vx6953,
1199 .csi_if = 1
1200};
1201static struct platform_device msm_camera_sensor_vx6953 = {
1202 .name = "msm_camera_vx6953",
1203 .dev = {
1204 .platform_data = &msm_camera_sensor_vx6953_data,
1205 },
1206};
1207#endif
1208
1209#ifdef CONFIG_SN12M0PZ
1210static struct msm_camera_sensor_flash_src msm_flash_src_current_driver = {
1211 .flash_sr_type = MSM_CAMERA_FLASH_SRC_CURRENT_DRIVER,
1212 ._fsrc.current_driver_src.low_current = 210,
1213 ._fsrc.current_driver_src.high_current = 700,
1214 ._fsrc.current_driver_src.driver_channel = &pm8058_fluid_leds_data,
1215};
1216
1217static struct msm_camera_sensor_flash_data flash_sn12m0pz = {
1218 .flash_type = MSM_CAMERA_FLASH_LED,
1219 .flash_src = &msm_flash_src_current_driver
1220};
1221static struct msm_camera_sensor_info msm_camera_sensor_sn12m0pz_data = {
1222 .sensor_name = "sn12m0pz",
1223 .sensor_reset = 0,
1224 .sensor_pwd = 85,
1225 .vcm_pwd = 1,
1226 .vcm_enable = 1,
1227 .pdata = &msm_camera_device_data,
1228 .flash_data = &flash_sn12m0pz,
1229 .resource = msm_camera_resources,
1230 .num_resources = ARRAY_SIZE(msm_camera_resources),
1231 .csi_if = 0
1232};
1233
1234static struct platform_device msm_camera_sensor_sn12m0pz = {
1235 .name = "msm_camera_sn12m0pz",
1236 .dev = {
1237 .platform_data = &msm_camera_sensor_sn12m0pz_data,
1238 },
1239};
1240#endif
1241
1242#ifdef CONFIG_MT9T013
1243static struct msm_camera_sensor_flash_data flash_mt9t013 = {
1244 .flash_type = MSM_CAMERA_FLASH_LED,
1245 .flash_src = &msm_flash_src_pwm
1246};
1247
1248static struct msm_camera_sensor_info msm_camera_sensor_mt9t013_data = {
1249 .sensor_name = "mt9t013",
1250 .sensor_reset = 0,
1251 .sensor_pwd = 85,
1252 .vcm_pwd = 1,
1253 .vcm_enable = 0,
1254 .pdata = &msm_camera_device_data,
1255 .resource = msm_camera_resources,
1256 .num_resources = ARRAY_SIZE(msm_camera_resources),
1257 .flash_data = &flash_mt9t013,
1258 .csi_if = 1
1259};
1260
1261static struct platform_device msm_camera_sensor_mt9t013 = {
1262 .name = "msm_camera_mt9t013",
1263 .dev = {
1264 .platform_data = &msm_camera_sensor_mt9t013_data,
1265 },
1266};
1267#endif
1268
1269#ifdef CONFIG_MSM_GEMINI
1270static struct resource msm_gemini_resources[] = {
1271 {
1272 .start = 0xA3A00000,
1273 .end = 0xA3A00000 + 0x0150 - 1,
1274 .flags = IORESOURCE_MEM,
1275 },
1276 {
1277 .start = INT_JPEG,
1278 .end = INT_JPEG,
1279 .flags = IORESOURCE_IRQ,
1280 },
1281};
1282
1283static struct platform_device msm_gemini_device = {
1284 .name = "msm_gemini",
1285 .resource = msm_gemini_resources,
1286 .num_resources = ARRAY_SIZE(msm_gemini_resources),
1287};
1288#endif
1289
1290#ifdef CONFIG_MSM_VPE
1291static struct resource msm_vpe_resources[] = {
1292 {
1293 .start = 0xAD200000,
1294 .end = 0xAD200000 + SZ_1M - 1,
1295 .flags = IORESOURCE_MEM,
1296 },
1297 {
1298 .start = INT_VPE,
1299 .end = INT_VPE,
1300 .flags = IORESOURCE_IRQ,
1301 },
1302};
1303
1304static struct platform_device msm_vpe_device = {
1305 .name = "msm_vpe",
1306 .id = 0,
1307 .num_resources = ARRAY_SIZE(msm_vpe_resources),
1308 .resource = msm_vpe_resources,
1309};
1310#endif
1311
1312#endif /*CONFIG_MSM_CAMERA*/
1313
1314#ifdef CONFIG_MSM7KV2_AUDIO
1315static uint32_t audio_pamp_gpio_config =
1316 GPIO_CFG(82, 0, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA);
1317
1318static uint32_t audio_fluid_icodec_tx_config =
1319 GPIO_CFG(85, 0, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA);
1320
1321static int __init snddev_poweramp_gpio_init(void)
1322{
1323 int rc;
1324
1325 pr_info("snddev_poweramp_gpio_init \n");
1326 rc = gpio_tlmm_config(audio_pamp_gpio_config, GPIO_CFG_ENABLE);
1327 if (rc) {
1328 printk(KERN_ERR
1329 "%s: gpio_tlmm_config(%#x)=%d\n",
1330 __func__, audio_pamp_gpio_config, rc);
1331 }
1332 return rc;
1333}
1334
1335void msm_snddev_tx_route_config(void)
1336{
1337 int rc;
1338
1339 pr_debug("%s()\n", __func__);
1340
1341 if (machine_is_msm7x30_fluid()) {
1342 rc = gpio_tlmm_config(audio_fluid_icodec_tx_config,
1343 GPIO_CFG_ENABLE);
1344 if (rc) {
1345 printk(KERN_ERR
1346 "%s: gpio_tlmm_config(%#x)=%d\n",
1347 __func__, audio_fluid_icodec_tx_config, rc);
1348 } else
1349 gpio_set_value(85, 0);
1350 }
1351}
1352
1353void msm_snddev_tx_route_deconfig(void)
1354{
1355 int rc;
1356
1357 pr_debug("%s()\n", __func__);
1358
1359 if (machine_is_msm7x30_fluid()) {
1360 rc = gpio_tlmm_config(audio_fluid_icodec_tx_config,
1361 GPIO_CFG_DISABLE);
1362 if (rc) {
1363 printk(KERN_ERR
1364 "%s: gpio_tlmm_config(%#x)=%d\n",
1365 __func__, audio_fluid_icodec_tx_config, rc);
1366 }
1367 }
1368}
1369
1370void msm_snddev_poweramp_on(void)
1371{
1372 gpio_set_value(82, 1); /* enable spkr poweramp */
1373 pr_info("%s: power on amplifier\n", __func__);
1374}
1375
1376void msm_snddev_poweramp_off(void)
1377{
1378 gpio_set_value(82, 0); /* disable spkr poweramp */
1379 pr_info("%s: power off amplifier\n", __func__);
1380}
1381
1382static struct vreg *snddev_vreg_ncp, *snddev_vreg_gp4;
1383
1384void msm_snddev_hsed_voltage_on(void)
1385{
1386 int rc;
1387
1388 snddev_vreg_gp4 = vreg_get(NULL, "gp4");
1389 if (IS_ERR(snddev_vreg_gp4)) {
1390 pr_err("%s: vreg_get(%s) failed (%ld)\n",
1391 __func__, "gp4", PTR_ERR(snddev_vreg_gp4));
1392 return;
1393 }
1394 rc = vreg_enable(snddev_vreg_gp4);
1395 if (rc)
1396 pr_err("%s: vreg_enable(gp4) failed (%d)\n", __func__, rc);
1397
1398 snddev_vreg_ncp = vreg_get(NULL, "ncp");
1399 if (IS_ERR(snddev_vreg_ncp)) {
1400 pr_err("%s: vreg_get(%s) failed (%ld)\n",
1401 __func__, "ncp", PTR_ERR(snddev_vreg_ncp));
1402 return;
1403 }
1404 rc = vreg_enable(snddev_vreg_ncp);
1405 if (rc)
1406 pr_err("%s: vreg_enable(ncp) failed (%d)\n", __func__, rc);
1407}
1408
1409void msm_snddev_hsed_voltage_off(void)
1410{
1411 int rc;
1412
1413 if (IS_ERR(snddev_vreg_ncp)) {
1414 pr_err("%s: vreg_get(%s) failed (%ld)\n",
1415 __func__, "ncp", PTR_ERR(snddev_vreg_ncp));
1416 return;
1417 }
1418 rc = vreg_disable(snddev_vreg_ncp);
1419 if (rc)
1420 pr_err("%s: vreg_disable(ncp) failed (%d)\n", __func__, rc);
1421 vreg_put(snddev_vreg_ncp);
1422
1423 if (IS_ERR(snddev_vreg_gp4)) {
1424 pr_err("%s: vreg_get(%s) failed (%ld)\n",
1425 __func__, "gp4", PTR_ERR(snddev_vreg_gp4));
1426 return;
1427 }
1428 rc = vreg_disable(snddev_vreg_gp4);
1429 if (rc)
1430 pr_err("%s: vreg_disable(gp4) failed (%d)\n", __func__, rc);
1431
1432 vreg_put(snddev_vreg_gp4);
1433
1434}
1435
1436static unsigned aux_pcm_gpio_on[] = {
1437 GPIO_CFG(138, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), /* PCM_DOUT */
1438 GPIO_CFG(139, 1, GPIO_CFG_INPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), /* PCM_DIN */
1439 GPIO_CFG(140, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), /* PCM_SYNC */
1440 GPIO_CFG(141, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), /* PCM_CLK */
1441};
1442
1443static int __init aux_pcm_gpio_init(void)
1444{
1445 int pin, rc;
1446
1447 pr_info("aux_pcm_gpio_init \n");
1448 for (pin = 0; pin < ARRAY_SIZE(aux_pcm_gpio_on); pin++) {
1449 rc = gpio_tlmm_config(aux_pcm_gpio_on[pin],
1450 GPIO_CFG_ENABLE);
1451 if (rc) {
1452 printk(KERN_ERR
1453 "%s: gpio_tlmm_config(%#x)=%d\n",
1454 __func__, aux_pcm_gpio_on[pin], rc);
1455 }
1456 }
1457 return rc;
1458}
1459
1460static struct msm_gpio mi2s_clk_gpios[] = {
1461 { GPIO_CFG(145, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA),
1462 "MI2S_SCLK"},
1463 { GPIO_CFG(144, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA),
1464 "MI2S_WS"},
1465 { GPIO_CFG(120, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA),
1466 "MI2S_MCLK_A"},
1467};
1468
1469static struct msm_gpio mi2s_rx_data_lines_gpios[] = {
1470 { GPIO_CFG(121, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA),
1471 "MI2S_DATA_SD0_A"},
1472 { GPIO_CFG(122, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA),
1473 "MI2S_DATA_SD1_A"},
1474 { GPIO_CFG(123, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA),
1475 "MI2S_DATA_SD2_A"},
1476 { GPIO_CFG(146, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA),
1477 "MI2S_DATA_SD3"},
1478};
1479
1480static struct msm_gpio mi2s_tx_data_lines_gpios[] = {
1481 { GPIO_CFG(146, 1, GPIO_CFG_INPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA),
1482 "MI2S_DATA_SD3"},
1483};
1484
1485int mi2s_config_clk_gpio(void)
1486{
1487 int rc = 0;
1488
1489 rc = msm_gpios_request_enable(mi2s_clk_gpios,
1490 ARRAY_SIZE(mi2s_clk_gpios));
1491 if (rc) {
1492 pr_err("%s: enable mi2s clk gpios failed\n",
1493 __func__);
1494 return rc;
1495 }
1496 return 0;
1497}
1498
1499int mi2s_unconfig_data_gpio(u32 direction, u8 sd_line_mask)
1500{
1501 int i, rc = 0;
1502 sd_line_mask &= MI2S_SD_LINE_MASK;
1503
1504 switch (direction) {
1505 case DIR_TX:
1506 msm_gpios_disable_free(mi2s_tx_data_lines_gpios, 1);
1507 break;
1508 case DIR_RX:
1509 i = 0;
1510 while (sd_line_mask) {
1511 if (sd_line_mask & 0x1)
1512 msm_gpios_disable_free(
1513 mi2s_rx_data_lines_gpios + i , 1);
1514 sd_line_mask = sd_line_mask >> 1;
1515 i++;
1516 }
1517 break;
1518 default:
1519 pr_err("%s: Invaild direction direction = %u\n",
1520 __func__, direction);
1521 rc = -EINVAL;
1522 break;
1523 }
1524 return rc;
1525}
1526
1527int mi2s_config_data_gpio(u32 direction, u8 sd_line_mask)
1528{
1529 int i , rc = 0;
1530 u8 sd_config_done_mask = 0;
1531
1532 sd_line_mask &= MI2S_SD_LINE_MASK;
1533
1534 switch (direction) {
1535 case DIR_TX:
1536 if ((sd_line_mask & MI2S_SD_0) || (sd_line_mask & MI2S_SD_1) ||
1537 (sd_line_mask & MI2S_SD_2) || !(sd_line_mask & MI2S_SD_3)) {
1538 pr_err("%s: can not use SD0 or SD1 or SD2 for TX"
1539 ".only can use SD3. sd_line_mask = 0x%x\n",
1540 __func__ , sd_line_mask);
1541 rc = -EINVAL;
1542 } else {
1543 rc = msm_gpios_request_enable(mi2s_tx_data_lines_gpios,
1544 1);
1545 if (rc)
1546 pr_err("%s: enable mi2s gpios for TX failed\n",
1547 __func__);
1548 }
1549 break;
1550 case DIR_RX:
1551 i = 0;
1552 while (sd_line_mask && (rc == 0)) {
1553 if (sd_line_mask & 0x1) {
1554 rc = msm_gpios_request_enable(
1555 mi2s_rx_data_lines_gpios + i , 1);
1556 if (rc) {
1557 pr_err("%s: enable mi2s gpios for"
1558 "RX failed. SD line = %s\n",
1559 __func__,
1560 (mi2s_rx_data_lines_gpios + i)->label);
1561 mi2s_unconfig_data_gpio(DIR_RX,
1562 sd_config_done_mask);
1563 } else
1564 sd_config_done_mask |= (1 << i);
1565 }
1566 sd_line_mask = sd_line_mask >> 1;
1567 i++;
1568 }
1569 break;
1570 default:
1571 pr_err("%s: Invaild direction direction = %u\n",
1572 __func__, direction);
1573 rc = -EINVAL;
1574 break;
1575 }
1576 return rc;
1577}
1578
1579int mi2s_unconfig_clk_gpio(void)
1580{
1581 msm_gpios_disable_free(mi2s_clk_gpios, ARRAY_SIZE(mi2s_clk_gpios));
1582 return 0;
1583}
1584
1585#endif /* CONFIG_MSM7KV2_AUDIO */
1586
1587static int __init buses_init(void)
1588{
1589 if (gpio_tlmm_config(GPIO_CFG(PMIC_GPIO_INT, 1, GPIO_CFG_INPUT,
1590 GPIO_CFG_NO_PULL, GPIO_CFG_2MA), GPIO_CFG_ENABLE))
1591 pr_err("%s: gpio_tlmm_config (gpio=%d) failed\n",
1592 __func__, PMIC_GPIO_INT);
1593
1594 if (machine_is_msm7x30_fluid()) {
1595 pm8058_7x30_data.sub_devices[PM8058_SUBDEV_KPD].platform_data
1596 = &fluid_keypad_data;
1597 } else {
1598 pm8058_7x30_data.sub_devices[PM8058_SUBDEV_KPD].platform_data
1599 = &surf_keypad_data;
1600 pm8058_7x30_data.sub_devices[PM8058_SUBDEV_KPD].pdata_size
1601 = sizeof(surf_keypad_data);
1602 }
1603
1604 i2c_register_board_info(6 /* I2C_SSBI ID */, pm8058_boardinfo,
1605 ARRAY_SIZE(pm8058_boardinfo));
1606
1607 return 0;
1608}
1609
1610#define TIMPANI_RESET_GPIO 1
1611
1612struct bahama_config_register{
1613 u8 reg;
1614 u8 value;
1615 u8 mask;
1616};
1617
1618enum version{
1619 VER_1_0,
1620 VER_2_0,
1621 VER_UNSUPPORTED = 0xFF
1622};
1623
1624
1625static struct vreg *vreg_marimba_1;
1626static struct vreg *vreg_marimba_2;
1627static struct vreg *vreg_marimba_3;
1628
1629static struct msm_gpio timpani_reset_gpio_cfg[] = {
1630{ GPIO_CFG(TIMPANI_RESET_GPIO, 0, GPIO_CFG_OUTPUT,
1631 GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "timpani_reset"} };
1632
1633static u8 read_bahama_ver(void)
1634{
1635 int rc;
1636 struct marimba config = { .mod_id = SLAVE_ID_BAHAMA };
1637 u8 bahama_version;
1638
1639 rc = marimba_read_bit_mask(&config, 0x00, &bahama_version, 1, 0x1F);
1640 if (rc < 0) {
1641 printk(KERN_ERR
1642 "%s: version read failed: %d\n",
1643 __func__, rc);
1644 return rc;
1645 } else {
1646 printk(KERN_INFO
1647 "%s: version read got: 0x%x\n",
1648 __func__, bahama_version);
1649 }
1650
1651 switch (bahama_version) {
1652 case 0x08: /* varient of bahama v1 */
1653 case 0x10:
1654 case 0x00:
1655 return VER_1_0;
1656 case 0x09: /* variant of bahama v2 */
1657 return VER_2_0;
1658 default:
1659 return VER_UNSUPPORTED;
1660 }
1661}
1662
1663static int config_timpani_reset(void)
1664{
1665 int rc;
1666
1667 rc = msm_gpios_request_enable(timpani_reset_gpio_cfg,
1668 ARRAY_SIZE(timpani_reset_gpio_cfg));
1669 if (rc < 0) {
1670 printk(KERN_ERR
1671 "%s: msm_gpios_request_enable failed (%d)\n",
1672 __func__, rc);
1673 }
1674 return rc;
1675}
1676
1677static unsigned int msm_timpani_setup_power(void)
1678{
1679 int rc;
1680
1681 rc = config_timpani_reset();
1682 if (rc < 0)
1683 goto out;
1684
1685 rc = vreg_enable(vreg_marimba_1);
1686 if (rc) {
1687 printk(KERN_ERR "%s: vreg_enable() = %d\n",
1688 __func__, rc);
1689 goto out;
1690 }
1691 rc = vreg_enable(vreg_marimba_2);
1692 if (rc) {
1693 printk(KERN_ERR "%s: vreg_enable() = %d\n",
1694 __func__, rc);
1695 goto fail_disable_vreg_marimba_1;
1696 }
1697
1698 rc = gpio_direction_output(TIMPANI_RESET_GPIO, 1);
1699 if (rc < 0) {
1700 printk(KERN_ERR
1701 "%s: gpio_direction_output failed (%d)\n",
1702 __func__, rc);
1703 msm_gpios_free(timpani_reset_gpio_cfg,
1704 ARRAY_SIZE(timpani_reset_gpio_cfg));
1705 vreg_disable(vreg_marimba_2);
1706 } else
1707 goto out;
1708
1709
1710fail_disable_vreg_marimba_1:
1711 vreg_disable(vreg_marimba_1);
1712
1713out:
1714 return rc;
1715};
1716
1717static void msm_timpani_shutdown_power(void)
1718{
1719 int rc;
1720
1721 rc = vreg_disable(vreg_marimba_1);
1722 if (rc) {
1723 printk(KERN_ERR "%s: return val: %d\n",
1724 __func__, rc);
1725 }
1726 rc = vreg_disable(vreg_marimba_2);
1727 if (rc) {
1728 printk(KERN_ERR "%s: return val: %d\n",
1729 __func__, rc);
1730 }
1731
1732 rc = gpio_direction_output(TIMPANI_RESET_GPIO, 0);
1733 if (rc < 0) {
1734 printk(KERN_ERR
1735 "%s: gpio_direction_output failed (%d)\n",
1736 __func__, rc);
1737 }
1738
1739 msm_gpios_free(timpani_reset_gpio_cfg,
1740 ARRAY_SIZE(timpani_reset_gpio_cfg));
1741};
1742
1743static unsigned int msm_bahama_core_config(int type)
1744{
1745 int rc = 0;
1746
1747 if (type == BAHAMA_ID) {
1748
1749 int i;
1750 struct marimba config = { .mod_id = SLAVE_ID_BAHAMA };
1751
1752 const struct bahama_config_register v20_init[] = {
1753 /* reg, value, mask */
1754 { 0xF4, 0x84, 0xFF }, /* AREG */
1755 { 0xF0, 0x04, 0xFF } /* DREG */
1756 };
1757
1758 if (read_bahama_ver() == VER_2_0) {
1759 for (i = 0; i < ARRAY_SIZE(v20_init); i++) {
1760 u8 value = v20_init[i].value;
1761 rc = marimba_write_bit_mask(&config,
1762 v20_init[i].reg,
1763 &value,
1764 sizeof(v20_init[i].value),
1765 v20_init[i].mask);
1766 if (rc < 0) {
1767 printk(KERN_ERR
1768 "%s: reg %d write failed: %d\n",
1769 __func__, v20_init[i].reg, rc);
1770 return rc;
1771 }
1772 printk(KERN_INFO "%s: reg 0x%02x value 0x%02x"
1773 " mask 0x%02x\n",
1774 __func__, v20_init[i].reg,
1775 v20_init[i].value, v20_init[i].mask);
1776 }
1777 }
1778 }
1779 printk(KERN_INFO "core type: %d\n", type);
1780
1781 return rc;
1782}
1783
1784static unsigned int msm_bahama_setup_power(void)
1785{
1786 int rc;
1787
1788 rc = vreg_enable(vreg_marimba_3);
1789 if (rc) {
1790 printk(KERN_ERR "%s: vreg_enable() = %d\n",
1791 __func__, rc);
1792 }
1793
1794 return rc;
1795};
1796
1797static unsigned int msm_bahama_shutdown_power(int value)
1798{
1799 int rc = 0;
1800
1801 if (value != BAHAMA_ID) {
1802 rc = vreg_disable(vreg_marimba_3);
1803 if (rc) {
1804 printk(KERN_ERR "%s: return val: %d\n",
1805 __func__, rc);
1806 }
1807 }
1808
1809 return rc;
1810};
1811
1812static struct msm_gpio marimba_svlte_config_clock[] = {
1813 { GPIO_CFG(34, 0, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA),
1814 "MARIMBA_SVLTE_CLOCK_ENABLE" },
1815};
1816
1817static unsigned int msm_marimba_gpio_config_svlte(int gpio_cfg_marimba)
1818{
1819 if (machine_is_msm8x55_svlte_surf() ||
1820 machine_is_msm8x55_svlte_ffa()) {
1821 if (gpio_cfg_marimba)
1822 gpio_set_value(GPIO_PIN
1823 (marimba_svlte_config_clock->gpio_cfg), 1);
1824 else
1825 gpio_set_value(GPIO_PIN
1826 (marimba_svlte_config_clock->gpio_cfg), 0);
1827 }
1828
1829 return 0;
1830};
1831
1832static unsigned int msm_marimba_setup_power(void)
1833{
1834 int rc;
1835
1836 rc = vreg_enable(vreg_marimba_1);
1837 if (rc) {
1838 printk(KERN_ERR "%s: vreg_enable() = %d \n",
1839 __func__, rc);
1840 goto out;
1841 }
1842 rc = vreg_enable(vreg_marimba_2);
1843 if (rc) {
1844 printk(KERN_ERR "%s: vreg_enable() = %d \n",
1845 __func__, rc);
1846 goto out;
1847 }
1848
1849 if (machine_is_msm8x55_svlte_surf() || machine_is_msm8x55_svlte_ffa()) {
1850 rc = msm_gpios_request_enable(marimba_svlte_config_clock,
1851 ARRAY_SIZE(marimba_svlte_config_clock));
1852 if (rc < 0) {
1853 printk(KERN_ERR
1854 "%s: msm_gpios_request_enable failed (%d)\n",
1855 __func__, rc);
1856 return rc;
1857 }
1858
1859 rc = gpio_direction_output(GPIO_PIN
1860 (marimba_svlte_config_clock->gpio_cfg), 0);
1861 if (rc < 0) {
1862 printk(KERN_ERR
1863 "%s: gpio_direction_output failed (%d)\n",
1864 __func__, rc);
1865 return rc;
1866 }
1867 }
1868
1869out:
1870 return rc;
1871};
1872
1873static void msm_marimba_shutdown_power(void)
1874{
1875 int rc;
1876
1877 rc = vreg_disable(vreg_marimba_1);
1878 if (rc) {
1879 printk(KERN_ERR "%s: return val: %d\n",
1880 __func__, rc);
1881 }
1882 rc = vreg_disable(vreg_marimba_2);
1883 if (rc) {
1884 printk(KERN_ERR "%s: return val: %d \n",
1885 __func__, rc);
1886 }
1887};
1888
1889static int bahama_present(void)
1890{
1891 int id;
1892 switch (id = adie_get_detected_connectivity_type()) {
1893 case BAHAMA_ID:
1894 return 1;
1895
1896 case MARIMBA_ID:
1897 return 0;
1898
1899 case TIMPANI_ID:
1900 default:
1901 printk(KERN_ERR "%s: unexpected adie connectivity type: %d\n",
1902 __func__, id);
1903 return -ENODEV;
1904 }
1905}
1906
1907struct vreg *fm_regulator;
1908static int fm_radio_setup(struct marimba_fm_platform_data *pdata)
1909{
1910 int rc;
1911 uint32_t irqcfg;
1912 const char *id = "FMPW";
1913
1914 int bahama_not_marimba = bahama_present();
1915
1916 if (bahama_not_marimba == -1) {
1917 printk(KERN_WARNING "%s: bahama_present: %d\n",
1918 __func__, bahama_not_marimba);
1919 return -ENODEV;
1920 }
1921 if (bahama_not_marimba)
1922 fm_regulator = vreg_get(NULL, "s3");
1923 else
1924 fm_regulator = vreg_get(NULL, "s2");
1925
1926 if (IS_ERR(fm_regulator)) {
1927 printk(KERN_ERR "%s: vreg get failed (%ld)\n",
1928 __func__, PTR_ERR(fm_regulator));
1929 return -1;
1930 }
1931 if (!bahama_not_marimba) {
1932
1933 rc = pmapp_vreg_level_vote(id, PMAPP_VREG_S2, 1300);
1934
1935 if (rc < 0) {
1936 printk(KERN_ERR "%s: voltage level vote failed (%d)\n",
1937 __func__, rc);
1938 return rc;
1939 }
1940 }
1941 rc = vreg_enable(fm_regulator);
1942 if (rc) {
1943 printk(KERN_ERR "%s: vreg_enable() = %d\n",
1944 __func__, rc);
1945 return rc;
1946 }
1947
1948 rc = pmapp_clock_vote(id, PMAPP_CLOCK_ID_DO,
1949 PMAPP_CLOCK_VOTE_ON);
1950 if (rc < 0) {
1951 printk(KERN_ERR "%s: clock vote failed (%d)\n",
1952 __func__, rc);
1953 goto fm_clock_vote_fail;
1954 }
1955 /*Request the Clock Using GPIO34/AP2MDM_MRMBCK_EN in case
1956 of svlte*/
1957 if (machine_is_msm8x55_svlte_surf() ||
1958 machine_is_msm8x55_svlte_ffa()) {
1959 rc = marimba_gpio_config(1);
1960 if (rc < 0)
1961 printk(KERN_ERR "%s: clock enable for svlte : %d\n",
1962 __func__, rc);
1963 }
1964 irqcfg = GPIO_CFG(147, 0, GPIO_CFG_INPUT, GPIO_CFG_NO_PULL,
1965 GPIO_CFG_2MA);
1966 rc = gpio_tlmm_config(irqcfg, GPIO_CFG_ENABLE);
1967 if (rc) {
1968 printk(KERN_ERR "%s: gpio_tlmm_config(%#x)=%d\n",
1969 __func__, irqcfg, rc);
1970 rc = -EIO;
1971 goto fm_gpio_config_fail;
1972
1973 }
1974 return 0;
1975fm_gpio_config_fail:
1976 pmapp_clock_vote(id, PMAPP_CLOCK_ID_DO,
1977 PMAPP_CLOCK_VOTE_OFF);
1978fm_clock_vote_fail:
1979 vreg_disable(fm_regulator);
1980 return rc;
1981
1982};
1983
1984static void fm_radio_shutdown(struct marimba_fm_platform_data *pdata)
1985{
1986 int rc;
1987 const char *id = "FMPW";
1988 uint32_t irqcfg = GPIO_CFG(147, 0, GPIO_CFG_INPUT, GPIO_CFG_PULL_UP,
1989 GPIO_CFG_2MA);
1990
1991 int bahama_not_marimba = bahama_present();
1992 if (bahama_not_marimba == -1) {
1993 printk(KERN_WARNING "%s: bahama_present: %d\n",
1994 __func__, bahama_not_marimba);
1995 return;
1996 }
1997
1998 rc = gpio_tlmm_config(irqcfg, GPIO_CFG_ENABLE);
1999 if (rc) {
2000 printk(KERN_ERR "%s: gpio_tlmm_config(%#x)=%d\n",
2001 __func__, irqcfg, rc);
2002 }
2003 if (fm_regulator != NULL) {
2004 rc = vreg_disable(fm_regulator);
2005
2006 if (rc) {
2007 printk(KERN_ERR "%s: return val: %d\n",
2008 __func__, rc);
2009 }
2010 fm_regulator = NULL;
2011 }
2012 rc = pmapp_clock_vote(id, PMAPP_CLOCK_ID_DO,
2013 PMAPP_CLOCK_VOTE_OFF);
2014 if (rc < 0)
2015 printk(KERN_ERR "%s: clock_vote return val: %d\n",
2016 __func__, rc);
2017
2018 /*Disable the Clock Using GPIO34/AP2MDM_MRMBCK_EN in case
2019 of svlte*/
2020 if (machine_is_msm8x55_svlte_surf() ||
2021 machine_is_msm8x55_svlte_ffa()) {
2022 rc = marimba_gpio_config(0);
2023 if (rc < 0)
2024 printk(KERN_ERR "%s: clock disable for svlte : %d\n",
2025 __func__, rc);
2026 }
2027
2028
2029 if (!bahama_not_marimba) {
2030 rc = pmapp_vreg_level_vote(id, PMAPP_VREG_S2, 0);
2031
2032 if (rc < 0)
2033 printk(KERN_ERR "%s: vreg level vote return val: %d\n",
2034 __func__, rc);
2035 }
2036}
2037
2038static struct marimba_fm_platform_data marimba_fm_pdata = {
2039 .fm_setup = fm_radio_setup,
2040 .fm_shutdown = fm_radio_shutdown,
2041 .irq = MSM_GPIO_TO_INT(147),
2042 .vreg_s2 = NULL,
2043 .vreg_xo_out = NULL,
2044 .is_fm_soc_i2s_master = false,
2045 .config_i2s_gpio = NULL,
2046};
2047
2048
2049/* Slave id address for FM/CDC/QMEMBIST
2050 * Values can be programmed using Marimba slave id 0
2051 * should there be a conflict with other I2C devices
2052 * */
2053#define MARIMBA_SLAVE_ID_FM_ADDR 0x2A
2054#define MARIMBA_SLAVE_ID_CDC_ADDR 0x77
2055#define MARIMBA_SLAVE_ID_QMEMBIST_ADDR 0X66
2056
2057#define BAHAMA_SLAVE_ID_FM_ADDR 0x2A
2058#define BAHAMA_SLAVE_ID_QMEMBIST_ADDR 0x7B
2059
2060static const char *tsadc_id = "MADC";
2061static const char *vregs_tsadc_name[] = {
2062 "gp12",
2063 "s2",
2064};
2065static struct vreg *vregs_tsadc[ARRAY_SIZE(vregs_tsadc_name)];
2066
2067static const char *vregs_timpani_tsadc_name[] = {
2068 "s3",
2069 "gp12",
2070 "gp16"
2071};
2072static struct vreg *vregs_timpani_tsadc[ARRAY_SIZE(vregs_timpani_tsadc_name)];
2073
2074static int marimba_tsadc_power(int vreg_on)
2075{
2076 int i, rc = 0;
2077 int tsadc_adie_type = adie_get_detected_codec_type();
2078
2079 if (tsadc_adie_type == TIMPANI_ID) {
2080 for (i = 0; i < ARRAY_SIZE(vregs_timpani_tsadc_name); i++) {
2081 if (!vregs_timpani_tsadc[i]) {
2082 pr_err("%s: vreg_get %s failed(%d)\n",
2083 __func__, vregs_timpani_tsadc_name[i], rc);
2084 goto vreg_fail;
2085 }
2086
2087 rc = vreg_on ? vreg_enable(vregs_timpani_tsadc[i]) :
2088 vreg_disable(vregs_timpani_tsadc[i]);
2089 if (rc < 0) {
2090 pr_err("%s: vreg %s %s failed(%d)\n",
2091 __func__, vregs_timpani_tsadc_name[i],
2092 vreg_on ? "enable" : "disable", rc);
2093 goto vreg_fail;
2094 }
2095 }
2096 /* Vote for D0 and D1 buffer */
2097 rc = pmapp_clock_vote(tsadc_id, PMAPP_CLOCK_ID_D1,
2098 vreg_on ? PMAPP_CLOCK_VOTE_ON : PMAPP_CLOCK_VOTE_OFF);
2099 if (rc) {
2100 pr_err("%s: unable to %svote for d1 clk\n",
2101 __func__, vreg_on ? "" : "de-");
2102 goto do_vote_fail;
2103 }
2104 rc = pmapp_clock_vote(tsadc_id, PMAPP_CLOCK_ID_DO,
2105 vreg_on ? PMAPP_CLOCK_VOTE_ON : PMAPP_CLOCK_VOTE_OFF);
2106 if (rc) {
2107 pr_err("%s: unable to %svote for d1 clk\n",
2108 __func__, vreg_on ? "" : "de-");
2109 goto do_vote_fail;
2110 }
2111 } else if (tsadc_adie_type == MARIMBA_ID) {
2112 for (i = 0; i < ARRAY_SIZE(vregs_tsadc_name); i++) {
2113 if (!vregs_tsadc[i]) {
2114 pr_err("%s: vreg_get %s failed (%d)\n",
2115 __func__, vregs_tsadc_name[i], rc);
2116 goto vreg_fail;
2117 }
2118
2119 rc = vreg_on ? vreg_enable(vregs_tsadc[i]) :
2120 vreg_disable(vregs_tsadc[i]);
2121 if (rc < 0) {
2122 pr_err("%s: vreg %s %s failed (%d)\n",
2123 __func__, vregs_tsadc_name[i],
2124 vreg_on ? "enable" : "disable", rc);
2125 goto vreg_fail;
2126 }
2127 }
2128 /* If marimba vote for DO buffer */
2129 rc = pmapp_clock_vote(tsadc_id, PMAPP_CLOCK_ID_DO,
2130 vreg_on ? PMAPP_CLOCK_VOTE_ON : PMAPP_CLOCK_VOTE_OFF);
2131 if (rc) {
2132 pr_err("%s: unable to %svote for d0 clk\n",
2133 __func__, vreg_on ? "" : "de-");
2134 goto do_vote_fail;
2135 }
2136 } else {
2137 pr_err("%s:Adie %d not supported\n",
2138 __func__, tsadc_adie_type);
2139 return -ENODEV;
2140 }
2141
2142 msleep(5); /* ensure power is stable */
2143
2144 return 0;
2145
2146do_vote_fail:
2147vreg_fail:
2148 while (i) {
2149 if (vreg_on) {
2150 if (tsadc_adie_type == TIMPANI_ID)
2151 vreg_disable(vregs_timpani_tsadc[--i]);
2152 else if (tsadc_adie_type == MARIMBA_ID)
2153 vreg_disable(vregs_tsadc[--i]);
2154 } else {
2155 if (tsadc_adie_type == TIMPANI_ID)
2156 vreg_enable(vregs_timpani_tsadc[--i]);
2157 else if (tsadc_adie_type == MARIMBA_ID)
2158 vreg_enable(vregs_tsadc[--i]);
2159 }
2160 }
2161
2162 return rc;
2163}
2164
2165static int marimba_tsadc_vote(int vote_on)
2166{
2167 int rc = 0;
2168
2169 if (adie_get_detected_codec_type() == MARIMBA_ID) {
2170 int level = vote_on ? 1300 : 0;
2171 rc = pmapp_vreg_level_vote(tsadc_id, PMAPP_VREG_S2, level);
2172 if (rc < 0)
2173 pr_err("%s: vreg level %s failed (%d)\n",
2174 __func__, vote_on ? "on" : "off", rc);
2175 }
2176
2177 return rc;
2178}
2179
2180static int marimba_tsadc_init(void)
2181{
2182 int i, rc = 0;
2183 int tsadc_adie_type = adie_get_detected_codec_type();
2184
2185 if (tsadc_adie_type == TIMPANI_ID) {
2186 for (i = 0; i < ARRAY_SIZE(vregs_timpani_tsadc_name); i++) {
2187 vregs_timpani_tsadc[i] = vreg_get(NULL,
2188 vregs_timpani_tsadc_name[i]);
2189 if (IS_ERR(vregs_timpani_tsadc[i])) {
2190 pr_err("%s: vreg get %s failed (%ld)\n",
2191 __func__, vregs_timpani_tsadc_name[i],
2192 PTR_ERR(vregs_timpani_tsadc[i]));
2193 rc = PTR_ERR(vregs_timpani_tsadc[i]);
2194 goto vreg_get_fail;
2195 }
2196 }
2197 } else if (tsadc_adie_type == MARIMBA_ID) {
2198 for (i = 0; i < ARRAY_SIZE(vregs_tsadc_name); i++) {
2199 vregs_tsadc[i] = vreg_get(NULL, vregs_tsadc_name[i]);
2200 if (IS_ERR(vregs_tsadc[i])) {
2201 pr_err("%s: vreg get %s failed (%ld)\n",
2202 __func__, vregs_tsadc_name[i],
2203 PTR_ERR(vregs_tsadc[i]));
2204 rc = PTR_ERR(vregs_tsadc[i]);
2205 goto vreg_get_fail;
2206 }
2207 }
2208 } else {
2209 pr_err("%s:Adie %d not supported\n",
2210 __func__, tsadc_adie_type);
2211 return -ENODEV;
2212 }
2213
2214 return 0;
2215
2216vreg_get_fail:
2217 while (i) {
2218 if (tsadc_adie_type == TIMPANI_ID)
2219 vreg_put(vregs_timpani_tsadc[--i]);
2220 else if (tsadc_adie_type == MARIMBA_ID)
2221 vreg_put(vregs_tsadc[--i]);
2222 }
2223 return rc;
2224}
2225
2226static int marimba_tsadc_exit(void)
2227{
2228 int i, rc = 0;
2229 int tsadc_adie_type = adie_get_detected_codec_type();
2230
2231 if (tsadc_adie_type == TIMPANI_ID) {
2232 for (i = 0; i < ARRAY_SIZE(vregs_timpani_tsadc_name); i++) {
2233 if (vregs_tsadc[i])
2234 vreg_put(vregs_timpani_tsadc[i]);
2235 }
2236 } else if (tsadc_adie_type == MARIMBA_ID) {
2237 for (i = 0; i < ARRAY_SIZE(vregs_tsadc_name); i++) {
2238 if (vregs_tsadc[i])
2239 vreg_put(vregs_tsadc[i]);
2240 }
2241 rc = pmapp_vreg_level_vote(tsadc_id, PMAPP_VREG_S2, 0);
2242 if (rc < 0)
2243 pr_err("%s: vreg level off failed (%d)\n",
2244 __func__, rc);
2245 } else {
2246 pr_err("%s:Adie %d not supported\n",
2247 __func__, tsadc_adie_type);
2248 rc = -ENODEV;
2249 }
2250
2251 return rc;
2252}
2253
2254
2255static struct msm_ts_platform_data msm_ts_data = {
2256 .min_x = 0,
2257 .max_x = 4096,
2258 .min_y = 0,
2259 .max_y = 4096,
2260 .min_press = 0,
2261 .max_press = 255,
2262 .inv_x = 4096,
2263 .inv_y = 4096,
2264 .can_wakeup = false,
2265};
2266
2267static struct marimba_tsadc_platform_data marimba_tsadc_pdata = {
2268 .marimba_tsadc_power = marimba_tsadc_power,
2269 .init = marimba_tsadc_init,
2270 .exit = marimba_tsadc_exit,
2271 .level_vote = marimba_tsadc_vote,
2272 .tsadc_prechg_en = true,
2273 .can_wakeup = false,
2274 .setup = {
2275 .pen_irq_en = true,
2276 .tsadc_en = true,
2277 },
2278 .params2 = {
2279 .input_clk_khz = 2400,
2280 .sample_prd = TSADC_CLK_3,
2281 },
2282 .params3 = {
2283 .prechg_time_nsecs = 6400,
2284 .stable_time_nsecs = 6400,
2285 .tsadc_test_mode = 0,
2286 },
2287 .tssc_data = &msm_ts_data,
2288};
2289
2290static struct vreg *vreg_codec_s4;
2291static int msm_marimba_codec_power(int vreg_on)
2292{
2293 int rc = 0;
2294
2295 if (!vreg_codec_s4) {
2296
2297 vreg_codec_s4 = vreg_get(NULL, "s4");
2298
2299 if (IS_ERR(vreg_codec_s4)) {
2300 printk(KERN_ERR "%s: vreg_get() failed (%ld)\n",
2301 __func__, PTR_ERR(vreg_codec_s4));
2302 rc = PTR_ERR(vreg_codec_s4);
2303 goto vreg_codec_s4_fail;
2304 }
2305 }
2306
2307 if (vreg_on) {
2308 rc = vreg_enable(vreg_codec_s4);
2309 if (rc)
2310 printk(KERN_ERR "%s: vreg_enable() = %d \n",
2311 __func__, rc);
2312 goto vreg_codec_s4_fail;
2313 } else {
2314 rc = vreg_disable(vreg_codec_s4);
2315 if (rc)
2316 printk(KERN_ERR "%s: vreg_disable() = %d \n",
2317 __func__, rc);
2318 goto vreg_codec_s4_fail;
2319 }
2320
2321vreg_codec_s4_fail:
2322 return rc;
2323}
2324
2325static struct marimba_codec_platform_data mariba_codec_pdata = {
2326 .marimba_codec_power = msm_marimba_codec_power,
2327#ifdef CONFIG_MARIMBA_CODEC
2328 .snddev_profile_init = msm_snddev_init,
2329#endif
2330};
2331
2332static struct marimba_platform_data marimba_pdata = {
2333 .slave_id[MARIMBA_SLAVE_ID_FM] = MARIMBA_SLAVE_ID_FM_ADDR,
2334 .slave_id[MARIMBA_SLAVE_ID_CDC] = MARIMBA_SLAVE_ID_CDC_ADDR,
2335 .slave_id[MARIMBA_SLAVE_ID_QMEMBIST] = MARIMBA_SLAVE_ID_QMEMBIST_ADDR,
2336 .slave_id[SLAVE_ID_BAHAMA_FM] = BAHAMA_SLAVE_ID_FM_ADDR,
2337 .slave_id[SLAVE_ID_BAHAMA_QMEMBIST] = BAHAMA_SLAVE_ID_QMEMBIST_ADDR,
2338 .marimba_setup = msm_marimba_setup_power,
2339 .marimba_shutdown = msm_marimba_shutdown_power,
2340 .bahama_setup = msm_bahama_setup_power,
2341 .bahama_shutdown = msm_bahama_shutdown_power,
2342 .marimba_gpio_config = msm_marimba_gpio_config_svlte,
2343 .bahama_core_config = msm_bahama_core_config,
2344 .fm = &marimba_fm_pdata,
2345 .codec = &mariba_codec_pdata,
2346 .tsadc_ssbi_adap = MARIMBA_SSBI_ADAP,
2347};
2348
2349static void __init msm7x30_init_marimba(void)
2350{
2351 int rc;
2352
2353 vreg_marimba_1 = vreg_get(NULL, "s3");
2354 if (IS_ERR(vreg_marimba_1)) {
2355 printk(KERN_ERR "%s: vreg get failed (%ld)\n",
2356 __func__, PTR_ERR(vreg_marimba_1));
2357 return;
2358 }
2359 rc = vreg_set_level(vreg_marimba_1, 1800);
2360
2361 vreg_marimba_2 = vreg_get(NULL, "gp16");
2362 if (IS_ERR(vreg_marimba_1)) {
2363 printk(KERN_ERR "%s: vreg get failed (%ld)\n",
2364 __func__, PTR_ERR(vreg_marimba_1));
2365 return;
2366 }
2367 rc = vreg_set_level(vreg_marimba_2, 1200);
2368
2369 vreg_marimba_3 = vreg_get(NULL, "usb2");
2370 if (IS_ERR(vreg_marimba_3)) {
2371 printk(KERN_ERR "%s: vreg get failed (%ld)\n",
2372 __func__, PTR_ERR(vreg_marimba_3));
2373 return;
2374 }
2375 rc = vreg_set_level(vreg_marimba_3, 1800);
2376}
2377
2378static struct marimba_codec_platform_data timpani_codec_pdata = {
2379 .marimba_codec_power = msm_marimba_codec_power,
2380#ifdef CONFIG_TIMPANI_CODEC
2381 .snddev_profile_init = msm_snddev_init_timpani,
2382#endif
2383};
2384
2385static struct marimba_platform_data timpani_pdata = {
2386 .slave_id[MARIMBA_SLAVE_ID_CDC] = MARIMBA_SLAVE_ID_CDC_ADDR,
2387 .slave_id[MARIMBA_SLAVE_ID_QMEMBIST] = MARIMBA_SLAVE_ID_QMEMBIST_ADDR,
2388 .marimba_setup = msm_timpani_setup_power,
2389 .marimba_shutdown = msm_timpani_shutdown_power,
2390 .codec = &timpani_codec_pdata,
2391 .tsadc = &marimba_tsadc_pdata,
2392 .tsadc_ssbi_adap = MARIMBA_SSBI_ADAP,
2393};
2394
2395#define TIMPANI_I2C_SLAVE_ADDR 0xD
2396
2397static struct i2c_board_info msm_i2c_gsbi7_timpani_info[] = {
2398 {
2399 I2C_BOARD_INFO("timpani", TIMPANI_I2C_SLAVE_ADDR),
2400 .platform_data = &timpani_pdata,
2401 },
2402};
2403
2404#ifdef CONFIG_MSM7KV2_AUDIO
2405static struct resource msm_aictl_resources[] = {
2406 {
2407 .name = "aictl",
2408 .start = 0xa5000100,
2409 .end = 0xa5000100,
2410 .flags = IORESOURCE_MEM,
2411 }
2412};
2413
2414static struct resource msm_mi2s_resources[] = {
2415 {
2416 .name = "hdmi",
2417 .start = 0xac900000,
2418 .end = 0xac900038,
2419 .flags = IORESOURCE_MEM,
2420 },
2421 {
2422 .name = "codec_rx",
2423 .start = 0xac940040,
2424 .end = 0xac940078,
2425 .flags = IORESOURCE_MEM,
2426 },
2427 {
2428 .name = "codec_tx",
2429 .start = 0xac980080,
2430 .end = 0xac9800B8,
2431 .flags = IORESOURCE_MEM,
2432 }
2433
2434};
2435
2436static struct msm_lpa_platform_data lpa_pdata = {
2437 .obuf_hlb_size = 0x2BFF8,
2438 .dsp_proc_id = 0,
2439 .app_proc_id = 2,
2440 .nosb_config = {
2441 .llb_min_addr = 0,
2442 .llb_max_addr = 0x3ff8,
2443 .sb_min_addr = 0,
2444 .sb_max_addr = 0,
2445 },
2446 .sb_config = {
2447 .llb_min_addr = 0,
2448 .llb_max_addr = 0x37f8,
2449 .sb_min_addr = 0x3800,
2450 .sb_max_addr = 0x3ff8,
2451 }
2452};
2453
2454static struct resource msm_lpa_resources[] = {
2455 {
2456 .name = "lpa",
2457 .start = 0xa5000000,
2458 .end = 0xa50000a0,
2459 .flags = IORESOURCE_MEM,
2460 }
2461};
2462
2463static struct resource msm_aux_pcm_resources[] = {
2464
2465 {
2466 .name = "aux_codec_reg_addr",
2467 .start = 0xac9c00c0,
2468 .end = 0xac9c00c8,
2469 .flags = IORESOURCE_MEM,
2470 },
2471 {
2472 .name = "aux_pcm_dout",
2473 .start = 138,
2474 .end = 138,
2475 .flags = IORESOURCE_IO,
2476 },
2477 {
2478 .name = "aux_pcm_din",
2479 .start = 139,
2480 .end = 139,
2481 .flags = IORESOURCE_IO,
2482 },
2483 {
2484 .name = "aux_pcm_syncout",
2485 .start = 140,
2486 .end = 140,
2487 .flags = IORESOURCE_IO,
2488 },
2489 {
2490 .name = "aux_pcm_clkin_a",
2491 .start = 141,
2492 .end = 141,
2493 .flags = IORESOURCE_IO,
2494 },
2495};
2496
2497static struct platform_device msm_aux_pcm_device = {
2498 .name = "msm_aux_pcm",
2499 .id = 0,
2500 .num_resources = ARRAY_SIZE(msm_aux_pcm_resources),
2501 .resource = msm_aux_pcm_resources,
2502};
2503
2504struct platform_device msm_aictl_device = {
2505 .name = "audio_interct",
2506 .id = 0,
2507 .num_resources = ARRAY_SIZE(msm_aictl_resources),
2508 .resource = msm_aictl_resources,
2509};
2510
2511struct platform_device msm_mi2s_device = {
2512 .name = "mi2s",
2513 .id = 0,
2514 .num_resources = ARRAY_SIZE(msm_mi2s_resources),
2515 .resource = msm_mi2s_resources,
2516};
2517
2518struct platform_device msm_lpa_device = {
2519 .name = "lpa",
2520 .id = 0,
2521 .num_resources = ARRAY_SIZE(msm_lpa_resources),
2522 .resource = msm_lpa_resources,
2523 .dev = {
2524 .platform_data = &lpa_pdata,
2525 },
2526};
2527#endif /* CONFIG_MSM7KV2_AUDIO */
2528
2529#define DEC0_FORMAT ((1<<MSM_ADSP_CODEC_MP3)| \
2530 (1<<MSM_ADSP_CODEC_AAC)|(1<<MSM_ADSP_CODEC_WMA)| \
2531 (1<<MSM_ADSP_CODEC_WMAPRO)|(1<<MSM_ADSP_CODEC_AMRWB)| \
2532 (1<<MSM_ADSP_CODEC_AMRNB)|(1<<MSM_ADSP_CODEC_WAV)| \
2533 (1<<MSM_ADSP_CODEC_ADPCM)|(1<<MSM_ADSP_CODEC_YADPCM)| \
2534 (1<<MSM_ADSP_CODEC_EVRC)|(1<<MSM_ADSP_CODEC_QCELP))
2535#define DEC1_FORMAT ((1<<MSM_ADSP_CODEC_MP3)| \
2536 (1<<MSM_ADSP_CODEC_AAC)|(1<<MSM_ADSP_CODEC_WMA)| \
2537 (1<<MSM_ADSP_CODEC_WMAPRO)|(1<<MSM_ADSP_CODEC_AMRWB)| \
2538 (1<<MSM_ADSP_CODEC_AMRNB)|(1<<MSM_ADSP_CODEC_WAV)| \
2539 (1<<MSM_ADSP_CODEC_ADPCM)|(1<<MSM_ADSP_CODEC_YADPCM)| \
2540 (1<<MSM_ADSP_CODEC_EVRC)|(1<<MSM_ADSP_CODEC_QCELP))
2541 #define DEC2_FORMAT ((1<<MSM_ADSP_CODEC_MP3)| \
2542 (1<<MSM_ADSP_CODEC_AAC)|(1<<MSM_ADSP_CODEC_WMA)| \
2543 (1<<MSM_ADSP_CODEC_WMAPRO)|(1<<MSM_ADSP_CODEC_AMRWB)| \
2544 (1<<MSM_ADSP_CODEC_AMRNB)|(1<<MSM_ADSP_CODEC_WAV)| \
2545 (1<<MSM_ADSP_CODEC_ADPCM)|(1<<MSM_ADSP_CODEC_YADPCM)| \
2546 (1<<MSM_ADSP_CODEC_EVRC)|(1<<MSM_ADSP_CODEC_QCELP))
2547 #define DEC3_FORMAT ((1<<MSM_ADSP_CODEC_MP3)| \
2548 (1<<MSM_ADSP_CODEC_AAC)|(1<<MSM_ADSP_CODEC_WMA)| \
2549 (1<<MSM_ADSP_CODEC_WMAPRO)|(1<<MSM_ADSP_CODEC_AMRWB)| \
2550 (1<<MSM_ADSP_CODEC_AMRNB)|(1<<MSM_ADSP_CODEC_WAV)| \
2551 (1<<MSM_ADSP_CODEC_ADPCM)|(1<<MSM_ADSP_CODEC_YADPCM)| \
2552 (1<<MSM_ADSP_CODEC_EVRC)|(1<<MSM_ADSP_CODEC_QCELP))
2553#define DEC4_FORMAT (1<<MSM_ADSP_CODEC_MIDI)
2554
2555static unsigned int dec_concurrency_table[] = {
2556 /* Audio LP */
2557 0,
2558 (DEC3_FORMAT|(1<<MSM_ADSP_MODE_NONTUNNEL)|(1<<MSM_ADSP_OP_DM)),
2559 (DEC2_FORMAT|(1<<MSM_ADSP_MODE_NONTUNNEL)|(1<<MSM_ADSP_OP_DM)),
2560 (DEC1_FORMAT|(1<<MSM_ADSP_MODE_NONTUNNEL)|(1<<MSM_ADSP_OP_DM)),
2561 (DEC0_FORMAT|(1<<MSM_ADSP_MODE_TUNNEL)|(1<<MSM_ADSP_MODE_LP)|
2562 (1<<MSM_ADSP_OP_DM)),
2563
2564 /* Concurrency 1 */
2565 (DEC4_FORMAT),
2566 (DEC3_FORMAT|(1<<MSM_ADSP_MODE_TUNNEL)|(1<<MSM_ADSP_OP_DM)),
2567 (DEC2_FORMAT|(1<<MSM_ADSP_MODE_TUNNEL)|(1<<MSM_ADSP_OP_DM)),
2568 (DEC1_FORMAT|(1<<MSM_ADSP_MODE_TUNNEL)|(1<<MSM_ADSP_OP_DM)),
2569 (DEC0_FORMAT|(1<<MSM_ADSP_MODE_TUNNEL)|(1<<MSM_ADSP_OP_DM)),
2570
2571 /* Concurrency 2 */
2572 (DEC4_FORMAT),
2573 (DEC3_FORMAT|(1<<MSM_ADSP_MODE_TUNNEL)|(1<<MSM_ADSP_OP_DM)),
2574 (DEC2_FORMAT|(1<<MSM_ADSP_MODE_TUNNEL)|(1<<MSM_ADSP_OP_DM)),
2575 (DEC1_FORMAT|(1<<MSM_ADSP_MODE_TUNNEL)|(1<<MSM_ADSP_OP_DM)),
2576 (DEC0_FORMAT|(1<<MSM_ADSP_MODE_TUNNEL)|(1<<MSM_ADSP_OP_DM)),
2577
2578 /* Concurrency 3 */
2579 (DEC4_FORMAT),
2580 (DEC3_FORMAT|(1<<MSM_ADSP_MODE_TUNNEL)|(1<<MSM_ADSP_OP_DM)),
2581 (DEC2_FORMAT|(1<<MSM_ADSP_MODE_TUNNEL)|(1<<MSM_ADSP_OP_DM)),
2582 (DEC1_FORMAT|(1<<MSM_ADSP_MODE_TUNNEL)|(1<<MSM_ADSP_OP_DM)),
2583 (DEC0_FORMAT|(1<<MSM_ADSP_MODE_NONTUNNEL)|(1<<MSM_ADSP_OP_DM)),
2584
2585 /* Concurrency 4 */
2586 (DEC4_FORMAT),
2587 (DEC3_FORMAT|(1<<MSM_ADSP_MODE_TUNNEL)|(1<<MSM_ADSP_OP_DM)),
2588 (DEC2_FORMAT|(1<<MSM_ADSP_MODE_TUNNEL)|(1<<MSM_ADSP_OP_DM)),
2589 (DEC1_FORMAT|(1<<MSM_ADSP_MODE_NONTUNNEL)|(1<<MSM_ADSP_OP_DM)),
2590 (DEC0_FORMAT|(1<<MSM_ADSP_MODE_NONTUNNEL)|(1<<MSM_ADSP_OP_DM)),
2591
2592 /* Concurrency 5 */
2593 (DEC4_FORMAT),
2594 (DEC3_FORMAT|(1<<MSM_ADSP_MODE_TUNNEL)|(1<<MSM_ADSP_OP_DM)),
2595 (DEC2_FORMAT|(1<<MSM_ADSP_MODE_NONTUNNEL)|(1<<MSM_ADSP_OP_DM)),
2596 (DEC1_FORMAT|(1<<MSM_ADSP_MODE_NONTUNNEL)|(1<<MSM_ADSP_OP_DM)),
2597 (DEC0_FORMAT|(1<<MSM_ADSP_MODE_NONTUNNEL)|(1<<MSM_ADSP_OP_DM)),
2598
2599 /* Concurrency 6 */
2600 (DEC4_FORMAT),
2601 (DEC3_FORMAT|(1<<MSM_ADSP_MODE_NONTUNNEL)|(1<<MSM_ADSP_OP_DM)),
2602 (DEC2_FORMAT|(1<<MSM_ADSP_MODE_NONTUNNEL)|(1<<MSM_ADSP_OP_DM)),
2603 (DEC1_FORMAT|(1<<MSM_ADSP_MODE_NONTUNNEL)|(1<<MSM_ADSP_OP_DM)),
2604 (DEC0_FORMAT|(1<<MSM_ADSP_MODE_NONTUNNEL)|(1<<MSM_ADSP_OP_DM)),
2605};
2606
2607#define DEC_INFO(name, queueid, decid, nr_codec) { .module_name = name, \
2608 .module_queueid = queueid, .module_decid = decid, \
2609 .nr_codec_support = nr_codec}
2610
2611#define DEC_INSTANCE(max_instance_same, max_instance_diff) { \
2612 .max_instances_same_dec = max_instance_same, \
2613 .max_instances_diff_dec = max_instance_diff}
2614
2615static struct msm_adspdec_info dec_info_list[] = {
2616 DEC_INFO("AUDPLAY4TASK", 17, 4, 1), /* AudPlay4BitStreamCtrlQueue */
2617 DEC_INFO("AUDPLAY3TASK", 16, 3, 11), /* AudPlay3BitStreamCtrlQueue */
2618 DEC_INFO("AUDPLAY2TASK", 15, 2, 11), /* AudPlay2BitStreamCtrlQueue */
2619 DEC_INFO("AUDPLAY1TASK", 14, 1, 11), /* AudPlay1BitStreamCtrlQueue */
2620 DEC_INFO("AUDPLAY0TASK", 13, 0, 11), /* AudPlay0BitStreamCtrlQueue */
2621};
2622
2623static struct dec_instance_table dec_instance_list[][MSM_MAX_DEC_CNT] = {
2624 /* Non Turbo Mode */
2625 {
2626 DEC_INSTANCE(4, 3), /* WAV */
2627 DEC_INSTANCE(4, 3), /* ADPCM */
2628 DEC_INSTANCE(4, 2), /* MP3 */
2629 DEC_INSTANCE(0, 0), /* Real Audio */
2630 DEC_INSTANCE(4, 2), /* WMA */
2631 DEC_INSTANCE(3, 2), /* AAC */
2632 DEC_INSTANCE(0, 0), /* Reserved */
2633 DEC_INSTANCE(0, 0), /* MIDI */
2634 DEC_INSTANCE(4, 3), /* YADPCM */
2635 DEC_INSTANCE(4, 3), /* QCELP */
2636 DEC_INSTANCE(4, 3), /* AMRNB */
2637 DEC_INSTANCE(1, 1), /* AMRWB/WB+ */
2638 DEC_INSTANCE(4, 3), /* EVRC */
2639 DEC_INSTANCE(1, 1), /* WMAPRO */
2640 },
2641 /* Turbo Mode */
2642 {
2643 DEC_INSTANCE(4, 3), /* WAV */
2644 DEC_INSTANCE(4, 3), /* ADPCM */
2645 DEC_INSTANCE(4, 3), /* MP3 */
2646 DEC_INSTANCE(0, 0), /* Real Audio */
2647 DEC_INSTANCE(4, 3), /* WMA */
2648 DEC_INSTANCE(4, 3), /* AAC */
2649 DEC_INSTANCE(0, 0), /* Reserved */
2650 DEC_INSTANCE(0, 0), /* MIDI */
2651 DEC_INSTANCE(4, 3), /* YADPCM */
2652 DEC_INSTANCE(4, 3), /* QCELP */
2653 DEC_INSTANCE(4, 3), /* AMRNB */
2654 DEC_INSTANCE(2, 3), /* AMRWB/WB+ */
2655 DEC_INSTANCE(4, 3), /* EVRC */
2656 DEC_INSTANCE(1, 2), /* WMAPRO */
2657 },
2658};
2659
2660static struct msm_adspdec_database msm_device_adspdec_database = {
2661 .num_dec = ARRAY_SIZE(dec_info_list),
2662 .num_concurrency_support = (ARRAY_SIZE(dec_concurrency_table) / \
2663 ARRAY_SIZE(dec_info_list)),
2664 .dec_concurrency_table = dec_concurrency_table,
2665 .dec_info_list = dec_info_list,
2666 .dec_instance_list = &dec_instance_list[0][0],
2667};
2668
2669static struct platform_device msm_device_adspdec = {
2670 .name = "msm_adspdec",
2671 .id = -1,
2672 .dev = {
2673 .platform_data = &msm_device_adspdec_database
2674 },
2675};
2676
2677static struct resource smc91x_resources[] = {
2678 [0] = {
2679 .start = 0x8A000300,
2680 .end = 0x8A0003ff,
2681 .flags = IORESOURCE_MEM,
2682 },
2683 [1] = {
2684 .start = MSM_GPIO_TO_INT(156),
2685 .end = MSM_GPIO_TO_INT(156),
2686 .flags = IORESOURCE_IRQ,
2687 },
2688};
2689
2690static struct platform_device smc91x_device = {
2691 .name = "smc91x",
2692 .id = 0,
2693 .num_resources = ARRAY_SIZE(smc91x_resources),
2694 .resource = smc91x_resources,
2695};
2696
2697static struct smsc911x_platform_config smsc911x_config = {
2698 .phy_interface = PHY_INTERFACE_MODE_MII,
2699 .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
2700 .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL,
2701 .flags = SMSC911X_USE_32BIT,
2702};
2703
2704static struct resource smsc911x_resources[] = {
2705 [0] = {
2706 .start = 0x8D000000,
2707 .end = 0x8D000100,
2708 .flags = IORESOURCE_MEM,
2709 },
2710 [1] = {
2711 .start = MSM_GPIO_TO_INT(88),
2712 .end = MSM_GPIO_TO_INT(88),
2713 .flags = IORESOURCE_IRQ,
2714 },
2715};
2716
2717static struct platform_device smsc911x_device = {
2718 .name = "smsc911x",
2719 .id = -1,
2720 .num_resources = ARRAY_SIZE(smsc911x_resources),
2721 .resource = smsc911x_resources,
2722 .dev = {
2723 .platform_data = &smsc911x_config,
2724 },
2725};
2726
2727static struct msm_gpio smsc911x_gpios[] = {
2728 { GPIO_CFG(172, 2, GPIO_CFG_OUTPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA), "ebi2_addr6" },
2729 { GPIO_CFG(173, 2, GPIO_CFG_OUTPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA), "ebi2_addr5" },
2730 { GPIO_CFG(174, 2, GPIO_CFG_OUTPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA), "ebi2_addr4" },
2731 { GPIO_CFG(175, 2, GPIO_CFG_OUTPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA), "ebi2_addr3" },
2732 { GPIO_CFG(176, 2, GPIO_CFG_OUTPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA), "ebi2_addr2" },
2733 { GPIO_CFG(177, 2, GPIO_CFG_OUTPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA), "ebi2_addr1" },
2734 { GPIO_CFG(178, 2, GPIO_CFG_OUTPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA), "ebi2_addr0" },
2735 { GPIO_CFG(88, 2, GPIO_CFG_INPUT, GPIO_CFG_PULL_UP, GPIO_CFG_2MA), "smsc911x_irq" },
2736};
2737
2738static void msm7x30_cfg_smsc911x(void)
2739{
2740 int rc;
2741
2742 rc = msm_gpios_request_enable(smsc911x_gpios,
2743 ARRAY_SIZE(smsc911x_gpios));
2744 if (rc)
2745 pr_err("%s: unable to enable gpios\n", __func__);
2746}
2747
2748#ifdef CONFIG_USB_G_ANDROID
2749static struct android_usb_platform_data android_usb_pdata = {
2750 .update_pid_and_serial_num = usb_diag_update_pid_and_serial_num,
2751};
2752
2753static struct platform_device android_usb_device = {
2754 .name = "android_usb",
2755 .id = -1,
2756 .dev = {
2757 .platform_data = &android_usb_pdata,
2758 },
2759};
2760#endif
2761
2762static struct msm_gpio optnav_config_data[] = {
2763 { GPIO_CFG(OPTNAV_CHIP_SELECT, 0, GPIO_CFG_OUTPUT, GPIO_CFG_PULL_UP, GPIO_CFG_8MA),
2764 "optnav_chip_select" },
2765};
2766
2767static void __iomem *virtual_optnav;
2768
2769static int optnav_gpio_setup(void)
2770{
2771 int rc = -ENODEV;
2772 rc = msm_gpios_request_enable(optnav_config_data,
2773 ARRAY_SIZE(optnav_config_data));
2774
2775 /* Configure the FPGA for GPIOs */
2776 virtual_optnav = ioremap(FPGA_OPTNAV_GPIO_ADDR, 0x4);
2777 if (!virtual_optnav) {
2778 pr_err("%s:Could not ioremap region\n", __func__);
2779 return -ENOMEM;
2780 }
2781 /*
2782 * Configure the FPGA to set GPIO 19 as
2783 * normal, active(enabled), output(MSM to SURF)
2784 */
2785 writew(0x311E, virtual_optnav);
2786 return rc;
2787}
2788
2789static void optnav_gpio_release(void)
2790{
2791 msm_gpios_disable_free(optnav_config_data,
2792 ARRAY_SIZE(optnav_config_data));
2793 iounmap(virtual_optnav);
2794}
2795
2796static struct vreg *vreg_gp7;
2797static struct vreg *vreg_gp4;
2798static struct vreg *vreg_gp9;
2799static struct vreg *vreg_usb3_3;
2800
2801static int optnav_enable(void)
2802{
2803 int rc;
2804 /*
2805 * Enable the VREGs L8(gp7), L10(gp4), L12(gp9), L6(usb)
2806 * for I2C communication with keyboard.
2807 */
2808 vreg_gp7 = vreg_get(NULL, "gp7");
2809 rc = vreg_set_level(vreg_gp7, 1800);
2810 if (rc) {
2811 pr_err("%s: vreg_set_level failed \n", __func__);
2812 goto fail_vreg_gp7;
2813 }
2814
2815 rc = vreg_enable(vreg_gp7);
2816 if (rc) {
2817 pr_err("%s: vreg_enable failed \n", __func__);
2818 goto fail_vreg_gp7;
2819 }
2820
2821 vreg_gp4 = vreg_get(NULL, "gp4");
2822 rc = vreg_set_level(vreg_gp4, 2600);
2823 if (rc) {
2824 pr_err("%s: vreg_set_level failed \n", __func__);
2825 goto fail_vreg_gp4;
2826 }
2827
2828 rc = vreg_enable(vreg_gp4);
2829 if (rc) {
2830 pr_err("%s: vreg_enable failed \n", __func__);
2831 goto fail_vreg_gp4;
2832 }
2833
2834 vreg_gp9 = vreg_get(NULL, "gp9");
2835 rc = vreg_set_level(vreg_gp9, 1800);
2836 if (rc) {
2837 pr_err("%s: vreg_set_level failed \n", __func__);
2838 goto fail_vreg_gp9;
2839 }
2840
2841 rc = vreg_enable(vreg_gp9);
2842 if (rc) {
2843 pr_err("%s: vreg_enable failed \n", __func__);
2844 goto fail_vreg_gp9;
2845 }
2846
2847 vreg_usb3_3 = vreg_get(NULL, "usb");
2848 rc = vreg_set_level(vreg_usb3_3, 3300);
2849 if (rc) {
2850 pr_err("%s: vreg_set_level failed \n", __func__);
2851 goto fail_vreg_3_3;
2852 }
2853
2854 rc = vreg_enable(vreg_usb3_3);
2855 if (rc) {
2856 pr_err("%s: vreg_enable failed \n", __func__);
2857 goto fail_vreg_3_3;
2858 }
2859
2860 /* Enable the chip select GPIO */
2861 gpio_set_value(OPTNAV_CHIP_SELECT, 1);
2862 gpio_set_value(OPTNAV_CHIP_SELECT, 0);
2863
2864 return 0;
2865
2866fail_vreg_3_3:
2867 vreg_disable(vreg_gp9);
2868fail_vreg_gp9:
2869 vreg_disable(vreg_gp4);
2870fail_vreg_gp4:
2871 vreg_disable(vreg_gp7);
2872fail_vreg_gp7:
2873 return rc;
2874}
2875
2876static void optnav_disable(void)
2877{
2878 vreg_disable(vreg_usb3_3);
2879 vreg_disable(vreg_gp9);
2880 vreg_disable(vreg_gp4);
2881 vreg_disable(vreg_gp7);
2882
2883 gpio_set_value(OPTNAV_CHIP_SELECT, 1);
2884}
2885
2886static struct ofn_atlab_platform_data optnav_data = {
2887 .gpio_setup = optnav_gpio_setup,
2888 .gpio_release = optnav_gpio_release,
2889 .optnav_on = optnav_enable,
2890 .optnav_off = optnav_disable,
2891 .rotate_xy = 0,
2892 .function1 = {
2893 .no_motion1_en = true,
2894 .touch_sensor_en = true,
2895 .ofn_en = true,
2896 .clock_select_khz = 1500,
2897 .cpi_selection = 1200,
2898 },
2899 .function2 = {
2900 .invert_y = false,
2901 .invert_x = true,
2902 .swap_x_y = false,
2903 .hold_a_b_en = true,
2904 .motion_filter_en = true,
2905 },
2906};
2907
2908static int hdmi_comm_power(int on, int show);
2909static int hdmi_init_irq(void);
2910static int hdmi_enable_5v(int on);
2911static int hdmi_core_power(int on, int show);
2912static int hdmi_cec_power(int on);
2913static bool hdmi_check_hdcp_hw_support(void);
2914
2915static struct msm_hdmi_platform_data adv7520_hdmi_data = {
2916 .irq = MSM_GPIO_TO_INT(18),
2917 .comm_power = hdmi_comm_power,
2918 .init_irq = hdmi_init_irq,
2919 .enable_5v = hdmi_enable_5v,
2920 .core_power = hdmi_core_power,
2921 .cec_power = hdmi_cec_power,
2922 .check_hdcp_hw_support = hdmi_check_hdcp_hw_support,
2923};
2924
2925#ifdef CONFIG_BOSCH_BMA150
2926static struct vreg *vreg_gp6;
2927static int sensors_ldo_enable(void)
2928{
2929 int rc;
2930
2931 /*
2932 * Enable the VREGs L8(gp7), L15(gp6)
2933 * for I2C communication with sensors.
2934 */
2935 pr_info("sensors_ldo_enable called!!\n");
2936 vreg_gp7 = vreg_get(NULL, "gp7");
2937 if (IS_ERR(vreg_gp7)) {
2938 pr_err("%s: vreg_get gp7 failed\n", __func__);
2939 rc = PTR_ERR(vreg_gp7);
2940 goto fail_gp7_get;
2941 }
2942
2943 rc = vreg_set_level(vreg_gp7, 1800);
2944 if (rc) {
2945 pr_err("%s: vreg_set_level gp7 failed\n", __func__);
2946 goto fail_gp7_level;
2947 }
2948
2949 rc = vreg_enable(vreg_gp7);
2950 if (rc) {
2951 pr_err("%s: vreg_enable gp7 failed\n", __func__);
2952 goto fail_gp7_level;
2953 }
2954
2955 vreg_gp6 = vreg_get(NULL, "gp6");
2956 if (IS_ERR(vreg_gp6)) {
2957 pr_err("%s: vreg_get gp6 failed\n", __func__);
2958 rc = PTR_ERR(vreg_gp6);
2959 goto fail_gp6_get;
2960 }
2961
2962 rc = vreg_set_level(vreg_gp6, 3050);
2963 if (rc) {
2964 pr_err("%s: vreg_set_level gp6 failed\n", __func__);
2965 goto fail_gp6_level;
2966 }
2967
2968 rc = vreg_enable(vreg_gp6);
2969 if (rc) {
2970 pr_err("%s: vreg_enable gp6 failed\n", __func__);
2971 goto fail_gp6_level;
2972 }
2973
2974 return 0;
2975
2976fail_gp6_level:
2977 vreg_put(vreg_gp6);
2978fail_gp6_get:
2979 vreg_disable(vreg_gp7);
2980fail_gp7_level:
2981 vreg_put(vreg_gp7);
2982fail_gp7_get:
2983 return rc;
2984}
2985
2986static void sensors_ldo_disable(void)
2987{
2988 pr_info("sensors_ldo_disable called!!\n");
2989 vreg_disable(vreg_gp6);
2990 vreg_put(vreg_gp6);
2991 vreg_disable(vreg_gp7);
2992 vreg_put(vreg_gp7);
2993}
2994static struct bma150_platform_data bma150_data = {
2995 .power_on = sensors_ldo_enable,
2996 .power_off = sensors_ldo_disable,
2997};
2998
2999static struct i2c_board_info bma150_board_info[] __initdata = {
3000 {
3001 I2C_BOARD_INFO("bma150", 0x38),
3002 .flags = I2C_CLIENT_WAKE,
3003 .irq = MSM_GPIO_TO_INT(BMA150_GPIO_INT),
3004 .platform_data = &bma150_data,
3005 },
3006};
3007#endif
3008
3009static struct i2c_board_info msm_i2c_board_info[] = {
3010 {
3011 I2C_BOARD_INFO("m33c01", OPTNAV_I2C_SLAVE_ADDR),
3012 .irq = MSM_GPIO_TO_INT(OPTNAV_IRQ),
3013 .platform_data = &optnav_data,
3014 },
3015 {
3016 I2C_BOARD_INFO("adv7520", ADV7520_I2C_ADDR),
3017 .platform_data = &adv7520_hdmi_data,
3018 },
3019};
3020
3021static struct i2c_board_info msm_marimba_board_info[] = {
3022 {
3023 I2C_BOARD_INFO("marimba", 0xc),
3024 .platform_data = &marimba_pdata,
3025 }
3026};
3027
3028
3029static struct msm_handset_platform_data hs_platform_data = {
3030 .hs_name = "7k_handset",
3031 .pwr_key_delay_ms = 500, /* 0 will disable end key */
3032};
3033
3034static struct platform_device hs_device = {
3035 .name = "msm-handset",
3036 .id = -1,
3037 .dev = {
3038 .platform_data = &hs_platform_data,
3039 },
3040};
3041
3042static struct msm_pm_platform_data msm_pm_data[MSM_PM_SLEEP_MODE_NR] = {
3043 [MSM_PM_SLEEP_MODE_POWER_COLLAPSE] = {
3044 .idle_supported = 1,
3045 .suspend_supported = 1,
3046 .idle_enabled = 1,
3047 .suspend_enabled = 1,
3048 .latency = 8594,
3049 .residency = 23740,
3050 },
3051 [MSM_PM_SLEEP_MODE_POWER_COLLAPSE_NO_XO_SHUTDOWN] = {
3052 .idle_supported = 1,
3053 .suspend_supported = 1,
3054 .idle_enabled = 1,
3055 .suspend_enabled = 1,
3056 .latency = 4594,
3057 .residency = 23740,
3058 },
3059 [MSM_PM_SLEEP_MODE_POWER_COLLAPSE_STANDALONE] = {
3060#ifdef CONFIG_MSM_STANDALONE_POWER_COLLAPSE
3061 .idle_supported = 1,
3062 .suspend_supported = 1,
3063 .idle_enabled = 1,
3064 .suspend_enabled = 0,
3065#else /*CONFIG_MSM_STANDALONE_POWER_COLLAPSE*/
3066 .idle_supported = 0,
3067 .suspend_supported = 0,
3068 .idle_enabled = 0,
3069 .suspend_enabled = 0,
3070#endif /*CONFIG_MSM_STANDALONE_POWER_COLLAPSE*/
3071 .latency = 500,
3072 .residency = 6000,
3073 },
3074 [MSM_PM_SLEEP_MODE_RAMP_DOWN_AND_WAIT_FOR_INTERRUPT] = {
3075 .idle_supported = 1,
3076 .suspend_supported = 1,
3077 .idle_enabled = 0,
3078 .suspend_enabled = 1,
3079 .latency = 443,
3080 .residency = 1098,
3081 },
3082 [MSM_PM_SLEEP_MODE_WAIT_FOR_INTERRUPT] = {
3083 .idle_supported = 1,
3084 .suspend_supported = 1,
3085 .idle_enabled = 1,
3086 .suspend_enabled = 1,
3087 .latency = 2,
3088 .residency = 0,
3089 },
3090};
3091
3092static struct resource qsd_spi_resources[] = {
3093 {
3094 .name = "spi_irq_in",
3095 .start = INT_SPI_INPUT,
3096 .end = INT_SPI_INPUT,
3097 .flags = IORESOURCE_IRQ,
3098 },
3099 {
3100 .name = "spi_irq_out",
3101 .start = INT_SPI_OUTPUT,
3102 .end = INT_SPI_OUTPUT,
3103 .flags = IORESOURCE_IRQ,
3104 },
3105 {
3106 .name = "spi_irq_err",
3107 .start = INT_SPI_ERROR,
3108 .end = INT_SPI_ERROR,
3109 .flags = IORESOURCE_IRQ,
3110 },
3111 {
3112 .name = "spi_base",
3113 .start = 0xA8000000,
3114 .end = 0xA8000000 + SZ_4K - 1,
3115 .flags = IORESOURCE_MEM,
3116 },
3117 {
3118 .name = "spidm_channels",
3119 .flags = IORESOURCE_DMA,
3120 },
3121 {
3122 .name = "spidm_crci",
3123 .flags = IORESOURCE_DMA,
3124 },
3125};
3126
3127#define AMDH0_BASE_PHYS 0xAC200000
3128#define ADMH0_GP_CTL (ct_adm_base + 0x3D8)
3129static int msm_qsd_spi_dma_config(void)
3130{
3131 void __iomem *ct_adm_base = 0;
3132 u32 spi_mux = 0;
3133 int ret = 0;
3134
3135 ct_adm_base = ioremap(AMDH0_BASE_PHYS, PAGE_SIZE);
3136 if (!ct_adm_base) {
3137 pr_err("%s: Could not remap %x\n", __func__, AMDH0_BASE_PHYS);
3138 return -ENOMEM;
3139 }
3140
3141 spi_mux = (ioread32(ADMH0_GP_CTL) & (0x3 << 12)) >> 12;
3142
3143 qsd_spi_resources[4].start = DMOV_USB_CHAN;
3144 qsd_spi_resources[4].end = DMOV_TSIF_CHAN;
3145
3146 switch (spi_mux) {
3147 case (1):
3148 qsd_spi_resources[5].start = DMOV_HSUART1_RX_CRCI;
3149 qsd_spi_resources[5].end = DMOV_HSUART1_TX_CRCI;
3150 break;
3151 case (2):
3152 qsd_spi_resources[5].start = DMOV_HSUART2_RX_CRCI;
3153 qsd_spi_resources[5].end = DMOV_HSUART2_TX_CRCI;
3154 break;
3155 case (3):
3156 qsd_spi_resources[5].start = DMOV_CE_OUT_CRCI;
3157 qsd_spi_resources[5].end = DMOV_CE_IN_CRCI;
3158 break;
3159 default:
3160 ret = -ENOENT;
3161 }
3162
3163 iounmap(ct_adm_base);
3164
3165 return ret;
3166}
3167
3168static struct platform_device qsd_device_spi = {
3169 .name = "spi_qsd",
3170 .id = 0,
3171 .num_resources = ARRAY_SIZE(qsd_spi_resources),
3172 .resource = qsd_spi_resources,
3173};
3174
3175#ifdef CONFIG_SPI_QSD
3176static struct spi_board_info lcdc_sharp_spi_board_info[] __initdata = {
3177 {
3178 .modalias = "lcdc_sharp_ls038y7dx01",
3179 .mode = SPI_MODE_1,
3180 .bus_num = 0,
3181 .chip_select = 0,
3182 .max_speed_hz = 26331429,
3183 }
3184};
3185static struct spi_board_info lcdc_toshiba_spi_board_info[] __initdata = {
3186 {
3187 .modalias = "lcdc_toshiba_ltm030dd40",
3188 .mode = SPI_MODE_3|SPI_CS_HIGH,
3189 .bus_num = 0,
3190 .chip_select = 0,
3191 .max_speed_hz = 9963243,
3192 }
3193};
3194#endif
3195
3196static struct msm_gpio qsd_spi_gpio_config_data[] = {
3197 { GPIO_CFG(45, 1, GPIO_CFG_INPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "spi_clk" },
3198 { GPIO_CFG(46, 1, GPIO_CFG_INPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "spi_cs0" },
3199 { GPIO_CFG(47, 1, GPIO_CFG_INPUT, GPIO_CFG_NO_PULL, GPIO_CFG_8MA), "spi_mosi" },
3200 { GPIO_CFG(48, 1, GPIO_CFG_INPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "spi_miso" },
3201};
3202
3203static int msm_qsd_spi_gpio_config(void)
3204{
3205 return msm_gpios_request_enable(qsd_spi_gpio_config_data,
3206 ARRAY_SIZE(qsd_spi_gpio_config_data));
3207}
3208
3209static void msm_qsd_spi_gpio_release(void)
3210{
3211 msm_gpios_disable_free(qsd_spi_gpio_config_data,
3212 ARRAY_SIZE(qsd_spi_gpio_config_data));
3213}
3214
3215static struct msm_spi_platform_data qsd_spi_pdata = {
3216 .max_clock_speed = 26331429,
3217 .gpio_config = msm_qsd_spi_gpio_config,
3218 .gpio_release = msm_qsd_spi_gpio_release,
3219 .dma_config = msm_qsd_spi_dma_config,
3220};
3221
3222static void __init msm_qsd_spi_init(void)
3223{
3224 qsd_device_spi.dev.platform_data = &qsd_spi_pdata;
3225}
3226
3227#ifdef CONFIG_USB_EHCI_MSM_72K
3228static void msm_hsusb_vbus_power(unsigned phy_info, int on)
3229{
3230 int rc;
3231 static int vbus_is_on;
3232 struct pm8058_gpio usb_vbus = {
3233 .direction = PM_GPIO_DIR_OUT,
3234 .pull = PM_GPIO_PULL_NO,
3235 .output_buffer = PM_GPIO_OUT_BUF_CMOS,
3236 .output_value = 1,
3237 .vin_sel = 2,
3238 .out_strength = PM_GPIO_STRENGTH_MED,
3239 .function = PM_GPIO_FUNC_NORMAL,
3240 .inv_int_pol = 0,
3241 };
3242
3243 /* If VBUS is already on (or off), do nothing. */
3244 if (unlikely(on == vbus_is_on))
3245 return;
3246
3247 if (on) {
3248 rc = pm8058_gpio_config(36, &usb_vbus);
3249 if (rc) {
3250 pr_err("%s PMIC GPIO 36 write failed\n", __func__);
3251 return;
3252 }
3253 } else {
3254 gpio_set_value_cansleep(PM8058_GPIO_PM_TO_SYS(36), 0);
3255 }
3256
3257 vbus_is_on = on;
3258}
3259
3260static struct msm_usb_host_platform_data msm_usb_host_pdata = {
3261 .phy_info = (USB_PHY_INTEGRATED | USB_PHY_MODEL_45NM),
3262 .vbus_power = msm_hsusb_vbus_power,
3263 .power_budget = 180,
3264};
3265#endif
3266
3267#ifdef CONFIG_USB_MSM_OTG_72K
3268static int hsusb_rpc_connect(int connect)
3269{
3270 if (connect)
3271 return msm_hsusb_rpc_connect();
3272 else
3273 return msm_hsusb_rpc_close();
3274}
3275#endif
3276
3277#ifdef CONFIG_USB_MSM_OTG_72K
3278static struct vreg *vreg_3p3;
3279static int msm_hsusb_ldo_init(int init)
3280{
3281 uint32_t version = 0;
3282 int def_vol = 3400;
3283
3284 version = socinfo_get_version();
3285
3286 if (SOCINFO_VERSION_MAJOR(version) >= 2 &&
3287 SOCINFO_VERSION_MINOR(version) >= 1) {
3288 def_vol = 3075;
3289 pr_debug("%s: default voltage:%d\n", __func__, def_vol);
3290 }
3291
3292 if (init) {
3293 vreg_3p3 = vreg_get(NULL, "usb");
3294 if (IS_ERR(vreg_3p3))
3295 return PTR_ERR(vreg_3p3);
3296 vreg_set_level(vreg_3p3, def_vol);
3297 } else
3298 vreg_put(vreg_3p3);
3299
3300 return 0;
3301}
3302
3303static int msm_hsusb_ldo_enable(int enable)
3304{
3305 static int ldo_status;
3306
3307 if (!vreg_3p3 || IS_ERR(vreg_3p3))
3308 return -ENODEV;
3309
3310 if (ldo_status == enable)
3311 return 0;
3312
3313 ldo_status = enable;
3314
3315 if (enable)
3316 return vreg_enable(vreg_3p3);
3317
3318 return vreg_disable(vreg_3p3);
3319}
3320
3321static int msm_hsusb_ldo_set_voltage(int mV)
3322{
3323 static int cur_voltage = 3400;
3324
3325 if (!vreg_3p3 || IS_ERR(vreg_3p3))
3326 return -ENODEV;
3327
3328 if (cur_voltage == mV)
3329 return 0;
3330
3331 cur_voltage = mV;
3332
3333 pr_debug("%s: (%d)\n", __func__, mV);
3334
3335 return vreg_set_level(vreg_3p3, mV);
3336}
3337#endif
3338
3339#ifndef CONFIG_USB_EHCI_MSM_72K
3340static int msm_hsusb_pmic_notif_init(void (*callback)(int online), int init);
3341#endif
3342static struct msm_otg_platform_data msm_otg_pdata = {
3343 .rpc_connect = hsusb_rpc_connect,
3344
3345#ifndef CONFIG_USB_EHCI_MSM_72K
3346 .pmic_vbus_notif_init = msm_hsusb_pmic_notif_init,
3347#else
3348 .vbus_power = msm_hsusb_vbus_power,
3349#endif
3350 .core_clk = 1,
3351 .pemp_level = PRE_EMPHASIS_WITH_20_PERCENT,
3352 .cdr_autoreset = CDR_AUTO_RESET_DISABLE,
3353 .drv_ampl = HS_DRV_AMPLITUDE_DEFAULT,
3354 .se1_gating = SE1_GATING_DISABLE,
3355 .chg_vbus_draw = hsusb_chg_vbus_draw,
3356 .chg_connected = hsusb_chg_connected,
3357 .chg_init = hsusb_chg_init,
3358 .ldo_enable = msm_hsusb_ldo_enable,
3359 .ldo_init = msm_hsusb_ldo_init,
3360 .ldo_set_voltage = msm_hsusb_ldo_set_voltage,
3361};
3362
3363#ifdef CONFIG_USB_GADGET
3364static struct msm_hsusb_gadget_platform_data msm_gadget_pdata = {
3365 .is_phy_status_timer_on = 1,
3366};
3367#endif
3368#ifndef CONFIG_USB_EHCI_MSM_72K
3369typedef void (*notify_vbus_state) (int);
3370notify_vbus_state notify_vbus_state_func_ptr;
3371int vbus_on_irq;
3372static irqreturn_t pmic_vbus_on_irq(int irq, void *data)
3373{
3374 pr_info("%s: vbus notification from pmic\n", __func__);
3375
3376 (*notify_vbus_state_func_ptr) (1);
3377
3378 return IRQ_HANDLED;
3379}
3380static int msm_hsusb_pmic_notif_init(void (*callback)(int online), int init)
3381{
3382 int ret;
3383
3384 if (init) {
3385 if (!callback)
3386 return -ENODEV;
3387
3388 notify_vbus_state_func_ptr = callback;
3389 vbus_on_irq = platform_get_irq_byname(&msm_device_otg,
3390 "vbus_on");
3391 if (vbus_on_irq <= 0) {
3392 pr_err("%s: unable to get vbus on irq\n", __func__);
3393 return -ENODEV;
3394 }
3395
3396 ret = request_any_context_irq(vbus_on_irq, pmic_vbus_on_irq,
3397 IRQF_TRIGGER_RISING, "msm_otg_vbus_on", NULL);
3398 if (ret < 0) {
3399 pr_info("%s: request_irq for vbus_on"
3400 "interrupt failed\n", __func__);
3401 return ret;
3402 }
3403 msm_otg_pdata.pmic_vbus_irq = vbus_on_irq;
3404 return 0;
3405 } else {
3406 free_irq(vbus_on_irq, 0);
3407 notify_vbus_state_func_ptr = NULL;
3408 return 0;
3409 }
3410}
3411#endif
3412
3413static struct android_pmem_platform_data android_pmem_pdata = {
3414 .name = "pmem",
3415 .allocator_type = PMEM_ALLOCATORTYPE_ALLORNOTHING,
3416 .cached = 1,
3417 .memory_type = MEMTYPE_EBI0,
3418};
3419
3420static struct platform_device android_pmem_device = {
3421 .name = "android_pmem",
3422 .id = 0,
3423 .dev = { .platform_data = &android_pmem_pdata },
3424};
3425
3426#ifndef CONFIG_SPI_QSD
3427static int lcdc_gpio_array_num[] = {
3428 45, /* spi_clk */
3429 46, /* spi_cs */
3430 47, /* spi_mosi */
3431 48, /* spi_miso */
3432 };
3433
3434static struct msm_gpio lcdc_gpio_config_data[] = {
3435 { GPIO_CFG(45, 0, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "spi_clk" },
3436 { GPIO_CFG(46, 0, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "spi_cs0" },
3437 { GPIO_CFG(47, 0, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "spi_mosi" },
3438 { GPIO_CFG(48, 0, GPIO_CFG_INPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "spi_miso" },
3439};
3440
3441static void lcdc_config_gpios(int enable)
3442{
3443 if (enable) {
3444 msm_gpios_request_enable(lcdc_gpio_config_data,
3445 ARRAY_SIZE(
3446 lcdc_gpio_config_data));
3447 } else
3448 msm_gpios_disable_free(lcdc_gpio_config_data,
3449 ARRAY_SIZE(
3450 lcdc_gpio_config_data));
3451}
3452#endif
3453
3454static struct msm_panel_common_pdata lcdc_sharp_panel_data = {
3455#ifndef CONFIG_SPI_QSD
3456 .panel_config_gpio = lcdc_config_gpios,
3457 .gpio_num = lcdc_gpio_array_num,
3458#endif
3459 .gpio = 2, /* LPG PMIC_GPIO26 channel number */
3460};
3461
3462static struct platform_device lcdc_sharp_panel_device = {
3463 .name = "lcdc_sharp_wvga",
3464 .id = 0,
3465 .dev = {
3466 .platform_data = &lcdc_sharp_panel_data,
3467 }
3468};
3469
3470static struct msm_gpio dtv_panel_irq_gpios[] = {
3471 { GPIO_CFG(18, 0, GPIO_CFG_INPUT, GPIO_CFG_NO_PULL, GPIO_CFG_4MA),
3472 "hdmi_int" },
3473};
3474
3475static struct msm_gpio dtv_panel_gpios[] = {
3476 { GPIO_CFG(120, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_4MA), "wca_mclk" },
3477 { GPIO_CFG(121, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_4MA), "wca_sd0" },
3478 { GPIO_CFG(122, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_4MA), "wca_sd1" },
3479 { GPIO_CFG(123, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_4MA), "wca_sd2" },
3480 { GPIO_CFG(124, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_8MA), "dtv_pclk" },
3481 { GPIO_CFG(125, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_4MA), "dtv_en" },
3482 { GPIO_CFG(126, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_4MA), "dtv_vsync" },
3483 { GPIO_CFG(127, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_4MA), "dtv_hsync" },
3484 { GPIO_CFG(128, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_4MA), "dtv_data0" },
3485 { GPIO_CFG(129, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_4MA), "dtv_data1" },
3486 { GPIO_CFG(130, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_4MA), "dtv_data2" },
3487 { GPIO_CFG(131, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_4MA), "dtv_data3" },
3488 { GPIO_CFG(132, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_4MA), "dtv_data4" },
3489 { GPIO_CFG(160, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_4MA), "dtv_data5" },
3490 { GPIO_CFG(161, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_4MA), "dtv_data6" },
3491 { GPIO_CFG(162, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_4MA), "dtv_data7" },
3492 { GPIO_CFG(163, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_4MA), "dtv_data8" },
3493 { GPIO_CFG(164, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_4MA), "dtv_data9" },
3494 { GPIO_CFG(165, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_4MA), "dtv_dat10" },
3495 { GPIO_CFG(166, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_4MA), "dtv_dat11" },
3496 { GPIO_CFG(167, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_4MA), "dtv_dat12" },
3497 { GPIO_CFG(168, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_4MA), "dtv_dat13" },
3498 { GPIO_CFG(169, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_4MA), "dtv_dat14" },
3499 { GPIO_CFG(170, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_4MA), "dtv_dat15" },
3500 { GPIO_CFG(171, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_4MA), "dtv_dat16" },
3501 { GPIO_CFG(172, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_4MA), "dtv_dat17" },
3502 { GPIO_CFG(173, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_4MA), "dtv_dat18" },
3503 { GPIO_CFG(174, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_4MA), "dtv_dat19" },
3504 { GPIO_CFG(175, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_4MA), "dtv_dat20" },
3505 { GPIO_CFG(176, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_4MA), "dtv_dat21" },
3506 { GPIO_CFG(177, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_4MA), "dtv_dat22" },
3507 { GPIO_CFG(178, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_4MA), "dtv_dat23" },
3508};
3509
3510
3511#ifdef HDMI_RESET
3512static unsigned dtv_reset_gpio =
3513 GPIO_CFG(37, 0, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA);
3514#endif
3515
3516static int gpio_set(const char *label, const char *name, int level, int on)
3517{
3518 struct vreg *vreg = vreg_get(NULL, label);
3519 int rc;
3520
3521 if (IS_ERR(vreg)) {
3522 rc = PTR_ERR(vreg);
3523 pr_err("%s: vreg %s get failed (%d)\n",
3524 __func__, name, rc);
3525 return rc;
3526 }
3527
3528 rc = vreg_set_level(vreg, level);
3529 if (rc) {
3530 pr_err("%s: vreg %s set level failed (%d)\n",
3531 __func__, name, rc);
3532 return rc;
3533 }
3534
3535 if (on)
3536 rc = vreg_enable(vreg);
3537 else
3538 rc = vreg_disable(vreg);
3539 if (rc)
3540 pr_err("%s: vreg %s enable failed (%d)\n",
3541 __func__, name, rc);
3542 return rc;
3543}
3544
3545#if defined(CONFIG_FB_MSM_HDMI_ADV7520_PANEL) || defined(CONFIG_BOSCH_BMA150)
3546/* there is an i2c address conflict between adv7520 and bma150 sensor after
3547 * power up on fluid. As a solution, the default address of adv7520's packet
3548 * memory is changed as soon as possible
3549 */
3550static int __init fluid_i2c_address_fixup(void)
3551{
3552 unsigned char wBuff[16];
3553 unsigned char rBuff[16];
3554 struct i2c_msg msgs[3];
3555 int res;
3556 int rc = -EINVAL;
3557 struct vreg *vreg_ldo8;
3558 struct i2c_adapter *adapter;
3559
3560 if (machine_is_msm7x30_fluid()) {
3561 adapter = i2c_get_adapter(0);
3562 if (!adapter) {
3563 pr_err("%s: invalid i2c adapter\n", __func__);
3564 return PTR_ERR(adapter);
3565 }
3566
3567 /* turn on LDO8 */
3568 vreg_ldo8 = vreg_get(NULL, "gp7");
3569 if (!vreg_ldo8) {
3570 pr_err("%s: VREG L8 get failed\n", __func__);
3571 goto adapter_put;
3572 }
3573
3574 rc = vreg_set_level(vreg_ldo8, 1800);
3575 if (rc) {
3576 pr_err("%s: VREG L8 set failed\n", __func__);
3577 goto ldo8_put;
3578 }
3579
3580 rc = vreg_enable(vreg_ldo8);
3581 if (rc) {
3582 pr_err("%s: VREG L8 enable failed\n", __func__);
3583 goto ldo8_put;
3584 }
3585
3586 /* change packet memory address to 0x74 */
3587 wBuff[0] = 0x45;
3588 wBuff[1] = 0x74;
3589
3590 msgs[0].addr = ADV7520_I2C_ADDR;
3591 msgs[0].flags = 0;
3592 msgs[0].buf = (unsigned char *) wBuff;
3593 msgs[0].len = 2;
3594
3595 res = i2c_transfer(adapter, msgs, 1);
3596 if (res != 1) {
3597 pr_err("%s: error writing adv7520\n", __func__);
3598 goto ldo8_disable;
3599 }
3600
3601 /* powerdown adv7520 using bit 6 */
3602 /* i2c read first */
3603 wBuff[0] = 0x41;
3604
3605 msgs[0].addr = ADV7520_I2C_ADDR;
3606 msgs[0].flags = 0;
3607 msgs[0].buf = (unsigned char *) wBuff;
3608 msgs[0].len = 1;
3609
3610 msgs[1].addr = ADV7520_I2C_ADDR;
3611 msgs[1].flags = I2C_M_RD;
3612 msgs[1].buf = rBuff;
3613 msgs[1].len = 1;
3614 res = i2c_transfer(adapter, msgs, 2);
3615 if (res != 2) {
3616 pr_err("%s: error reading adv7520\n", __func__);
3617 goto ldo8_disable;
3618 }
3619
3620 /* i2c write back */
3621 wBuff[0] = 0x41;
3622 wBuff[1] = rBuff[0] | 0x40;
3623
3624 msgs[0].addr = ADV7520_I2C_ADDR;
3625 msgs[0].flags = 0;
3626 msgs[0].buf = (unsigned char *) wBuff;
3627 msgs[0].len = 2;
3628
3629 res = i2c_transfer(adapter, msgs, 1);
3630 if (res != 1) {
3631 pr_err("%s: error writing adv7520\n", __func__);
3632 goto ldo8_disable;
3633 }
3634
3635 /* for successful fixup, we release the i2c adapter */
3636 /* but leave ldo8 on so that the adv7520 is not repowered */
3637 i2c_put_adapter(adapter);
3638 pr_info("%s: fluid i2c address conflict resolved\n", __func__);
3639 }
3640 return 0;
3641
3642ldo8_disable:
3643 vreg_disable(vreg_ldo8);
3644ldo8_put:
3645 vreg_put(vreg_ldo8);
3646adapter_put:
3647 i2c_put_adapter(adapter);
3648 return rc;
3649}
3650fs_initcall_sync(fluid_i2c_address_fixup);
3651#endif
3652
3653static int hdmi_comm_power(int on, int show)
3654{
3655 int rc = gpio_set("gp7", "LDO8", 1800, on);
3656 if (rc) {
3657 pr_warning("hdmi_comm_power: LDO8 gpio failed: rc=%d\n", rc);
3658 return rc;
3659 }
3660 rc = gpio_set("gp4", "LDO10", 2600, on);
3661 if (rc)
3662 pr_warning("hdmi_comm_power: LDO10 gpio failed: rc=%d\n", rc);
3663 if (show)
3664 pr_info("%s: i2c comm: %d <LDO8+LDO10>\n", __func__, on);
3665 return rc;
3666}
3667
3668static int hdmi_init_irq(void)
3669{
3670 int rc = msm_gpios_enable(dtv_panel_irq_gpios,
3671 ARRAY_SIZE(dtv_panel_irq_gpios));
3672 if (rc < 0) {
3673 pr_err("%s: gpio enable failed: %d\n", __func__, rc);
3674 return rc;
3675 }
3676 pr_info("%s\n", __func__);
3677
3678 return 0;
3679}
3680
3681static int hdmi_enable_5v(int on)
3682{
3683 int pmic_gpio_hdmi_5v_en ;
3684
3685 if (machine_is_msm8x55_svlte_surf() || machine_is_msm8x55_svlte_ffa() ||
3686 machine_is_msm7x30_fluid())
3687 pmic_gpio_hdmi_5v_en = PMIC_GPIO_HDMI_5V_EN_V2 ;
3688 else
3689 pmic_gpio_hdmi_5v_en = PMIC_GPIO_HDMI_5V_EN_V3 ;
3690
3691 pr_info("%s: %d\n", __func__, on);
3692 if (on) {
3693 int rc;
3694 rc = gpio_request(PM8058_GPIO_PM_TO_SYS(pmic_gpio_hdmi_5v_en),
3695 "hdmi_5V_en");
3696 if (rc) {
3697 pr_err("%s PMIC_GPIO_HDMI_5V_EN gpio_request failed\n",
3698 __func__);
3699 return rc;
3700 }
3701 gpio_set_value_cansleep(
3702 PM8058_GPIO_PM_TO_SYS(pmic_gpio_hdmi_5v_en), 1);
3703 } else {
3704 gpio_set_value_cansleep(
3705 PM8058_GPIO_PM_TO_SYS(pmic_gpio_hdmi_5v_en), 0);
3706 gpio_free(PM8058_GPIO_PM_TO_SYS(pmic_gpio_hdmi_5v_en));
3707 }
3708 return 0;
3709}
3710
3711static int hdmi_core_power(int on, int show)
3712{
3713 if (show)
3714 pr_info("%s: %d <LDO8>\n", __func__, on);
3715 return gpio_set("gp7", "LDO8", 1800, on);
3716}
3717
3718static int hdmi_cec_power(int on)
3719{
3720 pr_info("%s: %d <LDO17>\n", __func__, on);
3721 return gpio_set("gp11", "LDO17", 2600, on);
3722}
3723
3724static bool hdmi_check_hdcp_hw_support(void)
3725{
3726 if (machine_is_msm7x30_fluid())
3727 return false;
3728 else
3729 return true;
3730}
3731
3732static int dtv_panel_power(int on)
3733{
3734 int flag_on = !!on;
3735 static int dtv_power_save_on;
3736 int rc;
3737
3738 if (dtv_power_save_on == flag_on)
3739 return 0;
3740
3741 dtv_power_save_on = flag_on;
3742 pr_info("%s: %d\n", __func__, on);
3743
3744#ifdef HDMI_RESET
3745 if (on) {
3746 /* reset Toshiba WeGA chip -- toggle reset pin -- gpio_180 */
3747 rc = gpio_tlmm_config(dtv_reset_gpio, GPIO_CFG_ENABLE);
3748 if (rc) {
3749 pr_err("%s: gpio_tlmm_config(%#x)=%d\n",
3750 __func__, dtv_reset_gpio, rc);
3751 return rc;
3752 }
3753
3754 /* bring reset line low to hold reset*/
3755 gpio_set_value(37, 0);
3756 }
3757#endif
3758
3759 if (on) {
3760 rc = msm_gpios_enable(dtv_panel_gpios,
3761 ARRAY_SIZE(dtv_panel_gpios));
3762 if (rc < 0) {
3763 printk(KERN_ERR "%s: gpio enable failed: %d\n",
3764 __func__, rc);
3765 return rc;
3766 }
3767 } else {
3768 rc = msm_gpios_disable(dtv_panel_gpios,
3769 ARRAY_SIZE(dtv_panel_gpios));
3770 if (rc < 0) {
3771 printk(KERN_ERR "%s: gpio disable failed: %d\n",
3772 __func__, rc);
3773 return rc;
3774 }
3775 }
3776
3777 mdelay(5); /* ensure power is stable */
3778
3779#ifdef HDMI_RESET
3780 if (on) {
3781 gpio_set_value(37, 1); /* bring reset line high */
3782 mdelay(10); /* 10 msec before IO can be accessed */
3783 }
3784#endif
3785
3786 return rc;
3787}
3788
3789static struct lcdc_platform_data dtv_pdata = {
3790 .lcdc_power_save = dtv_panel_power,
3791};
3792
3793static struct msm_serial_hs_platform_data msm_uart_dm1_pdata = {
3794 .inject_rx_on_wakeup = 1,
3795 .rx_to_inject = 0xFD,
3796};
3797
3798static struct resource msm_fb_resources[] = {
3799 {
3800 .flags = IORESOURCE_DMA,
3801 }
3802};
3803
3804static int msm_fb_detect_panel(const char *name)
3805{
3806 if (machine_is_msm7x30_fluid()) {
3807 if (!strcmp(name, "lcdc_sharp_wvga_pt"))
3808 return 0;
3809 } else {
3810 if (!strncmp(name, "mddi_toshiba_wvga_pt", 20))
3811 return -EPERM;
3812 else if (!strncmp(name, "lcdc_toshiba_wvga_pt", 20))
3813 return 0;
3814 else if (!strcmp(name, "mddi_orise"))
3815 return -EPERM;
3816 else if (!strcmp(name, "mddi_quickvx"))
3817 return -EPERM;
3818 }
3819 return -ENODEV;
3820}
3821
3822static struct msm_fb_platform_data msm_fb_pdata = {
3823 .detect_client = msm_fb_detect_panel,
3824 .mddi_prescan = 1,
3825};
3826
3827static struct platform_device msm_fb_device = {
3828 .name = "msm_fb",
3829 .id = 0,
3830 .num_resources = ARRAY_SIZE(msm_fb_resources),
3831 .resource = msm_fb_resources,
3832 .dev = {
3833 .platform_data = &msm_fb_pdata,
3834 }
3835};
3836
3837static struct platform_device msm_migrate_pages_device = {
3838 .name = "msm_migrate_pages",
3839 .id = -1,
3840};
3841
3842static struct android_pmem_platform_data android_pmem_adsp_pdata = {
3843 .name = "pmem_adsp",
3844 .allocator_type = PMEM_ALLOCATORTYPE_BITMAP,
3845 .cached = 0,
3846 .memory_type = MEMTYPE_EBI0,
3847};
3848
3849static struct android_pmem_platform_data android_pmem_audio_pdata = {
3850 .name = "pmem_audio",
3851 .allocator_type = PMEM_ALLOCATORTYPE_BITMAP,
3852 .cached = 0,
3853 .memory_type = MEMTYPE_EBI0,
3854};
3855
3856static struct platform_device android_pmem_adsp_device = {
3857 .name = "android_pmem",
3858 .id = 2,
3859 .dev = { .platform_data = &android_pmem_adsp_pdata },
3860};
3861
3862static struct platform_device android_pmem_audio_device = {
3863 .name = "android_pmem",
3864 .id = 4,
3865 .dev = { .platform_data = &android_pmem_audio_pdata },
3866};
3867
3868#if defined(CONFIG_CRYPTO_DEV_QCRYPTO) || \
3869 defined(CONFIG_CRYPTO_DEV_QCRYPTO_MODULE) || \
3870 defined(CONFIG_CRYPTO_DEV_QCEDEV) || \
3871 defined(CONFIG_CRYPTO_DEV_QCEDEV_MODULE)
3872
3873#define QCE_SIZE 0x10000
3874#define QCE_0_BASE 0xA8400000
3875
3876#define QCE_HW_KEY_SUPPORT 1
3877#define QCE_SHA_HMAC_SUPPORT 0
3878#define QCE_SHARE_CE_RESOURCE 0
3879#define QCE_CE_SHARED 0
3880
3881static struct resource qcrypto_resources[] = {
3882 [0] = {
3883 .start = QCE_0_BASE,
3884 .end = QCE_0_BASE + QCE_SIZE - 1,
3885 .flags = IORESOURCE_MEM,
3886 },
3887 [1] = {
3888 .name = "crypto_channels",
3889 .start = DMOV_CE_IN_CHAN,
3890 .end = DMOV_CE_OUT_CHAN,
3891 .flags = IORESOURCE_DMA,
3892 },
3893 [2] = {
3894 .name = "crypto_crci_in",
3895 .start = DMOV_CE_IN_CRCI,
3896 .end = DMOV_CE_IN_CRCI,
3897 .flags = IORESOURCE_DMA,
3898 },
3899 [3] = {
3900 .name = "crypto_crci_out",
3901 .start = DMOV_CE_OUT_CRCI,
3902 .end = DMOV_CE_OUT_CRCI,
3903 .flags = IORESOURCE_DMA,
3904 },
3905 [4] = {
3906 .name = "crypto_crci_hash",
3907 .start = DMOV_CE_HASH_CRCI,
3908 .end = DMOV_CE_HASH_CRCI,
3909 .flags = IORESOURCE_DMA,
3910 },
3911};
3912
3913static struct resource qcedev_resources[] = {
3914 [0] = {
3915 .start = QCE_0_BASE,
3916 .end = QCE_0_BASE + QCE_SIZE - 1,
3917 .flags = IORESOURCE_MEM,
3918 },
3919 [1] = {
3920 .name = "crypto_channels",
3921 .start = DMOV_CE_IN_CHAN,
3922 .end = DMOV_CE_OUT_CHAN,
3923 .flags = IORESOURCE_DMA,
3924 },
3925 [2] = {
3926 .name = "crypto_crci_in",
3927 .start = DMOV_CE_IN_CRCI,
3928 .end = DMOV_CE_IN_CRCI,
3929 .flags = IORESOURCE_DMA,
3930 },
3931 [3] = {
3932 .name = "crypto_crci_out",
3933 .start = DMOV_CE_OUT_CRCI,
3934 .end = DMOV_CE_OUT_CRCI,
3935 .flags = IORESOURCE_DMA,
3936 },
3937 [4] = {
3938 .name = "crypto_crci_hash",
3939 .start = DMOV_CE_HASH_CRCI,
3940 .end = DMOV_CE_HASH_CRCI,
3941 .flags = IORESOURCE_DMA,
3942 },
3943};
3944
3945#endif
3946
3947#if defined(CONFIG_CRYPTO_DEV_QCRYPTO) || \
3948 defined(CONFIG_CRYPTO_DEV_QCRYPTO_MODULE)
3949
3950static struct msm_ce_hw_support qcrypto_ce_hw_suppport = {
3951 .ce_shared = QCE_CE_SHARED,
3952 .shared_ce_resource = QCE_SHARE_CE_RESOURCE,
3953 .hw_key_support = QCE_HW_KEY_SUPPORT,
3954 .sha_hmac = QCE_SHA_HMAC_SUPPORT,
3955};
3956
3957static struct platform_device qcrypto_device = {
3958 .name = "qcrypto",
3959 .id = 0,
3960 .num_resources = ARRAY_SIZE(qcrypto_resources),
3961 .resource = qcrypto_resources,
3962 .dev = {
3963 .coherent_dma_mask = DMA_BIT_MASK(32),
3964 .platform_data = &qcrypto_ce_hw_suppport,
3965 },
3966};
3967#endif
3968
3969#if defined(CONFIG_CRYPTO_DEV_QCEDEV) || \
3970 defined(CONFIG_CRYPTO_DEV_QCEDEV_MODULE)
3971
3972static struct msm_ce_hw_support qcedev_ce_hw_suppport = {
3973 .ce_shared = QCE_CE_SHARED,
3974 .shared_ce_resource = QCE_SHARE_CE_RESOURCE,
3975 .hw_key_support = QCE_HW_KEY_SUPPORT,
3976 .sha_hmac = QCE_SHA_HMAC_SUPPORT,
3977};
3978static struct platform_device qcedev_device = {
3979 .name = "qce",
3980 .id = 0,
3981 .num_resources = ARRAY_SIZE(qcedev_resources),
3982 .resource = qcedev_resources,
3983 .dev = {
3984 .coherent_dma_mask = DMA_BIT_MASK(32),
3985 .platform_data = &qcedev_ce_hw_suppport,
3986 },
3987};
3988#endif
3989
3990static int mddi_toshiba_pmic_bl(int level)
3991{
3992 int ret = -EPERM;
3993
3994 ret = pmic_set_led_intensity(LED_LCD, level);
3995
3996 if (ret)
3997 printk(KERN_WARNING "%s: can't set lcd backlight!\n",
3998 __func__);
3999 return ret;
4000}
4001
4002static struct msm_panel_common_pdata mddi_toshiba_pdata = {
4003 .pmic_backlight = mddi_toshiba_pmic_bl,
4004};
4005
4006static struct platform_device mddi_toshiba_device = {
4007 .name = "mddi_toshiba",
4008 .id = 0,
4009 .dev = {
4010 .platform_data = &mddi_toshiba_pdata,
4011 }
4012};
4013
4014static unsigned wega_reset_gpio =
4015 GPIO_CFG(180, 0, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA);
4016
4017static struct msm_gpio fluid_vee_reset_gpio[] = {
4018 { GPIO_CFG(20, 0, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "vee_reset" },
4019};
4020
4021static unsigned char quickvx_mddi_client = 1, other_mddi_client = 1;
4022static unsigned char quickvx_ldo_enabled;
4023
4024static unsigned quickvx_vlp_gpio =
4025 GPIO_CFG(97, 0, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA);
4026
4027static struct pm8058_gpio pmic_quickvx_clk_gpio = {
4028 .direction = PM_GPIO_DIR_OUT,
4029 .output_buffer = PM_GPIO_OUT_BUF_CMOS,
4030 .output_value = 1,
4031 .pull = PM_GPIO_PULL_NO,
4032 .vin_sel = PM_GPIO_VIN_S3,
4033 .out_strength = PM_GPIO_STRENGTH_HIGH,
4034 .function = PM_GPIO_FUNC_2,
4035};
4036
4037static int display_common_power(int on)
4038{
4039 int rc = 0, flag_on = !!on;
4040 static int display_common_power_save_on;
4041 struct vreg *vreg_ldo12, *vreg_ldo15 = NULL, *vreg_ldo6;
4042 struct vreg *vreg_ldo20, *vreg_ldo16, *vreg_ldo8 = NULL;
4043
4044 if (display_common_power_save_on == flag_on)
4045 return 0;
4046
4047 display_common_power_save_on = flag_on;
4048
4049 if (on) {
4050 /* reset Toshiba WeGA chip -- toggle reset pin -- gpio_180 */
4051 rc = gpio_tlmm_config(wega_reset_gpio, GPIO_CFG_ENABLE);
4052 if (rc) {
4053 pr_err("%s: gpio_tlmm_config(%#x)=%d\n",
4054 __func__, wega_reset_gpio, rc);
4055 return rc;
4056 }
4057
4058 /* bring reset line low to hold reset*/
4059 gpio_set_value(180, 0);
4060
4061 if (quickvx_mddi_client) {
4062 /* QuickVX chip -- VLP pin -- gpio 97 */
4063 rc = gpio_tlmm_config(quickvx_vlp_gpio,
4064 GPIO_CFG_ENABLE);
4065 if (rc) {
4066 pr_err("%s: gpio_tlmm_config(%#x)=%d\n",
4067 __func__, quickvx_vlp_gpio, rc);
4068 return rc;
4069 }
4070
4071 /* bring QuickVX VLP line low */
4072 gpio_set_value(97, 0);
4073
4074 rc = pm8058_gpio_config(PMIC_GPIO_QUICKVX_CLK,
4075 &pmic_quickvx_clk_gpio);
4076 if (rc) {
4077 pr_err("%s: pm8058_gpio_config(%#x)=%d\n",
4078 __func__, PMIC_GPIO_QUICKVX_CLK + 1,
4079 rc);
4080 return rc;
4081 }
4082
4083 gpio_set_value_cansleep(PM8058_GPIO_PM_TO_SYS(
4084 PMIC_GPIO_QUICKVX_CLK), 0);
4085 }
4086 }
4087
4088 /* Toshiba WeGA power -- has 3 power source */
4089 /* 1.5V -- LDO20*/
4090 vreg_ldo20 = vreg_get(NULL, "gp13");
4091
4092 if (IS_ERR(vreg_ldo20)) {
4093 rc = PTR_ERR(vreg_ldo20);
4094 pr_err("%s: gp13 vreg get failed (%d)\n",
4095 __func__, rc);
4096 return rc;
4097 }
4098
4099 /* 1.8V -- LDO12 */
4100 vreg_ldo12 = vreg_get(NULL, "gp9");
4101
4102 if (IS_ERR(vreg_ldo12)) {
4103 rc = PTR_ERR(vreg_ldo12);
4104 pr_err("%s: gp9 vreg get failed (%d)\n",
4105 __func__, rc);
4106 return rc;
4107 }
4108
4109 /* 2.6V -- LDO16 */
4110 vreg_ldo16 = vreg_get(NULL, "gp10");
4111
4112 if (IS_ERR(vreg_ldo16)) {
4113 rc = PTR_ERR(vreg_ldo16);
4114 pr_err("%s: gp10 vreg get failed (%d)\n",
4115 __func__, rc);
4116 return rc;
4117 }
4118
4119 /* 3.075V -- LDO6 */
4120 vreg_ldo6 = vreg_get(NULL, "usb");
4121
4122 if (IS_ERR(vreg_ldo6)) {
4123 rc = PTR_ERR(vreg_ldo6);
4124 pr_err("%s: usb vreg get failed (%d)\n",
4125 __func__, rc);
4126 return rc;
4127 }
4128
4129 if (machine_is_msm7x30_fluid()) {
4130 /* 1.8V -- LDO8 */
4131 vreg_ldo8 = vreg_get(NULL, "gp7");
4132
4133 if (IS_ERR(vreg_ldo8)) {
4134 rc = PTR_ERR(vreg_ldo8);
4135 pr_err("%s: gp7 vreg get failed (%d)\n",
4136 __func__, rc);
4137 return rc;
4138 }
4139 } else {
4140 /* lcd panel power */
4141 /* 3.1V -- LDO15 */
4142 vreg_ldo15 = vreg_get(NULL, "gp6");
4143
4144 if (IS_ERR(vreg_ldo15)) {
4145 rc = PTR_ERR(vreg_ldo15);
4146 pr_err("%s: gp6 vreg get failed (%d)\n",
4147 __func__, rc);
4148 return rc;
4149 }
4150 }
4151
4152 /* For QuickLogic chip, LDO20 requires 1.8V */
4153 /* Toshiba chip requires 1.5V, but can tolerate 1.8V since max is 3V */
4154 if (quickvx_mddi_client)
4155 rc = vreg_set_level(vreg_ldo20, 1800);
4156 else
4157 rc = vreg_set_level(vreg_ldo20, 1500);
4158 if (rc) {
4159 pr_err("%s: vreg LDO20 set level failed (%d)\n",
4160 __func__, rc);
4161 return rc;
4162 }
4163
4164 rc = vreg_set_level(vreg_ldo12, 1800);
4165 if (rc) {
4166 pr_err("%s: vreg LDO12 set level failed (%d)\n",
4167 __func__, rc);
4168 return rc;
4169 }
4170
4171 if (other_mddi_client) {
4172 rc = vreg_set_level(vreg_ldo16, 2600);
4173 if (rc) {
4174 pr_err("%s: vreg LDO16 set level failed (%d)\n",
4175 __func__, rc);
4176 return rc;
4177 }
4178 }
4179
4180 if (quickvx_mddi_client) {
4181 rc = vreg_set_level(vreg_ldo6, 3075);
4182 if (rc) {
4183 pr_err("%s: vreg LDO6 set level failed (%d)\n",
4184 __func__, rc);
4185 return rc;
4186 }
4187 }
4188
4189 if (machine_is_msm7x30_fluid()) {
4190 rc = vreg_set_level(vreg_ldo8, 1800);
4191 if (rc) {
4192 pr_err("%s: vreg LDO8 set level failed (%d)\n",
4193 __func__, rc);
4194 return rc;
4195 }
4196 } else {
4197 rc = vreg_set_level(vreg_ldo15, 3100);
4198 if (rc) {
4199 pr_err("%s: vreg LDO15 set level failed (%d)\n",
4200 __func__, rc);
4201 return rc;
4202 }
4203 }
4204
4205 if (on) {
4206 rc = vreg_enable(vreg_ldo20);
4207 if (rc) {
4208 pr_err("%s: LDO20 vreg enable failed (%d)\n",
4209 __func__, rc);
4210 return rc;
4211 }
4212
4213 rc = vreg_enable(vreg_ldo12);
4214 if (rc) {
4215 pr_err("%s: LDO12 vreg enable failed (%d)\n",
4216 __func__, rc);
4217 return rc;
4218 }
4219
4220 if (other_mddi_client) {
4221 rc = vreg_enable(vreg_ldo16);
4222 if (rc) {
4223 pr_err("%s: LDO16 vreg enable failed (%d)\n",
4224 __func__, rc);
4225 return rc;
4226 }
4227 }
4228
4229 if (quickvx_mddi_client && quickvx_ldo_enabled) {
4230 /* Disable LDO6 during display ON */
4231 rc = vreg_disable(vreg_ldo6);
4232 if (rc) {
4233 pr_err("%s: LDO6 vreg disable failed (%d)\n",
4234 __func__, rc);
4235 return rc;
4236 }
4237 quickvx_ldo_enabled = 0;
4238 }
4239
4240 if (machine_is_msm7x30_fluid()) {
4241 rc = vreg_enable(vreg_ldo8);
4242 if (rc) {
4243 pr_err("%s: LDO8 vreg enable failed (%d)\n",
4244 __func__, rc);
4245 return rc;
4246 }
4247 } else {
4248 rc = vreg_enable(vreg_ldo15);
4249 if (rc) {
4250 pr_err("%s: LDO15 vreg enable failed (%d)\n",
4251 __func__, rc);
4252 return rc;
4253 }
4254 }
4255
4256 mdelay(5); /* ensure power is stable */
4257
4258 if (machine_is_msm7x30_fluid()) {
4259 rc = msm_gpios_request_enable(fluid_vee_reset_gpio,
4260 ARRAY_SIZE(fluid_vee_reset_gpio));
4261 if (rc)
4262 pr_err("%s gpio_request_enable failed rc=%d\n",
4263 __func__, rc);
4264 else {
4265 /* assert vee reset_n */
4266 gpio_set_value(20, 1);
4267 gpio_set_value(20, 0);
4268 mdelay(1);
4269 gpio_set_value(20, 1);
4270 }
4271 }
4272
4273 gpio_set_value(180, 1); /* bring reset line high */
4274 mdelay(10); /* 10 msec before IO can be accessed */
4275
4276 if (quickvx_mddi_client) {
4277 gpio_set_value(97, 1);
4278 msleep(2);
4279 gpio_set_value_cansleep(PM8058_GPIO_PM_TO_SYS(
4280 PMIC_GPIO_QUICKVX_CLK), 1);
4281 msleep(2);
4282 }
4283
4284 rc = pmapp_display_clock_config(1);
4285 if (rc) {
4286 pr_err("%s pmapp_display_clock_config rc=%d\n",
4287 __func__, rc);
4288 return rc;
4289 }
4290
4291 } else {
4292 rc = vreg_disable(vreg_ldo20);
4293 if (rc) {
4294 pr_err("%s: LDO20 vreg disable failed (%d)\n",
4295 __func__, rc);
4296 return rc;
4297 }
4298
4299
4300 if (other_mddi_client) {
4301 rc = vreg_disable(vreg_ldo16);
4302 if (rc) {
4303 pr_err("%s: LDO16 vreg disable failed (%d)\n",
4304 __func__, rc);
4305 return rc;
4306 }
4307 }
4308
4309 if (quickvx_mddi_client && !quickvx_ldo_enabled) {
4310 /* Enable LDO6 during display OFF for
4311 Quicklogic chip to sleep with data retention */
4312 rc = vreg_enable(vreg_ldo6);
4313 if (rc) {
4314 pr_err("%s: LDO6 vreg enable failed (%d)\n",
4315 __func__, rc);
4316 return rc;
4317 }
4318 quickvx_ldo_enabled = 1;
4319 }
4320
4321 gpio_set_value(180, 0); /* bring reset line low */
4322
4323 if (quickvx_mddi_client) {
4324 gpio_set_value(97, 0);
4325 gpio_set_value_cansleep(PM8058_GPIO_PM_TO_SYS(
4326 PMIC_GPIO_QUICKVX_CLK), 0);
4327 }
4328
4329 if (machine_is_msm7x30_fluid()) {
4330 rc = vreg_disable(vreg_ldo8);
4331 if (rc) {
4332 pr_err("%s: LDO8 vreg disable failed (%d)\n",
4333 __func__, rc);
4334 return rc;
4335 }
4336 } else {
4337 rc = vreg_disable(vreg_ldo15);
4338 if (rc) {
4339 pr_err("%s: LDO15 vreg disable failed (%d)\n",
4340 __func__, rc);
4341 return rc;
4342 }
4343 }
4344
4345 mdelay(5); /* ensure power is stable */
4346
4347 rc = vreg_disable(vreg_ldo12);
4348 if (rc) {
4349 pr_err("%s: LDO12 vreg disable failed (%d)\n",
4350 __func__, rc);
4351 return rc;
4352 }
4353
4354 if (machine_is_msm7x30_fluid()) {
4355 msm_gpios_disable_free(fluid_vee_reset_gpio,
4356 ARRAY_SIZE(fluid_vee_reset_gpio));
4357 }
4358
4359 rc = pmapp_display_clock_config(0);
4360 if (rc) {
4361 pr_err("%s pmapp_display_clock_config rc=%d\n",
4362 __func__, rc);
4363 return rc;
4364 }
4365 }
4366
4367 return rc;
4368}
4369
4370static int msm_fb_mddi_sel_clk(u32 *clk_rate)
4371{
4372 *clk_rate *= 2;
4373 return 0;
4374}
4375
4376static int msm_fb_mddi_client_power(u32 client_id)
4377{
4378 struct vreg *vreg_ldo20, *vreg_ldo16;
4379 int rc;
4380
4381 printk(KERN_NOTICE "\n client_id = 0x%x", client_id);
4382 /* Check if it is Quicklogic client */
4383 if (client_id == 0xc5835800) {
4384 printk(KERN_NOTICE "\n Quicklogic MDDI client");
4385 other_mddi_client = 0;
4386 vreg_ldo16 = vreg_get(NULL, "gp10");
4387
4388 if (IS_ERR(vreg_ldo16)) {
4389 rc = PTR_ERR(vreg_ldo16);
4390 pr_err("%s: gp10 vreg get failed (%d)\n",
4391 __func__, rc);
4392 return rc;
4393 }
4394
4395 rc = vreg_disable(vreg_ldo16);
4396 if (rc) {
4397 pr_err("%s: LDO16 vreg enable failed (%d)\n",
4398 __func__, rc);
4399 return rc;
4400 }
4401 } else {
4402 printk(KERN_NOTICE "\n Non-Quicklogic MDDI client");
4403 quickvx_mddi_client = 0;
4404 gpio_set_value(97, 0);
4405 gpio_set_value_cansleep(PM8058_GPIO_PM_TO_SYS(
4406 PMIC_GPIO_QUICKVX_CLK), 0);
4407
4408 vreg_ldo20 = vreg_get(NULL, "gp13");
4409
4410 if (IS_ERR(vreg_ldo20)) {
4411 rc = PTR_ERR(vreg_ldo20);
4412 pr_err("%s: gp13 vreg get failed (%d)\n",
4413 __func__, rc);
4414 return rc;
4415 }
4416 rc = vreg_set_level(vreg_ldo20, 1500);
4417 if (rc) {
4418 pr_err("%s: vreg LDO20 set level failed (%d)\n",
4419 __func__, rc);
4420 return rc;
4421 }
4422 }
4423 return 0;
4424}
4425
4426static struct mddi_platform_data mddi_pdata = {
4427 .mddi_power_save = display_common_power,
4428 .mddi_sel_clk = msm_fb_mddi_sel_clk,
4429 .mddi_client_power = msm_fb_mddi_client_power,
4430};
4431
4432int mdp_core_clk_rate_table[] = {
4433 122880000,
4434 122880000,
4435 122880000,
4436 192000000,
4437};
4438
4439static struct msm_panel_common_pdata mdp_pdata = {
4440 .hw_revision_addr = 0xac001270,
4441 .gpio = 30,
4442 .mdp_core_clk_rate = 122880000,
4443 .mdp_core_clk_table = mdp_core_clk_rate_table,
4444 .num_mdp_clk = ARRAY_SIZE(mdp_core_clk_rate_table),
4445};
4446
4447static int lcd_panel_spi_gpio_num[] = {
4448 45, /* spi_clk */
4449 46, /* spi_cs */
4450 47, /* spi_mosi */
4451 48, /* spi_miso */
4452 };
4453
4454static struct msm_gpio lcd_panel_gpios[] = {
4455/* Workaround, since HDMI_INT is using the same GPIO line (18), and is used as
4456 * input. if there is a hardware revision; we should reassign this GPIO to a
4457 * new open line; and removing it will just ensure that this will be missed in
4458 * the future.
4459 { GPIO_CFG(18, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "lcdc_grn0" },
4460 */
4461 { GPIO_CFG(19, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "lcdc_grn1" },
4462 { GPIO_CFG(20, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "lcdc_blu0" },
4463 { GPIO_CFG(21, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "lcdc_blu1" },
4464 { GPIO_CFG(22, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "lcdc_blu2" },
4465 { GPIO_CFG(23, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "lcdc_red0" },
4466 { GPIO_CFG(24, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "lcdc_red1" },
4467 { GPIO_CFG(25, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "lcdc_red2" },
4468#ifndef CONFIG_SPI_QSD
4469 { GPIO_CFG(45, 0, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "spi_clk" },
4470 { GPIO_CFG(46, 0, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "spi_cs0" },
4471 { GPIO_CFG(47, 0, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "spi_mosi" },
4472 { GPIO_CFG(48, 0, GPIO_CFG_INPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "spi_miso" },
4473#endif
4474 { GPIO_CFG(90, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "lcdc_pclk" },
4475 { GPIO_CFG(91, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "lcdc_en" },
4476 { GPIO_CFG(92, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "lcdc_vsync" },
4477 { GPIO_CFG(93, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "lcdc_hsync" },
4478 { GPIO_CFG(94, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "lcdc_grn2" },
4479 { GPIO_CFG(95, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "lcdc_grn3" },
4480 { GPIO_CFG(96, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "lcdc_grn4" },
4481 { GPIO_CFG(97, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "lcdc_grn5" },
4482 { GPIO_CFG(98, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "lcdc_grn6" },
4483 { GPIO_CFG(99, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "lcdc_grn7" },
4484 { GPIO_CFG(100, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "lcdc_blu3" },
4485 { GPIO_CFG(101, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "lcdc_blu4" },
4486 { GPIO_CFG(102, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "lcdc_blu5" },
4487 { GPIO_CFG(103, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "lcdc_blu6" },
4488 { GPIO_CFG(104, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "lcdc_blu7" },
4489 { GPIO_CFG(105, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "lcdc_red3" },
4490 { GPIO_CFG(106, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "lcdc_red4" },
4491 { GPIO_CFG(107, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "lcdc_red5" },
4492 { GPIO_CFG(108, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "lcdc_red6" },
4493 { GPIO_CFG(109, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "lcdc_red7" },
4494};
4495
4496static struct msm_gpio lcd_sharp_panel_gpios[] = {
4497 { GPIO_CFG(22, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "lcdc_blu2" },
4498 { GPIO_CFG(25, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "lcdc_red2" },
4499 { GPIO_CFG(90, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "lcdc_pclk" },
4500 { GPIO_CFG(91, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "lcdc_en" },
4501 { GPIO_CFG(92, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "lcdc_vsync" },
4502 { GPIO_CFG(93, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "lcdc_hsync" },
4503 { GPIO_CFG(94, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "lcdc_grn2" },
4504 { GPIO_CFG(95, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "lcdc_grn3" },
4505 { GPIO_CFG(96, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "lcdc_grn4" },
4506 { GPIO_CFG(97, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "lcdc_grn5" },
4507 { GPIO_CFG(98, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "lcdc_grn6" },
4508 { GPIO_CFG(99, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "lcdc_grn7" },
4509 { GPIO_CFG(100, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "lcdc_blu3" },
4510 { GPIO_CFG(101, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "lcdc_blu4" },
4511 { GPIO_CFG(102, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "lcdc_blu5" },
4512 { GPIO_CFG(103, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "lcdc_blu6" },
4513 { GPIO_CFG(104, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "lcdc_blu7" },
4514 { GPIO_CFG(105, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "lcdc_red3" },
4515 { GPIO_CFG(106, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "lcdc_red4" },
4516 { GPIO_CFG(107, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "lcdc_red5" },
4517 { GPIO_CFG(108, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "lcdc_red6" },
4518 { GPIO_CFG(109, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "lcdc_red7" },
4519};
4520
4521static int lcdc_toshiba_panel_power(int on)
4522{
4523 int rc, i;
4524 struct msm_gpio *gp;
4525
4526 rc = display_common_power(on);
4527 if (rc < 0) {
4528 printk(KERN_ERR "%s display_common_power failed: %d\n",
4529 __func__, rc);
4530 return rc;
4531 }
4532
4533 if (on) {
4534 rc = msm_gpios_enable(lcd_panel_gpios,
4535 ARRAY_SIZE(lcd_panel_gpios));
4536 if (rc < 0) {
4537 printk(KERN_ERR "%s: gpio enable failed: %d\n",
4538 __func__, rc);
4539 }
4540 } else { /* off */
4541 gp = lcd_panel_gpios;
4542 for (i = 0; i < ARRAY_SIZE(lcd_panel_gpios); i++) {
4543 /* ouput low */
4544 gpio_set_value(GPIO_PIN(gp->gpio_cfg), 0);
4545 gp++;
4546 }
4547 }
4548
4549 return rc;
4550}
4551
4552static int lcdc_sharp_panel_power(int on)
4553{
4554 int rc, i;
4555 struct msm_gpio *gp;
4556
4557 rc = display_common_power(on);
4558 if (rc < 0) {
4559 printk(KERN_ERR "%s display_common_power failed: %d\n",
4560 __func__, rc);
4561 return rc;
4562 }
4563
4564 if (on) {
4565 rc = msm_gpios_enable(lcd_sharp_panel_gpios,
4566 ARRAY_SIZE(lcd_sharp_panel_gpios));
4567 if (rc < 0) {
4568 printk(KERN_ERR "%s: gpio enable failed: %d\n",
4569 __func__, rc);
4570 }
4571 } else { /* off */
4572 gp = lcd_sharp_panel_gpios;
4573 for (i = 0; i < ARRAY_SIZE(lcd_sharp_panel_gpios); i++) {
4574 /* ouput low */
4575 gpio_set_value(GPIO_PIN(gp->gpio_cfg), 0);
4576 gp++;
4577 }
4578 }
4579
4580 return rc;
4581}
4582
4583static int lcdc_panel_power(int on)
4584{
4585 int flag_on = !!on;
4586 static int lcdc_power_save_on;
4587
4588 if (lcdc_power_save_on == flag_on)
4589 return 0;
4590
4591 lcdc_power_save_on = flag_on;
4592 quickvx_mddi_client = 0;
4593
4594 if (machine_is_msm7x30_fluid())
4595 return lcdc_sharp_panel_power(on);
4596 else
4597 return lcdc_toshiba_panel_power(on);
4598}
4599
4600static struct lcdc_platform_data lcdc_pdata = {
4601 .lcdc_power_save = lcdc_panel_power,
4602};
4603
4604static int atv_dac_power(int on)
4605{
4606 int rc = 0;
4607 struct vreg *vreg_s4, *vreg_ldo9;
4608
4609 vreg_s4 = vreg_get(NULL, "s4");
4610 if (IS_ERR(vreg_s4)) {
4611 rc = PTR_ERR(vreg_s4);
4612 pr_err("%s: s4 vreg get failed (%d)\n",
4613 __func__, rc);
4614 return -1;
4615 }
4616 vreg_ldo9 = vreg_get(NULL, "gp1");
4617 if (IS_ERR(vreg_ldo9)) {
4618 rc = PTR_ERR(vreg_ldo9);
4619 pr_err("%s: ldo9 vreg get failed (%d)\n",
4620 __func__, rc);
4621 return rc;
4622 }
4623
4624 if (on) {
4625 rc = vreg_enable(vreg_s4);
4626 if (rc) {
4627 pr_err("%s: s4 vreg enable failed (%d)\n",
4628 __func__, rc);
4629 return rc;
4630 }
4631 rc = vreg_enable(vreg_ldo9);
4632 if (rc) {
4633 pr_err("%s: ldo9 vreg enable failed (%d)\n",
4634 __func__, rc);
4635 return rc;
4636 }
4637 } else {
4638 rc = vreg_disable(vreg_ldo9);
4639 if (rc) {
4640 pr_err("%s: ldo9 vreg disable failed (%d)\n",
4641 __func__, rc);
4642 return rc;
4643 }
4644 rc = vreg_disable(vreg_s4);
4645 if (rc) {
4646 pr_err("%s: s4 vreg disable failed (%d)\n",
4647 __func__, rc);
4648 return rc;
4649 }
4650 }
4651 return rc;
4652}
4653
4654static struct tvenc_platform_data atv_pdata = {
4655 .poll = 1,
4656 .pm_vid_en = atv_dac_power,
4657};
4658
4659static void __init msm_fb_add_devices(void)
4660{
4661 msm_fb_register_device("mdp", &mdp_pdata);
4662 msm_fb_register_device("pmdh", &mddi_pdata);
4663 msm_fb_register_device("lcdc", &lcdc_pdata);
4664 msm_fb_register_device("dtv", &dtv_pdata);
4665 msm_fb_register_device("tvenc", &atv_pdata);
4666#ifdef CONFIG_FB_MSM_TVOUT
4667 msm_fb_register_device("tvout_device", NULL);
4668#endif
4669}
4670
4671static struct msm_panel_common_pdata lcdc_toshiba_panel_data = {
4672 .gpio_num = lcd_panel_spi_gpio_num,
4673};
4674
4675static struct platform_device lcdc_toshiba_panel_device = {
4676 .name = "lcdc_toshiba_wvga",
4677 .id = 0,
4678 .dev = {
4679 .platform_data = &lcdc_toshiba_panel_data,
4680 }
4681};
4682
4683#if defined(CONFIG_MARIMBA_CORE) && \
4684 (defined(CONFIG_MSM_BT_POWER) || defined(CONFIG_MSM_BT_POWER_MODULE))
4685static struct platform_device msm_bt_power_device = {
4686 .name = "bt_power",
4687 .id = -1
4688};
4689
4690enum {
4691 BT_RFR,
4692 BT_CTS,
4693 BT_RX,
4694 BT_TX,
4695};
4696
4697static struct msm_gpio bt_config_power_on[] = {
4698 { GPIO_CFG(134, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA),
4699 "UART1DM_RFR" },
4700 { GPIO_CFG(135, 1, GPIO_CFG_INPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA),
4701 "UART1DM_CTS" },
4702 { GPIO_CFG(136, 1, GPIO_CFG_INPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA),
4703 "UART1DM_Rx" },
4704 { GPIO_CFG(137, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA),
4705 "UART1DM_Tx" }
4706};
4707
4708static struct msm_gpio bt_config_power_off[] = {
4709 { GPIO_CFG(134, 0, GPIO_CFG_INPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA),
4710 "UART1DM_RFR" },
4711 { GPIO_CFG(135, 0, GPIO_CFG_INPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA),
4712 "UART1DM_CTS" },
4713 { GPIO_CFG(136, 0, GPIO_CFG_INPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA),
4714 "UART1DM_Rx" },
4715 { GPIO_CFG(137, 0, GPIO_CFG_INPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA),
4716 "UART1DM_Tx" }
4717};
4718
4719static const char *vregs_bt_marimba_name[] = {
4720 "s3",
4721 "s2",
4722 "gp16",
4723 "wlan"
4724};
4725static struct vreg *vregs_bt_marimba[ARRAY_SIZE(vregs_bt_marimba_name)];
4726
4727static const char *vregs_bt_bahama_name[] = {
4728 "s3",
4729 "usb2",
4730 "s2",
4731 "wlan"
4732};
4733static struct vreg *vregs_bt_bahama[ARRAY_SIZE(vregs_bt_bahama_name)];
4734
4735static u8 bahama_version;
4736
4737static int marimba_bt(int on)
4738{
4739 int rc;
4740 int i;
4741 struct marimba config = { .mod_id = MARIMBA_SLAVE_ID_MARIMBA };
4742
4743 struct marimba_config_register {
4744 u8 reg;
4745 u8 value;
4746 u8 mask;
4747 };
4748
4749 struct marimba_variant_register {
4750 const size_t size;
4751 const struct marimba_config_register *set;
4752 };
4753
4754 const struct marimba_config_register *p;
4755
4756 u8 version;
4757
4758 const struct marimba_config_register v10_bt_on[] = {
4759 { 0xE5, 0x0B, 0x0F },
4760 { 0x05, 0x02, 0x07 },
4761 { 0x06, 0x88, 0xFF },
4762 { 0xE7, 0x21, 0x21 },
4763 { 0xE3, 0x38, 0xFF },
4764 { 0xE4, 0x06, 0xFF },
4765 };
4766
4767 const struct marimba_config_register v10_bt_off[] = {
4768 { 0xE5, 0x0B, 0x0F },
4769 { 0x05, 0x08, 0x0F },
4770 { 0x06, 0x88, 0xFF },
4771 { 0xE7, 0x00, 0x21 },
4772 { 0xE3, 0x00, 0xFF },
4773 { 0xE4, 0x00, 0xFF },
4774 };
4775
4776 const struct marimba_config_register v201_bt_on[] = {
4777 { 0x05, 0x08, 0x07 },
4778 { 0x06, 0x88, 0xFF },
4779 { 0xE7, 0x21, 0x21 },
4780 { 0xE3, 0x38, 0xFF },
4781 { 0xE4, 0x06, 0xFF },
4782 };
4783
4784 const struct marimba_config_register v201_bt_off[] = {
4785 { 0x05, 0x08, 0x07 },
4786 { 0x06, 0x88, 0xFF },
4787 { 0xE7, 0x00, 0x21 },
4788 { 0xE3, 0x00, 0xFF },
4789 { 0xE4, 0x00, 0xFF },
4790 };
4791
4792 const struct marimba_config_register v210_bt_on[] = {
4793 { 0xE9, 0x01, 0x01 },
4794 { 0x06, 0x88, 0xFF },
4795 { 0xE7, 0x21, 0x21 },
4796 { 0xE3, 0x38, 0xFF },
4797 { 0xE4, 0x06, 0xFF },
4798 };
4799
4800 const struct marimba_config_register v210_bt_off[] = {
4801 { 0x06, 0x88, 0xFF },
4802 { 0xE7, 0x00, 0x21 },
4803 { 0xE9, 0x00, 0x01 },
4804 { 0xE3, 0x00, 0xFF },
4805 { 0xE4, 0x00, 0xFF },
4806 };
4807
4808 const struct marimba_variant_register bt_marimba[2][4] = {
4809 {
4810 { ARRAY_SIZE(v10_bt_off), v10_bt_off },
4811 { 0, NULL },
4812 { ARRAY_SIZE(v201_bt_off), v201_bt_off },
4813 { ARRAY_SIZE(v210_bt_off), v210_bt_off }
4814 },
4815 {
4816 { ARRAY_SIZE(v10_bt_on), v10_bt_on },
4817 { 0, NULL },
4818 { ARRAY_SIZE(v201_bt_on), v201_bt_on },
4819 { ARRAY_SIZE(v210_bt_on), v210_bt_on }
4820 }
4821 };
4822
4823 on = on ? 1 : 0;
4824
4825 rc = marimba_read_bit_mask(&config, 0x11, &version, 1, 0x1F);
4826 if (rc < 0) {
4827 printk(KERN_ERR
4828 "%s: version read failed: %d\n",
4829 __func__, rc);
4830 return rc;
4831 }
4832
4833 if ((version >= ARRAY_SIZE(bt_marimba[on])) ||
4834 (bt_marimba[on][version].size == 0)) {
4835 printk(KERN_ERR
4836 "%s: unsupported version\n",
4837 __func__);
4838 return -EIO;
4839 }
4840
4841 p = bt_marimba[on][version].set;
4842
4843 printk(KERN_INFO "%s: found version %d\n", __func__, version);
4844
4845 for (i = 0; i < bt_marimba[on][version].size; i++) {
4846 u8 value = (p+i)->value;
4847 rc = marimba_write_bit_mask(&config,
4848 (p+i)->reg,
4849 &value,
4850 sizeof((p+i)->value),
4851 (p+i)->mask);
4852 if (rc < 0) {
4853 printk(KERN_ERR
4854 "%s: reg %d write failed: %d\n",
4855 __func__, (p+i)->reg, rc);
4856 return rc;
4857 }
4858 printk(KERN_INFO "%s: reg 0x%02x value 0x%02x mask 0x%02x\n",
4859 __func__, (p+i)->reg,
4860 value, (p+i)->mask);
4861 }
4862 return 0;
4863}
4864
4865static int bahama_bt(int on)
4866{
4867 int rc;
4868 int i;
4869 struct marimba config = { .mod_id = SLAVE_ID_BAHAMA };
4870
4871 struct bahama_variant_register {
4872 const size_t size;
4873 const struct bahama_config_register *set;
4874 };
4875
4876 const struct bahama_config_register *p;
4877
4878
4879 const struct bahama_config_register v10_bt_on[] = {
4880 { 0xE9, 0x00, 0xFF },
4881 { 0xF4, 0x80, 0xFF },
4882 { 0xF0, 0x06, 0xFF },
4883 { 0xE4, 0x00, 0xFF },
4884 { 0xE5, 0x00, 0x0F },
4885#ifdef CONFIG_WLAN
4886 { 0xE6, 0x38, 0x7F },
4887 { 0xE7, 0x06, 0xFF },
4888#endif
4889 { 0x11, 0x13, 0xFF },
4890 { 0xE9, 0x21, 0xFF },
4891 { 0x01, 0x0C, 0x1F },
4892 { 0x01, 0x08, 0x1F },
4893 };
4894
4895 const struct bahama_config_register v20_bt_on_fm_off[] = {
4896 { 0x11, 0x0C, 0xFF },
4897 { 0x13, 0x01, 0xFF },
4898 { 0xF4, 0x80, 0xFF },
4899 { 0xF0, 0x00, 0xFF },
4900 { 0xE9, 0x00, 0xFF },
4901#ifdef CONFIG_WLAN
4902 { 0x81, 0x00, 0xFF },
4903 { 0x82, 0x00, 0xFF },
4904 { 0xE6, 0x38, 0x7F },
4905 { 0xE7, 0x06, 0xFF },
4906#endif
4907 { 0xE9, 0x21, 0xFF }
4908 };
4909
4910 const struct bahama_config_register v20_bt_on_fm_on[] = {
4911 { 0x11, 0x0C, 0xFF },
4912 { 0x13, 0x01, 0xFF },
4913 { 0xF4, 0x86, 0xFF },
4914 { 0xF0, 0x06, 0xFF },
4915 { 0xE9, 0x00, 0xFF },
4916#ifdef CONFIG_WLAN
4917 { 0x81, 0x00, 0xFF },
4918 { 0x82, 0x00, 0xFF },
4919 { 0xE6, 0x38, 0x7F },
4920 { 0xE7, 0x06, 0xFF },
4921#endif
4922 { 0xE9, 0x21, 0xFF }
4923 };
4924
4925 const struct bahama_config_register v10_bt_off[] = {
4926 { 0xE9, 0x00, 0xFF },
4927 };
4928
4929 const struct bahama_config_register v20_bt_off_fm_off[] = {
4930 { 0xF4, 0x84, 0xFF },
4931 { 0xF0, 0x04, 0xFF },
4932 { 0xE9, 0x00, 0xFF }
4933 };
4934
4935 const struct bahama_config_register v20_bt_off_fm_on[] = {
4936 { 0xF4, 0x86, 0xFF },
4937 { 0xF0, 0x06, 0xFF },
4938 { 0xE9, 0x00, 0xFF }
4939 };
4940
4941 const struct bahama_variant_register bt_bahama[2][3] = {
4942 {
4943 { ARRAY_SIZE(v10_bt_off), v10_bt_off },
4944 { ARRAY_SIZE(v20_bt_off_fm_off), v20_bt_off_fm_off },
4945 { ARRAY_SIZE(v20_bt_off_fm_on), v20_bt_off_fm_on }
4946 },
4947 {
4948 { ARRAY_SIZE(v10_bt_on), v10_bt_on },
4949 { ARRAY_SIZE(v20_bt_on_fm_off), v20_bt_on_fm_off },
4950 { ARRAY_SIZE(v20_bt_on_fm_on), v20_bt_on_fm_on }
4951 }
4952 };
4953
4954 u8 offset = 0; /* index into bahama configs */
4955
4956 on = on ? 1 : 0;
4957
4958 bahama_version = read_bahama_ver();
4959
4960 if (((int)bahama_version) < 0 ||
4961 bahama_version == VER_UNSUPPORTED) {
4962 dev_err(&msm_bt_power_device.dev,
4963 "%s: i2c failure or unsupported version: %d\n",
4964 __func__, bahama_version);
4965 return -EIO;
4966 }
4967
4968 if (bahama_version == VER_2_0) {
4969 if (marimba_get_fm_status(&config))
4970 offset = 0x01;
4971 }
4972
4973 p = bt_bahama[on][bahama_version + offset].set;
4974
4975 dev_info(&msm_bt_power_device.dev,
4976 "%s: found version %d\n", __func__, bahama_version);
4977
4978 for (i = 0; i < bt_bahama[on][bahama_version + offset].size; i++) {
4979 u8 value = (p+i)->value;
4980 rc = marimba_write_bit_mask(&config,
4981 (p+i)->reg,
4982 &value,
4983 sizeof((p+i)->value),
4984 (p+i)->mask);
4985 if (rc < 0) {
4986 dev_err(&msm_bt_power_device.dev,
4987 "%s: reg %d write failed: %d\n",
4988 __func__, (p+i)->reg, rc);
4989 return rc;
4990 }
4991 dev_info(&msm_bt_power_device.dev,
4992 "%s: reg 0x%02x write value 0x%02x mask 0x%02x\n",
4993 __func__, (p+i)->reg,
4994 value, (p+i)->mask);
4995 }
4996 /* Update BT status */
4997 if (on)
4998 marimba_set_bt_status(&config, true);
4999 else
5000 marimba_set_bt_status(&config, false);
5001
5002 if (bahama_version == VER_2_0 && on) { /* variant of bahama v2 */
5003 /* Disable s2 as bahama v2 uses internal LDO regulator */
5004 for (i = 0; i < ARRAY_SIZE(vregs_bt_bahama_name); i++) {
5005 if (!strcmp(vregs_bt_bahama_name[i], "s2")) {
5006 rc = vreg_disable(vregs_bt_bahama[i]);
5007 if (rc < 0) {
5008 printk(KERN_ERR
5009 "%s: vreg %s disable "
5010 "failed (%d)\n",
5011 __func__,
5012 vregs_bt_bahama_name[i], rc);
5013 return -EIO;
5014 }
5015 rc = pmapp_vreg_level_vote("BTPW",
5016 PMAPP_VREG_S2,
5017 0);
5018 if (rc < 0) {
5019 printk(KERN_ERR "%s: vreg "
5020 "level off failed (%d)\n",
5021 __func__, rc);
5022 return -EIO;
5023 }
5024 printk(KERN_INFO "%s: vreg disable & "
5025 "level off successful (%d)\n",
5026 __func__, rc);
5027 }
5028 }
5029 }
5030
5031 return 0;
5032}
5033
5034static int bluetooth_power_regulators(int on, int bahama_not_marimba)
5035{
5036 int i, rc;
5037 const char **vregs_name;
5038 struct vreg **vregs;
5039 int vregs_size;
5040
5041 if (bahama_not_marimba) {
5042 vregs_name = vregs_bt_bahama_name;
5043 vregs = vregs_bt_bahama;
5044 vregs_size = ARRAY_SIZE(vregs_bt_bahama_name);
5045 } else {
5046 vregs_name = vregs_bt_marimba_name;
5047 vregs = vregs_bt_marimba;
5048 vregs_size = ARRAY_SIZE(vregs_bt_marimba_name);
5049 }
5050
5051 for (i = 0; i < vregs_size; i++) {
5052 if (bahama_not_marimba && (bahama_version == VER_2_0) &&
5053 !on && !strcmp(vregs_bt_bahama_name[i], "s2"))
5054 continue;
5055 rc = on ? vreg_enable(vregs[i]) :
5056 vreg_disable(vregs[i]);
5057 if (rc < 0) {
5058 printk(KERN_ERR "%s: vreg %s %s failed (%d)\n",
5059 __func__, vregs_name[i],
5060 on ? "enable" : "disable", rc);
5061 return -EIO;
5062 }
5063 }
5064 return 0;
5065}
5066
5067static int bluetooth_power(int on)
5068{
5069 int rc;
5070 const char *id = "BTPW";
5071
5072 int bahama_not_marimba = bahama_present();
5073
5074 if (bahama_not_marimba == -1) {
5075 printk(KERN_WARNING "%s: bahama_present: %d\n",
5076 __func__, bahama_not_marimba);
5077 return -ENODEV;
5078 }
5079
5080 if (on) {
5081 rc = pmapp_vreg_level_vote(id, PMAPP_VREG_S2, 1300);
5082 if (rc < 0) {
5083 printk(KERN_ERR "%s: vreg level on failed (%d)\n",
5084 __func__, rc);
5085 return rc;
5086 }
5087
5088 rc = bluetooth_power_regulators(on, bahama_not_marimba);
5089 if (rc < 0)
5090 return -EIO;
5091
5092 rc = pmapp_clock_vote(id, PMAPP_CLOCK_ID_DO,
5093 PMAPP_CLOCK_VOTE_ON);
5094 if (rc < 0)
5095 return -EIO;
5096
5097 if (machine_is_msm8x55_svlte_surf() ||
5098 machine_is_msm8x55_svlte_ffa()) {
5099 rc = marimba_gpio_config(1);
5100 if (rc < 0)
5101 return -EIO;
5102 }
5103
5104 rc = (bahama_not_marimba ? bahama_bt(on) : marimba_bt(on));
5105 if (rc < 0)
5106 return -EIO;
5107
5108 msleep(10);
5109
5110 rc = pmapp_clock_vote(id, PMAPP_CLOCK_ID_DO,
5111 PMAPP_CLOCK_VOTE_PIN_CTRL);
5112 if (rc < 0)
5113 return -EIO;
5114
5115 if (machine_is_msm8x55_svlte_surf() ||
5116 machine_is_msm8x55_svlte_ffa()) {
5117 rc = marimba_gpio_config(0);
5118 if (rc < 0)
5119 return -EIO;
5120 }
5121
5122 rc = msm_gpios_enable(bt_config_power_on,
5123 ARRAY_SIZE(bt_config_power_on));
5124
5125 if (rc < 0)
5126 return rc;
5127
5128 } else {
5129 rc = msm_gpios_enable(bt_config_power_off,
5130 ARRAY_SIZE(bt_config_power_off));
5131 if (rc < 0)
5132 return rc;
5133
5134 /* check for initial RFKILL block (power off) */
5135 if (platform_get_drvdata(&msm_bt_power_device) == NULL)
5136 goto out;
5137
5138 rc = (bahama_not_marimba ? bahama_bt(on) : marimba_bt(on));
5139 if (rc < 0)
5140 return -EIO;
5141
5142 rc = pmapp_clock_vote(id, PMAPP_CLOCK_ID_DO,
5143 PMAPP_CLOCK_VOTE_OFF);
5144 if (rc < 0)
5145 return -EIO;
5146
5147 rc = bluetooth_power_regulators(on, bahama_not_marimba);
5148 if (rc < 0)
5149 return -EIO;
5150
5151 if (bahama_version == VER_1_0) {
5152 rc = pmapp_vreg_level_vote(id, PMAPP_VREG_S2, 0);
5153 if (rc < 0) {
5154 printk(KERN_ERR "%s: vreg level off failed "
5155 "(%d)\n", __func__, rc);
5156 return -EIO;
5157 }
5158 }
5159 }
5160
5161out:
5162 printk(KERN_DEBUG "Bluetooth power switch: %d\n", on);
5163
5164 return 0;
5165}
5166
5167static void __init bt_power_init(void)
5168{
5169 int i;
5170
5171 for (i = 0; i < ARRAY_SIZE(vregs_bt_marimba_name); i++) {
5172 vregs_bt_marimba[i] = vreg_get(NULL, vregs_bt_marimba_name[i]);
5173 if (IS_ERR(vregs_bt_marimba[i])) {
5174 printk(KERN_ERR "%s: vreg get %s failed (%ld)\n",
5175 __func__, vregs_bt_marimba_name[i],
5176 PTR_ERR(vregs_bt_marimba[i]));
5177 return;
5178 }
5179 }
5180
5181 for (i = 0; i < ARRAY_SIZE(vregs_bt_bahama_name); i++) {
5182 vregs_bt_bahama[i] = vreg_get(NULL, vregs_bt_bahama_name[i]);
5183 if (IS_ERR(vregs_bt_bahama[i])) {
5184 printk(KERN_ERR "%s: vreg get %s failed (%ld)\n",
5185 __func__, vregs_bt_bahama_name[i],
5186 PTR_ERR(vregs_bt_bahama[i]));
5187 return;
5188 }
5189 }
5190
5191 msm_bt_power_device.dev.platform_data = &bluetooth_power;
5192}
5193#else
5194#define bt_power_init(x) do {} while (0)
5195#endif
5196
5197static struct msm_psy_batt_pdata msm_psy_batt_data = {
5198 .voltage_min_design = 2800,
5199 .voltage_max_design = 4300,
5200 .avail_chg_sources = AC_CHG | USB_CHG ,
5201 .batt_technology = POWER_SUPPLY_TECHNOLOGY_LION,
5202};
5203
5204static struct platform_device msm_batt_device = {
5205 .name = "msm-battery",
5206 .id = -1,
5207 .dev.platform_data = &msm_psy_batt_data,
5208};
5209
5210static char *msm_adc_fluid_device_names[] = {
5211 "LTC_ADC1",
5212 "LTC_ADC2",
5213 "LTC_ADC3",
5214};
5215
5216static char *msm_adc_surf_device_names[] = {
5217 "XO_ADC",
5218};
5219
5220static struct msm_adc_platform_data msm_adc_pdata;
5221
5222static struct platform_device msm_adc_device = {
5223 .name = "msm_adc",
5224 .id = -1,
5225 .dev = {
5226 .platform_data = &msm_adc_pdata,
5227 },
5228};
5229
5230#ifdef CONFIG_MSM_SDIO_AL
5231static struct msm_gpio mdm2ap_status = {
5232 GPIO_CFG(77, 0, GPIO_CFG_INPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA),
5233 "mdm2ap_status"
5234};
5235
5236
5237static int configure_mdm2ap_status(int on)
5238{
5239 if (on)
5240 return msm_gpios_request_enable(&mdm2ap_status, 1);
5241 else {
5242 msm_gpios_disable_free(&mdm2ap_status, 1);
5243 return 0;
5244 }
5245}
5246
5247static int get_mdm2ap_status(void)
5248{
5249 return gpio_get_value(GPIO_PIN(mdm2ap_status.gpio_cfg));
5250}
5251
5252static struct sdio_al_platform_data sdio_al_pdata = {
5253 .config_mdm2ap_status = configure_mdm2ap_status,
5254 .get_mdm2ap_status = get_mdm2ap_status,
5255 .allow_sdioc_version_major_2 = 1,
5256 .peer_sdioc_version_minor = 0x0001,
5257 .peer_sdioc_version_major = 0x0003,
5258 .peer_sdioc_boot_version_minor = 0x0001,
5259 .peer_sdioc_boot_version_major = 0x0003,
5260};
5261
5262struct platform_device msm_device_sdio_al = {
5263 .name = "msm_sdio_al",
5264 .id = -1,
5265 .dev = {
5266 .platform_data = &sdio_al_pdata,
5267 },
5268};
5269
5270#endif /* CONFIG_MSM_SDIO_AL */
5271
Daniel Walker8d747cd2010-02-25 11:37:43 -08005272static struct platform_device *devices[] __initdata = {
Daniel Walker90e37c52010-05-12 14:24:15 -07005273#if defined(CONFIG_SERIAL_MSM) || defined(CONFIG_MSM_SERIAL_DEBUGGER)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005274 &msm_device_uart2,
5275#endif
Justin Paupore637a25d2011-07-14 17:11:04 -07005276#ifdef CONFIG_MSM_PROC_COMM_REGULATOR
5277 &msm_proccomm_regulator_dev,
5278#endif
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005279 &asoc_msm_pcm,
5280 &asoc_msm_dai0,
5281 &asoc_msm_dai1,
5282#if defined (CONFIG_SND_MSM_MVS_DAI_SOC)
5283 &asoc_msm_mvs,
5284 &asoc_mvs_dai0,
5285 &asoc_mvs_dai1,
Daniel Walker90e37c52010-05-12 14:24:15 -07005286#endif
Niranjana Vishwanathapuraa8855e92010-10-06 13:52:10 -07005287 &msm_device_smd,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005288 &msm_device_dmov,
5289 &smc91x_device,
5290 &smsc911x_device,
5291 &msm_device_nand,
5292#ifdef CONFIG_USB_MSM_OTG_72K
Pavankumar Kondeti5155e2c2010-12-08 13:37:08 +05305293 &msm_device_otg,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005294#ifdef CONFIG_USB_GADGET
5295 &msm_device_gadget_peripheral,
5296#endif
5297#endif
5298#ifdef CONFIG_USB_G_ANDROID
5299 &android_usb_device,
5300#endif
5301 &qsd_device_spi,
5302#ifdef CONFIG_I2C_SSBI
5303 &msm_device_ssbi6,
5304 &msm_device_ssbi7,
5305#endif
5306 &android_pmem_device,
5307 &msm_fb_device,
5308 &msm_migrate_pages_device,
5309 &mddi_toshiba_device,
5310 &lcdc_toshiba_panel_device,
5311#ifdef CONFIG_MSM_ROTATOR
5312 &msm_rotator_device,
5313#endif
5314 &lcdc_sharp_panel_device,
5315 &android_pmem_adsp_device,
5316 &android_pmem_audio_device,
5317 &msm_device_i2c,
5318 &msm_device_i2c_2,
5319 &msm_device_uart_dm1,
5320 &hs_device,
5321#ifdef CONFIG_MSM7KV2_AUDIO
5322 &msm_aictl_device,
5323 &msm_mi2s_device,
5324 &msm_lpa_device,
5325 &msm_aux_pcm_device,
5326#endif
5327 &msm_device_adspdec,
5328 &qup_device_i2c,
5329#if defined(CONFIG_MARIMBA_CORE) && \
5330 (defined(CONFIG_MSM_BT_POWER) || defined(CONFIG_MSM_BT_POWER_MODULE))
5331 &msm_bt_power_device,
5332#endif
5333 &msm_kgsl_3d0,
5334 &msm_kgsl_2d0,
5335#ifdef CONFIG_MT9T013
5336 &msm_camera_sensor_mt9t013,
5337#endif
5338#ifdef CONFIG_MT9D112
5339 &msm_camera_sensor_mt9d112,
5340#endif
5341#ifdef CONFIG_WEBCAM_OV9726
5342 &msm_camera_sensor_ov9726,
5343#endif
5344#ifdef CONFIG_S5K3E2FX
5345 &msm_camera_sensor_s5k3e2fx,
5346#endif
5347#ifdef CONFIG_MT9P012
5348 &msm_camera_sensor_mt9p012,
5349#endif
5350#ifdef CONFIG_MT9E013
5351 &msm_camera_sensor_mt9e013,
5352#endif
5353#ifdef CONFIG_VX6953
5354 &msm_camera_sensor_vx6953,
5355#endif
5356#ifdef CONFIG_SN12M0PZ
5357 &msm_camera_sensor_sn12m0pz,
5358#endif
5359 &msm_device_vidc_720p,
5360#ifdef CONFIG_MSM_GEMINI
5361 &msm_gemini_device,
5362#endif
5363#ifdef CONFIG_MSM_VPE
5364 &msm_vpe_device,
5365#endif
5366#if defined(CONFIG_TSIF) || defined(CONFIG_TSIF_MODULE)
5367 &msm_device_tsif,
5368#endif
5369#ifdef CONFIG_MSM_SDIO_AL
5370 &msm_device_sdio_al,
5371#endif
5372
5373#if defined(CONFIG_CRYPTO_DEV_QCRYPTO) || \
5374 defined(CONFIG_CRYPTO_DEV_QCRYPTO_MODULE)
5375 &qcrypto_device,
5376#endif
5377
5378#if defined(CONFIG_CRYPTO_DEV_QCEDEV) || \
5379 defined(CONFIG_CRYPTO_DEV_QCEDEV_MODULE)
5380 &qcedev_device,
5381#endif
5382
5383 &msm_batt_device,
5384 &msm_adc_device,
5385 &msm_ebi0_thermal,
5386 &msm_ebi1_thermal
5387};
5388
5389static struct msm_gpio msm_i2c_gpios_hw[] = {
5390 { GPIO_CFG(70, 1, GPIO_CFG_INPUT, GPIO_CFG_NO_PULL, GPIO_CFG_16MA), "i2c_scl" },
5391 { GPIO_CFG(71, 1, GPIO_CFG_INPUT, GPIO_CFG_NO_PULL, GPIO_CFG_16MA), "i2c_sda" },
5392};
5393
5394static struct msm_gpio msm_i2c_gpios_io[] = {
5395 { GPIO_CFG(70, 0, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_16MA), "i2c_scl" },
5396 { GPIO_CFG(71, 0, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_16MA), "i2c_sda" },
5397};
5398
5399static struct msm_gpio qup_i2c_gpios_io[] = {
5400 { GPIO_CFG(16, 0, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_16MA), "qup_scl" },
5401 { GPIO_CFG(17, 0, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_16MA), "qup_sda" },
5402};
5403static struct msm_gpio qup_i2c_gpios_hw[] = {
5404 { GPIO_CFG(16, 2, GPIO_CFG_INPUT, GPIO_CFG_NO_PULL, GPIO_CFG_16MA), "qup_scl" },
5405 { GPIO_CFG(17, 2, GPIO_CFG_INPUT, GPIO_CFG_NO_PULL, GPIO_CFG_16MA), "qup_sda" },
5406};
5407
5408static void
5409msm_i2c_gpio_config(int adap_id, int config_type)
5410{
5411 struct msm_gpio *msm_i2c_table;
5412
5413 /* Each adapter gets 2 lines from the table */
5414 if (adap_id > 0)
5415 return;
5416 if (config_type)
5417 msm_i2c_table = &msm_i2c_gpios_hw[adap_id*2];
5418 else
5419 msm_i2c_table = &msm_i2c_gpios_io[adap_id*2];
5420 msm_gpios_enable(msm_i2c_table, 2);
5421}
5422/*This needs to be enabled only for OEMS*/
5423#ifndef CONFIG_QUP_EXCLUSIVE_TO_CAMERA
5424static struct vreg *qup_vreg;
5425#endif
5426static void
5427qup_i2c_gpio_config(int adap_id, int config_type)
5428{
5429 int rc = 0;
5430 struct msm_gpio *qup_i2c_table;
5431 /* Each adapter gets 2 lines from the table */
5432 if (adap_id != 4)
5433 return;
5434 if (config_type)
5435 qup_i2c_table = qup_i2c_gpios_hw;
5436 else
5437 qup_i2c_table = qup_i2c_gpios_io;
5438 rc = msm_gpios_enable(qup_i2c_table, 2);
5439 if (rc < 0)
5440 printk(KERN_ERR "QUP GPIO enable failed: %d\n", rc);
5441 /*This needs to be enabled only for OEMS*/
5442#ifndef CONFIG_QUP_EXCLUSIVE_TO_CAMERA
5443 if (qup_vreg) {
5444 int rc = vreg_set_level(qup_vreg, 1800);
5445 if (rc) {
5446 pr_err("%s: vreg LVS1 set level failed (%d)\n",
5447 __func__, rc);
5448 }
5449 rc = vreg_enable(qup_vreg);
5450 if (rc) {
5451 pr_err("%s: vreg_enable() = %d \n",
5452 __func__, rc);
5453 }
5454 }
5455#endif
5456}
5457
5458static struct msm_i2c_platform_data msm_i2c_pdata = {
5459 .clk_freq = 100000,
5460 .pri_clk = 70,
5461 .pri_dat = 71,
5462 .rmutex = 1,
5463 .rsl_id = "D:I2C02000021",
5464 .msm_i2c_config_gpio = msm_i2c_gpio_config,
5465};
5466
5467static void __init msm_device_i2c_init(void)
5468{
5469 if (msm_gpios_request(msm_i2c_gpios_hw, ARRAY_SIZE(msm_i2c_gpios_hw)))
5470 pr_err("failed to request I2C gpios\n");
5471
5472 msm_device_i2c.dev.platform_data = &msm_i2c_pdata;
5473}
5474
5475static struct msm_i2c_platform_data msm_i2c_2_pdata = {
5476 .clk_freq = 100000,
5477 .rmutex = 1,
5478 .rsl_id = "D:I2C02000022",
5479 .msm_i2c_config_gpio = msm_i2c_gpio_config,
5480};
5481
5482static void __init msm_device_i2c_2_init(void)
5483{
5484 msm_device_i2c_2.dev.platform_data = &msm_i2c_2_pdata;
5485}
5486
5487static struct msm_i2c_platform_data qup_i2c_pdata = {
5488 .clk_freq = 384000,
5489 .pclk = "camif_pad_pclk",
5490 .msm_i2c_config_gpio = qup_i2c_gpio_config,
5491};
5492
5493static void __init qup_device_i2c_init(void)
5494{
5495 if (msm_gpios_request(qup_i2c_gpios_hw, ARRAY_SIZE(qup_i2c_gpios_hw)))
5496 pr_err("failed to request I2C gpios\n");
5497
5498 qup_device_i2c.dev.platform_data = &qup_i2c_pdata;
5499 /*This needs to be enabled only for OEMS*/
5500#ifndef CONFIG_QUP_EXCLUSIVE_TO_CAMERA
5501 qup_vreg = vreg_get(NULL, "lvsw1");
5502 if (IS_ERR(qup_vreg)) {
5503 printk(KERN_ERR "%s: vreg get failed (%ld)\n",
5504 __func__, PTR_ERR(qup_vreg));
5505 }
5506#endif
5507}
5508
5509#ifdef CONFIG_I2C_SSBI
5510static struct msm_i2c_ssbi_platform_data msm_i2c_ssbi6_pdata = {
5511 .rsl_id = "D:PMIC_SSBI",
5512 .controller_type = MSM_SBI_CTRL_SSBI2,
5513};
5514
5515static struct msm_i2c_ssbi_platform_data msm_i2c_ssbi7_pdata = {
5516 .rsl_id = "D:CODEC_SSBI",
5517 .controller_type = MSM_SBI_CTRL_SSBI,
5518};
5519#endif
5520
5521static struct msm_acpu_clock_platform_data msm7x30_clock_data = {
5522 .acpu_switch_time_us = 50,
5523 .vdd_switch_time_us = 62,
Daniel Walker8d747cd2010-02-25 11:37:43 -08005524};
5525
5526static void __init msm7x30_init_irq(void)
5527{
5528 msm_init_irq();
5529}
5530
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005531static struct msm_gpio msm_nand_ebi2_cfg_data[] = {
5532 {GPIO_CFG(86, 1, GPIO_CFG_OUTPUT, GPIO_CFG_PULL_UP, GPIO_CFG_8MA), "ebi2_cs1"},
5533 {GPIO_CFG(115, 2, GPIO_CFG_OUTPUT, GPIO_CFG_PULL_UP, GPIO_CFG_8MA), "ebi2_busy1"},
5534};
5535
5536struct vreg *vreg_s3;
5537struct vreg *vreg_mmc;
5538
5539#if (defined(CONFIG_MMC_MSM_SDC1_SUPPORT)\
5540 || defined(CONFIG_MMC_MSM_SDC2_SUPPORT)\
5541 || defined(CONFIG_MMC_MSM_SDC3_SUPPORT)\
5542 || defined(CONFIG_MMC_MSM_SDC4_SUPPORT))
5543
5544struct sdcc_gpio {
5545 struct msm_gpio *cfg_data;
5546 uint32_t size;
5547 struct msm_gpio *sleep_cfg_data;
5548};
5549#if defined(CONFIG_MMC_MSM_SDC1_SUPPORT)
5550static struct msm_gpio sdc1_lvlshft_cfg_data[] = {
5551 {GPIO_CFG(35, 1, GPIO_CFG_OUTPUT, GPIO_CFG_PULL_UP, GPIO_CFG_16MA), "sdc1_lvlshft"},
5552};
5553#endif
5554static struct msm_gpio sdc1_cfg_data[] = {
5555 {GPIO_CFG(38, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_16MA), "sdc1_clk"},
5556 {GPIO_CFG(39, 1, GPIO_CFG_OUTPUT, GPIO_CFG_PULL_UP, GPIO_CFG_8MA), "sdc1_cmd"},
5557 {GPIO_CFG(40, 1, GPIO_CFG_OUTPUT, GPIO_CFG_PULL_UP, GPIO_CFG_8MA), "sdc1_dat_3"},
5558 {GPIO_CFG(41, 1, GPIO_CFG_OUTPUT, GPIO_CFG_PULL_UP, GPIO_CFG_8MA), "sdc1_dat_2"},
5559 {GPIO_CFG(42, 1, GPIO_CFG_OUTPUT, GPIO_CFG_PULL_UP, GPIO_CFG_8MA), "sdc1_dat_1"},
5560 {GPIO_CFG(43, 1, GPIO_CFG_OUTPUT, GPIO_CFG_PULL_UP, GPIO_CFG_8MA), "sdc1_dat_0"},
5561};
5562
5563static struct msm_gpio sdc2_cfg_data[] = {
5564 {GPIO_CFG(64, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_16MA), "sdc2_clk"},
5565 {GPIO_CFG(65, 1, GPIO_CFG_OUTPUT, GPIO_CFG_PULL_UP, GPIO_CFG_8MA), "sdc2_cmd"},
5566 {GPIO_CFG(66, 1, GPIO_CFG_OUTPUT, GPIO_CFG_PULL_UP, GPIO_CFG_8MA), "sdc2_dat_3"},
5567 {GPIO_CFG(67, 1, GPIO_CFG_OUTPUT, GPIO_CFG_PULL_UP, GPIO_CFG_8MA), "sdc2_dat_2"},
5568 {GPIO_CFG(68, 1, GPIO_CFG_OUTPUT, GPIO_CFG_PULL_UP, GPIO_CFG_8MA), "sdc2_dat_1"},
5569 {GPIO_CFG(69, 1, GPIO_CFG_OUTPUT, GPIO_CFG_PULL_UP, GPIO_CFG_8MA), "sdc2_dat_0"},
5570
5571#ifdef CONFIG_MMC_MSM_SDC2_8_BIT_SUPPORT
5572 {GPIO_CFG(115, 1, GPIO_CFG_OUTPUT, GPIO_CFG_PULL_UP, GPIO_CFG_8MA), "sdc2_dat_4"},
5573 {GPIO_CFG(114, 1, GPIO_CFG_OUTPUT, GPIO_CFG_PULL_UP, GPIO_CFG_8MA), "sdc2_dat_5"},
5574 {GPIO_CFG(113, 1, GPIO_CFG_OUTPUT, GPIO_CFG_PULL_UP, GPIO_CFG_8MA), "sdc2_dat_6"},
5575 {GPIO_CFG(112, 1, GPIO_CFG_OUTPUT, GPIO_CFG_PULL_UP, GPIO_CFG_8MA), "sdc2_dat_7"},
5576#endif
5577};
5578
5579static struct msm_gpio sdc3_cfg_data[] = {
5580 {GPIO_CFG(110, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_16MA), "sdc3_clk"},
5581 {GPIO_CFG(111, 1, GPIO_CFG_OUTPUT, GPIO_CFG_PULL_UP, GPIO_CFG_8MA), "sdc3_cmd"},
5582 {GPIO_CFG(116, 1, GPIO_CFG_OUTPUT, GPIO_CFG_PULL_UP, GPIO_CFG_8MA), "sdc3_dat_3"},
5583 {GPIO_CFG(117, 1, GPIO_CFG_OUTPUT, GPIO_CFG_PULL_UP, GPIO_CFG_8MA), "sdc3_dat_2"},
5584 {GPIO_CFG(118, 1, GPIO_CFG_OUTPUT, GPIO_CFG_PULL_UP, GPIO_CFG_8MA), "sdc3_dat_1"},
5585 {GPIO_CFG(119, 1, GPIO_CFG_OUTPUT, GPIO_CFG_PULL_UP, GPIO_CFG_8MA), "sdc3_dat_0"},
5586};
5587
5588static struct msm_gpio sdc3_sleep_cfg_data[] = {
5589 {GPIO_CFG(110, 0, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA),
5590 "sdc3_clk"},
5591 {GPIO_CFG(111, 0, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA),
5592 "sdc3_cmd"},
5593 {GPIO_CFG(116, 0, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA),
5594 "sdc3_dat_3"},
5595 {GPIO_CFG(117, 0, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA),
5596 "sdc3_dat_2"},
5597 {GPIO_CFG(118, 0, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA),
5598 "sdc3_dat_1"},
5599 {GPIO_CFG(119, 0, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA),
5600 "sdc3_dat_0"},
5601};
5602
5603static struct msm_gpio sdc4_cfg_data[] = {
5604 {GPIO_CFG(58, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_16MA), "sdc4_clk"},
5605 {GPIO_CFG(59, 1, GPIO_CFG_OUTPUT, GPIO_CFG_PULL_UP, GPIO_CFG_8MA), "sdc4_cmd"},
5606 {GPIO_CFG(60, 1, GPIO_CFG_OUTPUT, GPIO_CFG_PULL_UP, GPIO_CFG_8MA), "sdc4_dat_3"},
5607 {GPIO_CFG(61, 1, GPIO_CFG_OUTPUT, GPIO_CFG_PULL_UP, GPIO_CFG_8MA), "sdc4_dat_2"},
5608 {GPIO_CFG(62, 1, GPIO_CFG_OUTPUT, GPIO_CFG_PULL_UP, GPIO_CFG_8MA), "sdc4_dat_1"},
5609 {GPIO_CFG(63, 1, GPIO_CFG_OUTPUT, GPIO_CFG_PULL_UP, GPIO_CFG_8MA), "sdc4_dat_0"},
5610};
5611
5612static struct sdcc_gpio sdcc_cfg_data[] = {
5613 {
5614 .cfg_data = sdc1_cfg_data,
5615 .size = ARRAY_SIZE(sdc1_cfg_data),
5616 .sleep_cfg_data = NULL,
5617 },
5618 {
5619 .cfg_data = sdc2_cfg_data,
5620 .size = ARRAY_SIZE(sdc2_cfg_data),
5621 .sleep_cfg_data = NULL,
5622 },
5623 {
5624 .cfg_data = sdc3_cfg_data,
5625 .size = ARRAY_SIZE(sdc3_cfg_data),
5626 .sleep_cfg_data = sdc3_sleep_cfg_data,
5627 },
5628 {
5629 .cfg_data = sdc4_cfg_data,
5630 .size = ARRAY_SIZE(sdc4_cfg_data),
5631 .sleep_cfg_data = NULL,
5632 },
5633};
5634
5635struct sdcc_vreg {
5636 struct vreg *vreg_data;
5637 unsigned level;
5638};
5639
5640static struct sdcc_vreg sdcc_vreg_data[4];
5641
5642static unsigned long vreg_sts, gpio_sts;
5643
5644static uint32_t msm_sdcc_setup_gpio(int dev_id, unsigned int enable)
5645{
5646 int rc = 0;
5647 struct sdcc_gpio *curr;
5648
5649 curr = &sdcc_cfg_data[dev_id - 1];
5650
5651 if (!(test_bit(dev_id, &gpio_sts)^enable))
5652 return rc;
5653
5654 if (enable) {
5655 set_bit(dev_id, &gpio_sts);
5656 rc = msm_gpios_request_enable(curr->cfg_data, curr->size);
5657 if (rc)
5658 printk(KERN_ERR "%s: Failed to turn on GPIOs for slot %d\n",
5659 __func__, dev_id);
5660 } else {
5661 clear_bit(dev_id, &gpio_sts);
5662 if (curr->sleep_cfg_data) {
5663 msm_gpios_enable(curr->sleep_cfg_data, curr->size);
5664 msm_gpios_free(curr->sleep_cfg_data, curr->size);
5665 } else {
5666 msm_gpios_disable_free(curr->cfg_data, curr->size);
5667 }
5668 }
5669
5670 return rc;
5671}
5672
5673static uint32_t msm_sdcc_setup_vreg(int dev_id, unsigned int enable)
5674{
5675 int rc = 0;
5676 struct sdcc_vreg *curr;
5677 static int enabled_once[] = {0, 0, 0, 0};
5678
5679 curr = &sdcc_vreg_data[dev_id - 1];
5680
5681 if (!(test_bit(dev_id, &vreg_sts)^enable))
5682 return rc;
5683
5684 if (!enable || enabled_once[dev_id - 1])
5685 return 0;
5686
5687 if (enable) {
5688 set_bit(dev_id, &vreg_sts);
5689 rc = vreg_set_level(curr->vreg_data, curr->level);
5690 if (rc) {
5691 printk(KERN_ERR "%s: vreg_set_level() = %d \n",
5692 __func__, rc);
5693 }
5694 rc = vreg_enable(curr->vreg_data);
5695 if (rc) {
5696 printk(KERN_ERR "%s: vreg_enable() = %d \n",
5697 __func__, rc);
5698 }
5699 enabled_once[dev_id - 1] = 1;
5700 } else {
5701 clear_bit(dev_id, &vreg_sts);
5702 rc = vreg_disable(curr->vreg_data);
5703 if (rc) {
5704 printk(KERN_ERR "%s: vreg_disable() = %d \n",
5705 __func__, rc);
5706 }
5707 }
5708 return rc;
5709}
5710
5711static uint32_t msm_sdcc_setup_power(struct device *dv, unsigned int vdd)
5712{
5713 int rc = 0;
5714 struct platform_device *pdev;
5715
5716 pdev = container_of(dv, struct platform_device, dev);
5717 rc = msm_sdcc_setup_gpio(pdev->id, (vdd ? 1 : 0));
5718 if (rc)
5719 goto out;
5720
5721 if (pdev->id == 4) /* S3 is always ON and cannot be disabled */
5722 rc = msm_sdcc_setup_vreg(pdev->id, (vdd ? 1 : 0));
5723out:
5724 return rc;
5725}
5726
5727#if defined(CONFIG_MMC_MSM_SDC1_SUPPORT) && \
5728 defined(CONFIG_CSDIO_VENDOR_ID) && \
5729 defined(CONFIG_CSDIO_DEVICE_ID) && \
5730 (CONFIG_CSDIO_VENDOR_ID == 0x70 && CONFIG_CSDIO_DEVICE_ID == 0x1117)
5731
5732#define MBP_ON 1
5733#define MBP_OFF 0
5734
5735#define MBP_RESET_N \
5736 GPIO_CFG(44, 0, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_8MA)
5737#define MBP_INT0 \
5738 GPIO_CFG(46, 0, GPIO_CFG_INPUT, GPIO_CFG_PULL_UP, GPIO_CFG_8MA)
5739
5740#define MBP_MODE_CTRL_0 \
5741 GPIO_CFG(35, 0, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA)
5742#define MBP_MODE_CTRL_1 \
5743 GPIO_CFG(36, 0, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA)
5744#define MBP_MODE_CTRL_2 \
5745 GPIO_CFG(34, 0, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA)
5746#define TSIF_EN \
5747 GPIO_CFG(35, 1, GPIO_CFG_INPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA)
5748#define TSIF_DATA \
5749 GPIO_CFG(36, 1, GPIO_CFG_INPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA)
5750#define TSIF_CLK \
5751 GPIO_CFG(34, 1, GPIO_CFG_INPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA)
5752
5753static struct msm_gpio mbp_cfg_data[] = {
5754 {GPIO_CFG(44, 0, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_16MA),
5755 "mbp_reset"},
5756 {GPIO_CFG(85, 0, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_16MA),
5757 "mbp_io_voltage"},
5758};
5759
5760static int mbp_config_gpios_pre_init(int enable)
5761{
5762 int rc = 0;
5763
5764 if (enable) {
5765 rc = msm_gpios_request_enable(mbp_cfg_data,
5766 ARRAY_SIZE(mbp_cfg_data));
5767 if (rc) {
5768 printk(KERN_ERR
5769 "%s: Failed to turnon GPIOs for mbp chip(%d)\n",
5770 __func__, rc);
5771 }
5772 } else
5773 msm_gpios_disable_free(mbp_cfg_data, ARRAY_SIZE(mbp_cfg_data));
5774 return rc;
5775}
5776
5777static int mbp_setup_rf_vregs(int state)
5778{
5779 struct vreg *vreg_rf = NULL;
5780 struct vreg *vreg_rf_switch = NULL;
5781 int rc;
5782
5783 vreg_rf = vreg_get(NULL, "s2");
5784 if (IS_ERR(vreg_rf)) {
5785 pr_err("%s: s2 vreg get failed (%ld)",
5786 __func__, PTR_ERR(vreg_rf));
5787 return -EFAULT;
5788 }
5789 vreg_rf_switch = vreg_get(NULL, "rf");
5790 if (IS_ERR(vreg_rf_switch)) {
5791 pr_err("%s: rf vreg get failed (%ld)",
5792 __func__, PTR_ERR(vreg_rf_switch));
5793 return -EFAULT;
5794 }
5795
5796 if (state) {
5797 rc = vreg_set_level(vreg_rf, 1300);
5798 if (rc) {
5799 pr_err("%s: vreg s2 set level failed (%d)\n",
5800 __func__, rc);
5801 return rc;
5802 }
5803
5804 rc = vreg_enable(vreg_rf);
5805 if (rc) {
5806 printk(KERN_ERR "%s: vreg_enable(s2) = %d\n",
5807 __func__, rc);
5808 }
5809
5810 rc = vreg_set_level(vreg_rf_switch, 2600);
5811 if (rc) {
5812 pr_err("%s: vreg rf switch set level failed (%d)\n",
5813 __func__, rc);
5814 return rc;
5815 }
5816 rc = vreg_enable(vreg_rf_switch);
5817 if (rc) {
5818 printk(KERN_ERR "%s: vreg_enable(rf) = %d\n",
5819 __func__, rc);
5820 }
5821 } else {
5822 (void) vreg_disable(vreg_rf);
5823 (void) vreg_disable(vreg_rf_switch);
5824 }
5825 return 0;
5826}
5827
5828static int mbp_setup_vregs(int state)
5829{
5830 struct vreg *vreg_analog = NULL;
5831 struct vreg *vreg_io = NULL;
5832 int rc;
5833
5834 vreg_analog = vreg_get(NULL, "gp4");
5835 if (IS_ERR(vreg_analog)) {
5836 pr_err("%s: gp4 vreg get failed (%ld)",
5837 __func__, PTR_ERR(vreg_analog));
5838 return -EFAULT;
5839 }
5840 vreg_io = vreg_get(NULL, "s3");
5841 if (IS_ERR(vreg_io)) {
5842 pr_err("%s: s3 vreg get failed (%ld)",
5843 __func__, PTR_ERR(vreg_io));
5844 return -EFAULT;
5845 }
5846 if (state) {
5847 rc = vreg_set_level(vreg_analog, 2600);
5848 if (rc) {
5849 pr_err("%s: vreg_set_level failed (%d)",
5850 __func__, rc);
5851 }
5852 rc = vreg_enable(vreg_analog);
5853 if (rc) {
5854 pr_err("%s: analog vreg enable failed (%d)",
5855 __func__, rc);
5856 }
5857 rc = vreg_set_level(vreg_io, 1800);
5858 if (rc) {
5859 pr_err("%s: vreg_set_level failed (%d)",
5860 __func__, rc);
5861 }
5862 rc = vreg_enable(vreg_io);
5863 if (rc) {
5864 pr_err("%s: io vreg enable failed (%d)",
5865 __func__, rc);
5866 }
5867 } else {
5868 rc = vreg_disable(vreg_analog);
5869 if (rc) {
5870 pr_err("%s: analog vreg disable failed (%d)",
5871 __func__, rc);
5872 }
5873 rc = vreg_disable(vreg_io);
5874 if (rc) {
5875 pr_err("%s: io vreg disable failed (%d)",
5876 __func__, rc);
5877 }
5878 }
5879 return rc;
5880}
5881
5882static int mbp_set_tcxo_en(int enable)
5883{
5884 int rc;
5885 const char *id = "UBMC";
5886 struct vreg *vreg_analog = NULL;
5887
5888 rc = pmapp_clock_vote(id, PMAPP_CLOCK_ID_A1,
5889 enable ? PMAPP_CLOCK_VOTE_ON : PMAPP_CLOCK_VOTE_OFF);
5890 if (rc < 0) {
5891 printk(KERN_ERR "%s: unable to %svote for a1 clk\n",
5892 __func__, enable ? "" : "de-");
5893 return -EIO;
5894 }
5895 if (!enable) {
5896 vreg_analog = vreg_get(NULL, "gp4");
5897 if (IS_ERR(vreg_analog)) {
5898 pr_err("%s: gp4 vreg get failed (%ld)",
5899 __func__, PTR_ERR(vreg_analog));
5900 return -EFAULT;
5901 }
5902
5903 (void) vreg_disable(vreg_analog);
5904 }
5905 return rc;
5906}
5907
5908static void mbp_set_freeze_io(int state)
5909{
5910 if (state)
5911 gpio_set_value(85, 0);
5912 else
5913 gpio_set_value(85, 1);
5914}
5915
5916static int mbp_set_core_voltage_en(int enable)
5917{
5918 int rc;
5919 struct vreg *vreg_core1p2 = NULL;
5920
5921 vreg_core1p2 = vreg_get(NULL, "gp16");
5922 if (IS_ERR(vreg_core1p2)) {
5923 pr_err("%s: gp16 vreg get failed (%ld)",
5924 __func__, PTR_ERR(vreg_core1p2));
5925 return -EFAULT;
5926 }
5927 if (enable) {
5928 rc = vreg_set_level(vreg_core1p2, 1200);
5929 if (rc) {
5930 pr_err("%s: vreg_set_level failed (%d)",
5931 __func__, rc);
5932 }
5933 (void) vreg_enable(vreg_core1p2);
5934
5935 return 80;
5936 } else {
5937 gpio_set_value(85, 1);
5938 return 0;
5939 }
5940 return rc;
5941}
5942
5943static void mbp_set_reset(int state)
5944{
5945 if (state)
5946 gpio_set_value(GPIO_PIN(MBP_RESET_N), 0);
5947 else
5948 gpio_set_value(GPIO_PIN(MBP_RESET_N), 1);
5949}
5950
5951static int mbp_config_interface_mode(int state)
5952{
5953 if (state) {
5954 gpio_tlmm_config(MBP_MODE_CTRL_0, GPIO_CFG_ENABLE);
5955 gpio_tlmm_config(MBP_MODE_CTRL_1, GPIO_CFG_ENABLE);
5956 gpio_tlmm_config(MBP_MODE_CTRL_2, GPIO_CFG_ENABLE);
5957 gpio_set_value(GPIO_PIN(MBP_MODE_CTRL_0), 0);
5958 gpio_set_value(GPIO_PIN(MBP_MODE_CTRL_1), 1);
5959 gpio_set_value(GPIO_PIN(MBP_MODE_CTRL_2), 0);
5960 } else {
5961 gpio_tlmm_config(MBP_MODE_CTRL_0, GPIO_CFG_DISABLE);
5962 gpio_tlmm_config(MBP_MODE_CTRL_1, GPIO_CFG_DISABLE);
5963 gpio_tlmm_config(MBP_MODE_CTRL_2, GPIO_CFG_DISABLE);
5964 }
5965 return 0;
5966}
5967
5968static int mbp_setup_adc_vregs(int state)
5969{
5970 struct vreg *vreg_adc = NULL;
5971 int rc;
5972
5973 vreg_adc = vreg_get(NULL, "s4");
5974 if (IS_ERR(vreg_adc)) {
5975 pr_err("%s: s4 vreg get failed (%ld)",
5976 __func__, PTR_ERR(vreg_adc));
5977 return -EFAULT;
5978 }
5979 if (state) {
5980 rc = vreg_set_level(vreg_adc, 2200);
5981 if (rc) {
5982 pr_err("%s: vreg_set_level failed (%d)",
5983 __func__, rc);
5984 }
5985 rc = vreg_enable(vreg_adc);
5986 if (rc) {
5987 pr_err("%s: enable vreg adc failed (%d)",
5988 __func__, rc);
5989 }
5990 } else {
5991 rc = vreg_disable(vreg_adc);
5992 if (rc) {
5993 pr_err("%s: disable vreg adc failed (%d)",
5994 __func__, rc);
5995 }
5996 }
5997 return rc;
5998}
5999
6000static int mbp_power_up(void)
6001{
6002 int rc;
6003
6004 rc = mbp_config_gpios_pre_init(MBP_ON);
6005 if (rc)
6006 goto exit;
6007 pr_debug("%s: mbp_config_gpios_pre_init() done\n", __func__);
6008
6009 rc = mbp_setup_vregs(MBP_ON);
6010 if (rc)
6011 goto exit;
6012 pr_debug("%s: gp4 (2.6) and s3 (1.8) done\n", __func__);
6013
6014 rc = mbp_set_tcxo_en(MBP_ON);
6015 if (rc)
6016 goto exit;
6017 pr_debug("%s: tcxo clock done\n", __func__);
6018
6019 mbp_set_freeze_io(MBP_OFF);
6020 pr_debug("%s: set gpio 85 to 1 done\n", __func__);
6021
6022 udelay(100);
6023 mbp_set_reset(MBP_ON);
6024
6025 udelay(300);
6026 rc = mbp_config_interface_mode(MBP_ON);
6027 if (rc)
6028 goto exit;
6029 pr_debug("%s: mbp_config_interface_mode() done\n", __func__);
6030
6031 udelay(100 + mbp_set_core_voltage_en(MBP_ON));
6032 pr_debug("%s: power gp16 1.2V done\n", __func__);
6033
6034 mbp_set_freeze_io(MBP_ON);
6035 pr_debug("%s: set gpio 85 to 0 done\n", __func__);
6036
6037 udelay(100);
6038
6039 rc = mbp_setup_rf_vregs(MBP_ON);
6040 if (rc)
6041 goto exit;
6042 pr_debug("%s: s2 1.3V and rf 2.6V done\n", __func__);
6043
6044 rc = mbp_setup_adc_vregs(MBP_ON);
6045 if (rc)
6046 goto exit;
6047 pr_debug("%s: s4 2.2V done\n", __func__);
6048
6049 udelay(200);
6050
6051 mbp_set_reset(MBP_OFF);
6052 pr_debug("%s: close gpio 44 done\n", __func__);
6053
6054 msleep(20);
6055exit:
6056 return rc;
6057}
6058
6059static int mbp_power_down(void)
6060{
6061 int rc;
6062 struct vreg *vreg_adc = NULL;
6063
6064 vreg_adc = vreg_get(NULL, "s4");
6065 if (IS_ERR(vreg_adc)) {
6066 pr_err("%s: s4 vreg get failed (%ld)",
6067 __func__, PTR_ERR(vreg_adc));
6068 return -EFAULT;
6069 }
6070
6071 mbp_set_reset(MBP_ON);
6072 pr_debug("%s: mbp_set_reset(MBP_ON) done\n", __func__);
6073
6074 udelay(100);
6075
6076 rc = mbp_setup_adc_vregs(MBP_OFF);
6077 if (rc)
6078 goto exit;
6079 pr_debug("%s: vreg_disable(vreg_adc) done\n", __func__);
6080
6081 udelay(5);
6082
6083 rc = mbp_setup_rf_vregs(MBP_OFF);
6084 if (rc)
6085 goto exit;
6086 pr_debug("%s: mbp_setup_rf_vregs(MBP_OFF) done\n", __func__);
6087
6088 udelay(5);
6089
6090 mbp_set_freeze_io(MBP_OFF);
6091 pr_debug("%s: mbp_set_freeze_io(MBP_OFF) done\n", __func__);
6092
6093 udelay(100);
6094 rc = mbp_set_core_voltage_en(MBP_OFF);
6095 if (rc)
6096 goto exit;
6097 pr_debug("%s: mbp_set_core_voltage_en(MBP_OFF) done\n", __func__);
6098
6099 gpio_set_value(85, 1);
6100
6101 rc = mbp_set_tcxo_en(MBP_OFF);
6102 if (rc)
6103 goto exit;
6104 pr_debug("%s: mbp_set_tcxo_en(MBP_OFF) done\n", __func__);
6105
6106 rc = mbp_config_gpios_pre_init(MBP_OFF);
6107 if (rc)
6108 goto exit;
6109exit:
6110 return rc;
6111}
6112
6113static void (*mbp_status_notify_cb)(int card_present, void *dev_id);
6114static void *mbp_status_notify_cb_devid;
6115static int mbp_power_status;
6116static int mbp_power_init_done;
6117
6118static uint32_t mbp_setup_power(struct device *dv,
6119 unsigned int power_status)
6120{
6121 int rc = 0;
6122 struct platform_device *pdev;
6123
6124 pdev = container_of(dv, struct platform_device, dev);
6125
6126 if (power_status == mbp_power_status)
6127 goto exit;
6128 if (power_status) {
6129 pr_debug("turn on power of mbp slot");
6130 rc = mbp_power_up();
6131 mbp_power_status = 1;
6132 } else {
6133 pr_debug("turn off power of mbp slot");
6134 rc = mbp_power_down();
6135 mbp_power_status = 0;
6136 }
6137exit:
6138 return rc;
6139};
6140
6141int mbp_register_status_notify(void (*callback)(int, void *),
6142 void *dev_id)
6143{
6144 mbp_status_notify_cb = callback;
6145 mbp_status_notify_cb_devid = dev_id;
6146 return 0;
6147}
6148
6149static unsigned int mbp_status(struct device *dev)
6150{
6151 return mbp_power_status;
6152}
6153
6154static uint32_t msm_sdcc_setup_power_mbp(struct device *dv, unsigned int vdd)
6155{
6156 struct platform_device *pdev;
6157 uint32_t rc = 0;
6158
6159 pdev = container_of(dv, struct platform_device, dev);
6160 rc = msm_sdcc_setup_power(dv, vdd);
6161 if (rc) {
6162 pr_err("%s: Failed to setup power (%d)\n",
6163 __func__, rc);
6164 goto out;
6165 }
6166 if (!mbp_power_init_done) {
6167 mbp_setup_power(dv, 1);
6168 mbp_setup_power(dv, 0);
6169 mbp_power_init_done = 1;
6170 }
6171 if (vdd >= 0x8000) {
6172 rc = mbp_setup_power(dv, (0x8000 == vdd) ? 0 : 1);
6173 if (rc) {
6174 pr_err("%s: Failed to config mbp chip power (%d)\n",
6175 __func__, rc);
6176 goto out;
6177 }
6178 if (mbp_status_notify_cb) {
6179 mbp_status_notify_cb(mbp_power_status,
6180 mbp_status_notify_cb_devid);
6181 }
6182 }
6183out:
6184 /* should return 0 only */
6185 return 0;
6186}
6187
6188#endif
6189
6190#endif
6191
6192#ifdef CONFIG_MMC_MSM_SDC4_SUPPORT
6193#ifdef CONFIG_MMC_MSM_CARD_HW_DETECTION
6194static unsigned int msm7x30_sdcc_slot_status(struct device *dev)
6195{
6196 return (unsigned int)
6197 gpio_get_value_cansleep(
6198 PM8058_GPIO_PM_TO_SYS(PMIC_GPIO_SD_DET - 1));
6199}
6200#endif
6201
6202static int msm_sdcc_get_wpswitch(struct device *dv)
6203{
6204 void __iomem *wp_addr = 0;
6205 uint32_t ret = 0;
6206 struct platform_device *pdev;
6207
6208 if (!(machine_is_msm7x30_surf()))
6209 return -1;
6210 pdev = container_of(dv, struct platform_device, dev);
6211
6212 wp_addr = ioremap(FPGA_SDCC_STATUS, 4);
6213 if (!wp_addr) {
6214 pr_err("%s: Could not remap %x\n", __func__, FPGA_SDCC_STATUS);
6215 return -ENOMEM;
6216 }
6217
6218 ret = (((readl(wp_addr) >> 4) >> (pdev->id-1)) & 0x01);
6219 pr_info("%s: WP Status for Slot %d = 0x%x \n", __func__,
6220 pdev->id, ret);
6221 iounmap(wp_addr);
6222
6223 return ret;
6224}
6225#endif
6226
6227#if defined(CONFIG_MMC_MSM_SDC1_SUPPORT)
6228#if defined(CONFIG_CSDIO_VENDOR_ID) && \
6229 defined(CONFIG_CSDIO_DEVICE_ID) && \
6230 (CONFIG_CSDIO_VENDOR_ID == 0x70 && CONFIG_CSDIO_DEVICE_ID == 0x1117)
6231static struct mmc_platform_data msm7x30_sdc1_data = {
6232 .ocr_mask = MMC_VDD_165_195 | MMC_VDD_27_28 | MMC_VDD_28_29,
6233 .translate_vdd = msm_sdcc_setup_power_mbp,
6234 .mmc_bus_width = MMC_CAP_4_BIT_DATA,
6235 .status = mbp_status,
6236 .register_status_notify = mbp_register_status_notify,
6237#ifdef CONFIG_MMC_MSM_SDC1_DUMMY52_REQUIRED
6238 .dummy52_required = 1,
6239#endif
6240 .msmsdcc_fmin = 144000,
6241 .msmsdcc_fmid = 24576000,
6242 .msmsdcc_fmax = 24576000,
6243 .nonremovable = 0,
6244};
6245#else
6246static struct mmc_platform_data msm7x30_sdc1_data = {
6247 .ocr_mask = MMC_VDD_165_195,
6248 .translate_vdd = msm_sdcc_setup_power,
6249 .mmc_bus_width = MMC_CAP_4_BIT_DATA,
6250#ifdef CONFIG_MMC_MSM_SDC1_DUMMY52_REQUIRED
6251 .dummy52_required = 1,
6252#endif
6253 .msmsdcc_fmin = 144000,
6254 .msmsdcc_fmid = 24576000,
6255 .msmsdcc_fmax = 49152000,
6256 .nonremovable = 0,
6257};
6258#endif
6259#endif
6260
6261#ifdef CONFIG_MMC_MSM_SDC2_SUPPORT
6262static struct mmc_platform_data msm7x30_sdc2_data = {
6263 .ocr_mask = MMC_VDD_165_195 | MMC_VDD_27_28,
6264 .translate_vdd = msm_sdcc_setup_power,
6265#ifdef CONFIG_MMC_MSM_SDC2_8_BIT_SUPPORT
6266 .mmc_bus_width = MMC_CAP_8_BIT_DATA,
6267#else
6268 .mmc_bus_width = MMC_CAP_4_BIT_DATA,
6269#endif
6270#ifdef CONFIG_MMC_MSM_SDC2_DUMMY52_REQUIRED
6271 .dummy52_required = 1,
6272#endif
6273 .msmsdcc_fmin = 144000,
6274 .msmsdcc_fmid = 24576000,
6275 .msmsdcc_fmax = 49152000,
6276 .nonremovable = 1,
6277};
6278#endif
6279
6280#ifdef CONFIG_MMC_MSM_SDC3_SUPPORT
6281static struct mmc_platform_data msm7x30_sdc3_data = {
6282 .ocr_mask = MMC_VDD_27_28 | MMC_VDD_28_29,
6283 .translate_vdd = msm_sdcc_setup_power,
6284 .mmc_bus_width = MMC_CAP_4_BIT_DATA,
6285#ifdef CONFIG_MMC_MSM_SDIO_SUPPORT
6286 .sdiowakeup_irq = MSM_GPIO_TO_INT(118),
6287#endif
6288#ifdef CONFIG_MMC_MSM_SDC3_DUMMY52_REQUIRED
6289 .dummy52_required = 1,
6290#endif
6291 .msmsdcc_fmin = 144000,
6292 .msmsdcc_fmid = 24576000,
6293 .msmsdcc_fmax = 49152000,
6294 .nonremovable = 0,
6295};
6296#endif
6297
6298#ifdef CONFIG_MMC_MSM_SDC4_SUPPORT
6299static struct mmc_platform_data msm7x30_sdc4_data = {
6300 .ocr_mask = MMC_VDD_27_28 | MMC_VDD_28_29,
6301 .translate_vdd = msm_sdcc_setup_power,
6302 .mmc_bus_width = MMC_CAP_4_BIT_DATA,
6303#ifdef CONFIG_MMC_MSM_CARD_HW_DETECTION
6304 .status = msm7x30_sdcc_slot_status,
6305 .status_irq = PM8058_GPIO_IRQ(PMIC8058_IRQ_BASE, PMIC_GPIO_SD_DET - 1),
6306 .irq_flags = IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING,
6307#endif
6308 .wpswitch = msm_sdcc_get_wpswitch,
6309#ifdef CONFIG_MMC_MSM_SDC4_DUMMY52_REQUIRED
6310 .dummy52_required = 1,
6311#endif
6312 .msmsdcc_fmin = 144000,
6313 .msmsdcc_fmid = 24576000,
6314 .msmsdcc_fmax = 49152000,
6315 .nonremovable = 0,
6316};
6317#endif
6318
6319#ifdef CONFIG_MMC_MSM_SDC1_SUPPORT
6320static void msm_sdc1_lvlshft_enable(void)
6321{
6322 int rc;
6323
6324 /* Enable LDO5, an input to the FET that powers slot 1 */
6325 rc = vreg_set_level(vreg_mmc, 2850);
6326 if (rc)
6327 printk(KERN_ERR "%s: vreg_set_level() = %d \n", __func__, rc);
6328
6329 rc = vreg_enable(vreg_mmc);
6330 if (rc)
6331 printk(KERN_ERR "%s: vreg_enable() = %d \n", __func__, rc);
6332
6333 /* Enable GPIO 35, to turn on the FET that powers slot 1 */
6334 rc = msm_gpios_request_enable(sdc1_lvlshft_cfg_data,
6335 ARRAY_SIZE(sdc1_lvlshft_cfg_data));
6336 if (rc)
6337 printk(KERN_ERR "%s: Failed to enable GPIO 35\n", __func__);
6338
6339 rc = gpio_direction_output(GPIO_PIN(sdc1_lvlshft_cfg_data[0].gpio_cfg),
6340 1);
6341 if (rc)
6342 printk(KERN_ERR "%s: Failed to turn on GPIO 35\n", __func__);
6343}
6344#endif
6345
6346static void __init msm7x30_init_mmc(void)
6347{
6348 vreg_s3 = vreg_get(NULL, "s3");
6349 if (IS_ERR(vreg_s3)) {
6350 printk(KERN_ERR "%s: vreg get failed (%ld)\n",
6351 __func__, PTR_ERR(vreg_s3));
6352 return;
6353 }
6354
6355 vreg_mmc = vreg_get(NULL, "mmc");
6356 if (IS_ERR(vreg_mmc)) {
6357 printk(KERN_ERR "%s: vreg get failed (%ld)\n",
6358 __func__, PTR_ERR(vreg_mmc));
6359 return;
6360 }
6361
6362#ifdef CONFIG_MMC_MSM_SDC1_SUPPORT
6363 if (machine_is_msm7x30_fluid()) {
6364 msm7x30_sdc1_data.ocr_mask = MMC_VDD_27_28 | MMC_VDD_28_29;
6365 msm_sdc1_lvlshft_enable();
6366 }
6367 sdcc_vreg_data[0].vreg_data = vreg_s3;
6368 sdcc_vreg_data[0].level = 1800;
6369 msm_add_sdcc(1, &msm7x30_sdc1_data);
6370#endif
6371#ifdef CONFIG_MMC_MSM_SDC2_SUPPORT
6372 if (machine_is_msm8x55_svlte_surf())
6373 msm7x30_sdc2_data.msmsdcc_fmax = 24576000;
6374 sdcc_vreg_data[1].vreg_data = vreg_s3;
6375 sdcc_vreg_data[1].level = 1800;
6376 msm_add_sdcc(2, &msm7x30_sdc2_data);
6377#endif
6378#ifdef CONFIG_MMC_MSM_SDC3_SUPPORT
6379 sdcc_vreg_data[2].vreg_data = vreg_s3;
6380 sdcc_vreg_data[2].level = 1800;
6381 msm_sdcc_setup_gpio(3, 1);
6382 msm_add_sdcc(3, &msm7x30_sdc3_data);
6383#endif
6384#ifdef CONFIG_MMC_MSM_SDC4_SUPPORT
6385 sdcc_vreg_data[3].vreg_data = vreg_mmc;
6386 sdcc_vreg_data[3].level = 2850;
6387 msm_add_sdcc(4, &msm7x30_sdc4_data);
6388#endif
6389
6390}
6391
6392static void __init msm7x30_init_nand(void)
6393{
6394 char *build_id;
6395 struct flash_platform_data *plat_data;
6396
6397 build_id = socinfo_get_build_id();
6398 if (build_id == NULL) {
6399 pr_err("%s: Build ID not available from socinfo\n", __func__);
6400 return;
6401 }
6402
6403 if (build_id[8] == 'C' &&
6404 !msm_gpios_request_enable(msm_nand_ebi2_cfg_data,
6405 ARRAY_SIZE(msm_nand_ebi2_cfg_data))) {
6406 plat_data = msm_device_nand.dev.platform_data;
6407 plat_data->interleave = 1;
6408 printk(KERN_INFO "%s: Interleave mode Build ID found\n",
6409 __func__);
6410 }
6411}
6412
6413#ifdef CONFIG_SERIAL_MSM_CONSOLE
6414static struct msm_gpio uart2_config_data[] = {
6415 { GPIO_CFG(49, 2, GPIO_CFG_OUTPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA), "UART2_RFR"},
6416 { GPIO_CFG(50, 2, GPIO_CFG_INPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA), "UART2_CTS"},
6417 { GPIO_CFG(51, 2, GPIO_CFG_INPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA), "UART2_Rx"},
6418 { GPIO_CFG(52, 2, GPIO_CFG_OUTPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA), "UART2_Tx"},
6419};
6420
6421static void msm7x30_init_uart2(void)
6422{
6423 msm_gpios_request_enable(uart2_config_data,
6424 ARRAY_SIZE(uart2_config_data));
6425
6426}
6427#endif
6428
6429/* TSIF begin */
6430#if defined(CONFIG_TSIF) || defined(CONFIG_TSIF_MODULE)
6431
6432#define TSIF_B_SYNC GPIO_CFG(37, 1, GPIO_CFG_INPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA)
6433#define TSIF_B_DATA GPIO_CFG(36, 1, GPIO_CFG_INPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA)
6434#define TSIF_B_EN GPIO_CFG(35, 1, GPIO_CFG_INPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA)
6435#define TSIF_B_CLK GPIO_CFG(34, 1, GPIO_CFG_INPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA)
6436
6437static const struct msm_gpio tsif_gpios[] = {
6438 { .gpio_cfg = TSIF_B_CLK, .label = "tsif_clk", },
6439 { .gpio_cfg = TSIF_B_EN, .label = "tsif_en", },
6440 { .gpio_cfg = TSIF_B_DATA, .label = "tsif_data", },
6441 { .gpio_cfg = TSIF_B_SYNC, .label = "tsif_sync", },
6442};
6443
6444static struct msm_tsif_platform_data tsif_platform_data = {
6445 .num_gpios = ARRAY_SIZE(tsif_gpios),
6446 .gpios = tsif_gpios,
6447 .tsif_pclk = "tsif_pclk",
6448 .tsif_ref_clk = "tsif_ref_clk",
6449};
6450#endif /* defined(CONFIG_TSIF) || defined(CONFIG_TSIF_MODULE) */
6451/* TSIF end */
6452
6453static void __init pmic8058_leds_init(void)
6454{
6455 if (machine_is_msm7x30_surf()) {
6456 pm8058_7x30_data.sub_devices[PM8058_SUBDEV_LED].platform_data
6457 = &pm8058_surf_leds_data;
6458 } else if (!machine_is_msm7x30_fluid()) {
6459 pm8058_7x30_data.sub_devices[PM8058_SUBDEV_LED].platform_data
6460 = &pm8058_ffa_leds_data;
6461 } else if (machine_is_msm7x30_fluid()) {
6462 pm8058_7x30_data.sub_devices[PM8058_SUBDEV_LED].platform_data
6463 = &pm8058_fluid_leds_data;
6464 }
6465}
6466
6467static struct msm_spm_platform_data msm_spm_data __initdata = {
6468 .reg_base_addr = MSM_SAW_BASE,
6469
6470 .reg_init_values[MSM_SPM_REG_SAW_CFG] = 0x05,
6471 .reg_init_values[MSM_SPM_REG_SAW_SPM_CTL] = 0x18,
6472 .reg_init_values[MSM_SPM_REG_SAW_SPM_SLP_TMR_DLY] = 0x00006666,
6473 .reg_init_values[MSM_SPM_REG_SAW_SPM_WAKE_TMR_DLY] = 0xFF000666,
6474
6475 .reg_init_values[MSM_SPM_REG_SAW_SLP_CLK_EN] = 0x01,
6476 .reg_init_values[MSM_SPM_REG_SAW_SLP_HSFS_PRECLMP_EN] = 0x03,
6477 .reg_init_values[MSM_SPM_REG_SAW_SLP_HSFS_POSTCLMP_EN] = 0x00,
6478
6479 .reg_init_values[MSM_SPM_REG_SAW_SLP_CLMP_EN] = 0x01,
6480 .reg_init_values[MSM_SPM_REG_SAW_SLP_RST_EN] = 0x00,
6481 .reg_init_values[MSM_SPM_REG_SAW_SPM_MPM_CFG] = 0x00,
6482
6483 .awake_vlevel = 0xF2,
6484 .retention_vlevel = 0xE0,
6485 .collapse_vlevel = 0x72,
6486 .retention_mid_vlevel = 0xE0,
6487 .collapse_mid_vlevel = 0xE0,
6488
6489 .vctl_timeout_us = 50,
6490};
6491
6492#if defined(CONFIG_TOUCHSCREEN_TSC2007) || \
6493 defined(CONFIG_TOUCHSCREEN_TSC2007_MODULE)
6494
6495#define TSC2007_TS_PEN_INT 20
6496
6497static struct msm_gpio tsc2007_config_data[] = {
6498 { GPIO_CFG(TSC2007_TS_PEN_INT, 0, GPIO_CFG_INPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA),
6499 "tsc2007_irq" },
6500};
6501
6502static struct vreg *vreg_tsc_s3;
6503static struct vreg *vreg_tsc_s2;
6504
6505static int tsc2007_init(void)
6506{
6507 int rc;
6508
6509 vreg_tsc_s3 = vreg_get(NULL, "s3");
6510 if (IS_ERR(vreg_tsc_s3)) {
6511 printk(KERN_ERR "%s: vreg get failed (%ld)\n",
6512 __func__, PTR_ERR(vreg_tsc_s3));
6513 return -ENODEV;
6514 }
6515
6516 rc = vreg_set_level(vreg_tsc_s3, 1800);
6517 if (rc) {
6518 pr_err("%s: vreg_set_level failed \n", __func__);
6519 goto fail_vreg_set_level;
6520 }
6521
6522 rc = vreg_enable(vreg_tsc_s3);
6523 if (rc) {
6524 pr_err("%s: vreg_enable failed \n", __func__);
6525 goto fail_vreg_set_level;
6526 }
6527
6528 vreg_tsc_s2 = vreg_get(NULL, "s2");
6529 if (IS_ERR(vreg_tsc_s2)) {
6530 printk(KERN_ERR "%s: vreg get failed (%ld)\n",
6531 __func__, PTR_ERR(vreg_tsc_s2));
6532 goto fail_vreg_get;
6533 }
6534
6535 rc = vreg_set_level(vreg_tsc_s2, 1300);
6536 if (rc) {
6537 pr_err("%s: vreg_set_level failed \n", __func__);
6538 goto fail_vreg_s2_level;
6539 }
6540
6541 rc = vreg_enable(vreg_tsc_s2);
6542 if (rc) {
6543 pr_err("%s: vreg_enable failed \n", __func__);
6544 goto fail_vreg_s2_level;
6545 }
6546
6547 rc = msm_gpios_request_enable(tsc2007_config_data,
6548 ARRAY_SIZE(tsc2007_config_data));
6549 if (rc) {
6550 pr_err("%s: Unable to request gpios\n", __func__);
6551 goto fail_gpio_req;
6552 }
6553
6554 return 0;
6555
6556fail_gpio_req:
6557 vreg_disable(vreg_tsc_s2);
6558fail_vreg_s2_level:
6559 vreg_put(vreg_tsc_s2);
6560fail_vreg_get:
6561 vreg_disable(vreg_tsc_s3);
6562fail_vreg_set_level:
6563 vreg_put(vreg_tsc_s3);
6564 return rc;
6565}
6566
6567static int tsc2007_get_pendown_state(void)
6568{
6569 int rc;
6570
6571 rc = gpio_get_value(TSC2007_TS_PEN_INT);
6572 if (rc < 0) {
6573 pr_err("%s: MSM GPIO %d read failed\n", __func__,
6574 TSC2007_TS_PEN_INT);
6575 return rc;
6576 }
6577
6578 return (rc == 0 ? 1 : 0);
6579}
6580
6581static void tsc2007_exit(void)
6582{
6583 vreg_disable(vreg_tsc_s3);
6584 vreg_put(vreg_tsc_s3);
6585 vreg_disable(vreg_tsc_s2);
6586 vreg_put(vreg_tsc_s2);
6587
6588 msm_gpios_disable_free(tsc2007_config_data,
6589 ARRAY_SIZE(tsc2007_config_data));
6590}
6591
6592static int tsc2007_power_shutdown(bool enable)
6593{
6594 int rc;
6595
6596 if (enable == false) {
6597 rc = vreg_enable(vreg_tsc_s2);
6598 if (rc) {
6599 pr_err("%s: vreg_enable failed\n", __func__);
6600 return rc;
6601 }
6602 rc = vreg_enable(vreg_tsc_s3);
6603 if (rc) {
6604 pr_err("%s: vreg_enable failed\n", __func__);
6605 vreg_disable(vreg_tsc_s2);
6606 return rc;
6607 }
6608 /* Voltage settling delay */
6609 msleep(20);
6610 } else {
6611 rc = vreg_disable(vreg_tsc_s2);
6612 if (rc) {
6613 pr_err("%s: vreg_disable failed\n", __func__);
6614 return rc;
6615 }
6616 rc = vreg_disable(vreg_tsc_s3);
6617 if (rc) {
6618 pr_err("%s: vreg_disable failed\n", __func__);
6619 vreg_enable(vreg_tsc_s2);
6620 return rc;
6621 }
6622 }
6623
6624 return rc;
6625}
6626
6627static struct tsc2007_platform_data tsc2007_ts_data = {
6628 .model = 2007,
6629 .x_plate_ohms = 300,
6630 .irq_flags = IRQF_TRIGGER_LOW,
6631 .init_platform_hw = tsc2007_init,
6632 .exit_platform_hw = tsc2007_exit,
6633 .power_shutdown = tsc2007_power_shutdown,
6634 .invert_x = true,
6635 .invert_y = true,
6636 /* REVISIT: Temporary fix for reversed pressure */
6637 .invert_z1 = true,
6638 .invert_z2 = true,
6639 .get_pendown_state = tsc2007_get_pendown_state,
6640};
6641
6642static struct i2c_board_info tsc_i2c_board_info[] = {
6643 {
6644 I2C_BOARD_INFO("tsc2007", 0x48),
6645 .irq = MSM_GPIO_TO_INT(TSC2007_TS_PEN_INT),
6646 .platform_data = &tsc2007_ts_data,
6647 },
6648};
6649#endif
6650
6651static const char *vregs_isa1200_name[] = {
6652 "gp7",
6653 "gp10",
6654};
6655
6656static const int vregs_isa1200_val[] = {
6657 1800,
6658 2600,
6659};
6660static struct vreg *vregs_isa1200[ARRAY_SIZE(vregs_isa1200_name)];
6661
6662static int isa1200_power(int vreg_on)
6663{
6664 int i, rc = 0;
6665
6666 for (i = 0; i < ARRAY_SIZE(vregs_isa1200_name); i++) {
6667 if (!vregs_isa1200[i]) {
6668 pr_err("%s: vreg_get %s failed (%d)\n",
6669 __func__, vregs_isa1200_name[i], rc);
6670 goto vreg_fail;
6671 }
6672
6673 rc = vreg_on ? vreg_enable(vregs_isa1200[i]) :
6674 vreg_disable(vregs_isa1200[i]);
6675 if (rc < 0) {
6676 pr_err("%s: vreg %s %s failed (%d)\n",
6677 __func__, vregs_isa1200_name[i],
6678 vreg_on ? "enable" : "disable", rc);
6679 goto vreg_fail;
6680 }
6681 }
6682
6683 /* vote for DO buffer */
6684 rc = pmapp_clock_vote("VIBR", PMAPP_CLOCK_ID_DO,
6685 vreg_on ? PMAPP_CLOCK_VOTE_ON : PMAPP_CLOCK_VOTE_OFF);
6686 if (rc) {
6687 pr_err("%s: unable to %svote for d0 clk\n",
6688 __func__, vreg_on ? "" : "de-");
6689 goto vreg_fail;
6690 }
6691
6692 return 0;
6693
6694vreg_fail:
6695 while (i)
6696 vreg_disable(vregs_isa1200[--i]);
6697 return rc;
6698}
6699
6700static int isa1200_dev_setup(bool enable)
6701{
6702 int i, rc;
6703
6704 if (enable == true) {
6705 for (i = 0; i < ARRAY_SIZE(vregs_isa1200_name); i++) {
6706 vregs_isa1200[i] = vreg_get(NULL,
6707 vregs_isa1200_name[i]);
6708 if (IS_ERR(vregs_isa1200[i])) {
6709 pr_err("%s: vreg get %s failed (%ld)\n",
6710 __func__, vregs_isa1200_name[i],
6711 PTR_ERR(vregs_isa1200[i]));
6712 rc = PTR_ERR(vregs_isa1200[i]);
6713 goto vreg_get_fail;
6714 }
6715 rc = vreg_set_level(vregs_isa1200[i],
6716 vregs_isa1200_val[i]);
6717 if (rc) {
6718 pr_err("%s: vreg_set_level() = %d\n",
6719 __func__, rc);
6720 goto vreg_get_fail;
6721 }
6722 }
6723
6724 rc = gpio_tlmm_config(GPIO_CFG(HAP_LVL_SHFT_MSM_GPIO, 0,
6725 GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL,
6726 GPIO_CFG_2MA), GPIO_CFG_ENABLE);
6727 if (rc) {
6728 pr_err("%s: Could not configure gpio %d\n",
6729 __func__, HAP_LVL_SHFT_MSM_GPIO);
6730 goto vreg_get_fail;
6731 }
6732
6733 rc = gpio_request(HAP_LVL_SHFT_MSM_GPIO, "haptics_shft_lvl_oe");
6734 if (rc) {
6735 pr_err("%s: unable to request gpio %d (%d)\n",
6736 __func__, HAP_LVL_SHFT_MSM_GPIO, rc);
6737 goto vreg_get_fail;
6738 }
6739
6740 gpio_set_value(HAP_LVL_SHFT_MSM_GPIO, 1);
6741 } else {
6742 for (i = 0; i < ARRAY_SIZE(vregs_isa1200_name); i++)
6743 vreg_put(vregs_isa1200[i]);
6744
6745 gpio_free(HAP_LVL_SHFT_MSM_GPIO);
6746 }
6747
6748 return 0;
6749vreg_get_fail:
6750 while (i)
6751 vreg_put(vregs_isa1200[--i]);
6752 return rc;
6753}
6754static struct isa1200_platform_data isa1200_1_pdata = {
6755 .name = "vibrator",
6756 .power_on = isa1200_power,
6757 .dev_setup = isa1200_dev_setup,
6758 .pwm_ch_id = 1, /*channel id*/
6759 /*gpio to enable haptic*/
6760 .hap_en_gpio = PM8058_GPIO_PM_TO_SYS(PMIC_GPIO_HAP_ENABLE),
6761 .max_timeout = 15000,
6762 .mode_ctrl = PWM_GEN_MODE,
6763 .pwm_fd = {
6764 .pwm_div = 256,
6765 },
6766 .is_erm = false,
6767 .smart_en = true,
6768 .ext_clk_en = true,
6769 .chip_en = 1,
6770};
6771
6772static struct i2c_board_info msm_isa1200_board_info[] = {
6773 {
6774 I2C_BOARD_INFO("isa1200_1", 0x90>>1),
6775 .platform_data = &isa1200_1_pdata,
6776 },
6777};
6778
6779
6780static int kp_flip_mpp_config(void)
6781{
6782 return pm8058_mpp_config_digital_in(PM_FLIP_MPP,
6783 PM8058_MPP_DIG_LEVEL_S3, PM_MPP_DIN_TO_INT);
6784}
6785
6786static struct flip_switch_pdata flip_switch_data = {
6787 .name = "kp_flip_switch",
6788 .flip_gpio = PM8058_GPIO_PM_TO_SYS(PM8058_GPIOS) + PM_FLIP_MPP,
6789 .left_key = KEY_OPEN,
6790 .right_key = KEY_CLOSE,
6791 .active_low = 0,
6792 .wakeup = 1,
6793 .flip_mpp_config = kp_flip_mpp_config,
6794};
6795
6796static struct platform_device flip_switch_device = {
6797 .name = "kp_flip_switch",
6798 .id = -1,
6799 .dev = {
6800 .platform_data = &flip_switch_data,
6801 }
6802};
6803
6804static const char *vregs_tma300_name[] = {
6805 "gp6",
6806 "gp7",
6807};
6808
6809static const int vregs_tma300_val[] = {
6810 3050,
6811 1800,
6812};
6813static struct vreg *vregs_tma300[ARRAY_SIZE(vregs_tma300_name)];
6814
6815static int tma300_power(int vreg_on)
6816{
6817 int i, rc = -EINVAL;
6818
6819 for (i = 0; i < ARRAY_SIZE(vregs_tma300_name); i++) {
6820 /* Never disable gp6 for fluid as lcd has a problem with it */
6821 if (!i && !vreg_on)
6822 continue;
6823 if (!vregs_tma300[i]) {
6824 printk(KERN_ERR "%s: vreg_get %s failed (%d)\n",
6825 __func__, vregs_tma300_name[i], rc);
6826 return rc;
6827 }
6828
6829 rc = vreg_on ? vreg_enable(vregs_tma300[i]) :
6830 vreg_disable(vregs_tma300[i]);
6831 if (rc < 0) {
6832 printk(KERN_ERR "%s: vreg %s %s failed (%d)\n",
6833 __func__, vregs_tma300_name[i],
6834 vreg_on ? "enable" : "disable", rc);
6835 return rc;
6836 }
6837 }
6838
6839 return 0;
6840}
6841
6842#define TS_GPIO_IRQ 150
6843
6844static int tma300_dev_setup(bool enable)
6845{
6846 int i, rc;
6847
6848 if (enable) {
6849 /* get voltage sources */
6850 for (i = 0; i < ARRAY_SIZE(vregs_tma300_name); i++) {
6851 vregs_tma300[i] = vreg_get(NULL, vregs_tma300_name[i]);
6852 if (IS_ERR(vregs_tma300[i])) {
6853 pr_err("%s: vreg get %s failed (%ld)\n",
6854 __func__, vregs_tma300_name[i],
6855 PTR_ERR(vregs_tma300[i]));
6856 rc = PTR_ERR(vregs_tma300[i]);
6857 goto vreg_get_fail;
6858 }
6859 rc = vreg_set_level(vregs_tma300[i],
6860 vregs_tma300_val[i]);
6861 if (rc) {
6862 pr_err("%s: vreg_set_level() = %d\n",
6863 __func__, rc);
6864 i++;
6865 goto vreg_get_fail;
6866 }
6867 }
6868
6869 /* enable interrupt gpio */
6870 rc = gpio_tlmm_config(GPIO_CFG(TS_GPIO_IRQ, 0, GPIO_CFG_INPUT,
6871 GPIO_CFG_PULL_UP, GPIO_CFG_6MA), GPIO_CFG_ENABLE);
6872 if (rc) {
6873 pr_err("%s: Could not configure gpio %d\n",
6874 __func__, TS_GPIO_IRQ);
6875 goto vreg_get_fail;
6876 }
6877
6878 /* virtual keys */
6879 tma300_vkeys_attr.attr.name = "virtualkeys.msm_tma300_ts";
6880 properties_kobj = kobject_create_and_add("board_properties",
6881 NULL);
6882 if (!properties_kobj) {
6883 pr_err("%s: failed to create a kobject"
6884 "for board_properites\n", __func__);
6885 rc = -ENOMEM;
6886 goto vreg_get_fail;
6887 }
6888 rc = sysfs_create_group(properties_kobj,
6889 &tma300_properties_attr_group);
6890 if (rc) {
6891 pr_err("%s: failed to create a sysfs entry %s\n",
6892 __func__, tma300_vkeys_attr.attr.name);
6893 kobject_put(properties_kobj);
6894 goto vreg_get_fail;
6895 }
6896 } else {
6897 /* put voltage sources */
6898 for (i = 0; i < ARRAY_SIZE(vregs_tma300_name); i++)
6899 vreg_put(vregs_tma300[i]);
6900 /* destroy virtual keys */
6901 if (properties_kobj) {
6902 sysfs_remove_group(properties_kobj,
6903 &tma300_properties_attr_group);
6904 kobject_put(properties_kobj);
6905 }
6906 }
6907 return 0;
6908
6909vreg_get_fail:
6910 while (i)
6911 vreg_put(vregs_tma300[--i]);
6912 return rc;
6913}
6914
6915static struct cy8c_ts_platform_data cy8ctma300_pdata = {
6916 .power_on = tma300_power,
6917 .dev_setup = tma300_dev_setup,
6918 .ts_name = "msm_tma300_ts",
6919 .dis_min_x = 0,
6920 .dis_max_x = 479,
6921 .dis_min_y = 0,
6922 .dis_max_y = 799,
6923 .res_x = 479,
6924 .res_y = 1009,
6925 .min_tid = 1,
6926 .max_tid = 255,
6927 .min_touch = 0,
6928 .max_touch = 255,
6929 .min_width = 0,
6930 .max_width = 255,
6931 .invert_y = 1,
6932 .nfingers = 4,
6933 .irq_gpio = TS_GPIO_IRQ,
6934 .resout_gpio = -1,
6935};
6936
6937static struct i2c_board_info cy8ctma300_board_info[] = {
6938 {
6939 I2C_BOARD_INFO("cy8ctma300", 0x2),
6940 .platform_data = &cy8ctma300_pdata,
6941 }
6942};
6943
Daniel Walker8d747cd2010-02-25 11:37:43 -08006944static void __init msm7x30_init(void)
6945{
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07006946 int rc;
6947 unsigned smem_size;
6948 uint32_t usb_hub_gpio_cfg_value = GPIO_CFG(56,
6949 0,
6950 GPIO_CFG_OUTPUT,
6951 GPIO_CFG_NO_PULL,
6952 GPIO_CFG_2MA);
6953 uint32_t soc_version = 0;
Pavankumar Kondeti5155e2c2010-12-08 13:37:08 +05306954
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07006955 if (socinfo_init() < 0)
6956 printk(KERN_ERR "%s: socinfo_init() failed!\n",
6957 __func__);
6958
6959 soc_version = socinfo_get_version();
6960
6961 msm7x30_clock_init();
6962#ifdef CONFIG_SERIAL_MSM_CONSOLE
6963 msm7x30_init_uart2();
6964#endif
6965 msm_spm_init(&msm_spm_data, 1);
6966 msm_acpu_clock_init(&msm7x30_clock_data);
6967 if (machine_is_msm7x30_surf() || machine_is_msm7x30_fluid())
6968 msm7x30_cfg_smsc911x();
6969
6970#ifdef CONFIG_USB_MSM_OTG_72K
6971 if (SOCINFO_VERSION_MAJOR(soc_version) >= 2 &&
6972 SOCINFO_VERSION_MINOR(soc_version) >= 1) {
6973 pr_debug("%s: SOC Version:2.(1 or more)\n", __func__);
6974 msm_otg_pdata.ldo_set_voltage = 0;
6975 }
6976
6977 msm_device_otg.dev.platform_data = &msm_otg_pdata;
6978#ifdef CONFIG_USB_GADGET
6979 msm_otg_pdata.swfi_latency =
6980 msm_pm_data
6981 [MSM_PM_SLEEP_MODE_RAMP_DOWN_AND_WAIT_FOR_INTERRUPT].latency;
6982 msm_device_gadget_peripheral.dev.platform_data = &msm_gadget_pdata;
6983#endif
6984#endif
6985 msm_uart_dm1_pdata.wakeup_irq = gpio_to_irq(136);
6986 msm_device_uart_dm1.dev.platform_data = &msm_uart_dm1_pdata;
6987#if defined(CONFIG_TSIF) || defined(CONFIG_TSIF_MODULE)
6988 msm_device_tsif.dev.platform_data = &tsif_platform_data;
6989#endif
6990 if (machine_is_msm7x30_fluid()) {
6991 msm_adc_pdata.dev_names = msm_adc_fluid_device_names;
6992 msm_adc_pdata.num_adc = ARRAY_SIZE(msm_adc_fluid_device_names);
6993 } else {
6994 msm_adc_pdata.dev_names = msm_adc_surf_device_names;
6995 msm_adc_pdata.num_adc = ARRAY_SIZE(msm_adc_surf_device_names);
6996 }
6997
6998 platform_add_devices(msm_footswitch_devices,
6999 msm_num_footswitch_devices);
Daniel Walker8d747cd2010-02-25 11:37:43 -08007000 platform_add_devices(devices, ARRAY_SIZE(devices));
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07007001#ifdef CONFIG_USB_EHCI_MSM_72K
7002 msm_add_host(0, &msm_usb_host_pdata);
7003#endif
7004 msm7x30_init_mmc();
7005 msm7x30_init_nand();
7006 msm_qsd_spi_init();
7007
7008#ifdef CONFIG_SPI_QSD
7009 if (machine_is_msm7x30_fluid())
7010 spi_register_board_info(lcdc_sharp_spi_board_info,
7011 ARRAY_SIZE(lcdc_sharp_spi_board_info));
7012 else
7013 spi_register_board_info(lcdc_toshiba_spi_board_info,
7014 ARRAY_SIZE(lcdc_toshiba_spi_board_info));
7015#endif
7016
7017 msm_fb_add_devices();
7018 msm_pm_set_platform_data(msm_pm_data, ARRAY_SIZE(msm_pm_data));
7019 msm_device_i2c_init();
7020 msm_device_i2c_2_init();
7021 qup_device_i2c_init();
7022 buses_init();
7023 msm7x30_init_marimba();
7024#ifdef CONFIG_MSM7KV2_AUDIO
7025 snddev_poweramp_gpio_init();
7026 aux_pcm_gpio_init();
7027#endif
7028
7029 i2c_register_board_info(0, msm_i2c_board_info,
7030 ARRAY_SIZE(msm_i2c_board_info));
7031
7032 if (!machine_is_msm8x55_svlte_ffa() && !machine_is_msm7x30_fluid())
7033 marimba_pdata.tsadc = &marimba_tsadc_pdata;
7034
7035 if (machine_is_msm7x30_fluid())
7036 i2c_register_board_info(0, cy8info,
7037 ARRAY_SIZE(cy8info));
7038#ifdef CONFIG_BOSCH_BMA150
7039 if (machine_is_msm7x30_fluid())
7040 i2c_register_board_info(0, bma150_board_info,
7041 ARRAY_SIZE(bma150_board_info));
7042#endif
7043
7044 i2c_register_board_info(2, msm_marimba_board_info,
7045 ARRAY_SIZE(msm_marimba_board_info));
7046
7047 i2c_register_board_info(2, msm_i2c_gsbi7_timpani_info,
7048 ARRAY_SIZE(msm_i2c_gsbi7_timpani_info));
7049
7050 i2c_register_board_info(4 /* QUP ID */, msm_camera_boardinfo,
7051 ARRAY_SIZE(msm_camera_boardinfo));
7052
7053 bt_power_init();
7054#ifdef CONFIG_I2C_SSBI
7055 msm_device_ssbi6.dev.platform_data = &msm_i2c_ssbi6_pdata;
7056 msm_device_ssbi7.dev.platform_data = &msm_i2c_ssbi7_pdata;
7057#endif
7058 if (machine_is_msm7x30_fluid())
7059 i2c_register_board_info(0, msm_isa1200_board_info,
7060 ARRAY_SIZE(msm_isa1200_board_info));
7061
7062#if defined(CONFIG_TOUCHSCREEN_TSC2007) || \
7063 defined(CONFIG_TOUCHSCREEN_TSC2007_MODULE)
7064 if (machine_is_msm8x55_svlte_ffa())
7065 i2c_register_board_info(2, tsc_i2c_board_info,
7066 ARRAY_SIZE(tsc_i2c_board_info));
7067#endif
7068
7069 if (machine_is_msm7x30_surf())
7070 platform_device_register(&flip_switch_device);
7071 pmic8058_leds_init();
7072
7073 if (machine_is_msm7x30_fluid()) {
7074 /* Initialize platform data for fluid v2 hardware */
7075 if (SOCINFO_VERSION_MAJOR(
7076 socinfo_get_platform_version()) == 2) {
7077 cy8ctma300_pdata.res_y = 920;
7078 cy8ctma300_pdata.invert_y = 0;
7079 }
7080 i2c_register_board_info(0, cy8ctma300_board_info,
7081 ARRAY_SIZE(cy8ctma300_board_info));
7082 }
7083
7084 if (machine_is_msm8x55_svlte_surf() || machine_is_msm8x55_svlte_ffa()) {
7085 rc = gpio_tlmm_config(usb_hub_gpio_cfg_value, GPIO_CFG_ENABLE);
7086 if (rc)
7087 pr_err("%s: gpio_tlmm_config(%#x)=%d\n",
7088 __func__, usb_hub_gpio_cfg_value, rc);
7089 }
7090
7091 boot_reason = *(unsigned int *)
7092 (smem_get_entry(SMEM_POWER_ON_STATUS_INFO, &smem_size));
7093 printk(KERN_NOTICE "Boot Reason = 0x%02x\n", boot_reason);
7094}
7095
7096static unsigned pmem_sf_size = MSM_PMEM_SF_SIZE;
7097static int __init pmem_sf_size_setup(char *p)
7098{
7099 pmem_sf_size = memparse(p, NULL);
7100 return 0;
7101}
7102early_param("pmem_sf_size", pmem_sf_size_setup);
7103
7104static unsigned fb_size = MSM_FB_SIZE;
7105static int __init fb_size_setup(char *p)
7106{
7107 fb_size = memparse(p, NULL);
7108 return 0;
7109}
7110early_param("fb_size", fb_size_setup);
7111
7112static unsigned pmem_adsp_size = MSM_PMEM_ADSP_SIZE;
7113static int __init pmem_adsp_size_setup(char *p)
7114{
7115 pmem_adsp_size = memparse(p, NULL);
7116 return 0;
7117}
7118early_param("pmem_adsp_size", pmem_adsp_size_setup);
7119
7120static unsigned fluid_pmem_adsp_size = MSM_FLUID_PMEM_ADSP_SIZE;
7121static int __init fluid_pmem_adsp_size_setup(char *p)
7122{
7123 fluid_pmem_adsp_size = memparse(p, NULL);
7124 return 0;
7125}
7126early_param("fluid_pmem_adsp_size", fluid_pmem_adsp_size_setup);
7127
7128static unsigned pmem_audio_size = MSM_PMEM_AUDIO_SIZE;
7129static int __init pmem_audio_size_setup(char *p)
7130{
7131 pmem_audio_size = memparse(p, NULL);
7132 return 0;
7133}
7134early_param("pmem_audio_size", pmem_audio_size_setup);
7135
7136static unsigned pmem_kernel_ebi0_size = PMEM_KERNEL_EBI0_SIZE;
7137static int __init pmem_kernel_ebi0_size_setup(char *p)
7138{
7139 pmem_kernel_ebi0_size = memparse(p, NULL);
7140 return 0;
7141}
7142early_param("pmem_kernel_ebi0_size", pmem_kernel_ebi0_size_setup);
7143
7144static struct memtype_reserve msm7x30_reserve_table[] __initdata = {
7145 [MEMTYPE_SMI] = {
7146 },
7147 [MEMTYPE_EBI0] = {
7148 .flags = MEMTYPE_FLAGS_1M_ALIGN,
7149 },
7150 [MEMTYPE_EBI1] = {
7151 .flags = MEMTYPE_FLAGS_1M_ALIGN,
7152 },
7153};
7154
7155static void __init size_pmem_devices(void)
7156{
7157#ifdef CONFIG_ANDROID_PMEM
7158 unsigned long size;
7159
7160 if machine_is_msm7x30_fluid()
7161 size = fluid_pmem_adsp_size;
7162 else
7163 size = pmem_adsp_size;
7164 android_pmem_adsp_pdata.size = size;
7165 android_pmem_audio_pdata.size = pmem_audio_size;
7166 android_pmem_pdata.size = pmem_sf_size;
7167#endif
7168}
7169
7170static void __init reserve_memory_for(struct android_pmem_platform_data *p)
7171{
7172 msm7x30_reserve_table[p->memory_type].size += p->size;
7173}
7174
7175static void __init reserve_pmem_memory(void)
7176{
7177#ifdef CONFIG_ANDROID_PMEM
7178 reserve_memory_for(&android_pmem_adsp_pdata);
7179 reserve_memory_for(&android_pmem_audio_pdata);
7180 reserve_memory_for(&android_pmem_pdata);
7181 msm7x30_reserve_table[MEMTYPE_EBI0].size += pmem_kernel_ebi0_size;
7182#endif
7183}
7184
7185static void __init msm7x30_calculate_reserve_sizes(void)
7186{
7187 size_pmem_devices();
7188 reserve_pmem_memory();
7189}
7190
7191static int msm7x30_paddr_to_memtype(unsigned int paddr)
7192{
7193 if (paddr < 0x40000000)
7194 return MEMTYPE_EBI0;
7195 if (paddr >= 0x40000000 && paddr < 0x80000000)
7196 return MEMTYPE_EBI1;
7197 return MEMTYPE_NONE;
7198}
7199
7200static struct reserve_info msm7x30_reserve_info __initdata = {
7201 .memtype_reserve_table = msm7x30_reserve_table,
7202 .calculate_reserve_sizes = msm7x30_calculate_reserve_sizes,
7203 .paddr_to_memtype = msm7x30_paddr_to_memtype,
7204};
7205
7206static void __init msm7x30_reserve(void)
7207{
7208 reserve_info = &msm7x30_reserve_info;
7209 msm_reserve();
7210}
7211
7212static void __init msm7x30_allocate_memory_regions(void)
7213{
7214 void *addr;
7215 unsigned long size;
7216
7217 size = fb_size ? : MSM_FB_SIZE;
7218 addr = alloc_bootmem_align(size, 0x1000);
7219 msm_fb_resources[0].start = __pa(addr);
7220 msm_fb_resources[0].end = msm_fb_resources[0].start + size - 1;
7221 pr_info("allocating %lu bytes at %p (%lx physical) for fb\n",
7222 size, addr, __pa(addr));
Daniel Walker8d747cd2010-02-25 11:37:43 -08007223}
7224
7225static void __init msm7x30_map_io(void)
7226{
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07007227 msm_shared_ram_phys = 0x00100000;
Daniel Walker8d747cd2010-02-25 11:37:43 -08007228 msm_map_msm7x30_io();
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07007229}
7230
7231static void __init msm7x30_init_early(void)
7232{
7233 msm7x30_allocate_memory_regions();
Daniel Walker8d747cd2010-02-25 11:37:43 -08007234}
7235
7236MACHINE_START(MSM7X30_SURF, "QCT MSM7X30 SURF")
Russell Kingb75c1782011-01-04 19:03:16 +00007237 .boot_params = PLAT_PHYS_OFFSET + 0x100,
Daniel Walker8d747cd2010-02-25 11:37:43 -08007238 .map_io = msm7x30_map_io,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07007239 .reserve = msm7x30_reserve,
Daniel Walker8d747cd2010-02-25 11:37:43 -08007240 .init_irq = msm7x30_init_irq,
7241 .init_machine = msm7x30_init,
7242 .timer = &msm_timer,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07007243 .init_early = msm7x30_init_early,
Daniel Walker8d747cd2010-02-25 11:37:43 -08007244MACHINE_END
7245
7246MACHINE_START(MSM7X30_FFA, "QCT MSM7X30 FFA")
Russell Kingb75c1782011-01-04 19:03:16 +00007247 .boot_params = PLAT_PHYS_OFFSET + 0x100,
Daniel Walker8d747cd2010-02-25 11:37:43 -08007248 .map_io = msm7x30_map_io,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07007249 .reserve = msm7x30_reserve,
Daniel Walker8d747cd2010-02-25 11:37:43 -08007250 .init_irq = msm7x30_init_irq,
7251 .init_machine = msm7x30_init,
7252 .timer = &msm_timer,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07007253 .init_early = msm7x30_init_early,
Daniel Walker8d747cd2010-02-25 11:37:43 -08007254MACHINE_END
7255
7256MACHINE_START(MSM7X30_FLUID, "QCT MSM7X30 FLUID")
Russell Kingb75c1782011-01-04 19:03:16 +00007257 .boot_params = PLAT_PHYS_OFFSET + 0x100,
Daniel Walker8d747cd2010-02-25 11:37:43 -08007258 .map_io = msm7x30_map_io,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07007259 .reserve = msm7x30_reserve,
Daniel Walker8d747cd2010-02-25 11:37:43 -08007260 .init_irq = msm7x30_init_irq,
7261 .init_machine = msm7x30_init,
7262 .timer = &msm_timer,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07007263 .init_early = msm7x30_init_early,
7264MACHINE_END
7265
7266MACHINE_START(MSM8X55_SURF, "QCT MSM8X55 SURF")
7267 .boot_params = PHYS_OFFSET + 0x100,
7268 .map_io = msm7x30_map_io,
7269 .reserve = msm7x30_reserve,
7270 .init_irq = msm7x30_init_irq,
7271 .init_machine = msm7x30_init,
7272 .timer = &msm_timer,
7273 .init_early = msm7x30_init_early,
7274MACHINE_END
7275
7276MACHINE_START(MSM8X55_FFA, "QCT MSM8X55 FFA")
7277 .boot_params = PHYS_OFFSET + 0x100,
7278 .map_io = msm7x30_map_io,
7279 .reserve = msm7x30_reserve,
7280 .init_irq = msm7x30_init_irq,
7281 .init_machine = msm7x30_init,
7282 .timer = &msm_timer,
7283 .init_early = msm7x30_init_early,
7284MACHINE_END
7285MACHINE_START(MSM8X55_SVLTE_SURF, "QCT MSM8X55 SVLTE SURF")
7286 .boot_params = PHYS_OFFSET + 0x100,
7287 .map_io = msm7x30_map_io,
7288 .reserve = msm7x30_reserve,
7289 .init_irq = msm7x30_init_irq,
7290 .init_machine = msm7x30_init,
7291 .timer = &msm_timer,
7292 .init_early = msm7x30_init_early,
7293MACHINE_END
7294MACHINE_START(MSM8X55_SVLTE_FFA, "QCT MSM8X55 SVLTE FFA")
7295 .boot_params = PHYS_OFFSET + 0x100,
7296 .map_io = msm7x30_map_io,
7297 .reserve = msm7x30_reserve,
7298 .init_irq = msm7x30_init_irq,
7299 .init_machine = msm7x30_init,
7300 .timer = &msm_timer,
7301 .init_early = msm7x30_init_early,
Daniel Walker8d747cd2010-02-25 11:37:43 -08007302MACHINE_END