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review.evervolv.com / android_kernel_htc_msm8960 / 68398a4f0e87aa7285ccf55d1e087f15c32aedca / . / arch / arm / boot / dts / msm8974.dtsi
blob: 2eb8216a7a99606622f66d9cb7c6747d14cfb814 [file] [log] [blame]
Sathish Ambley9d69ac32012-03-21 10:28:26 -0700[diff] [blame]1/* Copyright (c) 2012, Code Aurora Forum. All rights reserved.
2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 */
Sathish Ambley4df614c2011-10-07 16:30:46 -0700[diff] [blame]12
13/include/ "skeleton.dtsi"
Abhimanyu Kapur90ced6e2012-06-26 17:41:25 -0700[diff] [blame]14/include/ "msm8974_pm.dtsi"
Abhimanyu Kapur90ced6e2012-06-26 17:41:25 -0700[diff] [blame]15/include/ "msm8974-iommu.dtsi"
Matt Wagantallfc727212012-01-06 18:18:25 -0800[diff] [blame]16/include/ "msm-gdsc.dtsi"
Sathish Ambley4df614c2011-10-07 16:30:46 -0700[diff] [blame]17
18/ {
Abhimanyu Kapur90ced6e2012-06-26 17:41:25 -0700[diff] [blame]19 model = "Qualcomm MSM 8974";
20 compatible = "qcom,msm8974";
Sathish Ambley4df614c2011-10-07 16:30:46 -0700[diff] [blame]21 interrupt-parent = <&intc>;
22
23 intc: interrupt-controller@F9000000 {
24 compatible = "qcom,msm-qgic2";
25 interrupt-controller;
Michael Bohanc7224532012-01-06 16:02:52 -0800[diff] [blame]26 #interrupt-cells = <3>;
Sathish Ambley4df614c2011-10-07 16:30:46 -0700[diff] [blame]27 reg = <0xF9000000 0x1000>,
28 <0xF9002000 0x1000>;
29 };
Sathish Ambley3d50c762011-10-25 15:26:00 -0700[diff] [blame]30
Sathish Ambleye046b242012-04-09 12:38:05 -0700[diff] [blame]31 msmgpio: gpio@fd510000 {
Michael Bohan0425f6f2012-01-17 14:36:39 -0800[diff] [blame]32 compatible = "qcom,msm-gpio";
33 interrupt-controller;
34 #interrupt-cells = <2>;
Sathish Ambleye046b242012-04-09 12:38:05 -0700[diff] [blame]35 reg = <0xfd510000 0x4000>;
36 #gpio-cells = <2>;
Michael Bohan0425f6f2012-01-17 14:36:39 -0800[diff] [blame]37 };
38
Sathish Ambley098f9bd2011-11-09 16:32:53 -0800[diff] [blame]39 timer {
Sathish Ambley2f27a172012-03-16 10:46:28 -0700[diff] [blame]40 compatible = "qcom,msm-qtimer", "arm,armv7-timer";
Sathish Ambleyddd099e2012-04-25 13:24:47 -0700[diff] [blame]41 interrupts = <1 2 0 1 3 0>;
Sathish Ambley2f27a172012-03-16 10:46:28 -0700[diff] [blame]42 clock-frequency = <19200000>;
Sathish Ambley098f9bd2011-11-09 16:32:53 -0800[diff] [blame]43 };
44
Praneeth Paladugu4b73ec82012-02-08 12:55:59 -0800[diff] [blame]45 qcom,vidc@fdc00000 {
46 compatible = "qcom,msm-vidc";
47 reg = <0xfdc00000 0xff000>;
48 interrupts = <0 44 0>;
Vinay Kalia68398a42012-06-22 18:36:12 -0700[diff] [blame^]49 vidc-cp-map = <0x1000000 0x40000000>;
50 vidc-ns-map = <0x40000000 0x40000000>;
Praneeth Paladugu4b73ec82012-02-08 12:55:59 -0800[diff] [blame]51 };
52
David Brown225abee2012-02-09 22:28:50 -0800[diff] [blame]53 serial@f991f000 {
Sathish Ambley3d50c762011-10-25 15:26:00 -0700[diff] [blame]54 compatible = "qcom,msm-lsuart-v14";
David Brown225abee2012-02-09 22:28:50 -0800[diff] [blame]55 reg = <0xf991f000 0x1000>;
Michael Bohanc7224532012-01-06 16:02:52 -0800[diff] [blame]56 interrupts = <0 109 0>;
Sathish Ambley3d50c762011-10-25 15:26:00 -0700[diff] [blame]57 };
Pavankumar Kondetieaea7fe2011-10-27 14:46:45 +0530[diff] [blame]58
Sathish Ambley9d69ac32012-03-21 10:28:26 -0700[diff] [blame]59 serial@f995e000 {
60 compatible = "qcom,msm-lsuart-v14";
61 reg = <0xf995e000 0x1000>;
62 interrupts = <0 114 0>;
63 };
64
David Brown225abee2012-02-09 22:28:50 -0800[diff] [blame]65 usb@f9a55000 {
Pavankumar Kondetieaea7fe2011-10-27 14:46:45 +0530[diff] [blame]66 compatible = "qcom,hsusb-otg";
David Brown225abee2012-02-09 22:28:50 -0800[diff] [blame]67 reg = <0xf9a55000 0x400>;
Michael Bohanc7224532012-01-06 16:02:52 -0800[diff] [blame]68 interrupts = <0 134 0>;
Michael Bohane66a3a92012-03-26 12:47:28 -0700[diff] [blame]69 HSUSB_VDDCX-supply = <&pm8841_s2>;
70 HSUSB_1p8-supply = <&pm8941_l6>;
71 HSUSB_3p3-supply = <&pm8941_l24>;
Pavankumar Kondetieaea7fe2011-10-27 14:46:45 +0530[diff] [blame]72
73 qcom,hsusb-otg-phy-type = <2>;
74 qcom,hsusb-otg-mode = <1>;
75 qcom,hsusb-otg-otg-control = <1>;
76 };
Sujit Reddy Thumma7285c2e2011-11-04 10:18:15 +0530[diff] [blame]77
Sujit Reddy Thumma85fc52c2012-05-02 12:53:45 +0530[diff] [blame]78 qcom,sdcc@f9824000 {
Sujit Reddy Thumma7285c2e2011-11-04 10:18:15 +0530[diff] [blame]79 cell-index = <1>;
80 compatible = "qcom,msm-sdcc";
Sujit Reddy Thumma85fc52c2012-05-02 12:53:45 +0530[diff] [blame]81 reg = <0xf9824000 0x1000>;
Michael Bohanc7224532012-01-06 16:02:52 -0800[diff] [blame]82 interrupts = <0 123 0>;
Sujit Reddy Thummab9ff7f02012-05-04 09:57:49 +0530[diff] [blame]83 vdd-supply = <&pm8941_l20>;
84 vdd-io-supply = <&pm8941_s3>;
85
86 qcom,sdcc-vdd-voltage_level = <2950000 2950000>;
87 qcom,sdcc-vdd-current_level = <800 500000>;
88
89 qcom,sdcc-vdd-io-always_on;
90 qcom,sdcc-vdd-io-voltage_level = <1800000 1800000>;
91 qcom,sdcc-vdd-io-current_level = <250 154000>;
Sujit Reddy Thumma7285c2e2011-11-04 10:18:15 +0530[diff] [blame]92
Sujit Reddy Thumma85fc52c2012-05-02 12:53:45 +0530[diff] [blame]93 qcom,sdcc-clk-rates = <400000 25000000 50000000 100000000 200000000>;
94 qcom,sdcc-sup-voltages = <2950 2950>;
Sujit Reddy Thumma7285c2e2011-11-04 10:18:15 +0530[diff] [blame]95 qcom,sdcc-bus-width = <8>;
96 qcom,sdcc-nonremovable;
Sujit Reddy Thumma824b7522012-05-30 13:04:34 +0530[diff] [blame]97 qcom,sdcc-bus-speed-mode = "HS200_1p8v", "DDR_1p8v";
Sujit Reddy Thumma7285c2e2011-11-04 10:18:15 +0530[diff] [blame]98 };
99
Sujit Reddy Thumma85fc52c2012-05-02 12:53:45 +0530[diff] [blame]100 qcom,sdcc@f98a4000 {
101 cell-index = <2>;
102 compatible = "qcom,msm-sdcc";
103 reg = <0xf98a4000 0x1000>;
104 interrupts = <0 125 0>;
Sujit Reddy Thummab9ff7f02012-05-04 09:57:49 +0530[diff] [blame]105 vdd-supply = <&pm8941_l21>;
106 vdd-io-supply = <&pm8941_l13>;
107
108 qcom,sdcc-vdd-voltage_level = <2950000 2950000>;
109 qcom,sdcc-vdd-current_level = <9000 800000>;
110
111 qcom,sdcc-vdd-io-always_on;
112 qcom,sdcc-vdd-io-lpm_sup;
113 qcom,sdcc-vdd-io-voltage_level = <1800000 2950000>;
114 qcom,sdcc-vdd-io-current_level = <6 22000>;
Sujit Reddy Thumma85fc52c2012-05-02 12:53:45 +0530[diff] [blame]115
116 qcom,sdcc-clk-rates = <400000 25000000 50000000 100000000 200000000>;
117 qcom,sdcc-sup-voltages = <2950 2950>;
118 qcom,sdcc-bus-width = <4>;
Sujit Reddy Thumma824b7522012-05-30 13:04:34 +0530[diff] [blame]119 qcom,sdcc-xpc;
120 qcom,sdcc-bus-speed-mode = "SDR12", "SDR25", "SDR50", "DDR50", "SDR104";
121 qcom,sdcc-current-limit = <800>;
Sujit Reddy Thumma85fc52c2012-05-02 12:53:45 +0530[diff] [blame]122 };
123
124 qcom,sdcc@f9864000 {
Sujit Reddy Thumma7285c2e2011-11-04 10:18:15 +0530[diff] [blame]125 cell-index = <3>;
126 compatible = "qcom,msm-sdcc";
Sujit Reddy Thumma85fc52c2012-05-02 12:53:45 +0530[diff] [blame]127 reg = <0xf9864000 0x1000>;
Michael Bohanc7224532012-01-06 16:02:52 -0800[diff] [blame]128 interrupts = <0 127 0>;
Sujit Reddy Thumma7285c2e2011-11-04 10:18:15 +0530[diff] [blame]129
Sujit Reddy Thumma85fc52c2012-05-02 12:53:45 +0530[diff] [blame]130 qcom,sdcc-clk-rates = <400000 25000000 50000000 100000000>;
131 qcom,sdcc-sup-voltages = <1800 1800>;
Sujit Reddy Thumma7285c2e2011-11-04 10:18:15 +0530[diff] [blame]132 qcom,sdcc-bus-width = <4>;
Sujit Reddy Thumma824b7522012-05-30 13:04:34 +0530[diff] [blame]133 qcom,sdcc-bus-speed-mode = "SDR12", "SDR25", "SDR50", "DDR50";
Sujit Reddy Thumma7138b3e2012-06-04 09:10:11 +0530[diff] [blame]134 status = "disable";
Sujit Reddy Thumma85fc52c2012-05-02 12:53:45 +0530[diff] [blame]135 };
136
137 qcom,sdcc@f98e4000 {
138 cell-index = <4>;
139 compatible = "qcom,msm-sdcc";
140 reg = <0xf98e4000 0x1000>;
141 interrupts = <0 129 0>;
142
143 qcom,sdcc-clk-rates = <400000 25000000 50000000 100000000>;
144 qcom,sdcc-sup-voltages = <1800 1800>;
145 qcom,sdcc-bus-width = <4>;
Sujit Reddy Thumma824b7522012-05-30 13:04:34 +0530[diff] [blame]146 qcom,sdcc-bus-speed-mode = "SDR12", "SDR25", "SDR50", "DDR50";
Sujit Reddy Thumma7138b3e2012-06-04 09:10:11 +0530[diff] [blame]147 status = "disable";
Sujit Reddy Thumma7285c2e2011-11-04 10:18:15 +0530[diff] [blame]148 };
Yan He1466daa2011-11-30 17:25:38 -0800[diff] [blame]149
David Brown225abee2012-02-09 22:28:50 -0800[diff] [blame]150 qcom,sps@f9980000 {
Yan He1466daa2011-11-30 17:25:38 -0800[diff] [blame]151 compatible = "qcom,msm_sps";
David Brown225abee2012-02-09 22:28:50 -0800[diff] [blame]152 reg = <0xf9984000 0x15000>,
153 <0xf9999000 0xb000>;
Michael Bohanc7224532012-01-06 16:02:52 -0800[diff] [blame]154 interrupts = <0 94 0>;
Yan He1466daa2011-11-30 17:25:38 -0800[diff] [blame]155
156 qcom,bam-dma-res-pipes = <6>;
157 };
158
Hariprasad Dhalinarasimhade991f02012-05-31 13:15:51 -0700[diff] [blame]159
Harini Jayaraman5f98dbb2011-12-20 13:38:19 -0700[diff] [blame]160 spi@f9924000 {
161 compatible = "qcom,spi-qup-v2";
162 reg = <0xf9924000 0x1000>;
Michael Bohan857c8ac2012-01-23 16:57:34 -0800[diff] [blame]163 interrupts = <0 96 0>;
Vikram Mulukutla703e5722012-05-24 21:53:40 -0700[diff] [blame]164 spi-max-frequency = <25000000>;
Harini Jayaraman5f98dbb2011-12-20 13:38:19 -0700[diff] [blame]165 };
Kenneth Heitkef3c829c2012-01-13 17:02:43 -0700[diff] [blame]166
Sagar Dhariaa316a962012-03-21 16:13:22 -0600[diff] [blame]167 slim@fe12f000 {
168 cell-index = <1>;
169 compatible = "qcom,slim-msm";
170 reg = <0xfe12f000 0x35000>,
171 <0xfe104000 0x20000>;
172 reg-names = "slimbus_physical", "slimbus_bam_physical";
173 interrupts = <0 163 0 0 164 0>;
174 interrupt-names = "slimbus_irq", "slimbus_bam_irq";
175 qcom,min-clk-gear = <10>;
176 };
177
Varad Deshmukh18057ed2012-07-03 16:34:53 -0700[diff] [blame]178 spmi_bus: qcom,spmi@fc4c0000 {
Kenneth Heitkef3c829c2012-01-13 17:02:43 -0700[diff] [blame]179 cell-index = <0>;
180 compatible = "qcom,spmi-pmic-arb";
181 reg = <0xfc4cf000 0x1000>,
182 <0Xfc4cb000 0x1000>;
183 /* 190,ee0_krait_hlos_spmi_periph_irq */
184 /* 187,channel_0_krait_hlos_trans_done_irq */
185 interrupts = <0 190 0 0 187 0>;
186 qcom,pmic-arb-ee = <0>;
187 qcom,pmic-arb-channel = <0>;
Gilad Avidova11c0b52012-02-15 15:30:49 -0700[diff] [blame]188 qcom,pmic-arb-ppid-map = <0x13000000>, /* PM8941_LDO1 */
189 <0x13100001>, /* PM8941_LDO2 */
190 <0x13200002>, /* PM8941_LDO3 */
191 <0x13300003>, /* PM8941_LDO4 */
192 <0x13400004>, /* PM8941_LDO5 */
193 <0x13500005>, /* PM8941_LDO6 */
194 <0x13600006>, /* PM8941_LDO7 */
195 <0x13700007>, /* PM8941_LDO8 */
196 <0x13800008>, /* PM8941_LDO9 */
197 <0x13900009>, /* PM8941_LDO10 */
198 <0x13a0000a>, /* PM8941_LDO11 */
199 <0x13b0000b>, /* PM8941_LDO12 */
200 <0x13c0000c>, /* PM8941_LDO13 */
201 <0x13d0000d>, /* PM8941_LDO14 */
202 <0x13e0000e>, /* PM8941_LDO15 */
203 <0x13f0000f>, /* PM8941_LDO16 */
204 <0x14000010>, /* PM8941_LDO17 */
205 <0x14100011>, /* PM8941_LDO18 */
206 <0x14200012>, /* PM8941_LDO19 */
207 <0x14300013>, /* PM8941_LDO20 */
208 <0x14400014>, /* PM8941_LDO21 */
209 <0x14500015>, /* PM8941_LDO22 */
210 <0x14600016>, /* PM8941_LDO23 */
211 <0x14700017>, /* PM8941_LDO24 */
212 <0x14800018>, /* PM8941_LDO25 */
213 <0x14900019>, /* PM8941_LDO26 */
214 <0x0c00001a>, /* PM8941_GPIO1 */
215 <0x0c10001b>, /* PM8941_GPIO2 */
216 <0x0c20001c>, /* PM8941_GPIO3 */
217 <0x0c30001d>, /* PM8941_GPIO4 */
218 <0x0c40001e>, /* PM8941_GPIO5 */
219 <0x0c50001f>, /* PM8941_GPIO6 */
220 <0x0c600020>, /* PM8941_GPIO7 */
221 <0x0c700021>, /* PM8941_GPIO8 */
222 <0x0c800022>, /* PM8941_GPIO9 */
223 <0x0c900023>, /* PM8941_GPIO10 */
224 <0x0ca00024>, /* PM8941_GPIO11 */
225 <0x0cb00025>, /* PM8941_GPIO12 */
226 <0x0cc00026>, /* PM8941_GPIO13 */
227 <0x0cd00027>, /* PM8941_GPIO14 */
228 <0x0ce00028>, /* PM8941_GPIO15 */
229 <0x0cf00029>, /* PM8941_GPIO16 */
230 <0x0d00002a>, /* PM8941_GPIO17 */
231 <0x0d10002b>, /* PM8941_GPIO18 */
232 <0x0d20002c>, /* PM8941_GPIO19 */
233 <0x0d30002d>, /* PM8941_GPIO20 */
234 <0x0d40002e>, /* PM8941_GPIO21 */
235 <0x0d50002f>, /* PM8941_GPIO22 */
236 <0x0d600030>, /* PM8941_GPIO23 */
237 <0x0d700031>, /* PM8941_GPIO24 */
238 <0x0d800032>, /* PM8941_GPIO25 */
239 <0x0d900033>, /* PM8941_GPIO26 */
240 <0x0da00034>, /* PM8941_GPIO27 */
241 <0x0db00035>, /* PM8941_GPIO28 */
242 <0x0dc00036>, /* PM8941_GPIO29 */
243 <0x0dd00037>, /* PM8941_GPIO30 */
244 <0x0de00038>, /* PM8941_GPIO31 */
245 <0x0df00039>, /* PM8941_GPIO32 */
246 <0x0e00003a>, /* PM8941_GPIO33 */
247 <0x0e10003b>, /* PM8941_GPIO34 */
248 <0x0e20003c>, /* PM8941_GPIO35 */
249 <0x0e30003d>, /* PM8941_GPIO36 */
250 <0x0280003e>, /* COINCELL */
251 <0x0100003f>, /* SMBC_OVP */
252 <0x01100040>, /* SMBC_CHG */
253 <0x01200041>, /* SMBC_BIF */
254 <0x00500042>, /* INTERRUPT */
255 <0x00100043>, /* PM8941_0 */
256 <0x20100044>, /* PM8841_0 */
257 <0x10100045>, /* PM8941_1 */
258 <0x30100046>, /* PM8841_1 */
259 <0x00800047>, /* PON0 */
260 <0x20800048>, /* PON1 */
261 <0x11000049>, /* PM8941_SMPS1 */
262 <0x1110004a>, /* PM8941_SMPS2 */
263 <0x1120004b>, /* PM8941_SMPS3 */
264 <0x3100004c>, /* PM8841_SMPS1 */
265 <0x3110004d>, /* PM8841_SMPS2 */
266 <0x3120004e>, /* PM8841_SMPS3 */
267 <0x3130004f>, /* PM8841_SMPS4 */
268 <0x31400050>, /* PM8841_SMPS5 */
269 <0x31500051>, /* PM8841_SMPS6 */
270 <0x31600052>, /* PM8841_SMPS7 */
271 <0x31700053>, /* PM8841_SMPS8 */
272 <0x05000054>, /* SHARED_XO */
273 <0x05100055>, /* BB_CLK1 */
274 <0x05200056>, /* BB_CLK2 */
275 <0x05900057>, /* SLEEP_CLK */
276 <0x07000058>, /* PBS_CORE */
277 <0x07100059>, /* PBS_CLIENT1 */
278 <0x0720005a>; /* PBS_CLIENT2 */
Kenneth Heitkef3c829c2012-01-13 17:02:43 -0700[diff] [blame]279 };
Sagar Dharia218edb92012-01-15 18:03:01 -0700[diff] [blame]280
281 i2c@f9966000 {
282 cell-index = <0>;
283 compatible = "qcom,i2c-qup";
284 reg = <0Xf9966000 0x1000>;
285 reg-names = "qup_phys_addr";
286 interrupts = <0 104 0>;
287 interrupt-names = "qup_err_intr";
288 qcom,i2c-bus-freq = <100000>;
289 qcom,i2c-src-freq = <24000000>;
290 };
Matt Wagantalle9b715a2012-01-04 18:16:14 -0800[diff] [blame]291
Matt Wagantall48523022012-04-23 13:28:42 -0700[diff] [blame]292 qcom,acpuclk@f9000000 {
Abhimanyu Kapur90ced6e2012-06-26 17:41:25 -0700[diff] [blame]293 compatible = "qcom,acpuclk-8974";
Matt Wagantallbf9eb2c2012-05-31 09:44:22 -0700[diff] [blame]294 krait0-supply = <&krait0_vreg>;
295 krait1-supply = <&krait1_vreg>;
296 krait2-supply = <&krait2_vreg>;
297 krait3-supply = <&krait3_vreg>;
David Collins1c91ea72012-05-03 16:17:35 -0700[diff] [blame]298 krait0_mem-supply = <&pm8841_s1_ao>;
299 krait1_mem-supply = <&pm8841_s1_ao>;
300 krait2_mem-supply = <&pm8841_s1_ao>;
301 krait3_mem-supply = <&pm8841_s1_ao>;
302 krait0_dig-supply = <&pm8841_s2_corner_ao>;
303 krait1_dig-supply = <&pm8841_s2_corner_ao>;
304 krait2_dig-supply = <&pm8841_s2_corner_ao>;
305 krait3_dig-supply = <&pm8841_s2_corner_ao>;
Matt Wagantall337cdb72012-06-29 12:07:27 -0700[diff] [blame]306 krait0_hfpll_a-supply = <&pm8941_s2_ao>;
307 krait1_hfpll_a-supply = <&pm8941_s2_ao>;
308 krait2_hfpll_a-supply = <&pm8941_s2_ao>;
309 krait3_hfpll_a-supply = <&pm8941_s2_ao>;
310 l2_hfpll_a-supply = <&pm8941_s2_ao>;
311 krait0_hfpll_b-supply = <&pm8941_l12_ao>;
312 krait1_hfpll_b-supply = <&pm8941_l12_ao>;
313 krait2_hfpll_b-supply = <&pm8941_l12_ao>;
314 krait3_hfpll_b-supply = <&pm8941_l12_ao>;
315 l2_hfpll_b-supply = <&pm8941_l12_ao>;
Matt Wagantalle9b715a2012-01-04 18:16:14 -0800[diff] [blame]316 };
Ido Shayevitzef72ddd2012-03-28 18:55:55 +0200[diff] [blame]317
318 qcom,ssusb@F9200000 {
319 compatible = "qcom,dwc-usb3-msm";
Manu Gautam8c642812012-06-07 10:35:10 +0530[diff] [blame]320 reg = <0xF9200000 0xFA000>;
Manu Gautam17206c22012-06-21 10:17:53 +0530[diff] [blame]321 interrupts = <0 131 0 0 179 0>;
322 interrupt-names = "irq", "otg_irq";
Manu Gautam60e01352012-05-29 09:00:34 +0530[diff] [blame]323 SSUSB_VDDCX-supply = <&pm8841_s2>;
324 SSUSB_1p8-supply = <&pm8941_l6>;
325 HSUSB_VDDCX-supply = <&pm8841_s2>;
326 HSUSB_1p8-supply = <&pm8941_l6>;
327 HSUSB_3p3-supply = <&pm8941_l24>;
Ido Shayevitzef72ddd2012-03-28 18:55:55 +0200[diff] [blame]328 qcom,dwc-usb3-msm-dbm-eps = <4>;
329 };
Matt Wagantallc2bbdc32012-03-21 19:44:50 -0700[diff] [blame]330
Matt Wagantallfc727212012-01-06 18:18:25 -0800[diff] [blame]331 gdsc_oxili_gx: qcom,gdsc@fd8c4024 {
332 parent-supply = <&pm8841_s4>;
333 };
334
Matt Wagantallc2bbdc32012-03-21 19:44:50 -0700[diff] [blame]335 qcom,lpass@fe200000 {
336 compatible = "qcom,pil-q6v5-lpass";
337 reg = <0xfe200000 0x00100>,
Matt Wagantallc2bbdc32012-03-21 19:44:50 -0700[diff] [blame]338 <0xfd485100 0x00010>;
339
Matt Wagantall6e6b8cd2012-05-24 12:42:24 -0700[diff] [blame]340 qcom,firmware-name = "adsp";
Matt Wagantallc2bbdc32012-03-21 19:44:50 -0700[diff] [blame]341 };
Tianyi Gouc1e049f82011-11-23 14:20:16 -0800[diff] [blame]342
Phani Kumar Uppalapati87841c82012-06-14 21:28:43 -0700[diff] [blame]343 qcom,msm-pcm {
344 compatible = "qcom,msm-pcm-dsp";
345 };
Phani Kumar Uppalapatic6651692012-06-14 20:33:09 -0700[diff] [blame]346
Phani Kumar Uppalapati87841c82012-06-14 21:28:43 -0700[diff] [blame]347 qcom,msm-pcm-routing {
348 compatible = "qcom,msm-pcm-routing";
349 };
Phani Kumar Uppalapatic6651692012-06-14 20:33:09 -0700[diff] [blame]350
Phani Kumar Uppalapati87841c82012-06-14 21:28:43 -0700[diff] [blame]351 qcom,msm-pcm-lpa {
352 compatible = "qcom,msm-pcm-lpa";
353 };
Phani Kumar Uppalapatic6651692012-06-14 20:33:09 -0700[diff] [blame]354
Phani Kumar Uppalapati87841c82012-06-14 21:28:43 -0700[diff] [blame]355 qcom,msm-voip-dsp {
356 compatible = "qcom,msm-voip-dsp";
357 };
Phani Kumar Uppalapatic6651692012-06-14 20:33:09 -0700[diff] [blame]358
Phani Kumar Uppalapati87841c82012-06-14 21:28:43 -0700[diff] [blame]359 qcom,msm-stub-codec {
360 compatible = "qcom,msm-stub-codec";
361 };
Phani Kumar Uppalapatic6651692012-06-14 20:33:09 -0700[diff] [blame]362
Phani Kumar Uppalapati87841c82012-06-14 21:28:43 -0700[diff] [blame]363 qcom,msm-dai-fe {
364 compatible = "qcom,msm-dai-fe";
365 };
Phani Kumar Uppalapatic6651692012-06-14 20:33:09 -0700[diff] [blame]366
Phani Kumar Uppalapati87841c82012-06-14 21:28:43 -0700[diff] [blame]367 qcom,msm-auxpcm {
368 compatible = "qcom,msm-auxpcm-resource";
369 qcom,msm-cpudai-auxpcm-clk = "pcm_clk";
370 qcom,msm-cpudai-auxpcm-mode = <0>;
371 qcom,msm-cpudai-auxpcm-sync = <1>;
372 qcom,msm-cpudai-auxpcm-frame = <5>;
373 qcom,msm-cpudai-auxpcm-quant = <2>;
374 qcom,msm-cpudai-auxpcm-slot = <1>;
375 qcom,msm-cpudai-auxpcm-data = <0>;
376 qcom,msm-cpudai-auxpcm-pcm-clk-rate = <2048000>;
Phani Kumar Uppalapatic6651692012-06-14 20:33:09 -0700[diff] [blame]377
Phani Kumar Uppalapati87841c82012-06-14 21:28:43 -0700[diff] [blame]378 qcom,msm-auxpcm-rx {
379 qcom,msm-auxpcm-dev-id = <4106>;
380 compatible = "qcom,msm-auxpcm-dev";
381 };
Phani Kumar Uppalapatic6651692012-06-14 20:33:09 -0700[diff] [blame]382
Phani Kumar Uppalapati87841c82012-06-14 21:28:43 -0700[diff] [blame]383 qcom,msm-auxpcm-tx {
384 qcom,msm-auxpcm-dev-id = <4107>;
385 compatible = "qcom,msm-auxpcm-dev";
386 };
387 };
388
389 qcom,msm-pcm-hostless {
390 compatible = "qcom,msm-pcm-hostless";
391 };
Phani Kumar Uppalapatic6651692012-06-14 20:33:09 -0700[diff] [blame]392
Matt Wagantall4e2599e2012-03-21 22:31:35 -0700[diff] [blame]393 qcom,mss@fc880000 {
394 compatible = "qcom,pil-q6v5-mss";
395 reg = <0xfc880000 0x100>,
396 <0xfd485000 0x400>,
397 <0xfc820000 0x020>,
398 <0xfc401680 0x004>;
399 vdd_mss-supply = <&pm8841_s3>;
400
401 qcom,firmware-name = "mba";
402 qcom,pil-self-auth = <1>;
403 };
404
Matt Wagantalle6e00d52012-03-08 17:39:07 -0800[diff] [blame]405 qcom,mba@fc820000 {
406 compatible = "qcom,pil-mba";
407 reg = <0xfc820000 0x0020>,
408 <0x0d1fc000 0x4000>;
409
410 qcom,firmware-name = "modem";
411 qcom,depends-on = "mba";
412 };
413
Tianyi Gouc1e049f82011-11-23 14:20:16 -0800[diff] [blame]414 qcom,pronto@fb21b000 {
415 compatible = "qcom,pil-pronto";
416 reg = <0xfb21b000 0x3000>,
417 <0xfc401700 0x4>,
418 <0xfd485300 0xc>;
419 vdd_pronto_pll-supply = <&pm8941_l12>;
420
421 qcom,firmware-name = "wcnss";
422 };
Naveen Ramaraj51f5e8b2012-04-09 15:58:40 -0700[diff] [blame]423
424 qcom,ocmem@fdd00000 {
Naveen Ramaraj94455a42012-07-05 16:01:40 -0700[diff] [blame]425 compatible = "qcom,msm-ocmem";
426 reg = <0xfdd00000 0x2000>,
427 <0xfdd02000 0x2000>,
428 <0xfe039000 0x400>,
429 <0xfec00000 0x180000>;
430 reg-names = "ocmem_ctrl_physical", "dm_ctrl_physical", "br_ctrl_physical", "ocmem_physical";
431 interrupts = <0 76 0 0 77 0>;
432 interrupt-names = "ocmem_irq", "dm_irq";
433 qcom,ocmem-num-regions = <0x3>;
434 #address-cells = <1>;
435 #size-cells = <1>;
436 ranges = <0x0 0xfec00000 0x180000>;
437
438 partition@0 {
439 reg = <0x0 0x100000>;
440 qcom,ocmem-part-name = "graphics";
441 qcom,ocmem-part-min = <0x80000>;
442 };
443
444 partition@80000 {
445 reg = <0x80000 0xA0000>;
446 qcom,ocmem-part-name = "lp_audio";
447 qcom,ocmem-part-min = <0xA0000>;
448 };
449
450 partition@E0000 {
451 reg = <0x120000 0x20000>;
452 qcom,ocmem-part-name = "blast";
453 qcom,ocmem-part-min = <0x20000>;
454 };
455
456 partition@100000 {
457 reg = <0x100000 0x80000>;
458 qcom,ocmem-part-name = "video";
459 qcom,ocmem-part-min = <0x55000>;
460 };
461
462 partition@140000 {
463 reg = <0x140000 0x40000>;
464 qcom,ocmem-part-name = "sensors";
465 qcom,ocmem-part-min = <0x40000>;
466 };
Naveen Ramaraj51f5e8b2012-04-09 15:58:40 -0700[diff] [blame]467 };
Mahesh Sivasubramanian3f0d0c72012-05-04 17:35:55 -0600[diff] [blame]468
Varad Deshmukh18057ed2012-07-03 16:34:53 -0700[diff] [blame]469 rpm_bus: qcom,rpm-smd {
Mahesh Sivasubramanian3f0d0c72012-05-04 17:35:55 -0600[diff] [blame]470 compatible = "qcom,rpm-smd";
471 rpm-channel-name = "rpm_requests";
472 rpm-channel-type = <15>; /* SMD_APPS_RPM */
473 };
Hariprasad Dhalinarasimhade991f02012-05-31 13:15:51 -0700[diff] [blame]474
475 qcom,msm-rng@f9bff000 {
476 compatible = "qcom,msm-rng";
477 reg = <0xf9bff000 0x200>;
478 };
Ramesh Masavarapufb1f01e2012-06-14 09:40:40 -0700[diff] [blame]479
480 qcom,qseecom@fe806000 {
481 compatible = "qcom,qseecom";
482 };
Adrian Salido-Moreno5ef3ac02012-05-14 18:40:47 -0700[diff] [blame]483
484 qcom,mdss_mdp@fd900000 {
485 cell-index = <0>;
486 compatible = "qcom,mdss_mdp";
487 reg = <0xfd900000 0x22100>;
488 interrupts = <0 72 0>;
Matt Wagantall37320fb2012-06-26 14:50:28 -0700[diff] [blame]489 vdd-supply = <&gdsc_mdss>;
Adrian Salido-Moreno5ef3ac02012-05-14 18:40:47 -0700[diff] [blame]490 };
491
492 qcom,mdss_wb_panel {
493 cell-index = <1>;
494 compatible = "qcom,mdss_wb";
495 qcom,mdss_pan_res = <640 480>;
496 qcom,mdss_pan_bpp = <24>;
497 };
Hanumant72aec702012-06-25 11:51:07 -0700[diff] [blame]498
499 qcom,wdt@f9017000 {
500 compatible = "qcom,msm-watchdog";
501 reg = <0xf9017000 0x1000>;
502 interrupts = <0 3 0 0 4 0>;
503 qcom,bark-time = <11000>;
504 qcom,pet-time = <10000>;
505 qcom,ipi-ping = <1>;
506 };
Hariprasad Dhalinarasimha0fc258f2012-07-05 13:01:29 -0700[diff] [blame]507
508 qcom,tz-log@fe805720 {
509 compatible = "qcom,tz-log";
510 reg = <0xfe805720 0x1000>;
511 };
Tianyi Gou828798d2012-05-02 21:12:38 -0700[diff] [blame]512
513 qcom,venus@fdce0000 {
514 compatible = "qcom,pil-venus";
515 reg = <0xfdce0000 0x4000>,
516 <0xfdc80208 0x8>;
517 vdd-supply = <&gdsc_venus>;
518
519 qcom,firmware-name = "venus";
520 qcom,firmware-min-paddr = <0xF500000>;
521 qcom,firmware-max-paddr = <0xFA00000>;
522 };
Siddartha Mohanadoss05a6e382012-05-14 15:13:37 -0700[diff] [blame]523
524 tsens@fc4a8000 {
525 compatible = "qcom,msm-tsens";
526 reg = <0xfc4a8000 0x2000>,
527 <0xfc4b80d0 0x5>;
528 reg-names = "tsens_physical", "tsens_eeprom_physical";
529 interrupts = <0 184 0>;
530 qcom,sensors = <11>;
531 qcom,slope = <1134 1122 1142 1123 1176 1176 1176 1186 1176
532 1176 1176>;
533 };
Sathish Ambley4df614c2011-10-07 16:30:46 -0700[diff] [blame]534};
Varad Deshmukh18057ed2012-07-03 16:34:53 -0700[diff] [blame]535
536/include/ "msm-pm8x41-rpm-regulator.dtsi"
537/include/ "msm-pm8841.dtsi"
538/include/ "msm-pm8941.dtsi"
539/include/ "msm8974-regulator.dtsi"
540/include/ "msm8974-gpio.dtsi"