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Rajendra Nayak4aef7a22011-02-25 16:06:47 -07001/*
2 * OMAP2 and OMAP3 clockdomain control
3 *
4 * Copyright (C) 2008-2010 Texas Instruments, Inc.
5 * Copyright (C) 2008-2010 Nokia Corporation
6 *
7 * Derived from mach-omap2/clockdomain.c written by Paul Walmsley
8 * Rajendra Nayak <rnayak@ti.com>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
15#include <linux/types.h>
16#include <plat/prcm.h>
17#include "prm.h"
18#include "prm2xxx_3xxx.h"
19#include "cm.h"
20#include "cm2xxx_3xxx.h"
21#include "cm-regbits-24xx.h"
22#include "cm-regbits-34xx.h"
Rajendra Nayak68b921a2011-02-25 16:06:47 -070023#include "prm-regbits-24xx.h"
Rajendra Nayak4aef7a22011-02-25 16:06:47 -070024#include "clockdomain.h"
25
26static int omap2_clkdm_add_wkdep(struct clockdomain *clkdm1,
27 struct clockdomain *clkdm2)
28{
29 omap2_prm_set_mod_reg_bits((1 << clkdm2->dep_bit),
30 clkdm1->pwrdm.ptr->prcm_offs, PM_WKDEP);
31 return 0;
32}
33
34static int omap2_clkdm_del_wkdep(struct clockdomain *clkdm1,
35 struct clockdomain *clkdm2)
36{
37 omap2_prm_clear_mod_reg_bits((1 << clkdm2->dep_bit),
38 clkdm1->pwrdm.ptr->prcm_offs, PM_WKDEP);
39 return 0;
40}
41
42static int omap2_clkdm_read_wkdep(struct clockdomain *clkdm1,
43 struct clockdomain *clkdm2)
44{
45 return omap2_prm_read_mod_bits_shift(clkdm1->pwrdm.ptr->prcm_offs,
46 PM_WKDEP, (1 << clkdm2->dep_bit));
47}
48
49static int omap2_clkdm_clear_all_wkdeps(struct clockdomain *clkdm)
50{
51 struct clkdm_dep *cd;
52 u32 mask = 0;
53
54 for (cd = clkdm->wkdep_srcs; cd && cd->clkdm_name; cd++) {
55 if (!omap_chip_is(cd->omap_chip))
56 continue;
57 if (!cd->clkdm)
58 continue; /* only happens if data is erroneous */
59
60 /* PRM accesses are slow, so minimize them */
61 mask |= 1 << cd->clkdm->dep_bit;
62 atomic_set(&cd->wkdep_usecount, 0);
63 }
64
65 omap2_prm_clear_mod_reg_bits(mask, clkdm->pwrdm.ptr->prcm_offs,
66 PM_WKDEP);
67 return 0;
68}
69
70static int omap3_clkdm_add_sleepdep(struct clockdomain *clkdm1,
71 struct clockdomain *clkdm2)
72{
73 omap2_cm_set_mod_reg_bits((1 << clkdm2->dep_bit),
74 clkdm1->pwrdm.ptr->prcm_offs,
75 OMAP3430_CM_SLEEPDEP);
76 return 0;
77}
78
79static int omap3_clkdm_del_sleepdep(struct clockdomain *clkdm1,
80 struct clockdomain *clkdm2)
81{
82 omap2_cm_clear_mod_reg_bits((1 << clkdm2->dep_bit),
83 clkdm1->pwrdm.ptr->prcm_offs,
84 OMAP3430_CM_SLEEPDEP);
85 return 0;
86}
87
88static int omap3_clkdm_read_sleepdep(struct clockdomain *clkdm1,
89 struct clockdomain *clkdm2)
90{
91 return omap2_prm_read_mod_bits_shift(clkdm1->pwrdm.ptr->prcm_offs,
92 OMAP3430_CM_SLEEPDEP, (1 << clkdm2->dep_bit));
93}
94
95static int omap3_clkdm_clear_all_sleepdeps(struct clockdomain *clkdm)
96{
97 struct clkdm_dep *cd;
98 u32 mask = 0;
99
100 for (cd = clkdm->sleepdep_srcs; cd && cd->clkdm_name; cd++) {
101 if (!omap_chip_is(cd->omap_chip))
102 continue;
103 if (!cd->clkdm)
104 continue; /* only happens if data is erroneous */
105
106 /* PRM accesses are slow, so minimize them */
107 mask |= 1 << cd->clkdm->dep_bit;
108 atomic_set(&cd->sleepdep_usecount, 0);
109 }
110 omap2_prm_clear_mod_reg_bits(mask, clkdm->pwrdm.ptr->prcm_offs,
111 OMAP3430_CM_SLEEPDEP);
112 return 0;
113}
114
Rajendra Nayak68b921a2011-02-25 16:06:47 -0700115static int omap2_clkdm_sleep(struct clockdomain *clkdm)
116{
117 omap2_cm_set_mod_reg_bits(OMAP24XX_FORCESTATE_MASK,
118 clkdm->pwrdm.ptr->prcm_offs,
119 OMAP2_PM_PWSTCTRL);
120 return 0;
121}
122
123static int omap2_clkdm_wakeup(struct clockdomain *clkdm)
124{
125 omap2_cm_clear_mod_reg_bits(OMAP24XX_FORCESTATE_MASK,
126 clkdm->pwrdm.ptr->prcm_offs,
127 OMAP2_PM_PWSTCTRL);
128 return 0;
129}
130
131static int omap3_clkdm_sleep(struct clockdomain *clkdm)
132{
133 omap3xxx_cm_clkdm_force_sleep(clkdm->pwrdm.ptr->prcm_offs,
134 clkdm->clktrctrl_mask);
135 return 0;
136}
137
138static int omap3_clkdm_wakeup(struct clockdomain *clkdm)
139{
140 omap3xxx_cm_clkdm_force_wakeup(clkdm->pwrdm.ptr->prcm_offs,
141 clkdm->clktrctrl_mask);
142 return 0;
143}
144
Rajendra Nayak4aef7a22011-02-25 16:06:47 -0700145struct clkdm_ops omap2_clkdm_operations = {
146 .clkdm_add_wkdep = omap2_clkdm_add_wkdep,
147 .clkdm_del_wkdep = omap2_clkdm_del_wkdep,
148 .clkdm_read_wkdep = omap2_clkdm_read_wkdep,
149 .clkdm_clear_all_wkdeps = omap2_clkdm_clear_all_wkdeps,
Rajendra Nayak68b921a2011-02-25 16:06:47 -0700150 .clkdm_sleep = omap2_clkdm_sleep,
151 .clkdm_wakeup = omap2_clkdm_wakeup,
Rajendra Nayak4aef7a22011-02-25 16:06:47 -0700152};
153
154struct clkdm_ops omap3_clkdm_operations = {
155 .clkdm_add_wkdep = omap2_clkdm_add_wkdep,
156 .clkdm_del_wkdep = omap2_clkdm_del_wkdep,
157 .clkdm_read_wkdep = omap2_clkdm_read_wkdep,
158 .clkdm_clear_all_wkdeps = omap2_clkdm_clear_all_wkdeps,
159 .clkdm_add_sleepdep = omap3_clkdm_add_sleepdep,
160 .clkdm_del_sleepdep = omap3_clkdm_del_sleepdep,
161 .clkdm_read_sleepdep = omap3_clkdm_read_sleepdep,
162 .clkdm_clear_all_sleepdeps = omap3_clkdm_clear_all_sleepdeps,
Rajendra Nayak68b921a2011-02-25 16:06:47 -0700163 .clkdm_sleep = omap3_clkdm_sleep,
164 .clkdm_wakeup = omap3_clkdm_wakeup,
Rajendra Nayak4aef7a22011-02-25 16:06:47 -0700165};