blob: ca919317a0dbed9f8086a256ab408dc60ca0811c [file] [log] [blame]
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001/* Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved.
Steve Mucklea55df6e2010-01-07 12:43:24 -08002 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 *
Steve Mucklea55df6e2010-01-07 12:43:24 -080012 */
13
14#include <linux/kernel.h>
15#include <linux/platform_device.h>
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070016#include <linux/gpio.h>
Steve Muckle9161d302010-02-11 11:50:40 -080017#include <linux/irq.h>
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070018#include <linux/io.h>
Anirudh Ghayal9d9cdc22011-10-10 17:17:07 +053019#include <linux/msm_ssbi.h>
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070020#include <linux/mfd/pmic8058.h>
Steve Mucklea55df6e2010-01-07 12:43:24 -080021
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070022#include <linux/input/pmic8058-keypad.h>
23#include <linux/pmic8058-batt-alarm.h>
24#include <linux/pmic8058-pwrkey.h>
Ashay Jaiswal4d1ab552011-07-15 11:30:49 +053025#include <linux/rtc/rtc-pm8058.h>
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070026#include <linux/pmic8058-vibrator.h>
27#include <linux/leds.h>
28#include <linux/pmic8058-othc.h>
29#include <linux/mfd/pmic8901.h>
30#include <linux/regulator/pmic8058-regulator.h>
31#include <linux/regulator/pmic8901-regulator.h>
32#include <linux/bootmem.h>
33#include <linux/pwm.h>
34#include <linux/pmic8058-pwm.h>
35#include <linux/leds-pmic8058.h>
36#include <linux/pmic8058-xoadc.h>
37#include <linux/msm_adc.h>
38#include <linux/m_adcproc.h>
39#include <linux/mfd/marimba.h>
40#include <linux/msm-charger.h>
41#include <linux/i2c.h>
42#include <linux/i2c/sx150x.h>
43#include <linux/smsc911x.h>
44#include <linux/spi/spi.h>
45#include <linux/input/tdisc_shinetsu.h>
46#include <linux/input/cy8c_ts.h>
47#include <linux/cyttsp.h>
48#include <linux/i2c/isa1200.h>
49#include <linux/dma-mapping.h>
50#include <linux/i2c/bq27520.h>
51
52#ifdef CONFIG_ANDROID_PMEM
53#include <linux/android_pmem.h>
54#endif
55
56#if defined(CONFIG_SMB137B_CHARGER) || defined(CONFIG_SMB137B_CHARGER_MODULE)
57#include <linux/i2c/smb137b.h>
58#endif
Lei Zhou338cab82011-08-19 13:38:17 -040059#ifdef CONFIG_SND_SOC_WM8903
60#include <sound/wm8903.h>
61#endif
Steve Mucklea55df6e2010-01-07 12:43:24 -080062#include <asm/mach-types.h>
63#include <asm/mach/arch.h>
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070064#include <asm/setup.h>
Steve Mucklea55df6e2010-01-07 12:43:24 -080065
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070066#include <mach/dma.h>
67#include <mach/mpp.h>
Steve Mucklea55df6e2010-01-07 12:43:24 -080068#include <mach/board.h>
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070069#include <mach/irqs.h>
70#include <mach/msm_spi.h>
71#include <mach/msm_serial_hs.h>
72#include <mach/msm_serial_hs_lite.h>
Steve Mucklea55df6e2010-01-07 12:43:24 -080073#include <mach/msm_iomap.h>
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070074#include <mach/msm_memtypes.h>
75#include <asm/mach/mmc.h>
76#include <mach/msm_battery.h>
77#include <mach/msm_hsusb.h>
Rohit Vaswania513aa8d2011-07-18 15:14:28 -070078#include <mach/gpiomux.h>
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070079#ifdef CONFIG_MSM_DSPS
80#include <mach/msm_dsps.h>
81#endif
82#include <mach/msm_xo.h>
83#include <mach/msm_bus_board.h>
84#include <mach/socinfo.h>
85#include <linux/i2c/isl9519.h>
86#ifdef CONFIG_USB_G_ANDROID
87#include <linux/usb/android.h>
88#include <mach/usbdiag.h>
89#endif
90#include <linux/regulator/consumer.h>
91#include <linux/regulator/machine.h>
92#include <mach/sdio_al.h>
93#include <mach/rpm.h>
94#include <mach/rpm-regulator.h>
Abhijeet Dharmapurikar6d565fd2011-09-15 18:49:56 -070095#include <mach/restart.h>
Steve Mucklea55df6e2010-01-07 12:43:24 -080096
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070097#include "devices.h"
98#include "devices-msm8x60.h"
99#include "cpuidle.h"
100#include "pm.h"
101#include "mpm.h"
102#include "spm.h"
103#include "rpm_log.h"
104#include "timer.h"
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700105#include "gpiomux-8x60.h"
106#include "rpm_stats.h"
107#include "peripheral-loader.h"
108#include <linux/platform_data/qcom_crypto_device.h>
109#include "rpm_resources.h"
Matt Wagantall6d9ebee2011-08-26 12:15:24 -0700110#include "acpuclock.h"
Maheshkumar Sivasubramanian8ccc16e2011-10-25 15:59:57 -0600111#include "pm-boot.h"
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700112#define MSM_SHARED_RAM_PHYS 0x40000000
113
114/* Macros assume PMIC GPIOs start at 0 */
115#define PM8058_GPIO_BASE NR_MSM_GPIOS
116#define PM8058_GPIO_PM_TO_SYS(pm_gpio) (pm_gpio + PM8058_GPIO_BASE)
117#define PM8058_GPIO_SYS_TO_PM(sys_gpio) (sys_gpio - PM8058_GPIO_BASE)
118#define PM8058_MPP_BASE (PM8058_GPIO_BASE + PM8058_GPIOS)
119#define PM8058_MPP_PM_TO_SYS(pm_gpio) (pm_gpio + PM8058_MPP_BASE)
120#define PM8058_MPP_SYS_TO_PM(sys_gpio) (sys_gpio - PM8058_MPP_BASE)
121#define PM8058_IRQ_BASE (NR_MSM_IRQS + NR_GPIO_IRQS)
122
123#define PM8901_GPIO_BASE (PM8058_GPIO_BASE + \
124 PM8058_GPIOS + PM8058_MPPS)
125#define PM8901_GPIO_PM_TO_SYS(pm_gpio) (pm_gpio + PM8901_GPIO_BASE)
126#define PM8901_GPIO_SYS_TO_PM(sys_gpio) (sys_gpio - PM901_GPIO_BASE)
127#define PM8901_IRQ_BASE (PM8058_IRQ_BASE + \
128 NR_PMIC8058_IRQS)
129
130#define MDM2AP_SYNC 129
131
Terence Hampson1c73fef2011-07-19 17:10:49 -0400132#define GPIO_ETHERNET_RESET_N_DRAGON 30
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700133#define LCDC_SPI_GPIO_CLK 73
134#define LCDC_SPI_GPIO_CS 72
135#define LCDC_SPI_GPIO_MOSI 70
136#define LCDC_AUO_PANEL_NAME "lcdc_auo_wvga"
137#define LCDC_SAMSUNG_OLED_PANEL_NAME "lcdc_samsung_oled"
138#define LCDC_SAMSUNG_WSVGA_PANEL_NAME "lcdc_samsung_wsvga"
139#define LCDC_SAMSUNG_SPI_DEVICE_NAME "lcdc_samsung_ams367pe02"
140#define LCDC_AUO_SPI_DEVICE_NAME "lcdc_auo_nt35582"
Zhang Chang Ken3a8b8512011-08-04 18:41:39 -0400141#define LCDC_NT35582_PANEL_NAME "lcdc_nt35582_wvga"
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700142
Ravishangar Kalyanam61a7bd12011-07-28 16:48:36 -0700143#define PANEL_NAME_MAX_LEN 30
144#define MIPI_CMD_NOVATEK_QHD_PANEL_NAME "mipi_cmd_novatek_qhd"
145#define MIPI_VIDEO_NOVATEK_QHD_PANEL_NAME "mipi_video_novatek_qhd"
146#define MIPI_VIDEO_TOSHIBA_WVGA_PANEL_NAME "mipi_video_toshiba_wvga"
147#define HDMI_PANEL_NAME "hdmi_msm"
148#define TVOUT_PANEL_NAME "tvout_msm"
149
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700150#define DSPS_PIL_GENERIC_NAME "dsps"
151#define DSPS_PIL_FLUID_NAME "dsps_fluid"
152
153enum {
154 GPIO_EXPANDER_IRQ_BASE = PM8901_IRQ_BASE + NR_PMIC8901_IRQS,
155 GPIO_EXPANDER_GPIO_BASE = PM8901_GPIO_BASE + PM8901_MPPS,
156 /* CORE expander */
157 GPIO_CORE_EXPANDER_BASE = GPIO_EXPANDER_GPIO_BASE,
158 GPIO_CLASS_D1_EN = GPIO_CORE_EXPANDER_BASE,
159 GPIO_WLAN_DEEP_SLEEP_N,
160 GPIO_LVDS_SHUTDOWN_N,
161 GPIO_DISP_RESX_N = GPIO_LVDS_SHUTDOWN_N,
162 GPIO_MS_SYS_RESET_N,
163 GPIO_CAP_TS_RESOUT_N,
164 GPIO_CAP_GAUGE_BI_TOUT,
165 GPIO_ETHERNET_PME,
166 GPIO_EXT_GPS_LNA_EN,
167 GPIO_MSM_WAKES_BT,
168 GPIO_ETHERNET_RESET_N,
169 GPIO_HEADSET_DET_N,
170 GPIO_USB_UICC_EN,
171 GPIO_BACKLIGHT_EN,
172 GPIO_EXT_CAMIF_PWR_EN,
173 GPIO_BATT_GAUGE_INT_N,
174 GPIO_BATT_GAUGE_EN,
175 /* DOCKING expander */
176 GPIO_DOCKING_EXPANDER_BASE = GPIO_EXPANDER_GPIO_BASE + 16,
177 GPIO_MIPI_DSI_RST_N = GPIO_DOCKING_EXPANDER_BASE,
178 GPIO_AUX_JTAG_DET_N,
179 GPIO_DONGLE_DET_N,
180 GPIO_SVIDEO_LOAD_DET,
181 GPIO_SVID_AMP_SHUTDOWN1_N,
182 GPIO_SVID_AMP_SHUTDOWN0_N,
183 GPIO_SDC_WP,
184 GPIO_IRDA_PWDN,
185 GPIO_IRDA_RESET_N,
186 GPIO_DONGLE_GPIO0,
187 GPIO_DONGLE_GPIO1,
188 GPIO_DONGLE_GPIO2,
189 GPIO_DONGLE_GPIO3,
190 GPIO_DONGLE_PWR_EN,
191 GPIO_EMMC_RESET_N,
192 GPIO_TP_EXP2_IO15,
193 /* SURF expander */
194 GPIO_SURF_EXPANDER_BASE = GPIO_EXPANDER_GPIO_BASE + (16 * 2),
195 GPIO_SD_CARD_DET_1 = GPIO_SURF_EXPANDER_BASE,
196 GPIO_SD_CARD_DET_2,
197 GPIO_SD_CARD_DET_4,
198 GPIO_SD_CARD_DET_5,
199 GPIO_UIM3_RST,
200 GPIO_SURF_EXPANDER_IO5,
201 GPIO_SURF_EXPANDER_IO6,
202 GPIO_ADC_I2C_EN,
203 GPIO_SURF_EXPANDER_IO8,
204 GPIO_SURF_EXPANDER_IO9,
205 GPIO_SURF_EXPANDER_IO10,
206 GPIO_SURF_EXPANDER_IO11,
207 GPIO_SURF_EXPANDER_IO12,
208 GPIO_SURF_EXPANDER_IO13,
209 GPIO_SURF_EXPANDER_IO14,
210 GPIO_SURF_EXPANDER_IO15,
211 /* LEFT KB IO expander */
212 GPIO_LEFT_KB_EXPANDER_BASE = GPIO_EXPANDER_GPIO_BASE + (16 * 3),
213 GPIO_LEFT_LED_1 = GPIO_LEFT_KB_EXPANDER_BASE,
214 GPIO_LEFT_LED_2,
215 GPIO_LEFT_LED_3,
216 GPIO_LEFT_LED_WLAN,
217 GPIO_JOYSTICK_EN,
218 GPIO_CAP_TS_SLEEP,
219 GPIO_LEFT_KB_IO6,
220 GPIO_LEFT_LED_5,
221 /* RIGHT KB IO expander */
222 GPIO_RIGHT_KB_EXPANDER_BASE = GPIO_EXPANDER_GPIO_BASE + (16 * 3) + 8,
223 GPIO_RIGHT_LED_1 = GPIO_RIGHT_KB_EXPANDER_BASE,
224 GPIO_RIGHT_LED_2,
225 GPIO_RIGHT_LED_3,
226 GPIO_RIGHT_LED_BT,
227 GPIO_WEB_CAMIF_STANDBY,
228 GPIO_COMPASS_RST_N,
229 GPIO_WEB_CAMIF_RESET_N,
230 GPIO_RIGHT_LED_5,
231 GPIO_R_ALTIMETER_RESET_N,
232 /* FLUID S IO expander */
233 GPIO_SOUTH_EXPANDER_BASE,
234 GPIO_MIC2_ANCR_SEL = GPIO_SOUTH_EXPANDER_BASE,
235 GPIO_MIC1_ANCL_SEL,
236 GPIO_HS_MIC4_SEL,
237 GPIO_FML_MIC3_SEL,
238 GPIO_FMR_MIC5_SEL,
239 GPIO_TS_SLEEP,
240 GPIO_HAP_SHIFT_LVL_OE,
241 GPIO_HS_SW_DIR,
242 /* FLUID N IO expander */
243 GPIO_NORTH_EXPANDER_BASE,
244 GPIO_EPM_3_3V_EN = GPIO_NORTH_EXPANDER_BASE,
245 GPIO_EPM_5V_BOOST_EN,
246 GPIO_AUX_CAM_2P7_EN,
247 GPIO_LED_FLASH_EN,
248 GPIO_LED1_GREEN_N,
249 GPIO_LED2_RED_N,
250 GPIO_FRONT_CAM_RESET_N,
251 GPIO_EPM_LVLSFT_EN,
252 GPIO_N_ALTIMETER_RESET_N,
253 /* EPM expander */
254 GPIO_EPM_EXPANDER_BASE,
255 GPIO_PWR_MON_START = GPIO_EPM_EXPANDER_BASE,
256 GPIO_PWR_MON_RESET_N,
257 GPIO_ADC1_PWDN_N,
258 GPIO_ADC2_PWDN_N,
259 GPIO_EPM_EXPANDER_IO4,
260 GPIO_ADC1_MUX_SPI_INT_N_3_3V,
261 GPIO_ADC2_MUX_SPI_INT_N,
262 GPIO_EPM_EXPANDER_IO7,
263 GPIO_PWR_MON_ENABLE,
264 GPIO_EPM_SPI_ADC1_CS_N,
265 GPIO_EPM_SPI_ADC2_CS_N,
266 GPIO_EPM_EXPANDER_IO11,
267 GPIO_EPM_EXPANDER_IO12,
268 GPIO_EPM_EXPANDER_IO13,
269 GPIO_EPM_EXPANDER_IO14,
270 GPIO_EPM_EXPANDER_IO15,
271};
272
273/*
274 * The UI_INTx_N lines are pmic gpio lines which connect i2c
275 * gpio expanders to the pm8058.
276 */
277#define UI_INT1_N 25
278#define UI_INT2_N 34
279#define UI_INT3_N 14
280/*
281FM GPIO is GPIO 18 on PMIC 8058.
282As the index starts from 0 in the PMIC driver, and hence 17
283corresponds to GPIO 18 on PMIC 8058.
284*/
285#define FM_GPIO 17
286
287#ifdef CONFIG_MMC_MSM_SDC2_SUPPORT
288static void (*sdc2_status_notify_cb)(int card_present, void *dev_id);
289static void *sdc2_status_notify_cb_devid;
290#endif
291
292#ifdef CONFIG_MMC_MSM_SDC5_SUPPORT
293static void (*sdc5_status_notify_cb)(int card_present, void *dev_id);
294static void *sdc5_status_notify_cb_devid;
295#endif
296
297static struct msm_spm_platform_data msm_spm_data_v1[] __initdata = {
298 [0] = {
299 .reg_base_addr = MSM_SAW0_BASE,
300
301#ifdef CONFIG_MSM_AVS_HW
302 .reg_init_values[MSM_SPM_REG_SAW_AVS_CTL] = 0x586020FF,
303#endif
304 .reg_init_values[MSM_SPM_REG_SAW_CFG] = 0x0F,
305 .reg_init_values[MSM_SPM_REG_SAW_SPM_CTL] = 0x68,
306 .reg_init_values[MSM_SPM_REG_SAW_SPM_SLP_TMR_DLY] = 0xFFFFFFFF,
307 .reg_init_values[MSM_SPM_REG_SAW_SPM_WAKE_TMR_DLY] = 0xFFFFFFFF,
308
309 .reg_init_values[MSM_SPM_REG_SAW_SLP_CLK_EN] = 0x01,
310 .reg_init_values[MSM_SPM_REG_SAW_SLP_HSFS_PRECLMP_EN] = 0x07,
311 .reg_init_values[MSM_SPM_REG_SAW_SLP_HSFS_POSTCLMP_EN] = 0x00,
312
313 .reg_init_values[MSM_SPM_REG_SAW_SLP_CLMP_EN] = 0x01,
314 .reg_init_values[MSM_SPM_REG_SAW_SLP_RST_EN] = 0x00,
315 .reg_init_values[MSM_SPM_REG_SAW_SPM_MPM_CFG] = 0x00,
316
317 .awake_vlevel = 0x94,
318 .retention_vlevel = 0x81,
319 .collapse_vlevel = 0x20,
320 .retention_mid_vlevel = 0x94,
321 .collapse_mid_vlevel = 0x8C,
322
323 .vctl_timeout_us = 50,
324 },
325
326 [1] = {
327 .reg_base_addr = MSM_SAW1_BASE,
328
329#ifdef CONFIG_MSM_AVS_HW
330 .reg_init_values[MSM_SPM_REG_SAW_AVS_CTL] = 0x586020FF,
331#endif
332 .reg_init_values[MSM_SPM_REG_SAW_CFG] = 0x0F,
333 .reg_init_values[MSM_SPM_REG_SAW_SPM_CTL] = 0x68,
334 .reg_init_values[MSM_SPM_REG_SAW_SPM_SLP_TMR_DLY] = 0xFFFFFFFF,
335 .reg_init_values[MSM_SPM_REG_SAW_SPM_WAKE_TMR_DLY] = 0xFFFFFFFF,
336
337 .reg_init_values[MSM_SPM_REG_SAW_SLP_CLK_EN] = 0x13,
338 .reg_init_values[MSM_SPM_REG_SAW_SLP_HSFS_PRECLMP_EN] = 0x07,
339 .reg_init_values[MSM_SPM_REG_SAW_SLP_HSFS_POSTCLMP_EN] = 0x00,
340
341 .reg_init_values[MSM_SPM_REG_SAW_SLP_CLMP_EN] = 0x01,
342 .reg_init_values[MSM_SPM_REG_SAW_SLP_RST_EN] = 0x00,
343 .reg_init_values[MSM_SPM_REG_SAW_SPM_MPM_CFG] = 0x00,
344
345 .awake_vlevel = 0x94,
346 .retention_vlevel = 0x81,
347 .collapse_vlevel = 0x20,
348 .retention_mid_vlevel = 0x94,
349 .collapse_mid_vlevel = 0x8C,
350
351 .vctl_timeout_us = 50,
352 },
353};
354
355static struct msm_spm_platform_data msm_spm_data[] __initdata = {
356 [0] = {
357 .reg_base_addr = MSM_SAW0_BASE,
358
359#ifdef CONFIG_MSM_AVS_HW
360 .reg_init_values[MSM_SPM_REG_SAW_AVS_CTL] = 0x586020FF,
361#endif
362 .reg_init_values[MSM_SPM_REG_SAW_CFG] = 0x1C,
363 .reg_init_values[MSM_SPM_REG_SAW_SPM_CTL] = 0x68,
364 .reg_init_values[MSM_SPM_REG_SAW_SPM_SLP_TMR_DLY] = 0x0C0CFFFF,
365 .reg_init_values[MSM_SPM_REG_SAW_SPM_WAKE_TMR_DLY] = 0x78780FFF,
366
367 .reg_init_values[MSM_SPM_REG_SAW_SLP_CLK_EN] = 0x01,
368 .reg_init_values[MSM_SPM_REG_SAW_SLP_HSFS_PRECLMP_EN] = 0x07,
369 .reg_init_values[MSM_SPM_REG_SAW_SLP_HSFS_POSTCLMP_EN] = 0x00,
370
371 .reg_init_values[MSM_SPM_REG_SAW_SLP_CLMP_EN] = 0x01,
372 .reg_init_values[MSM_SPM_REG_SAW_SLP_RST_EN] = 0x00,
373 .reg_init_values[MSM_SPM_REG_SAW_SPM_MPM_CFG] = 0x00,
374
375 .awake_vlevel = 0xA0,
376 .retention_vlevel = 0x89,
377 .collapse_vlevel = 0x20,
378 .retention_mid_vlevel = 0x89,
379 .collapse_mid_vlevel = 0x89,
380
381 .vctl_timeout_us = 50,
382 },
383
384 [1] = {
385 .reg_base_addr = MSM_SAW1_BASE,
386
387#ifdef CONFIG_MSM_AVS_HW
388 .reg_init_values[MSM_SPM_REG_SAW_AVS_CTL] = 0x586020FF,
389#endif
390 .reg_init_values[MSM_SPM_REG_SAW_CFG] = 0x1C,
391 .reg_init_values[MSM_SPM_REG_SAW_SPM_CTL] = 0x68,
392 .reg_init_values[MSM_SPM_REG_SAW_SPM_SLP_TMR_DLY] = 0x0C0CFFFF,
393 .reg_init_values[MSM_SPM_REG_SAW_SPM_WAKE_TMR_DLY] = 0x78780FFF,
394
395 .reg_init_values[MSM_SPM_REG_SAW_SLP_CLK_EN] = 0x13,
396 .reg_init_values[MSM_SPM_REG_SAW_SLP_HSFS_PRECLMP_EN] = 0x07,
397 .reg_init_values[MSM_SPM_REG_SAW_SLP_HSFS_POSTCLMP_EN] = 0x00,
398
399 .reg_init_values[MSM_SPM_REG_SAW_SLP_CLMP_EN] = 0x01,
400 .reg_init_values[MSM_SPM_REG_SAW_SLP_RST_EN] = 0x00,
401 .reg_init_values[MSM_SPM_REG_SAW_SPM_MPM_CFG] = 0x00,
402
403 .awake_vlevel = 0xA0,
404 .retention_vlevel = 0x89,
405 .collapse_vlevel = 0x20,
406 .retention_mid_vlevel = 0x89,
407 .collapse_mid_vlevel = 0x89,
408
409 .vctl_timeout_us = 50,
410 },
411};
412
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700413/*
414 * Consumer specific regulator names:
415 * regulator name consumer dev_name
416 */
417static struct regulator_consumer_supply vreg_consumers_8901_S0[] = {
418 REGULATOR_SUPPLY("8901_s0", NULL),
419};
420static struct regulator_consumer_supply vreg_consumers_8901_S1[] = {
421 REGULATOR_SUPPLY("8901_s1", NULL),
422};
423
424static struct regulator_init_data saw_s0_init_data = {
425 .constraints = {
426 .name = "8901_s0",
427 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
Tianyi Gou7c81dfa2011-07-27 12:15:24 -0700428 .min_uV = 800000,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700429 .max_uV = 1250000,
430 },
431 .consumer_supplies = vreg_consumers_8901_S0,
432 .num_consumer_supplies = ARRAY_SIZE(vreg_consumers_8901_S0),
433};
434
435static struct regulator_init_data saw_s1_init_data = {
436 .constraints = {
437 .name = "8901_s1",
438 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
Tianyi Gou7c81dfa2011-07-27 12:15:24 -0700439 .min_uV = 800000,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700440 .max_uV = 1250000,
441 },
442 .consumer_supplies = vreg_consumers_8901_S1,
443 .num_consumer_supplies = ARRAY_SIZE(vreg_consumers_8901_S1),
444};
445
446static struct platform_device msm_device_saw_s0 = {
447 .name = "saw-regulator",
448 .id = 0,
449 .dev = {
450 .platform_data = &saw_s0_init_data,
451 },
452};
453
454static struct platform_device msm_device_saw_s1 = {
455 .name = "saw-regulator",
456 .id = 1,
457 .dev = {
458 .platform_data = &saw_s1_init_data,
459 },
460};
461
462/*
463 * The smc91x configuration varies depending on platform.
464 * The resources data structure is filled in at runtime.
465 */
466static struct resource smc91x_resources[] = {
467 [0] = {
468 .flags = IORESOURCE_MEM,
469 },
470 [1] = {
471 .flags = IORESOURCE_IRQ,
472 },
473};
474
475static struct platform_device smc91x_device = {
476 .name = "smc91x",
477 .id = 0,
478 .num_resources = ARRAY_SIZE(smc91x_resources),
479 .resource = smc91x_resources,
480};
481
482static struct resource smsc911x_resources[] = {
483 [0] = {
484 .flags = IORESOURCE_MEM,
485 .start = 0x1b800000,
486 .end = 0x1b8000ff
487 },
488 [1] = {
489 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
490 },
491};
492
493static struct smsc911x_platform_config smsc911x_config = {
494 .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
495 .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL,
496 .flags = SMSC911X_USE_16BIT,
497 .has_reset_gpio = 1,
498 .reset_gpio = GPIO_ETHERNET_RESET_N
499};
500
501static struct platform_device smsc911x_device = {
502 .name = "smsc911x",
503 .id = 0,
504 .num_resources = ARRAY_SIZE(smsc911x_resources),
505 .resource = smsc911x_resources,
506 .dev = {
507 .platform_data = &smsc911x_config
508 }
509};
510
511#if defined(CONFIG_CRYPTO_DEV_QCRYPTO) || \
512 defined(CONFIG_CRYPTO_DEV_QCRYPTO_MODULE) || \
513 defined(CONFIG_CRYPTO_DEV_QCEDEV) || \
514 defined(CONFIG_CRYPTO_DEV_QCEDEV_MODULE)
515
516#define QCE_SIZE 0x10000
517#define QCE_0_BASE 0x18500000
518
519#define QCE_HW_KEY_SUPPORT 0
520#define QCE_SHA_HMAC_SUPPORT 0
521#define QCE_SHARE_CE_RESOURCE 2
522#define QCE_CE_SHARED 1
523
524static struct resource qcrypto_resources[] = {
525 [0] = {
526 .start = QCE_0_BASE,
527 .end = QCE_0_BASE + QCE_SIZE - 1,
528 .flags = IORESOURCE_MEM,
529 },
530 [1] = {
531 .name = "crypto_channels",
532 .start = DMOV_CE_IN_CHAN,
533 .end = DMOV_CE_OUT_CHAN,
534 .flags = IORESOURCE_DMA,
535 },
536 [2] = {
537 .name = "crypto_crci_in",
538 .start = DMOV_CE_IN_CRCI,
539 .end = DMOV_CE_IN_CRCI,
540 .flags = IORESOURCE_DMA,
541 },
542 [3] = {
543 .name = "crypto_crci_out",
544 .start = DMOV_CE_OUT_CRCI,
545 .end = DMOV_CE_OUT_CRCI,
546 .flags = IORESOURCE_DMA,
547 },
548 [4] = {
549 .name = "crypto_crci_hash",
550 .start = DMOV_CE_HASH_CRCI,
551 .end = DMOV_CE_HASH_CRCI,
552 .flags = IORESOURCE_DMA,
553 },
554};
555
556static struct resource qcedev_resources[] = {
557 [0] = {
558 .start = QCE_0_BASE,
559 .end = QCE_0_BASE + QCE_SIZE - 1,
560 .flags = IORESOURCE_MEM,
561 },
562 [1] = {
563 .name = "crypto_channels",
564 .start = DMOV_CE_IN_CHAN,
565 .end = DMOV_CE_OUT_CHAN,
566 .flags = IORESOURCE_DMA,
567 },
568 [2] = {
569 .name = "crypto_crci_in",
570 .start = DMOV_CE_IN_CRCI,
571 .end = DMOV_CE_IN_CRCI,
572 .flags = IORESOURCE_DMA,
573 },
574 [3] = {
575 .name = "crypto_crci_out",
576 .start = DMOV_CE_OUT_CRCI,
577 .end = DMOV_CE_OUT_CRCI,
578 .flags = IORESOURCE_DMA,
579 },
580 [4] = {
581 .name = "crypto_crci_hash",
582 .start = DMOV_CE_HASH_CRCI,
583 .end = DMOV_CE_HASH_CRCI,
584 .flags = IORESOURCE_DMA,
585 },
586};
587
588#endif
589
590#if defined(CONFIG_CRYPTO_DEV_QCRYPTO) || \
591 defined(CONFIG_CRYPTO_DEV_QCRYPTO_MODULE)
592
593static struct msm_ce_hw_support qcrypto_ce_hw_suppport = {
594 .ce_shared = QCE_CE_SHARED,
595 .shared_ce_resource = QCE_SHARE_CE_RESOURCE,
596 .hw_key_support = QCE_HW_KEY_SUPPORT,
597 .sha_hmac = QCE_SHA_HMAC_SUPPORT,
598};
599
600static struct platform_device qcrypto_device = {
601 .name = "qcrypto",
602 .id = 0,
603 .num_resources = ARRAY_SIZE(qcrypto_resources),
604 .resource = qcrypto_resources,
605 .dev = {
606 .coherent_dma_mask = DMA_BIT_MASK(32),
607 .platform_data = &qcrypto_ce_hw_suppport,
608 },
609};
610#endif
611
612#if defined(CONFIG_CRYPTO_DEV_QCEDEV) || \
613 defined(CONFIG_CRYPTO_DEV_QCEDEV_MODULE)
614
615static struct msm_ce_hw_support qcedev_ce_hw_suppport = {
616 .ce_shared = QCE_CE_SHARED,
617 .shared_ce_resource = QCE_SHARE_CE_RESOURCE,
618 .hw_key_support = QCE_HW_KEY_SUPPORT,
619 .sha_hmac = QCE_SHA_HMAC_SUPPORT,
620};
621
622static struct platform_device qcedev_device = {
623 .name = "qce",
624 .id = 0,
625 .num_resources = ARRAY_SIZE(qcedev_resources),
626 .resource = qcedev_resources,
627 .dev = {
628 .coherent_dma_mask = DMA_BIT_MASK(32),
629 .platform_data = &qcedev_ce_hw_suppport,
630 },
631};
632#endif
633
634#if defined(CONFIG_HAPTIC_ISA1200) || \
635 defined(CONFIG_HAPTIC_ISA1200_MODULE)
636
637static const char *vregs_isa1200_name[] = {
638 "8058_s3",
639 "8901_l4",
640};
641
642static const int vregs_isa1200_val[] = {
643 1800000,/* uV */
644 2600000,
645};
646static struct regulator *vregs_isa1200[ARRAY_SIZE(vregs_isa1200_name)];
647static struct msm_xo_voter *xo_handle_a1;
648
649static int isa1200_power(int vreg_on)
Steve Mucklea55df6e2010-01-07 12:43:24 -0800650{
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700651 int i, rc = 0;
652
653 for (i = 0; i < ARRAY_SIZE(vregs_isa1200_name); i++) {
654 rc = vreg_on ? regulator_enable(vregs_isa1200[i]) :
655 regulator_disable(vregs_isa1200[i]);
656 if (rc < 0) {
657 pr_err("%s: vreg %s %s failed (%d)\n",
658 __func__, vregs_isa1200_name[i],
659 vreg_on ? "enable" : "disable", rc);
660 goto vreg_fail;
661 }
662 }
663
664 rc = vreg_on ? msm_xo_mode_vote(xo_handle_a1, MSM_XO_MODE_ON) :
665 msm_xo_mode_vote(xo_handle_a1, MSM_XO_MODE_OFF);
666 if (rc < 0) {
667 pr_err("%s: failed to %svote for TCXO A1 buffer%d\n",
668 __func__, vreg_on ? "" : "de-", rc);
669 goto vreg_fail;
670 }
671 return 0;
672
673vreg_fail:
674 while (i--)
675 !vreg_on ? regulator_enable(vregs_isa1200[i]) :
676 regulator_disable(vregs_isa1200[i]);
677 return rc;
Steve Mucklea55df6e2010-01-07 12:43:24 -0800678}
679
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700680static int isa1200_dev_setup(bool enable)
Steve Mucklea55df6e2010-01-07 12:43:24 -0800681{
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700682 int i, rc;
Steve Muckle9161d302010-02-11 11:50:40 -0800683
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700684 if (enable == true) {
685 for (i = 0; i < ARRAY_SIZE(vregs_isa1200_name); i++) {
686 vregs_isa1200[i] = regulator_get(NULL,
687 vregs_isa1200_name[i]);
688 if (IS_ERR(vregs_isa1200[i])) {
689 pr_err("%s: regulator get of %s failed (%ld)\n",
690 __func__, vregs_isa1200_name[i],
691 PTR_ERR(vregs_isa1200[i]));
692 rc = PTR_ERR(vregs_isa1200[i]);
693 goto vreg_get_fail;
694 }
695 rc = regulator_set_voltage(vregs_isa1200[i],
696 vregs_isa1200_val[i], vregs_isa1200_val[i]);
697 if (rc) {
698 pr_err("%s: regulator_set_voltage(%s) failed\n",
699 __func__, vregs_isa1200_name[i]);
700 goto vreg_get_fail;
701 }
702 }
Steve Muckle9161d302010-02-11 11:50:40 -0800703
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700704 rc = gpio_request(GPIO_HAP_SHIFT_LVL_OE, "haptics_shft_lvl_oe");
705 if (rc) {
706 pr_err("%s: unable to request gpio %d (%d)\n",
707 __func__, GPIO_HAP_SHIFT_LVL_OE, rc);
708 goto vreg_get_fail;
709 }
Steve Muckle9161d302010-02-11 11:50:40 -0800710
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700711 rc = gpio_direction_output(GPIO_HAP_SHIFT_LVL_OE, 1);
712 if (rc) {
713 pr_err("%s: Unable to set direction\n", __func__);;
714 goto free_gpio;
715 }
716
717 xo_handle_a1 = msm_xo_get(MSM_XO_TCXO_A1, "isa1200");
718 if (IS_ERR(xo_handle_a1)) {
719 rc = PTR_ERR(xo_handle_a1);
720 pr_err("%s: failed to get the handle for A1(%d)\n",
721 __func__, rc);
722 goto gpio_set_dir;
723 }
724 } else {
725 gpio_set_value(GPIO_HAP_SHIFT_LVL_OE, 0);
726 gpio_free(GPIO_HAP_SHIFT_LVL_OE);
727
728 for (i = 0; i < ARRAY_SIZE(vregs_isa1200_name); i++)
729 regulator_put(vregs_isa1200[i]);
730
731 msm_xo_put(xo_handle_a1);
732 }
733
734 return 0;
735gpio_set_dir:
736 gpio_set_value(GPIO_HAP_SHIFT_LVL_OE, 0);
737free_gpio:
738 gpio_free(GPIO_HAP_SHIFT_LVL_OE);
739vreg_get_fail:
740 while (i)
741 regulator_put(vregs_isa1200[--i]);
742 return rc;
743}
744
745#define PMIC_GPIO_HAP_ENABLE 18 /* PMIC GPIO Number 19 */
746static struct isa1200_platform_data isa1200_1_pdata = {
747 .name = "vibrator",
748 .power_on = isa1200_power,
749 .dev_setup = isa1200_dev_setup,
750 /*gpio to enable haptic*/
751 .hap_en_gpio = PM8058_GPIO_PM_TO_SYS(PMIC_GPIO_HAP_ENABLE),
752 .max_timeout = 15000,
753 .mode_ctrl = PWM_GEN_MODE,
754 .pwm_fd = {
755 .pwm_div = 256,
756 },
757 .is_erm = false,
758 .smart_en = true,
759 .ext_clk_en = true,
760 .chip_en = 1,
761};
762
763static struct i2c_board_info msm_isa1200_board_info[] = {
764 {
765 I2C_BOARD_INFO("isa1200_1", 0x90>>1),
766 .platform_data = &isa1200_1_pdata,
767 },
768};
769#endif
770
771#if defined(CONFIG_BATTERY_BQ27520) || \
772 defined(CONFIG_BATTERY_BQ27520_MODULE)
773static struct bq27520_platform_data bq27520_pdata = {
774 .name = "fuel-gauge",
775 .vreg_name = "8058_s3",
776 .vreg_value = 1800000,
777 .soc_int = GPIO_BATT_GAUGE_INT_N,
778 .bi_tout = GPIO_CAP_GAUGE_BI_TOUT,
779 .chip_en = GPIO_BATT_GAUGE_EN,
780 .enable_dlog = 0, /* if enable coulomb counter logger */
781};
782
783static struct i2c_board_info msm_bq27520_board_info[] = {
784 {
785 I2C_BOARD_INFO("bq27520", 0xaa>>1),
786 .platform_data = &bq27520_pdata,
787 },
788};
789#endif
790
791static struct msm_pm_platform_data msm_pm_data[MSM_PM_SLEEP_MODE_NR * 2] = {
792 [MSM_PM_MODE(0, MSM_PM_SLEEP_MODE_POWER_COLLAPSE)] = {
793 .idle_supported = 1,
794 .suspend_supported = 1,
795 .idle_enabled = 0,
796 .suspend_enabled = 0,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700797 },
798
799 [MSM_PM_MODE(0, MSM_PM_SLEEP_MODE_POWER_COLLAPSE_STANDALONE)] = {
800 .idle_supported = 1,
801 .suspend_supported = 1,
802 .idle_enabled = 0,
803 .suspend_enabled = 0,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700804 },
805
806 [MSM_PM_MODE(0, MSM_PM_SLEEP_MODE_WAIT_FOR_INTERRUPT)] = {
807 .idle_supported = 1,
808 .suspend_supported = 1,
809 .idle_enabled = 1,
810 .suspend_enabled = 1,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700811 },
812
813 [MSM_PM_MODE(1, MSM_PM_SLEEP_MODE_POWER_COLLAPSE)] = {
814 .idle_supported = 1,
815 .suspend_supported = 1,
816 .idle_enabled = 0,
817 .suspend_enabled = 0,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700818 },
819
820 [MSM_PM_MODE(1, MSM_PM_SLEEP_MODE_POWER_COLLAPSE_STANDALONE)] = {
821 .idle_supported = 1,
822 .suspend_supported = 1,
823 .idle_enabled = 0,
824 .suspend_enabled = 0,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700825 },
826
827 [MSM_PM_MODE(1, MSM_PM_SLEEP_MODE_WAIT_FOR_INTERRUPT)] = {
828 .idle_supported = 1,
829 .suspend_supported = 1,
830 .idle_enabled = 1,
831 .suspend_enabled = 1,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700832 },
833};
834
835static struct msm_cpuidle_state msm_cstates[] __initdata = {
836 {0, 0, "C0", "WFI",
837 MSM_PM_SLEEP_MODE_WAIT_FOR_INTERRUPT},
838
839 {0, 1, "C1", "STANDALONE_POWER_COLLAPSE",
840 MSM_PM_SLEEP_MODE_POWER_COLLAPSE_STANDALONE},
841
842 {0, 2, "C2", "POWER_COLLAPSE",
843 MSM_PM_SLEEP_MODE_POWER_COLLAPSE},
844
845 {1, 0, "C0", "WFI",
846 MSM_PM_SLEEP_MODE_WAIT_FOR_INTERRUPT},
847
848 {1, 1, "C1", "STANDALONE_POWER_COLLAPSE",
849 MSM_PM_SLEEP_MODE_POWER_COLLAPSE_STANDALONE},
850};
851
852static struct msm_rpmrs_level msm_rpmrs_levels[] __initdata = {
853 {
854 MSM_PM_SLEEP_MODE_WAIT_FOR_INTERRUPT,
855 MSM_RPMRS_LIMITS(ON, ACTIVE, MAX, ACTIVE),
856 true,
857 1, 8000, 100000, 1,
858 },
859
860 {
861 MSM_PM_SLEEP_MODE_POWER_COLLAPSE_STANDALONE,
862 MSM_RPMRS_LIMITS(ON, ACTIVE, MAX, ACTIVE),
863 true,
864 1500, 5000, 60100000, 3000,
865 },
866
867 {
868 MSM_PM_SLEEP_MODE_POWER_COLLAPSE,
869 MSM_RPMRS_LIMITS(ON, ACTIVE, MAX, ACTIVE),
870 false,
871 1800, 5000, 60350000, 3500,
872 },
873 {
874 MSM_PM_SLEEP_MODE_POWER_COLLAPSE,
875 MSM_RPMRS_LIMITS(OFF, ACTIVE, MAX, ACTIVE),
876 false,
877 3800, 4500, 65350000, 5500,
878 },
879
880 {
881 MSM_PM_SLEEP_MODE_POWER_COLLAPSE,
882 MSM_RPMRS_LIMITS(ON, HSFS_OPEN, MAX, ACTIVE),
883 false,
884 2800, 2500, 66850000, 4800,
885 },
886
887 {
888 MSM_PM_SLEEP_MODE_POWER_COLLAPSE,
889 MSM_RPMRS_LIMITS(OFF, HSFS_OPEN, MAX, ACTIVE),
890 false,
891 4800, 2000, 71850000, 6800,
892 },
893
894 {
895 MSM_PM_SLEEP_MODE_POWER_COLLAPSE,
896 MSM_RPMRS_LIMITS(OFF, HSFS_OPEN, ACTIVE, RET_HIGH),
897 false,
898 6800, 500, 75850000, 8800,
899 },
900
901 {
902 MSM_PM_SLEEP_MODE_POWER_COLLAPSE,
903 MSM_RPMRS_LIMITS(OFF, HSFS_OPEN, RET_HIGH, RET_LOW),
904 false,
905 7800, 0, 76350000, 9800,
906 },
907};
908
909#if defined(CONFIG_USB_PEHCI_HCD) || defined(CONFIG_USB_PEHCI_HCD_MODULE)
910
911#define ISP1763_INT_GPIO 117
912#define ISP1763_RST_GPIO 152
913static struct resource isp1763_resources[] = {
914 [0] = {
915 .flags = IORESOURCE_MEM,
916 .start = 0x1D000000,
917 .end = 0x1D005FFF, /* 24KB */
918 },
919 [1] = {
920 .flags = IORESOURCE_IRQ,
921 },
922};
923static void __init msm8x60_cfg_isp1763(void)
924{
925 isp1763_resources[1].start = gpio_to_irq(ISP1763_INT_GPIO);
926 isp1763_resources[1].end = gpio_to_irq(ISP1763_INT_GPIO);
927}
928
929static int isp1763_setup_gpio(int enable)
930{
931 int status = 0;
932
933 if (enable) {
934 status = gpio_request(ISP1763_INT_GPIO, "isp1763_usb");
935 if (status) {
936 pr_err("%s:Failed to request GPIO %d\n",
937 __func__, ISP1763_INT_GPIO);
938 return status;
939 }
940 status = gpio_direction_input(ISP1763_INT_GPIO);
941 if (status) {
942 pr_err("%s:Failed to configure GPIO %d\n",
943 __func__, ISP1763_INT_GPIO);
944 goto gpio_free_int;
945 }
946 status = gpio_request(ISP1763_RST_GPIO, "isp1763_usb");
947 if (status) {
948 pr_err("%s:Failed to request GPIO %d\n",
949 __func__, ISP1763_RST_GPIO);
950 goto gpio_free_int;
951 }
952 status = gpio_direction_output(ISP1763_RST_GPIO, 1);
953 if (status) {
954 pr_err("%s:Failed to configure GPIO %d\n",
955 __func__, ISP1763_RST_GPIO);
956 goto gpio_free_rst;
957 }
958 pr_debug("\nISP GPIO configuration done\n");
959 return status;
960 }
961
962gpio_free_rst:
963 gpio_free(ISP1763_RST_GPIO);
964gpio_free_int:
965 gpio_free(ISP1763_INT_GPIO);
966
967 return status;
968}
969static struct isp1763_platform_data isp1763_pdata = {
970 .reset_gpio = ISP1763_RST_GPIO,
971 .setup_gpio = isp1763_setup_gpio
972};
973
974static struct platform_device isp1763_device = {
975 .name = "isp1763_usb",
976 .num_resources = ARRAY_SIZE(isp1763_resources),
977 .resource = isp1763_resources,
978 .dev = {
979 .platform_data = &isp1763_pdata
980 }
981};
982#endif
983
984#if defined(CONFIG_USB_GADGET_MSM_72K) || defined(CONFIG_USB_EHCI_MSM_72K)
Anji jonnalaeb9e60d2011-10-05 12:19:46 +0530985static struct msm_otg_platform_data msm_otg_pdata;
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700986static struct regulator *ldo6_3p3;
987static struct regulator *ldo7_1p8;
988static struct regulator *vdd_cx;
989#define PMICID_INT PM8058_GPIO_IRQ(PM8058_IRQ_BASE, 36)
990notify_vbus_state notify_vbus_state_func_ptr;
991static int usb_phy_susp_dig_vol = 750000;
992static int pmic_id_notif_supported;
993
994#ifdef CONFIG_USB_EHCI_MSM_72K
995#define USB_PMIC_ID_DET_DELAY msecs_to_jiffies(100)
996struct delayed_work pmic_id_det;
997
998static int __init usb_id_pin_rework_setup(char *support)
999{
1000 if (strncmp(support, "true", 4) == 0)
1001 pmic_id_notif_supported = 1;
1002
1003 return 1;
1004}
1005__setup("usb_id_pin_rework=", usb_id_pin_rework_setup);
1006
1007static void pmic_id_detect(struct work_struct *w)
1008{
1009 int val = gpio_get_value_cansleep(PM8058_GPIO_PM_TO_SYS(36));
1010 pr_debug("%s(): gpio_read_value = %d\n", __func__, val);
1011
1012 if (notify_vbus_state_func_ptr)
1013 (*notify_vbus_state_func_ptr) (val);
1014}
1015
1016static irqreturn_t pmic_id_on_irq(int irq, void *data)
1017{
1018 /*
1019 * Spurious interrupts are observed on pmic gpio line
1020 * even though there is no state change on USB ID. Schedule the
1021 * work to to allow debounce on gpio
Steve Muckle9161d302010-02-11 11:50:40 -08001022 */
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001023 schedule_delayed_work(&pmic_id_det, USB_PMIC_ID_DET_DELAY);
Steve Muckle9161d302010-02-11 11:50:40 -08001024
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001025 return IRQ_HANDLED;
1026}
1027
1028static int msm_hsusb_pmic_id_notif_init(void (*callback)(int online), int init)
1029{
1030 unsigned ret = -ENODEV;
1031
1032 if (!callback)
1033 return -EINVAL;
1034
1035 if (machine_is_msm8x60_fluid())
1036 return -ENOTSUPP;
1037
1038 if (SOCINFO_VERSION_MAJOR(socinfo_get_version()) != 2) {
1039 pr_debug("%s: USB_ID pin is not routed to PMIC"
1040 "on V1 surf/ffa\n", __func__);
1041 return -ENOTSUPP;
1042 }
1043
1044 if ((machine_is_msm8x60_fusion() || machine_is_msm8x60_fusn_ffa()) &&
1045 !pmic_id_notif_supported) {
1046 pr_debug("%s: USB_ID is not routed to PMIC"
1047 "on V2 ffa\n", __func__);
1048 return -ENOTSUPP;
1049 }
1050
1051 usb_phy_susp_dig_vol = 500000;
1052
1053 if (init) {
1054 notify_vbus_state_func_ptr = callback;
1055 ret = pm8901_mpp_config_digital_out(1,
1056 PM8901_MPP_DIG_LEVEL_L5, 1);
1057 if (ret) {
1058 pr_err("%s: MPP2 configuration failed\n", __func__);
1059 return -ENODEV;
1060 }
1061 INIT_DELAYED_WORK(&pmic_id_det, pmic_id_detect);
1062 ret = request_threaded_irq(PMICID_INT, NULL, pmic_id_on_irq,
1063 (IRQF_TRIGGER_RISING|IRQF_TRIGGER_FALLING),
1064 "msm_otg_id", NULL);
1065 if (ret) {
1066 pm8901_mpp_config_digital_out(1,
1067 PM8901_MPP_DIG_LEVEL_L5, 0);
1068 pr_err("%s:pmic_usb_id interrupt registration failed",
1069 __func__);
1070 return ret;
1071 }
1072 /* Notify the initial Id status */
1073 pmic_id_detect(&pmic_id_det.work);
Anji jonnalaeb9e60d2011-10-05 12:19:46 +05301074 msm_otg_pdata.pmic_id_irq = PMICID_INT;
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001075 } else {
1076 free_irq(PMICID_INT, 0);
Anji jonnalaeb9e60d2011-10-05 12:19:46 +05301077 msm_otg_pdata.pmic_id_irq = 0;
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001078 cancel_delayed_work_sync(&pmic_id_det);
1079 notify_vbus_state_func_ptr = NULL;
1080 ret = pm8901_mpp_config_digital_out(1,
1081 PM8901_MPP_DIG_LEVEL_L5, 0);
1082 if (ret) {
1083 pr_err("%s:MPP2 configuration failed\n", __func__);
1084 return -ENODEV;
1085 }
1086 }
1087 return 0;
1088}
1089#endif
1090
1091#define USB_PHY_OPERATIONAL_MIN_VDD_DIG_VOL 1000000
1092#define USB_PHY_MAX_VDD_DIG_VOL 1320000
1093static int msm_hsusb_init_vddcx(int init)
1094{
1095 int ret = 0;
1096
1097 if (init) {
1098 vdd_cx = regulator_get(NULL, "8058_s1");
1099 if (IS_ERR(vdd_cx)) {
1100 return PTR_ERR(vdd_cx);
1101 }
1102
1103 ret = regulator_set_voltage(vdd_cx,
1104 USB_PHY_OPERATIONAL_MIN_VDD_DIG_VOL,
1105 USB_PHY_MAX_VDD_DIG_VOL);
1106 if (ret) {
1107 pr_err("%s: unable to set the voltage for regulator"
1108 "vdd_cx\n", __func__);
1109 regulator_put(vdd_cx);
1110 return ret;
1111 }
1112
1113 ret = regulator_enable(vdd_cx);
1114 if (ret) {
1115 pr_err("%s: unable to enable regulator"
1116 "vdd_cx\n", __func__);
1117 regulator_put(vdd_cx);
1118 }
1119 } else {
1120 ret = regulator_disable(vdd_cx);
1121 if (ret) {
1122 pr_err("%s: Unable to disable the regulator:"
1123 "vdd_cx\n", __func__);
1124 return ret;
1125 }
1126
1127 regulator_put(vdd_cx);
1128 }
1129
1130 return ret;
1131}
1132
1133static int msm_hsusb_config_vddcx(int high)
1134{
1135 int max_vol = USB_PHY_MAX_VDD_DIG_VOL;
1136 int min_vol;
1137 int ret;
1138
1139 if (high)
1140 min_vol = USB_PHY_OPERATIONAL_MIN_VDD_DIG_VOL;
1141 else
1142 min_vol = usb_phy_susp_dig_vol;
1143
1144 ret = regulator_set_voltage(vdd_cx, min_vol, max_vol);
1145 if (ret) {
1146 pr_err("%s: unable to set the voltage for regulator"
1147 "vdd_cx\n", __func__);
1148 return ret;
1149 }
1150
1151 pr_debug("%s: min_vol:%d max_vol:%d\n", __func__, min_vol, max_vol);
1152
1153 return ret;
1154}
1155
1156#define USB_PHY_3P3_VOL_MIN 3050000 /* uV */
1157#define USB_PHY_3P3_VOL_MAX 3050000 /* uV */
1158#define USB_PHY_3P3_HPM_LOAD 50000 /* uA */
1159#define USB_PHY_3P3_LPM_LOAD 4000 /* uA */
1160
1161#define USB_PHY_1P8_VOL_MIN 1800000 /* uV */
1162#define USB_PHY_1P8_VOL_MAX 1800000 /* uV */
1163#define USB_PHY_1P8_HPM_LOAD 50000 /* uA */
1164#define USB_PHY_1P8_LPM_LOAD 4000 /* uA */
1165static int msm_hsusb_ldo_init(int init)
1166{
1167 int rc = 0;
1168
1169 if (init) {
1170 ldo6_3p3 = regulator_get(NULL, "8058_l6");
1171 if (IS_ERR(ldo6_3p3))
1172 return PTR_ERR(ldo6_3p3);
1173
1174 ldo7_1p8 = regulator_get(NULL, "8058_l7");
1175 if (IS_ERR(ldo7_1p8)) {
1176 rc = PTR_ERR(ldo7_1p8);
1177 goto put_3p3;
1178 }
1179
1180 rc = regulator_set_voltage(ldo6_3p3, USB_PHY_3P3_VOL_MIN,
1181 USB_PHY_3P3_VOL_MAX);
1182 if (rc) {
1183 pr_err("%s: Unable to set voltage level for"
1184 "ldo6_3p3 regulator\n", __func__);
1185 goto put_1p8;
1186 }
1187 rc = regulator_enable(ldo6_3p3);
1188 if (rc) {
1189 pr_err("%s: Unable to enable the regulator:"
1190 "ldo6_3p3\n", __func__);
1191 goto put_1p8;
1192 }
1193 rc = regulator_set_voltage(ldo7_1p8, USB_PHY_1P8_VOL_MIN,
1194 USB_PHY_1P8_VOL_MAX);
1195 if (rc) {
1196 pr_err("%s: Unable to set voltage level for"
1197 "ldo7_1p8 regulator\n", __func__);
1198 goto disable_3p3;
1199 }
1200 rc = regulator_enable(ldo7_1p8);
1201 if (rc) {
1202 pr_err("%s: Unable to enable the regulator:"
1203 "ldo7_1p8\n", __func__);
1204 goto disable_3p3;
1205 }
1206
1207 return 0;
1208 }
1209
1210 regulator_disable(ldo7_1p8);
1211disable_3p3:
1212 regulator_disable(ldo6_3p3);
1213put_1p8:
1214 regulator_put(ldo7_1p8);
1215put_3p3:
1216 regulator_put(ldo6_3p3);
1217 return rc;
1218}
1219
1220static int msm_hsusb_ldo_enable(int on)
1221{
1222 int ret = 0;
1223
1224 if (!ldo7_1p8 || IS_ERR(ldo7_1p8)) {
1225 pr_err("%s: ldo7_1p8 is not initialized\n", __func__);
1226 return -ENODEV;
1227 }
1228
1229 if (!ldo6_3p3 || IS_ERR(ldo6_3p3)) {
1230 pr_err("%s: ldo6_3p3 is not initialized\n", __func__);
1231 return -ENODEV;
1232 }
1233
1234 if (on) {
1235 ret = regulator_set_optimum_mode(ldo7_1p8,
1236 USB_PHY_1P8_HPM_LOAD);
1237 if (ret < 0) {
1238 pr_err("%s: Unable to set HPM of the regulator:"
1239 "ldo7_1p8\n", __func__);
1240 return ret;
1241 }
1242 ret = regulator_set_optimum_mode(ldo6_3p3,
1243 USB_PHY_3P3_HPM_LOAD);
1244 if (ret < 0) {
1245 pr_err("%s: Unable to set HPM of the regulator:"
1246 "ldo6_3p3\n", __func__);
1247 regulator_set_optimum_mode(ldo7_1p8,
1248 USB_PHY_1P8_LPM_LOAD);
1249 return ret;
1250 }
1251 } else {
1252 ret = regulator_set_optimum_mode(ldo7_1p8,
1253 USB_PHY_1P8_LPM_LOAD);
1254 if (ret < 0)
1255 pr_err("%s: Unable to set LPM of the regulator:"
1256 "ldo7_1p8\n", __func__);
1257 ret = regulator_set_optimum_mode(ldo6_3p3,
1258 USB_PHY_3P3_LPM_LOAD);
1259 if (ret < 0)
1260 pr_err("%s: Unable to set LPM of the regulator:"
1261 "ldo6_3p3\n", __func__);
1262 }
1263
1264 pr_debug("reg (%s)\n", on ? "HPM" : "LPM");
1265 return ret < 0 ? ret : 0;
1266 }
1267#endif
1268#ifdef CONFIG_USB_EHCI_MSM_72K
1269#if defined(CONFIG_SMB137B_CHARGER) || defined(CONFIG_SMB137B_CHARGER_MODULE)
1270static void msm_hsusb_smb137b_vbus_power(unsigned phy_info, int on)
1271{
1272 static int vbus_is_on;
1273
1274 /* If VBUS is already on (or off), do nothing. */
1275 if (on == vbus_is_on)
1276 return;
1277 smb137b_otg_power(on);
1278 vbus_is_on = on;
1279}
1280#endif
1281static void msm_hsusb_vbus_power(unsigned phy_info, int on)
1282{
1283 static struct regulator *votg_5v_switch;
1284 static struct regulator *ext_5v_reg;
1285 static int vbus_is_on;
1286
1287 /* If VBUS is already on (or off), do nothing. */
1288 if (on == vbus_is_on)
1289 return;
1290
1291 if (!votg_5v_switch) {
1292 votg_5v_switch = regulator_get(NULL, "8901_usb_otg");
1293 if (IS_ERR(votg_5v_switch)) {
1294 pr_err("%s: unable to get votg_5v_switch\n", __func__);
1295 return;
1296 }
1297 }
1298 if (!ext_5v_reg) {
1299 ext_5v_reg = regulator_get(NULL, "8901_mpp0");
1300 if (IS_ERR(ext_5v_reg)) {
1301 pr_err("%s: unable to get ext_5v_reg\n", __func__);
1302 return;
1303 }
1304 }
1305 if (on) {
1306 if (regulator_enable(ext_5v_reg)) {
1307 pr_err("%s: Unable to enable the regulator:"
1308 " ext_5v_reg\n", __func__);
1309 return;
1310 }
1311 if (regulator_enable(votg_5v_switch)) {
1312 pr_err("%s: Unable to enable the regulator:"
1313 " votg_5v_switch\n", __func__);
1314 return;
1315 }
1316 } else {
1317 if (regulator_disable(votg_5v_switch))
1318 pr_err("%s: Unable to enable the regulator:"
1319 " votg_5v_switch\n", __func__);
1320 if (regulator_disable(ext_5v_reg))
1321 pr_err("%s: Unable to enable the regulator:"
1322 " ext_5v_reg\n", __func__);
1323 }
1324
1325 vbus_is_on = on;
1326}
1327
1328static struct msm_usb_host_platform_data msm_usb_host_pdata = {
1329 .phy_info = (USB_PHY_INTEGRATED | USB_PHY_MODEL_45NM),
1330 .power_budget = 390,
1331};
1332#endif
1333
1334#ifdef CONFIG_BATTERY_MSM8X60
1335static int msm_hsusb_pmic_vbus_notif_init(void (*callback)(int online),
1336 int init)
1337{
1338 int ret = -ENOTSUPP;
1339
1340#if defined(CONFIG_SMB137B_CHARGER) || defined(CONFIG_SMB137B_CHARGER_MODULE)
1341 if (machine_is_msm8x60_fluid()) {
1342 if (init)
1343 msm_charger_register_vbus_sn(callback);
1344 else
1345 msm_charger_unregister_vbus_sn(callback);
1346 return 0;
1347 }
1348#endif
1349 /* ID and VBUS lines are connected to pmic on 8660.V2.SURF,
1350 * hence, irrespective of either peripheral only mode or
1351 * OTG (host and peripheral) modes, can depend on pmic for
1352 * vbus notifications
Steve Muckle9161d302010-02-11 11:50:40 -08001353 */
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001354 if ((SOCINFO_VERSION_MAJOR(socinfo_get_version()) == 2)
1355 && (machine_is_msm8x60_surf() ||
1356 pmic_id_notif_supported)) {
1357 if (init)
1358 ret = msm_charger_register_vbus_sn(callback);
1359 else {
1360 msm_charger_unregister_vbus_sn(callback);
1361 ret = 0;
1362 }
1363 } else {
1364#if !defined(CONFIG_USB_EHCI_MSM_72K)
1365 if (init)
1366 ret = msm_charger_register_vbus_sn(callback);
1367 else {
1368 msm_charger_unregister_vbus_sn(callback);
1369 ret = 0;
1370 }
1371#endif
1372 }
1373 return ret;
1374}
1375#endif
1376
1377#if defined(CONFIG_USB_GADGET_MSM_72K) || defined(CONFIG_USB_EHCI_MSM_72K)
1378static struct msm_otg_platform_data msm_otg_pdata = {
1379 /* if usb link is in sps there is no need for
1380 * usb pclk as dayatona fabric clock will be
1381 * used instead
1382 */
1383 .pclk_src_name = "dfab_usb_hs_clk",
1384 .pemp_level = PRE_EMPHASIS_WITH_20_PERCENT,
1385 .cdr_autoreset = CDR_AUTO_RESET_DISABLE,
1386 .se1_gating = SE1_GATING_DISABLE,
Chandra Devireddyb3fc78c2011-08-30 17:25:55 +05301387 .bam_disable = 1,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001388#ifdef CONFIG_USB_EHCI_MSM_72K
1389 .pmic_id_notif_init = msm_hsusb_pmic_id_notif_init,
1390#endif
1391#ifdef CONFIG_USB_EHCI_MSM_72K
1392 .vbus_power = msm_hsusb_vbus_power,
1393#endif
1394#ifdef CONFIG_BATTERY_MSM8X60
1395 .pmic_vbus_notif_init = msm_hsusb_pmic_vbus_notif_init,
1396#endif
1397 .ldo_init = msm_hsusb_ldo_init,
1398 .ldo_enable = msm_hsusb_ldo_enable,
1399 .config_vddcx = msm_hsusb_config_vddcx,
1400 .init_vddcx = msm_hsusb_init_vddcx,
1401#ifdef CONFIG_BATTERY_MSM8X60
1402 .chg_vbus_draw = msm_charger_vbus_draw,
1403#endif
1404};
1405#endif
1406
1407#ifdef CONFIG_USB_GADGET_MSM_72K
1408static struct msm_hsusb_gadget_platform_data msm_gadget_pdata = {
1409 .is_phy_status_timer_on = 1,
1410};
1411#endif
1412
1413#ifdef CONFIG_USB_G_ANDROID
1414
1415#define PID_MAGIC_ID 0x71432909
1416#define SERIAL_NUM_MAGIC_ID 0x61945374
1417#define SERIAL_NUMBER_LENGTH 127
1418#define DLOAD_USB_BASE_ADD 0x2A05F0C8
1419
1420struct magic_num_struct {
1421 uint32_t pid;
1422 uint32_t serial_num;
1423};
1424
1425struct dload_struct {
1426 uint32_t reserved1;
1427 uint32_t reserved2;
1428 uint32_t reserved3;
1429 uint16_t reserved4;
1430 uint16_t pid;
1431 char serial_number[SERIAL_NUMBER_LENGTH];
1432 uint16_t reserved5;
1433 struct magic_num_struct
1434 magic_struct;
1435};
1436
1437static int usb_diag_update_pid_and_serial_num(uint32_t pid, const char *snum)
1438{
1439 struct dload_struct __iomem *dload = 0;
1440
1441 dload = ioremap(DLOAD_USB_BASE_ADD, sizeof(*dload));
1442 if (!dload) {
1443 pr_err("%s: cannot remap I/O memory region: %08x\n",
1444 __func__, DLOAD_USB_BASE_ADD);
1445 return -ENXIO;
1446 }
1447
1448 pr_debug("%s: dload:%p pid:%x serial_num:%s\n",
1449 __func__, dload, pid, snum);
1450 /* update pid */
1451 dload->magic_struct.pid = PID_MAGIC_ID;
1452 dload->pid = pid;
1453
1454 /* update serial number */
1455 dload->magic_struct.serial_num = 0;
1456 if (!snum)
1457 return 0;
1458
1459 dload->magic_struct.serial_num = SERIAL_NUM_MAGIC_ID;
1460 strncpy(dload->serial_number, snum, SERIAL_NUMBER_LENGTH);
1461 dload->serial_number[SERIAL_NUMBER_LENGTH - 1] = '\0';
1462
1463 iounmap(dload);
1464
1465 return 0;
1466}
1467
1468static struct android_usb_platform_data android_usb_pdata = {
1469 .update_pid_and_serial_num = usb_diag_update_pid_and_serial_num,
1470};
1471
1472static struct platform_device android_usb_device = {
1473 .name = "android_usb",
1474 .id = -1,
1475 .dev = {
1476 .platform_data = &android_usb_pdata,
1477 },
1478};
1479
1480
1481#endif
1482
1483#ifdef CONFIG_MSM_VPE
1484static struct resource msm_vpe_resources[] = {
1485 {
1486 .start = 0x05300000,
1487 .end = 0x05300000 + SZ_1M - 1,
1488 .flags = IORESOURCE_MEM,
1489 },
1490 {
1491 .start = INT_VPE,
1492 .end = INT_VPE,
1493 .flags = IORESOURCE_IRQ,
1494 },
1495};
1496
1497static struct platform_device msm_vpe_device = {
1498 .name = "msm_vpe",
1499 .id = 0,
1500 .num_resources = ARRAY_SIZE(msm_vpe_resources),
1501 .resource = msm_vpe_resources,
1502};
1503#endif
1504
1505#ifdef CONFIG_MSM_CAMERA
1506#ifdef CONFIG_MSM_CAMERA_FLASH
1507#define VFE_CAMIF_TIMER1_GPIO 29
1508#define VFE_CAMIF_TIMER2_GPIO 30
1509#define VFE_CAMIF_TIMER3_GPIO_INT 31
1510#define FUSION_VFE_CAMIF_TIMER1_GPIO 42
1511static struct msm_camera_sensor_flash_src msm_flash_src = {
1512 .flash_sr_type = MSM_CAMERA_FLASH_SRC_PMIC,
1513 ._fsrc.pmic_src.num_of_src = 2,
1514 ._fsrc.pmic_src.low_current = 100,
1515 ._fsrc.pmic_src.high_current = 300,
1516 ._fsrc.pmic_src.led_src_1 = PMIC8058_ID_FLASH_LED_0,
1517 ._fsrc.pmic_src.led_src_2 = PMIC8058_ID_FLASH_LED_1,
1518 ._fsrc.pmic_src.pmic_set_current = pm8058_set_flash_led_current,
1519};
1520#ifdef CONFIG_IMX074
1521static struct msm_camera_sensor_strobe_flash_data strobe_flash_xenon = {
1522 .flash_trigger = VFE_CAMIF_TIMER2_GPIO,
1523 .flash_charge = VFE_CAMIF_TIMER1_GPIO,
1524 .flash_charge_done = VFE_CAMIF_TIMER3_GPIO_INT,
1525 .flash_recharge_duration = 50000,
1526 .irq = MSM_GPIO_TO_INT(VFE_CAMIF_TIMER3_GPIO_INT),
1527};
1528#endif
1529#endif
1530
1531int msm_cam_gpio_tbl[] = {
1532 32,/*CAMIF_MCLK*/
1533 47,/*CAMIF_I2C_DATA*/
1534 48,/*CAMIF_I2C_CLK*/
1535 105,/*STANDBY*/
1536};
1537
1538enum msm_cam_stat{
1539 MSM_CAM_OFF,
1540 MSM_CAM_ON,
1541};
1542
1543static int config_gpio_table(enum msm_cam_stat stat)
1544{
1545 int rc = 0, i = 0;
1546 if (stat == MSM_CAM_ON) {
1547 for (i = 0; i < ARRAY_SIZE(msm_cam_gpio_tbl); i++) {
1548 rc = gpio_request(msm_cam_gpio_tbl[i], "CAM_GPIO");
1549 if (unlikely(rc < 0)) {
1550 pr_err("%s not able to get gpio\n", __func__);
1551 for (i--; i >= 0; i--)
1552 gpio_free(msm_cam_gpio_tbl[i]);
1553 break;
1554 }
1555 }
1556 } else {
1557 for (i = 0; i < ARRAY_SIZE(msm_cam_gpio_tbl); i++)
1558 gpio_free(msm_cam_gpio_tbl[i]);
1559 }
1560 return rc;
1561}
1562
1563static struct msm_camera_sensor_platform_info sensor_board_info = {
1564 .mount_angle = 0
1565};
1566
1567/*external regulator VREG_5V*/
1568static struct regulator *reg_flash_5V;
1569
1570static int config_camera_on_gpios_fluid(void)
1571{
1572 int rc = 0;
1573
1574 reg_flash_5V = regulator_get(NULL, "8901_mpp0");
1575 if (IS_ERR(reg_flash_5V)) {
1576 pr_err("'%s' regulator not found, rc=%ld\n",
1577 "8901_mpp0", IS_ERR(reg_flash_5V));
1578 return -ENODEV;
1579 }
1580
1581 rc = regulator_enable(reg_flash_5V);
1582 if (rc) {
1583 pr_err("'%s' regulator enable failed, rc=%d\n",
1584 "8901_mpp0", rc);
1585 regulator_put(reg_flash_5V);
1586 return rc;
1587 }
1588
1589#ifdef CONFIG_IMX074
1590 sensor_board_info.mount_angle = 90;
1591#endif
1592 rc = config_gpio_table(MSM_CAM_ON);
1593 if (rc < 0) {
1594 printk(KERN_ERR "%s: CAMSENSOR gpio table request"
1595 "failed\n", __func__);
1596 return rc;
1597 }
1598
1599 rc = gpio_request(GPIO_EXT_CAMIF_PWR_EN, "CAM_EN");
1600 if (rc < 0) {
1601 printk(KERN_ERR "%s: CAMSENSOR gpio %d request"
1602 "failed\n", __func__, GPIO_EXT_CAMIF_PWR_EN);
1603 regulator_disable(reg_flash_5V);
1604 regulator_put(reg_flash_5V);
1605 return rc;
1606 }
1607 gpio_direction_output(GPIO_EXT_CAMIF_PWR_EN, 0);
1608 msleep(20);
1609 gpio_set_value_cansleep(GPIO_EXT_CAMIF_PWR_EN, 1);
1610
1611
1612 /*Enable LED_FLASH_EN*/
1613 rc = gpio_request(GPIO_LED_FLASH_EN, "LED_FLASH_EN");
1614 if (rc < 0) {
1615 printk(KERN_ERR "%s: CAMSENSOR gpio %d request"
1616 "failed\n", __func__, GPIO_LED_FLASH_EN);
1617
1618 regulator_disable(reg_flash_5V);
1619 regulator_put(reg_flash_5V);
1620 config_gpio_table(MSM_CAM_OFF);
1621 gpio_set_value_cansleep(GPIO_EXT_CAMIF_PWR_EN, 0);
1622 gpio_free(GPIO_EXT_CAMIF_PWR_EN);
1623 return rc;
1624 }
1625 gpio_direction_output(GPIO_LED_FLASH_EN, 1);
1626 msleep(20);
1627 return rc;
1628}
1629
1630
1631static void config_camera_off_gpios_fluid(void)
1632{
1633 regulator_disable(reg_flash_5V);
1634 regulator_put(reg_flash_5V);
1635
1636 gpio_direction_output(GPIO_LED_FLASH_EN, 0);
1637 gpio_free(GPIO_LED_FLASH_EN);
1638
1639 config_gpio_table(MSM_CAM_OFF);
1640
1641 gpio_set_value_cansleep(GPIO_EXT_CAMIF_PWR_EN, 0);
1642 gpio_free(GPIO_EXT_CAMIF_PWR_EN);
1643}
1644static int config_camera_on_gpios(void)
1645{
1646 int rc = 0;
1647
1648 if (machine_is_msm8x60_fluid())
1649 return config_camera_on_gpios_fluid();
1650
1651 rc = config_gpio_table(MSM_CAM_ON);
1652 if (rc < 0) {
1653 printk(KERN_ERR "%s: CAMSENSOR gpio table request"
1654 "failed\n", __func__);
1655 return rc;
1656 }
1657
Jilai Wang971f97f2011-07-13 14:25:25 -04001658 if (!machine_is_msm8x60_dragon()) {
1659 rc = gpio_request(GPIO_EXT_CAMIF_PWR_EN, "CAM_EN");
1660 if (rc < 0) {
1661 config_gpio_table(MSM_CAM_OFF);
1662 pr_err("%s: CAMSENSOR gpio %d request"
1663 "failed\n", __func__, GPIO_EXT_CAMIF_PWR_EN);
1664 return rc;
1665 }
1666 gpio_direction_output(GPIO_EXT_CAMIF_PWR_EN, 0);
1667 msleep(20);
1668 gpio_set_value_cansleep(GPIO_EXT_CAMIF_PWR_EN, 1);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001669 }
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001670
1671#ifdef CONFIG_MSM_CAMERA_FLASH
1672#ifdef CONFIG_IMX074
1673 if (machine_is_msm8x60_fusion() || machine_is_msm8x60_fusn_ffa())
1674 strobe_flash_xenon.flash_charge = FUSION_VFE_CAMIF_TIMER1_GPIO;
1675#endif
1676#endif
1677 return rc;
1678}
1679
1680static void config_camera_off_gpios(void)
1681{
1682 if (machine_is_msm8x60_fluid())
1683 return config_camera_off_gpios_fluid();
1684
1685
1686 config_gpio_table(MSM_CAM_OFF);
1687
Jilai Wang971f97f2011-07-13 14:25:25 -04001688 if (!machine_is_msm8x60_dragon()) {
1689 gpio_set_value_cansleep(GPIO_EXT_CAMIF_PWR_EN, 0);
1690 gpio_free(GPIO_EXT_CAMIF_PWR_EN);
1691 }
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001692}
1693
1694#ifdef CONFIG_QS_S5K4E1
1695
1696#define QS_CAM_HC37_CAM_PD PM8058_GPIO_PM_TO_SYS(26)
1697
1698static int config_camera_on_gpios_qs_cam_fluid(void)
1699{
1700 int rc = 0;
1701
1702 /* request QS_CAM_HC37_CAM_PD as an output to HC37 ASIC pin CAM_PD */
1703 rc = gpio_request(QS_CAM_HC37_CAM_PD, "QS_CAM_HC37_CAM_PD");
1704 if (rc < 0) {
1705 printk(KERN_ERR "%s: QS_CAM_HC37_CAM_PD gpio %d request"
1706 " failed\n", __func__, QS_CAM_HC37_CAM_PD);
1707 return rc;
1708 }
1709 gpio_direction_output(QS_CAM_HC37_CAM_PD, 0);
1710 msleep(20);
1711 gpio_set_value_cansleep(QS_CAM_HC37_CAM_PD, 1);
1712 msleep(20);
1713
1714 /*
1715 * Set GPIO_AUX_CAM_2P7_EN to 1 on North Expander IO2
1716 * to enable 2.7V power to Camera
1717 */
1718 rc = gpio_request(GPIO_AUX_CAM_2P7_EN, "CAM_2P7_EN");
1719 if (rc < 0) {
1720 printk(KERN_ERR "%s: CAMSENSOR gpio %d request"
1721 " failed\n", __func__, GPIO_AUX_CAM_2P7_EN);
1722 gpio_set_value_cansleep(QS_CAM_HC37_CAM_PD, 0);
1723 gpio_free(QS_CAM_HC37_CAM_PD);
1724 return rc;
1725 }
1726 gpio_direction_output(GPIO_AUX_CAM_2P7_EN, 0);
1727 msleep(20);
1728 gpio_set_value_cansleep(GPIO_AUX_CAM_2P7_EN, 1);
1729 msleep(20);
1730
1731 rc = config_camera_on_gpios_fluid();
1732 if (rc < 0) {
1733 printk(KERN_ERR "%s: config_camera_on_gpios_fluid"
1734 " failed\n", __func__);
1735 gpio_set_value_cansleep(QS_CAM_HC37_CAM_PD, 0);
1736 gpio_free(QS_CAM_HC37_CAM_PD);
1737 gpio_set_value_cansleep(GPIO_AUX_CAM_2P7_EN, 0);
1738 gpio_free(GPIO_AUX_CAM_2P7_EN);
1739 return rc;
1740 }
1741 return rc;
1742}
1743
1744static void config_camera_off_gpios_qs_cam_fluid(void)
1745{
1746 /*
1747 * Set GPIO_AUX_CAM_2P7_EN to 0 on North Expander IO2
1748 * to disable 2.7V power to Camera
1749 */
1750 gpio_set_value_cansleep(GPIO_AUX_CAM_2P7_EN, 0);
1751 gpio_free(GPIO_AUX_CAM_2P7_EN);
1752
1753 /* set QS_CAM_HC37_CAM_PD to 0 to power off HC37 ASIC*/
1754 gpio_set_value_cansleep(QS_CAM_HC37_CAM_PD, 0);
1755 gpio_free(QS_CAM_HC37_CAM_PD);
1756
1757 config_camera_off_gpios_fluid();
1758 return;
1759}
1760
1761static int config_camera_on_gpios_qs_cam(void)
1762{
1763 int rc = 0;
1764
1765 if (machine_is_msm8x60_fluid())
1766 return config_camera_on_gpios_qs_cam_fluid();
1767
1768 rc = config_camera_on_gpios();
1769 return rc;
1770}
1771
1772static void config_camera_off_gpios_qs_cam(void)
1773{
1774 if (machine_is_msm8x60_fluid())
1775 return config_camera_off_gpios_qs_cam_fluid();
1776
1777 config_camera_off_gpios();
1778 return;
1779}
1780#endif
1781
1782static int config_camera_on_gpios_web_cam(void)
1783{
1784 int rc = 0;
1785 rc = config_gpio_table(MSM_CAM_ON);
1786 if (rc < 0) {
1787 printk(KERN_ERR "%s: CAMSENSOR gpio table request"
1788 "failed\n", __func__);
1789 return rc;
1790 }
1791
Jilai Wang53d27a82011-07-13 14:32:58 -04001792 if (!(machine_is_msm8x60_fluid() || machine_is_msm8x60_dragon())) {
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001793 rc = gpio_request(GPIO_WEB_CAMIF_STANDBY, "CAM_EN");
1794 if (rc < 0) {
1795 config_gpio_table(MSM_CAM_OFF);
1796 pr_err(KERN_ERR "%s: CAMSENSOR gpio %d request"
1797 "failed\n", __func__, GPIO_WEB_CAMIF_STANDBY);
1798 return rc;
1799 }
1800 gpio_direction_output(GPIO_WEB_CAMIF_STANDBY, 0);
1801 }
1802 return rc;
1803}
1804
1805static void config_camera_off_gpios_web_cam(void)
1806{
1807 config_gpio_table(MSM_CAM_OFF);
Jilai Wang53d27a82011-07-13 14:32:58 -04001808 if (!(machine_is_msm8x60_fluid() || machine_is_msm8x60_dragon())) {
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001809 gpio_set_value_cansleep(GPIO_WEB_CAMIF_STANDBY, 1);
1810 gpio_free(GPIO_WEB_CAMIF_STANDBY);
1811 }
1812 return;
1813}
1814
1815#ifdef CONFIG_MSM_BUS_SCALING
1816static struct msm_bus_vectors cam_init_vectors[] = {
1817 {
1818 .src = MSM_BUS_MASTER_VFE,
1819 .dst = MSM_BUS_SLAVE_SMI,
1820 .ab = 0,
1821 .ib = 0,
1822 },
1823 {
1824 .src = MSM_BUS_MASTER_VFE,
1825 .dst = MSM_BUS_SLAVE_EBI_CH0,
1826 .ab = 0,
1827 .ib = 0,
1828 },
1829 {
1830 .src = MSM_BUS_MASTER_VPE,
1831 .dst = MSM_BUS_SLAVE_SMI,
1832 .ab = 0,
1833 .ib = 0,
1834 },
1835 {
1836 .src = MSM_BUS_MASTER_VPE,
1837 .dst = MSM_BUS_SLAVE_EBI_CH0,
1838 .ab = 0,
1839 .ib = 0,
1840 },
1841 {
1842 .src = MSM_BUS_MASTER_JPEG_ENC,
1843 .dst = MSM_BUS_SLAVE_SMI,
1844 .ab = 0,
1845 .ib = 0,
1846 },
1847 {
1848 .src = MSM_BUS_MASTER_JPEG_ENC,
1849 .dst = MSM_BUS_SLAVE_EBI_CH0,
1850 .ab = 0,
1851 .ib = 0,
1852 },
1853};
1854
1855static struct msm_bus_vectors cam_preview_vectors[] = {
1856 {
1857 .src = MSM_BUS_MASTER_VFE,
1858 .dst = MSM_BUS_SLAVE_SMI,
1859 .ab = 0,
1860 .ib = 0,
1861 },
1862 {
1863 .src = MSM_BUS_MASTER_VFE,
1864 .dst = MSM_BUS_SLAVE_EBI_CH0,
1865 .ab = 283115520,
1866 .ib = 452984832,
1867 },
1868 {
1869 .src = MSM_BUS_MASTER_VPE,
1870 .dst = MSM_BUS_SLAVE_SMI,
1871 .ab = 0,
1872 .ib = 0,
1873 },
1874 {
1875 .src = MSM_BUS_MASTER_VPE,
1876 .dst = MSM_BUS_SLAVE_EBI_CH0,
1877 .ab = 0,
1878 .ib = 0,
1879 },
1880 {
1881 .src = MSM_BUS_MASTER_JPEG_ENC,
1882 .dst = MSM_BUS_SLAVE_SMI,
1883 .ab = 0,
1884 .ib = 0,
1885 },
1886 {
1887 .src = MSM_BUS_MASTER_JPEG_ENC,
1888 .dst = MSM_BUS_SLAVE_EBI_CH0,
1889 .ab = 0,
1890 .ib = 0,
1891 },
1892};
1893
1894static struct msm_bus_vectors cam_video_vectors[] = {
1895 {
1896 .src = MSM_BUS_MASTER_VFE,
1897 .dst = MSM_BUS_SLAVE_SMI,
1898 .ab = 283115520,
1899 .ib = 452984832,
1900 },
1901 {
1902 .src = MSM_BUS_MASTER_VFE,
1903 .dst = MSM_BUS_SLAVE_EBI_CH0,
1904 .ab = 283115520,
1905 .ib = 452984832,
1906 },
1907 {
1908 .src = MSM_BUS_MASTER_VPE,
1909 .dst = MSM_BUS_SLAVE_SMI,
1910 .ab = 319610880,
1911 .ib = 511377408,
1912 },
1913 {
1914 .src = MSM_BUS_MASTER_VPE,
1915 .dst = MSM_BUS_SLAVE_EBI_CH0,
1916 .ab = 0,
1917 .ib = 0,
1918 },
1919 {
1920 .src = MSM_BUS_MASTER_JPEG_ENC,
1921 .dst = MSM_BUS_SLAVE_SMI,
1922 .ab = 0,
1923 .ib = 0,
1924 },
1925 {
1926 .src = MSM_BUS_MASTER_JPEG_ENC,
1927 .dst = MSM_BUS_SLAVE_EBI_CH0,
1928 .ab = 0,
1929 .ib = 0,
1930 },
1931};
1932
1933static struct msm_bus_vectors cam_snapshot_vectors[] = {
1934 {
1935 .src = MSM_BUS_MASTER_VFE,
1936 .dst = MSM_BUS_SLAVE_SMI,
1937 .ab = 566231040,
1938 .ib = 905969664,
1939 },
1940 {
1941 .src = MSM_BUS_MASTER_VFE,
1942 .dst = MSM_BUS_SLAVE_EBI_CH0,
1943 .ab = 69984000,
1944 .ib = 111974400,
1945 },
1946 {
1947 .src = MSM_BUS_MASTER_VPE,
1948 .dst = MSM_BUS_SLAVE_SMI,
1949 .ab = 0,
1950 .ib = 0,
1951 },
1952 {
1953 .src = MSM_BUS_MASTER_VPE,
1954 .dst = MSM_BUS_SLAVE_EBI_CH0,
1955 .ab = 0,
1956 .ib = 0,
1957 },
1958 {
1959 .src = MSM_BUS_MASTER_JPEG_ENC,
1960 .dst = MSM_BUS_SLAVE_SMI,
1961 .ab = 320864256,
1962 .ib = 513382810,
1963 },
1964 {
1965 .src = MSM_BUS_MASTER_JPEG_ENC,
1966 .dst = MSM_BUS_SLAVE_EBI_CH0,
1967 .ab = 320864256,
1968 .ib = 513382810,
1969 },
1970};
1971
1972static struct msm_bus_vectors cam_zsl_vectors[] = {
1973 {
1974 .src = MSM_BUS_MASTER_VFE,
1975 .dst = MSM_BUS_SLAVE_SMI,
1976 .ab = 566231040,
1977 .ib = 905969664,
1978 },
1979 {
1980 .src = MSM_BUS_MASTER_VFE,
1981 .dst = MSM_BUS_SLAVE_EBI_CH0,
1982 .ab = 706199040,
1983 .ib = 1129918464,
1984 },
1985 {
1986 .src = MSM_BUS_MASTER_VPE,
1987 .dst = MSM_BUS_SLAVE_SMI,
1988 .ab = 0,
1989 .ib = 0,
1990 },
1991 {
1992 .src = MSM_BUS_MASTER_VPE,
1993 .dst = MSM_BUS_SLAVE_EBI_CH0,
1994 .ab = 0,
1995 .ib = 0,
1996 },
1997 {
1998 .src = MSM_BUS_MASTER_JPEG_ENC,
1999 .dst = MSM_BUS_SLAVE_SMI,
2000 .ab = 320864256,
2001 .ib = 513382810,
2002 },
2003 {
2004 .src = MSM_BUS_MASTER_JPEG_ENC,
2005 .dst = MSM_BUS_SLAVE_EBI_CH0,
2006 .ab = 320864256,
2007 .ib = 513382810,
2008 },
2009};
2010
2011static struct msm_bus_vectors cam_stereo_video_vectors[] = {
2012 {
2013 .src = MSM_BUS_MASTER_VFE,
2014 .dst = MSM_BUS_SLAVE_SMI,
2015 .ab = 212336640,
2016 .ib = 339738624,
2017 },
2018 {
2019 .src = MSM_BUS_MASTER_VFE,
2020 .dst = MSM_BUS_SLAVE_EBI_CH0,
2021 .ab = 25090560,
2022 .ib = 40144896,
2023 },
2024 {
2025 .src = MSM_BUS_MASTER_VPE,
2026 .dst = MSM_BUS_SLAVE_SMI,
2027 .ab = 239708160,
2028 .ib = 383533056,
2029 },
2030 {
2031 .src = MSM_BUS_MASTER_VPE,
2032 .dst = MSM_BUS_SLAVE_EBI_CH0,
2033 .ab = 79902720,
2034 .ib = 127844352,
2035 },
2036 {
2037 .src = MSM_BUS_MASTER_JPEG_ENC,
2038 .dst = MSM_BUS_SLAVE_SMI,
2039 .ab = 0,
2040 .ib = 0,
2041 },
2042 {
2043 .src = MSM_BUS_MASTER_JPEG_ENC,
2044 .dst = MSM_BUS_SLAVE_EBI_CH0,
2045 .ab = 0,
2046 .ib = 0,
2047 },
2048};
2049
2050static struct msm_bus_vectors cam_stereo_snapshot_vectors[] = {
2051 {
2052 .src = MSM_BUS_MASTER_VFE,
2053 .dst = MSM_BUS_SLAVE_SMI,
2054 .ab = 0,
2055 .ib = 0,
2056 },
2057 {
2058 .src = MSM_BUS_MASTER_VFE,
2059 .dst = MSM_BUS_SLAVE_EBI_CH0,
2060 .ab = 300902400,
2061 .ib = 481443840,
2062 },
2063 {
2064 .src = MSM_BUS_MASTER_VPE,
2065 .dst = MSM_BUS_SLAVE_SMI,
2066 .ab = 230307840,
2067 .ib = 368492544,
2068 },
2069 {
2070 .src = MSM_BUS_MASTER_VPE,
2071 .dst = MSM_BUS_SLAVE_EBI_CH0,
2072 .ab = 245113344,
2073 .ib = 392181351,
2074 },
2075 {
2076 .src = MSM_BUS_MASTER_JPEG_ENC,
2077 .dst = MSM_BUS_SLAVE_SMI,
2078 .ab = 106536960,
2079 .ib = 170459136,
2080 },
2081 {
2082 .src = MSM_BUS_MASTER_JPEG_ENC,
2083 .dst = MSM_BUS_SLAVE_EBI_CH0,
2084 .ab = 106536960,
2085 .ib = 170459136,
2086 },
2087};
2088
2089static struct msm_bus_paths cam_bus_client_config[] = {
2090 {
2091 ARRAY_SIZE(cam_init_vectors),
2092 cam_init_vectors,
2093 },
2094 {
2095 ARRAY_SIZE(cam_preview_vectors),
2096 cam_preview_vectors,
2097 },
2098 {
2099 ARRAY_SIZE(cam_video_vectors),
2100 cam_video_vectors,
2101 },
2102 {
2103 ARRAY_SIZE(cam_snapshot_vectors),
2104 cam_snapshot_vectors,
2105 },
2106 {
2107 ARRAY_SIZE(cam_zsl_vectors),
2108 cam_zsl_vectors,
2109 },
2110 {
2111 ARRAY_SIZE(cam_stereo_video_vectors),
2112 cam_stereo_video_vectors,
2113 },
2114 {
2115 ARRAY_SIZE(cam_stereo_snapshot_vectors),
2116 cam_stereo_snapshot_vectors,
2117 },
2118};
2119
2120static struct msm_bus_scale_pdata cam_bus_client_pdata = {
2121 cam_bus_client_config,
2122 ARRAY_SIZE(cam_bus_client_config),
2123 .name = "msm_camera",
2124};
2125#endif
2126
2127struct msm_camera_device_platform_data msm_camera_device_data = {
2128 .camera_gpio_on = config_camera_on_gpios,
2129 .camera_gpio_off = config_camera_off_gpios,
2130 .ioext.csiphy = 0x04800000,
2131 .ioext.csisz = 0x00000400,
2132 .ioext.csiirq = CSI_0_IRQ,
2133 .ioclk.mclk_clk_rate = 24000000,
2134 .ioclk.vfe_clk_rate = 228570000,
2135#ifdef CONFIG_MSM_BUS_SCALING
2136 .cam_bus_scale_table = &cam_bus_client_pdata,
2137#endif
2138};
2139
2140#ifdef CONFIG_QS_S5K4E1
2141struct msm_camera_device_platform_data msm_camera_device_data_qs_cam = {
2142 .camera_gpio_on = config_camera_on_gpios_qs_cam,
2143 .camera_gpio_off = config_camera_off_gpios_qs_cam,
2144 .ioext.csiphy = 0x04800000,
2145 .ioext.csisz = 0x00000400,
2146 .ioext.csiirq = CSI_0_IRQ,
2147 .ioclk.mclk_clk_rate = 24000000,
2148 .ioclk.vfe_clk_rate = 228570000,
2149#ifdef CONFIG_MSM_BUS_SCALING
2150 .cam_bus_scale_table = &cam_bus_client_pdata,
2151#endif
2152};
2153#endif
2154
2155struct msm_camera_device_platform_data msm_camera_device_data_web_cam = {
2156 .camera_gpio_on = config_camera_on_gpios_web_cam,
2157 .camera_gpio_off = config_camera_off_gpios_web_cam,
2158 .ioext.csiphy = 0x04900000,
2159 .ioext.csisz = 0x00000400,
2160 .ioext.csiirq = CSI_1_IRQ,
2161 .ioclk.mclk_clk_rate = 24000000,
2162 .ioclk.vfe_clk_rate = 228570000,
2163#ifdef CONFIG_MSM_BUS_SCALING
2164 .cam_bus_scale_table = &cam_bus_client_pdata,
2165#endif
2166};
2167
2168struct resource msm_camera_resources[] = {
2169 {
2170 .start = 0x04500000,
2171 .end = 0x04500000 + SZ_1M - 1,
2172 .flags = IORESOURCE_MEM,
2173 },
2174 {
2175 .start = VFE_IRQ,
2176 .end = VFE_IRQ,
2177 .flags = IORESOURCE_IRQ,
2178 },
2179};
2180#ifdef CONFIG_MT9E013
2181static struct msm_camera_sensor_platform_info mt9e013_sensor_8660_info = {
2182 .mount_angle = 0
2183};
2184
2185static struct msm_camera_sensor_flash_data flash_mt9e013 = {
2186 .flash_type = MSM_CAMERA_FLASH_LED,
2187 .flash_src = &msm_flash_src
2188};
2189
2190static struct msm_camera_sensor_info msm_camera_sensor_mt9e013_data = {
2191 .sensor_name = "mt9e013",
2192 .sensor_reset = 106,
2193 .sensor_pwd = 85,
2194 .vcm_pwd = 1,
2195 .vcm_enable = 0,
2196 .pdata = &msm_camera_device_data,
2197 .resource = msm_camera_resources,
2198 .num_resources = ARRAY_SIZE(msm_camera_resources),
2199 .flash_data = &flash_mt9e013,
2200 .strobe_flash_data = &strobe_flash_xenon,
2201 .sensor_platform_info = &mt9e013_sensor_8660_info,
2202 .csi_if = 1
2203};
2204struct platform_device msm_camera_sensor_mt9e013 = {
2205 .name = "msm_camera_mt9e013",
2206 .dev = {
2207 .platform_data = &msm_camera_sensor_mt9e013_data,
2208 },
2209};
2210#endif
2211
2212#ifdef CONFIG_IMX074
Roja Rani Yarubandi68ebb4d2011-10-20 10:33:16 +05302213static struct msm_camera_sensor_platform_info imx074_sensor_board_info = {
2214 .mount_angle = 180
2215};
2216
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002217static struct msm_camera_sensor_flash_data flash_imx074 = {
2218 .flash_type = MSM_CAMERA_FLASH_LED,
2219 .flash_src = &msm_flash_src
2220};
2221
2222static struct msm_camera_sensor_info msm_camera_sensor_imx074_data = {
2223 .sensor_name = "imx074",
2224 .sensor_reset = 106,
2225 .sensor_pwd = 85,
2226 .vcm_pwd = GPIO_AUX_CAM_2P7_EN,
2227 .vcm_enable = 1,
2228 .pdata = &msm_camera_device_data,
2229 .resource = msm_camera_resources,
2230 .num_resources = ARRAY_SIZE(msm_camera_resources),
2231 .flash_data = &flash_imx074,
2232 .strobe_flash_data = &strobe_flash_xenon,
Roja Rani Yarubandi68ebb4d2011-10-20 10:33:16 +05302233 .sensor_platform_info = &imx074_sensor_board_info,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002234 .csi_if = 1
2235};
2236struct platform_device msm_camera_sensor_imx074 = {
2237 .name = "msm_camera_imx074",
2238 .dev = {
2239 .platform_data = &msm_camera_sensor_imx074_data,
2240 },
2241};
2242#endif
2243#ifdef CONFIG_WEBCAM_OV9726
2244
2245static struct msm_camera_sensor_platform_info ov9726_sensor_8660_info = {
2246 .mount_angle = 0
2247};
2248
2249static struct msm_camera_sensor_flash_data flash_ov9726 = {
2250 .flash_type = MSM_CAMERA_FLASH_LED,
2251 .flash_src = &msm_flash_src
2252};
2253static struct msm_camera_sensor_info msm_camera_sensor_ov9726_data = {
2254 .sensor_name = "ov9726",
Kevin Chan3382c512011-07-19 21:00:45 -07002255 .sensor_reset_enable = 1,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002256 .sensor_reset = GPIO_FRONT_CAM_RESET_N,
2257 .sensor_pwd = 85,
2258 .vcm_pwd = 1,
2259 .vcm_enable = 0,
2260 .pdata = &msm_camera_device_data_web_cam,
2261 .resource = msm_camera_resources,
2262 .num_resources = ARRAY_SIZE(msm_camera_resources),
2263 .flash_data = &flash_ov9726,
2264 .sensor_platform_info = &ov9726_sensor_8660_info,
2265 .csi_if = 1
2266};
2267struct platform_device msm_camera_sensor_webcam_ov9726 = {
2268 .name = "msm_camera_ov9726",
2269 .dev = {
2270 .platform_data = &msm_camera_sensor_ov9726_data,
2271 },
2272};
2273#endif
2274#ifdef CONFIG_WEBCAM_OV7692
2275static struct msm_camera_sensor_flash_data flash_ov7692 = {
2276 .flash_type = MSM_CAMERA_FLASH_LED,
2277 .flash_src = &msm_flash_src
2278};
2279static struct msm_camera_sensor_info msm_camera_sensor_ov7692_data = {
2280 .sensor_name = "ov7692",
2281 .sensor_reset = GPIO_WEB_CAMIF_RESET_N,
2282 .sensor_pwd = 85,
2283 .vcm_pwd = 1,
2284 .vcm_enable = 0,
2285 .pdata = &msm_camera_device_data_web_cam,
2286 .resource = msm_camera_resources,
2287 .num_resources = ARRAY_SIZE(msm_camera_resources),
2288 .flash_data = &flash_ov7692,
2289 .csi_if = 1
2290};
2291
2292static struct platform_device msm_camera_sensor_webcam_ov7692 = {
2293 .name = "msm_camera_ov7692",
2294 .dev = {
2295 .platform_data = &msm_camera_sensor_ov7692_data,
2296 },
2297};
2298#endif
Jilai Wang971f97f2011-07-13 14:25:25 -04002299#ifdef CONFIG_VX6953
2300static struct msm_camera_sensor_platform_info vx6953_sensor_8660_info = {
2301 .mount_angle = 270
2302};
2303
2304static struct msm_camera_sensor_flash_data flash_vx6953 = {
2305 .flash_type = MSM_CAMERA_FLASH_NONE,
2306 .flash_src = &msm_flash_src
2307};
2308
2309static struct msm_camera_sensor_info msm_camera_sensor_vx6953_data = {
2310 .sensor_name = "vx6953",
2311 .sensor_reset = 63,
2312 .sensor_pwd = 63,
2313 .vcm_pwd = GPIO_AUX_CAM_2P7_EN,
2314 .vcm_enable = 1,
2315 .pdata = &msm_camera_device_data,
2316 .resource = msm_camera_resources,
2317 .num_resources = ARRAY_SIZE(msm_camera_resources),
2318 .flash_data = &flash_vx6953,
2319 .sensor_platform_info = &vx6953_sensor_8660_info,
2320 .csi_if = 1
2321};
2322struct platform_device msm_camera_sensor_vx6953 = {
2323 .name = "msm_camera_vx6953",
2324 .dev = {
2325 .platform_data = &msm_camera_sensor_vx6953_data,
2326 },
2327};
2328#endif
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002329#ifdef CONFIG_QS_S5K4E1
2330
Nishant Pandit613ab7a2011-09-02 03:36:01 +05302331static struct msm_camera_sensor_platform_info qs_s5k4e1_sensor_8660_info = {
2332#ifdef CONFIG_FB_MSM_MIPI_NOVATEK_CMD_QHD_PT
2333 .mount_angle = 90
2334#else
2335 .mount_angle = 0
2336#endif
2337};
2338
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002339static char eeprom_data[864];
2340static struct msm_camera_sensor_flash_data flash_qs_s5k4e1 = {
2341 .flash_type = MSM_CAMERA_FLASH_LED,
2342 .flash_src = &msm_flash_src
2343};
2344
2345static struct msm_camera_sensor_info msm_camera_sensor_qs_s5k4e1_data = {
2346 .sensor_name = "qs_s5k4e1",
2347 .sensor_reset = 106,
2348 .sensor_pwd = 85,
2349 .vcm_pwd = 1,
2350 .vcm_enable = 0,
2351 .pdata = &msm_camera_device_data_qs_cam,
2352 .resource = msm_camera_resources,
2353 .num_resources = ARRAY_SIZE(msm_camera_resources),
2354 .flash_data = &flash_qs_s5k4e1,
2355 .strobe_flash_data = &strobe_flash_xenon,
Nishant Pandit613ab7a2011-09-02 03:36:01 +05302356 .sensor_platform_info = &qs_s5k4e1_sensor_8660_info,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002357 .csi_if = 1,
2358 .eeprom_data = eeprom_data,
2359};
2360struct platform_device msm_camera_sensor_qs_s5k4e1 = {
2361 .name = "msm_camera_qs_s5k4e1",
2362 .dev = {
2363 .platform_data = &msm_camera_sensor_qs_s5k4e1_data,
2364 },
2365};
2366#endif
2367static struct i2c_board_info msm_camera_boardinfo[] __initdata = {
2368 #ifdef CONFIG_MT9E013
2369 {
2370 I2C_BOARD_INFO("mt9e013", 0x6C >> 2),
2371 },
2372 #endif
2373 #ifdef CONFIG_IMX074
2374 {
2375 I2C_BOARD_INFO("imx074", 0x1A),
2376 },
2377 #endif
2378 #ifdef CONFIG_WEBCAM_OV7692
2379 {
2380 I2C_BOARD_INFO("ov7692", 0x78),
2381 },
2382 #endif
2383 #ifdef CONFIG_WEBCAM_OV9726
2384 {
2385 I2C_BOARD_INFO("ov9726", 0x10),
2386 },
2387 #endif
2388 #ifdef CONFIG_QS_S5K4E1
2389 {
2390 I2C_BOARD_INFO("qs_s5k4e1", 0x20),
2391 },
2392 #endif
2393};
Jilai Wang971f97f2011-07-13 14:25:25 -04002394
2395static struct i2c_board_info msm_camera_dragon_boardinfo[] __initdata = {
Jilai Wang53d27a82011-07-13 14:32:58 -04002396 #ifdef CONFIG_WEBCAM_OV9726
2397 {
2398 I2C_BOARD_INFO("ov9726", 0x10),
2399 },
2400 #endif
Jilai Wang971f97f2011-07-13 14:25:25 -04002401 #ifdef CONFIG_VX6953
2402 {
2403 I2C_BOARD_INFO("vx6953", 0x20),
2404 },
2405 #endif
2406};
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002407#endif
2408
2409#ifdef CONFIG_MSM_GEMINI
2410static struct resource msm_gemini_resources[] = {
2411 {
2412 .start = 0x04600000,
2413 .end = 0x04600000 + SZ_1M - 1,
2414 .flags = IORESOURCE_MEM,
2415 },
2416 {
2417 .start = INT_JPEG,
2418 .end = INT_JPEG,
2419 .flags = IORESOURCE_IRQ,
2420 },
2421};
2422
2423static struct platform_device msm_gemini_device = {
2424 .name = "msm_gemini",
2425 .resource = msm_gemini_resources,
2426 .num_resources = ARRAY_SIZE(msm_gemini_resources),
2427};
2428#endif
2429
2430#ifdef CONFIG_I2C_QUP
2431static void gsbi_qup_i2c_gpio_config(int adap_id, int config_type)
2432{
2433}
2434
2435static struct msm_i2c_platform_data msm_gsbi3_qup_i2c_pdata = {
2436 .clk_freq = 384000,
2437 .src_clk_rate = 24000000,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002438 .msm_i2c_config_gpio = gsbi_qup_i2c_gpio_config,
2439};
2440
2441static struct msm_i2c_platform_data msm_gsbi4_qup_i2c_pdata = {
2442 .clk_freq = 100000,
2443 .src_clk_rate = 24000000,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002444 .msm_i2c_config_gpio = gsbi_qup_i2c_gpio_config,
2445};
2446
2447static struct msm_i2c_platform_data msm_gsbi7_qup_i2c_pdata = {
2448 .clk_freq = 100000,
2449 .src_clk_rate = 24000000,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002450 .msm_i2c_config_gpio = gsbi_qup_i2c_gpio_config,
2451};
2452
2453static struct msm_i2c_platform_data msm_gsbi8_qup_i2c_pdata = {
2454 .clk_freq = 100000,
2455 .src_clk_rate = 24000000,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002456 .msm_i2c_config_gpio = gsbi_qup_i2c_gpio_config,
2457};
2458
2459static struct msm_i2c_platform_data msm_gsbi9_qup_i2c_pdata = {
2460 .clk_freq = 100000,
2461 .src_clk_rate = 24000000,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002462 .msm_i2c_config_gpio = gsbi_qup_i2c_gpio_config,
2463};
2464
2465static struct msm_i2c_platform_data msm_gsbi12_qup_i2c_pdata = {
2466 .clk_freq = 100000,
2467 .src_clk_rate = 24000000,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002468 .use_gsbi_shared_mode = 1,
2469 .msm_i2c_config_gpio = gsbi_qup_i2c_gpio_config,
2470};
2471#endif
2472
2473#if defined(CONFIG_SPI_QUP) || defined(CONFIG_SPI_QUP_MODULE)
2474static struct msm_spi_platform_data msm_gsbi1_qup_spi_pdata = {
2475 .max_clock_speed = 24000000,
2476};
2477
2478static struct msm_spi_platform_data msm_gsbi10_qup_spi_pdata = {
2479 .max_clock_speed = 24000000,
2480};
2481#endif
2482
2483#ifdef CONFIG_I2C_SSBI
2484/* PMIC SSBI */
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002485static struct msm_i2c_ssbi_platform_data msm_ssbi2_pdata = {
2486 .controller_type = MSM_SBI_CTRL_PMIC_ARBITER,
2487};
2488
2489/* CODEC/TSSC SSBI */
2490static struct msm_i2c_ssbi_platform_data msm_ssbi3_pdata = {
2491 .controller_type = MSM_SBI_CTRL_SSBI,
2492};
2493#endif
2494
2495#ifdef CONFIG_BATTERY_MSM
2496/* Use basic value for fake MSM battery */
2497static struct msm_psy_batt_pdata msm_psy_batt_data = {
2498 .avail_chg_sources = AC_CHG,
2499};
2500
2501static struct platform_device msm_batt_device = {
2502 .name = "msm-battery",
2503 .id = -1,
2504 .dev.platform_data = &msm_psy_batt_data,
2505};
2506#endif
2507
2508#ifdef CONFIG_FB_MSM_LCDC_DSUB
2509/* VGA = 1440 x 900 x 4(bpp) x 2(pages)
2510 prim = 1024 x 600 x 4(bpp) x 2(pages)
2511 This is the difference. */
2512#define MSM_FB_DSUB_PMEM_ADDER (0xA32000-0x4B0000)
2513#else
2514#define MSM_FB_DSUB_PMEM_ADDER (0)
2515#endif
2516
2517/* Sensors DSPS platform data */
2518#ifdef CONFIG_MSM_DSPS
2519
2520static struct dsps_gpio_info dsps_surf_gpios[] = {
2521 {
2522 .name = "compass_rst_n",
2523 .num = GPIO_COMPASS_RST_N,
2524 .on_val = 1, /* device not in reset */
2525 .off_val = 0, /* device in reset */
2526 },
2527 {
2528 .name = "gpio_r_altimeter_reset_n",
2529 .num = GPIO_R_ALTIMETER_RESET_N,
2530 .on_val = 1, /* device not in reset */
2531 .off_val = 0, /* device in reset */
2532 }
2533};
2534
2535static struct dsps_gpio_info dsps_fluid_gpios[] = {
2536 {
2537 .name = "gpio_n_altimeter_reset_n",
2538 .num = GPIO_N_ALTIMETER_RESET_N,
2539 .on_val = 1, /* device not in reset */
2540 .off_val = 0, /* device in reset */
2541 }
2542};
2543
2544static void __init msm8x60_init_dsps(void)
2545{
2546 struct msm_dsps_platform_data *pdata =
2547 msm_dsps_device.dev.platform_data;
2548 /*
2549 * On Fluid the Compass sensor Chip-Select (CS) is directly connected
2550 * to the power supply and not controled via GPIOs. Fluid uses a
2551 * different IO-Expender (north) than used on surf/ffa.
2552 */
2553 if (machine_is_msm8x60_fluid()) {
2554 /* fluid has different firmware, gpios */
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002555 pdata->pil_name = DSPS_PIL_FLUID_NAME;
2556 pdata->gpios = dsps_fluid_gpios;
2557 pdata->gpios_num = ARRAY_SIZE(dsps_fluid_gpios);
2558 } else {
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002559 pdata->pil_name = DSPS_PIL_GENERIC_NAME;
2560 pdata->gpios = dsps_surf_gpios;
2561 pdata->gpios_num = ARRAY_SIZE(dsps_surf_gpios);
2562 }
2563
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002564 platform_device_register(&msm_dsps_device);
2565}
2566#endif /* CONFIG_MSM_DSPS */
2567
2568#ifdef CONFIG_FB_MSM_TRIPLE_BUFFER
kuogee hsiehc9a2e6d2011-09-12 15:27:01 -07002569#define MSM_FB_PRIM_BUF_SIZE (1024 * 600 * 4 * 3) /* 4 bpp x 3 pages */
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002570#else
kuogee hsiehc9a2e6d2011-09-12 15:27:01 -07002571#define MSM_FB_PRIM_BUF_SIZE (1024 * 600 * 4 * 2) /* 4 bpp x 2 pages */
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002572#endif
2573
kuogee hsiehc9a2e6d2011-09-12 15:27:01 -07002574#ifdef CONFIG_FB_MSM_HDMI_MSM_PANEL
2575#define MSM_FB_EXT_BUF_SIZE (1920 * 1080 * 2 * 1) /* 2 bpp x 1 page */
2576#elif defined(CONFIG_FB_MSM_TVOUT)
2577#define MSM_FB_EXT_BUF_SIZE (720 * 576 * 2 * 2) /* 2 bpp x 2 pages */
2578#else
2579#define MSM_FB_EXT_BUFT_SIZE 0
2580#endif
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002581
2582#ifdef CONFIG_FB_MSM_OVERLAY_WRITEBACK
kuogee hsieha39040b2011-08-11 15:40:45 -07002583/* width x height x 3 bpp x 2 frame buffer */
2584#define MSM_FB_WRITEBACK_SIZE (1024 * 600 * 3 * 2)
kuogee hsiehc9a2e6d2011-09-12 15:27:01 -07002585#define MSM_FB_WRITEBACK_OFFSET \
2586 (MSM_FB_PRIM_BUF_SIZE + MSM_FB_EXT_BUF_SIZE)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002587#else
kuogee hsiehc9a2e6d2011-09-12 15:27:01 -07002588#define MSM_FB_WRITEBACK_SIZE 0
2589#define MSM_FB_WRITEBACK_OFFSET 0
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002590#endif
2591
Ravishangar Kalyanam75f37322011-10-14 12:15:40 -07002592#ifdef CONFIG_FB_MSM_HDMI_AS_PRIMARY
2593/* 4 bpp x 2 page HDMI case */
2594#define MSM_FB_SIZE roundup((1920 * 1088 * 4 * 2), 4096)
2595#else
kuogee hsiehc9a2e6d2011-09-12 15:27:01 -07002596/* Note: must be multiple of 4096 */
2597#define MSM_FB_SIZE roundup(MSM_FB_PRIM_BUF_SIZE + MSM_FB_EXT_BUF_SIZE + \
2598 MSM_FB_WRITEBACK_SIZE + \
2599 MSM_FB_DSUB_PMEM_ADDER, 4096)
Ravishangar Kalyanam75f37322011-10-14 12:15:40 -07002600#endif
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002601
Ravishangar Kalyanam75f37322011-10-14 12:15:40 -07002602#ifdef CONFIG_FB_MSM_HDMI_AS_PRIMARY
2603#define MSM_PMEM_SF_SIZE 0x8000000 /* 128 Mbytes */
2604#else
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002605#define MSM_PMEM_SF_SIZE 0x4000000 /* 64 Mbytes */
Ravishangar Kalyanam75f37322011-10-14 12:15:40 -07002606#endif
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002607
kuogee hsiehc9a2e6d2011-09-12 15:27:01 -07002608static int writeback_offset(void)
2609{
2610 return MSM_FB_WRITEBACK_OFFSET;
2611}
2612
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002613#define MSM_PMEM_KERNEL_EBI1_SIZE 0x600000
2614#define MSM_PMEM_ADSP_SIZE 0x2000000
Ben Romberger09e462d2011-08-09 15:24:37 -07002615#define MSM_PMEM_AUDIO_SIZE 0x28B000
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002616
2617#define MSM_SMI_BASE 0x38000000
2618#define MSM_SMI_SIZE 0x4000000
2619
2620#define KERNEL_SMI_BASE (MSM_SMI_BASE)
2621#define KERNEL_SMI_SIZE 0x300000
2622
2623#define USER_SMI_BASE (KERNEL_SMI_BASE + KERNEL_SMI_SIZE)
2624#define USER_SMI_SIZE (MSM_SMI_SIZE - KERNEL_SMI_SIZE)
2625#define MSM_PMEM_SMIPOOL_SIZE USER_SMI_SIZE
2626
2627static unsigned fb_size;
2628static int __init fb_size_setup(char *p)
2629{
2630 fb_size = memparse(p, NULL);
2631 return 0;
2632}
2633early_param("fb_size", fb_size_setup);
2634
2635static unsigned pmem_kernel_ebi1_size = MSM_PMEM_KERNEL_EBI1_SIZE;
2636static int __init pmem_kernel_ebi1_size_setup(char *p)
2637{
2638 pmem_kernel_ebi1_size = memparse(p, NULL);
2639 return 0;
2640}
2641early_param("pmem_kernel_ebi1_size", pmem_kernel_ebi1_size_setup);
2642
2643#ifdef CONFIG_ANDROID_PMEM
2644static unsigned pmem_sf_size = MSM_PMEM_SF_SIZE;
2645static int __init pmem_sf_size_setup(char *p)
2646{
2647 pmem_sf_size = memparse(p, NULL);
2648 return 0;
2649}
2650early_param("pmem_sf_size", pmem_sf_size_setup);
2651
2652static unsigned pmem_adsp_size = MSM_PMEM_ADSP_SIZE;
2653
2654static int __init pmem_adsp_size_setup(char *p)
2655{
2656 pmem_adsp_size = memparse(p, NULL);
2657 return 0;
2658}
2659early_param("pmem_adsp_size", pmem_adsp_size_setup);
2660
2661static unsigned pmem_audio_size = MSM_PMEM_AUDIO_SIZE;
2662
2663static int __init pmem_audio_size_setup(char *p)
2664{
2665 pmem_audio_size = memparse(p, NULL);
2666 return 0;
2667}
2668early_param("pmem_audio_size", pmem_audio_size_setup);
2669#endif
2670
2671static struct resource msm_fb_resources[] = {
2672 {
2673 .flags = IORESOURCE_DMA,
2674 }
2675};
2676
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002677static int msm_fb_detect_panel(const char *name)
2678{
2679 if (machine_is_msm8x60_fluid()) {
2680 uint32_t soc_platform_version = socinfo_get_platform_version();
2681 if (SOCINFO_VERSION_MAJOR(soc_platform_version) < 3) {
2682#ifdef CONFIG_FB_MSM_LCDC_SAMSUNG_OLED_PT
2683 if (!strncmp(name, LCDC_SAMSUNG_OLED_PANEL_NAME,
Ravishangar Kalyanam61a7bd12011-07-28 16:48:36 -07002684 strnlen(LCDC_SAMSUNG_OLED_PANEL_NAME,
2685 PANEL_NAME_MAX_LEN)))
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002686 return 0;
2687#endif
2688 } else { /*P3 and up use AUO panel */
2689#ifdef CONFIG_FB_MSM_LCDC_AUO_WVGA
2690 if (!strncmp(name, LCDC_AUO_PANEL_NAME,
Ravishangar Kalyanam61a7bd12011-07-28 16:48:36 -07002691 strnlen(LCDC_AUO_PANEL_NAME,
2692 PANEL_NAME_MAX_LEN)))
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002693 return 0;
2694#endif
2695 }
Zhang Chang Ken3a8b8512011-08-04 18:41:39 -04002696#ifdef CONFIG_FB_MSM_LCDC_NT35582_WVGA
2697 } else if machine_is_msm8x60_dragon() {
2698 if (!strncmp(name, LCDC_NT35582_PANEL_NAME,
Ravishangar Kalyanam61a7bd12011-07-28 16:48:36 -07002699 strnlen(LCDC_NT35582_PANEL_NAME,
2700 PANEL_NAME_MAX_LEN)))
Zhang Chang Ken3a8b8512011-08-04 18:41:39 -04002701 return 0;
2702#endif
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002703 } else {
2704 if (!strncmp(name, LCDC_SAMSUNG_WSVGA_PANEL_NAME,
Ravishangar Kalyanam61a7bd12011-07-28 16:48:36 -07002705 strnlen(LCDC_SAMSUNG_WSVGA_PANEL_NAME,
2706 PANEL_NAME_MAX_LEN)))
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002707 return 0;
Ravishangar Kalyanam61a7bd12011-07-28 16:48:36 -07002708
2709#if !defined(CONFIG_FB_MSM_LCDC_AUTO_DETECT) && \
2710 !defined(CONFIG_FB_MSM_MIPI_PANEL_AUTO_DETECT) && \
2711 !defined(CONFIG_FB_MSM_LCDC_MIPI_PANEL_AUTO_DETECT)
2712 if (!strncmp(name, MIPI_VIDEO_TOSHIBA_WVGA_PANEL_NAME,
2713 strnlen(MIPI_VIDEO_TOSHIBA_WVGA_PANEL_NAME,
2714 PANEL_NAME_MAX_LEN)))
2715 return 0;
2716
2717 if (!strncmp(name, MIPI_VIDEO_NOVATEK_QHD_PANEL_NAME,
2718 strnlen(MIPI_VIDEO_NOVATEK_QHD_PANEL_NAME,
2719 PANEL_NAME_MAX_LEN)))
2720 return 0;
2721
2722 if (!strncmp(name, MIPI_CMD_NOVATEK_QHD_PANEL_NAME,
2723 strnlen(MIPI_CMD_NOVATEK_QHD_PANEL_NAME,
2724 PANEL_NAME_MAX_LEN)))
2725 return 0;
2726#endif
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002727 }
Ravishangar Kalyanam61a7bd12011-07-28 16:48:36 -07002728
2729 if (!strncmp(name, HDMI_PANEL_NAME,
2730 strnlen(HDMI_PANEL_NAME,
2731 PANEL_NAME_MAX_LEN)))
2732 return 0;
2733
2734 if (!strncmp(name, TVOUT_PANEL_NAME,
2735 strnlen(TVOUT_PANEL_NAME,
2736 PANEL_NAME_MAX_LEN)))
2737 return 0;
2738
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002739 pr_warning("%s: not supported '%s'", __func__, name);
2740 return -ENODEV;
2741}
2742
2743static struct msm_fb_platform_data msm_fb_pdata = {
2744 .detect_client = msm_fb_detect_panel,
2745};
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002746
2747static struct platform_device msm_fb_device = {
2748 .name = "msm_fb",
2749 .id = 0,
2750 .num_resources = ARRAY_SIZE(msm_fb_resources),
2751 .resource = msm_fb_resources,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002752 .dev.platform_data = &msm_fb_pdata,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002753};
2754
2755#ifdef CONFIG_ANDROID_PMEM
2756static struct android_pmem_platform_data android_pmem_pdata = {
2757 .name = "pmem",
2758 .allocator_type = PMEM_ALLOCATORTYPE_ALLORNOTHING,
2759 .cached = 1,
2760 .memory_type = MEMTYPE_EBI1,
2761};
2762
2763static struct platform_device android_pmem_device = {
2764 .name = "android_pmem",
2765 .id = 0,
2766 .dev = {.platform_data = &android_pmem_pdata},
2767};
2768
2769static struct android_pmem_platform_data android_pmem_adsp_pdata = {
2770 .name = "pmem_adsp",
2771 .allocator_type = PMEM_ALLOCATORTYPE_BITMAP,
2772 .cached = 0,
2773 .memory_type = MEMTYPE_EBI1,
2774};
2775
2776static struct platform_device android_pmem_adsp_device = {
2777 .name = "android_pmem",
2778 .id = 2,
2779 .dev = { .platform_data = &android_pmem_adsp_pdata },
2780};
2781
2782static struct android_pmem_platform_data android_pmem_audio_pdata = {
2783 .name = "pmem_audio",
2784 .allocator_type = PMEM_ALLOCATORTYPE_BITMAP,
2785 .cached = 0,
2786 .memory_type = MEMTYPE_EBI1,
2787};
2788
2789static struct platform_device android_pmem_audio_device = {
2790 .name = "android_pmem",
2791 .id = 4,
2792 .dev = { .platform_data = &android_pmem_audio_pdata },
2793};
2794
Laura Abbott1e36a022011-06-22 17:08:13 -07002795#define PMEM_BUS_WIDTH(_bw) \
2796 { \
2797 .vectors = &(struct msm_bus_vectors){ \
2798 .src = MSM_BUS_MASTER_AMPSS_M0, \
2799 .dst = MSM_BUS_SLAVE_SMI, \
2800 .ib = (_bw), \
2801 .ab = 0, \
2802 }, \
2803 .num_paths = 1, \
2804 }
2805static struct msm_bus_paths pmem_smi_table[] = {
2806 [0] = PMEM_BUS_WIDTH(0), /* Off */
2807 [1] = PMEM_BUS_WIDTH(1), /* On */
2808};
2809
2810static struct msm_bus_scale_pdata smi_client_pdata = {
2811 .usecase = pmem_smi_table,
2812 .num_usecases = ARRAY_SIZE(pmem_smi_table),
2813 .name = "pmem_smi",
2814};
2815
Alex Bird199980e2011-10-21 11:29:27 -07002816void request_smi_region(void *data)
Laura Abbott1e36a022011-06-22 17:08:13 -07002817{
2818 int bus_id = (int) data;
2819
2820 msm_bus_scale_client_update_request(bus_id, 1);
2821}
2822
Alex Bird199980e2011-10-21 11:29:27 -07002823void release_smi_region(void *data)
Laura Abbott1e36a022011-06-22 17:08:13 -07002824{
2825 int bus_id = (int) data;
2826
2827 msm_bus_scale_client_update_request(bus_id, 0);
2828}
2829
Alex Bird199980e2011-10-21 11:29:27 -07002830void *setup_smi_region(void)
Laura Abbott1e36a022011-06-22 17:08:13 -07002831{
2832 return (void *)msm_bus_scale_register_client(&smi_client_pdata);
2833}
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002834static struct android_pmem_platform_data android_pmem_smipool_pdata = {
2835 .name = "pmem_smipool",
2836 .allocator_type = PMEM_ALLOCATORTYPE_BITMAP,
2837 .cached = 0,
2838 .memory_type = MEMTYPE_SMI,
Alex Bird199980e2011-10-21 11:29:27 -07002839 .request_region = request_smi_region,
2840 .release_region = release_smi_region,
2841 .setup_region = setup_smi_region,
Laura Abbott1e36a022011-06-22 17:08:13 -07002842 .map_on_demand = 1,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002843};
2844static struct platform_device android_pmem_smipool_device = {
2845 .name = "android_pmem",
2846 .id = 7,
2847 .dev = { .platform_data = &android_pmem_smipool_pdata },
2848};
2849
2850#endif
2851
2852#define GPIO_DONGLE_PWR_EN 258
2853static void setup_display_power(void);
2854static int lcdc_vga_enabled;
2855static int vga_enable_request(int enable)
2856{
2857 if (enable)
2858 lcdc_vga_enabled = 1;
2859 else
2860 lcdc_vga_enabled = 0;
2861 setup_display_power();
2862
2863 return 0;
2864}
2865
2866#define GPIO_BACKLIGHT_PWM0 0
2867#define GPIO_BACKLIGHT_PWM1 1
2868
2869static int pmic_backlight_gpio[2]
2870 = { GPIO_BACKLIGHT_PWM0, GPIO_BACKLIGHT_PWM1 };
2871static struct msm_panel_common_pdata lcdc_samsung_panel_data = {
2872 .gpio_num = pmic_backlight_gpio, /* two LPG CHANNELS for backlight */
2873 .vga_switch = vga_enable_request,
2874};
2875
2876static struct platform_device lcdc_samsung_panel_device = {
2877 .name = LCDC_SAMSUNG_WSVGA_PANEL_NAME,
2878 .id = 0,
2879 .dev = {
2880 .platform_data = &lcdc_samsung_panel_data,
2881 }
2882};
2883#if (!defined(CONFIG_SPI_QUP)) && \
2884 (defined(CONFIG_FB_MSM_LCDC_SAMSUNG_OLED_PT) || \
2885 defined(CONFIG_FB_MSM_LCDC_AUO_WVGA))
2886
2887static int lcdc_spi_gpio_array_num[] = {
2888 LCDC_SPI_GPIO_CLK,
2889 LCDC_SPI_GPIO_CS,
2890 LCDC_SPI_GPIO_MOSI,
2891};
2892
2893static uint32_t lcdc_spi_gpio_config_data[] = {
2894 GPIO_CFG(LCDC_SPI_GPIO_CLK, 0,
2895 GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA),
2896 GPIO_CFG(LCDC_SPI_GPIO_CS, 0,
2897 GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA),
2898 GPIO_CFG(LCDC_SPI_GPIO_MOSI, 0,
2899 GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA),
2900};
2901
2902static void lcdc_config_spi_gpios(int enable)
2903{
2904 int n;
2905 for (n = 0; n < ARRAY_SIZE(lcdc_spi_gpio_config_data); ++n)
2906 gpio_tlmm_config(lcdc_spi_gpio_config_data[n], 0);
2907}
2908#endif
2909
2910#ifdef CONFIG_FB_MSM_LCDC_SAMSUNG_OLED_PT
2911#ifdef CONFIG_SPI_QUP
2912static struct spi_board_info lcdc_samsung_spi_board_info[] __initdata = {
2913 {
2914 .modalias = LCDC_SAMSUNG_SPI_DEVICE_NAME,
2915 .mode = SPI_MODE_3,
2916 .bus_num = 1,
2917 .chip_select = 0,
2918 .max_speed_hz = 10800000,
2919 }
2920};
2921#endif /* CONFIG_SPI_QUP */
2922
2923static struct msm_panel_common_pdata lcdc_samsung_oled_panel_data = {
2924#ifndef CONFIG_SPI_QUP
2925 .panel_config_gpio = lcdc_config_spi_gpios,
2926 .gpio_num = lcdc_spi_gpio_array_num,
2927#endif
2928};
2929
2930static struct platform_device lcdc_samsung_oled_panel_device = {
2931 .name = LCDC_SAMSUNG_OLED_PANEL_NAME,
2932 .id = 0,
2933 .dev.platform_data = &lcdc_samsung_oled_panel_data,
2934};
2935#endif /*CONFIG_FB_MSM_LCDC_SAMSUNG_OLED_PT */
2936
2937#ifdef CONFIG_FB_MSM_LCDC_AUO_WVGA
2938#ifdef CONFIG_SPI_QUP
2939static struct spi_board_info lcdc_auo_spi_board_info[] __initdata = {
2940 {
2941 .modalias = LCDC_AUO_SPI_DEVICE_NAME,
2942 .mode = SPI_MODE_3,
2943 .bus_num = 1,
2944 .chip_select = 0,
2945 .max_speed_hz = 10800000,
2946 }
2947};
2948#endif
2949
2950static struct msm_panel_common_pdata lcdc_auo_wvga_panel_data = {
2951#ifndef CONFIG_SPI_QUP
2952 .panel_config_gpio = lcdc_config_spi_gpios,
2953 .gpio_num = lcdc_spi_gpio_array_num,
2954#endif
2955};
2956
2957static struct platform_device lcdc_auo_wvga_panel_device = {
2958 .name = LCDC_AUO_PANEL_NAME,
2959 .id = 0,
2960 .dev.platform_data = &lcdc_auo_wvga_panel_data,
2961};
2962#endif /*CONFIG_FB_MSM_LCDC_AUO_WVGA*/
2963
Zhang Chang Ken3a8b8512011-08-04 18:41:39 -04002964#ifdef CONFIG_FB_MSM_LCDC_NT35582_WVGA
2965
2966#define GPIO_NT35582_RESET 94
2967#define GPIO_NT35582_BL_EN_HW_PIN 24
2968#define GPIO_NT35582_BL_EN \
2969 PM8058_GPIO_PM_TO_SYS(GPIO_NT35582_BL_EN_HW_PIN - 1)
2970
2971static int lcdc_nt35582_pmic_gpio[] = {GPIO_NT35582_BL_EN };
2972
2973static struct msm_panel_common_pdata lcdc_nt35582_panel_data = {
2974 .gpio_num = lcdc_nt35582_pmic_gpio,
2975};
2976
2977static struct platform_device lcdc_nt35582_panel_device = {
2978 .name = LCDC_NT35582_PANEL_NAME,
2979 .id = 0,
2980 .dev = {
2981 .platform_data = &lcdc_nt35582_panel_data,
2982 }
2983};
2984
2985static struct spi_board_info lcdc_nt35582_spi_board_info[] __initdata = {
2986 {
2987 .modalias = "lcdc_nt35582_spi",
2988 .mode = SPI_MODE_0,
2989 .bus_num = 0,
2990 .chip_select = 0,
2991 .max_speed_hz = 1100000,
2992 }
2993};
2994#endif
2995
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002996#ifdef CONFIG_FB_MSM_HDMI_MSM_PANEL
2997static struct resource hdmi_msm_resources[] = {
2998 {
2999 .name = "hdmi_msm_qfprom_addr",
3000 .start = 0x00700000,
3001 .end = 0x007060FF,
3002 .flags = IORESOURCE_MEM,
3003 },
3004 {
3005 .name = "hdmi_msm_hdmi_addr",
3006 .start = 0x04A00000,
3007 .end = 0x04A00FFF,
3008 .flags = IORESOURCE_MEM,
3009 },
3010 {
3011 .name = "hdmi_msm_irq",
3012 .start = HDMI_IRQ,
3013 .end = HDMI_IRQ,
3014 .flags = IORESOURCE_IRQ,
3015 },
3016};
3017
3018static int hdmi_enable_5v(int on);
3019static int hdmi_core_power(int on, int show);
3020static int hdmi_cec_power(int on);
3021
3022static struct msm_hdmi_platform_data hdmi_msm_data = {
3023 .irq = HDMI_IRQ,
3024 .enable_5v = hdmi_enable_5v,
3025 .core_power = hdmi_core_power,
3026 .cec_power = hdmi_cec_power,
3027};
3028
3029static struct platform_device hdmi_msm_device = {
3030 .name = "hdmi_msm",
3031 .id = 0,
3032 .num_resources = ARRAY_SIZE(hdmi_msm_resources),
3033 .resource = hdmi_msm_resources,
3034 .dev.platform_data = &hdmi_msm_data,
3035};
3036#endif /* CONFIG_FB_MSM_HDMI_MSM_PANEL */
3037
3038#ifdef CONFIG_FB_MSM_MIPI_DSI
3039static struct platform_device mipi_dsi_toshiba_panel_device = {
3040 .name = "mipi_toshiba",
3041 .id = 0,
3042};
3043
3044#define FPGA_3D_GPIO_CONFIG_ADDR 0x1D00017A
3045
Nagamalleswararao Ganjieac5dfa2011-07-23 17:31:16 -07003046static struct mipi_dsi_panel_platform_data novatek_pdata = {
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003047 .fpga_3d_config_addr = FPGA_3D_GPIO_CONFIG_ADDR,
Chandan Uddaraju83eac3c2011-09-11 18:32:23 -07003048 .fpga_ctrl_mode = FPGA_EBI2_INTF,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003049};
3050
3051static struct platform_device mipi_dsi_novatek_panel_device = {
3052 .name = "mipi_novatek",
3053 .id = 0,
3054 .dev = {
3055 .platform_data = &novatek_pdata,
3056 }
3057};
3058#endif
3059
3060static void __init msm8x60_allocate_memory_regions(void)
3061{
3062 void *addr;
3063 unsigned long size;
3064
3065 size = MSM_FB_SIZE;
3066 addr = alloc_bootmem_align(size, 0x1000);
3067 msm_fb_resources[0].start = __pa(addr);
3068 msm_fb_resources[0].end = msm_fb_resources[0].start + size - 1;
3069 pr_info("allocating %lu bytes at %p (%lx physical) for fb\n",
3070 size, addr, __pa(addr));
3071
3072}
3073
3074#if defined(CONFIG_TOUCHSCREEN_CYTTSP_I2C) || \
3075 defined(CONFIG_TOUCHSCREEN_CYTTSP_I2C_MODULE)
3076/*virtual key support */
3077static ssize_t tma300_vkeys_show(struct kobject *kobj,
3078 struct kobj_attribute *attr, char *buf)
3079{
3080 return sprintf(buf,
3081 __stringify(EV_KEY) ":" __stringify(KEY_BACK) ":60:900:90:120"
3082 ":" __stringify(EV_KEY) ":" __stringify(KEY_MENU) ":180:900:90:120"
3083 ":" __stringify(EV_KEY) ":" __stringify(KEY_HOME) ":300:900:90:120"
3084 ":" __stringify(EV_KEY) ":" __stringify(KEY_SEARCH) ":420:900:90:120"
3085 "\n");
3086}
3087
3088static struct kobj_attribute tma300_vkeys_attr = {
3089 .attr = {
3090 .mode = S_IRUGO,
3091 },
3092 .show = &tma300_vkeys_show,
3093};
3094
3095static struct attribute *tma300_properties_attrs[] = {
3096 &tma300_vkeys_attr.attr,
3097 NULL
3098};
3099
3100static struct attribute_group tma300_properties_attr_group = {
3101 .attrs = tma300_properties_attrs,
3102};
3103
3104static struct kobject *properties_kobj;
3105
3106
3107
3108#define CYTTSP_TS_GPIO_IRQ 61
3109static int cyttsp_platform_init(struct i2c_client *client)
3110{
3111 int rc = -EINVAL;
3112 struct regulator *pm8058_l5 = NULL, *pm8058_s3;
3113
3114 if (machine_is_msm8x60_fluid()) {
3115 pm8058_l5 = regulator_get(NULL, "8058_l5");
3116 if (IS_ERR(pm8058_l5)) {
3117 pr_err("%s: regulator get of 8058_l5 failed (%ld)\n",
3118 __func__, PTR_ERR(pm8058_l5));
3119 rc = PTR_ERR(pm8058_l5);
3120 return rc;
3121 }
3122 rc = regulator_set_voltage(pm8058_l5, 2850000, 2850000);
3123 if (rc) {
3124 pr_err("%s: regulator_set_voltage of 8058_l5 failed(%d)\n",
3125 __func__, rc);
3126 goto reg_l5_put;
3127 }
3128
3129 rc = regulator_enable(pm8058_l5);
3130 if (rc) {
3131 pr_err("%s: regulator_enable of 8058_l5 failed(%d)\n",
3132 __func__, rc);
3133 goto reg_l5_put;
3134 }
3135 }
3136 /* vote for s3 to enable i2c communication lines */
3137 pm8058_s3 = regulator_get(NULL, "8058_s3");
3138 if (IS_ERR(pm8058_s3)) {
3139 pr_err("%s: regulator get of 8058_s3 failed (%ld)\n",
3140 __func__, PTR_ERR(pm8058_s3));
3141 rc = PTR_ERR(pm8058_s3);
3142 goto reg_l5_disable;
3143 }
3144
3145 rc = regulator_set_voltage(pm8058_s3, 1800000, 1800000);
3146 if (rc) {
3147 pr_err("%s: regulator_set_voltage() = %d\n",
3148 __func__, rc);
3149 goto reg_s3_put;
3150 }
3151
3152 rc = regulator_enable(pm8058_s3);
3153 if (rc) {
3154 pr_err("%s: regulator_enable of 8058_l5 failed(%d)\n",
3155 __func__, rc);
3156 goto reg_s3_put;
3157 }
3158
3159 /* wait for vregs to stabilize */
3160 usleep_range(10000, 10000);
3161
3162 /* check this device active by reading first byte/register */
3163 rc = i2c_smbus_read_byte_data(client, 0x01);
3164 if (rc < 0) {
3165 pr_err("%s: i2c sanity check failed\n", __func__);
3166 goto reg_s3_disable;
3167 }
3168
3169 /* virtual keys */
3170 if (machine_is_msm8x60_fluid()) {
3171 tma300_vkeys_attr.attr.name = "virtualkeys.cyttsp-i2c";
3172 properties_kobj = kobject_create_and_add("board_properties",
3173 NULL);
3174 if (properties_kobj)
3175 rc = sysfs_create_group(properties_kobj,
3176 &tma300_properties_attr_group);
3177 if (!properties_kobj || rc)
3178 pr_err("%s: failed to create board_properties\n",
3179 __func__);
3180 }
3181 return CY_OK;
3182
3183reg_s3_disable:
3184 regulator_disable(pm8058_s3);
3185reg_s3_put:
3186 regulator_put(pm8058_s3);
3187reg_l5_disable:
3188 if (machine_is_msm8x60_fluid())
3189 regulator_disable(pm8058_l5);
3190reg_l5_put:
3191 if (machine_is_msm8x60_fluid())
3192 regulator_put(pm8058_l5);
3193 return rc;
3194}
3195
3196static int cyttsp_platform_resume(struct i2c_client *client)
3197{
3198 /* add any special code to strobe a wakeup pin or chip reset */
3199 msleep(10);
3200
3201 return CY_OK;
3202}
3203
3204static struct cyttsp_platform_data cyttsp_fluid_pdata = {
3205 .flags = 0x04,
3206 .gen = CY_GEN3, /* or */
3207 .use_st = CY_USE_ST,
3208 .use_mt = CY_USE_MT,
3209 .use_hndshk = CY_SEND_HNDSHK,
3210 .use_trk_id = CY_USE_TRACKING_ID,
Anirudh Ghayal15187772011-06-22 17:39:41 +05303211 .use_sleep = CY_USE_DEEP_SLEEP_SEL | CY_USE_LOW_POWER_SEL,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003212 .use_gestures = CY_USE_GESTURES,
3213 /* activate up to 4 groups
3214 * and set active distance
3215 */
3216 .gest_set = CY_GEST_GRP1 | CY_GEST_GRP2 |
3217 CY_GEST_GRP3 | CY_GEST_GRP4 |
3218 CY_ACT_DIST,
3219 /* change act_intrvl to customize the Active power state
3220 * scanning/processing refresh interval for Operating mode
3221 */
3222 .act_intrvl = CY_ACT_INTRVL_DFLT,
3223 /* change tch_tmout to customize the touch timeout for the
3224 * Active power state for Operating mode
3225 */
3226 .tch_tmout = CY_TCH_TMOUT_DFLT,
3227 /* change lp_intrvl to customize the Low Power power state
3228 * scanning/processing refresh interval for Operating mode
3229 */
3230 .lp_intrvl = CY_LP_INTRVL_DFLT,
3231 .sleep_gpio = -1,
3232 .resout_gpio = -1,
3233 .irq_gpio = CYTTSP_TS_GPIO_IRQ,
3234 .resume = cyttsp_platform_resume,
3235 .init = cyttsp_platform_init,
3236};
3237
3238static struct cyttsp_platform_data cyttsp_tmg240_pdata = {
3239 .panel_maxx = 1083,
3240 .panel_maxy = 659,
3241 .disp_minx = 30,
3242 .disp_maxx = 1053,
3243 .disp_miny = 30,
3244 .disp_maxy = 629,
3245 .correct_fw_ver = 8,
3246 .fw_fname = "cyttsp_8660_ffa.hex",
3247 .flags = 0x00,
3248 .gen = CY_GEN2, /* or */
3249 .use_st = CY_USE_ST,
3250 .use_mt = CY_USE_MT,
3251 .use_hndshk = CY_SEND_HNDSHK,
3252 .use_trk_id = CY_USE_TRACKING_ID,
Anirudh Ghayal15187772011-06-22 17:39:41 +05303253 .use_sleep = CY_USE_DEEP_SLEEP_SEL | CY_USE_LOW_POWER_SEL,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003254 .use_gestures = CY_USE_GESTURES,
3255 /* activate up to 4 groups
3256 * and set active distance
3257 */
3258 .gest_set = CY_GEST_GRP1 | CY_GEST_GRP2 |
3259 CY_GEST_GRP3 | CY_GEST_GRP4 |
3260 CY_ACT_DIST,
3261 /* change act_intrvl to customize the Active power state
3262 * scanning/processing refresh interval for Operating mode
3263 */
3264 .act_intrvl = CY_ACT_INTRVL_DFLT,
3265 /* change tch_tmout to customize the touch timeout for the
3266 * Active power state for Operating mode
3267 */
3268 .tch_tmout = CY_TCH_TMOUT_DFLT,
3269 /* change lp_intrvl to customize the Low Power power state
3270 * scanning/processing refresh interval for Operating mode
3271 */
3272 .lp_intrvl = CY_LP_INTRVL_DFLT,
3273 .sleep_gpio = -1,
3274 .resout_gpio = -1,
3275 .irq_gpio = CYTTSP_TS_GPIO_IRQ,
3276 .resume = cyttsp_platform_resume,
3277 .init = cyttsp_platform_init,
Mohan Pallaka1ea7d8a2011-08-18 15:06:00 +05303278 .disable_ghost_det = true,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003279};
3280static void cyttsp_set_params(void)
3281{
3282 if (SOCINFO_VERSION_MAJOR(socinfo_get_platform_version()) < 3) {
3283 cyttsp_fluid_pdata.fw_fname = "cyttsp_8660_fluid_p2.hex";
3284 cyttsp_fluid_pdata.panel_maxx = 539;
3285 cyttsp_fluid_pdata.panel_maxy = 994;
3286 cyttsp_fluid_pdata.disp_minx = 30;
3287 cyttsp_fluid_pdata.disp_maxx = 509;
3288 cyttsp_fluid_pdata.disp_miny = 60;
3289 cyttsp_fluid_pdata.disp_maxy = 859;
3290 cyttsp_fluid_pdata.correct_fw_ver = 4;
3291 } else {
3292 cyttsp_fluid_pdata.fw_fname = "cyttsp_8660_fluid_p3.hex";
3293 cyttsp_fluid_pdata.panel_maxx = 550;
3294 cyttsp_fluid_pdata.panel_maxy = 1013;
3295 cyttsp_fluid_pdata.disp_minx = 35;
3296 cyttsp_fluid_pdata.disp_maxx = 515;
3297 cyttsp_fluid_pdata.disp_miny = 69;
3298 cyttsp_fluid_pdata.disp_maxy = 869;
3299 cyttsp_fluid_pdata.correct_fw_ver = 5;
3300 }
3301
3302}
3303
3304static struct i2c_board_info cyttsp_fluid_info[] __initdata = {
3305 {
3306 I2C_BOARD_INFO(CY_I2C_NAME, 0x24),
3307 .platform_data = &cyttsp_fluid_pdata,
3308#ifndef CY_USE_TIMER
3309 .irq = MSM_GPIO_TO_INT(CYTTSP_TS_GPIO_IRQ),
3310#endif /* CY_USE_TIMER */
3311 },
3312};
3313
3314static struct i2c_board_info cyttsp_ffa_info[] __initdata = {
3315 {
3316 I2C_BOARD_INFO(CY_I2C_NAME, 0x3b),
3317 .platform_data = &cyttsp_tmg240_pdata,
3318#ifndef CY_USE_TIMER
3319 .irq = MSM_GPIO_TO_INT(CYTTSP_TS_GPIO_IRQ),
3320#endif /* CY_USE_TIMER */
3321 },
3322};
3323#endif
3324
3325static struct regulator *vreg_tmg200;
3326
3327#define TS_PEN_IRQ_GPIO 61
3328static int tmg200_power(int vreg_on)
3329{
3330 int rc = -EINVAL;
3331
3332 if (!vreg_tmg200) {
3333 printk(KERN_ERR "%s: regulator 8058_s3 not found (%d)\n",
3334 __func__, rc);
3335 return rc;
3336 }
3337
3338 rc = vreg_on ? regulator_enable(vreg_tmg200) :
3339 regulator_disable(vreg_tmg200);
3340 if (rc < 0)
3341 printk(KERN_ERR "%s: vreg 8058_s3 %s failed (%d)\n",
3342 __func__, vreg_on ? "enable" : "disable", rc);
3343
3344 /* wait for vregs to stabilize */
Amy Maloche12b5d4e2011-08-03 15:42:28 -07003345 msleep(20);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003346
3347 return rc;
3348}
3349
3350static int tmg200_dev_setup(bool enable)
3351{
3352 int rc;
3353
3354 if (enable) {
3355 vreg_tmg200 = regulator_get(NULL, "8058_s3");
3356 if (IS_ERR(vreg_tmg200)) {
3357 pr_err("%s: regulator get of 8058_s3 failed (%ld)\n",
3358 __func__, PTR_ERR(vreg_tmg200));
3359 rc = PTR_ERR(vreg_tmg200);
3360 return rc;
3361 }
3362
3363 rc = regulator_set_voltage(vreg_tmg200, 1800000, 1800000);
3364 if (rc) {
3365 pr_err("%s: regulator_set_voltage() = %d\n",
3366 __func__, rc);
3367 goto reg_put;
3368 }
3369 } else {
3370 /* put voltage sources */
3371 regulator_put(vreg_tmg200);
3372 }
3373 return 0;
3374reg_put:
3375 regulator_put(vreg_tmg200);
3376 return rc;
3377}
3378
3379static struct cy8c_ts_platform_data cy8ctmg200_pdata = {
3380 .ts_name = "msm_tmg200_ts",
3381 .dis_min_x = 0,
3382 .dis_max_x = 1023,
3383 .dis_min_y = 0,
3384 .dis_max_y = 599,
3385 .min_tid = 0,
3386 .max_tid = 255,
3387 .min_touch = 0,
3388 .max_touch = 255,
3389 .min_width = 0,
3390 .max_width = 255,
3391 .power_on = tmg200_power,
3392 .dev_setup = tmg200_dev_setup,
3393 .nfingers = 2,
3394 .irq_gpio = TS_PEN_IRQ_GPIO,
3395 .resout_gpio = GPIO_CAP_TS_RESOUT_N,
3396};
3397
3398static struct i2c_board_info cy8ctmg200_board_info[] = {
3399 {
3400 I2C_BOARD_INFO("cy8ctmg200", 0x2),
3401 .platform_data = &cy8ctmg200_pdata,
3402 }
3403};
3404
Zhang Chang Ken211df572011-07-05 19:16:39 -04003405static struct regulator *vreg_tma340;
3406
3407static int tma340_power(int vreg_on)
3408{
3409 int rc = -EINVAL;
3410
3411 if (!vreg_tma340) {
3412 pr_err("%s: regulator 8901_l2 not found (%d)\n",
3413 __func__, rc);
3414 return rc;
3415 }
3416
3417 rc = vreg_on ? regulator_enable(vreg_tma340) :
3418 regulator_disable(vreg_tma340);
3419 if (rc < 0)
3420 pr_err("%s: vreg 8901_l2 %s failed (%d)\n",
3421 __func__, vreg_on ? "enable" : "disable", rc);
3422
3423 /* wait for vregs to stabilize */
Amy Malocheb5c67e8d2011-08-18 16:39:35 -07003424 msleep(100);
Zhang Chang Ken211df572011-07-05 19:16:39 -04003425
3426 return rc;
3427}
3428
3429static struct kobject *tma340_prop_kobj;
3430
3431static int tma340_dragon_dev_setup(bool enable)
3432{
3433 int rc;
3434
3435 if (enable) {
3436 vreg_tma340 = regulator_get(NULL, "8901_l2");
3437 if (IS_ERR(vreg_tma340)) {
3438 pr_err("%s: regulator get of 8901_l2 failed (%ld)\n",
3439 __func__, PTR_ERR(vreg_tma340));
3440 rc = PTR_ERR(vreg_tma340);
3441 return rc;
3442 }
3443
3444 rc = regulator_set_voltage(vreg_tma340, 3300000, 3300000);
3445 if (rc) {
3446 pr_err("%s: regulator_set_voltage() = %d\n",
3447 __func__, rc);
3448 goto reg_put;
3449 }
3450 tma300_vkeys_attr.attr.name = "virtualkeys.cy8ctma340";
3451 tma340_prop_kobj = kobject_create_and_add("board_properties",
3452 NULL);
3453 if (tma340_prop_kobj) {
3454 rc = sysfs_create_group(tma340_prop_kobj,
3455 &tma300_properties_attr_group);
3456 if (rc) {
3457 kobject_put(tma340_prop_kobj);
3458 pr_err("%s: failed to create board_properties\n",
3459 __func__);
3460 goto reg_put;
3461 }
3462 }
3463
3464 } else {
3465 /* put voltage sources */
3466 regulator_put(vreg_tma340);
3467 /* destroy virtual keys */
3468 if (tma340_prop_kobj) {
3469 sysfs_remove_group(tma340_prop_kobj,
3470 &tma300_properties_attr_group);
3471 kobject_put(tma340_prop_kobj);
3472 }
3473 }
3474 return 0;
3475reg_put:
3476 regulator_put(vreg_tma340);
3477 return rc;
3478}
3479
3480
3481static struct cy8c_ts_platform_data cy8ctma340_dragon_pdata = {
3482 .ts_name = "cy8ctma340",
3483 .dis_min_x = 0,
3484 .dis_max_x = 479,
3485 .dis_min_y = 0,
3486 .dis_max_y = 799,
3487 .min_tid = 0,
3488 .max_tid = 255,
3489 .min_touch = 0,
3490 .max_touch = 255,
3491 .min_width = 0,
3492 .max_width = 255,
3493 .power_on = tma340_power,
3494 .dev_setup = tma340_dragon_dev_setup,
3495 .nfingers = 2,
3496 .irq_gpio = TS_PEN_IRQ_GPIO,
3497 .resout_gpio = -1,
3498};
3499
3500static struct i2c_board_info cy8ctma340_dragon_board_info[] = {
3501 {
3502 I2C_BOARD_INFO("cy8ctma340", 0x24),
3503 .platform_data = &cy8ctma340_dragon_pdata,
3504 }
3505};
3506
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003507#ifdef CONFIG_SERIAL_MSM_HS
3508static int configure_uart_gpios(int on)
3509{
3510 int ret = 0, i;
3511 int uart_gpios[] = {53, 54, 55, 56};
3512 for (i = 0; i < ARRAY_SIZE(uart_gpios); i++) {
3513 if (on) {
3514 ret = msm_gpiomux_get(uart_gpios[i]);
3515 if (unlikely(ret))
3516 break;
3517 } else {
3518 ret = msm_gpiomux_put(uart_gpios[i]);
3519 if (unlikely(ret))
3520 return ret;
3521 }
3522 }
3523 if (ret)
3524 for (; i >= 0; i--)
3525 msm_gpiomux_put(uart_gpios[i]);
3526 return ret;
3527}
3528static struct msm_serial_hs_platform_data msm_uart_dm1_pdata = {
3529 .inject_rx_on_wakeup = 1,
3530 .rx_to_inject = 0xFD,
3531 .gpio_config = configure_uart_gpios,
3532};
3533#endif
3534
3535
3536#if defined(CONFIG_GPIO_SX150X) || defined(CONFIG_GPIO_SX150X_MODULE)
3537
3538static struct gpio_led gpio_exp_leds_config[] = {
3539 {
3540 .name = "left_led1:green",
3541 .gpio = GPIO_LEFT_LED_1,
3542 .active_low = 1,
3543 .retain_state_suspended = 0,
3544 .default_state = LEDS_GPIO_DEFSTATE_OFF,
3545 },
3546 {
3547 .name = "left_led2:red",
3548 .gpio = GPIO_LEFT_LED_2,
3549 .active_low = 1,
3550 .retain_state_suspended = 0,
3551 .default_state = LEDS_GPIO_DEFSTATE_OFF,
3552 },
3553 {
3554 .name = "left_led3:green",
3555 .gpio = GPIO_LEFT_LED_3,
3556 .active_low = 1,
3557 .retain_state_suspended = 0,
3558 .default_state = LEDS_GPIO_DEFSTATE_OFF,
3559 },
3560 {
3561 .name = "wlan_led:orange",
3562 .gpio = GPIO_LEFT_LED_WLAN,
3563 .active_low = 1,
3564 .retain_state_suspended = 0,
3565 .default_state = LEDS_GPIO_DEFSTATE_OFF,
3566 },
3567 {
3568 .name = "left_led5:green",
3569 .gpio = GPIO_LEFT_LED_5,
3570 .active_low = 1,
3571 .retain_state_suspended = 0,
3572 .default_state = LEDS_GPIO_DEFSTATE_OFF,
3573 },
3574 {
3575 .name = "right_led1:green",
3576 .gpio = GPIO_RIGHT_LED_1,
3577 .active_low = 1,
3578 .retain_state_suspended = 0,
3579 .default_state = LEDS_GPIO_DEFSTATE_OFF,
3580 },
3581 {
3582 .name = "right_led2:red",
3583 .gpio = GPIO_RIGHT_LED_2,
3584 .active_low = 1,
3585 .retain_state_suspended = 0,
3586 .default_state = LEDS_GPIO_DEFSTATE_OFF,
3587 },
3588 {
3589 .name = "right_led3:green",
3590 .gpio = GPIO_RIGHT_LED_3,
3591 .active_low = 1,
3592 .retain_state_suspended = 0,
3593 .default_state = LEDS_GPIO_DEFSTATE_OFF,
3594 },
3595 {
3596 .name = "bt_led:blue",
3597 .gpio = GPIO_RIGHT_LED_BT,
3598 .active_low = 1,
3599 .retain_state_suspended = 0,
3600 .default_state = LEDS_GPIO_DEFSTATE_OFF,
3601 },
3602 {
3603 .name = "right_led5:green",
3604 .gpio = GPIO_RIGHT_LED_5,
3605 .active_low = 1,
3606 .retain_state_suspended = 0,
3607 .default_state = LEDS_GPIO_DEFSTATE_OFF,
3608 },
3609};
3610
3611static struct gpio_led_platform_data gpio_leds_pdata = {
3612 .num_leds = ARRAY_SIZE(gpio_exp_leds_config),
3613 .leds = gpio_exp_leds_config,
3614};
3615
3616static struct platform_device gpio_leds = {
3617 .name = "leds-gpio",
3618 .id = -1,
3619 .dev = {
3620 .platform_data = &gpio_leds_pdata,
3621 },
3622};
3623
3624static struct gpio_led fluid_gpio_leds[] = {
3625 {
3626 .name = "dual_led:green",
3627 .gpio = GPIO_LED1_GREEN_N,
3628 .default_state = LEDS_GPIO_DEFSTATE_OFF,
3629 .active_low = 1,
3630 .retain_state_suspended = 0,
3631 },
3632 {
3633 .name = "dual_led:red",
3634 .gpio = GPIO_LED2_RED_N,
3635 .default_state = LEDS_GPIO_DEFSTATE_OFF,
3636 .active_low = 1,
3637 .retain_state_suspended = 0,
3638 },
3639};
3640
3641static struct gpio_led_platform_data gpio_led_pdata = {
3642 .leds = fluid_gpio_leds,
3643 .num_leds = ARRAY_SIZE(fluid_gpio_leds),
3644};
3645
3646static struct platform_device fluid_leds_gpio = {
3647 .name = "leds-gpio",
3648 .id = -1,
3649 .dev = {
3650 .platform_data = &gpio_led_pdata,
3651 },
3652};
3653
3654#endif
3655
3656#if defined(CONFIG_MSM_RPM_LOG) || defined(CONFIG_MSM_RPM_LOG_MODULE)
3657
3658static struct msm_rpm_log_platform_data msm_rpm_log_pdata = {
3659 .phys_addr_base = 0x00106000,
3660 .reg_offsets = {
3661 [MSM_RPM_LOG_PAGE_INDICES] = 0x00000C80,
3662 [MSM_RPM_LOG_PAGE_BUFFER] = 0x00000CA0,
3663 },
3664 .phys_size = SZ_8K,
3665 .log_len = 4096, /* log's buffer length in bytes */
3666 .log_len_mask = (4096 >> 2) - 1, /* length mask in units of u32 */
3667};
3668
3669static struct platform_device msm_rpm_log_device = {
3670 .name = "msm_rpm_log",
3671 .id = -1,
3672 .dev = {
3673 .platform_data = &msm_rpm_log_pdata,
3674 },
3675};
3676#endif
3677
3678#ifdef CONFIG_BATTERY_MSM8X60
3679static struct msm_charger_platform_data msm_charger_data = {
3680 .safety_time = 180,
3681 .update_time = 1,
3682 .max_voltage = 4200,
3683 .min_voltage = 3200,
3684};
3685
3686static struct platform_device msm_charger_device = {
3687 .name = "msm-charger",
3688 .id = -1,
3689 .dev = {
3690 .platform_data = &msm_charger_data,
3691 }
3692};
3693#endif
3694
3695/*
3696 * Consumer specific regulator names:
3697 * regulator name consumer dev_name
3698 */
3699static struct regulator_consumer_supply vreg_consumers_PM8058_L0[] = {
3700 REGULATOR_SUPPLY("8058_l0", NULL),
3701};
3702static struct regulator_consumer_supply vreg_consumers_PM8058_L1[] = {
3703 REGULATOR_SUPPLY("8058_l1", NULL),
3704};
3705static struct regulator_consumer_supply vreg_consumers_PM8058_L2[] = {
3706 REGULATOR_SUPPLY("8058_l2", NULL),
3707};
3708static struct regulator_consumer_supply vreg_consumers_PM8058_L3[] = {
3709 REGULATOR_SUPPLY("8058_l3", NULL),
3710};
3711static struct regulator_consumer_supply vreg_consumers_PM8058_L4[] = {
3712 REGULATOR_SUPPLY("8058_l4", NULL),
3713};
3714static struct regulator_consumer_supply vreg_consumers_PM8058_L5[] = {
3715 REGULATOR_SUPPLY("8058_l5", NULL),
3716};
3717static struct regulator_consumer_supply vreg_consumers_PM8058_L6[] = {
3718 REGULATOR_SUPPLY("8058_l6", NULL),
3719};
3720static struct regulator_consumer_supply vreg_consumers_PM8058_L7[] = {
3721 REGULATOR_SUPPLY("8058_l7", NULL),
3722};
3723static struct regulator_consumer_supply vreg_consumers_PM8058_L8[] = {
3724 REGULATOR_SUPPLY("8058_l8", NULL),
3725};
3726static struct regulator_consumer_supply vreg_consumers_PM8058_L9[] = {
3727 REGULATOR_SUPPLY("8058_l9", NULL),
3728};
3729static struct regulator_consumer_supply vreg_consumers_PM8058_L10[] = {
3730 REGULATOR_SUPPLY("8058_l10", NULL),
3731};
3732static struct regulator_consumer_supply vreg_consumers_PM8058_L11[] = {
3733 REGULATOR_SUPPLY("8058_l11", NULL),
3734};
3735static struct regulator_consumer_supply vreg_consumers_PM8058_L12[] = {
3736 REGULATOR_SUPPLY("8058_l12", NULL),
3737};
3738static struct regulator_consumer_supply vreg_consumers_PM8058_L13[] = {
3739 REGULATOR_SUPPLY("8058_l13", NULL),
3740};
3741static struct regulator_consumer_supply vreg_consumers_PM8058_L14[] = {
3742 REGULATOR_SUPPLY("8058_l14", NULL),
3743};
3744static struct regulator_consumer_supply vreg_consumers_PM8058_L15[] = {
3745 REGULATOR_SUPPLY("8058_l15", NULL),
3746};
3747static struct regulator_consumer_supply vreg_consumers_PM8058_L16[] = {
3748 REGULATOR_SUPPLY("8058_l16", NULL),
3749};
3750static struct regulator_consumer_supply vreg_consumers_PM8058_L17[] = {
3751 REGULATOR_SUPPLY("8058_l17", NULL),
3752};
3753static struct regulator_consumer_supply vreg_consumers_PM8058_L18[] = {
3754 REGULATOR_SUPPLY("8058_l18", NULL),
3755};
3756static struct regulator_consumer_supply vreg_consumers_PM8058_L19[] = {
3757 REGULATOR_SUPPLY("8058_l19", NULL),
3758};
3759static struct regulator_consumer_supply vreg_consumers_PM8058_L20[] = {
3760 REGULATOR_SUPPLY("8058_l20", NULL),
3761};
3762static struct regulator_consumer_supply vreg_consumers_PM8058_L21[] = {
3763 REGULATOR_SUPPLY("8058_l21", NULL),
3764};
3765static struct regulator_consumer_supply vreg_consumers_PM8058_L22[] = {
3766 REGULATOR_SUPPLY("8058_l22", NULL),
3767};
3768static struct regulator_consumer_supply vreg_consumers_PM8058_L23[] = {
3769 REGULATOR_SUPPLY("8058_l23", NULL),
3770};
3771static struct regulator_consumer_supply vreg_consumers_PM8058_L24[] = {
3772 REGULATOR_SUPPLY("8058_l24", NULL),
3773};
3774static struct regulator_consumer_supply vreg_consumers_PM8058_L25[] = {
3775 REGULATOR_SUPPLY("8058_l25", NULL),
3776};
3777static struct regulator_consumer_supply vreg_consumers_PM8058_S0[] = {
3778 REGULATOR_SUPPLY("8058_s0", NULL),
3779};
3780static struct regulator_consumer_supply vreg_consumers_PM8058_S1[] = {
3781 REGULATOR_SUPPLY("8058_s1", NULL),
3782};
3783static struct regulator_consumer_supply vreg_consumers_PM8058_S2[] = {
3784 REGULATOR_SUPPLY("8058_s2", NULL),
3785};
3786static struct regulator_consumer_supply vreg_consumers_PM8058_S3[] = {
3787 REGULATOR_SUPPLY("8058_s3", NULL),
3788};
3789static struct regulator_consumer_supply vreg_consumers_PM8058_S4[] = {
3790 REGULATOR_SUPPLY("8058_s4", NULL),
3791};
3792static struct regulator_consumer_supply vreg_consumers_PM8058_LVS0[] = {
3793 REGULATOR_SUPPLY("8058_lvs0", NULL),
3794};
3795static struct regulator_consumer_supply vreg_consumers_PM8058_LVS1[] = {
3796 REGULATOR_SUPPLY("8058_lvs1", NULL),
3797};
3798static struct regulator_consumer_supply vreg_consumers_PM8058_NCP[] = {
3799 REGULATOR_SUPPLY("8058_ncp", NULL),
3800};
3801
3802static struct regulator_consumer_supply vreg_consumers_PM8901_L0[] = {
3803 REGULATOR_SUPPLY("8901_l0", NULL),
3804};
3805static struct regulator_consumer_supply vreg_consumers_PM8901_L1[] = {
3806 REGULATOR_SUPPLY("8901_l1", NULL),
3807};
3808static struct regulator_consumer_supply vreg_consumers_PM8901_L2[] = {
3809 REGULATOR_SUPPLY("8901_l2", NULL),
3810};
3811static struct regulator_consumer_supply vreg_consumers_PM8901_L3[] = {
3812 REGULATOR_SUPPLY("8901_l3", NULL),
3813};
3814static struct regulator_consumer_supply vreg_consumers_PM8901_L4[] = {
3815 REGULATOR_SUPPLY("8901_l4", NULL),
3816};
3817static struct regulator_consumer_supply vreg_consumers_PM8901_L5[] = {
3818 REGULATOR_SUPPLY("8901_l5", NULL),
3819};
3820static struct regulator_consumer_supply vreg_consumers_PM8901_L6[] = {
3821 REGULATOR_SUPPLY("8901_l6", NULL),
3822};
3823static struct regulator_consumer_supply vreg_consumers_PM8901_S2[] = {
3824 REGULATOR_SUPPLY("8901_s2", NULL),
3825};
3826static struct regulator_consumer_supply vreg_consumers_PM8901_S3[] = {
3827 REGULATOR_SUPPLY("8901_s3", NULL),
3828};
3829static struct regulator_consumer_supply vreg_consumers_PM8901_S4[] = {
3830 REGULATOR_SUPPLY("8901_s4", NULL),
3831};
3832static struct regulator_consumer_supply vreg_consumers_PM8901_LVS0[] = {
3833 REGULATOR_SUPPLY("8901_lvs0", NULL),
3834};
3835static struct regulator_consumer_supply vreg_consumers_PM8901_LVS1[] = {
3836 REGULATOR_SUPPLY("8901_lvs1", NULL),
3837};
3838static struct regulator_consumer_supply vreg_consumers_PM8901_LVS2[] = {
3839 REGULATOR_SUPPLY("8901_lvs2", NULL),
3840};
3841static struct regulator_consumer_supply vreg_consumers_PM8901_LVS3[] = {
3842 REGULATOR_SUPPLY("8901_lvs3", NULL),
3843};
3844static struct regulator_consumer_supply vreg_consumers_PM8901_MVS0[] = {
3845 REGULATOR_SUPPLY("8901_mvs0", NULL),
3846};
3847
David Collins6f032ba2011-08-31 14:08:15 -07003848/* Pin control regulators */
3849static struct regulator_consumer_supply vreg_consumers_PM8058_L8_PC[] = {
3850 REGULATOR_SUPPLY("8058_l8_pc", NULL),
3851};
3852static struct regulator_consumer_supply vreg_consumers_PM8058_L20_PC[] = {
3853 REGULATOR_SUPPLY("8058_l20_pc", NULL),
3854};
3855static struct regulator_consumer_supply vreg_consumers_PM8058_L21_PC[] = {
3856 REGULATOR_SUPPLY("8058_l21_pc", NULL),
3857};
3858static struct regulator_consumer_supply vreg_consumers_PM8058_S2_PC[] = {
3859 REGULATOR_SUPPLY("8058_s2_pc", NULL),
3860};
3861static struct regulator_consumer_supply vreg_consumers_PM8901_L0_PC[] = {
3862 REGULATOR_SUPPLY("8901_l0_pc", NULL),
3863};
3864static struct regulator_consumer_supply vreg_consumers_PM8901_S4_PC[] = {
3865 REGULATOR_SUPPLY("8901_s4_pc", NULL),
3866};
3867
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003868#define RPM_VREG_INIT(_id, _min_uV, _max_uV, _modes, _ops, _apply_uV, \
3869 _default_uV, _peak_uA, _avg_uA, _pull_down, _pin_ctrl, \
David Collins6f032ba2011-08-31 14:08:15 -07003870 _freq, _pin_fn, _force_mode, _state, _sleep_selectable, \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003871 _always_on) \
David Collins6f032ba2011-08-31 14:08:15 -07003872 { \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003873 .init_data = { \
3874 .constraints = { \
David Collins6f032ba2011-08-31 14:08:15 -07003875 .valid_modes_mask = _modes, \
3876 .valid_ops_mask = _ops, \
3877 .min_uV = _min_uV, \
3878 .max_uV = _max_uV, \
3879 .input_uV = _min_uV, \
3880 .apply_uV = _apply_uV, \
3881 .always_on = _always_on, \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003882 }, \
David Collins6f032ba2011-08-31 14:08:15 -07003883 .consumer_supplies = vreg_consumers_##_id, \
3884 .num_consumer_supplies = \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003885 ARRAY_SIZE(vreg_consumers_##_id), \
3886 }, \
David Collins6f032ba2011-08-31 14:08:15 -07003887 .id = RPM_VREG_ID_##_id, \
3888 .default_uV = _default_uV, \
3889 .peak_uA = _peak_uA, \
3890 .avg_uA = _avg_uA, \
3891 .pull_down_enable = _pull_down, \
3892 .pin_ctrl = _pin_ctrl, \
3893 .freq = RPM_VREG_FREQ_##_freq, \
3894 .pin_fn = _pin_fn, \
3895 .force_mode = _force_mode, \
3896 .state = _state, \
3897 .sleep_selectable = _sleep_selectable, \
3898 }
3899
3900/* Pin control initialization */
3901#define RPM_PC(_id, _always_on, _pin_fn, _pin_ctrl) \
3902 { \
3903 .init_data = { \
3904 .constraints = { \
3905 .valid_ops_mask = REGULATOR_CHANGE_STATUS, \
3906 .always_on = _always_on, \
3907 }, \
3908 .num_consumer_supplies = \
3909 ARRAY_SIZE(vreg_consumers_##_id##_PC), \
3910 .consumer_supplies = vreg_consumers_##_id##_PC, \
3911 }, \
3912 .id = RPM_VREG_ID_##_id##_PC, \
3913 .pin_fn = RPM_VREG_PIN_FN_8660_##_pin_fn, \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003914 .pin_ctrl = _pin_ctrl, \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003915 }
3916
3917/*
3918 * The default LPM/HPM state of an RPM controlled regulator can be controlled
3919 * via the peak_uA value specified in the table below. If the value is less
3920 * than the high power min threshold for the regulator, then the regulator will
3921 * be set to LPM. Otherwise, it will be set to HPM.
3922 *
3923 * This value can be further overridden by specifying an initial mode via
3924 * .init_data.constraints.initial_mode.
3925 */
3926
David Collins6f032ba2011-08-31 14:08:15 -07003927#define RPM_LDO(_id, _always_on, _pd, _sleep_selectable, _min_uV, _max_uV, \
3928 _init_peak_uA) \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003929 RPM_VREG_INIT(_id, _min_uV, _max_uV, REGULATOR_MODE_FAST | \
3930 REGULATOR_MODE_NORMAL | REGULATOR_MODE_IDLE | \
3931 REGULATOR_MODE_STANDBY, REGULATOR_CHANGE_VOLTAGE | \
3932 REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_MODE | \
3933 REGULATOR_CHANGE_DRMS, 0, _min_uV, _init_peak_uA, \
David Collins6f032ba2011-08-31 14:08:15 -07003934 _init_peak_uA, _pd, RPM_VREG_PIN_CTRL_NONE, NONE, \
3935 RPM_VREG_PIN_FN_8660_ENABLE, \
3936 RPM_VREG_FORCE_MODE_8660_NONE, RPM_VREG_STATE_OFF, \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003937 _sleep_selectable, _always_on)
3938
David Collins6f032ba2011-08-31 14:08:15 -07003939#define RPM_SMPS(_id, _always_on, _pd, _sleep_selectable, _min_uV, _max_uV, \
3940 _init_peak_uA, _freq) \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003941 RPM_VREG_INIT(_id, _min_uV, _max_uV, REGULATOR_MODE_FAST | \
3942 REGULATOR_MODE_NORMAL | REGULATOR_MODE_IDLE | \
3943 REGULATOR_MODE_STANDBY, REGULATOR_CHANGE_VOLTAGE | \
3944 REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_MODE | \
3945 REGULATOR_CHANGE_DRMS, 0, _min_uV, _init_peak_uA, \
David Collins6f032ba2011-08-31 14:08:15 -07003946 _init_peak_uA, _pd, RPM_VREG_PIN_CTRL_NONE, _freq, \
3947 RPM_VREG_PIN_FN_8660_ENABLE, \
3948 RPM_VREG_FORCE_MODE_8660_NONE, RPM_VREG_STATE_OFF, \
3949 _sleep_selectable, _always_on)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003950
David Collins6f032ba2011-08-31 14:08:15 -07003951#define RPM_VS(_id, _always_on, _pd, _sleep_selectable) \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003952 RPM_VREG_INIT(_id, 0, 0, REGULATOR_MODE_NORMAL | REGULATOR_MODE_IDLE, \
3953 REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_MODE, 0, 0, \
David Collins6f032ba2011-08-31 14:08:15 -07003954 1000, 1000, _pd, RPM_VREG_PIN_CTRL_NONE, NONE, \
3955 RPM_VREG_PIN_FN_8660_ENABLE, \
3956 RPM_VREG_FORCE_MODE_8660_NONE, RPM_VREG_STATE_OFF, \
3957 _sleep_selectable, _always_on)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003958
David Collins6f032ba2011-08-31 14:08:15 -07003959#define RPM_NCP(_id, _always_on, _pd, _sleep_selectable, _min_uV, _max_uV) \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003960 RPM_VREG_INIT(_id, _min_uV, _max_uV, REGULATOR_MODE_NORMAL, \
3961 REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS, 0, \
David Collins6f032ba2011-08-31 14:08:15 -07003962 _min_uV, 1000, 1000, _pd, RPM_VREG_PIN_CTRL_NONE, NONE, \
3963 RPM_VREG_PIN_FN_8660_ENABLE, \
3964 RPM_VREG_FORCE_MODE_8660_NONE, RPM_VREG_STATE_OFF, \
3965 _sleep_selectable, _always_on)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003966
David Collins6f032ba2011-08-31 14:08:15 -07003967#define LDO50HMIN RPM_VREG_8660_LDO_50_HPM_MIN_LOAD
3968#define LDO150HMIN RPM_VREG_8660_LDO_150_HPM_MIN_LOAD
3969#define LDO300HMIN RPM_VREG_8660_LDO_300_HPM_MIN_LOAD
3970#define SMPS_HMIN RPM_VREG_8660_SMPS_HPM_MIN_LOAD
3971#define FTS_HMIN RPM_VREG_8660_FTSMPS_HPM_MIN_LOAD
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003972
David Collins6f032ba2011-08-31 14:08:15 -07003973/* RPM early regulator constraints */
3974static struct rpm_regulator_init_data rpm_regulator_early_init_data[] = {
3975 /* ID a_on pd ss min_uV max_uV init_ip freq */
3976 RPM_SMPS(PM8058_S0, 0, 1, 1, 500000, 1250000, SMPS_HMIN, 1p60),
3977 RPM_SMPS(PM8058_S1, 0, 1, 1, 500000, 1250000, SMPS_HMIN, 1p60),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003978};
3979
David Collins6f032ba2011-08-31 14:08:15 -07003980/* RPM regulator constraints */
3981static struct rpm_regulator_init_data rpm_regulator_init_data[] = {
3982 /* ID a_on pd ss min_uV max_uV init_ip */
3983 RPM_LDO(PM8058_L0, 0, 1, 0, 1200000, 1200000, LDO150HMIN),
3984 RPM_LDO(PM8058_L1, 0, 1, 0, 1200000, 1200000, LDO300HMIN),
3985 RPM_LDO(PM8058_L2, 0, 1, 0, 1800000, 2600000, LDO300HMIN),
3986 RPM_LDO(PM8058_L3, 0, 1, 0, 1800000, 1800000, LDO150HMIN),
3987 RPM_LDO(PM8058_L4, 0, 1, 0, 2850000, 2850000, LDO50HMIN),
3988 RPM_LDO(PM8058_L5, 0, 1, 0, 2850000, 2850000, LDO300HMIN),
3989 RPM_LDO(PM8058_L6, 0, 1, 0, 3000000, 3600000, LDO50HMIN),
3990 RPM_LDO(PM8058_L7, 0, 1, 0, 1800000, 1800000, LDO50HMIN),
3991 RPM_LDO(PM8058_L8, 0, 1, 0, 2900000, 3050000, LDO300HMIN),
3992 RPM_LDO(PM8058_L9, 0, 1, 0, 1800000, 1800000, LDO300HMIN),
3993 RPM_LDO(PM8058_L10, 0, 1, 0, 2600000, 2600000, LDO300HMIN),
3994 RPM_LDO(PM8058_L11, 0, 1, 0, 1500000, 1500000, LDO150HMIN),
3995 RPM_LDO(PM8058_L12, 0, 1, 0, 2900000, 2900000, LDO150HMIN),
3996 RPM_LDO(PM8058_L13, 0, 1, 0, 2050000, 2050000, LDO300HMIN),
3997 RPM_LDO(PM8058_L14, 0, 0, 0, 2850000, 2850000, LDO300HMIN),
3998 RPM_LDO(PM8058_L15, 0, 1, 0, 2850000, 2850000, LDO300HMIN),
3999 RPM_LDO(PM8058_L16, 1, 1, 0, 1800000, 1800000, LDO300HMIN),
4000 RPM_LDO(PM8058_L17, 0, 1, 0, 2600000, 2600000, LDO150HMIN),
4001 RPM_LDO(PM8058_L18, 0, 1, 0, 2200000, 2200000, LDO150HMIN),
4002 RPM_LDO(PM8058_L19, 0, 1, 0, 2500000, 2500000, LDO150HMIN),
4003 RPM_LDO(PM8058_L20, 0, 1, 0, 1800000, 1800000, LDO150HMIN),
4004 RPM_LDO(PM8058_L21, 1, 1, 0, 1200000, 1200000, LDO150HMIN),
4005 RPM_LDO(PM8058_L22, 0, 1, 0, 1150000, 1150000, LDO300HMIN),
4006 RPM_LDO(PM8058_L23, 0, 1, 0, 1200000, 1200000, LDO300HMIN),
4007 RPM_LDO(PM8058_L24, 0, 1, 0, 1200000, 1200000, LDO150HMIN),
4008 RPM_LDO(PM8058_L25, 0, 1, 0, 1200000, 1200000, LDO150HMIN),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004009
David Collins6f032ba2011-08-31 14:08:15 -07004010 /* ID a_on pd ss min_uV max_uV init_ip freq */
4011 RPM_SMPS(PM8058_S2, 0, 1, 1, 1200000, 1400000, SMPS_HMIN, 1p60),
4012 RPM_SMPS(PM8058_S3, 1, 1, 0, 1800000, 1800000, SMPS_HMIN, 1p60),
4013 RPM_SMPS(PM8058_S4, 1, 1, 0, 2200000, 2200000, SMPS_HMIN, 1p60),
4014
4015 /* ID a_on pd ss */
4016 RPM_VS(PM8058_LVS0, 0, 1, 0),
4017 RPM_VS(PM8058_LVS1, 0, 1, 0),
4018
4019 /* ID a_on pd ss min_uV max_uV */
4020 RPM_NCP(PM8058_NCP, 0, 1, 0, 1800000, 1800000),
4021
4022 /* ID a_on pd ss min_uV max_uV init_ip */
4023 RPM_LDO(PM8901_L0, 0, 1, 0, 1200000, 1200000, LDO300HMIN),
4024 RPM_LDO(PM8901_L1, 0, 1, 0, 3300000, 3300000, LDO300HMIN),
4025 RPM_LDO(PM8901_L2, 0, 1, 0, 2850000, 3300000, LDO300HMIN),
4026 RPM_LDO(PM8901_L3, 0, 1, 0, 3300000, 3300000, LDO300HMIN),
4027 RPM_LDO(PM8901_L4, 0, 1, 0, 2600000, 2600000, LDO300HMIN),
4028 RPM_LDO(PM8901_L5, 0, 1, 0, 2850000, 2850000, LDO300HMIN),
4029 RPM_LDO(PM8901_L6, 0, 1, 0, 2200000, 2200000, LDO300HMIN),
4030
4031 /* ID a_on pd ss min_uV max_uV init_ip freq */
4032 RPM_SMPS(PM8901_S2, 0, 1, 0, 1300000, 1300000, FTS_HMIN, 1p60),
4033 RPM_SMPS(PM8901_S3, 0, 1, 0, 1100000, 1100000, FTS_HMIN, 1p60),
4034 RPM_SMPS(PM8901_S4, 0, 1, 0, 1225000, 1225000, FTS_HMIN, 1p60),
4035
4036 /* ID a_on pd ss */
4037 RPM_VS(PM8901_LVS0, 1, 1, 0),
4038 RPM_VS(PM8901_LVS1, 0, 1, 0),
4039 RPM_VS(PM8901_LVS2, 0, 1, 0),
4040 RPM_VS(PM8901_LVS3, 0, 1, 0),
4041 RPM_VS(PM8901_MVS0, 0, 1, 0),
4042
4043 /* ID a_on pin_func pin_ctrl */
4044 RPM_PC(PM8058_L8, 0, SLEEP_B, RPM_VREG_PIN_CTRL_NONE),
4045 RPM_PC(PM8058_L20, 0, SLEEP_B, RPM_VREG_PIN_CTRL_NONE),
4046 RPM_PC(PM8058_L21, 1, SLEEP_B, RPM_VREG_PIN_CTRL_NONE),
4047 RPM_PC(PM8058_S2, 0, ENABLE, RPM_VREG_PIN_CTRL_PM8058_A0),
4048 RPM_PC(PM8901_L0, 0, ENABLE, RPM_VREG_PIN_CTRL_PM8901_A0),
4049 RPM_PC(PM8901_S4, 0, ENABLE, RPM_VREG_PIN_CTRL_PM8901_A0),
4050};
4051
4052static struct rpm_regulator_platform_data rpm_regulator_early_pdata = {
4053 .init_data = rpm_regulator_early_init_data,
4054 .num_regulators = ARRAY_SIZE(rpm_regulator_early_init_data),
4055 .version = RPM_VREG_VERSION_8660,
4056 .vreg_id_vdd_mem = RPM_VREG_ID_PM8058_S0,
4057 .vreg_id_vdd_dig = RPM_VREG_ID_PM8058_S1,
4058};
4059
4060static struct rpm_regulator_platform_data rpm_regulator_pdata = {
4061 .init_data = rpm_regulator_init_data,
4062 .num_regulators = ARRAY_SIZE(rpm_regulator_init_data),
4063 .version = RPM_VREG_VERSION_8660,
4064};
4065
4066static struct platform_device rpm_regulator_early_device = {
4067 .name = "rpm-regulator",
4068 .id = 0,
4069 .dev = {
4070 .platform_data = &rpm_regulator_early_pdata,
4071 },
4072};
4073
4074static struct platform_device rpm_regulator_device = {
4075 .name = "rpm-regulator",
4076 .id = 1,
4077 .dev = {
4078 .platform_data = &rpm_regulator_pdata,
4079 },
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004080};
4081
4082static struct platform_device *early_regulators[] __initdata = {
4083 &msm_device_saw_s0,
4084 &msm_device_saw_s1,
David Collins6f032ba2011-08-31 14:08:15 -07004085 &rpm_regulator_early_device,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004086};
4087
4088static struct platform_device *early_devices[] __initdata = {
4089#ifdef CONFIG_MSM_BUS_SCALING
4090 &msm_bus_apps_fabric,
4091 &msm_bus_sys_fabric,
4092 &msm_bus_mm_fabric,
4093 &msm_bus_sys_fpb,
4094 &msm_bus_cpss_fpb,
4095#endif
4096 &msm_device_dmov_adm0,
4097 &msm_device_dmov_adm1,
4098};
4099
4100#if (defined(CONFIG_MARIMBA_CORE)) && \
4101 (defined(CONFIG_MSM_BT_POWER) || defined(CONFIG_MSM_BT_POWER_MODULE))
4102
4103static int bluetooth_power(int);
4104static struct platform_device msm_bt_power_device = {
4105 .name = "bt_power",
4106 .id = -1,
4107 .dev = {
4108 .platform_data = &bluetooth_power,
4109 },
4110};
4111#endif
4112
4113static struct platform_device msm_tsens_device = {
4114 .name = "tsens-tm",
4115 .id = -1,
4116};
4117
4118static struct platform_device *rumi_sim_devices[] __initdata = {
4119 &smc91x_device,
4120 &msm_device_uart_dm12,
4121#ifdef CONFIG_I2C_QUP
4122 &msm_gsbi3_qup_i2c_device,
4123 &msm_gsbi4_qup_i2c_device,
4124 &msm_gsbi7_qup_i2c_device,
4125 &msm_gsbi8_qup_i2c_device,
4126 &msm_gsbi9_qup_i2c_device,
4127 &msm_gsbi12_qup_i2c_device,
4128#endif
4129#ifdef CONFIG_I2C_SSBI
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004130 &msm_device_ssbi2,
4131 &msm_device_ssbi3,
4132#endif
4133#ifdef CONFIG_ANDROID_PMEM
4134 &android_pmem_device,
4135 &android_pmem_adsp_device,
4136 &android_pmem_audio_device,
4137 &android_pmem_smipool_device,
4138#endif
4139#ifdef CONFIG_MSM_ROTATOR
4140 &msm_rotator_device,
4141#endif
4142 &msm_fb_device,
4143 &msm_kgsl_3d0,
4144 &msm_kgsl_2d0,
4145 &msm_kgsl_2d1,
4146 &lcdc_samsung_panel_device,
4147#ifdef CONFIG_FB_MSM_HDMI_MSM_PANEL
4148 &hdmi_msm_device,
4149#endif /* CONFIG_FB_MSM_HDMI_MSM_PANEL */
4150#ifdef CONFIG_MSM_CAMERA
4151#ifdef CONFIG_MT9E013
4152 &msm_camera_sensor_mt9e013,
4153#endif
4154#ifdef CONFIG_IMX074
4155 &msm_camera_sensor_imx074,
4156#endif
Jilai Wang971f97f2011-07-13 14:25:25 -04004157#ifdef CONFIG_VX6953
4158 &msm_camera_sensor_vx6953,
4159#endif
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004160#ifdef CONFIG_WEBCAM_OV7692
4161 &msm_camera_sensor_webcam_ov7692,
4162#endif
4163#ifdef CONFIG_WEBCAM_OV9726
4164 &msm_camera_sensor_webcam_ov9726,
4165#endif
4166#ifdef CONFIG_QS_S5K4E1
4167 &msm_camera_sensor_qs_s5k4e1,
4168#endif
4169#endif
4170#ifdef CONFIG_MSM_GEMINI
4171 &msm_gemini_device,
4172#endif
4173#ifdef CONFIG_MSM_VPE
4174 &msm_vpe_device,
4175#endif
4176 &msm_device_vidc,
4177};
4178
4179#if defined(CONFIG_GPIO_SX150X) || defined(CONFIG_GPIO_SX150X_MODULE)
4180enum {
4181 SX150X_CORE,
4182 SX150X_DOCKING,
4183 SX150X_SURF,
4184 SX150X_LEFT_FHA,
4185 SX150X_RIGHT_FHA,
4186 SX150X_SOUTH,
4187 SX150X_NORTH,
4188 SX150X_CORE_FLUID,
4189};
4190
4191static struct sx150x_platform_data sx150x_data[] __initdata = {
4192 [SX150X_CORE] = {
4193 .gpio_base = GPIO_CORE_EXPANDER_BASE,
4194 .oscio_is_gpo = false,
4195 .io_pullup_ena = 0x0c08,
4196 .io_pulldn_ena = 0x4060,
4197 .io_open_drain_ena = 0x000c,
4198 .io_polarity = 0,
4199 .irq_summary = -1, /* see fixup_i2c_configs() */
4200 .irq_base = GPIO_EXPANDER_IRQ_BASE,
4201 },
4202 [SX150X_DOCKING] = {
4203 .gpio_base = GPIO_DOCKING_EXPANDER_BASE,
4204 .oscio_is_gpo = false,
4205 .io_pullup_ena = 0x5e06,
4206 .io_pulldn_ena = 0x81b8,
4207 .io_open_drain_ena = 0,
4208 .io_polarity = 0,
4209 .irq_summary = PM8058_GPIO_IRQ(PM8058_IRQ_BASE,
4210 UI_INT2_N),
4211 .irq_base = GPIO_EXPANDER_IRQ_BASE +
4212 GPIO_DOCKING_EXPANDER_BASE -
4213 GPIO_EXPANDER_GPIO_BASE,
4214 },
4215 [SX150X_SURF] = {
4216 .gpio_base = GPIO_SURF_EXPANDER_BASE,
4217 .oscio_is_gpo = false,
4218 .io_pullup_ena = 0,
4219 .io_pulldn_ena = 0,
4220 .io_open_drain_ena = 0,
4221 .io_polarity = 0,
4222 .irq_summary = PM8058_GPIO_IRQ(PM8058_IRQ_BASE,
4223 UI_INT1_N),
4224 .irq_base = GPIO_EXPANDER_IRQ_BASE +
4225 GPIO_SURF_EXPANDER_BASE -
4226 GPIO_EXPANDER_GPIO_BASE,
4227 },
4228 [SX150X_LEFT_FHA] = {
4229 .gpio_base = GPIO_LEFT_KB_EXPANDER_BASE,
4230 .oscio_is_gpo = false,
4231 .io_pullup_ena = 0,
4232 .io_pulldn_ena = 0x40,
4233 .io_open_drain_ena = 0,
4234 .io_polarity = 0,
4235 .irq_summary = PM8058_GPIO_IRQ(PM8058_IRQ_BASE,
4236 UI_INT3_N),
4237 .irq_base = GPIO_EXPANDER_IRQ_BASE +
4238 GPIO_LEFT_KB_EXPANDER_BASE -
4239 GPIO_EXPANDER_GPIO_BASE,
4240 },
4241 [SX150X_RIGHT_FHA] = {
4242 .gpio_base = GPIO_RIGHT_KB_EXPANDER_BASE,
4243 .oscio_is_gpo = true,
4244 .io_pullup_ena = 0,
4245 .io_pulldn_ena = 0,
4246 .io_open_drain_ena = 0,
4247 .io_polarity = 0,
4248 .irq_summary = PM8058_GPIO_IRQ(PM8058_IRQ_BASE,
4249 UI_INT3_N),
4250 .irq_base = GPIO_EXPANDER_IRQ_BASE +
4251 GPIO_RIGHT_KB_EXPANDER_BASE -
4252 GPIO_EXPANDER_GPIO_BASE,
4253 },
4254 [SX150X_SOUTH] = {
4255 .gpio_base = GPIO_SOUTH_EXPANDER_BASE,
4256 .irq_base = GPIO_EXPANDER_IRQ_BASE +
4257 GPIO_SOUTH_EXPANDER_BASE -
4258 GPIO_EXPANDER_GPIO_BASE,
4259 .irq_summary = PM8058_GPIO_IRQ(PM8058_IRQ_BASE, UI_INT3_N),
4260 },
4261 [SX150X_NORTH] = {
4262 .gpio_base = GPIO_NORTH_EXPANDER_BASE,
4263 .irq_base = GPIO_EXPANDER_IRQ_BASE +
4264 GPIO_NORTH_EXPANDER_BASE -
4265 GPIO_EXPANDER_GPIO_BASE,
4266 .irq_summary = PM8058_GPIO_IRQ(PM8058_IRQ_BASE, UI_INT3_N),
4267 .oscio_is_gpo = true,
4268 .io_open_drain_ena = 0x30,
4269 },
4270 [SX150X_CORE_FLUID] = {
4271 .gpio_base = GPIO_CORE_EXPANDER_BASE,
4272 .oscio_is_gpo = false,
4273 .io_pullup_ena = 0x0408,
4274 .io_pulldn_ena = 0x4060,
4275 .io_open_drain_ena = 0x0008,
4276 .io_polarity = 0,
4277 .irq_summary = -1, /* see fixup_i2c_configs() */
4278 .irq_base = GPIO_EXPANDER_IRQ_BASE,
4279 },
4280};
4281
4282#ifdef CONFIG_SENSORS_MSM_ADC
4283/* Configuration of EPM expander is done when client
4284 * request an adc read
4285 */
4286static struct sx150x_platform_data sx150x_epmdata = {
4287 .gpio_base = GPIO_EPM_EXPANDER_BASE,
4288 .irq_base = GPIO_EXPANDER_IRQ_BASE +
4289 GPIO_EPM_EXPANDER_BASE -
4290 GPIO_EXPANDER_GPIO_BASE,
4291 .irq_summary = -1,
4292};
4293#endif
4294
4295/* sx150x_low_power_cfg
4296 *
4297 * This data and init function are used to put unused gpio-expander output
4298 * lines into their low-power states at boot. The init
4299 * function must be deferred until a later init stage because the i2c
4300 * gpio expander drivers do not probe until after they are registered
4301 * (see register_i2c_devices) and the work-queues for those registrations
4302 * are processed. Because these lines are unused, there is no risk of
4303 * competing with a device driver for the gpio.
4304 *
4305 * gpio lines whose low-power states are input are naturally in their low-
4306 * power configurations once probed, see the platform data structures above.
4307 */
4308struct sx150x_low_power_cfg {
4309 unsigned gpio;
4310 unsigned val;
4311};
4312
4313static struct sx150x_low_power_cfg
4314common_sx150x_lp_cfgs[] __initdata = {
4315 {GPIO_WLAN_DEEP_SLEEP_N, 0},
4316 {GPIO_EXT_GPS_LNA_EN, 0},
4317 {GPIO_MSM_WAKES_BT, 0},
4318 {GPIO_USB_UICC_EN, 0},
4319 {GPIO_BATT_GAUGE_EN, 0},
4320};
4321
4322static struct sx150x_low_power_cfg
4323surf_ffa_sx150x_lp_cfgs[] __initdata = {
4324 {GPIO_MIPI_DSI_RST_N, 0},
4325 {GPIO_DONGLE_PWR_EN, 0},
4326 {GPIO_CAP_TS_SLEEP, 1},
4327 {GPIO_WEB_CAMIF_RESET_N, 0},
4328};
4329
4330static void __init
4331cfg_gpio_low_power(struct sx150x_low_power_cfg *cfgs, unsigned nelems)
4332{
4333 unsigned n;
4334 int rc;
4335
4336 for (n = 0; n < nelems; ++n) {
4337 rc = gpio_request(cfgs[n].gpio, NULL);
4338 if (!rc) {
4339 rc = gpio_direction_output(cfgs[n].gpio, cfgs[n].val);
4340 gpio_free(cfgs[n].gpio);
4341 }
4342
4343 if (rc) {
4344 printk(KERN_NOTICE "%s: failed to sleep gpio %d: %d\n",
4345 __func__, cfgs[n].gpio, rc);
4346 }
Steve Muckle9161d302010-02-11 11:50:40 -08004347 }
Steve Mucklea55df6e2010-01-07 12:43:24 -08004348}
4349
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004350static int __init cfg_sx150xs_low_power(void)
Steve Mucklea55df6e2010-01-07 12:43:24 -08004351{
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004352 cfg_gpio_low_power(common_sx150x_lp_cfgs,
4353 ARRAY_SIZE(common_sx150x_lp_cfgs));
4354 if (!machine_is_msm8x60_fluid())
4355 cfg_gpio_low_power(surf_ffa_sx150x_lp_cfgs,
4356 ARRAY_SIZE(surf_ffa_sx150x_lp_cfgs));
4357 return 0;
4358}
4359module_init(cfg_sx150xs_low_power);
4360
4361#ifdef CONFIG_I2C
4362static struct i2c_board_info core_expander_i2c_info[] __initdata = {
4363 {
4364 I2C_BOARD_INFO("sx1509q", 0x3e),
4365 .platform_data = &sx150x_data[SX150X_CORE]
4366 },
4367};
4368
4369static struct i2c_board_info docking_expander_i2c_info[] __initdata = {
4370 {
4371 I2C_BOARD_INFO("sx1509q", 0x3f),
4372 .platform_data = &sx150x_data[SX150X_DOCKING]
4373 },
4374};
4375
4376static struct i2c_board_info surf_expanders_i2c_info[] __initdata = {
4377 {
4378 I2C_BOARD_INFO("sx1509q", 0x70),
4379 .platform_data = &sx150x_data[SX150X_SURF]
4380 }
4381};
4382
4383static struct i2c_board_info fha_expanders_i2c_info[] __initdata = {
4384 {
4385 I2C_BOARD_INFO("sx1508q", 0x21),
4386 .platform_data = &sx150x_data[SX150X_LEFT_FHA]
4387 },
4388 {
4389 I2C_BOARD_INFO("sx1508q", 0x22),
4390 .platform_data = &sx150x_data[SX150X_RIGHT_FHA]
4391 }
4392};
4393
4394static struct i2c_board_info fluid_expanders_i2c_info[] __initdata = {
4395 {
4396 I2C_BOARD_INFO("sx1508q", 0x23),
4397 .platform_data = &sx150x_data[SX150X_SOUTH]
4398 },
4399 {
4400 I2C_BOARD_INFO("sx1508q", 0x20),
4401 .platform_data = &sx150x_data[SX150X_NORTH]
4402 }
4403};
4404
4405static struct i2c_board_info fluid_core_expander_i2c_info[] __initdata = {
4406 {
4407 I2C_BOARD_INFO("sx1509q", 0x3e),
4408 .platform_data = &sx150x_data[SX150X_CORE_FLUID]
4409 },
4410};
4411
4412#ifdef CONFIG_SENSORS_MSM_ADC
4413static struct i2c_board_info fluid_expanders_i2c_epm_info[] = {
4414 {
4415 I2C_BOARD_INFO("sx1509q", 0x3e),
4416 .platform_data = &sx150x_epmdata
4417 },
4418};
4419#endif
4420#endif
4421#endif
4422
4423#ifdef CONFIG_SENSORS_MSM_ADC
4424static struct resource resources_adc[] = {
4425 {
4426 .start = PM8058_ADC_IRQ(PM8058_IRQ_BASE),
4427 .end = PM8058_ADC_IRQ(PM8058_IRQ_BASE),
4428 .flags = IORESOURCE_IRQ,
4429 },
4430};
4431
4432static struct adc_access_fn xoadc_fn = {
4433 pm8058_xoadc_select_chan_and_start_conv,
4434 pm8058_xoadc_read_adc_code,
4435 pm8058_xoadc_get_properties,
4436 pm8058_xoadc_slot_request,
4437 pm8058_xoadc_restore_slot,
4438 pm8058_xoadc_calibrate,
4439};
4440
4441#if defined(CONFIG_I2C) && \
4442 (defined(CONFIG_GPIO_SX150X) || defined(CONFIG_GPIO_SX150X_MODULE))
4443static struct regulator *vreg_adc_epm1;
4444
4445static struct i2c_client *epm_expander_i2c_register_board(void)
4446
4447{
4448 struct i2c_adapter *i2c_adap;
4449 struct i2c_client *client = NULL;
4450 i2c_adap = i2c_get_adapter(0x0);
4451
4452 if (i2c_adap == NULL)
4453 printk(KERN_ERR "\nepm_expander_i2c_adapter is NULL\n");
4454
4455 if (i2c_adap != NULL)
4456 client = i2c_new_device(i2c_adap,
4457 &fluid_expanders_i2c_epm_info[0]);
4458 return client;
4459
4460}
4461
4462static unsigned int msm_adc_gpio_configure_expander_enable(void)
4463{
4464 int rc = 0;
4465 static struct i2c_client *epm_i2c_client;
4466
4467 printk(KERN_DEBUG "Enter msm_adc_gpio_configure_expander_enable\n");
4468
4469 vreg_adc_epm1 = regulator_get(NULL, "8058_s3");
4470
4471 if (IS_ERR(vreg_adc_epm1)) {
4472 printk(KERN_ERR "%s: Unable to get 8058_s3\n", __func__);
4473 return 0;
4474 }
4475
4476 rc = regulator_set_voltage(vreg_adc_epm1, 1800000, 1800000);
4477 if (rc)
4478 printk(KERN_ERR "msm_adc_gpio_configure_expander_enable: "
4479 "regulator set voltage failed\n");
4480
4481 rc = regulator_enable(vreg_adc_epm1);
4482 if (rc) {
4483 printk(KERN_ERR "msm_adc_gpio_configure_expander_enable: "
4484 "Error while enabling regulator for epm s3 %d\n", rc);
4485 return rc;
4486 }
4487
4488 printk(KERN_DEBUG "msm_adc_gpio_configure_expander_enable: Start"
4489 " setting the value of the EPM 3.3, 5v and lvlsft\n");
4490
4491 msleep(1000);
4492
4493 rc = gpio_request(GPIO_EPM_5V_BOOST_EN, "boost_epm_5v");
4494 if (!rc) {
4495 printk(KERN_DEBUG "msm_adc_gpio_configure_expander_enable: "
4496 "Configure 5v boost\n");
4497 gpio_direction_output(GPIO_EPM_5V_BOOST_EN, 1);
4498 } else {
4499 printk(KERN_ERR "msm_adc_gpio_configure_expander_enable: "
4500 "Error for epm 5v boost en\n");
4501 goto exit_vreg_epm;
4502 }
4503
4504 msleep(500);
4505
4506 rc = gpio_request(GPIO_EPM_3_3V_EN, "epm_3_3v");
4507 if (!rc) {
4508 gpio_direction_output(GPIO_EPM_3_3V_EN, 1);
4509 printk(KERN_DEBUG "msm_adc_gpio_configure_expander_enable: "
4510 "Configure epm 3.3v\n");
4511 } else {
4512 printk(KERN_ERR "msm_adc_gpio_configure_expander_enable: "
4513 "Error for gpio 3.3ven\n");
4514 goto exit_vreg_epm;
4515 }
4516 msleep(500);
4517
4518 printk(KERN_DEBUG "msm_adc_gpio_configure_expander_enable: "
4519 "Trying to request EPM LVLSFT_EN\n");
4520 rc = gpio_request(GPIO_EPM_LVLSFT_EN, "lvsft_en");
4521 if (!rc) {
4522 gpio_direction_output(GPIO_EPM_LVLSFT_EN, 1);
4523 printk(KERN_DEBUG "msm_adc_gpio_configure_expander_enable: "
4524 "Configure the lvlsft\n");
4525 } else {
4526 printk(KERN_ERR "msm_adc_gpio_configure_expander_enable: "
4527 "Error for epm lvlsft_en\n");
4528 goto exit_vreg_epm;
4529 }
4530
4531 msleep(500);
4532
4533 if (!epm_i2c_client)
4534 epm_i2c_client = epm_expander_i2c_register_board();
4535
4536 rc = gpio_request(GPIO_PWR_MON_ENABLE, "pwr_mon_enable");
4537 if (!rc)
4538 rc = gpio_direction_output(GPIO_PWR_MON_ENABLE, 1);
4539 if (rc) {
4540 printk(KERN_ERR "msm_adc_gpio_configure_expander_enable"
4541 ": GPIO PWR MON Enable issue\n");
4542 goto exit_vreg_epm;
4543 }
4544
4545 msleep(1000);
4546
4547 rc = gpio_request(GPIO_ADC1_PWDN_N, "adc1_pwdn");
4548 if (!rc) {
4549 rc = gpio_direction_output(GPIO_ADC1_PWDN_N, 1);
4550 if (rc) {
4551 printk(KERN_ERR "msm_adc_gpio_configure_expander_enable"
4552 ": ADC1_PWDN error direction out\n");
4553 goto exit_vreg_epm;
4554 }
4555 }
4556
4557 msleep(100);
4558
4559 rc = gpio_request(GPIO_ADC2_PWDN_N, "adc2_pwdn");
4560 if (!rc) {
4561 rc = gpio_direction_output(GPIO_ADC2_PWDN_N, 1);
4562 if (rc) {
4563 printk(KERN_ERR "msm_adc_gpio_configure_expander_enable"
4564 ": ADC2_PWD error direction out\n");
4565 goto exit_vreg_epm;
4566 }
4567 }
4568
4569 msleep(1000);
4570
4571 rc = gpio_request(GPIO_PWR_MON_START, "pwr_mon_start");
4572 if (!rc) {
4573 rc = gpio_direction_output(GPIO_PWR_MON_START, 0);
4574 if (rc) {
4575 printk(KERN_ERR "msm_adc_gpio_configure_expander_enable"
4576 "Gpio request problem %d\n", rc);
4577 goto exit_vreg_epm;
4578 }
4579 }
4580
4581 rc = gpio_request(GPIO_EPM_SPI_ADC1_CS_N, "spi_adc1_cs");
4582 if (!rc) {
4583 rc = gpio_direction_output(GPIO_EPM_SPI_ADC1_CS_N, 0);
4584 if (rc) {
4585 printk(KERN_ERR "msm_adc_gpio_configure_expander_enable"
4586 ": EPM_SPI_ADC1_CS_N error\n");
4587 goto exit_vreg_epm;
4588 }
4589 }
4590
4591 rc = gpio_request(GPIO_EPM_SPI_ADC2_CS_N, "spi_adc2_cs");
4592 if (!rc) {
4593 rc = gpio_direction_output(GPIO_EPM_SPI_ADC2_CS_N, 0);
4594 if (rc) {
4595 printk(KERN_ERR "msm_adc_gpio_configure_expander_enable"
4596 ": EPM_SPI_ADC2_Cs_N error\n");
4597 goto exit_vreg_epm;
4598 }
4599 }
4600
4601 printk(KERN_DEBUG "msm_adc_gpio_configure_expander_enable: Set "
4602 "the power monitor reset for epm\n");
4603
4604 rc = gpio_request(GPIO_PWR_MON_RESET_N, "pwr_mon_reset_n");
4605 if (!rc) {
4606 gpio_direction_output(GPIO_PWR_MON_RESET_N, 0);
4607 if (rc) {
4608 printk(KERN_ERR "msm_adc_gpio_configure_expander_enable"
4609 ": Error in the power mon reset\n");
4610 goto exit_vreg_epm;
4611 }
4612 }
4613
4614 msleep(1000);
4615
4616 gpio_set_value_cansleep(GPIO_PWR_MON_RESET_N, 1);
4617
4618 msleep(500);
4619
4620 gpio_set_value_cansleep(GPIO_EPM_SPI_ADC1_CS_N, 1);
4621
4622 gpio_set_value_cansleep(GPIO_EPM_SPI_ADC2_CS_N, 1);
4623
4624 return rc;
4625
4626exit_vreg_epm:
4627 regulator_disable(vreg_adc_epm1);
4628
4629 printk(KERN_ERR "msm_adc_gpio_configure_expander_enable: Exit."
4630 " rc = %d.\n", rc);
4631 return rc;
4632};
4633
4634static unsigned int msm_adc_gpio_configure_expander_disable(void)
4635{
4636 int rc = 0;
4637
4638 gpio_set_value_cansleep(GPIO_PWR_MON_RESET_N, 0);
4639 gpio_free(GPIO_PWR_MON_RESET_N);
4640
4641 gpio_set_value_cansleep(GPIO_EPM_SPI_ADC1_CS_N, 0);
4642 gpio_free(GPIO_EPM_SPI_ADC1_CS_N);
4643
4644 gpio_set_value_cansleep(GPIO_EPM_SPI_ADC2_CS_N, 0);
4645 gpio_free(GPIO_EPM_SPI_ADC2_CS_N);
4646
4647 gpio_set_value_cansleep(GPIO_PWR_MON_START, 0);
4648 gpio_free(GPIO_PWR_MON_START);
4649
4650 gpio_direction_output(GPIO_ADC1_PWDN_N, 0);
4651 gpio_free(GPIO_ADC1_PWDN_N);
4652
4653 gpio_direction_output(GPIO_ADC2_PWDN_N, 0);
4654 gpio_free(GPIO_ADC2_PWDN_N);
4655
4656 gpio_set_value_cansleep(GPIO_PWR_MON_ENABLE, 0);
4657 gpio_free(GPIO_PWR_MON_ENABLE);
4658
4659 gpio_set_value_cansleep(GPIO_EPM_LVLSFT_EN, 0);
4660 gpio_free(GPIO_EPM_LVLSFT_EN);
4661
4662 gpio_set_value_cansleep(GPIO_EPM_5V_BOOST_EN, 0);
4663 gpio_free(GPIO_EPM_5V_BOOST_EN);
4664
4665 gpio_set_value_cansleep(GPIO_EPM_3_3V_EN, 0);
4666 gpio_free(GPIO_EPM_3_3V_EN);
4667
4668 rc = regulator_disable(vreg_adc_epm1);
4669 if (rc)
4670 printk(KERN_DEBUG "msm_adc_gpio_configure_expander_disable: "
4671 "Error while enabling regulator for epm s3 %d\n", rc);
4672 regulator_put(vreg_adc_epm1);
4673
4674 printk(KERN_DEBUG "Exi msm_adc_gpio_configure_expander_disable\n");
4675 return rc;
4676};
4677
4678unsigned int msm_adc_gpio_expander_enable(int cs_enable)
4679{
4680 int rc = 0;
4681
4682 printk(KERN_DEBUG "msm_adc_gpio_expander_enable: cs_enable = %d",
4683 cs_enable);
4684
4685 if (cs_enable < 16) {
4686 gpio_set_value_cansleep(GPIO_EPM_SPI_ADC1_CS_N, 0);
4687 gpio_set_value_cansleep(GPIO_EPM_SPI_ADC2_CS_N, 1);
4688 } else {
4689 gpio_set_value_cansleep(GPIO_EPM_SPI_ADC2_CS_N, 0);
4690 gpio_set_value_cansleep(GPIO_EPM_SPI_ADC1_CS_N, 1);
4691 }
4692 return rc;
4693};
4694
4695unsigned int msm_adc_gpio_expander_disable(int cs_disable)
4696{
4697 int rc = 0;
4698
4699 printk(KERN_DEBUG "Enter msm_adc_gpio_expander_disable.\n");
4700
4701 gpio_set_value_cansleep(GPIO_EPM_SPI_ADC1_CS_N, 1);
4702
4703 gpio_set_value_cansleep(GPIO_EPM_SPI_ADC2_CS_N, 1);
4704
4705 return rc;
4706};
4707#endif
4708
4709static struct msm_adc_channels msm_adc_channels_data[] = {
4710 {"vbatt", CHANNEL_ADC_VBATT, 0, &xoadc_fn, CHAN_PATH_TYPE2,
4711 ADC_CONFIG_TYPE2, ADC_CALIB_CONFIG_TYPE3, scale_default},
4712 {"vcoin", CHANNEL_ADC_VCOIN, 0, &xoadc_fn, CHAN_PATH_TYPE1,
4713 ADC_CONFIG_TYPE2, ADC_CALIB_CONFIG_TYPE2, scale_default},
4714 {"vcharger_channel", CHANNEL_ADC_VCHG, 0, &xoadc_fn, CHAN_PATH_TYPE3,
4715 ADC_CONFIG_TYPE2, ADC_CALIB_CONFIG_TYPE4, scale_default},
4716 {"charger_current_monitor", CHANNEL_ADC_CHG_MONITOR, 0, &xoadc_fn,
4717 CHAN_PATH_TYPE4,
4718 ADC_CONFIG_TYPE2, ADC_CALIB_CONFIG_TYPE1, scale_default},
4719 {"vph_pwr", CHANNEL_ADC_VPH_PWR, 0, &xoadc_fn, CHAN_PATH_TYPE5,
4720 ADC_CONFIG_TYPE2, ADC_CALIB_CONFIG_TYPE3, scale_default},
4721 {"usb_vbus", CHANNEL_ADC_USB_VBUS, 0, &xoadc_fn, CHAN_PATH_TYPE11,
4722 ADC_CONFIG_TYPE2, ADC_CALIB_CONFIG_TYPE3, scale_default},
4723 {"pmic_therm", CHANNEL_ADC_DIE_TEMP, 0, &xoadc_fn, CHAN_PATH_TYPE12,
4724 ADC_CONFIG_TYPE2, ADC_CALIB_CONFIG_TYPE1, scale_pmic_therm},
4725 {"pmic_therm_4K", CHANNEL_ADC_DIE_TEMP_4K, 0, &xoadc_fn,
4726 CHAN_PATH_TYPE12,
4727 ADC_CONFIG_TYPE1, ADC_CALIB_CONFIG_TYPE7, scale_pmic_therm},
4728 {"xo_therm", CHANNEL_ADC_XOTHERM, 0, &xoadc_fn, CHAN_PATH_TYPE_NONE,
4729 ADC_CONFIG_TYPE2, ADC_CALIB_CONFIG_TYPE5, tdkntcgtherm},
4730 {"xo_therm_4K", CHANNEL_ADC_XOTHERM_4K, 0, &xoadc_fn,
4731 CHAN_PATH_TYPE_NONE,
4732 ADC_CONFIG_TYPE1, ADC_CALIB_CONFIG_TYPE6, tdkntcgtherm},
4733 {"hdset_detect", CHANNEL_ADC_HDSET, 0, &xoadc_fn, CHAN_PATH_TYPE6,
4734 ADC_CONFIG_TYPE2, ADC_CALIB_CONFIG_TYPE1, scale_default},
4735 {"chg_batt_amon", CHANNEL_ADC_BATT_AMON, 0, &xoadc_fn, CHAN_PATH_TYPE10,
4736 ADC_CONFIG_TYPE2, ADC_CALIB_CONFIG_TYPE1,
4737 scale_xtern_chgr_cur},
4738 {"msm_therm", CHANNEL_ADC_MSM_THERM, 0, &xoadc_fn, CHAN_PATH_TYPE8,
4739 ADC_CONFIG_TYPE2, ADC_CALIB_CONFIG_TYPE2, scale_msm_therm},
4740 {"batt_therm", CHANNEL_ADC_BATT_THERM, 0, &xoadc_fn, CHAN_PATH_TYPE7,
4741 ADC_CONFIG_TYPE2, ADC_CALIB_CONFIG_TYPE2, scale_batt_therm},
4742 {"batt_id", CHANNEL_ADC_BATT_ID, 0, &xoadc_fn, CHAN_PATH_TYPE9,
4743 ADC_CONFIG_TYPE2, ADC_CALIB_CONFIG_TYPE2, scale_default},
4744 {"ref_625mv", CHANNEL_ADC_625_REF, 0, &xoadc_fn, CHAN_PATH_TYPE15,
4745 ADC_CONFIG_TYPE2, ADC_CALIB_CONFIG_TYPE2, scale_default},
4746 {"ref_1250mv", CHANNEL_ADC_1250_REF, 0, &xoadc_fn, CHAN_PATH_TYPE13,
4747 ADC_CONFIG_TYPE2, ADC_CALIB_CONFIG_TYPE2, scale_default},
4748 {"ref_325mv", CHANNEL_ADC_325_REF, 0, &xoadc_fn, CHAN_PATH_TYPE14,
4749 ADC_CONFIG_TYPE2, ADC_CALIB_CONFIG_TYPE2, scale_default},
4750};
4751
4752static char *msm_adc_fluid_device_names[] = {
4753 "ADS_ADC1",
4754 "ADS_ADC2",
4755};
4756
4757static struct msm_adc_platform_data msm_adc_pdata = {
4758 .channel = msm_adc_channels_data,
4759 .num_chan_supported = ARRAY_SIZE(msm_adc_channels_data),
4760#if defined(CONFIG_I2C) && \
4761 (defined(CONFIG_GPIO_SX150X) || defined(CONFIG_GPIO_SX150X_MODULE))
4762 .adc_gpio_enable = msm_adc_gpio_expander_enable,
4763 .adc_gpio_disable = msm_adc_gpio_expander_disable,
4764 .adc_fluid_enable = msm_adc_gpio_configure_expander_enable,
4765 .adc_fluid_disable = msm_adc_gpio_configure_expander_disable,
4766#endif
4767};
4768
4769static struct platform_device msm_adc_device = {
4770 .name = "msm_adc",
4771 .id = -1,
4772 .dev = {
4773 .platform_data = &msm_adc_pdata,
4774 },
4775};
4776
4777static void pmic8058_xoadc_mpp_config(void)
4778{
4779 int rc;
4780
4781 rc = pm8901_mpp_config_digital_out(XOADC_MPP_4,
4782 PM8901_MPP_DIG_LEVEL_S4, PM_MPP_DOUT_CTL_LOW);
4783 if (rc)
4784 pr_err("%s: Config mpp4 on pmic 8901 failed\n", __func__);
4785
4786 rc = pm8058_mpp_config_analog_input(XOADC_MPP_3,
4787 PM_MPP_AIN_AMUX_CH5, PM_MPP_AOUT_CTL_DISABLE);
4788 if (rc)
4789 pr_err("%s: Config mpp3 on pmic 8058 failed\n", __func__);
4790
4791 rc = pm8058_mpp_config_analog_input(XOADC_MPP_5,
4792 PM_MPP_AIN_AMUX_CH9, PM_MPP_AOUT_CTL_DISABLE);
4793 if (rc)
4794 pr_err("%s: Config mpp5 on pmic 8058 failed\n", __func__);
4795
4796 rc = pm8058_mpp_config_analog_input(XOADC_MPP_7,
4797 PM_MPP_AIN_AMUX_CH6, PM_MPP_AOUT_CTL_DISABLE);
4798 if (rc)
4799 pr_err("%s: Config mpp7 on pmic 8058 failed\n", __func__);
4800
4801 rc = pm8058_mpp_config_analog_input(XOADC_MPP_8,
4802 PM_MPP_AIN_AMUX_CH8, PM_MPP_AOUT_CTL_DISABLE);
4803 if (rc)
4804 pr_err("%s: Config mpp8 on pmic 8058 failed\n", __func__);
4805
4806 rc = pm8058_mpp_config_analog_input(XOADC_MPP_10,
4807 PM_MPP_AIN_AMUX_CH7, PM_MPP_AOUT_CTL_DISABLE);
4808 if (rc)
4809 pr_err("%s: Config mpp10 on pmic 8058 failed\n", __func__);
4810}
4811
4812static struct regulator *vreg_ldo18_adc;
4813
4814static int pmic8058_xoadc_vreg_config(int on)
4815{
4816 int rc;
4817
4818 if (on) {
4819 rc = regulator_enable(vreg_ldo18_adc);
4820 if (rc)
4821 pr_err("%s: Enable of regulator ldo18_adc "
4822 "failed\n", __func__);
4823 } else {
4824 rc = regulator_disable(vreg_ldo18_adc);
4825 if (rc)
4826 pr_err("%s: Disable of regulator ldo18_adc "
4827 "failed\n", __func__);
4828 }
4829
4830 return rc;
4831}
4832
4833static int pmic8058_xoadc_vreg_setup(void)
4834{
4835 int rc;
4836
4837 vreg_ldo18_adc = regulator_get(NULL, "8058_l18");
4838 if (IS_ERR(vreg_ldo18_adc)) {
4839 printk(KERN_ERR "%s: vreg get failed (%ld)\n",
4840 __func__, PTR_ERR(vreg_ldo18_adc));
4841 rc = PTR_ERR(vreg_ldo18_adc);
4842 goto fail;
4843 }
4844
4845 rc = regulator_set_voltage(vreg_ldo18_adc, 2200000, 2200000);
4846 if (rc) {
4847 pr_err("%s: unable to set ldo18 voltage to 2.2V\n", __func__);
4848 goto fail;
4849 }
4850
4851 return rc;
4852fail:
4853 regulator_put(vreg_ldo18_adc);
4854 return rc;
4855}
4856
4857static void pmic8058_xoadc_vreg_shutdown(void)
4858{
4859 regulator_put(vreg_ldo18_adc);
4860}
4861
4862/* usec. For this ADC,
4863 * this time represents clk rate @ txco w/ 1024 decimation ratio.
4864 * Each channel has different configuration, thus at the time of starting
4865 * the conversion, xoadc will return actual conversion time
4866 * */
4867static struct adc_properties pm8058_xoadc_data = {
4868 .adc_reference = 2200, /* milli-voltage for this adc */
4869 .bitresolution = 15,
4870 .bipolar = 0,
4871 .conversiontime = 54,
4872};
4873
4874static struct xoadc_platform_data xoadc_pdata = {
4875 .xoadc_prop = &pm8058_xoadc_data,
4876 .xoadc_mpp_config = pmic8058_xoadc_mpp_config,
4877 .xoadc_vreg_set = pmic8058_xoadc_vreg_config,
4878 .xoadc_num = XOADC_PMIC_0,
4879 .xoadc_vreg_setup = pmic8058_xoadc_vreg_setup,
4880 .xoadc_vreg_shutdown = pmic8058_xoadc_vreg_shutdown,
4881};
4882#endif
4883
4884#ifdef CONFIG_MSM_SDIO_AL
4885
4886static unsigned mdm2ap_status = 140;
4887
4888static int configure_mdm2ap_status(int on)
4889{
4890 int ret = 0;
4891 if (on)
4892 ret = msm_gpiomux_get(mdm2ap_status);
4893 else
4894 ret = msm_gpiomux_put(mdm2ap_status);
4895
4896 if (ret)
4897 pr_err("%s: mdm2ap_status config failed, on = %d\n", __func__,
4898 on);
4899
4900 return ret;
4901}
4902
4903
4904static int get_mdm2ap_status(void)
4905{
4906 return gpio_get_value(mdm2ap_status);
4907}
4908
4909static struct sdio_al_platform_data sdio_al_pdata = {
4910 .config_mdm2ap_status = configure_mdm2ap_status,
4911 .get_mdm2ap_status = get_mdm2ap_status,
4912 .allow_sdioc_version_major_2 = 0,
Konstantin Dorfmanee2e3082011-08-16 15:12:01 +03004913 .peer_sdioc_version_minor = 0x0202,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004914 .peer_sdioc_version_major = 0x0004,
4915 .peer_sdioc_boot_version_minor = 0x0001,
4916 .peer_sdioc_boot_version_major = 0x0003
4917};
4918
4919struct platform_device msm_device_sdio_al = {
4920 .name = "msm_sdio_al",
4921 .id = -1,
4922 .dev = {
Maya Erez6862b142011-08-22 09:07:07 +03004923 .parent = &msm_charm_modem.dev,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004924 .platform_data = &sdio_al_pdata,
4925 },
4926};
4927
4928#endif /* CONFIG_MSM_SDIO_AL */
4929
4930static struct platform_device *charm_devices[] __initdata = {
4931 &msm_charm_modem,
4932#ifdef CONFIG_MSM_SDIO_AL
4933 &msm_device_sdio_al,
4934#endif
4935};
4936
Lei Zhou338cab82011-08-19 13:38:17 -04004937#ifdef CONFIG_SND_SOC_MSM8660_APQ
4938static struct platform_device *dragon_alsa_devices[] __initdata = {
4939 &msm_pcm,
4940 &msm_pcm_routing,
4941 &msm_cpudai0,
4942 &msm_cpudai1,
4943 &msm_cpudai_hdmi_rx,
4944 &msm_cpudai_bt_rx,
4945 &msm_cpudai_bt_tx,
4946 &msm_cpudai_fm_rx,
4947 &msm_cpudai_fm_tx,
4948 &msm_cpu_fe,
4949 &msm_stub_codec,
4950 &msm_lpa_pcm,
4951};
4952#endif
4953
4954static struct platform_device *asoc_devices[] __initdata = {
4955 &asoc_msm_pcm,
4956 &asoc_msm_dai0,
4957 &asoc_msm_dai1,
4958};
4959
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004960static struct platform_device *surf_devices[] __initdata = {
4961 &msm_device_smd,
4962 &msm_device_uart_dm12,
4963#ifdef CONFIG_I2C_QUP
4964 &msm_gsbi3_qup_i2c_device,
4965 &msm_gsbi4_qup_i2c_device,
4966 &msm_gsbi7_qup_i2c_device,
4967 &msm_gsbi8_qup_i2c_device,
4968 &msm_gsbi9_qup_i2c_device,
4969 &msm_gsbi12_qup_i2c_device,
4970#endif
4971#ifdef CONFIG_SERIAL_MSM_HS
4972 &msm_device_uart_dm1,
4973#endif
Anirudh Ghayal9d9cdc22011-10-10 17:17:07 +05304974#ifdef CONFIG_MSM_SSBI
4975 &msm_device_ssbi_pmic1,
4976#endif
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004977#ifdef CONFIG_I2C_SSBI
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004978 &msm_device_ssbi2,
4979 &msm_device_ssbi3,
4980#endif
4981#if defined(CONFIG_USB_PEHCI_HCD) || defined(CONFIG_USB_PEHCI_HCD_MODULE)
4982 &isp1763_device,
4983#endif
4984
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004985#if defined (CONFIG_MSM_8x60_VOIP)
4986 &asoc_msm_mvs,
4987 &asoc_mvs_dai0,
4988 &asoc_mvs_dai1,
4989#endif
Lei Zhou338cab82011-08-19 13:38:17 -04004990
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004991#if defined(CONFIG_USB_GADGET_MSM_72K) || defined(CONFIG_USB_EHCI_HCD)
4992 &msm_device_otg,
4993#endif
4994#ifdef CONFIG_USB_GADGET_MSM_72K
4995 &msm_device_gadget_peripheral,
4996#endif
4997#ifdef CONFIG_USB_G_ANDROID
4998 &android_usb_device,
4999#endif
5000#ifdef CONFIG_BATTERY_MSM
5001 &msm_batt_device,
5002#endif
5003#ifdef CONFIG_ANDROID_PMEM
5004 &android_pmem_device,
5005 &android_pmem_adsp_device,
5006 &android_pmem_audio_device,
5007 &android_pmem_smipool_device,
5008#endif
5009#ifdef CONFIG_MSM_ROTATOR
5010 &msm_rotator_device,
5011#endif
5012 &msm_fb_device,
5013 &msm_kgsl_3d0,
5014 &msm_kgsl_2d0,
5015 &msm_kgsl_2d1,
5016 &lcdc_samsung_panel_device,
Zhang Chang Ken3a8b8512011-08-04 18:41:39 -04005017#ifdef CONFIG_FB_MSM_LCDC_NT35582_WVGA
5018 &lcdc_nt35582_panel_device,
5019#endif
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005020#ifdef CONFIG_FB_MSM_LCDC_SAMSUNG_OLED_PT
5021 &lcdc_samsung_oled_panel_device,
5022#endif
5023#ifdef CONFIG_FB_MSM_LCDC_AUO_WVGA
5024 &lcdc_auo_wvga_panel_device,
5025#endif
5026#ifdef CONFIG_FB_MSM_HDMI_MSM_PANEL
5027 &hdmi_msm_device,
5028#endif /* CONFIG_FB_MSM_HDMI_MSM_PANEL */
5029#ifdef CONFIG_FB_MSM_MIPI_DSI
5030 &mipi_dsi_toshiba_panel_device,
5031 &mipi_dsi_novatek_panel_device,
5032#endif
5033#ifdef CONFIG_MSM_CAMERA
5034#ifdef CONFIG_MT9E013
5035 &msm_camera_sensor_mt9e013,
5036#endif
5037#ifdef CONFIG_IMX074
5038 &msm_camera_sensor_imx074,
5039#endif
5040#ifdef CONFIG_WEBCAM_OV7692
5041 &msm_camera_sensor_webcam_ov7692,
5042#endif
5043#ifdef CONFIG_WEBCAM_OV9726
5044 &msm_camera_sensor_webcam_ov9726,
5045#endif
5046#ifdef CONFIG_QS_S5K4E1
5047 &msm_camera_sensor_qs_s5k4e1,
5048#endif
Jilai Wang971f97f2011-07-13 14:25:25 -04005049#ifdef CONFIG_VX6953
5050 &msm_camera_sensor_vx6953,
5051#endif
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005052#endif
5053#ifdef CONFIG_MSM_GEMINI
5054 &msm_gemini_device,
5055#endif
5056#ifdef CONFIG_MSM_VPE
5057 &msm_vpe_device,
5058#endif
5059
5060#if defined(CONFIG_MSM_RPM_LOG) || defined(CONFIG_MSM_RPM_LOG_MODULE)
5061 &msm_rpm_log_device,
5062#endif
5063#if defined(CONFIG_MSM_RPM_STATS_LOG)
5064 &msm_rpm_stat_device,
5065#endif
5066 &msm_device_vidc,
5067#if (defined(CONFIG_MARIMBA_CORE)) && \
5068 (defined(CONFIG_MSM_BT_POWER) || defined(CONFIG_MSM_BT_POWER_MODULE))
5069 &msm_bt_power_device,
5070#endif
5071#ifdef CONFIG_SENSORS_MSM_ADC
5072 &msm_adc_device,
5073#endif
David Collins6f032ba2011-08-31 14:08:15 -07005074 &rpm_regulator_device,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005075
5076#if defined(CONFIG_CRYPTO_DEV_QCRYPTO) || \
5077 defined(CONFIG_CRYPTO_DEV_QCRYPTO_MODULE)
5078 &qcrypto_device,
5079#endif
5080
5081#if defined(CONFIG_CRYPTO_DEV_QCEDEV) || \
5082 defined(CONFIG_CRYPTO_DEV_QCEDEV_MODULE)
5083 &qcedev_device,
5084#endif
5085
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005086
5087#if defined(CONFIG_TSIF) || defined(CONFIG_TSIF_MODULE)
5088#ifdef CONFIG_MSM_USE_TSIF1
5089 &msm_device_tsif[1],
5090#else
5091 &msm_device_tsif[0],
5092#endif /* CONFIG_MSM_USE_TSIF1 */
5093#endif /* CONFIG_TSIF */
5094
5095#ifdef CONFIG_HW_RANDOM_MSM
5096 &msm_device_rng,
5097#endif
5098
5099 &msm_tsens_device,
Praveen Chidambaram043f4ce2011-08-02 09:37:59 -06005100 &msm_rpm_device,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005101
5102};
5103
5104static struct memtype_reserve msm8x60_reserve_table[] __initdata = {
5105 /* Kernel SMI memory pool for video core, used for firmware */
5106 /* and encoder, decoder scratch buffers */
5107 /* Kernel SMI memory pool should always precede the user space */
5108 /* SMI memory pool, as the video core will use offset address */
5109 /* from the Firmware base */
5110 [MEMTYPE_SMI_KERNEL] = {
5111 .start = KERNEL_SMI_BASE,
5112 .limit = KERNEL_SMI_SIZE,
5113 .size = KERNEL_SMI_SIZE,
5114 .flags = MEMTYPE_FLAGS_FIXED,
5115 },
5116 /* User space SMI memory pool for video core */
5117 /* used for encoder, decoder input & output buffers */
5118 [MEMTYPE_SMI] = {
5119 .start = USER_SMI_BASE,
5120 .limit = USER_SMI_SIZE,
5121 .flags = MEMTYPE_FLAGS_FIXED,
5122 },
5123 [MEMTYPE_EBI0] = {
5124 .flags = MEMTYPE_FLAGS_1M_ALIGN,
5125 },
5126 [MEMTYPE_EBI1] = {
5127 .flags = MEMTYPE_FLAGS_1M_ALIGN,
5128 },
5129};
5130
5131static void __init size_pmem_devices(void)
5132{
5133#ifdef CONFIG_ANDROID_PMEM
5134 android_pmem_adsp_pdata.size = pmem_adsp_size;
5135 android_pmem_smipool_pdata.size = MSM_PMEM_SMIPOOL_SIZE;
5136 android_pmem_audio_pdata.size = MSM_PMEM_AUDIO_SIZE;
5137 android_pmem_pdata.size = pmem_sf_size;
5138#endif
5139}
5140
5141static void __init reserve_memory_for(struct android_pmem_platform_data *p)
5142{
5143 msm8x60_reserve_table[p->memory_type].size += p->size;
5144}
5145
5146static void __init reserve_pmem_memory(void)
5147{
5148#ifdef CONFIG_ANDROID_PMEM
5149 reserve_memory_for(&android_pmem_adsp_pdata);
5150 reserve_memory_for(&android_pmem_smipool_pdata);
5151 reserve_memory_for(&android_pmem_audio_pdata);
5152 reserve_memory_for(&android_pmem_pdata);
5153 msm8x60_reserve_table[MEMTYPE_EBI1].size += pmem_kernel_ebi1_size;
5154#endif
5155}
5156
5157static void __init msm8x60_calculate_reserve_sizes(void)
5158{
5159 size_pmem_devices();
5160 reserve_pmem_memory();
5161}
5162
5163static int msm8x60_paddr_to_memtype(unsigned int paddr)
5164{
5165 if (paddr >= 0x40000000 && paddr < 0x60000000)
5166 return MEMTYPE_EBI1;
5167 if (paddr >= 0x38000000 && paddr < 0x40000000)
5168 return MEMTYPE_SMI;
5169 return MEMTYPE_NONE;
5170}
5171
5172static struct reserve_info msm8x60_reserve_info __initdata = {
5173 .memtype_reserve_table = msm8x60_reserve_table,
5174 .calculate_reserve_sizes = msm8x60_calculate_reserve_sizes,
5175 .paddr_to_memtype = msm8x60_paddr_to_memtype,
5176};
5177
5178static void __init msm8x60_reserve(void)
5179{
5180 reserve_info = &msm8x60_reserve_info;
5181 msm_reserve();
5182}
5183
5184#define EXT_CHG_VALID_MPP 10
5185#define EXT_CHG_VALID_MPP_2 11
5186
5187#ifdef CONFIG_ISL9519_CHARGER
5188static int isl_detection_setup(void)
5189{
5190 int ret = 0;
5191
5192 ret = pm8058_mpp_config_digital_in(EXT_CHG_VALID_MPP,
5193 PM8058_MPP_DIG_LEVEL_S3,
5194 PM_MPP_DIN_TO_INT);
5195 ret |= pm8058_mpp_config_bi_dir(EXT_CHG_VALID_MPP_2,
5196 PM8058_MPP_DIG_LEVEL_S3,
5197 PM_MPP_BI_PULLUP_10KOHM
5198 );
5199 return ret;
5200}
5201
5202static struct isl_platform_data isl_data __initdata = {
5203 .chgcurrent = 700,
5204 .valid_n_gpio = PM8058_MPP_PM_TO_SYS(10),
5205 .chg_detection_config = isl_detection_setup,
5206 .max_system_voltage = 4200,
5207 .min_system_voltage = 3200,
5208 .term_current = 120,
5209 .input_current = 2048,
5210};
5211
5212static struct i2c_board_info isl_charger_i2c_info[] __initdata = {
5213 {
5214 I2C_BOARD_INFO("isl9519q", 0x9),
5215 .irq = PM8058_CBLPWR_IRQ(PM8058_IRQ_BASE),
5216 .platform_data = &isl_data,
5217 },
5218};
5219#endif
5220
5221#if defined(CONFIG_SMB137B_CHARGER) || defined(CONFIG_SMB137B_CHARGER_MODULE)
5222static int smb137b_detection_setup(void)
5223{
5224 int ret = 0;
5225
5226 ret = pm8058_mpp_config_digital_in(EXT_CHG_VALID_MPP,
5227 PM8058_MPP_DIG_LEVEL_S3,
5228 PM_MPP_DIN_TO_INT);
5229 ret |= pm8058_mpp_config_bi_dir(EXT_CHG_VALID_MPP_2,
5230 PM8058_MPP_DIG_LEVEL_S3,
5231 PM_MPP_BI_PULLUP_10KOHM);
5232 return ret;
5233}
5234
5235static struct smb137b_platform_data smb137b_data __initdata = {
5236 .chg_detection_config = smb137b_detection_setup,
5237 .valid_n_gpio = PM8058_MPP_PM_TO_SYS(10),
5238 .batt_mah_rating = 950,
5239};
5240
5241static struct i2c_board_info smb137b_charger_i2c_info[] __initdata = {
5242 {
5243 I2C_BOARD_INFO("smb137b", 0x08),
5244 .irq = PM8058_CBLPWR_IRQ(PM8058_IRQ_BASE),
5245 .platform_data = &smb137b_data,
5246 },
5247};
5248#endif
5249
5250#ifdef CONFIG_PMIC8058
5251#define PMIC_GPIO_SDC3_DET 22
5252
5253static int pm8058_gpios_init(void)
5254{
5255 int i;
5256 int rc;
5257 struct pm8058_gpio_cfg {
5258 int gpio;
5259 struct pm8058_gpio cfg;
5260 };
5261
5262 struct pm8058_gpio_cfg gpio_cfgs[] = {
5263 { /* FFA ethernet */
5264 6,
5265 {
5266 .direction = PM_GPIO_DIR_IN,
5267 .pull = PM_GPIO_PULL_DN,
5268 .vin_sel = 2,
5269 .function = PM_GPIO_FUNC_NORMAL,
5270 .inv_int_pol = 0,
5271 },
5272 },
5273#ifdef CONFIG_MMC_MSM_CARD_HW_DETECTION
5274 {
5275 PMIC_GPIO_SDC3_DET - 1,
5276 {
5277 .direction = PM_GPIO_DIR_IN,
5278 .pull = PM_GPIO_PULL_UP_30,
5279 .vin_sel = 2,
5280 .function = PM_GPIO_FUNC_NORMAL,
5281 .inv_int_pol = 0,
5282 },
5283 },
5284#endif
5285 { /* core&surf gpio expander */
5286 UI_INT1_N,
5287 {
5288 .direction = PM_GPIO_DIR_IN,
5289 .pull = PM_GPIO_PULL_NO,
5290 .vin_sel = PM_GPIO_VIN_S3,
5291 .function = PM_GPIO_FUNC_NORMAL,
5292 .inv_int_pol = 0,
5293 },
5294 },
5295 { /* docking gpio expander */
5296 UI_INT2_N,
5297 {
5298 .direction = PM_GPIO_DIR_IN,
5299 .pull = PM_GPIO_PULL_NO,
5300 .vin_sel = PM_GPIO_VIN_S3,
5301 .function = PM_GPIO_FUNC_NORMAL,
5302 .inv_int_pol = 0,
5303 },
5304 },
5305 { /* FHA/keypad gpio expanders */
5306 UI_INT3_N,
5307 {
5308 .direction = PM_GPIO_DIR_IN,
5309 .pull = PM_GPIO_PULL_NO,
5310 .vin_sel = PM_GPIO_VIN_S3,
5311 .function = PM_GPIO_FUNC_NORMAL,
5312 .inv_int_pol = 0,
5313 },
5314 },
5315 { /* TouchDisc Interrupt */
5316 5,
5317 {
5318 .direction = PM_GPIO_DIR_IN,
5319 .pull = PM_GPIO_PULL_UP_1P5,
5320 .vin_sel = 2,
5321 .function = PM_GPIO_FUNC_NORMAL,
5322 .inv_int_pol = 0,
5323 }
5324 },
5325 { /* Timpani Reset */
5326 20,
5327 {
5328 .direction = PM_GPIO_DIR_OUT,
5329 .output_value = 1,
5330 .output_buffer = PM_GPIO_OUT_BUF_CMOS,
5331 .pull = PM_GPIO_PULL_DN,
5332 .out_strength = PM_GPIO_STRENGTH_HIGH,
5333 .function = PM_GPIO_FUNC_NORMAL,
5334 .vin_sel = 2,
5335 .inv_int_pol = 0,
5336 }
5337 },
5338 { /* PMIC ID interrupt */
5339 36,
5340 {
5341 .direction = PM_GPIO_DIR_IN,
5342 .pull = PM_GPIO_PULL_UP_1P5,
5343 .function = PM_GPIO_FUNC_NORMAL,
5344 .vin_sel = 2,
5345 .inv_int_pol = 0,
5346 }
5347 },
5348 };
5349
5350#if defined(CONFIG_HAPTIC_ISA1200) || \
5351 defined(CONFIG_HAPTIC_ISA1200_MODULE)
5352
5353 struct pm8058_gpio_cfg en_hap_gpio_cfg = {
5354 PMIC_GPIO_HAP_ENABLE,
5355 {
5356 .direction = PM_GPIO_DIR_OUT,
5357 .pull = PM_GPIO_PULL_NO,
5358 .out_strength = PM_GPIO_STRENGTH_HIGH,
5359 .function = PM_GPIO_FUNC_NORMAL,
5360 .inv_int_pol = 0,
5361 .vin_sel = 2,
5362 .output_buffer = PM_GPIO_OUT_BUF_CMOS,
5363 .output_value = 0,
5364 }
5365
5366 };
5367#endif
5368
5369#if defined(CONFIG_PMIC8058_OTHC) || defined(CONFIG_PMIC8058_OTHC_MODULE)
5370 struct pm8058_gpio_cfg line_in_gpio_cfg = {
5371 18,
5372 {
5373 .direction = PM_GPIO_DIR_IN,
5374 .pull = PM_GPIO_PULL_UP_1P5,
5375 .vin_sel = 2,
5376 .function = PM_GPIO_FUNC_NORMAL,
5377 .inv_int_pol = 0,
5378 }
5379 };
5380#endif
5381
5382#if defined(CONFIG_QS_S5K4E1)
5383 {
5384 struct pm8058_gpio_cfg qs_hc37_cam_pd_gpio_cfg = {
5385 26,
5386 {
5387 .direction = PM_GPIO_DIR_OUT,
5388 .output_value = 0,
5389 .output_buffer = PM_GPIO_OUT_BUF_CMOS,
5390 .pull = PM_GPIO_PULL_DN,
5391 .out_strength = PM_GPIO_STRENGTH_HIGH,
5392 .function = PM_GPIO_FUNC_NORMAL,
5393 .vin_sel = 2,
5394 .inv_int_pol = 0,
5395 }
5396 };
5397#endif
Zhang Chang Ken3a8b8512011-08-04 18:41:39 -04005398#ifdef CONFIG_FB_MSM_LCDC_NT35582_WVGA
5399 struct pm8058_gpio_cfg pmic_lcdc_nt35582_gpio_cfg = {
5400 GPIO_NT35582_BL_EN_HW_PIN - 1,
5401 {
5402 .direction = PM_GPIO_DIR_OUT,
5403 .output_buffer = PM_GPIO_OUT_BUF_CMOS,
5404 .output_value = 1,
5405 .pull = PM_GPIO_PULL_UP_30,
5406 /* 2.9V PM_GPIO_VIN_L2, which gives 2.6V */
5407 .vin_sel = PM_GPIO_VIN_L5,
5408 .out_strength = PM_GPIO_STRENGTH_HIGH,
5409 .function = PM_GPIO_FUNC_NORMAL,
5410 .inv_int_pol = 0,
5411 }
5412 };
5413#endif
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005414#if defined(CONFIG_HAPTIC_ISA1200) || \
5415 defined(CONFIG_HAPTIC_ISA1200_MODULE)
5416 if (machine_is_msm8x60_fluid()) {
5417 rc = pm8058_gpio_config(en_hap_gpio_cfg.gpio,
5418 &en_hap_gpio_cfg.cfg);
5419 if (rc < 0) {
5420 pr_err("%s pmic haptics gpio config failed\n",
5421 __func__);
5422 return rc;
5423 }
5424 }
5425#endif
5426
5427#if defined(CONFIG_PMIC8058_OTHC) || defined(CONFIG_PMIC8058_OTHC_MODULE)
5428 /* Line_in only for 8660 ffa & surf */
5429 if (machine_is_msm8x60_ffa() || machine_is_msm8x60_surf() ||
Zhang Chang Ken6baadf02011-08-05 09:48:15 -04005430 machine_is_msm8x60_fusion() || machine_is_msm8x60_dragon() ||
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005431 machine_is_msm8x60_fusn_ffa()) {
5432 rc = pm8058_gpio_config(line_in_gpio_cfg.gpio,
5433 &line_in_gpio_cfg.cfg);
5434 if (rc < 0) {
5435 pr_err("%s pmic line_in gpio config failed\n",
5436 __func__);
5437 return rc;
5438 }
5439 }
5440#endif
5441
Zhang Chang Ken3a8b8512011-08-04 18:41:39 -04005442#ifdef CONFIG_FB_MSM_LCDC_NT35582_WVGA
5443 if (machine_is_msm8x60_dragon()) {
5444 rc = pm8058_gpio_config(pmic_lcdc_nt35582_gpio_cfg.gpio,
5445 &pmic_lcdc_nt35582_gpio_cfg.cfg);
5446 if (rc < 0) {
5447 pr_err("%s pmic gpio config failed\n", __func__);
5448 return rc;
5449 }
5450 }
5451#endif
5452
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005453#if defined(CONFIG_QS_S5K4E1)
5454 /* qs_cam_hc37_cam_pd only for 8660 fluid qs camera*/
5455 if (machine_is_msm8x60_fluid()) {
5456 rc = pm8058_gpio_config(qs_hc37_cam_pd_gpio_cfg.gpio,
5457 &qs_hc37_cam_pd_gpio_cfg.cfg);
5458 if (rc < 0) {
5459 pr_err("%s pmic qs_hc37_cam_pd gpio config failed\n",
5460 __func__);
5461 return rc;
5462 }
5463 }
5464 }
5465#endif
5466
5467 for (i = 0; i < ARRAY_SIZE(gpio_cfgs); ++i) {
5468 rc = pm8058_gpio_config(gpio_cfgs[i].gpio,
5469 &gpio_cfgs[i].cfg);
5470 if (rc < 0) {
5471 pr_err("%s pmic gpio config failed\n",
5472 __func__);
5473 return rc;
5474 }
5475 }
5476
5477 return 0;
5478}
5479
5480static const unsigned int ffa_keymap[] = {
5481 KEY(0, 0, KEY_FN_F1), /* LS - PUSH1 */
5482 KEY(0, 1, KEY_UP), /* NAV - UP */
5483 KEY(0, 2, KEY_LEFT), /* NAV - LEFT */
5484 KEY(0, 3, KEY_VOLUMEUP), /* Shuttle SW_UP */
5485
5486 KEY(1, 0, KEY_FN_F2), /* LS - PUSH2 */
5487 KEY(1, 1, KEY_RIGHT), /* NAV - RIGHT */
5488 KEY(1, 2, KEY_DOWN), /* NAV - DOWN */
5489 KEY(1, 3, KEY_VOLUMEDOWN),
5490
5491 KEY(2, 3, KEY_ENTER), /* SW_PUSH key */
5492
5493 KEY(4, 0, KEY_CAMERA_FOCUS), /* RS - PUSH1 */
5494 KEY(4, 1, KEY_UP), /* USER_UP */
5495 KEY(4, 2, KEY_LEFT), /* USER_LEFT */
5496 KEY(4, 3, KEY_HOME), /* Right switch: MIC Bd */
5497 KEY(4, 4, KEY_FN_F3), /* Reserved MIC */
5498
5499 KEY(5, 0, KEY_CAMERA), /* RS - PUSH2 */
5500 KEY(5, 1, KEY_RIGHT), /* USER_RIGHT */
5501 KEY(5, 2, KEY_DOWN), /* USER_DOWN */
5502 KEY(5, 3, KEY_BACK), /* Left switch: MIC */
5503 KEY(5, 4, KEY_MENU), /* Center switch: MIC */
5504};
5505
Zhang Chang Ken683be172011-08-10 17:45:34 -04005506static const unsigned int dragon_keymap[] = {
5507 KEY(0, 0, KEY_MENU),
5508 KEY(0, 2, KEY_1),
5509 KEY(0, 3, KEY_4),
5510 KEY(0, 4, KEY_7),
5511
5512 KEY(1, 0, KEY_UP),
5513 KEY(1, 1, KEY_LEFT),
5514 KEY(1, 2, KEY_DOWN),
5515 KEY(1, 3, KEY_5),
5516 KEY(1, 4, KEY_8),
5517
5518 KEY(2, 0, KEY_HOME),
5519 KEY(2, 1, KEY_REPLY),
5520 KEY(2, 2, KEY_2),
5521 KEY(2, 3, KEY_6),
5522 KEY(2, 4, KEY_0),
5523
5524 KEY(3, 0, KEY_VOLUMEUP),
5525 KEY(3, 1, KEY_RIGHT),
5526 KEY(3, 2, KEY_3),
5527 KEY(3, 3, KEY_9),
5528 KEY(3, 4, KEY_SWITCHVIDEOMODE),
5529
5530 KEY(4, 0, KEY_VOLUMEDOWN),
5531 KEY(4, 1, KEY_BACK),
5532 KEY(4, 2, KEY_CAMERA),
5533 KEY(4, 3, KEY_KBDILLUMTOGGLE),
5534};
5535
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005536static struct resource resources_keypad[] = {
5537 {
5538 .start = PM8058_KEYPAD_IRQ(PM8058_IRQ_BASE),
5539 .end = PM8058_KEYPAD_IRQ(PM8058_IRQ_BASE),
5540 .flags = IORESOURCE_IRQ,
5541 },
5542 {
5543 .start = PM8058_KEYSTUCK_IRQ(PM8058_IRQ_BASE),
5544 .end = PM8058_KEYSTUCK_IRQ(PM8058_IRQ_BASE),
5545 .flags = IORESOURCE_IRQ,
5546 },
5547};
5548
5549static struct matrix_keymap_data ffa_keymap_data = {
5550 .keymap_size = ARRAY_SIZE(ffa_keymap),
5551 .keymap = ffa_keymap,
5552};
5553
5554static struct pmic8058_keypad_data ffa_keypad_data = {
5555 .input_name = "ffa-keypad",
5556 .input_phys_device = "ffa-keypad/input0",
5557 .num_rows = 6,
5558 .num_cols = 5,
5559 .rows_gpio_start = 8,
5560 .cols_gpio_start = 0,
5561 .debounce_ms = {8, 10},
5562 .scan_delay_ms = 32,
5563 .row_hold_ns = 91500,
5564 .wakeup = 1,
5565 .keymap_data = &ffa_keymap_data,
5566};
5567
Zhang Chang Ken683be172011-08-10 17:45:34 -04005568static struct matrix_keymap_data dragon_keymap_data = {
5569 .keymap_size = ARRAY_SIZE(dragon_keymap),
5570 .keymap = dragon_keymap,
5571};
5572
5573static struct pmic8058_keypad_data dragon_keypad_data = {
5574 .input_name = "dragon-keypad",
5575 .input_phys_device = "dragon-keypad/input0",
5576 .num_rows = 6,
5577 .num_cols = 5,
5578 .rows_gpio_start = 8,
5579 .cols_gpio_start = 0,
5580 .debounce_ms = {8, 10},
5581 .scan_delay_ms = 32,
5582 .row_hold_ns = 91500,
5583 .wakeup = 1,
5584 .keymap_data = &dragon_keymap_data,
5585};
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005586static const unsigned int fluid_keymap[] = {
5587 KEY(0, 0, KEY_FN_F1), /* LS - PUSH1 */
5588 KEY(0, 1, KEY_UP), /* NAV - UP */
5589 KEY(0, 2, KEY_LEFT), /* NAV - LEFT */
5590 KEY(0, 3, KEY_VOLUMEDOWN), /* Shuttle SW_UP */
5591
5592 KEY(1, 0, KEY_FN_F2), /* LS - PUSH2 */
5593 KEY(1, 1, KEY_RIGHT), /* NAV - RIGHT */
5594 KEY(1, 2, KEY_DOWN), /* NAV - DOWN */
5595 KEY(1, 3, KEY_VOLUMEUP),
5596
5597 KEY(2, 3, KEY_ENTER), /* SW_PUSH key */
5598
5599 KEY(4, 0, KEY_CAMERA_FOCUS), /* RS - PUSH1 */
5600 KEY(4, 1, KEY_UP), /* USER_UP */
5601 KEY(4, 2, KEY_LEFT), /* USER_LEFT */
5602 KEY(4, 3, KEY_HOME), /* Right switch: MIC Bd */
5603 KEY(4, 4, KEY_FN_F3), /* Reserved MIC */
5604
Jilai Wang9a895102011-07-12 14:00:35 -04005605 KEY(5, 0, KEY_CAMERA), /* RS - PUSH2 */
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005606 KEY(5, 1, KEY_RIGHT), /* USER_RIGHT */
5607 KEY(5, 2, KEY_DOWN), /* USER_DOWN */
5608 KEY(5, 3, KEY_BACK), /* Left switch: MIC */
5609 KEY(5, 4, KEY_MENU), /* Center switch: MIC */
5610};
5611
5612static struct matrix_keymap_data fluid_keymap_data = {
5613 .keymap_size = ARRAY_SIZE(fluid_keymap),
5614 .keymap = fluid_keymap,
5615};
5616
5617static struct pmic8058_keypad_data fluid_keypad_data = {
5618 .input_name = "fluid-keypad",
5619 .input_phys_device = "fluid-keypad/input0",
5620 .num_rows = 6,
5621 .num_cols = 5,
5622 .rows_gpio_start = 8,
5623 .cols_gpio_start = 0,
5624 .debounce_ms = {8, 10},
5625 .scan_delay_ms = 32,
5626 .row_hold_ns = 91500,
5627 .wakeup = 1,
5628 .keymap_data = &fluid_keymap_data,
5629};
5630
5631static struct resource resources_pwrkey[] = {
5632 {
5633 .start = PM8058_PWRKEY_REL_IRQ(PM8058_IRQ_BASE),
5634 .end = PM8058_PWRKEY_REL_IRQ(PM8058_IRQ_BASE),
5635 .flags = IORESOURCE_IRQ,
5636 },
5637 {
5638 .start = PM8058_PWRKEY_PRESS_IRQ(PM8058_IRQ_BASE),
5639 .end = PM8058_PWRKEY_PRESS_IRQ(PM8058_IRQ_BASE),
5640 .flags = IORESOURCE_IRQ,
5641 },
5642};
5643
5644static struct pmic8058_pwrkey_pdata pwrkey_pdata = {
5645 .pull_up = 1,
5646 .kpd_trigger_delay_us = 970,
5647 .wakeup = 1,
5648 .pwrkey_time_ms = 500,
5649};
5650
5651static struct pmic8058_vibrator_pdata pmic_vib_pdata = {
5652 .initial_vibrate_ms = 500,
5653 .level_mV = 3000,
5654 .max_timeout_ms = 15000,
5655};
5656
5657#if defined(CONFIG_PMIC8058_OTHC) || defined(CONFIG_PMIC8058_OTHC_MODULE)
5658#define PM8058_OTHC_CNTR_BASE0 0xA0
5659#define PM8058_OTHC_CNTR_BASE1 0x134
5660#define PM8058_OTHC_CNTR_BASE2 0x137
5661#define PM8058_LINE_IN_DET_GPIO PM8058_GPIO_PM_TO_SYS(18)
5662
5663static struct othc_accessory_info othc_accessories[] = {
5664 {
5665 .accessory = OTHC_SVIDEO_OUT,
5666 .detect_flags = OTHC_MICBIAS_DETECT | OTHC_SWITCH_DETECT
5667 | OTHC_ADC_DETECT,
5668 .key_code = SW_VIDEOOUT_INSERT,
5669 .enabled = false,
5670 .adc_thres = {
5671 .min_threshold = 20,
5672 .max_threshold = 40,
5673 },
5674 },
5675 {
5676 .accessory = OTHC_ANC_HEADPHONE,
5677 .detect_flags = OTHC_MICBIAS_DETECT | OTHC_GPIO_DETECT |
5678 OTHC_SWITCH_DETECT,
5679 .gpio = PM8058_LINE_IN_DET_GPIO,
5680 .active_low = 1,
5681 .key_code = SW_HEADPHONE_INSERT,
5682 .enabled = true,
5683 },
5684 {
5685 .accessory = OTHC_ANC_HEADSET,
5686 .detect_flags = OTHC_MICBIAS_DETECT | OTHC_GPIO_DETECT,
5687 .gpio = PM8058_LINE_IN_DET_GPIO,
5688 .active_low = 1,
5689 .key_code = SW_HEADPHONE_INSERT,
5690 .enabled = true,
5691 },
5692 {
5693 .accessory = OTHC_HEADPHONE,
5694 .detect_flags = OTHC_MICBIAS_DETECT | OTHC_SWITCH_DETECT,
5695 .key_code = SW_HEADPHONE_INSERT,
5696 .enabled = true,
5697 },
5698 {
5699 .accessory = OTHC_MICROPHONE,
5700 .detect_flags = OTHC_GPIO_DETECT,
5701 .gpio = PM8058_LINE_IN_DET_GPIO,
5702 .active_low = 1,
5703 .key_code = SW_MICROPHONE_INSERT,
5704 .enabled = true,
5705 },
5706 {
5707 .accessory = OTHC_HEADSET,
5708 .detect_flags = OTHC_MICBIAS_DETECT,
5709 .key_code = SW_HEADPHONE_INSERT,
5710 .enabled = true,
5711 },
5712};
5713
5714static struct othc_switch_info switch_info[] = {
5715 {
5716 .min_adc_threshold = 0,
5717 .max_adc_threshold = 100,
5718 .key_code = KEY_PLAYPAUSE,
5719 },
5720 {
5721 .min_adc_threshold = 100,
5722 .max_adc_threshold = 200,
5723 .key_code = KEY_REWIND,
5724 },
5725 {
5726 .min_adc_threshold = 200,
5727 .max_adc_threshold = 500,
5728 .key_code = KEY_FASTFORWARD,
5729 },
5730};
5731
5732static struct othc_n_switch_config switch_config = {
5733 .voltage_settling_time_ms = 0,
5734 .num_adc_samples = 3,
5735 .adc_channel = CHANNEL_ADC_HDSET,
5736 .switch_info = switch_info,
5737 .num_keys = ARRAY_SIZE(switch_info),
5738 .default_sw_en = true,
5739 .default_sw_idx = 0,
5740};
5741
5742static struct hsed_bias_config hsed_bias_config = {
5743 /* HSED mic bias config info */
5744 .othc_headset = OTHC_HEADSET_NO,
5745 .othc_lowcurr_thresh_uA = 100,
5746 .othc_highcurr_thresh_uA = 600,
5747 .othc_hyst_prediv_us = 7800,
5748 .othc_period_clkdiv_us = 62500,
5749 .othc_hyst_clk_us = 121000,
5750 .othc_period_clk_us = 312500,
5751 .othc_wakeup = 1,
5752};
5753
5754static struct othc_hsed_config hsed_config_1 = {
5755 .hsed_bias_config = &hsed_bias_config,
5756 /*
5757 * The detection delay and switch reporting delay are
5758 * required to encounter a hardware bug (spurious switch
5759 * interrupts on slow insertion/removal of the headset).
5760 * This will introduce a delay in reporting the accessory
5761 * insertion and removal to the userspace.
5762 */
5763 .detection_delay_ms = 1500,
5764 /* Switch info */
5765 .switch_debounce_ms = 1500,
5766 .othc_support_n_switch = false,
5767 .switch_config = &switch_config,
5768 .ir_gpio = -1,
5769 /* Accessory info */
5770 .accessories_support = true,
5771 .accessories = othc_accessories,
5772 .othc_num_accessories = ARRAY_SIZE(othc_accessories),
5773};
5774
5775static struct othc_regulator_config othc_reg = {
5776 .regulator = "8058_l5",
5777 .max_uV = 2850000,
5778 .min_uV = 2850000,
5779};
5780
5781/* MIC_BIAS0 is configured as normal MIC BIAS */
5782static struct pmic8058_othc_config_pdata othc_config_pdata_0 = {
5783 .micbias_select = OTHC_MICBIAS_0,
5784 .micbias_capability = OTHC_MICBIAS,
5785 .micbias_enable = OTHC_SIGNAL_OFF,
5786 .micbias_regulator = &othc_reg,
5787};
5788
5789/* MIC_BIAS1 is configured as HSED_BIAS for OTHC */
5790static struct pmic8058_othc_config_pdata othc_config_pdata_1 = {
5791 .micbias_select = OTHC_MICBIAS_1,
5792 .micbias_capability = OTHC_MICBIAS_HSED,
5793 .micbias_enable = OTHC_SIGNAL_PWM_TCXO,
5794 .micbias_regulator = &othc_reg,
5795 .hsed_config = &hsed_config_1,
5796 .hsed_name = "8660_handset",
5797};
5798
5799/* MIC_BIAS2 is configured as normal MIC BIAS */
5800static struct pmic8058_othc_config_pdata othc_config_pdata_2 = {
5801 .micbias_select = OTHC_MICBIAS_2,
5802 .micbias_capability = OTHC_MICBIAS,
5803 .micbias_enable = OTHC_SIGNAL_OFF,
5804 .micbias_regulator = &othc_reg,
5805};
5806
5807static struct resource resources_othc_0[] = {
5808 {
5809 .name = "othc_base",
5810 .start = PM8058_OTHC_CNTR_BASE0,
5811 .end = PM8058_OTHC_CNTR_BASE0,
5812 .flags = IORESOURCE_IO,
5813 },
5814};
5815
5816static struct resource resources_othc_1[] = {
5817 {
5818 .start = PM8058_SW_1_IRQ(PM8058_IRQ_BASE),
5819 .end = PM8058_SW_1_IRQ(PM8058_IRQ_BASE),
5820 .flags = IORESOURCE_IRQ,
5821 },
5822 {
5823 .start = PM8058_IR_1_IRQ(PM8058_IRQ_BASE),
5824 .end = PM8058_IR_1_IRQ(PM8058_IRQ_BASE),
5825 .flags = IORESOURCE_IRQ,
5826 },
5827 {
5828 .name = "othc_base",
5829 .start = PM8058_OTHC_CNTR_BASE1,
5830 .end = PM8058_OTHC_CNTR_BASE1,
5831 .flags = IORESOURCE_IO,
5832 },
5833};
5834
5835static struct resource resources_othc_2[] = {
5836 {
5837 .name = "othc_base",
5838 .start = PM8058_OTHC_CNTR_BASE2,
5839 .end = PM8058_OTHC_CNTR_BASE2,
5840 .flags = IORESOURCE_IO,
5841 },
5842};
5843
5844static void __init msm8x60_init_pm8058_othc(void)
5845{
5846 int i;
5847
5848 if (SOCINFO_VERSION_MAJOR(socinfo_get_version()) == 2 ||
5849 machine_is_msm8x60_fluid() || machine_is_msm8x60_fusion() ||
5850 machine_is_msm8x60_fusn_ffa()) {
5851 /* 3-switch headset supported only by V2 FFA and FLUID */
5852 hsed_config_1.accessories_adc_support = true,
5853 /* ADC based accessory detection works only on V2 and FLUID */
5854 hsed_config_1.accessories_adc_channel = CHANNEL_ADC_HDSET,
5855 hsed_config_1.othc_support_n_switch = true;
5856 }
5857
5858 /* IR GPIO is absent on FLUID */
5859 if (machine_is_msm8x60_fluid())
5860 hsed_config_1.ir_gpio = -1;
5861
5862 for (i = 0; i < ARRAY_SIZE(othc_accessories); i++) {
5863 if (machine_is_msm8x60_fluid()) {
5864 switch (othc_accessories[i].accessory) {
5865 case OTHC_ANC_HEADPHONE:
5866 case OTHC_ANC_HEADSET:
5867 othc_accessories[i].gpio = GPIO_HEADSET_DET_N;
5868 break;
5869 case OTHC_MICROPHONE:
5870 othc_accessories[i].enabled = false;
5871 break;
5872 case OTHC_SVIDEO_OUT:
5873 othc_accessories[i].enabled = true;
5874 hsed_config_1.video_out_gpio = GPIO_HS_SW_DIR;
5875 break;
5876 }
5877 }
5878 }
5879}
5880#endif
5881
5882static struct resource resources_pm8058_charger[] = {
5883 { .name = "CHGVAL",
5884 .start = PM8058_CHGVAL_IRQ(PM8058_IRQ_BASE),
5885 .end = PM8058_CHGVAL_IRQ(PM8058_IRQ_BASE),
5886 .flags = IORESOURCE_IRQ,
5887 },
5888 { .name = "CHGINVAL",
5889 .start = PM8058_CHGINVAL_IRQ(PM8058_IRQ_BASE),
5890 .end = PM8058_CHGINVAL_IRQ(PM8058_IRQ_BASE),
5891 .flags = IORESOURCE_IRQ,
5892 },
5893 {
5894 .name = "CHGILIM",
5895 .start = PM8058_CHGILIM_IRQ(PM8058_IRQ_BASE),
5896 .end = PM8058_CHGILIM_IRQ(PM8058_IRQ_BASE),
5897 .flags = IORESOURCE_IRQ,
5898 },
5899 {
5900 .name = "VCP",
5901 .start = PM8058_VCP_IRQ(PM8058_IRQ_BASE),
5902 .end = PM8058_VCP_IRQ(PM8058_IRQ_BASE),
5903 .flags = IORESOURCE_IRQ,
5904 },
5905 {
5906 .name = "ATC_DONE",
5907 .start = PM8058_ATC_DONE_IRQ(PM8058_IRQ_BASE),
5908 .end = PM8058_ATC_DONE_IRQ(PM8058_IRQ_BASE),
5909 .flags = IORESOURCE_IRQ,
5910 },
5911 {
5912 .name = "ATCFAIL",
5913 .start = PM8058_ATCFAIL_IRQ(PM8058_IRQ_BASE),
5914 .end = PM8058_ATCFAIL_IRQ(PM8058_IRQ_BASE),
5915 .flags = IORESOURCE_IRQ,
5916 },
5917 {
5918 .name = "AUTO_CHGDONE",
5919 .start = PM8058_AUTO_CHGDONE_IRQ(PM8058_IRQ_BASE),
5920 .end = PM8058_AUTO_CHGDONE_IRQ(PM8058_IRQ_BASE),
5921 .flags = IORESOURCE_IRQ,
5922 },
5923 {
5924 .name = "AUTO_CHGFAIL",
5925 .start = PM8058_AUTO_CHGFAIL_IRQ(PM8058_IRQ_BASE),
5926 .end = PM8058_AUTO_CHGFAIL_IRQ(PM8058_IRQ_BASE),
5927 .flags = IORESOURCE_IRQ,
5928 },
5929 {
5930 .name = "CHGSTATE",
5931 .start = PM8058_CHGSTATE_IRQ(PM8058_IRQ_BASE),
5932 .end = PM8058_CHGSTATE_IRQ(PM8058_IRQ_BASE),
5933 .flags = IORESOURCE_IRQ,
5934 },
5935 {
5936 .name = "FASTCHG",
5937 .start = PM8058_FASTCHG_IRQ(PM8058_IRQ_BASE),
5938 .end = PM8058_FASTCHG_IRQ(PM8058_IRQ_BASE),
5939 .flags = IORESOURCE_IRQ,
5940 },
5941 {
5942 .name = "CHG_END",
5943 .start = PM8058_CHG_END_IRQ(PM8058_IRQ_BASE),
5944 .end = PM8058_CHG_END_IRQ(PM8058_IRQ_BASE),
5945 .flags = IORESOURCE_IRQ,
5946 },
5947 {
5948 .name = "BATTTEMP",
5949 .start = PM8058_BATTTEMP_IRQ(PM8058_IRQ_BASE),
5950 .end = PM8058_BATTTEMP_IRQ(PM8058_IRQ_BASE),
5951 .flags = IORESOURCE_IRQ,
5952 },
5953 {
5954 .name = "CHGHOT",
5955 .start = PM8058_CHGHOT_IRQ(PM8058_IRQ_BASE),
5956 .end = PM8058_CHGHOT_IRQ(PM8058_IRQ_BASE),
5957 .flags = IORESOURCE_IRQ,
5958 },
5959 {
5960 .name = "CHGTLIMIT",
5961 .start = PM8058_CHGTLIMIT_IRQ(PM8058_IRQ_BASE),
5962 .end = PM8058_CHGTLIMIT_IRQ(PM8058_IRQ_BASE),
5963 .flags = IORESOURCE_IRQ,
5964 },
5965 {
5966 .name = "CHG_GONE",
5967 .start = PM8058_CHG_GONE_IRQ(PM8058_IRQ_BASE),
5968 .end = PM8058_CHG_GONE_IRQ(PM8058_IRQ_BASE),
5969 .flags = IORESOURCE_IRQ,
5970 },
5971 {
5972 .name = "VCPMAJOR",
5973 .start = PM8058_VCPMAJOR_IRQ(PM8058_IRQ_BASE),
5974 .end = PM8058_VCPMAJOR_IRQ(PM8058_IRQ_BASE),
5975 .flags = IORESOURCE_IRQ,
5976 },
5977 {
5978 .name = "VBATDET",
5979 .start = PM8058_VBATDET_IRQ(PM8058_IRQ_BASE),
5980 .end = PM8058_VBATDET_IRQ(PM8058_IRQ_BASE),
5981 .flags = IORESOURCE_IRQ,
5982 },
5983 {
5984 .name = "BATFET",
5985 .start = PM8058_BATFET_IRQ(PM8058_IRQ_BASE),
5986 .end = PM8058_BATFET_IRQ(PM8058_IRQ_BASE),
5987 .flags = IORESOURCE_IRQ,
5988 },
5989 {
5990 .name = "BATT_REPLACE",
5991 .start = PM8058_BATT_REPLACE_IRQ(PM8058_IRQ_BASE),
5992 .end = PM8058_BATT_REPLACE_IRQ(PM8058_IRQ_BASE),
5993 .flags = IORESOURCE_IRQ,
5994 },
5995 {
5996 .name = "BATTCONNECT",
5997 .start = PM8058_BATTCONNECT_IRQ(PM8058_IRQ_BASE),
5998 .end = PM8058_BATTCONNECT_IRQ(PM8058_IRQ_BASE),
5999 .flags = IORESOURCE_IRQ,
6000 },
6001 {
6002 .name = "VBATDET_LOW",
6003 .start = PM8058_VBATDET_LOW_IRQ(PM8058_IRQ_BASE),
6004 .end = PM8058_VBATDET_LOW_IRQ(PM8058_IRQ_BASE),
6005 .flags = IORESOURCE_IRQ,
6006 },
6007};
6008
6009static int pm8058_pwm_config(struct pwm_device *pwm, int ch, int on)
6010{
6011 struct pm8058_gpio pwm_gpio_config = {
6012 .direction = PM_GPIO_DIR_OUT,
6013 .output_buffer = PM_GPIO_OUT_BUF_CMOS,
6014 .output_value = 0,
6015 .pull = PM_GPIO_PULL_NO,
6016 .vin_sel = PM_GPIO_VIN_VPH,
6017 .out_strength = PM_GPIO_STRENGTH_HIGH,
6018 .function = PM_GPIO_FUNC_2,
6019 };
6020
6021 int rc = -EINVAL;
6022 int id, mode, max_mA;
6023
6024 id = mode = max_mA = 0;
6025 switch (ch) {
6026 case 0:
6027 case 1:
6028 case 2:
6029 if (on) {
6030 id = 24 + ch;
6031 rc = pm8058_gpio_config(id - 1, &pwm_gpio_config);
6032 if (rc)
6033 pr_err("%s: pm8058_gpio_config(%d): rc=%d\n",
6034 __func__, id, rc);
6035 }
6036 break;
6037
6038 case 6:
6039 id = PM_PWM_LED_FLASH;
6040 mode = PM_PWM_CONF_PWM1;
6041 max_mA = 300;
6042 break;
6043
6044 case 7:
6045 id = PM_PWM_LED_FLASH1;
6046 mode = PM_PWM_CONF_PWM1;
6047 max_mA = 300;
6048 break;
6049
6050 default:
6051 break;
6052 }
6053
6054 if (ch >= 6 && ch <= 7) {
6055 if (!on) {
6056 mode = PM_PWM_CONF_NONE;
6057 max_mA = 0;
6058 }
6059 rc = pm8058_pwm_config_led(pwm, id, mode, max_mA);
6060 if (rc)
6061 pr_err("%s: pm8058_pwm_config_led(ch=%d): rc=%d\n",
6062 __func__, ch, rc);
6063 }
6064 return rc;
6065
6066}
6067
6068static struct pm8058_pwm_pdata pm8058_pwm_data = {
6069 .config = pm8058_pwm_config,
6070};
6071
6072#define PM8058_GPIO_INT 88
6073
6074static struct pm8058_gpio_platform_data pm8058_gpio_data = {
6075 .gpio_base = PM8058_GPIO_PM_TO_SYS(0),
6076 .irq_base = PM8058_GPIO_IRQ(PM8058_IRQ_BASE, 0),
6077 .init = pm8058_gpios_init,
6078};
6079
6080static struct pm8058_gpio_platform_data pm8058_mpp_data = {
6081 .gpio_base = PM8058_GPIO_PM_TO_SYS(PM8058_GPIOS),
6082 .irq_base = PM8058_MPP_IRQ(PM8058_IRQ_BASE, 0),
6083};
6084
6085static struct resource resources_rtc[] = {
6086 {
6087 .start = PM8058_RTC_IRQ(PM8058_IRQ_BASE),
6088 .end = PM8058_RTC_IRQ(PM8058_IRQ_BASE),
6089 .flags = IORESOURCE_IRQ,
6090 },
6091 {
6092 .start = PM8058_RTC_ALARM_IRQ(PM8058_IRQ_BASE),
6093 .end = PM8058_RTC_ALARM_IRQ(PM8058_IRQ_BASE),
6094 .flags = IORESOURCE_IRQ,
6095 },
6096};
6097
Ashay Jaiswal4d1ab552011-07-15 11:30:49 +05306098static struct pm8058_rtc_platform_data pm8058_rtc_pdata = {
6099 .rtc_alarm_powerup = false,
6100};
6101
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07006102static struct pmic8058_led pmic8058_flash_leds[] = {
6103 [0] = {
6104 .name = "camera:flash0",
6105 .max_brightness = 15,
6106 .id = PMIC8058_ID_FLASH_LED_0,
6107 },
6108 [1] = {
6109 .name = "camera:flash1",
6110 .max_brightness = 15,
6111 .id = PMIC8058_ID_FLASH_LED_1,
6112 },
6113};
6114
6115static struct pmic8058_leds_platform_data pm8058_flash_leds_data = {
6116 .num_leds = ARRAY_SIZE(pmic8058_flash_leds),
6117 .leds = pmic8058_flash_leds,
6118};
6119
Terence Hampsonc0b6dfb2011-07-15 11:07:17 -04006120static struct pmic8058_led pmic8058_dragon_leds[] = {
6121 [0] = {
6122 /* RED */
6123 .name = "led_drv0",
6124 .max_brightness = 15,
6125 .id = PMIC8058_ID_LED_0,
6126 },/* 300 mA flash led0 drv sink */
6127 [1] = {
6128 /* Yellow */
6129 .name = "led_drv1",
6130 .max_brightness = 15,
6131 .id = PMIC8058_ID_LED_1,
6132 },/* 300 mA flash led0 drv sink */
6133 [2] = {
6134 /* Green */
6135 .name = "led_drv2",
6136 .max_brightness = 15,
6137 .id = PMIC8058_ID_LED_2,
6138 },/* 300 mA flash led0 drv sink */
6139 [3] = {
6140 .name = "led_psensor",
6141 .max_brightness = 15,
6142 .id = PMIC8058_ID_LED_KB_LIGHT,
6143 },/* 300 mA flash led0 drv sink */
6144};
6145
6146static struct pmic8058_leds_platform_data pm8058_dragon_leds_data = {
6147 .num_leds = ARRAY_SIZE(pmic8058_dragon_leds),
6148 .leds = pmic8058_dragon_leds,
6149};
6150
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07006151static struct pmic8058_led pmic8058_fluid_flash_leds[] = {
6152 [0] = {
6153 .name = "led:drv0",
6154 .max_brightness = 15,
6155 .id = PMIC8058_ID_FLASH_LED_0,
6156 },/* 300 mA flash led0 drv sink */
6157 [1] = {
6158 .name = "led:drv1",
6159 .max_brightness = 15,
6160 .id = PMIC8058_ID_FLASH_LED_1,
6161 },/* 300 mA flash led1 sink */
6162 [2] = {
6163 .name = "led:drv2",
6164 .max_brightness = 20,
6165 .id = PMIC8058_ID_LED_0,
6166 },/* 40 mA led0 sink */
6167 [3] = {
6168 .name = "keypad:drv",
6169 .max_brightness = 15,
6170 .id = PMIC8058_ID_LED_KB_LIGHT,
6171 },/* 300 mA keypad drv sink */
6172};
6173
6174static struct pmic8058_leds_platform_data pm8058_fluid_flash_leds_data = {
6175 .num_leds = ARRAY_SIZE(pmic8058_fluid_flash_leds),
6176 .leds = pmic8058_fluid_flash_leds,
6177};
6178
6179static struct resource resources_temp_alarm[] = {
6180 {
6181 .start = PM8058_TEMP_ALARM_IRQ(PM8058_IRQ_BASE),
6182 .end = PM8058_TEMP_ALARM_IRQ(PM8058_IRQ_BASE),
6183 .flags = IORESOURCE_IRQ,
6184 },
6185};
6186
6187static struct resource resources_pm8058_misc[] = {
6188 {
6189 .start = PM8058_OSCHALT_IRQ(PM8058_IRQ_BASE),
6190 .end = PM8058_OSCHALT_IRQ(PM8058_IRQ_BASE),
6191 .flags = IORESOURCE_IRQ,
6192 },
6193};
6194
6195static struct resource resources_pm8058_batt_alarm[] = {
6196 {
6197 .start = PM8058_BATT_ALARM_IRQ(PM8058_IRQ_BASE),
6198 .end = PM8058_BATT_ALARM_IRQ(PM8058_IRQ_BASE),
6199 .flags = IORESOURCE_IRQ,
6200 },
6201};
6202
6203#define PM8058_SUBDEV_KPD 0
6204#define PM8058_SUBDEV_LED 1
6205#define PM8058_SUBDEV_VIB 2
6206
6207static struct mfd_cell pm8058_subdevs[] = {
6208 {
6209 .name = "pm8058-keypad",
6210 .id = -1,
6211 .num_resources = ARRAY_SIZE(resources_keypad),
6212 .resources = resources_keypad,
6213 },
6214 { .name = "pm8058-led",
6215 .id = -1,
6216 },
6217 {
6218 .name = "pm8058-vib",
6219 .id = -1,
6220 },
6221 { .name = "pm8058-gpio",
6222 .id = -1,
6223 .platform_data = &pm8058_gpio_data,
6224 .pdata_size = sizeof(pm8058_gpio_data),
6225 },
6226 { .name = "pm8058-mpp",
6227 .id = -1,
6228 .platform_data = &pm8058_mpp_data,
6229 .pdata_size = sizeof(pm8058_mpp_data),
6230 },
6231 { .name = "pm8058-pwrkey",
6232 .id = -1,
6233 .resources = resources_pwrkey,
6234 .num_resources = ARRAY_SIZE(resources_pwrkey),
6235 .platform_data = &pwrkey_pdata,
6236 .pdata_size = sizeof(pwrkey_pdata),
6237 },
6238 {
6239 .name = "pm8058-pwm",
6240 .id = -1,
6241 .platform_data = &pm8058_pwm_data,
6242 .pdata_size = sizeof(pm8058_pwm_data),
6243 },
6244#ifdef CONFIG_SENSORS_MSM_ADC
6245 {
6246 .name = "pm8058-xoadc",
6247 .id = -1,
6248 .num_resources = ARRAY_SIZE(resources_adc),
6249 .resources = resources_adc,
6250 .platform_data = &xoadc_pdata,
6251 .pdata_size = sizeof(xoadc_pdata),
6252 },
6253#endif
6254#if defined(CONFIG_PMIC8058_OTHC) || defined(CONFIG_PMIC8058_OTHC_MODULE)
6255 {
6256 .name = "pm8058-othc",
6257 .id = 0,
6258 .platform_data = &othc_config_pdata_0,
6259 .pdata_size = sizeof(othc_config_pdata_0),
6260 .num_resources = ARRAY_SIZE(resources_othc_0),
6261 .resources = resources_othc_0,
6262 },
6263 {
6264 /* OTHC1 module has headset/switch dection */
6265 .name = "pm8058-othc",
6266 .id = 1,
6267 .num_resources = ARRAY_SIZE(resources_othc_1),
6268 .resources = resources_othc_1,
6269 .platform_data = &othc_config_pdata_1,
6270 .pdata_size = sizeof(othc_config_pdata_1),
6271 },
6272 {
6273 .name = "pm8058-othc",
6274 .id = 2,
6275 .platform_data = &othc_config_pdata_2,
6276 .pdata_size = sizeof(othc_config_pdata_2),
6277 .num_resources = ARRAY_SIZE(resources_othc_2),
6278 .resources = resources_othc_2,
6279 },
6280#endif
6281 {
6282 .name = "pm8058-rtc",
6283 .id = -1,
6284 .num_resources = ARRAY_SIZE(resources_rtc),
6285 .resources = resources_rtc,
Ashay Jaiswal4d1ab552011-07-15 11:30:49 +05306286 .platform_data = &pm8058_rtc_pdata,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07006287 },
6288 {
6289 .name = "pm8058-tm",
6290 .id = -1,
6291 .num_resources = ARRAY_SIZE(resources_temp_alarm),
6292 .resources = resources_temp_alarm,
6293 },
6294 { .name = "pm8058-upl",
6295 .id = -1,
6296 },
6297 {
6298 .name = "pm8058-misc",
6299 .id = -1,
6300 .num_resources = ARRAY_SIZE(resources_pm8058_misc),
6301 .resources = resources_pm8058_misc,
6302 },
6303 { .name = "pm8058-batt-alarm",
6304 .id = -1,
6305 .num_resources = ARRAY_SIZE(resources_pm8058_batt_alarm),
6306 .resources = resources_pm8058_batt_alarm,
6307 },
6308};
6309
Terence Hampson90508a92011-08-09 10:40:08 -04006310static struct pmic8058_charger_data pmic8058_charger_dragon = {
6311 .max_source_current = 1800,
6312 .charger_type = CHG_TYPE_AC,
6313};
6314
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07006315static struct mfd_cell pm8058_charger_sub_dev = {
6316 .name = "pm8058-charger",
6317 .id = -1,
6318 .num_resources = ARRAY_SIZE(resources_pm8058_charger),
6319 .resources = resources_pm8058_charger,
6320};
6321
6322static struct pm8058_platform_data pm8058_platform_data = {
6323 .irq_base = PM8058_IRQ_BASE,
Anirudh Ghayal9d9cdc22011-10-10 17:17:07 +05306324 .irq = MSM_GPIO_TO_INT(PM8058_GPIO_INT),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07006325
6326 .num_subdevs = ARRAY_SIZE(pm8058_subdevs),
6327 .sub_devices = pm8058_subdevs,
6328 .irq_trigger_flags = IRQF_TRIGGER_LOW,
6329};
6330
Anirudh Ghayal9d9cdc22011-10-10 17:17:07 +05306331#ifdef CONFIG_MSM_SSBI
6332static struct msm_ssbi_platform_data msm8x60_ssbi_pm8058_pdata __devinitdata = {
6333 .controller_type = MSM_SBI_CTRL_PMIC_ARBITER,
6334 .slave = {
6335 .name = "pm8058-core",
6336 .platform_data = &pm8058_platform_data,
6337 },
6338};
6339#endif
6340#endif /* CONFIG_PMIC8058 */
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07006341
6342#if defined(CONFIG_TOUCHDISC_VTD518_SHINETSU) || \
6343 defined(CONFIG_TOUCHDISC_VTD518_SHINETSU_MODULE)
6344#define TDISC_I2C_SLAVE_ADDR 0x67
6345#define PMIC_GPIO_TDISC PM8058_GPIO_PM_TO_SYS(5)
6346#define TDISC_INT PM8058_GPIO_IRQ(PM8058_IRQ_BASE, 5)
6347
6348static const char *vregs_tdisc_name[] = {
6349 "8058_l5",
6350 "8058_s3",
6351};
6352
6353static const int vregs_tdisc_val[] = {
6354 2850000,/* uV */
6355 1800000,
6356};
6357static struct regulator *vregs_tdisc[ARRAY_SIZE(vregs_tdisc_name)];
6358
6359static int tdisc_shinetsu_setup(void)
6360{
6361 int rc, i;
6362
6363 rc = gpio_request(PMIC_GPIO_TDISC, "tdisc_interrupt");
6364 if (rc) {
6365 pr_err("%s: gpio_request failed for PMIC_GPIO_TDISC\n",
6366 __func__);
6367 return rc;
6368 }
6369
6370 rc = gpio_request(GPIO_JOYSTICK_EN, "tdisc_oe");
6371 if (rc) {
6372 pr_err("%s: gpio_request failed for GPIO_JOYSTICK_EN\n",
6373 __func__);
6374 goto fail_gpio_oe;
6375 }
6376
6377 rc = gpio_direction_output(GPIO_JOYSTICK_EN, 1);
6378 if (rc) {
6379 pr_err("%s: gpio_direction_output failed for GPIO_JOYSTICK_EN\n",
6380 __func__);
6381 gpio_free(GPIO_JOYSTICK_EN);
6382 goto fail_gpio_oe;
6383 }
6384
6385 for (i = 0; i < ARRAY_SIZE(vregs_tdisc_name); i++) {
6386 vregs_tdisc[i] = regulator_get(NULL, vregs_tdisc_name[i]);
6387 if (IS_ERR(vregs_tdisc[i])) {
6388 printk(KERN_ERR "%s: regulator get %s failed (%ld)\n",
6389 __func__, vregs_tdisc_name[i],
6390 PTR_ERR(vregs_tdisc[i]));
6391 rc = PTR_ERR(vregs_tdisc[i]);
6392 goto vreg_get_fail;
6393 }
6394
6395 rc = regulator_set_voltage(vregs_tdisc[i],
6396 vregs_tdisc_val[i], vregs_tdisc_val[i]);
6397 if (rc) {
6398 printk(KERN_ERR "%s: regulator_set_voltage() = %d\n",
6399 __func__, rc);
6400 goto vreg_set_voltage_fail;
6401 }
6402 }
6403
6404 return rc;
6405vreg_set_voltage_fail:
6406 i++;
6407vreg_get_fail:
6408 while (i)
6409 regulator_put(vregs_tdisc[--i]);
6410fail_gpio_oe:
6411 gpio_free(PMIC_GPIO_TDISC);
6412 return rc;
6413}
6414
6415static void tdisc_shinetsu_release(void)
6416{
6417 int i;
6418
6419 for (i = 0; i < ARRAY_SIZE(vregs_tdisc_name); i++)
6420 regulator_put(vregs_tdisc[i]);
6421
6422 gpio_free(PMIC_GPIO_TDISC);
6423 gpio_free(GPIO_JOYSTICK_EN);
6424}
6425
6426static int tdisc_shinetsu_enable(void)
6427{
6428 int i, rc = -EINVAL;
6429
6430 for (i = 0; i < ARRAY_SIZE(vregs_tdisc_name); i++) {
6431 rc = regulator_enable(vregs_tdisc[i]);
6432 if (rc < 0) {
6433 printk(KERN_ERR "%s: vreg %s enable failed (%d)\n",
6434 __func__, vregs_tdisc_name[i], rc);
6435 goto vreg_fail;
6436 }
6437 }
6438
6439 /* Enable the OE (output enable) gpio */
6440 gpio_set_value_cansleep(GPIO_JOYSTICK_EN, 1);
6441 /* voltage and gpio stabilization delay */
6442 msleep(50);
6443
6444 return 0;
6445vreg_fail:
6446 while (i)
6447 regulator_disable(vregs_tdisc[--i]);
6448 return rc;
6449}
6450
6451static int tdisc_shinetsu_disable(void)
6452{
6453 int i, rc;
6454
6455 for (i = 0; i < ARRAY_SIZE(vregs_tdisc_name); i++) {
6456 rc = regulator_disable(vregs_tdisc[i]);
6457 if (rc < 0) {
6458 printk(KERN_ERR "%s: vreg %s disable failed (%d)\n",
6459 __func__, vregs_tdisc_name[i], rc);
6460 goto tdisc_reg_fail;
6461 }
6462 }
6463
6464 /* Disable the OE (output enable) gpio */
6465 gpio_set_value_cansleep(GPIO_JOYSTICK_EN, 0);
6466
6467 return 0;
6468
6469tdisc_reg_fail:
6470 while (i)
6471 regulator_enable(vregs_tdisc[--i]);
6472 return rc;
6473}
6474
6475static struct tdisc_abs_values tdisc_abs = {
6476 .x_max = 32,
6477 .y_max = 32,
6478 .x_min = -32,
6479 .y_min = -32,
6480 .pressure_max = 32,
6481 .pressure_min = 0,
6482};
6483
6484static struct tdisc_platform_data tdisc_data = {
6485 .tdisc_setup = tdisc_shinetsu_setup,
6486 .tdisc_release = tdisc_shinetsu_release,
6487 .tdisc_enable = tdisc_shinetsu_enable,
6488 .tdisc_disable = tdisc_shinetsu_disable,
6489 .tdisc_wakeup = 0,
6490 .tdisc_gpio = PMIC_GPIO_TDISC,
6491 .tdisc_report_keys = true,
6492 .tdisc_report_relative = true,
6493 .tdisc_report_absolute = false,
6494 .tdisc_report_wheel = false,
6495 .tdisc_reverse_x = false,
6496 .tdisc_reverse_y = true,
6497 .tdisc_abs = &tdisc_abs,
6498};
6499
6500static struct i2c_board_info msm_i2c_gsbi3_tdisc_info[] = {
6501 {
6502 I2C_BOARD_INFO("vtd518", TDISC_I2C_SLAVE_ADDR),
6503 .irq = TDISC_INT,
6504 .platform_data = &tdisc_data,
6505 },
6506};
6507#endif
6508
6509#define PM_GPIO_CDC_RST_N 20
6510#define GPIO_CDC_RST_N PM8058_GPIO_PM_TO_SYS(PM_GPIO_CDC_RST_N)
6511
6512static struct regulator *vreg_timpani_1;
6513static struct regulator *vreg_timpani_2;
6514
6515static unsigned int msm_timpani_setup_power(void)
6516{
6517 int rc;
6518
6519 vreg_timpani_1 = regulator_get(NULL, "8058_l0");
6520 if (IS_ERR(vreg_timpani_1)) {
6521 pr_err("%s: Unable to get 8058_l0\n", __func__);
6522 return -ENODEV;
6523 }
6524
6525 vreg_timpani_2 = regulator_get(NULL, "8058_s3");
6526 if (IS_ERR(vreg_timpani_2)) {
6527 pr_err("%s: Unable to get 8058_s3\n", __func__);
6528 regulator_put(vreg_timpani_1);
6529 return -ENODEV;
6530 }
6531
6532 rc = regulator_set_voltage(vreg_timpani_1, 1200000, 1200000);
6533 if (rc) {
6534 pr_err("%s: unable to set L0 voltage to 1.2V\n", __func__);
6535 goto fail;
6536 }
6537
6538 rc = regulator_set_voltage(vreg_timpani_2, 1800000, 1800000);
6539 if (rc) {
6540 pr_err("%s: unable to set S3 voltage to 1.8V\n", __func__);
6541 goto fail;
6542 }
6543
6544 rc = regulator_enable(vreg_timpani_1);
6545 if (rc) {
6546 pr_err("%s: Enable regulator 8058_l0 failed\n", __func__);
6547 goto fail;
6548 }
6549
6550 /* The settings for LDO0 should be set such that
6551 * it doesn't require to reset the timpani. */
6552 rc = regulator_set_optimum_mode(vreg_timpani_1, 5000);
6553 if (rc < 0) {
6554 pr_err("Timpani regulator optimum mode setting failed\n");
6555 goto fail;
6556 }
6557
6558 rc = regulator_enable(vreg_timpani_2);
6559 if (rc) {
6560 pr_err("%s: Enable regulator 8058_s3 failed\n", __func__);
6561 regulator_disable(vreg_timpani_1);
6562 goto fail;
6563 }
6564
6565 rc = gpio_request(GPIO_CDC_RST_N, "CDC_RST_N");
6566 if (rc) {
6567 pr_err("%s: GPIO Request %d failed\n", __func__,
6568 GPIO_CDC_RST_N);
6569 regulator_disable(vreg_timpani_1);
6570 regulator_disable(vreg_timpani_2);
6571 goto fail;
6572 } else {
6573 gpio_direction_output(GPIO_CDC_RST_N, 1);
6574 usleep_range(1000, 1050);
6575 gpio_direction_output(GPIO_CDC_RST_N, 0);
6576 usleep_range(1000, 1050);
6577 gpio_direction_output(GPIO_CDC_RST_N, 1);
6578 gpio_free(GPIO_CDC_RST_N);
6579 }
6580 return rc;
6581
6582fail:
6583 regulator_put(vreg_timpani_1);
6584 regulator_put(vreg_timpani_2);
6585 return rc;
6586}
6587
6588static void msm_timpani_shutdown_power(void)
6589{
6590 int rc;
6591
6592 rc = regulator_disable(vreg_timpani_1);
6593 if (rc)
6594 pr_err("%s: Disable regulator 8058_l0 failed\n", __func__);
6595
6596 regulator_put(vreg_timpani_1);
6597
6598 rc = regulator_disable(vreg_timpani_2);
6599 if (rc)
6600 pr_err("%s: Disable regulator 8058_s3 failed\n", __func__);
6601
6602 regulator_put(vreg_timpani_2);
6603}
6604
6605/* Power analog function of codec */
6606static struct regulator *vreg_timpani_cdc_apwr;
6607static int msm_timpani_codec_power(int vreg_on)
6608{
6609 int rc = 0;
6610
6611 if (!vreg_timpani_cdc_apwr) {
6612
6613 vreg_timpani_cdc_apwr = regulator_get(NULL, "8058_s4");
6614
6615 if (IS_ERR(vreg_timpani_cdc_apwr)) {
6616 pr_err("%s: vreg_get failed (%ld)\n",
6617 __func__, PTR_ERR(vreg_timpani_cdc_apwr));
6618 rc = PTR_ERR(vreg_timpani_cdc_apwr);
6619 return rc;
6620 }
6621 }
6622
6623 if (vreg_on) {
6624
6625 rc = regulator_set_voltage(vreg_timpani_cdc_apwr,
6626 2200000, 2200000);
6627 if (rc) {
6628 pr_err("%s: unable to set 8058_s4 voltage to 2.2 V\n",
6629 __func__);
6630 goto vreg_fail;
6631 }
6632
6633 rc = regulator_enable(vreg_timpani_cdc_apwr);
6634 if (rc) {
6635 pr_err("%s: vreg_enable failed %d\n", __func__, rc);
6636 goto vreg_fail;
6637 }
6638 } else {
6639 rc = regulator_disable(vreg_timpani_cdc_apwr);
6640 if (rc) {
6641 pr_err("%s: vreg_disable failed %d\n",
6642 __func__, rc);
6643 goto vreg_fail;
6644 }
6645 }
6646
6647 return 0;
6648
6649vreg_fail:
6650 regulator_put(vreg_timpani_cdc_apwr);
6651 vreg_timpani_cdc_apwr = NULL;
6652 return rc;
6653}
6654
6655static struct marimba_codec_platform_data timpani_codec_pdata = {
6656 .marimba_codec_power = msm_timpani_codec_power,
6657};
6658
6659#define TIMPANI_SLAVE_ID_CDC_ADDR 0X77
6660#define TIMPANI_SLAVE_ID_QMEMBIST_ADDR 0X66
6661
6662static struct marimba_platform_data timpani_pdata = {
6663 .slave_id[MARIMBA_SLAVE_ID_CDC] = TIMPANI_SLAVE_ID_CDC_ADDR,
6664 .slave_id[MARIMBA_SLAVE_ID_QMEMBIST] = TIMPANI_SLAVE_ID_QMEMBIST_ADDR,
6665 .marimba_setup = msm_timpani_setup_power,
6666 .marimba_shutdown = msm_timpani_shutdown_power,
6667 .codec = &timpani_codec_pdata,
6668 .tsadc_ssbi_adap = MARIMBA_SSBI_ADAP,
6669};
6670
6671#define TIMPANI_I2C_SLAVE_ADDR 0xD
6672
6673static struct i2c_board_info msm_i2c_gsbi7_timpani_info[] = {
6674 {
6675 I2C_BOARD_INFO("timpani", TIMPANI_I2C_SLAVE_ADDR),
6676 .platform_data = &timpani_pdata,
6677 },
6678};
6679
Lei Zhou338cab82011-08-19 13:38:17 -04006680#ifdef CONFIG_SND_SOC_WM8903
6681static struct wm8903_platform_data wm8903_pdata = {
6682 .gpio_cfg[2] = 0x3A8,
6683};
6684
6685#define WM8903_I2C_SLAVE_ADDR 0x34
6686static struct i2c_board_info wm8903_codec_i2c_info[] = {
6687 {
6688 I2C_BOARD_INFO("wm8903", WM8903_I2C_SLAVE_ADDR >> 1),
6689 .platform_data = &wm8903_pdata,
6690 },
6691};
6692#endif
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07006693#ifdef CONFIG_PMIC8901
6694
6695#define PM8901_GPIO_INT 91
6696
6697static struct pm8901_gpio_platform_data pm8901_mpp_data = {
6698 .gpio_base = PM8901_GPIO_PM_TO_SYS(0),
6699 .irq_base = PM8901_MPP_IRQ(PM8901_IRQ_BASE, 0),
6700};
6701
6702static struct resource pm8901_temp_alarm[] = {
6703 {
6704 .start = PM8901_TEMP_ALARM_IRQ(PM8901_IRQ_BASE),
6705 .end = PM8901_TEMP_ALARM_IRQ(PM8901_IRQ_BASE),
6706 .flags = IORESOURCE_IRQ,
6707 },
6708 {
6709 .start = PM8901_TEMP_HI_ALARM_IRQ(PM8901_IRQ_BASE),
6710 .end = PM8901_TEMP_HI_ALARM_IRQ(PM8901_IRQ_BASE),
6711 .flags = IORESOURCE_IRQ,
6712 },
6713};
6714
6715/*
6716 * Consumer specific regulator names:
6717 * regulator name consumer dev_name
6718 */
6719static struct regulator_consumer_supply vreg_consumers_8901_MPP0[] = {
6720 REGULATOR_SUPPLY("8901_mpp0", NULL),
6721};
6722static struct regulator_consumer_supply vreg_consumers_8901_USB_OTG[] = {
6723 REGULATOR_SUPPLY("8901_usb_otg", NULL),
6724};
6725static struct regulator_consumer_supply vreg_consumers_8901_HDMI_MVS[] = {
6726 REGULATOR_SUPPLY("8901_hdmi_mvs", NULL),
6727};
6728
6729#define PM8901_VREG_INIT(_id, _min_uV, _max_uV, _modes, _ops, _apply_uV, \
6730 _always_on, _active_high) \
6731 [PM8901_VREG_ID_##_id] = { \
6732 .init_data = { \
6733 .constraints = { \
6734 .valid_modes_mask = _modes, \
6735 .valid_ops_mask = _ops, \
6736 .min_uV = _min_uV, \
6737 .max_uV = _max_uV, \
6738 .input_uV = _min_uV, \
6739 .apply_uV = _apply_uV, \
6740 .always_on = _always_on, \
6741 }, \
6742 .consumer_supplies = vreg_consumers_8901_##_id, \
6743 .num_consumer_supplies = \
6744 ARRAY_SIZE(vreg_consumers_8901_##_id), \
6745 }, \
6746 .active_high = _active_high, \
6747 }
6748
6749#define PM8901_VREG_INIT_MPP(_id, _active_high) \
6750 PM8901_VREG_INIT(_id, 0, 0, REGULATOR_MODE_NORMAL, \
6751 REGULATOR_CHANGE_STATUS, 0, 0, _active_high)
6752
6753#define PM8901_VREG_INIT_VS(_id) \
6754 PM8901_VREG_INIT(_id, 0, 0, REGULATOR_MODE_NORMAL, \
6755 REGULATOR_CHANGE_STATUS, 0, 0, 0)
6756
6757static struct pm8901_vreg_pdata pm8901_vreg_init_pdata[PM8901_VREG_MAX] = {
6758 PM8901_VREG_INIT_MPP(MPP0, 1),
6759
6760 PM8901_VREG_INIT_VS(USB_OTG),
6761 PM8901_VREG_INIT_VS(HDMI_MVS),
6762};
6763
6764#define PM8901_VREG(_id) { \
6765 .name = "pm8901-regulator", \
6766 .id = _id, \
6767 .platform_data = &pm8901_vreg_init_pdata[_id], \
6768 .pdata_size = sizeof(pm8901_vreg_init_pdata[_id]), \
6769}
6770
6771static struct mfd_cell pm8901_subdevs[] = {
6772 { .name = "pm8901-mpp",
6773 .id = -1,
6774 .platform_data = &pm8901_mpp_data,
6775 .pdata_size = sizeof(pm8901_mpp_data),
6776 },
6777 { .name = "pm8901-tm",
6778 .id = -1,
6779 .num_resources = ARRAY_SIZE(pm8901_temp_alarm),
6780 .resources = pm8901_temp_alarm,
6781 },
6782 PM8901_VREG(PM8901_VREG_ID_MPP0),
6783 PM8901_VREG(PM8901_VREG_ID_USB_OTG),
6784 PM8901_VREG(PM8901_VREG_ID_HDMI_MVS),
6785};
6786
6787static struct pm8901_platform_data pm8901_platform_data = {
6788 .irq_base = PM8901_IRQ_BASE,
6789 .num_subdevs = ARRAY_SIZE(pm8901_subdevs),
6790 .sub_devices = pm8901_subdevs,
6791 .irq_trigger_flags = IRQF_TRIGGER_LOW,
6792};
6793
6794static struct i2c_board_info pm8901_boardinfo[] __initdata = {
6795 {
6796 I2C_BOARD_INFO("pm8901-core", 0x55),
6797 .irq = MSM_GPIO_TO_INT(PM8901_GPIO_INT),
6798 .platform_data = &pm8901_platform_data,
6799 },
6800};
6801
6802#endif /* CONFIG_PMIC8901 */
6803
6804#if defined(CONFIG_MARIMBA_CORE) && (defined(CONFIG_GPIO_SX150X) \
6805 || defined(CONFIG_GPIO_SX150X_MODULE))
6806
6807static struct regulator *vreg_bahama;
Zhang Chang Kene1fd3da2011-08-10 08:25:57 -04006808static int msm_bahama_sys_rst = GPIO_MS_SYS_RESET_N;
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07006809
6810struct bahama_config_register{
6811 u8 reg;
6812 u8 value;
6813 u8 mask;
6814};
6815
6816enum version{
6817 VER_1_0,
6818 VER_2_0,
6819 VER_UNSUPPORTED = 0xFF
6820};
6821
6822static u8 read_bahama_ver(void)
6823{
6824 int rc;
6825 struct marimba config = { .mod_id = SLAVE_ID_BAHAMA };
6826 u8 bahama_version;
6827
6828 rc = marimba_read_bit_mask(&config, 0x00, &bahama_version, 1, 0x1F);
6829 if (rc < 0) {
6830 printk(KERN_ERR
6831 "%s: version read failed: %d\n",
6832 __func__, rc);
6833 return VER_UNSUPPORTED;
6834 } else {
6835 printk(KERN_INFO
6836 "%s: version read got: 0x%x\n",
6837 __func__, bahama_version);
6838 }
6839
6840 switch (bahama_version) {
6841 case 0x08: /* varient of bahama v1 */
6842 case 0x10:
6843 case 0x00:
6844 return VER_1_0;
6845 case 0x09: /* variant of bahama v2 */
6846 return VER_2_0;
6847 default:
6848 return VER_UNSUPPORTED;
6849 }
6850}
6851
Siddartha Mohanadoss7e8e9dd2011-09-27 19:04:58 -07006852static int msm_bahama_setup_power_enable;
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07006853static unsigned int msm_bahama_setup_power(void)
6854{
6855 int rc = 0;
6856 const char *msm_bahama_regulator = "8058_s3";
Zhang Chang Kene1fd3da2011-08-10 08:25:57 -04006857
6858 if (machine_is_msm8x60_dragon())
6859 msm_bahama_sys_rst = GPIO_CDC_RST_N;
6860
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07006861 vreg_bahama = regulator_get(NULL, msm_bahama_regulator);
6862
6863 if (IS_ERR(vreg_bahama)) {
6864 rc = PTR_ERR(vreg_bahama);
6865 pr_err("%s: regulator_get %s = %d\n", __func__,
6866 msm_bahama_regulator, rc);
Siddartha Mohanadoss7e8e9dd2011-09-27 19:04:58 -07006867 return rc;
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07006868 }
6869
Siddartha Mohanadoss7e8e9dd2011-09-27 19:04:58 -07006870 rc = regulator_set_voltage(vreg_bahama, 1800000, 1800000);
6871 if (rc) {
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07006872 pr_err("%s: regulator_set_voltage %s = %d\n", __func__,
6873 msm_bahama_regulator, rc);
6874 goto unget;
6875 }
6876
Siddartha Mohanadoss7e8e9dd2011-09-27 19:04:58 -07006877 rc = regulator_enable(vreg_bahama);
6878 if (rc) {
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07006879 pr_err("%s: regulator_enable %s = %d\n", __func__,
6880 msm_bahama_regulator, rc);
6881 goto unget;
6882 }
6883
Siddartha Mohanadoss7e8e9dd2011-09-27 19:04:58 -07006884 rc = gpio_request(msm_bahama_sys_rst, "bahama sys_rst_n");
6885 if (rc) {
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07006886 pr_err("%s: gpio_request %d = %d\n", __func__,
Zhang Chang Kene1fd3da2011-08-10 08:25:57 -04006887 msm_bahama_sys_rst, rc);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07006888 goto unenable;
6889 }
6890
Siddartha Mohanadoss7e8e9dd2011-09-27 19:04:58 -07006891 gpio_direction_output(msm_bahama_sys_rst, 0);
6892 usleep_range(1000, 1050);
6893 gpio_set_value_cansleep(msm_bahama_sys_rst, 1);
6894 usleep_range(1000, 1050);
6895 msm_bahama_setup_power_enable = 1;
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07006896 return rc;
6897
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07006898unenable:
6899 regulator_disable(vreg_bahama);
6900unget:
6901 regulator_put(vreg_bahama);
6902 return rc;
6903};
Siddartha Mohanadoss7e8e9dd2011-09-27 19:04:58 -07006904
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07006905static unsigned int msm_bahama_shutdown_power(int value)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07006906{
Siddartha Mohanadoss7e8e9dd2011-09-27 19:04:58 -07006907 if (msm_bahama_setup_power_enable) {
6908 gpio_set_value_cansleep(msm_bahama_sys_rst, 0);
6909 gpio_free(msm_bahama_sys_rst);
6910 regulator_disable(vreg_bahama);
6911 regulator_put(vreg_bahama);
6912 msm_bahama_setup_power_enable = 0;
6913 }
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07006914
6915 return 0;
6916};
6917
6918static unsigned int msm_bahama_core_config(int type)
6919{
6920 int rc = 0;
6921
6922 if (type == BAHAMA_ID) {
6923
6924 int i;
6925 struct marimba config = { .mod_id = SLAVE_ID_BAHAMA };
6926
6927 const struct bahama_config_register v20_init[] = {
6928 /* reg, value, mask */
6929 { 0xF4, 0x84, 0xFF }, /* AREG */
6930 { 0xF0, 0x04, 0xFF } /* DREG */
6931 };
6932
6933 if (read_bahama_ver() == VER_2_0) {
6934 for (i = 0; i < ARRAY_SIZE(v20_init); i++) {
6935 u8 value = v20_init[i].value;
6936 rc = marimba_write_bit_mask(&config,
6937 v20_init[i].reg,
6938 &value,
6939 sizeof(v20_init[i].value),
6940 v20_init[i].mask);
6941 if (rc < 0) {
6942 printk(KERN_ERR
6943 "%s: reg %d write failed: %d\n",
6944 __func__, v20_init[i].reg, rc);
6945 return rc;
6946 }
6947 printk(KERN_INFO "%s: reg 0x%02x value 0x%02x"
6948 " mask 0x%02x\n",
6949 __func__, v20_init[i].reg,
6950 v20_init[i].value, v20_init[i].mask);
6951 }
6952 }
6953 }
6954 printk(KERN_INFO "core type: %d\n", type);
6955
6956 return rc;
6957}
6958
6959static struct regulator *fm_regulator_s3;
6960static struct msm_xo_voter *fm_clock;
6961
6962static int fm_radio_setup(struct marimba_fm_platform_data *pdata)
6963{
6964 int rc = 0;
6965 struct pm8058_gpio cfg = {
6966 .direction = PM_GPIO_DIR_IN,
6967 .pull = PM_GPIO_PULL_NO,
6968 .vin_sel = PM_GPIO_VIN_S3,
6969 .function = PM_GPIO_FUNC_NORMAL,
6970 .inv_int_pol = 0,
6971 };
6972
6973 if (!fm_regulator_s3) {
6974 fm_regulator_s3 = regulator_get(NULL, "8058_s3");
6975 if (IS_ERR(fm_regulator_s3)) {
6976 rc = PTR_ERR(fm_regulator_s3);
6977 printk(KERN_ERR "%s: regulator get s3 (%d)\n",
6978 __func__, rc);
6979 goto out;
6980 }
6981 }
6982
6983
6984 rc = regulator_set_voltage(fm_regulator_s3, 1800000, 1800000);
6985 if (rc < 0) {
6986 printk(KERN_ERR "%s: regulator set voltage failed (%d)\n",
6987 __func__, rc);
6988 goto fm_fail_put;
6989 }
6990
6991 rc = regulator_enable(fm_regulator_s3);
6992 if (rc < 0) {
6993 printk(KERN_ERR "%s: regulator s3 enable failed (%d)\n",
6994 __func__, rc);
6995 goto fm_fail_put;
6996 }
6997
6998 /*Vote for XO clock*/
6999 fm_clock = msm_xo_get(MSM_XO_TCXO_D0, "fm_power");
7000
7001 if (IS_ERR(fm_clock)) {
7002 rc = PTR_ERR(fm_clock);
7003 printk(KERN_ERR "%s: Couldn't get TCXO_D0 vote for FM (%d)\n",
7004 __func__, rc);
7005 goto fm_fail_switch;
7006 }
7007
7008 rc = msm_xo_mode_vote(fm_clock, MSM_XO_MODE_ON);
7009 if (rc < 0) {
7010 printk(KERN_ERR "%s: Failed to vote for TCX0_D0 ON (%d)\n",
7011 __func__, rc);
7012 goto fm_fail_vote;
7013 }
7014
7015 /*GPIO 18 on PMIC is FM_IRQ*/
7016 rc = pm8058_gpio_config(FM_GPIO, &cfg);
7017 if (rc) {
7018 printk(KERN_ERR "%s: return val of pm8058_gpio_config: %d\n",
7019 __func__, rc);
7020 goto fm_fail_clock;
7021 }
7022 goto out;
7023
7024fm_fail_clock:
7025 msm_xo_mode_vote(fm_clock, MSM_XO_MODE_OFF);
7026fm_fail_vote:
7027 msm_xo_put(fm_clock);
7028fm_fail_switch:
7029 regulator_disable(fm_regulator_s3);
7030fm_fail_put:
7031 regulator_put(fm_regulator_s3);
7032out:
7033 return rc;
7034};
7035
7036static void fm_radio_shutdown(struct marimba_fm_platform_data *pdata)
7037{
7038 int rc = 0;
7039 if (fm_regulator_s3 != NULL) {
7040 rc = regulator_disable(fm_regulator_s3);
7041 if (rc < 0) {
7042 printk(KERN_ERR "%s: regulator s3 disable (%d)\n",
7043 __func__, rc);
7044 }
7045 regulator_put(fm_regulator_s3);
7046 fm_regulator_s3 = NULL;
7047 }
7048 printk(KERN_ERR "%s: Voting off for XO", __func__);
7049
7050 if (fm_clock != NULL) {
7051 rc = msm_xo_mode_vote(fm_clock, MSM_XO_MODE_OFF);
7052 if (rc < 0) {
7053 printk(KERN_ERR "%s: Voting off XO clock (%d)\n",
7054 __func__, rc);
7055 }
7056 msm_xo_put(fm_clock);
7057 }
7058 printk(KERN_ERR "%s: coming out of fm_radio_shutdown", __func__);
7059}
7060
7061/* Slave id address for FM/CDC/QMEMBIST
7062 * Values can be programmed using Marimba slave id 0
7063 * should there be a conflict with other I2C devices
7064 * */
7065#define BAHAMA_SLAVE_ID_FM_ADDR 0x2A
7066#define BAHAMA_SLAVE_ID_QMEMBIST_ADDR 0x7B
7067
7068static struct marimba_fm_platform_data marimba_fm_pdata = {
7069 .fm_setup = fm_radio_setup,
7070 .fm_shutdown = fm_radio_shutdown,
7071 .irq = PM8058_GPIO_IRQ(PM8058_IRQ_BASE, FM_GPIO),
7072 .is_fm_soc_i2s_master = false,
7073 .config_i2s_gpio = NULL,
7074};
7075
7076/*
7077Just initializing the BAHAMA related slave
7078*/
7079static struct marimba_platform_data marimba_pdata = {
7080 .slave_id[SLAVE_ID_BAHAMA_FM] = BAHAMA_SLAVE_ID_FM_ADDR,
7081 .slave_id[SLAVE_ID_BAHAMA_QMEMBIST] = BAHAMA_SLAVE_ID_QMEMBIST_ADDR,
7082 .bahama_setup = msm_bahama_setup_power,
7083 .bahama_shutdown = msm_bahama_shutdown_power,
7084 .bahama_core_config = msm_bahama_core_config,
7085 .fm = &marimba_fm_pdata,
7086 .tsadc_ssbi_adap = MARIMBA_SSBI_ADAP,
7087};
7088
7089
7090static struct i2c_board_info msm_marimba_board_info[] = {
7091 {
7092 I2C_BOARD_INFO("marimba", 0xc),
7093 .platform_data = &marimba_pdata,
7094 }
7095};
7096#endif /* CONFIG_MAIMBA_CORE */
7097
7098#ifdef CONFIG_I2C
7099#define I2C_SURF 1
7100#define I2C_FFA (1 << 1)
7101#define I2C_RUMI (1 << 2)
7102#define I2C_SIM (1 << 3)
7103#define I2C_FLUID (1 << 4)
Zhang Chang Ken6baadf02011-08-05 09:48:15 -04007104#define I2C_DRAGON (1 << 5)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07007105
7106struct i2c_registry {
7107 u8 machs;
7108 int bus;
7109 struct i2c_board_info *info;
7110 int len;
7111};
7112
7113static struct i2c_registry msm8x60_i2c_devices[] __initdata = {
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07007114#ifdef CONFIG_PMIC8901
7115 {
Zhang Chang Ken6baadf02011-08-05 09:48:15 -04007116 I2C_SURF | I2C_FFA | I2C_FLUID | I2C_DRAGON,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07007117 MSM_SSBI2_I2C_BUS_ID,
7118 pm8901_boardinfo,
7119 ARRAY_SIZE(pm8901_boardinfo),
7120 },
7121#endif
7122#if defined(CONFIG_GPIO_SX150X) || defined(CONFIG_GPIO_SX150X_MODULE)
7123 {
Zhang Chang Ken6baadf02011-08-05 09:48:15 -04007124 I2C_SURF | I2C_FFA | I2C_DRAGON,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07007125 MSM_GSBI8_QUP_I2C_BUS_ID,
7126 core_expander_i2c_info,
7127 ARRAY_SIZE(core_expander_i2c_info),
7128 },
7129 {
Zhang Chang Ken6baadf02011-08-05 09:48:15 -04007130 I2C_SURF | I2C_FFA | I2C_DRAGON,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07007131 MSM_GSBI8_QUP_I2C_BUS_ID,
7132 docking_expander_i2c_info,
7133 ARRAY_SIZE(docking_expander_i2c_info),
7134 },
7135 {
7136 I2C_SURF,
7137 MSM_GSBI8_QUP_I2C_BUS_ID,
7138 surf_expanders_i2c_info,
7139 ARRAY_SIZE(surf_expanders_i2c_info),
7140 },
7141 {
Zhang Chang Ken6baadf02011-08-05 09:48:15 -04007142 I2C_SURF | I2C_FFA | I2C_DRAGON,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07007143 MSM_GSBI3_QUP_I2C_BUS_ID,
7144 fha_expanders_i2c_info,
7145 ARRAY_SIZE(fha_expanders_i2c_info),
7146 },
7147 {
7148 I2C_FLUID,
7149 MSM_GSBI3_QUP_I2C_BUS_ID,
7150 fluid_expanders_i2c_info,
7151 ARRAY_SIZE(fluid_expanders_i2c_info),
7152 },
7153 {
7154 I2C_FLUID,
7155 MSM_GSBI8_QUP_I2C_BUS_ID,
7156 fluid_core_expander_i2c_info,
7157 ARRAY_SIZE(fluid_core_expander_i2c_info),
7158 },
7159#endif
7160#if defined(CONFIG_TOUCHDISC_VTD518_SHINETSU) || \
7161 defined(CONFIG_TOUCHDISC_VTD518_SHINETSU_MODULE)
7162 {
Zhang Chang Ken6baadf02011-08-05 09:48:15 -04007163 I2C_SURF | I2C_FFA | I2C_FLUID | I2C_DRAGON,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07007164 MSM_GSBI3_QUP_I2C_BUS_ID,
7165 msm_i2c_gsbi3_tdisc_info,
7166 ARRAY_SIZE(msm_i2c_gsbi3_tdisc_info),
7167 },
7168#endif
7169 {
Zhang Chang Ken211df572011-07-05 19:16:39 -04007170 I2C_SURF | I2C_FFA | I2C_FLUID,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07007171 MSM_GSBI3_QUP_I2C_BUS_ID,
7172 cy8ctmg200_board_info,
7173 ARRAY_SIZE(cy8ctmg200_board_info),
7174 },
Zhang Chang Ken211df572011-07-05 19:16:39 -04007175 {
7176 I2C_DRAGON,
7177 MSM_GSBI3_QUP_I2C_BUS_ID,
7178 cy8ctma340_dragon_board_info,
7179 ARRAY_SIZE(cy8ctma340_dragon_board_info),
7180 },
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07007181#if defined(CONFIG_TOUCHSCREEN_CYTTSP_I2C) || \
7182 defined(CONFIG_TOUCHSCREEN_CYTTSP_I2C_MODULE)
7183 {
7184 I2C_FLUID,
7185 MSM_GSBI3_QUP_I2C_BUS_ID,
7186 cyttsp_fluid_info,
7187 ARRAY_SIZE(cyttsp_fluid_info),
7188 },
7189 {
7190 I2C_FFA | I2C_SURF,
7191 MSM_GSBI3_QUP_I2C_BUS_ID,
7192 cyttsp_ffa_info,
7193 ARRAY_SIZE(cyttsp_ffa_info),
7194 },
7195#endif
7196#ifdef CONFIG_MSM_CAMERA
Jilai Wang971f97f2011-07-13 14:25:25 -04007197 {
7198 I2C_SURF | I2C_FFA | I2C_FLUID ,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07007199 MSM_GSBI4_QUP_I2C_BUS_ID,
7200 msm_camera_boardinfo,
7201 ARRAY_SIZE(msm_camera_boardinfo),
7202 },
Jilai Wang971f97f2011-07-13 14:25:25 -04007203 {
7204 I2C_DRAGON,
7205 MSM_GSBI4_QUP_I2C_BUS_ID,
7206 msm_camera_dragon_boardinfo,
7207 ARRAY_SIZE(msm_camera_dragon_boardinfo),
7208 },
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07007209#endif
7210 {
7211 I2C_SURF | I2C_FFA | I2C_FLUID,
7212 MSM_GSBI7_QUP_I2C_BUS_ID,
7213 msm_i2c_gsbi7_timpani_info,
7214 ARRAY_SIZE(msm_i2c_gsbi7_timpani_info),
7215 },
7216#if defined(CONFIG_MARIMBA_CORE)
7217 {
Zhang Chang Kene1fd3da2011-08-10 08:25:57 -04007218 I2C_SURF | I2C_FFA | I2C_FLUID | I2C_DRAGON,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07007219 MSM_GSBI7_QUP_I2C_BUS_ID,
7220 msm_marimba_board_info,
7221 ARRAY_SIZE(msm_marimba_board_info),
7222 },
7223#endif /* CONFIG_MARIMBA_CORE */
7224#ifdef CONFIG_ISL9519_CHARGER
7225 {
7226 I2C_SURF | I2C_FFA,
7227 MSM_GSBI8_QUP_I2C_BUS_ID,
7228 isl_charger_i2c_info,
7229 ARRAY_SIZE(isl_charger_i2c_info),
7230 },
7231#endif
7232#if defined(CONFIG_HAPTIC_ISA1200) || \
7233 defined(CONFIG_HAPTIC_ISA1200_MODULE)
7234 {
7235 I2C_FLUID,
7236 MSM_GSBI8_QUP_I2C_BUS_ID,
7237 msm_isa1200_board_info,
7238 ARRAY_SIZE(msm_isa1200_board_info),
7239 },
7240#endif
7241#if defined(CONFIG_SMB137B_CHARGER) || defined(CONFIG_SMB137B_CHARGER_MODULE)
7242 {
7243 I2C_FLUID,
7244 MSM_GSBI8_QUP_I2C_BUS_ID,
7245 smb137b_charger_i2c_info,
7246 ARRAY_SIZE(smb137b_charger_i2c_info),
7247 },
7248#endif
7249#if defined(CONFIG_BATTERY_BQ27520) || \
7250 defined(CONFIG_BATTERY_BQ27520_MODULE)
7251 {
7252 I2C_FLUID,
7253 MSM_GSBI8_QUP_I2C_BUS_ID,
7254 msm_bq27520_board_info,
7255 ARRAY_SIZE(msm_bq27520_board_info),
7256 },
7257#endif
Lei Zhou338cab82011-08-19 13:38:17 -04007258#if defined(CONFIG_SND_SOC_WM8903) || defined(CONFIG_SND_SOC_WM8903_MODULE)
7259 {
7260 I2C_DRAGON,
7261 MSM_GSBI8_QUP_I2C_BUS_ID,
7262 wm8903_codec_i2c_info,
7263 ARRAY_SIZE(wm8903_codec_i2c_info),
7264 },
7265#endif
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07007266};
7267#endif /* CONFIG_I2C */
7268
7269static void fixup_i2c_configs(void)
7270{
7271#ifdef CONFIG_I2C
7272#if defined(CONFIG_GPIO_SX150X) || defined(CONFIG_GPIO_SX150X_MODULE)
7273 if (machine_is_msm8x60_surf() || machine_is_msm8x60_fusion())
7274 sx150x_data[SX150X_CORE].irq_summary =
7275 PM8058_GPIO_IRQ(PM8058_IRQ_BASE, UI_INT2_N);
Zhang Chang Ken6baadf02011-08-05 09:48:15 -04007276 else if (machine_is_msm8x60_ffa() || machine_is_msm8x60_fusn_ffa() ||
7277 machine_is_msm8x60_dragon())
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07007278 sx150x_data[SX150X_CORE].irq_summary =
7279 PM8058_GPIO_IRQ(PM8058_IRQ_BASE, UI_INT1_N);
7280 else if (machine_is_msm8x60_fluid())
7281 sx150x_data[SX150X_CORE_FLUID].irq_summary =
7282 PM8058_GPIO_IRQ(PM8058_IRQ_BASE, UI_INT1_N);
7283#endif
7284 /*
7285 * Set PMIC 8901 MPP0 active_high to 0 for surf and charm_surf. This
7286 * implies that the regulator connected to MPP0 is enabled when
7287 * MPP0 is low.
7288 */
7289 if (machine_is_msm8x60_surf() || machine_is_msm8x60_fusion())
7290 pm8901_vreg_init_pdata[PM8901_VREG_ID_MPP0].active_high = 0;
7291 else
7292 pm8901_vreg_init_pdata[PM8901_VREG_ID_MPP0].active_high = 1;
7293#endif
7294}
7295
7296static void register_i2c_devices(void)
7297{
7298#ifdef CONFIG_I2C
7299 u8 mach_mask = 0;
7300 int i;
7301
7302 /* Build the matching 'supported_machs' bitmask */
7303 if (machine_is_msm8x60_surf() || machine_is_msm8x60_fusion())
7304 mach_mask = I2C_SURF;
7305 else if (machine_is_msm8x60_ffa() || machine_is_msm8x60_fusn_ffa())
7306 mach_mask = I2C_FFA;
7307 else if (machine_is_msm8x60_rumi3())
7308 mach_mask = I2C_RUMI;
7309 else if (machine_is_msm8x60_sim())
7310 mach_mask = I2C_SIM;
7311 else if (machine_is_msm8x60_fluid())
7312 mach_mask = I2C_FLUID;
Zhang Chang Ken6baadf02011-08-05 09:48:15 -04007313 else if (machine_is_msm8x60_dragon())
7314 mach_mask = I2C_DRAGON;
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07007315 else
7316 pr_err("unmatched machine ID in register_i2c_devices\n");
7317
7318 /* Run the array and install devices as appropriate */
7319 for (i = 0; i < ARRAY_SIZE(msm8x60_i2c_devices); ++i) {
7320 if (msm8x60_i2c_devices[i].machs & mach_mask)
7321 i2c_register_board_info(msm8x60_i2c_devices[i].bus,
7322 msm8x60_i2c_devices[i].info,
7323 msm8x60_i2c_devices[i].len);
7324 }
7325#endif
7326}
7327
7328static void __init msm8x60_init_uart12dm(void)
7329{
7330#if !defined(CONFIG_USB_PEHCI_HCD) && !defined(CONFIG_USB_PEHCI_HCD_MODULE)
7331 /* 0x1D000000 now belongs to EBI2:CS3 i.e. USB ISP Controller */
7332 void *fpga_mem = ioremap_nocache(0x1D000000, SZ_4K);
7333
7334 if (!fpga_mem)
7335 pr_err("%s(): Error getting memory\n", __func__);
7336
7337 /* Advanced mode */
7338 writew(0xFFFF, fpga_mem + 0x15C);
7339 /* FPGA_UART_SEL */
7340 writew(0, fpga_mem + 0x172);
7341 /* FPGA_GPIO_CONFIG_117 */
7342 writew(1, fpga_mem + 0xEA);
7343 /* FPGA_GPIO_CONFIG_118 */
7344 writew(1, fpga_mem + 0xEC);
7345 mb();
7346 iounmap(fpga_mem);
7347#endif
7348}
7349
7350#define MSM_GSBI9_PHYS 0x19900000
7351#define GSBI_DUAL_MODE_CODE 0x60
7352
7353static void __init msm8x60_init_buses(void)
7354{
7355#ifdef CONFIG_I2C_QUP
7356 void *gsbi_mem = ioremap_nocache(0x19C00000, 4);
7357 /* Setting protocol code to 0x60 for dual UART/I2C in GSBI12 */
7358 writel_relaxed(0x6 << 4, gsbi_mem);
7359 /* Ensure protocol code is written before proceeding further */
7360 mb();
7361 iounmap(gsbi_mem);
7362
7363 msm_gsbi3_qup_i2c_device.dev.platform_data = &msm_gsbi3_qup_i2c_pdata;
7364 msm_gsbi4_qup_i2c_device.dev.platform_data = &msm_gsbi4_qup_i2c_pdata;
7365 msm_gsbi7_qup_i2c_device.dev.platform_data = &msm_gsbi7_qup_i2c_pdata;
7366 msm_gsbi8_qup_i2c_device.dev.platform_data = &msm_gsbi8_qup_i2c_pdata;
7367
7368#ifdef CONFIG_MSM_GSBI9_UART
7369 if (machine_is_msm8x60_fusion() || machine_is_msm8x60_fusn_ffa()) {
7370 /* Setting protocol code to 0x60 for dual UART/I2C in GSBI9 */
7371 gsbi_mem = ioremap_nocache(MSM_GSBI9_PHYS, 4);
7372 writel_relaxed(GSBI_DUAL_MODE_CODE, gsbi_mem);
7373 iounmap(gsbi_mem);
7374 msm_gsbi9_qup_i2c_pdata.use_gsbi_shared_mode = 1;
7375 }
7376#endif
7377 msm_gsbi9_qup_i2c_device.dev.platform_data = &msm_gsbi9_qup_i2c_pdata;
7378 msm_gsbi12_qup_i2c_device.dev.platform_data = &msm_gsbi12_qup_i2c_pdata;
7379#endif
7380#if defined(CONFIG_SPI_QUP) || defined(CONFIG_SPI_QUP_MODULE)
7381 msm_gsbi1_qup_spi_device.dev.platform_data = &msm_gsbi1_qup_spi_pdata;
7382#endif
7383#ifdef CONFIG_I2C_SSBI
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07007384 msm_device_ssbi2.dev.platform_data = &msm_ssbi2_pdata;
7385 msm_device_ssbi3.dev.platform_data = &msm_ssbi3_pdata;
7386#endif
7387
Anirudh Ghayal9d9cdc22011-10-10 17:17:07 +05307388#ifdef CONFIG_MSM_SSBI
7389 msm_device_ssbi_pmic1.dev.platform_data =
7390 &msm8x60_ssbi_pm8058_pdata;
7391#endif
7392
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07007393 if (machine_is_msm8x60_fluid()) {
7394#if (defined(CONFIG_USB_EHCI_MSM_72K) && \
7395 (defined(CONFIG_SMB137B_CHARGER) || \
7396 defined(CONFIG_SMB137B_CHARGER_MODULE)))
7397 msm_otg_pdata.vbus_power = msm_hsusb_smb137b_vbus_power;
7398#endif
7399#if defined(CONFIG_SPI_QUP) || defined(CONFIG_SPI_QUP_MODULE)
7400 msm_gsbi10_qup_spi_device.dev.platform_data =
7401 &msm_gsbi10_qup_spi_pdata;
7402#endif
7403 }
7404
7405#if defined(CONFIG_USB_GADGET_MSM_72K) || defined(CONFIG_USB_EHCI_HCD)
7406 /*
7407 * We can not put USB regulators (8058_l6 and 8058_l7) in LPM
7408 * when we depend on USB PHY for VBUS/ID notifications. VBUS
7409 * and ID notifications are available only on V2 surf and FFA
7410 * with a hardware workaround.
7411 */
7412 if (SOCINFO_VERSION_MAJOR(socinfo_get_version()) == 2 &&
7413 (machine_is_msm8x60_surf() ||
7414 (machine_is_msm8x60_ffa() &&
7415 pmic_id_notif_supported)))
7416 msm_otg_pdata.phy_can_powercollapse = 1;
7417 msm_device_otg.dev.platform_data = &msm_otg_pdata;
7418#endif
7419
7420#ifdef CONFIG_USB_GADGET_MSM_72K
7421 msm_device_gadget_peripheral.dev.platform_data = &msm_gadget_pdata;
7422#endif
7423
7424#ifdef CONFIG_SERIAL_MSM_HS
7425 msm_uart_dm1_pdata.wakeup_irq = gpio_to_irq(54); /* GSBI6(2) */
7426 msm_device_uart_dm1.dev.platform_data = &msm_uart_dm1_pdata;
7427#endif
7428#ifdef CONFIG_MSM_GSBI9_UART
7429 if (machine_is_msm8x60_fusion() || machine_is_msm8x60_fusn_ffa()) {
7430 msm_device_uart_gsbi9 = msm_add_gsbi9_uart();
7431 if (IS_ERR(msm_device_uart_gsbi9))
7432 pr_err("%s(): Failed to create uart gsbi9 device\n",
7433 __func__);
7434 }
7435#endif
7436
7437#ifdef CONFIG_MSM_BUS_SCALING
7438
7439 /* RPM calls are only enabled on V2 */
7440 if (SOCINFO_VERSION_MAJOR(socinfo_get_version()) == 2) {
7441 msm_bus_apps_fabric_pdata.rpm_enabled = 1;
7442 msm_bus_sys_fabric_pdata.rpm_enabled = 1;
7443 msm_bus_mm_fabric_pdata.rpm_enabled = 1;
7444 msm_bus_sys_fpb_pdata.rpm_enabled = 1;
7445 msm_bus_cpss_fpb_pdata.rpm_enabled = 1;
7446 }
7447
7448 msm_bus_apps_fabric.dev.platform_data = &msm_bus_apps_fabric_pdata;
7449 msm_bus_sys_fabric.dev.platform_data = &msm_bus_sys_fabric_pdata;
7450 msm_bus_mm_fabric.dev.platform_data = &msm_bus_mm_fabric_pdata;
7451 msm_bus_sys_fpb.dev.platform_data = &msm_bus_sys_fpb_pdata;
7452 msm_bus_cpss_fpb.dev.platform_data = &msm_bus_cpss_fpb_pdata;
7453#endif
7454}
7455
7456static void __init msm8x60_map_io(void)
7457{
7458 msm_shared_ram_phys = MSM_SHARED_RAM_PHYS;
7459 msm_map_msm8x60_io();
Jeff Ohlstein3a77f9f2011-09-06 14:50:20 -07007460
7461 if (socinfo_init() < 0)
7462 pr_err("socinfo_init() failed!\n");
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07007463}
7464
7465/*
7466 * Most segments of the EBI2 bus are disabled by default.
7467 */
7468static void __init msm8x60_init_ebi2(void)
7469{
7470 uint32_t ebi2_cfg;
7471 void *ebi2_cfg_ptr;
Terence Hampsonb36a38c2011-09-19 19:10:40 -04007472 struct clk *mem_clk = clk_get_sys("msm_ebi2", "mem_clk");
7473
7474 if (IS_ERR(mem_clk)) {
7475 pr_err("%s: clk_get_sys(%s,%s), failed", __func__,
7476 "msm_ebi2", "mem_clk");
7477 return;
7478 }
7479 clk_enable(mem_clk);
7480 clk_put(mem_clk);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07007481
7482 ebi2_cfg_ptr = ioremap_nocache(0x1a100000, sizeof(uint32_t));
7483 if (ebi2_cfg_ptr != 0) {
7484 ebi2_cfg = readl_relaxed(ebi2_cfg_ptr);
7485
7486 if (machine_is_msm8x60_surf() || machine_is_msm8x60_ffa() ||
Zhang Chang Ken6baadf02011-08-05 09:48:15 -04007487 machine_is_msm8x60_fluid() ||
7488 machine_is_msm8x60_dragon())
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07007489 ebi2_cfg |= (1 << 4) | (1 << 5); /* CS2, CS3 */
7490 else if (machine_is_msm8x60_sim())
7491 ebi2_cfg |= (1 << 4); /* CS2 */
7492 else if (machine_is_msm8x60_rumi3())
7493 ebi2_cfg |= (1 << 5); /* CS3 */
7494
7495 writel_relaxed(ebi2_cfg, ebi2_cfg_ptr);
7496 iounmap(ebi2_cfg_ptr);
7497 }
7498
7499 if (machine_is_msm8x60_surf() || machine_is_msm8x60_ffa() ||
Zhang Chang Ken6baadf02011-08-05 09:48:15 -04007500 machine_is_msm8x60_fluid() || machine_is_msm8x60_dragon()) {
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07007501 ebi2_cfg_ptr = ioremap_nocache(0x1a110000, SZ_4K);
7502 if (ebi2_cfg_ptr != 0) {
7503 /* EBI2_XMEM_CFG:PWRSAVE_MODE off */
7504 writel_relaxed(0UL, ebi2_cfg_ptr);
7505
7506 /* CS2: Delay 9 cycles (140ns@64MHz) between SMSC
7507 * LAN9221 Ethernet controller reads and writes.
7508 * The lowest 4 bits are the read delay, the next
7509 * 4 are the write delay. */
7510 writel_relaxed(0x031F1C99, ebi2_cfg_ptr + 0x10);
7511#if defined(CONFIG_USB_PEHCI_HCD) || defined(CONFIG_USB_PEHCI_HCD_MODULE)
7512 /*
7513 * RECOVERY=5, HOLD_WR=1
7514 * INIT_LATENCY_WR=1, INIT_LATENCY_RD=1
7515 * WAIT_WR=1, WAIT_RD=2
7516 */
7517 writel_relaxed(0x51010112, ebi2_cfg_ptr + 0x14);
7518 /*
7519 * HOLD_RD=1
7520 * ADV_OE_RECOVERY=0, ADDR_HOLD_ENA=1
7521 */
7522 writel_relaxed(0x01000020, ebi2_cfg_ptr + 0x34);
7523#else
7524 /* EBI2 CS3 muxed address/data,
7525 * two cyc addr enable */
7526 writel_relaxed(0xA3030020, ebi2_cfg_ptr + 0x34);
7527
7528#endif
7529 iounmap(ebi2_cfg_ptr);
7530 }
7531 }
7532}
7533
7534static void __init msm8x60_configure_smc91x(void)
7535{
7536 if (machine_is_msm8x60_sim()) {
7537
7538 smc91x_resources[0].start = 0x1b800300;
7539 smc91x_resources[0].end = 0x1b8003ff;
7540
7541 smc91x_resources[1].start = (NR_MSM_IRQS + 40);
7542 smc91x_resources[1].end = (NR_MSM_IRQS + 40);
7543
7544 } else if (machine_is_msm8x60_rumi3()) {
7545
7546 smc91x_resources[0].start = 0x1d000300;
7547 smc91x_resources[0].end = 0x1d0003ff;
7548
7549 smc91x_resources[1].start = TLMM_MSM_DIR_CONN_IRQ_0;
7550 smc91x_resources[1].end = TLMM_MSM_DIR_CONN_IRQ_0;
7551 }
7552}
7553
7554static void __init msm8x60_init_tlmm(void)
7555{
7556 if (machine_is_msm8x60_rumi3())
7557 msm_gpio_install_direct_irq(0, 0, 1);
7558}
7559
7560#if (defined(CONFIG_MMC_MSM_SDC1_SUPPORT)\
7561 || defined(CONFIG_MMC_MSM_SDC2_SUPPORT)\
7562 || defined(CONFIG_MMC_MSM_SDC3_SUPPORT)\
7563 || defined(CONFIG_MMC_MSM_SDC4_SUPPORT)\
7564 || defined(CONFIG_MMC_MSM_SDC5_SUPPORT))
7565
7566/* 8x60 is having 5 SDCC controllers */
7567#define MAX_SDCC_CONTROLLER 5
7568
7569struct msm_sdcc_gpio {
7570 /* maximum 10 GPIOs per SDCC controller */
7571 s16 no;
7572 /* name of this GPIO */
7573 const char *name;
7574 bool always_on;
7575 bool is_enabled;
7576};
7577
7578#ifdef CONFIG_MMC_MSM_SDC1_SUPPORT
7579static struct msm_sdcc_gpio sdc1_gpio_cfg[] = {
7580 {159, "sdc1_dat_0"},
7581 {160, "sdc1_dat_1"},
7582 {161, "sdc1_dat_2"},
7583 {162, "sdc1_dat_3"},
7584#ifdef CONFIG_MMC_MSM_SDC1_8_BIT_SUPPORT
7585 {163, "sdc1_dat_4"},
7586 {164, "sdc1_dat_5"},
7587 {165, "sdc1_dat_6"},
7588 {166, "sdc1_dat_7"},
7589#endif
7590 {167, "sdc1_clk"},
7591 {168, "sdc1_cmd"}
7592};
7593#endif
7594
7595#ifdef CONFIG_MMC_MSM_SDC2_SUPPORT
7596static struct msm_sdcc_gpio sdc2_gpio_cfg[] = {
7597 {143, "sdc2_dat_0"},
7598 {144, "sdc2_dat_1", 1},
7599 {145, "sdc2_dat_2"},
7600 {146, "sdc2_dat_3"},
7601#ifdef CONFIG_MMC_MSM_SDC2_8_BIT_SUPPORT
7602 {147, "sdc2_dat_4"},
7603 {148, "sdc2_dat_5"},
7604 {149, "sdc2_dat_6"},
7605 {150, "sdc2_dat_7"},
7606#endif
7607 {151, "sdc2_cmd"},
7608 {152, "sdc2_clk", 1}
7609};
7610#endif
7611
7612#ifdef CONFIG_MMC_MSM_SDC5_SUPPORT
7613static struct msm_sdcc_gpio sdc5_gpio_cfg[] = {
7614 {95, "sdc5_cmd"},
7615 {96, "sdc5_dat_3"},
7616 {97, "sdc5_clk", 1},
7617 {98, "sdc5_dat_2"},
7618 {99, "sdc5_dat_1", 1},
7619 {100, "sdc5_dat_0"}
7620};
7621#endif
7622
7623struct msm_sdcc_pad_pull_cfg {
7624 enum msm_tlmm_pull_tgt pull;
7625 u32 pull_val;
7626};
7627
7628struct msm_sdcc_pad_drv_cfg {
7629 enum msm_tlmm_hdrive_tgt drv;
7630 u32 drv_val;
7631};
7632
7633#ifdef CONFIG_MMC_MSM_SDC3_SUPPORT
7634static struct msm_sdcc_pad_drv_cfg sdc3_pad_on_drv_cfg[] = {
7635 {TLMM_HDRV_SDC3_CLK, GPIO_CFG_8MA},
7636 {TLMM_HDRV_SDC3_CMD, GPIO_CFG_8MA},
7637 {TLMM_HDRV_SDC3_DATA, GPIO_CFG_8MA}
7638};
7639
7640static struct msm_sdcc_pad_pull_cfg sdc3_pad_on_pull_cfg[] = {
7641 {TLMM_PULL_SDC3_CMD, GPIO_CFG_PULL_UP},
7642 {TLMM_PULL_SDC3_DATA, GPIO_CFG_PULL_UP}
7643};
7644
7645static struct msm_sdcc_pad_drv_cfg sdc3_pad_off_drv_cfg[] = {
7646 {TLMM_HDRV_SDC3_CLK, GPIO_CFG_2MA},
7647 {TLMM_HDRV_SDC3_CMD, GPIO_CFG_2MA},
7648 {TLMM_HDRV_SDC3_DATA, GPIO_CFG_2MA}
7649};
7650
7651static struct msm_sdcc_pad_pull_cfg sdc3_pad_off_pull_cfg[] = {
7652 {TLMM_PULL_SDC3_CMD, GPIO_CFG_PULL_DOWN},
7653 {TLMM_PULL_SDC3_DATA, GPIO_CFG_PULL_DOWN}
7654};
7655#endif
7656
7657#ifdef CONFIG_MMC_MSM_SDC4_SUPPORT
7658static struct msm_sdcc_pad_drv_cfg sdc4_pad_on_drv_cfg[] = {
7659 {TLMM_HDRV_SDC4_CLK, GPIO_CFG_8MA},
7660 {TLMM_HDRV_SDC4_CMD, GPIO_CFG_8MA},
7661 {TLMM_HDRV_SDC4_DATA, GPIO_CFG_8MA}
7662};
7663
7664static struct msm_sdcc_pad_pull_cfg sdc4_pad_on_pull_cfg[] = {
7665 {TLMM_PULL_SDC4_CMD, GPIO_CFG_PULL_UP},
7666 {TLMM_PULL_SDC4_DATA, GPIO_CFG_PULL_UP}
7667};
7668
7669static struct msm_sdcc_pad_drv_cfg sdc4_pad_off_drv_cfg[] = {
7670 {TLMM_HDRV_SDC4_CLK, GPIO_CFG_2MA},
7671 {TLMM_HDRV_SDC4_CMD, GPIO_CFG_2MA},
7672 {TLMM_HDRV_SDC4_DATA, GPIO_CFG_2MA}
7673};
7674
7675static struct msm_sdcc_pad_pull_cfg sdc4_pad_off_pull_cfg[] = {
7676 {TLMM_PULL_SDC4_CMD, GPIO_CFG_PULL_DOWN},
7677 {TLMM_PULL_SDC4_DATA, GPIO_CFG_PULL_DOWN}
7678};
7679#endif
7680
7681struct msm_sdcc_pin_cfg {
7682 /*
7683 * = 1 if controller pins are using gpios
7684 * = 0 if controller has dedicated MSM pins
7685 */
7686 u8 is_gpio;
7687 u8 cfg_sts;
7688 u8 gpio_data_size;
7689 struct msm_sdcc_gpio *gpio_data;
7690 struct msm_sdcc_pad_drv_cfg *pad_drv_on_data;
7691 struct msm_sdcc_pad_drv_cfg *pad_drv_off_data;
7692 struct msm_sdcc_pad_pull_cfg *pad_pull_on_data;
7693 struct msm_sdcc_pad_pull_cfg *pad_pull_off_data;
7694 u8 pad_drv_data_size;
7695 u8 pad_pull_data_size;
7696 u8 sdio_lpm_gpio_cfg;
7697};
7698
7699
7700static struct msm_sdcc_pin_cfg sdcc_pin_cfg_data[MAX_SDCC_CONTROLLER] = {
7701#ifdef CONFIG_MMC_MSM_SDC1_SUPPORT
7702 [0] = {
7703 .is_gpio = 1,
7704 .gpio_data_size = ARRAY_SIZE(sdc1_gpio_cfg),
7705 .gpio_data = sdc1_gpio_cfg
7706 },
7707#endif
7708#ifdef CONFIG_MMC_MSM_SDC2_SUPPORT
7709 [1] = {
7710 .is_gpio = 1,
7711 .gpio_data_size = ARRAY_SIZE(sdc2_gpio_cfg),
7712 .gpio_data = sdc2_gpio_cfg
7713 },
7714#endif
7715#ifdef CONFIG_MMC_MSM_SDC3_SUPPORT
7716 [2] = {
7717 .is_gpio = 0,
7718 .pad_drv_on_data = sdc3_pad_on_drv_cfg,
7719 .pad_drv_off_data = sdc3_pad_off_drv_cfg,
7720 .pad_pull_on_data = sdc3_pad_on_pull_cfg,
7721 .pad_pull_off_data = sdc3_pad_off_pull_cfg,
7722 .pad_drv_data_size = ARRAY_SIZE(sdc3_pad_on_drv_cfg),
7723 .pad_pull_data_size = ARRAY_SIZE(sdc3_pad_on_pull_cfg)
7724 },
7725#endif
7726#ifdef CONFIG_MMC_MSM_SDC4_SUPPORT
7727 [3] = {
7728 .is_gpio = 0,
7729 .pad_drv_on_data = sdc4_pad_on_drv_cfg,
7730 .pad_drv_off_data = sdc4_pad_off_drv_cfg,
7731 .pad_pull_on_data = sdc4_pad_on_pull_cfg,
7732 .pad_pull_off_data = sdc4_pad_off_pull_cfg,
7733 .pad_drv_data_size = ARRAY_SIZE(sdc4_pad_on_drv_cfg),
7734 .pad_pull_data_size = ARRAY_SIZE(sdc4_pad_on_pull_cfg)
7735 },
7736#endif
7737#ifdef CONFIG_MMC_MSM_SDC5_SUPPORT
7738 [4] = {
7739 .is_gpio = 1,
7740 .gpio_data_size = ARRAY_SIZE(sdc5_gpio_cfg),
7741 .gpio_data = sdc5_gpio_cfg
7742 }
7743#endif
7744};
7745
7746static int msm_sdcc_setup_gpio(int dev_id, unsigned int enable)
7747{
7748 int rc = 0;
7749 struct msm_sdcc_pin_cfg *curr;
7750 int n;
7751
7752 curr = &sdcc_pin_cfg_data[dev_id - 1];
7753 if (!curr->gpio_data)
7754 goto out;
7755
7756 for (n = 0; n < curr->gpio_data_size; n++) {
7757 if (enable) {
7758
7759 if (curr->gpio_data[n].always_on &&
7760 curr->gpio_data[n].is_enabled)
7761 continue;
7762 pr_debug("%s: enable: %s\n", __func__,
7763 curr->gpio_data[n].name);
7764 rc = gpio_request(curr->gpio_data[n].no,
7765 curr->gpio_data[n].name);
7766 if (rc) {
7767 pr_err("%s: gpio_request(%d, %s)"
7768 "failed", __func__,
7769 curr->gpio_data[n].no,
7770 curr->gpio_data[n].name);
7771 goto free_gpios;
7772 }
7773 /* set direction as output for all GPIOs */
7774 rc = gpio_direction_output(
7775 curr->gpio_data[n].no, 1);
7776 if (rc) {
7777 pr_err("%s: gpio_direction_output"
7778 "(%d, 1) failed\n", __func__,
7779 curr->gpio_data[n].no);
7780 goto free_gpios;
7781 }
7782 curr->gpio_data[n].is_enabled = 1;
7783 } else {
7784 /*
7785 * now free this GPIO which will put GPIO
7786 * in low power mode and will also put GPIO
7787 * in input mode
7788 */
7789 if (curr->gpio_data[n].always_on)
7790 continue;
7791 pr_debug("%s: disable: %s\n", __func__,
7792 curr->gpio_data[n].name);
7793 gpio_free(curr->gpio_data[n].no);
7794 curr->gpio_data[n].is_enabled = 0;
7795 }
7796 }
7797 curr->cfg_sts = enable;
7798 goto out;
7799
7800free_gpios:
7801 for (; n >= 0; n--)
7802 gpio_free(curr->gpio_data[n].no);
7803out:
7804 return rc;
7805}
7806
7807static int msm_sdcc_setup_pad(int dev_id, unsigned int enable)
7808{
7809 int rc = 0;
7810 struct msm_sdcc_pin_cfg *curr;
7811 int n;
7812
7813 curr = &sdcc_pin_cfg_data[dev_id - 1];
7814 if (!curr->pad_drv_on_data || !curr->pad_pull_on_data)
7815 goto out;
7816
7817 if (enable) {
7818 /*
7819 * set up the normal driver strength and
7820 * pull config for pads
7821 */
7822 for (n = 0; n < curr->pad_drv_data_size; n++) {
7823 if (curr->sdio_lpm_gpio_cfg) {
7824 if (curr->pad_drv_on_data[n].drv ==
7825 TLMM_HDRV_SDC4_DATA)
7826 continue;
7827 }
7828 msm_tlmm_set_hdrive(curr->pad_drv_on_data[n].drv,
7829 curr->pad_drv_on_data[n].drv_val);
7830 }
7831 for (n = 0; n < curr->pad_pull_data_size; n++) {
7832 if (curr->sdio_lpm_gpio_cfg) {
7833 if (curr->pad_pull_on_data[n].pull ==
7834 TLMM_PULL_SDC4_DATA)
7835 continue;
7836 }
7837 msm_tlmm_set_pull(curr->pad_pull_on_data[n].pull,
7838 curr->pad_pull_on_data[n].pull_val);
7839 }
7840 } else {
7841 /* set the low power config for pads */
7842 for (n = 0; n < curr->pad_drv_data_size; n++) {
7843 if (curr->sdio_lpm_gpio_cfg) {
7844 if (curr->pad_drv_off_data[n].drv ==
7845 TLMM_HDRV_SDC4_DATA)
7846 continue;
7847 }
7848 msm_tlmm_set_hdrive(
7849 curr->pad_drv_off_data[n].drv,
7850 curr->pad_drv_off_data[n].drv_val);
7851 }
7852 for (n = 0; n < curr->pad_pull_data_size; n++) {
7853 if (curr->sdio_lpm_gpio_cfg) {
7854 if (curr->pad_pull_off_data[n].pull ==
7855 TLMM_PULL_SDC4_DATA)
7856 continue;
7857 }
7858 msm_tlmm_set_pull(
7859 curr->pad_pull_off_data[n].pull,
7860 curr->pad_pull_off_data[n].pull_val);
7861 }
7862 }
7863 curr->cfg_sts = enable;
7864out:
7865 return rc;
7866}
7867
7868struct sdcc_reg {
7869 /* VDD/VCC/VCCQ regulator name on PMIC8058/PMIC8089*/
7870 const char *reg_name;
7871 /*
7872 * is set voltage supported for this regulator?
7873 * 0 = not supported, 1 = supported
7874 */
7875 unsigned char set_voltage_sup;
7876 /* voltage level to be set */
7877 unsigned int level;
7878 /* VDD/VCC/VCCQ voltage regulator handle */
7879 struct regulator *reg;
7880 /* is this regulator enabled? */
7881 bool enabled;
7882 /* is this regulator needs to be always on? */
7883 bool always_on;
7884 /* is operating power mode setting required for this regulator? */
7885 bool op_pwr_mode_sup;
7886 /* Load values for low power and high power mode */
7887 unsigned int lpm_uA;
7888 unsigned int hpm_uA;
7889};
7890/* all SDCC controllers requires VDD/VCC voltage */
7891static struct sdcc_reg sdcc_vdd_reg_data[MAX_SDCC_CONTROLLER];
7892/* only SDCC1 requires VCCQ voltage */
7893static struct sdcc_reg sdcc_vccq_reg_data[1];
7894/* all SDCC controllers may require voting for VDD PAD voltage */
7895static struct sdcc_reg sdcc_vddp_reg_data[MAX_SDCC_CONTROLLER];
7896
7897struct sdcc_reg_data {
7898 struct sdcc_reg *vdd_data; /* keeps VDD/VCC regulator info */
7899 struct sdcc_reg *vccq_data; /* keeps VCCQ regulator info */
7900 struct sdcc_reg *vddp_data; /* keeps VDD Pad regulator info */
7901 unsigned char sts; /* regulator enable/disable status */
7902};
7903/* msm8x60 have 5 SDCC controllers */
7904static struct sdcc_reg_data sdcc_vreg_data[MAX_SDCC_CONTROLLER];
7905
7906static int msm_sdcc_vreg_init_reg(struct sdcc_reg *vreg)
7907{
7908 int rc = 0;
7909
7910 /* Get the regulator handle */
7911 vreg->reg = regulator_get(NULL, vreg->reg_name);
7912 if (IS_ERR(vreg->reg)) {
7913 rc = PTR_ERR(vreg->reg);
7914 pr_err("%s: regulator_get(%s) failed. rc=%d\n",
7915 __func__, vreg->reg_name, rc);
7916 goto out;
7917 }
7918
7919 /* Set the voltage level if required */
7920 if (vreg->set_voltage_sup) {
7921 rc = regulator_set_voltage(vreg->reg, vreg->level,
7922 vreg->level);
7923 if (rc) {
7924 pr_err("%s: regulator_set_voltage(%s) failed rc=%d\n",
7925 __func__, vreg->reg_name, rc);
7926 goto vreg_put;
7927 }
7928 }
7929 goto out;
7930
7931vreg_put:
7932 regulator_put(vreg->reg);
7933out:
7934 return rc;
7935}
7936
7937static inline void msm_sdcc_vreg_deinit_reg(struct sdcc_reg *vreg)
7938{
7939 regulator_put(vreg->reg);
7940}
7941
7942/* this init function should be called only once for each SDCC */
7943static int msm_sdcc_vreg_init(int dev_id, unsigned char init)
7944{
7945 int rc = 0;
7946 struct sdcc_reg *curr_vdd_reg, *curr_vccq_reg, *curr_vddp_reg;
7947 struct sdcc_reg_data *curr;
7948
7949 curr = &sdcc_vreg_data[dev_id - 1];
7950 curr_vdd_reg = curr->vdd_data;
7951 curr_vccq_reg = curr->vccq_data;
7952 curr_vddp_reg = curr->vddp_data;
7953
7954 if (init) {
7955 /*
7956 * get the regulator handle from voltage regulator framework
7957 * and then try to set the voltage level for the regulator
7958 */
7959 if (curr_vdd_reg) {
7960 rc = msm_sdcc_vreg_init_reg(curr_vdd_reg);
7961 if (rc)
7962 goto out;
7963 }
7964 if (curr_vccq_reg) {
7965 rc = msm_sdcc_vreg_init_reg(curr_vccq_reg);
7966 if (rc)
7967 goto vdd_reg_deinit;
7968 }
7969 if (curr_vddp_reg) {
7970 rc = msm_sdcc_vreg_init_reg(curr_vddp_reg);
7971 if (rc)
7972 goto vccq_reg_deinit;
7973 }
7974 goto out;
7975 } else
7976 /* deregister with all regulators from regulator framework */
7977 goto vddp_reg_deinit;
7978
7979vddp_reg_deinit:
7980 if (curr_vddp_reg)
7981 msm_sdcc_vreg_deinit_reg(curr_vddp_reg);
7982vccq_reg_deinit:
7983 if (curr_vccq_reg)
7984 msm_sdcc_vreg_deinit_reg(curr_vccq_reg);
7985vdd_reg_deinit:
7986 if (curr_vdd_reg)
7987 msm_sdcc_vreg_deinit_reg(curr_vdd_reg);
7988out:
7989 return rc;
7990}
7991
7992static int msm_sdcc_vreg_enable(struct sdcc_reg *vreg)
7993{
7994 int rc;
7995
7996 if (!vreg->enabled) {
7997 rc = regulator_enable(vreg->reg);
7998 if (rc) {
7999 pr_err("%s: regulator_enable(%s) failed. rc=%d\n",
8000 __func__, vreg->reg_name, rc);
8001 goto out;
8002 }
8003 vreg->enabled = 1;
8004 }
8005
8006 /* Put always_on regulator in HPM (high power mode) */
8007 if (vreg->always_on && vreg->op_pwr_mode_sup) {
8008 rc = regulator_set_optimum_mode(vreg->reg, vreg->hpm_uA);
8009 if (rc < 0) {
8010 pr_err("%s: reg=%s: HPM setting failed"
8011 " hpm_uA=%d, rc=%d\n",
8012 __func__, vreg->reg_name,
8013 vreg->hpm_uA, rc);
8014 goto vreg_disable;
8015 }
8016 rc = 0;
8017 }
8018 goto out;
8019
8020vreg_disable:
8021 regulator_disable(vreg->reg);
8022 vreg->enabled = 0;
8023out:
8024 return rc;
8025}
8026
8027static int msm_sdcc_vreg_disable(struct sdcc_reg *vreg)
8028{
8029 int rc;
8030
8031 /* Never disable always_on regulator */
8032 if (!vreg->always_on) {
8033 rc = regulator_disable(vreg->reg);
8034 if (rc) {
8035 pr_err("%s: regulator_disable(%s) failed. rc=%d\n",
8036 __func__, vreg->reg_name, rc);
8037 goto out;
8038 }
8039 vreg->enabled = 0;
8040 }
8041
8042 /* Put always_on regulator in LPM (low power mode) */
8043 if (vreg->always_on && vreg->op_pwr_mode_sup) {
8044 rc = regulator_set_optimum_mode(vreg->reg, vreg->lpm_uA);
8045 if (rc < 0) {
8046 pr_err("%s: reg=%s: LPM setting failed"
8047 " lpm_uA=%d, rc=%d\n",
8048 __func__,
8049 vreg->reg_name,
8050 vreg->lpm_uA, rc);
8051 goto out;
8052 }
8053 rc = 0;
8054 }
8055
8056out:
8057 return rc;
8058}
8059
8060static int msm_sdcc_setup_vreg(int dev_id, unsigned char enable)
8061{
8062 int rc = 0;
8063 struct sdcc_reg *curr_vdd_reg, *curr_vccq_reg, *curr_vddp_reg;
8064 struct sdcc_reg_data *curr;
8065
8066 curr = &sdcc_vreg_data[dev_id - 1];
8067 curr_vdd_reg = curr->vdd_data;
8068 curr_vccq_reg = curr->vccq_data;
8069 curr_vddp_reg = curr->vddp_data;
8070
8071 /* check if regulators are initialized or not? */
8072 if ((curr_vdd_reg && !curr_vdd_reg->reg) ||
8073 (curr_vccq_reg && !curr_vccq_reg->reg) ||
8074 (curr_vddp_reg && !curr_vddp_reg->reg)) {
8075 /* initialize voltage regulators required for this SDCC */
8076 rc = msm_sdcc_vreg_init(dev_id, 1);
8077 if (rc) {
8078 pr_err("%s: regulator init failed = %d\n",
8079 __func__, rc);
8080 goto out;
8081 }
8082 }
8083
8084 if (curr->sts == enable)
8085 goto out;
8086
8087 if (curr_vdd_reg) {
8088 if (enable)
8089 rc = msm_sdcc_vreg_enable(curr_vdd_reg);
8090 else
8091 rc = msm_sdcc_vreg_disable(curr_vdd_reg);
8092 if (rc)
8093 goto out;
8094 }
8095
8096 if (curr_vccq_reg) {
8097 if (enable)
8098 rc = msm_sdcc_vreg_enable(curr_vccq_reg);
8099 else
8100 rc = msm_sdcc_vreg_disable(curr_vccq_reg);
8101 if (rc)
8102 goto out;
8103 }
8104
8105 if (curr_vddp_reg) {
8106 if (enable)
8107 rc = msm_sdcc_vreg_enable(curr_vddp_reg);
8108 else
8109 rc = msm_sdcc_vreg_disable(curr_vddp_reg);
8110 if (rc)
8111 goto out;
8112 }
8113 curr->sts = enable;
8114
8115out:
8116 return rc;
8117}
8118
8119static u32 msm_sdcc_setup_power(struct device *dv, unsigned int vdd)
8120{
8121 u32 rc_pin_cfg = 0;
8122 u32 rc_vreg_cfg = 0;
8123 u32 rc = 0;
8124 struct platform_device *pdev;
8125 struct msm_sdcc_pin_cfg *curr_pin_cfg;
8126
8127 pdev = container_of(dv, struct platform_device, dev);
8128
8129 /* setup gpio/pad */
8130 curr_pin_cfg = &sdcc_pin_cfg_data[pdev->id - 1];
8131 if (curr_pin_cfg->cfg_sts == !!vdd)
8132 goto setup_vreg;
8133
8134 if (curr_pin_cfg->is_gpio)
8135 rc_pin_cfg = msm_sdcc_setup_gpio(pdev->id, !!vdd);
8136 else
8137 rc_pin_cfg = msm_sdcc_setup_pad(pdev->id, !!vdd);
8138
8139setup_vreg:
8140 /* setup voltage regulators */
8141 rc_vreg_cfg = msm_sdcc_setup_vreg(pdev->id, !!vdd);
8142
8143 if (rc_pin_cfg || rc_vreg_cfg)
8144 rc = rc_pin_cfg ? rc_pin_cfg : rc_vreg_cfg;
8145
8146 return rc;
8147}
8148
8149static void msm_sdcc_sdio_lpm_gpio(struct device *dv, unsigned int active)
8150{
8151 struct msm_sdcc_pin_cfg *curr_pin_cfg;
8152 struct platform_device *pdev;
8153
8154 pdev = container_of(dv, struct platform_device, dev);
8155 /* setup gpio/pad */
8156 curr_pin_cfg = &sdcc_pin_cfg_data[pdev->id - 1];
8157
8158 if (curr_pin_cfg->cfg_sts == active)
8159 return;
8160
8161 curr_pin_cfg->sdio_lpm_gpio_cfg = 1;
8162 if (curr_pin_cfg->is_gpio)
8163 msm_sdcc_setup_gpio(pdev->id, active);
8164 else
8165 msm_sdcc_setup_pad(pdev->id, active);
8166 curr_pin_cfg->sdio_lpm_gpio_cfg = 0;
8167}
8168
8169static int msm_sdc3_get_wpswitch(struct device *dev)
8170{
8171 struct platform_device *pdev;
8172 int status;
8173 pdev = container_of(dev, struct platform_device, dev);
8174
8175 status = gpio_request(GPIO_SDC_WP, "SD_WP_Switch");
8176 if (status) {
8177 pr_err("%s:Failed to request GPIO %d\n",
8178 __func__, GPIO_SDC_WP);
8179 } else {
8180 status = gpio_direction_input(GPIO_SDC_WP);
8181 if (!status) {
8182 status = gpio_get_value_cansleep(GPIO_SDC_WP);
8183 pr_info("%s: WP Status for Slot %d = %d\n",
8184 __func__, pdev->id, status);
8185 }
8186 gpio_free(GPIO_SDC_WP);
8187 }
8188 return status;
8189}
8190
8191#ifdef CONFIG_MMC_MSM_SDC5_SUPPORT
8192int sdc5_register_status_notify(void (*callback)(int, void *),
8193 void *dev_id)
8194{
8195 sdc5_status_notify_cb = callback;
8196 sdc5_status_notify_cb_devid = dev_id;
8197 return 0;
8198}
8199#endif
8200
8201#ifdef CONFIG_MMC_MSM_SDC2_SUPPORT
8202int sdc2_register_status_notify(void (*callback)(int, void *),
8203 void *dev_id)
8204{
8205 sdc2_status_notify_cb = callback;
8206 sdc2_status_notify_cb_devid = dev_id;
8207 return 0;
8208}
8209#endif
8210
8211/* Interrupt handler for SDC2 and SDC5 detection
8212 * This function uses dual-edge interrputs settings in order
8213 * to get SDIO detection when the GPIO is rising and SDIO removal
8214 * when the GPIO is falling */
8215static irqreturn_t msm8x60_multi_sdio_slot_status_irq(int irq, void *dev_id)
8216{
8217 int status;
8218
8219 if (!machine_is_msm8x60_fusion() &&
8220 !machine_is_msm8x60_fusn_ffa())
8221 return IRQ_NONE;
8222
8223 status = gpio_get_value(MDM2AP_SYNC);
8224 pr_info("%s: MDM2AP_SYNC Status = %d\n",
8225 __func__, status);
8226
8227#ifdef CONFIG_MMC_MSM_SDC2_SUPPORT
8228 if (sdc2_status_notify_cb) {
8229 pr_info("%s: calling sdc2_status_notify_cb\n", __func__);
8230 sdc2_status_notify_cb(status,
8231 sdc2_status_notify_cb_devid);
8232 }
8233#endif
8234
8235#ifdef CONFIG_MMC_MSM_SDC5_SUPPORT
8236 if (sdc5_status_notify_cb) {
8237 pr_info("%s: calling sdc5_status_notify_cb\n", __func__);
8238 sdc5_status_notify_cb(status,
8239 sdc5_status_notify_cb_devid);
8240 }
8241#endif
8242 return IRQ_HANDLED;
8243}
8244
8245static int msm8x60_multi_sdio_init(void)
8246{
8247 int ret, irq_num;
8248
8249 if (!machine_is_msm8x60_fusion() &&
8250 !machine_is_msm8x60_fusn_ffa())
8251 return 0;
8252
8253 ret = msm_gpiomux_get(MDM2AP_SYNC);
8254 if (ret) {
8255 pr_err("%s:Failed to request GPIO %d, ret=%d\n",
8256 __func__, MDM2AP_SYNC, ret);
8257 return ret;
8258 }
8259
8260 irq_num = gpio_to_irq(MDM2AP_SYNC);
8261
8262 ret = request_irq(irq_num,
8263 msm8x60_multi_sdio_slot_status_irq,
8264 IRQ_TYPE_EDGE_BOTH,
8265 "sdio_multidetection", NULL);
8266
8267 if (ret) {
8268 pr_err("%s:Failed to request irq, ret=%d\n",
8269 __func__, ret);
8270 return ret;
8271 }
8272
8273 return ret;
8274}
8275
8276#ifdef CONFIG_MMC_MSM_SDC3_SUPPORT
8277#ifdef CONFIG_MMC_MSM_CARD_HW_DETECTION
8278static unsigned int msm8x60_sdcc_slot_status(struct device *dev)
8279{
8280 int status;
8281
8282 status = gpio_request(PM8058_GPIO_PM_TO_SYS(PMIC_GPIO_SDC3_DET - 1)
8283 , "SD_HW_Detect");
8284 if (status) {
8285 pr_err("%s:Failed to request GPIO %d\n", __func__,
8286 PM8058_GPIO_PM_TO_SYS(PMIC_GPIO_SDC3_DET - 1));
8287 } else {
8288 status = gpio_direction_input(
8289 PM8058_GPIO_PM_TO_SYS(PMIC_GPIO_SDC3_DET - 1));
8290 if (!status)
8291 status = !(gpio_get_value_cansleep(
8292 PM8058_GPIO_PM_TO_SYS(PMIC_GPIO_SDC3_DET - 1)));
8293 gpio_free(PM8058_GPIO_PM_TO_SYS(PMIC_GPIO_SDC3_DET - 1));
8294 }
8295 return (unsigned int) status;
8296}
8297#endif
8298#endif
8299
8300#ifdef CONFIG_MMC_MSM_SDC4_SUPPORT
8301static int msm_sdcc_cfg_mpm_sdiowakeup(struct device *dev, unsigned mode)
8302{
8303 struct platform_device *pdev;
8304 enum msm_mpm_pin pin;
8305 int ret = 0;
8306
8307 pdev = container_of(dev, struct platform_device, dev);
8308
8309 /* Only SDCC4 slot connected to WLAN chip has wakeup capability */
8310 if (pdev->id == 4)
8311 pin = MSM_MPM_PIN_SDC4_DAT1;
8312 else
8313 return -EINVAL;
8314
8315 switch (mode) {
8316 case SDC_DAT1_DISABLE:
8317 ret = msm_mpm_enable_pin(pin, 0);
8318 break;
8319 case SDC_DAT1_ENABLE:
8320 ret = msm_mpm_set_pin_type(pin, IRQ_TYPE_LEVEL_LOW);
8321 ret = msm_mpm_enable_pin(pin, 1);
8322 break;
8323 case SDC_DAT1_ENWAKE:
8324 ret = msm_mpm_set_pin_wake(pin, 1);
8325 break;
8326 case SDC_DAT1_DISWAKE:
8327 ret = msm_mpm_set_pin_wake(pin, 0);
8328 break;
8329 default:
8330 ret = -EINVAL;
8331 break;
8332 }
8333 return ret;
8334}
8335#endif
8336#endif
8337
8338#ifdef CONFIG_MMC_MSM_SDC1_SUPPORT
8339static struct mmc_platform_data msm8x60_sdc1_data = {
8340 .ocr_mask = MMC_VDD_27_28 | MMC_VDD_28_29,
8341 .translate_vdd = msm_sdcc_setup_power,
8342#ifdef CONFIG_MMC_MSM_SDC1_8_BIT_SUPPORT
8343 .mmc_bus_width = MMC_CAP_8_BIT_DATA,
8344#else
8345 .mmc_bus_width = MMC_CAP_4_BIT_DATA,
8346#endif
8347 .msmsdcc_fmin = 400000,
8348 .msmsdcc_fmid = 24000000,
8349 .msmsdcc_fmax = 48000000,
8350 .nonremovable = 1,
8351 .pclk_src_dfab = 1,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07008352};
8353#endif
8354
8355#ifdef CONFIG_MMC_MSM_SDC2_SUPPORT
8356static struct mmc_platform_data msm8x60_sdc2_data = {
8357 .ocr_mask = MMC_VDD_27_28 | MMC_VDD_28_29 | MMC_VDD_165_195,
8358 .translate_vdd = msm_sdcc_setup_power,
8359 .sdio_lpm_gpio_setup = msm_sdcc_sdio_lpm_gpio,
8360 .mmc_bus_width = MMC_CAP_8_BIT_DATA,
8361 .msmsdcc_fmin = 400000,
8362 .msmsdcc_fmid = 24000000,
8363 .msmsdcc_fmax = 48000000,
8364 .nonremovable = 0,
8365 .pclk_src_dfab = 1,
8366 .register_status_notify = sdc2_register_status_notify,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07008367#ifdef CONFIG_MSM_SDIO_AL
8368 .is_sdio_al_client = 1,
8369#endif
8370};
8371#endif
8372
8373#ifdef CONFIG_MMC_MSM_SDC3_SUPPORT
8374static struct mmc_platform_data msm8x60_sdc3_data = {
8375 .ocr_mask = MMC_VDD_27_28 | MMC_VDD_28_29,
8376 .translate_vdd = msm_sdcc_setup_power,
8377 .mmc_bus_width = MMC_CAP_4_BIT_DATA,
8378 .wpswitch = msm_sdc3_get_wpswitch,
8379#ifdef CONFIG_MMC_MSM_CARD_HW_DETECTION
8380 .status = msm8x60_sdcc_slot_status,
8381 .status_irq = PM8058_GPIO_IRQ(PM8058_IRQ_BASE,
8382 PMIC_GPIO_SDC3_DET - 1),
8383 .irq_flags = IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING,
8384#endif
8385 .msmsdcc_fmin = 400000,
8386 .msmsdcc_fmid = 24000000,
8387 .msmsdcc_fmax = 48000000,
8388 .nonremovable = 0,
8389 .pclk_src_dfab = 1,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07008390};
8391#endif
8392
8393#ifdef CONFIG_MMC_MSM_SDC4_SUPPORT
8394static struct mmc_platform_data msm8x60_sdc4_data = {
8395 .ocr_mask = MMC_VDD_27_28 | MMC_VDD_28_29,
8396 .translate_vdd = msm_sdcc_setup_power,
8397 .mmc_bus_width = MMC_CAP_4_BIT_DATA,
8398 .msmsdcc_fmin = 400000,
8399 .msmsdcc_fmid = 24000000,
8400 .msmsdcc_fmax = 48000000,
8401 .nonremovable = 0,
8402 .pclk_src_dfab = 1,
8403 .cfg_mpm_sdiowakeup = msm_sdcc_cfg_mpm_sdiowakeup,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07008404};
8405#endif
8406
8407#ifdef CONFIG_MMC_MSM_SDC5_SUPPORT
8408static struct mmc_platform_data msm8x60_sdc5_data = {
8409 .ocr_mask = MMC_VDD_27_28 | MMC_VDD_28_29 | MMC_VDD_165_195,
8410 .translate_vdd = msm_sdcc_setup_power,
8411 .sdio_lpm_gpio_setup = msm_sdcc_sdio_lpm_gpio,
8412 .mmc_bus_width = MMC_CAP_4_BIT_DATA,
8413 .msmsdcc_fmin = 400000,
8414 .msmsdcc_fmid = 24000000,
8415 .msmsdcc_fmax = 48000000,
8416 .nonremovable = 0,
8417 .pclk_src_dfab = 1,
8418 .register_status_notify = sdc5_register_status_notify,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07008419#ifdef CONFIG_MSM_SDIO_AL
8420 .is_sdio_al_client = 1,
8421#endif
8422};
8423#endif
8424
8425static void __init msm8x60_init_mmc(void)
8426{
8427#ifdef CONFIG_MMC_MSM_SDC1_SUPPORT
8428 /* SDCC1 : eMMC card connected */
8429 sdcc_vreg_data[0].vdd_data = &sdcc_vdd_reg_data[0];
8430 sdcc_vreg_data[0].vdd_data->reg_name = "8901_l5";
8431 sdcc_vreg_data[0].vdd_data->set_voltage_sup = 1;
8432 sdcc_vreg_data[0].vdd_data->level = 2850000;
Subhash Jadavania8482a32011-08-08 11:01:44 +05308433 sdcc_vreg_data[0].vdd_data->always_on = 1;
8434 sdcc_vreg_data[0].vdd_data->op_pwr_mode_sup = 1;
8435 sdcc_vreg_data[0].vdd_data->lpm_uA = 9000;
8436 sdcc_vreg_data[0].vdd_data->hpm_uA = 200000;
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07008437
8438 sdcc_vreg_data[0].vccq_data = &sdcc_vccq_reg_data[0];
8439 sdcc_vreg_data[0].vccq_data->reg_name = "8901_lvs0";
8440 sdcc_vreg_data[0].vccq_data->set_voltage_sup = 0;
8441 sdcc_vreg_data[0].vccq_data->always_on = 1;
8442
8443 msm_add_sdcc(1, &msm8x60_sdc1_data);
8444#endif
8445#ifdef CONFIG_MMC_MSM_SDC2_SUPPORT
8446 /*
8447 * MDM SDIO client is connected to SDC2 on charm SURF/FFA
8448 * and no card is connected on 8660 SURF/FFA/FLUID.
8449 */
8450 sdcc_vreg_data[1].vdd_data = &sdcc_vdd_reg_data[1];
8451 sdcc_vreg_data[1].vdd_data->reg_name = "8058_s3";
8452 sdcc_vreg_data[1].vdd_data->set_voltage_sup = 1;
8453 sdcc_vreg_data[1].vdd_data->level = 1800000;
8454
8455 sdcc_vreg_data[1].vccq_data = NULL;
8456
8457 if (machine_is_msm8x60_fusion())
8458 msm8x60_sdc2_data.msmsdcc_fmax = 24000000;
8459 if (machine_is_msm8x60_fusion() || machine_is_msm8x60_fusn_ffa()) {
8460#ifdef CONFIG_MMC_MSM_SDIO_SUPPORT
8461 msm8x60_sdc2_data.sdiowakeup_irq = gpio_to_irq(144);
8462 msm_sdcc_setup_gpio(2, 1);
8463#endif
8464 msm_add_sdcc(2, &msm8x60_sdc2_data);
8465 }
8466#endif
8467#ifdef CONFIG_MMC_MSM_SDC3_SUPPORT
8468 /* SDCC3 : External card slot connected */
8469 sdcc_vreg_data[2].vdd_data = &sdcc_vdd_reg_data[2];
8470 sdcc_vreg_data[2].vdd_data->reg_name = "8058_l14";
8471 sdcc_vreg_data[2].vdd_data->set_voltage_sup = 1;
8472 sdcc_vreg_data[2].vdd_data->level = 2850000;
8473 sdcc_vreg_data[2].vdd_data->always_on = 1;
8474 sdcc_vreg_data[2].vdd_data->op_pwr_mode_sup = 1;
8475 sdcc_vreg_data[2].vdd_data->lpm_uA = 9000;
8476 sdcc_vreg_data[2].vdd_data->hpm_uA = 200000;
8477
8478 sdcc_vreg_data[2].vccq_data = NULL;
8479
8480 sdcc_vreg_data[2].vddp_data = &sdcc_vddp_reg_data[2];
8481 sdcc_vreg_data[2].vddp_data->reg_name = "8058_l5";
8482 sdcc_vreg_data[2].vddp_data->set_voltage_sup = 1;
8483 sdcc_vreg_data[2].vddp_data->level = 2850000;
8484 sdcc_vreg_data[2].vddp_data->always_on = 1;
8485 sdcc_vreg_data[2].vddp_data->op_pwr_mode_sup = 1;
8486 /* Sleep current required is ~300 uA. But min. RPM
8487 * vote can be in terms of mA (min. 1 mA).
8488 * So let's vote for 2 mA during sleep.
8489 */
8490 sdcc_vreg_data[2].vddp_data->lpm_uA = 2000;
8491 /* Max. Active current required is 16 mA */
8492 sdcc_vreg_data[2].vddp_data->hpm_uA = 16000;
8493
8494 if (machine_is_msm8x60_fluid())
8495 msm8x60_sdc3_data.wpswitch = NULL;
8496 msm_add_sdcc(3, &msm8x60_sdc3_data);
8497#endif
8498#ifdef CONFIG_MMC_MSM_SDC4_SUPPORT
8499 /* SDCC4 : WLAN WCN1314 chip is connected */
8500 sdcc_vreg_data[3].vdd_data = &sdcc_vdd_reg_data[3];
8501 sdcc_vreg_data[3].vdd_data->reg_name = "8058_s3";
8502 sdcc_vreg_data[3].vdd_data->set_voltage_sup = 1;
8503 sdcc_vreg_data[3].vdd_data->level = 1800000;
8504
8505 sdcc_vreg_data[3].vccq_data = NULL;
8506
8507 msm_add_sdcc(4, &msm8x60_sdc4_data);
8508#endif
8509#ifdef CONFIG_MMC_MSM_SDC5_SUPPORT
8510 /*
8511 * MDM SDIO client is connected to SDC5 on charm SURF/FFA
8512 * and no card is connected on 8660 SURF/FFA/FLUID.
8513 */
8514 sdcc_vreg_data[4].vdd_data = &sdcc_vdd_reg_data[4];
8515 sdcc_vreg_data[4].vdd_data->reg_name = "8058_s3";
8516 sdcc_vreg_data[4].vdd_data->set_voltage_sup = 1;
8517 sdcc_vreg_data[4].vdd_data->level = 1800000;
8518
8519 sdcc_vreg_data[4].vccq_data = NULL;
8520
8521 if (machine_is_msm8x60_fusion())
8522 msm8x60_sdc5_data.msmsdcc_fmax = 24000000;
8523 if (machine_is_msm8x60_fusion() || machine_is_msm8x60_fusn_ffa()) {
8524#ifdef CONFIG_MMC_MSM_SDIO_SUPPORT
8525 msm8x60_sdc5_data.sdiowakeup_irq = gpio_to_irq(99);
8526 msm_sdcc_setup_gpio(5, 1);
8527#endif
8528 msm_add_sdcc(5, &msm8x60_sdc5_data);
8529 }
8530#endif
8531}
8532
8533#if !defined(CONFIG_GPIO_SX150X) && !defined(CONFIG_GPIO_SX150X_MODULE)
8534static inline void display_common_power(int on) {}
8535#else
8536
8537#define _GET_REGULATOR(var, name) do { \
8538 if (var == NULL) { \
8539 var = regulator_get(NULL, name); \
8540 if (IS_ERR(var)) { \
8541 pr_err("'%s' regulator not found, rc=%ld\n", \
8542 name, PTR_ERR(var)); \
8543 var = NULL; \
8544 } \
8545 } \
8546} while (0)
8547
8548static int dsub_regulator(int on)
8549{
8550 static struct regulator *dsub_reg;
8551 static struct regulator *mpp0_reg;
8552 static int dsub_reg_enabled;
8553 int rc = 0;
8554
8555 _GET_REGULATOR(dsub_reg, "8901_l3");
8556 if (IS_ERR(dsub_reg)) {
8557 printk(KERN_ERR "%s: failed to get reg 8901_l3 err=%ld",
8558 __func__, PTR_ERR(dsub_reg));
8559 return PTR_ERR(dsub_reg);
8560 }
8561
8562 _GET_REGULATOR(mpp0_reg, "8901_mpp0");
8563 if (IS_ERR(mpp0_reg)) {
8564 printk(KERN_ERR "%s: failed to get reg 8901_mpp0 err=%ld",
8565 __func__, PTR_ERR(mpp0_reg));
8566 return PTR_ERR(mpp0_reg);
8567 }
8568
8569 if (on && !dsub_reg_enabled) {
8570 rc = regulator_set_voltage(dsub_reg, 3300000, 3300000);
8571 if (rc) {
8572 printk(KERN_ERR "%s: failed to set reg 8901_l3 voltage"
8573 " err=%d", __func__, rc);
8574 goto dsub_regulator_err;
8575 }
8576 rc = regulator_enable(dsub_reg);
8577 if (rc) {
8578 printk(KERN_ERR "%s: failed to enable reg 8901_l3"
8579 " err=%d", __func__, rc);
8580 goto dsub_regulator_err;
8581 }
8582 rc = regulator_enable(mpp0_reg);
8583 if (rc) {
8584 printk(KERN_ERR "%s: failed to enable reg 8901_mpp0"
8585 " err=%d", __func__, rc);
8586 goto dsub_regulator_err;
8587 }
8588 dsub_reg_enabled = 1;
8589 } else if (!on && dsub_reg_enabled) {
8590 rc = regulator_disable(dsub_reg);
8591 if (rc)
8592 printk(KERN_WARNING "%s: failed to disable reg 8901_l3"
8593 " err=%d", __func__, rc);
8594 rc = regulator_disable(mpp0_reg);
8595 if (rc)
8596 printk(KERN_WARNING "%s: failed to disable reg "
8597 "8901_mpp0 err=%d", __func__, rc);
8598 dsub_reg_enabled = 0;
8599 }
8600
8601 return rc;
8602
8603dsub_regulator_err:
8604 regulator_put(mpp0_reg);
8605 regulator_put(dsub_reg);
8606 return rc;
8607}
8608
8609static int display_power_on;
8610static void setup_display_power(void)
8611{
8612 if (display_power_on)
8613 if (lcdc_vga_enabled) {
8614 dsub_regulator(1);
8615 gpio_set_value_cansleep(GPIO_LVDS_SHUTDOWN_N, 0);
8616 gpio_set_value_cansleep(GPIO_BACKLIGHT_EN, 0);
8617 if (machine_is_msm8x60_ffa() ||
8618 machine_is_msm8x60_fusn_ffa())
8619 gpio_set_value_cansleep(GPIO_DONGLE_PWR_EN, 1);
8620 } else {
8621 dsub_regulator(0);
8622 gpio_set_value_cansleep(GPIO_LVDS_SHUTDOWN_N, 1);
8623 gpio_set_value_cansleep(GPIO_BACKLIGHT_EN, 1);
8624 if (machine_is_msm8x60_ffa() ||
8625 machine_is_msm8x60_fusn_ffa())
8626 gpio_set_value_cansleep(GPIO_DONGLE_PWR_EN, 0);
8627 }
8628 else {
8629 dsub_regulator(0);
8630 if (machine_is_msm8x60_ffa() || machine_is_msm8x60_fusn_ffa())
8631 gpio_set_value_cansleep(GPIO_DONGLE_PWR_EN, 0);
8632 /* BACKLIGHT */
8633 gpio_set_value_cansleep(GPIO_BACKLIGHT_EN, 0);
8634 /* LVDS */
8635 gpio_set_value_cansleep(GPIO_LVDS_SHUTDOWN_N, 0);
8636 }
8637}
8638
8639#define _GET_REGULATOR(var, name) do { \
8640 if (var == NULL) { \
8641 var = regulator_get(NULL, name); \
8642 if (IS_ERR(var)) { \
8643 pr_err("'%s' regulator not found, rc=%ld\n", \
8644 name, PTR_ERR(var)); \
8645 var = NULL; \
8646 } \
8647 } \
8648} while (0)
8649
8650#define GPIO_RESX_N (GPIO_EXPANDER_GPIO_BASE + 2)
8651
8652static void display_common_power(int on)
8653{
8654 int rc;
8655 static struct regulator *display_reg;
8656
8657 if (machine_is_msm8x60_surf() || machine_is_msm8x60_ffa() ||
8658 machine_is_msm8x60_fusion() || machine_is_msm8x60_fusn_ffa()) {
8659 if (on) {
8660 /* LVDS */
8661 _GET_REGULATOR(display_reg, "8901_l2");
8662 if (!display_reg)
8663 return;
8664 rc = regulator_set_voltage(display_reg,
8665 3300000, 3300000);
8666 if (rc)
8667 goto out;
8668 rc = regulator_enable(display_reg);
8669 if (rc)
8670 goto out;
8671 rc = gpio_request(GPIO_LVDS_SHUTDOWN_N,
8672 "LVDS_STDN_OUT_N");
8673 if (rc) {
8674 printk(KERN_ERR "%s: LVDS gpio %d request"
8675 "failed\n", __func__,
8676 GPIO_LVDS_SHUTDOWN_N);
8677 goto out2;
8678 }
8679
8680 /* BACKLIGHT */
8681 rc = gpio_request(GPIO_BACKLIGHT_EN, "BACKLIGHT_EN");
8682 if (rc) {
8683 printk(KERN_ERR "%s: BACKLIGHT gpio %d request"
8684 "failed\n", __func__,
8685 GPIO_BACKLIGHT_EN);
8686 goto out3;
8687 }
8688
8689 if (machine_is_msm8x60_ffa() ||
8690 machine_is_msm8x60_fusn_ffa()) {
8691 rc = gpio_request(GPIO_DONGLE_PWR_EN,
8692 "DONGLE_PWR_EN");
8693 if (rc) {
8694 printk(KERN_ERR "%s: DONGLE_PWR_EN gpio"
8695 " %d request failed\n", __func__,
8696 GPIO_DONGLE_PWR_EN);
8697 goto out4;
8698 }
8699 }
8700
8701 gpio_direction_output(GPIO_LVDS_SHUTDOWN_N, 0);
8702 gpio_direction_output(GPIO_BACKLIGHT_EN, 0);
8703 if (machine_is_msm8x60_ffa() ||
8704 machine_is_msm8x60_fusn_ffa())
8705 gpio_direction_output(GPIO_DONGLE_PWR_EN, 0);
8706 mdelay(20);
8707 display_power_on = 1;
8708 setup_display_power();
8709 } else {
8710 if (display_power_on) {
8711 display_power_on = 0;
8712 setup_display_power();
8713 mdelay(20);
8714 if (machine_is_msm8x60_ffa() ||
8715 machine_is_msm8x60_fusn_ffa())
8716 gpio_free(GPIO_DONGLE_PWR_EN);
8717 goto out4;
8718 }
8719 }
8720 }
8721#if defined(CONFIG_FB_MSM_LCDC_SAMSUNG_OLED_PT) || \
8722 defined(CONFIG_FB_MSM_LCDC_AUO_WVGA)
8723 else if (machine_is_msm8x60_fluid()) {
8724 static struct regulator *fluid_reg;
8725 static struct regulator *fluid_reg2;
8726
8727 if (on) {
8728 _GET_REGULATOR(fluid_reg, "8901_l2");
8729 if (!fluid_reg)
8730 return;
8731 _GET_REGULATOR(fluid_reg2, "8058_s3");
8732 if (!fluid_reg2) {
8733 regulator_put(fluid_reg);
8734 return;
8735 }
8736 rc = gpio_request(GPIO_RESX_N, "RESX_N");
8737 if (rc) {
8738 regulator_put(fluid_reg2);
8739 regulator_put(fluid_reg);
8740 return;
8741 }
8742 regulator_set_voltage(fluid_reg, 2850000, 2850000);
8743 regulator_set_voltage(fluid_reg2, 1800000, 1800000);
8744 regulator_enable(fluid_reg);
8745 regulator_enable(fluid_reg2);
8746 msleep(20);
8747 gpio_direction_output(GPIO_RESX_N, 0);
8748 udelay(10);
8749 gpio_set_value_cansleep(GPIO_RESX_N, 1);
8750 display_power_on = 1;
8751 setup_display_power();
8752 } else {
8753 gpio_set_value_cansleep(GPIO_RESX_N, 0);
8754 gpio_free(GPIO_RESX_N);
8755 msleep(20);
8756 regulator_disable(fluid_reg2);
8757 regulator_disable(fluid_reg);
8758 regulator_put(fluid_reg2);
8759 regulator_put(fluid_reg);
8760 display_power_on = 0;
8761 setup_display_power();
8762 fluid_reg = NULL;
8763 fluid_reg2 = NULL;
8764 }
8765 }
8766#endif
Zhang Chang Ken3a8b8512011-08-04 18:41:39 -04008767#if defined(CONFIG_FB_MSM_LCDC_NT35582_WVGA)
8768 else if (machine_is_msm8x60_dragon()) {
8769 static struct regulator *dragon_reg;
8770 static struct regulator *dragon_reg2;
8771
8772 if (on) {
8773 _GET_REGULATOR(dragon_reg, "8901_l2");
8774 if (!dragon_reg)
8775 return;
8776 _GET_REGULATOR(dragon_reg2, "8058_l16");
8777 if (!dragon_reg2) {
8778 regulator_put(dragon_reg);
8779 dragon_reg = NULL;
8780 return;
8781 }
8782
8783 rc = gpio_request(GPIO_NT35582_BL_EN, "lcdc_bl_en");
8784 if (rc) {
8785 pr_err("%s: gpio %d request failed with rc=%d\n",
8786 __func__, GPIO_NT35582_BL_EN, rc);
8787 regulator_put(dragon_reg);
8788 regulator_put(dragon_reg2);
8789 dragon_reg = NULL;
8790 dragon_reg2 = NULL;
8791 return;
8792 }
8793
8794 if (gpio_tlmm_config(GPIO_CFG(GPIO_NT35582_RESET, 0,
8795 GPIO_CFG_OUTPUT, GPIO_CFG_PULL_DOWN,
8796 GPIO_CFG_16MA), GPIO_CFG_ENABLE)) {
8797 pr_err("%s: config gpio '%d' failed!\n",
8798 __func__, GPIO_NT35582_RESET);
8799 gpio_free(GPIO_NT35582_BL_EN);
8800 regulator_put(dragon_reg);
8801 regulator_put(dragon_reg2);
8802 dragon_reg = NULL;
8803 dragon_reg2 = NULL;
8804 return;
8805 }
8806
8807 rc = gpio_request(GPIO_NT35582_RESET, "lcdc_reset");
8808 if (rc) {
8809 pr_err("%s: unable to request gpio %d (rc=%d)\n",
8810 __func__, GPIO_NT35582_RESET, rc);
8811 gpio_free(GPIO_NT35582_BL_EN);
8812 regulator_put(dragon_reg);
8813 regulator_put(dragon_reg2);
8814 dragon_reg = NULL;
8815 dragon_reg2 = NULL;
8816 return;
8817 }
8818
8819 regulator_set_voltage(dragon_reg, 3300000, 3300000);
8820 regulator_set_voltage(dragon_reg2, 1800000, 1800000);
8821 regulator_enable(dragon_reg);
8822 regulator_enable(dragon_reg2);
8823 msleep(20);
8824
8825 gpio_set_value_cansleep(GPIO_NT35582_RESET, 1);
8826 msleep(20);
8827 gpio_set_value_cansleep(GPIO_NT35582_RESET, 0);
8828 msleep(20);
8829 gpio_set_value_cansleep(GPIO_NT35582_RESET, 1);
8830 msleep(50);
8831
8832 gpio_set_value_cansleep(GPIO_NT35582_BL_EN, 1);
8833
8834 display_power_on = 1;
8835 } else if ((dragon_reg != NULL) && (dragon_reg2 != NULL)) {
8836 gpio_free(GPIO_NT35582_RESET);
8837 gpio_free(GPIO_NT35582_BL_EN);
8838 regulator_disable(dragon_reg2);
8839 regulator_disable(dragon_reg);
8840 regulator_put(dragon_reg2);
8841 regulator_put(dragon_reg);
8842 display_power_on = 0;
8843 dragon_reg = NULL;
8844 dragon_reg2 = NULL;
8845 }
8846 }
8847#endif
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07008848 return;
8849
8850out4:
8851 gpio_free(GPIO_BACKLIGHT_EN);
8852out3:
8853 gpio_free(GPIO_LVDS_SHUTDOWN_N);
8854out2:
8855 regulator_disable(display_reg);
8856out:
8857 regulator_put(display_reg);
8858 display_reg = NULL;
8859}
8860#undef _GET_REGULATOR
8861#endif
8862
8863static int mipi_dsi_panel_power(int on);
8864
8865#define LCDC_NUM_GPIO 28
8866#define LCDC_GPIO_START 0
8867
8868static void lcdc_samsung_panel_power(int on)
8869{
8870 int n, ret = 0;
8871
8872 display_common_power(on);
8873
8874 for (n = 0; n < LCDC_NUM_GPIO; n++) {
8875 if (on) {
8876 ret = gpio_request(LCDC_GPIO_START + n, "LCDC_GPIO");
8877 if (unlikely(ret)) {
8878 pr_err("%s not able to get gpio\n", __func__);
8879 break;
8880 }
8881 } else
8882 gpio_free(LCDC_GPIO_START + n);
8883 }
8884
8885 if (ret) {
8886 for (n--; n >= 0; n--)
8887 gpio_free(LCDC_GPIO_START + n);
8888 }
8889
8890 mipi_dsi_panel_power(0); /* set 8058_ldo0 to LPM */
8891}
8892
8893#ifdef CONFIG_FB_MSM_HDMI_MSM_PANEL
8894#define _GET_REGULATOR(var, name) do { \
8895 var = regulator_get(NULL, name); \
8896 if (IS_ERR(var)) { \
8897 pr_err("'%s' regulator not found, rc=%ld\n", \
8898 name, IS_ERR(var)); \
8899 var = NULL; \
8900 return -ENODEV; \
8901 } \
8902} while (0)
8903
8904static int hdmi_enable_5v(int on)
8905{
8906 static struct regulator *reg_8901_hdmi_mvs; /* HDMI_5V */
8907 static struct regulator *reg_8901_mpp0; /* External 5V */
8908 static int prev_on;
8909 int rc;
8910
8911 if (on == prev_on)
8912 return 0;
8913
8914 if (!reg_8901_hdmi_mvs)
8915 _GET_REGULATOR(reg_8901_hdmi_mvs, "8901_hdmi_mvs");
8916 if (!reg_8901_mpp0)
8917 _GET_REGULATOR(reg_8901_mpp0, "8901_mpp0");
8918
8919 if (on) {
8920 rc = regulator_enable(reg_8901_mpp0);
8921 if (rc) {
8922 pr_err("'%s' regulator enable failed, rc=%d\n",
8923 "reg_8901_mpp0", rc);
8924 return rc;
8925 }
8926 rc = regulator_enable(reg_8901_hdmi_mvs);
8927 if (rc) {
8928 pr_err("'%s' regulator enable failed, rc=%d\n",
8929 "8901_hdmi_mvs", rc);
8930 return rc;
8931 }
8932 pr_info("%s(on): success\n", __func__);
8933 } else {
8934 rc = regulator_disable(reg_8901_hdmi_mvs);
8935 if (rc)
8936 pr_warning("'%s' regulator disable failed, rc=%d\n",
8937 "8901_hdmi_mvs", rc);
8938 rc = regulator_disable(reg_8901_mpp0);
8939 if (rc)
8940 pr_warning("'%s' regulator disable failed, rc=%d\n",
8941 "reg_8901_mpp0", rc);
8942 pr_info("%s(off): success\n", __func__);
8943 }
8944
8945 prev_on = on;
8946
8947 return 0;
8948}
8949
8950static int hdmi_core_power(int on, int show)
8951{
8952 static struct regulator *reg_8058_l16; /* VDD_HDMI */
8953 static int prev_on;
8954 int rc;
8955
8956 if (on == prev_on)
8957 return 0;
8958
8959 if (!reg_8058_l16)
8960 _GET_REGULATOR(reg_8058_l16, "8058_l16");
8961
8962 if (on) {
8963 rc = regulator_set_voltage(reg_8058_l16, 1800000, 1800000);
8964 if (!rc)
8965 rc = regulator_enable(reg_8058_l16);
8966 if (rc) {
8967 pr_err("'%s' regulator enable failed, rc=%d\n",
8968 "8058_l16", rc);
8969 return rc;
8970 }
8971 rc = gpio_request(170, "HDMI_DDC_CLK");
8972 if (rc) {
8973 pr_err("'%s'(%d) gpio_request failed, rc=%d\n",
8974 "HDMI_DDC_CLK", 170, rc);
8975 goto error1;
8976 }
8977 rc = gpio_request(171, "HDMI_DDC_DATA");
8978 if (rc) {
8979 pr_err("'%s'(%d) gpio_request failed, rc=%d\n",
8980 "HDMI_DDC_DATA", 171, rc);
8981 goto error2;
8982 }
8983 rc = gpio_request(172, "HDMI_HPD");
8984 if (rc) {
8985 pr_err("'%s'(%d) gpio_request failed, rc=%d\n",
8986 "HDMI_HPD", 172, rc);
8987 goto error3;
8988 }
8989 pr_info("%s(on): success\n", __func__);
8990 } else {
8991 gpio_free(170);
8992 gpio_free(171);
8993 gpio_free(172);
8994 rc = regulator_disable(reg_8058_l16);
8995 if (rc)
8996 pr_warning("'%s' regulator disable failed, rc=%d\n",
8997 "8058_l16", rc);
8998 pr_info("%s(off): success\n", __func__);
8999 }
9000
9001 prev_on = on;
9002
9003 return 0;
9004
9005error3:
9006 gpio_free(171);
9007error2:
9008 gpio_free(170);
9009error1:
9010 regulator_disable(reg_8058_l16);
9011 return rc;
9012}
9013
9014static int hdmi_cec_power(int on)
9015{
9016 static struct regulator *reg_8901_l3; /* HDMI_CEC */
9017 static int prev_on;
9018 int rc;
9019
9020 if (on == prev_on)
9021 return 0;
9022
9023 if (!reg_8901_l3)
9024 _GET_REGULATOR(reg_8901_l3, "8901_l3");
9025
9026 if (on) {
9027 rc = regulator_set_voltage(reg_8901_l3, 3300000, 3300000);
9028 if (!rc)
9029 rc = regulator_enable(reg_8901_l3);
9030 if (rc) {
9031 pr_err("'%s' regulator enable failed, rc=%d\n",
9032 "8901_l3", rc);
9033 return rc;
9034 }
9035 rc = gpio_request(169, "HDMI_CEC_VAR");
9036 if (rc) {
9037 pr_err("'%s'(%d) gpio_request failed, rc=%d\n",
9038 "HDMI_CEC_VAR", 169, rc);
9039 goto error;
9040 }
9041 pr_info("%s(on): success\n", __func__);
9042 } else {
9043 gpio_free(169);
9044 rc = regulator_disable(reg_8901_l3);
9045 if (rc)
9046 pr_warning("'%s' regulator disable failed, rc=%d\n",
9047 "8901_l3", rc);
9048 pr_info("%s(off): success\n", __func__);
9049 }
9050
9051 prev_on = on;
9052
9053 return 0;
9054error:
9055 regulator_disable(reg_8901_l3);
9056 return rc;
9057}
9058
9059#undef _GET_REGULATOR
9060
9061#endif /* CONFIG_FB_MSM_HDMI_MSM_PANEL */
9062
9063static int lcdc_panel_power(int on)
9064{
9065 int flag_on = !!on;
9066 static int lcdc_power_save_on;
9067
9068 if (lcdc_power_save_on == flag_on)
9069 return 0;
9070
9071 lcdc_power_save_on = flag_on;
9072
9073 lcdc_samsung_panel_power(on);
9074
9075 return 0;
9076}
9077
9078#ifdef CONFIG_MSM_BUS_SCALING
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07009079static struct msm_bus_vectors mdp_init_vectors[] = {
9080 /* For now, 0th array entry is reserved.
9081 * Please leave 0 as is and don't use it
9082 */
9083 {
9084 .src = MSM_BUS_MASTER_MDP_PORT0,
9085 .dst = MSM_BUS_SLAVE_SMI,
9086 .ab = 0,
9087 .ib = 0,
9088 },
9089 /* Master and slaves can be from different fabrics */
9090 {
9091 .src = MSM_BUS_MASTER_MDP_PORT0,
9092 .dst = MSM_BUS_SLAVE_EBI_CH0,
9093 .ab = 0,
9094 .ib = 0,
9095 },
9096};
9097
Ravishangar Kalyanam75f37322011-10-14 12:15:40 -07009098#ifdef CONFIG_FB_MSM_HDMI_AS_PRIMARY
9099static struct msm_bus_vectors hdmi_as_primary_vectors[] = {
9100 /* If HDMI is used as primary */
9101 {
9102 .src = MSM_BUS_MASTER_MDP_PORT0,
9103 .dst = MSM_BUS_SLAVE_SMI,
9104 .ab = 2000000000,
9105 .ib = 2000000000,
9106 },
9107 /* Master and slaves can be from different fabrics */
9108 {
9109 .src = MSM_BUS_MASTER_MDP_PORT0,
9110 .dst = MSM_BUS_SLAVE_EBI_CH0,
9111 .ab = 2000000000,
9112 .ib = 2000000000,
9113 },
9114};
9115
9116static struct msm_bus_paths mdp_bus_scale_usecases[] = {
9117 {
9118 ARRAY_SIZE(mdp_init_vectors),
9119 mdp_init_vectors,
9120 },
9121 {
9122 ARRAY_SIZE(hdmi_as_primary_vectors),
9123 hdmi_as_primary_vectors,
9124 },
9125 {
9126 ARRAY_SIZE(hdmi_as_primary_vectors),
9127 hdmi_as_primary_vectors,
9128 },
9129 {
9130 ARRAY_SIZE(hdmi_as_primary_vectors),
9131 hdmi_as_primary_vectors,
9132 },
9133 {
9134 ARRAY_SIZE(hdmi_as_primary_vectors),
9135 hdmi_as_primary_vectors,
9136 },
9137 {
9138 ARRAY_SIZE(hdmi_as_primary_vectors),
9139 hdmi_as_primary_vectors,
9140 },
9141};
9142#else
9143#ifdef CONFIG_FB_MSM_LCDC_DSUB
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07009144static struct msm_bus_vectors mdp_sd_smi_vectors[] = {
9145 /* Default case static display/UI/2d/3d if FB SMI */
9146 {
9147 .src = MSM_BUS_MASTER_MDP_PORT0,
9148 .dst = MSM_BUS_SLAVE_SMI,
9149 .ab = 388800000,
9150 .ib = 486000000,
9151 },
9152 /* Master and slaves can be from different fabrics */
9153 {
9154 .src = MSM_BUS_MASTER_MDP_PORT0,
9155 .dst = MSM_BUS_SLAVE_EBI_CH0,
9156 .ab = 0,
9157 .ib = 0,
9158 },
9159};
9160
9161static struct msm_bus_vectors mdp_sd_ebi_vectors[] = {
9162 /* Default case static display/UI/2d/3d if FB SMI */
9163 {
9164 .src = MSM_BUS_MASTER_MDP_PORT0,
9165 .dst = MSM_BUS_SLAVE_SMI,
9166 .ab = 0,
9167 .ib = 0,
9168 },
9169 /* Master and slaves can be from different fabrics */
9170 {
9171 .src = MSM_BUS_MASTER_MDP_PORT0,
9172 .dst = MSM_BUS_SLAVE_EBI_CH0,
9173 .ab = 388800000,
9174 .ib = 486000000 * 2,
9175 },
9176};
9177static struct msm_bus_vectors mdp_vga_vectors[] = {
9178 /* VGA and less video */
9179 {
9180 .src = MSM_BUS_MASTER_MDP_PORT0,
9181 .dst = MSM_BUS_SLAVE_SMI,
9182 .ab = 458092800,
9183 .ib = 572616000,
9184 },
9185 {
9186 .src = MSM_BUS_MASTER_MDP_PORT0,
9187 .dst = MSM_BUS_SLAVE_EBI_CH0,
9188 .ab = 458092800,
9189 .ib = 572616000 * 2,
9190 },
9191};
9192static struct msm_bus_vectors mdp_720p_vectors[] = {
9193 /* 720p and less video */
9194 {
9195 .src = MSM_BUS_MASTER_MDP_PORT0,
9196 .dst = MSM_BUS_SLAVE_SMI,
9197 .ab = 471744000,
9198 .ib = 589680000,
9199 },
9200 /* Master and slaves can be from different fabrics */
9201 {
9202 .src = MSM_BUS_MASTER_MDP_PORT0,
9203 .dst = MSM_BUS_SLAVE_EBI_CH0,
9204 .ab = 471744000,
9205 .ib = 589680000 * 2,
9206 },
9207};
9208
9209static struct msm_bus_vectors mdp_1080p_vectors[] = {
9210 /* 1080p and less video */
9211 {
9212 .src = MSM_BUS_MASTER_MDP_PORT0,
9213 .dst = MSM_BUS_SLAVE_SMI,
9214 .ab = 575424000,
9215 .ib = 719280000,
9216 },
9217 /* Master and slaves can be from different fabrics */
9218 {
9219 .src = MSM_BUS_MASTER_MDP_PORT0,
9220 .dst = MSM_BUS_SLAVE_EBI_CH0,
9221 .ab = 575424000,
9222 .ib = 719280000 * 2,
9223 },
9224};
9225
9226#else
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07009227static struct msm_bus_vectors mdp_sd_smi_vectors[] = {
9228 /* Default case static display/UI/2d/3d if FB SMI */
9229 {
9230 .src = MSM_BUS_MASTER_MDP_PORT0,
9231 .dst = MSM_BUS_SLAVE_SMI,
9232 .ab = 175110000,
9233 .ib = 218887500,
9234 },
9235 /* Master and slaves can be from different fabrics */
9236 {
9237 .src = MSM_BUS_MASTER_MDP_PORT0,
9238 .dst = MSM_BUS_SLAVE_EBI_CH0,
9239 .ab = 0,
9240 .ib = 0,
9241 },
9242};
9243
9244static struct msm_bus_vectors mdp_sd_ebi_vectors[] = {
9245 /* Default case static display/UI/2d/3d if FB SMI */
9246 {
9247 .src = MSM_BUS_MASTER_MDP_PORT0,
9248 .dst = MSM_BUS_SLAVE_SMI,
9249 .ab = 0,
9250 .ib = 0,
9251 },
9252 /* Master and slaves can be from different fabrics */
9253 {
9254 .src = MSM_BUS_MASTER_MDP_PORT0,
9255 .dst = MSM_BUS_SLAVE_EBI_CH0,
9256 .ab = 216000000,
9257 .ib = 270000000 * 2,
9258 },
9259};
9260static struct msm_bus_vectors mdp_vga_vectors[] = {
9261 /* VGA and less video */
9262 {
9263 .src = MSM_BUS_MASTER_MDP_PORT0,
9264 .dst = MSM_BUS_SLAVE_SMI,
9265 .ab = 216000000,
9266 .ib = 270000000,
9267 },
9268 {
9269 .src = MSM_BUS_MASTER_MDP_PORT0,
9270 .dst = MSM_BUS_SLAVE_EBI_CH0,
9271 .ab = 216000000,
9272 .ib = 270000000 * 2,
9273 },
9274};
9275
9276static struct msm_bus_vectors mdp_720p_vectors[] = {
9277 /* 720p and less video */
9278 {
9279 .src = MSM_BUS_MASTER_MDP_PORT0,
9280 .dst = MSM_BUS_SLAVE_SMI,
9281 .ab = 230400000,
9282 .ib = 288000000,
9283 },
9284 /* Master and slaves can be from different fabrics */
9285 {
9286 .src = MSM_BUS_MASTER_MDP_PORT0,
9287 .dst = MSM_BUS_SLAVE_EBI_CH0,
9288 .ab = 230400000,
9289 .ib = 288000000 * 2,
9290 },
9291};
9292
9293static struct msm_bus_vectors mdp_1080p_vectors[] = {
9294 /* 1080p and less video */
9295 {
9296 .src = MSM_BUS_MASTER_MDP_PORT0,
9297 .dst = MSM_BUS_SLAVE_SMI,
9298 .ab = 334080000,
9299 .ib = 417600000,
9300 },
9301 /* Master and slaves can be from different fabrics */
9302 {
9303 .src = MSM_BUS_MASTER_MDP_PORT0,
9304 .dst = MSM_BUS_SLAVE_EBI_CH0,
9305 .ab = 334080000,
Ravishangar Kalyanam731beb92011-07-07 18:27:32 -07009306 .ib = 550000000 * 2,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07009307 },
9308};
9309
9310#endif
9311static struct msm_bus_paths mdp_bus_scale_usecases[] = {
9312 {
9313 ARRAY_SIZE(mdp_init_vectors),
9314 mdp_init_vectors,
9315 },
9316 {
9317 ARRAY_SIZE(mdp_sd_smi_vectors),
9318 mdp_sd_smi_vectors,
9319 },
9320 {
9321 ARRAY_SIZE(mdp_sd_ebi_vectors),
9322 mdp_sd_ebi_vectors,
9323 },
9324 {
9325 ARRAY_SIZE(mdp_vga_vectors),
9326 mdp_vga_vectors,
9327 },
9328 {
9329 ARRAY_SIZE(mdp_720p_vectors),
9330 mdp_720p_vectors,
9331 },
9332 {
9333 ARRAY_SIZE(mdp_1080p_vectors),
9334 mdp_1080p_vectors,
9335 },
9336};
Ravishangar Kalyanam75f37322011-10-14 12:15:40 -07009337#endif
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07009338static struct msm_bus_scale_pdata mdp_bus_scale_pdata = {
9339 mdp_bus_scale_usecases,
9340 ARRAY_SIZE(mdp_bus_scale_usecases),
9341 .name = "mdp",
9342};
9343
9344#endif
9345#ifdef CONFIG_MSM_BUS_SCALING
9346static struct msm_bus_vectors dtv_bus_init_vectors[] = {
9347 /* For now, 0th array entry is reserved.
9348 * Please leave 0 as is and don't use it
9349 */
9350 {
9351 .src = MSM_BUS_MASTER_MDP_PORT0,
9352 .dst = MSM_BUS_SLAVE_SMI,
9353 .ab = 0,
9354 .ib = 0,
9355 },
9356 /* Master and slaves can be from different fabrics */
9357 {
9358 .src = MSM_BUS_MASTER_MDP_PORT0,
9359 .dst = MSM_BUS_SLAVE_EBI_CH0,
9360 .ab = 0,
9361 .ib = 0,
9362 },
9363};
Ravishangar Kalyanam75f37322011-10-14 12:15:40 -07009364#ifdef CONFIG_FB_MSM_HDMI_AS_PRIMARY
9365static struct msm_bus_vectors dtv_bus_def_vectors[] = {
9366 /* For now, 0th array entry is reserved.
9367 * Please leave 0 as is and don't use it
9368 */
9369 {
9370 .src = MSM_BUS_MASTER_MDP_PORT0,
9371 .dst = MSM_BUS_SLAVE_SMI,
9372 .ab = 2000000000,
9373 .ib = 2000000000,
9374 },
9375 /* Master and slaves can be from different fabrics */
9376 {
9377 .src = MSM_BUS_MASTER_MDP_PORT0,
9378 .dst = MSM_BUS_SLAVE_EBI_CH0,
9379 .ab = 2000000000,
9380 .ib = 2000000000,
9381 },
9382};
9383#else
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07009384static struct msm_bus_vectors dtv_bus_def_vectors[] = {
9385 /* For now, 0th array entry is reserved.
9386 * Please leave 0 as is and don't use it
9387 */
9388 {
9389 .src = MSM_BUS_MASTER_MDP_PORT0,
9390 .dst = MSM_BUS_SLAVE_SMI,
9391 .ab = 566092800,
9392 .ib = 707616000,
9393 },
9394 /* Master and slaves can be from different fabrics */
9395 {
9396 .src = MSM_BUS_MASTER_MDP_PORT0,
9397 .dst = MSM_BUS_SLAVE_EBI_CH0,
9398 .ab = 566092800,
9399 .ib = 707616000,
9400 },
9401};
Ravishangar Kalyanam75f37322011-10-14 12:15:40 -07009402#endif
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07009403static struct msm_bus_paths dtv_bus_scale_usecases[] = {
9404 {
9405 ARRAY_SIZE(dtv_bus_init_vectors),
9406 dtv_bus_init_vectors,
9407 },
9408 {
9409 ARRAY_SIZE(dtv_bus_def_vectors),
9410 dtv_bus_def_vectors,
9411 },
9412};
9413static struct msm_bus_scale_pdata dtv_bus_scale_pdata = {
9414 dtv_bus_scale_usecases,
9415 ARRAY_SIZE(dtv_bus_scale_usecases),
9416 .name = "dtv",
9417};
9418
9419static struct lcdc_platform_data dtv_pdata = {
9420 .bus_scale_table = &dtv_bus_scale_pdata,
9421};
9422#endif
9423
9424
9425static struct lcdc_platform_data lcdc_pdata = {
9426 .lcdc_power_save = lcdc_panel_power,
9427};
9428
9429
9430#define MDP_VSYNC_GPIO 28
9431
9432/*
9433 * MIPI_DSI only use 8058_LDO0 which need always on
9434 * therefore it need to be put at low power mode if
9435 * it was not used instead of turn it off.
9436 */
9437static int mipi_dsi_panel_power(int on)
9438{
9439 int flag_on = !!on;
9440 static int mipi_dsi_power_save_on;
9441 static struct regulator *ldo0;
9442 int rc = 0;
9443
9444 if (mipi_dsi_power_save_on == flag_on)
9445 return 0;
9446
9447 mipi_dsi_power_save_on = flag_on;
9448
9449 if (ldo0 == NULL) { /* init */
9450 ldo0 = regulator_get(NULL, "8058_l0");
9451 if (IS_ERR(ldo0)) {
9452 pr_debug("%s: LDO0 failed\n", __func__);
9453 rc = PTR_ERR(ldo0);
9454 return rc;
9455 }
9456
9457 rc = regulator_set_voltage(ldo0, 1200000, 1200000);
9458 if (rc)
9459 goto out;
9460
9461 rc = regulator_enable(ldo0);
9462 if (rc)
9463 goto out;
9464 }
9465
9466 if (on) {
9467 /* set ldo0 to HPM */
9468 rc = regulator_set_optimum_mode(ldo0, 100000);
9469 if (rc < 0)
9470 goto out;
9471 } else {
9472 /* set ldo0 to LPM */
9473 rc = regulator_set_optimum_mode(ldo0, 9000);
9474 if (rc < 0)
9475 goto out;
9476 }
9477
9478 return 0;
9479out:
9480 regulator_disable(ldo0);
9481 regulator_put(ldo0);
9482 ldo0 = NULL;
9483 return rc;
9484}
9485
9486static struct mipi_dsi_platform_data mipi_dsi_pdata = {
9487 .vsync_gpio = MDP_VSYNC_GPIO,
9488 .dsi_power_save = mipi_dsi_panel_power,
9489};
9490
9491#ifdef CONFIG_FB_MSM_TVOUT
9492static struct regulator *reg_8058_l13;
9493
9494static int atv_dac_power(int on)
9495{
9496 int rc = 0;
9497 #define _GET_REGULATOR(var, name) do { \
9498 var = regulator_get(NULL, name); \
9499 if (IS_ERR(var)) { \
9500 pr_info("'%s' regulator not found, rc=%ld\n", \
9501 name, IS_ERR(var)); \
9502 var = NULL; \
9503 return -ENODEV; \
9504 } \
9505 } while (0)
9506
9507 if (!reg_8058_l13)
9508 _GET_REGULATOR(reg_8058_l13, "8058_l13");
9509 #undef _GET_REGULATOR
9510
9511 if (on) {
9512 rc = regulator_set_voltage(reg_8058_l13, 2050000, 2050000);
9513 if (rc) {
9514 pr_info("%s: '%s' regulator set voltage failed,\
9515 rc=%d\n", __func__, "8058_l13", rc);
9516 return rc;
9517 }
9518
9519 rc = regulator_enable(reg_8058_l13);
9520 if (rc) {
9521 pr_err("%s: '%s' regulator enable failed,\
9522 rc=%d\n", __func__, "8058_l13", rc);
9523 return rc;
9524 }
9525 } else {
9526 rc = regulator_force_disable(reg_8058_l13);
9527 if (rc)
9528 pr_warning("%s: '%s' regulator disable failed, rc=%d\n",
9529 __func__, "8058_l13", rc);
9530 }
9531 return rc;
9532
9533}
9534#endif
9535
9536#ifdef CONFIG_FB_MSM_MIPI_DSI
9537int mdp_core_clk_rate_table[] = {
9538 85330000,
9539 85330000,
9540 160000000,
9541 200000000,
9542};
Ravishangar Kalyanam75f37322011-10-14 12:15:40 -07009543#elif defined(CONFIG_FB_MSM_HDMI_AS_PRIMARY)
9544int mdp_core_clk_rate_table[] = {
9545 200000000,
9546 200000000,
9547 200000000,
9548 200000000,
9549};
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07009550#else
9551int mdp_core_clk_rate_table[] = {
9552 59080000,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07009553 85330000,
kuogee hsieh26791a92011-08-01 18:35:58 -07009554 128000000,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07009555 200000000,
9556};
9557#endif
9558
9559static struct msm_panel_common_pdata mdp_pdata = {
9560 .gpio = MDP_VSYNC_GPIO,
Ravishangar Kalyanam75f37322011-10-14 12:15:40 -07009561#ifdef CONFIG_FB_MSM_HDMI_AS_PRIMARY
9562 .mdp_core_clk_rate = 200000000,
9563#else
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07009564 .mdp_core_clk_rate = 59080000,
Ravishangar Kalyanam75f37322011-10-14 12:15:40 -07009565#endif
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07009566 .mdp_core_clk_table = mdp_core_clk_rate_table,
9567 .num_mdp_clk = ARRAY_SIZE(mdp_core_clk_rate_table),
9568#ifdef CONFIG_MSM_BUS_SCALING
9569 .mdp_bus_scale_table = &mdp_bus_scale_pdata,
9570#endif
9571 .mdp_rev = MDP_REV_41,
kuogee hsiehc9a2e6d2011-09-12 15:27:01 -07009572 .writeback_offset = writeback_offset,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07009573};
9574
9575#ifdef CONFIG_FB_MSM_TVOUT
9576
9577#ifdef CONFIG_MSM_BUS_SCALING
9578static struct msm_bus_vectors atv_bus_init_vectors[] = {
9579 /* For now, 0th array entry is reserved.
9580 * Please leave 0 as is and don't use it
9581 */
9582 {
9583 .src = MSM_BUS_MASTER_MDP_PORT0,
9584 .dst = MSM_BUS_SLAVE_SMI,
9585 .ab = 0,
9586 .ib = 0,
9587 },
9588 /* Master and slaves can be from different fabrics */
9589 {
9590 .src = MSM_BUS_MASTER_MDP_PORT0,
9591 .dst = MSM_BUS_SLAVE_EBI_CH0,
9592 .ab = 0,
9593 .ib = 0,
9594 },
9595};
9596static struct msm_bus_vectors atv_bus_def_vectors[] = {
9597 /* For now, 0th array entry is reserved.
9598 * Please leave 0 as is and don't use it
9599 */
9600 {
9601 .src = MSM_BUS_MASTER_MDP_PORT0,
9602 .dst = MSM_BUS_SLAVE_SMI,
9603 .ab = 236390400,
9604 .ib = 265939200,
9605 },
9606 /* Master and slaves can be from different fabrics */
9607 {
9608 .src = MSM_BUS_MASTER_MDP_PORT0,
9609 .dst = MSM_BUS_SLAVE_EBI_CH0,
9610 .ab = 236390400,
9611 .ib = 265939200,
9612 },
9613};
9614static struct msm_bus_paths atv_bus_scale_usecases[] = {
9615 {
9616 ARRAY_SIZE(atv_bus_init_vectors),
9617 atv_bus_init_vectors,
9618 },
9619 {
9620 ARRAY_SIZE(atv_bus_def_vectors),
9621 atv_bus_def_vectors,
9622 },
9623};
9624static struct msm_bus_scale_pdata atv_bus_scale_pdata = {
9625 atv_bus_scale_usecases,
9626 ARRAY_SIZE(atv_bus_scale_usecases),
9627 .name = "atv",
9628};
9629#endif
9630
9631static struct tvenc_platform_data atv_pdata = {
9632 .poll = 0,
9633 .pm_vid_en = atv_dac_power,
9634#ifdef CONFIG_MSM_BUS_SCALING
9635 .bus_scale_table = &atv_bus_scale_pdata,
9636#endif
9637};
9638#endif
9639
9640static void __init msm_fb_add_devices(void)
9641{
9642#ifdef CONFIG_FB_MSM_LCDC_DSUB
9643 mdp_pdata.mdp_core_clk_table = NULL;
9644 mdp_pdata.num_mdp_clk = 0;
9645 mdp_pdata.mdp_core_clk_rate = 200000000;
9646#endif
9647 if (machine_is_msm8x60_rumi3())
9648 msm_fb_register_device("mdp", NULL);
9649 else
9650 msm_fb_register_device("mdp", &mdp_pdata);
9651
9652 msm_fb_register_device("lcdc", &lcdc_pdata);
9653 msm_fb_register_device("mipi_dsi", &mipi_dsi_pdata);
9654#ifdef CONFIG_MSM_BUS_SCALING
9655 msm_fb_register_device("dtv", &dtv_pdata);
9656#endif
9657#ifdef CONFIG_FB_MSM_TVOUT
9658 msm_fb_register_device("tvenc", &atv_pdata);
9659 msm_fb_register_device("tvout_device", NULL);
9660#endif
9661}
9662
9663#if (defined(CONFIG_MARIMBA_CORE)) && \
9664 (defined(CONFIG_MSM_BT_POWER) || defined(CONFIG_MSM_BT_POWER_MODULE))
9665
9666static const struct {
9667 char *name;
9668 int vmin;
9669 int vmax;
9670} bt_regs_info[] = {
9671 { "8058_s3", 1800000, 1800000 },
9672 { "8058_s2", 1300000, 1300000 },
9673 { "8058_l8", 2900000, 3050000 },
9674};
9675
9676static struct {
9677 bool enabled;
9678} bt_regs_status[] = {
9679 { false },
9680 { false },
9681 { false },
9682};
9683static struct regulator *bt_regs[ARRAY_SIZE(bt_regs_info)];
9684
9685static int bahama_bt(int on)
9686{
9687 int rc;
9688 int i;
9689 struct marimba config = { .mod_id = SLAVE_ID_BAHAMA};
9690
9691 struct bahama_variant_register {
9692 const size_t size;
9693 const struct bahama_config_register *set;
9694 };
9695
9696 const struct bahama_config_register *p;
9697
9698 u8 version;
9699
9700 const struct bahama_config_register v10_bt_on[] = {
9701 { 0xE9, 0x00, 0xFF },
9702 { 0xF4, 0x80, 0xFF },
9703 { 0xE4, 0x00, 0xFF },
9704 { 0xE5, 0x00, 0x0F },
9705#ifdef CONFIG_WLAN
9706 { 0xE6, 0x38, 0x7F },
9707 { 0xE7, 0x06, 0xFF },
9708#endif
9709 { 0xE9, 0x21, 0xFF },
9710 { 0x01, 0x0C, 0x1F },
9711 { 0x01, 0x08, 0x1F },
9712 };
9713
9714 const struct bahama_config_register v20_bt_on_fm_off[] = {
9715 { 0x11, 0x0C, 0xFF },
9716 { 0x13, 0x01, 0xFF },
9717 { 0xF4, 0x80, 0xFF },
9718 { 0xF0, 0x00, 0xFF },
9719 { 0xE9, 0x00, 0xFF },
9720#ifdef CONFIG_WLAN
9721 { 0x81, 0x00, 0x7F },
9722 { 0x82, 0x00, 0xFF },
9723 { 0xE6, 0x38, 0x7F },
9724 { 0xE7, 0x06, 0xFF },
9725#endif
9726 { 0xE9, 0x21, 0xFF },
9727 };
9728
9729 const struct bahama_config_register v20_bt_on_fm_on[] = {
9730 { 0x11, 0x0C, 0xFF },
9731 { 0x13, 0x01, 0xFF },
9732 { 0xF4, 0x86, 0xFF },
9733 { 0xF0, 0x06, 0xFF },
9734 { 0xE9, 0x00, 0xFF },
9735#ifdef CONFIG_WLAN
9736 { 0x81, 0x00, 0x7F },
9737 { 0x82, 0x00, 0xFF },
9738 { 0xE6, 0x38, 0x7F },
9739 { 0xE7, 0x06, 0xFF },
9740#endif
9741 { 0xE9, 0x21, 0xFF },
9742 };
9743
9744 const struct bahama_config_register v10_bt_off[] = {
9745 { 0xE9, 0x00, 0xFF },
9746 };
9747
9748 const struct bahama_config_register v20_bt_off_fm_off[] = {
9749 { 0xF4, 0x84, 0xFF },
9750 { 0xF0, 0x04, 0xFF },
9751 { 0xE9, 0x00, 0xFF }
9752 };
9753
9754 const struct bahama_config_register v20_bt_off_fm_on[] = {
9755 { 0xF4, 0x86, 0xFF },
9756 { 0xF0, 0x06, 0xFF },
9757 { 0xE9, 0x00, 0xFF }
9758 };
9759 const struct bahama_variant_register bt_bahama[2][3] = {
9760 {
9761 { ARRAY_SIZE(v10_bt_off), v10_bt_off },
9762 { ARRAY_SIZE(v20_bt_off_fm_off), v20_bt_off_fm_off },
9763 { ARRAY_SIZE(v20_bt_off_fm_on), v20_bt_off_fm_on }
9764 },
9765 {
9766 { ARRAY_SIZE(v10_bt_on), v10_bt_on },
9767 { ARRAY_SIZE(v20_bt_on_fm_off), v20_bt_on_fm_off },
9768 { ARRAY_SIZE(v20_bt_on_fm_on), v20_bt_on_fm_on }
9769 }
9770 };
9771
9772 u8 offset = 0; /* index into bahama configs */
9773
9774 on = on ? 1 : 0;
9775 version = read_bahama_ver();
9776
9777 if (version == VER_UNSUPPORTED) {
9778 dev_err(&msm_bt_power_device.dev,
9779 "%s: unsupported version\n",
9780 __func__);
9781 return -EIO;
9782 }
9783
9784 if (version == VER_2_0) {
9785 if (marimba_get_fm_status(&config))
9786 offset = 0x01;
9787 }
9788
9789 /* Voting off 1.3V S2 Regulator,BahamaV2 used in Normal mode */
9790 if (on && (version == VER_2_0)) {
9791 for (i = 0; i < ARRAY_SIZE(bt_regs_info); i++) {
9792 if ((!strcmp(bt_regs_info[i].name, "8058_s2"))
9793 && (bt_regs_status[i].enabled == true)) {
9794 if (regulator_disable(bt_regs[i])) {
9795 dev_err(&msm_bt_power_device.dev,
9796 "%s: regulator disable failed",
9797 __func__);
9798 }
9799 bt_regs_status[i].enabled = false;
9800 break;
9801 }
9802 }
9803 }
9804
9805 p = bt_bahama[on][version + offset].set;
9806
9807 dev_info(&msm_bt_power_device.dev,
9808 "%s: found version %d\n", __func__, version);
9809
9810 for (i = 0; i < bt_bahama[on][version + offset].size; i++) {
9811 u8 value = (p+i)->value;
9812 rc = marimba_write_bit_mask(&config,
9813 (p+i)->reg,
9814 &value,
9815 sizeof((p+i)->value),
9816 (p+i)->mask);
9817 if (rc < 0) {
9818 dev_err(&msm_bt_power_device.dev,
9819 "%s: reg %d write failed: %d\n",
9820 __func__, (p+i)->reg, rc);
9821 return rc;
9822 }
9823 dev_dbg(&msm_bt_power_device.dev,
9824 "%s: reg 0x%02x write value 0x%02x mask 0x%02x\n",
9825 __func__, (p+i)->reg,
9826 value, (p+i)->mask);
9827 }
9828 /* Update BT Status */
9829 if (on)
9830 marimba_set_bt_status(&config, true);
9831 else
9832 marimba_set_bt_status(&config, false);
9833
9834 return 0;
9835}
9836
9837static int bluetooth_use_regulators(int on)
9838{
9839 int i, recover = -1, rc = 0;
9840
9841 for (i = 0; i < ARRAY_SIZE(bt_regs_info); i++) {
9842 bt_regs[i] = on ? regulator_get(&msm_bt_power_device.dev,
9843 bt_regs_info[i].name) :
9844 (regulator_put(bt_regs[i]), NULL);
9845 if (IS_ERR(bt_regs[i])) {
9846 rc = PTR_ERR(bt_regs[i]);
9847 dev_err(&msm_bt_power_device.dev,
9848 "regulator %s get failed (%d)\n",
9849 bt_regs_info[i].name, rc);
9850 recover = i - 1;
9851 bt_regs[i] = NULL;
9852 break;
9853 }
9854
9855 if (!on)
9856 continue;
9857
9858 rc = regulator_set_voltage(bt_regs[i],
9859 bt_regs_info[i].vmin,
9860 bt_regs_info[i].vmax);
9861 if (rc < 0) {
9862 dev_err(&msm_bt_power_device.dev,
9863 "regulator %s voltage set (%d)\n",
9864 bt_regs_info[i].name, rc);
9865 recover = i;
9866 break;
9867 }
9868 }
9869
9870 if (on && (recover > -1))
9871 for (i = recover; i >= 0; i--) {
9872 regulator_put(bt_regs[i]);
9873 bt_regs[i] = NULL;
9874 }
9875
9876 return rc;
9877}
9878
9879static int bluetooth_switch_regulators(int on)
9880{
9881 int i, rc = 0;
9882
9883 for (i = 0; i < ARRAY_SIZE(bt_regs_info); i++) {
9884 if (on && (bt_regs_status[i].enabled == false)) {
9885 rc = regulator_enable(bt_regs[i]);
9886 if (rc < 0) {
9887 dev_err(&msm_bt_power_device.dev,
9888 "regulator %s %s failed (%d)\n",
9889 bt_regs_info[i].name,
9890 "enable", rc);
9891 if (i > 0) {
9892 while (--i) {
9893 regulator_disable(bt_regs[i]);
9894 bt_regs_status[i].enabled
9895 = false;
9896 }
9897 break;
9898 }
9899 }
9900 bt_regs_status[i].enabled = true;
9901 } else if (!on && (bt_regs_status[i].enabled == true)) {
9902 rc = regulator_disable(bt_regs[i]);
9903 if (rc < 0) {
9904 dev_err(&msm_bt_power_device.dev,
9905 "regulator %s %s failed (%d)\n",
9906 bt_regs_info[i].name,
9907 "disable", rc);
9908 break;
9909 }
9910 bt_regs_status[i].enabled = false;
9911 }
9912 }
9913 return rc;
9914}
9915
9916static struct msm_xo_voter *bt_clock;
9917
9918static int bluetooth_power(int on)
9919{
9920 int rc = 0;
9921 int id;
9922
9923 /* In case probe function fails, cur_connv_type would be -1 */
9924 id = adie_get_detected_connectivity_type();
9925 if (id != BAHAMA_ID) {
9926 pr_err("%s: unexpected adie connectivity type: %d\n",
9927 __func__, id);
9928 return -ENODEV;
9929 }
9930
9931 if (on) {
9932
9933 rc = bluetooth_use_regulators(1);
9934 if (rc < 0)
9935 goto out;
9936
9937 rc = bluetooth_switch_regulators(1);
9938
9939 if (rc < 0)
9940 goto fail_put;
9941
9942 bt_clock = msm_xo_get(MSM_XO_TCXO_D0, "bt_power");
9943
9944 if (IS_ERR(bt_clock)) {
9945 pr_err("Couldn't get TCXO_D0 voter\n");
9946 goto fail_switch;
9947 }
9948
9949 rc = msm_xo_mode_vote(bt_clock, MSM_XO_MODE_ON);
9950
9951 if (rc < 0) {
9952 pr_err("Failed to vote for TCXO_DO ON\n");
9953 goto fail_vote;
9954 }
9955
9956 rc = bahama_bt(1);
9957
9958 if (rc < 0)
9959 goto fail_clock;
9960
9961 msleep(10);
9962
9963 rc = msm_xo_mode_vote(bt_clock, MSM_XO_MODE_PIN_CTRL);
9964
9965 if (rc < 0) {
9966 pr_err("Failed to vote for TCXO_DO pin control\n");
9967 goto fail_vote;
9968 }
9969 } else {
9970 /* check for initial RFKILL block (power off) */
9971 /* some RFKILL versions/configurations rfkill_register */
9972 /* calls here for an initial set_block */
9973 /* avoid calling i2c and regulator before unblock (on) */
9974 if (platform_get_drvdata(&msm_bt_power_device) == NULL) {
9975 dev_info(&msm_bt_power_device.dev,
9976 "%s: initialized OFF/blocked\n", __func__);
9977 goto out;
9978 }
9979
9980 bahama_bt(0);
9981
9982fail_clock:
9983 msm_xo_mode_vote(bt_clock, MSM_XO_MODE_OFF);
9984fail_vote:
9985 msm_xo_put(bt_clock);
9986fail_switch:
9987 bluetooth_switch_regulators(0);
9988fail_put:
9989 bluetooth_use_regulators(0);
9990 }
9991
9992out:
9993 if (rc < 0)
9994 on = 0;
9995 dev_info(&msm_bt_power_device.dev,
9996 "Bluetooth power switch: state %d result %d\n", on, rc);
9997
9998 return rc;
9999}
10000
10001#endif /*CONFIG_MARIMBA_CORE, CONFIG_MSM_BT_POWER, CONFIG_MSM_BT_POWER_MODULE*/
10002
10003static void __init msm8x60_cfg_smsc911x(void)
10004{
10005 smsc911x_resources[1].start =
10006 PM8058_GPIO_IRQ(PM8058_IRQ_BASE, 6);
10007 smsc911x_resources[1].end =
10008 PM8058_GPIO_IRQ(PM8058_IRQ_BASE, 6);
10009}
10010
10011#ifdef CONFIG_MSM_RPM
10012static struct msm_rpm_platform_data msm_rpm_data = {
10013 .reg_base_addrs = {
10014 [MSM_RPM_PAGE_STATUS] = MSM_RPM_BASE,
10015 [MSM_RPM_PAGE_CTRL] = MSM_RPM_BASE + 0x400,
10016 [MSM_RPM_PAGE_REQ] = MSM_RPM_BASE + 0x600,
10017 [MSM_RPM_PAGE_ACK] = MSM_RPM_BASE + 0xa00,
10018 },
10019
10020 .irq_ack = RPM_SCSS_CPU0_GP_HIGH_IRQ,
10021 .irq_err = RPM_SCSS_CPU0_GP_LOW_IRQ,
10022 .irq_vmpm = RPM_SCSS_CPU0_GP_MEDIUM_IRQ,
10023 .msm_apps_ipc_rpm_reg = MSM_GCC_BASE + 0x008,
10024 .msm_apps_ipc_rpm_val = 4,
10025};
10026#endif
10027
Laura Abbott5d2d1e62011-08-10 16:27:35 -070010028void msm_fusion_setup_pinctrl(void)
10029{
10030 struct msm_xo_voter *a1;
10031
10032 if (socinfo_get_platform_subtype() == 0x3) {
10033 /*
10034 * Vote for the A1 clock to be in pin control mode before
10035 * the external images are loaded.
10036 */
10037 a1 = msm_xo_get(MSM_XO_TCXO_A1, "mdm");
10038 BUG_ON(!a1);
10039 msm_xo_mode_vote(a1, MSM_XO_MODE_PIN_CTRL);
10040 }
10041}
10042
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070010043struct msm_board_data {
10044 struct msm_gpiomux_configs *gpiomux_cfgs;
10045};
10046
10047static struct msm_board_data msm8x60_rumi3_board_data __initdata = {
10048 .gpiomux_cfgs = msm8x60_surf_ffa_gpiomux_cfgs,
10049};
10050
10051static struct msm_board_data msm8x60_sim_board_data __initdata = {
10052 .gpiomux_cfgs = msm8x60_surf_ffa_gpiomux_cfgs,
10053};
10054
10055static struct msm_board_data msm8x60_surf_board_data __initdata = {
10056 .gpiomux_cfgs = msm8x60_surf_ffa_gpiomux_cfgs,
10057};
10058
10059static struct msm_board_data msm8x60_ffa_board_data __initdata = {
10060 .gpiomux_cfgs = msm8x60_surf_ffa_gpiomux_cfgs,
10061};
10062
10063static struct msm_board_data msm8x60_fluid_board_data __initdata = {
10064 .gpiomux_cfgs = msm8x60_fluid_gpiomux_cfgs,
10065};
10066
10067static struct msm_board_data msm8x60_charm_surf_board_data __initdata = {
10068 .gpiomux_cfgs = msm8x60_charm_gpiomux_cfgs,
10069};
10070
10071static struct msm_board_data msm8x60_charm_ffa_board_data __initdata = {
10072 .gpiomux_cfgs = msm8x60_charm_gpiomux_cfgs,
10073};
10074
Zhang Chang Kenef05b172011-07-27 15:28:13 -040010075static struct msm_board_data msm8x60_dragon_board_data __initdata = {
10076 .gpiomux_cfgs = msm8x60_dragon_gpiomux_cfgs,
10077};
10078
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070010079static void __init msm8x60_init(struct msm_board_data *board_data)
10080{
10081 uint32_t soc_platform_version;
10082
Abhijeet Dharmapurikar6d565fd2011-09-15 18:49:56 -070010083 pmic_reset_irq = PM8058_RESOUT_IRQ(PM8058_IRQ_BASE);
10084
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070010085 /*
10086 * Initialize RPM first as other drivers and devices may need
10087 * it for their initialization.
10088 */
10089#ifdef CONFIG_MSM_RPM
10090 BUG_ON(msm_rpm_init(&msm_rpm_data));
10091#endif
10092 BUG_ON(msm_rpmrs_levels_init(msm_rpmrs_levels,
10093 ARRAY_SIZE(msm_rpmrs_levels)));
10094 if (msm_xo_init())
10095 pr_err("Failed to initialize XO votes\n");
10096
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070010097 msm8x60_check_2d_hardware();
10098
10099 /* Change SPM handling of core 1 if PMM 8160 is present. */
10100 soc_platform_version = socinfo_get_platform_version();
10101 if (SOCINFO_VERSION_MAJOR(soc_platform_version) == 1 &&
10102 SOCINFO_VERSION_MINOR(soc_platform_version) >= 2) {
10103 struct msm_spm_platform_data *spm_data;
10104
10105 spm_data = &msm_spm_data_v1[1];
10106 spm_data->reg_init_values[MSM_SPM_REG_SAW_CFG] &= ~0x0F00UL;
10107 spm_data->reg_init_values[MSM_SPM_REG_SAW_CFG] |= 0x0100UL;
10108
10109 spm_data = &msm_spm_data[1];
10110 spm_data->reg_init_values[MSM_SPM_REG_SAW_CFG] &= ~0x0F00UL;
10111 spm_data->reg_init_values[MSM_SPM_REG_SAW_CFG] |= 0x0100UL;
10112 }
10113
10114 /*
10115 * Initialize SPM before acpuclock as the latter calls into SPM
10116 * driver to set ACPU voltages.
10117 */
10118 if (SOCINFO_VERSION_MAJOR(socinfo_get_version()) != 1)
10119 msm_spm_init(msm_spm_data, ARRAY_SIZE(msm_spm_data));
10120 else
10121 msm_spm_init(msm_spm_data_v1, ARRAY_SIZE(msm_spm_data_v1));
10122
10123 /*
10124 * Set regulators 8901_l4 and 8901_l6 to be always on in HPM for SURF
10125 * devices so that the RPM doesn't drop into a low power mode that an
10126 * un-reworked SURF cannot resume from.
10127 */
10128 if (machine_is_msm8x60_surf()) {
David Collins6f032ba2011-08-31 14:08:15 -070010129 int i;
10130
10131 for (i = 0; i < ARRAY_SIZE(rpm_regulator_init_data); i++)
10132 if (rpm_regulator_init_data[i].id
10133 == RPM_VREG_ID_PM8901_L4
10134 || rpm_regulator_init_data[i].id
10135 == RPM_VREG_ID_PM8901_L6)
10136 rpm_regulator_init_data[i]
10137 .init_data.constraints.always_on = 1;
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070010138 }
10139
10140 /*
10141 * Disable regulator info printing so that regulator registration
10142 * messages do not enter the kmsg log.
10143 */
10144 regulator_suppress_info_printing();
10145
10146 /* Initialize regulators needed for clock_init. */
10147 platform_add_devices(early_regulators, ARRAY_SIZE(early_regulators));
10148
Stephen Boydbb600ae2011-08-02 20:11:40 -070010149 msm_clock_init(&msm8x60_clock_init_data);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070010150
10151 /* Buses need to be initialized before early-device registration
10152 * to get the platform data for fabrics.
10153 */
10154 msm8x60_init_buses();
10155 platform_add_devices(early_devices, ARRAY_SIZE(early_devices));
10156 /* CPU frequency control is not supported on simulated targets. */
10157 if (!machine_is_msm8x60_rumi3() && !machine_is_msm8x60_sim())
Matt Wagantallec57f062011-08-16 23:54:46 -070010158 acpuclk_init(&acpuclk_8x60_soc_data);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070010159
Terence Hampsonb36a38c2011-09-19 19:10:40 -040010160 /*
10161 * Enable EBI2 only for boards which make use of it. Leave
10162 * it disabled for all others for additional power savings.
10163 */
10164 if (machine_is_msm8x60_surf() || machine_is_msm8x60_ffa() ||
10165 machine_is_msm8x60_rumi3() ||
10166 machine_is_msm8x60_sim() ||
10167 machine_is_msm8x60_fluid() ||
10168 machine_is_msm8x60_dragon())
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070010169 msm8x60_init_ebi2();
10170 msm8x60_init_tlmm();
10171 msm8x60_init_gpiomux(board_data->gpiomux_cfgs);
10172 msm8x60_init_uart12dm();
10173 msm8x60_init_mmc();
10174
10175#if defined(CONFIG_PMIC8058_OTHC) || defined(CONFIG_PMIC8058_OTHC_MODULE)
10176 msm8x60_init_pm8058_othc();
10177#endif
10178
10179 if (machine_is_msm8x60_fluid()) {
10180 pm8058_platform_data.sub_devices[PM8058_SUBDEV_KPD].
10181 platform_data = &fluid_keypad_data;
10182 pm8058_platform_data.sub_devices[PM8058_SUBDEV_KPD].pdata_size
10183 = sizeof(fluid_keypad_data);
Zhang Chang Ken683be172011-08-10 17:45:34 -040010184 } else if (machine_is_msm8x60_dragon()) {
10185 pm8058_platform_data.sub_devices[PM8058_SUBDEV_KPD].
10186 platform_data = &dragon_keypad_data;
10187 pm8058_platform_data.sub_devices[PM8058_SUBDEV_KPD].pdata_size
10188 = sizeof(dragon_keypad_data);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070010189 } else {
10190 pm8058_platform_data.sub_devices[PM8058_SUBDEV_KPD].
10191 platform_data = &ffa_keypad_data;
10192 pm8058_platform_data.sub_devices[PM8058_SUBDEV_KPD].pdata_size
10193 = sizeof(ffa_keypad_data);
10194
10195 }
10196
10197 /* Disable END_CALL simulation function of powerkey on fluid */
10198 if (machine_is_msm8x60_fluid()) {
10199 pwrkey_pdata.pwrkey_time_ms = 0;
10200 }
10201
Jilai Wang53d27a82011-07-13 14:32:58 -040010202 /* Specify reset pin for OV9726 */
10203 if (machine_is_msm8x60_dragon()) {
10204 msm_camera_sensor_ov9726_data.sensor_reset = 62;
10205 ov9726_sensor_8660_info.mount_angle = 270;
10206 }
10207
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070010208 if (machine_is_msm8x60_surf() || machine_is_msm8x60_ffa() ||
10209 machine_is_msm8x60_fluid() || machine_is_msm8x60_fusion() ||
Zhang Chang Ken6baadf02011-08-05 09:48:15 -040010210 machine_is_msm8x60_fusn_ffa() || machine_is_msm8x60_dragon()) {
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070010211 msm8x60_cfg_smsc911x();
10212 if (SOCINFO_VERSION_MAJOR(socinfo_get_version()) != 1)
10213 platform_add_devices(msm_footswitch_devices,
10214 msm_num_footswitch_devices);
10215 platform_add_devices(surf_devices,
10216 ARRAY_SIZE(surf_devices));
10217
10218#ifdef CONFIG_MSM_DSPS
10219 if (machine_is_msm8x60_fluid()) {
10220 platform_device_unregister(&msm_gsbi12_qup_i2c_device);
10221 msm8x60_init_dsps();
10222 }
10223#endif
10224
10225#ifdef CONFIG_USB_EHCI_MSM_72K
10226 /*
10227 * Drive MPP2 pin HIGH for PHY to generate ID interrupts on 8660
10228 * fluid
10229 */
10230 if (machine_is_msm8x60_fluid()) {
10231 pm8901_mpp_config_digital_out(1,
10232 PM8901_MPP_DIG_LEVEL_L5, 1);
10233 }
10234 msm_add_host(0, &msm_usb_host_pdata);
10235#endif
Lei Zhou338cab82011-08-19 13:38:17 -040010236
10237#ifdef CONFIG_SND_SOC_MSM8660_APQ
10238 if (machine_is_msm8x60_dragon())
10239 platform_add_devices(dragon_alsa_devices,
10240 ARRAY_SIZE(dragon_alsa_devices));
10241 else
10242#endif
10243 platform_add_devices(asoc_devices,
10244 ARRAY_SIZE(asoc_devices));
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070010245 } else {
10246 msm8x60_configure_smc91x();
10247 platform_add_devices(rumi_sim_devices,
10248 ARRAY_SIZE(rumi_sim_devices));
10249 }
10250#if defined(CONFIG_USB_PEHCI_HCD) || defined(CONFIG_USB_PEHCI_HCD_MODULE)
Zhang Chang Ken6baadf02011-08-05 09:48:15 -040010251 if (machine_is_msm8x60_surf() || machine_is_msm8x60_ffa() ||
10252 machine_is_msm8x60_dragon())
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070010253 msm8x60_cfg_isp1763();
10254#endif
10255#ifdef CONFIG_BATTERY_MSM8X60
10256 if (machine_is_msm8x60_surf() || machine_is_msm8x60_ffa() ||
Zhang Chang Ken6baadf02011-08-05 09:48:15 -040010257 machine_is_msm8x60_fusion() || machine_is_msm8x60_dragon() ||
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070010258 machine_is_msm8x60_fusn_ffa() || machine_is_msm8x60_fluid())
10259 platform_device_register(&msm_charger_device);
10260#endif
10261
10262 if (machine_is_msm8x60_fusion() || machine_is_msm8x60_fusn_ffa())
10263 platform_add_devices(charm_devices, ARRAY_SIZE(charm_devices));
10264
Terence Hampson90508a92011-08-09 10:40:08 -040010265 if (machine_is_msm8x60_dragon()) {
10266 pm8058_charger_sub_dev.platform_data
10267 = &pmic8058_charger_dragon;
10268 pm8058_charger_sub_dev.pdata_size
10269 = sizeof(pmic8058_charger_dragon);
10270 }
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070010271 if (!machine_is_msm8x60_fluid())
10272 pm8058_platform_data.charger_sub_device
10273 = &pm8058_charger_sub_dev;
10274
10275#if defined(CONFIG_SPI_QUP) || defined(CONFIG_SPI_QUP_MODULE)
10276 if (machine_is_msm8x60_fluid())
10277 platform_device_register(&msm_gsbi10_qup_spi_device);
10278 else
10279 platform_device_register(&msm_gsbi1_qup_spi_device);
10280#endif
10281
10282#if defined(CONFIG_TOUCHSCREEN_CYTTSP_I2C) || \
10283 defined(CONFIG_TOUCHSCREEN_CYTTSP_I2C_MODULE)
10284 if (machine_is_msm8x60_fluid())
10285 cyttsp_set_params();
10286#endif
10287 if (!machine_is_msm8x60_sim())
10288 msm_fb_add_devices();
10289 fixup_i2c_configs();
10290 register_i2c_devices();
10291
Terence Hampson1c73fef2011-07-19 17:10:49 -040010292 if (machine_is_msm8x60_dragon())
10293 smsc911x_config.reset_gpio
10294 = GPIO_ETHERNET_RESET_N_DRAGON;
10295
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070010296 platform_device_register(&smsc911x_device);
10297
10298#if (defined(CONFIG_SPI_QUP)) && \
10299 (defined(CONFIG_FB_MSM_LCDC_SAMSUNG_OLED_PT) || \
Zhang Chang Ken3a8b8512011-08-04 18:41:39 -040010300 defined(CONFIG_FB_MSM_LCDC_AUO_WVGA) || \
10301 defined(CONFIG_FB_MSM_LCDC_NT35582_WVGA))
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070010302
10303 if (machine_is_msm8x60_fluid()) {
10304#ifdef CONFIG_FB_MSM_LCDC_SAMSUNG_OLED_PT
10305 if (SOCINFO_VERSION_MAJOR(soc_platform_version) < 3) {
10306 spi_register_board_info(lcdc_samsung_spi_board_info,
10307 ARRAY_SIZE(lcdc_samsung_spi_board_info));
10308 } else
10309#endif
10310 {
10311#ifdef CONFIG_FB_MSM_LCDC_AUO_WVGA
10312 spi_register_board_info(lcdc_auo_spi_board_info,
10313 ARRAY_SIZE(lcdc_auo_spi_board_info));
10314#endif
10315 }
Zhang Chang Ken3a8b8512011-08-04 18:41:39 -040010316#ifdef CONFIG_FB_MSM_LCDC_NT35582_WVGA
10317 } else if (machine_is_msm8x60_dragon()) {
10318 spi_register_board_info(lcdc_nt35582_spi_board_info,
10319 ARRAY_SIZE(lcdc_nt35582_spi_board_info));
10320#endif
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070010321 }
10322#endif
10323
10324 msm_pm_set_platform_data(msm_pm_data, ARRAY_SIZE(msm_pm_data));
10325 msm_pm_set_rpm_wakeup_irq(RPM_SCSS_CPU0_WAKE_UP_IRQ);
10326 msm_cpuidle_set_states(msm_cstates, ARRAY_SIZE(msm_cstates),
10327 msm_pm_data);
Maheshkumar Sivasubramanian8ccc16e2011-10-25 15:59:57 -060010328 BUG_ON(msm_pm_boot_init(MSM_PM_BOOT_CONFIG_TZ, NULL));
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070010329
10330#ifdef CONFIG_SENSORS_MSM_ADC
10331 if (machine_is_msm8x60_fluid()) {
10332 msm_adc_pdata.dev_names = msm_adc_fluid_device_names;
10333 msm_adc_pdata.num_adc = ARRAY_SIZE(msm_adc_fluid_device_names);
10334 if (SOCINFO_VERSION_MAJOR(soc_platform_version) < 3)
10335 msm_adc_pdata.gpio_config = APROC_CONFIG;
10336 else
10337 msm_adc_pdata.gpio_config = MPROC_CONFIG;
10338 }
10339 msm_adc_pdata.target_hw = MSM_8x60;
10340#endif
10341#ifdef CONFIG_MSM8X60_AUDIO
10342 msm_snddev_init();
10343#endif
10344#if defined(CONFIG_GPIO_SX150X) || defined(CONFIG_GPIO_SX150X_MODULE)
10345 if (machine_is_msm8x60_fluid())
10346 platform_device_register(&fluid_leds_gpio);
10347 else
10348 platform_device_register(&gpio_leds);
10349#endif
10350
10351 /* configure pmic leds */
10352 if (machine_is_msm8x60_fluid()) {
10353 pm8058_platform_data.sub_devices[PM8058_SUBDEV_LED].
10354 platform_data = &pm8058_fluid_flash_leds_data;
10355 pm8058_platform_data.sub_devices[PM8058_SUBDEV_LED].pdata_size
10356 = sizeof(pm8058_fluid_flash_leds_data);
Terence Hampsonc0b6dfb2011-07-15 11:07:17 -040010357 } else if (machine_is_msm8x60_dragon()) {
10358 pm8058_platform_data.sub_devices[PM8058_SUBDEV_LED].
10359 platform_data = &pm8058_dragon_leds_data;
10360 pm8058_platform_data.sub_devices[PM8058_SUBDEV_LED].pdata_size
10361 = sizeof(pm8058_dragon_leds_data);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070010362 } else {
10363 pm8058_platform_data.sub_devices[PM8058_SUBDEV_LED].
10364 platform_data = &pm8058_flash_leds_data;
10365 pm8058_platform_data.sub_devices[PM8058_SUBDEV_LED].pdata_size
10366 = sizeof(pm8058_flash_leds_data);
10367 }
10368
Zhang Chang Ken6baadf02011-08-05 09:48:15 -040010369 if (machine_is_msm8x60_ffa() || machine_is_msm8x60_fusn_ffa() ||
10370 machine_is_msm8x60_dragon()) {
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070010371 pm8058_platform_data.sub_devices[PM8058_SUBDEV_VIB].
10372 platform_data = &pmic_vib_pdata;
10373 pm8058_platform_data.sub_devices[PM8058_SUBDEV_VIB].
10374 pdata_size = sizeof(pmic_vib_pdata);
10375 }
10376
10377 msm8x60_multi_sdio_init();
Laura Abbott5d2d1e62011-08-10 16:27:35 -070010378
10379 if (machine_is_msm8x60_fusion() || machine_is_msm8x60_fusn_ffa())
10380 msm_fusion_setup_pinctrl();
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070010381}
10382
10383static void __init msm8x60_rumi3_init(void)
10384{
10385 msm8x60_init(&msm8x60_rumi3_board_data);
10386}
10387
10388static void __init msm8x60_sim_init(void)
10389{
10390 msm8x60_init(&msm8x60_sim_board_data);
10391}
10392
10393static void __init msm8x60_surf_init(void)
10394{
10395 msm8x60_init(&msm8x60_surf_board_data);
10396}
10397
10398static void __init msm8x60_ffa_init(void)
10399{
10400 msm8x60_init(&msm8x60_ffa_board_data);
10401}
10402
10403static void __init msm8x60_fluid_init(void)
10404{
10405 msm8x60_init(&msm8x60_fluid_board_data);
10406}
10407
10408static void __init msm8x60_charm_surf_init(void)
10409{
10410 msm8x60_init(&msm8x60_charm_surf_board_data);
10411}
10412
10413static void __init msm8x60_charm_ffa_init(void)
10414{
10415 msm8x60_init(&msm8x60_charm_ffa_board_data);
10416}
10417
10418static void __init msm8x60_charm_init_early(void)
10419{
10420 msm8x60_allocate_memory_regions();
Steve Mucklea55df6e2010-01-07 12:43:24 -080010421}
10422
Zhang Chang Kenef05b172011-07-27 15:28:13 -040010423static void __init msm8x60_dragon_init(void)
10424{
10425 msm8x60_init(&msm8x60_dragon_board_data);
10426}
10427
Steve Mucklea55df6e2010-01-07 12:43:24 -080010428MACHINE_START(MSM8X60_RUMI3, "QCT MSM8X60 RUMI3")
10429 .map_io = msm8x60_map_io,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070010430 .reserve = msm8x60_reserve,
Steve Mucklea55df6e2010-01-07 12:43:24 -080010431 .init_irq = msm8x60_init_irq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070010432 .init_machine = msm8x60_rumi3_init,
Steve Mucklea55df6e2010-01-07 12:43:24 -080010433 .timer = &msm_timer,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070010434 .init_early = msm8x60_charm_init_early,
Steve Muckle49b76f72010-03-19 17:00:08 -070010435MACHINE_END
Steve Muckle57bbf1c2010-01-07 12:51:10 -080010436
10437MACHINE_START(MSM8X60_SIM, "QCT MSM8X60 SIMULATOR")
10438 .map_io = msm8x60_map_io,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070010439 .reserve = msm8x60_reserve,
Steve Muckle57bbf1c2010-01-07 12:51:10 -080010440 .init_irq = msm8x60_init_irq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070010441 .init_machine = msm8x60_sim_init,
Steve Muckle57bbf1c2010-01-07 12:51:10 -080010442 .timer = &msm_timer,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070010443 .init_early = msm8x60_charm_init_early,
10444MACHINE_END
10445
10446MACHINE_START(MSM8X60_SURF, "QCT MSM8X60 SURF")
10447 .map_io = msm8x60_map_io,
10448 .reserve = msm8x60_reserve,
10449 .init_irq = msm8x60_init_irq,
10450 .init_machine = msm8x60_surf_init,
10451 .timer = &msm_timer,
10452 .init_early = msm8x60_charm_init_early,
Steve Muckle57bbf1c2010-01-07 12:51:10 -080010453MACHINE_END
Gregory Bean69b7f6f2010-04-04 22:29:02 -070010454
10455MACHINE_START(MSM8X60_FFA, "QCT MSM8X60 FFA")
10456 .map_io = msm8x60_map_io,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070010457 .reserve = msm8x60_reserve,
Gregory Bean69b7f6f2010-04-04 22:29:02 -070010458 .init_irq = msm8x60_init_irq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070010459 .init_machine = msm8x60_ffa_init,
Gregory Bean69b7f6f2010-04-04 22:29:02 -070010460 .timer = &msm_timer,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070010461 .init_early = msm8x60_charm_init_early,
10462MACHINE_END
10463
10464MACHINE_START(MSM8X60_FLUID, "QCT MSM8X60 FLUID")
10465 .map_io = msm8x60_map_io,
10466 .reserve = msm8x60_reserve,
10467 .init_irq = msm8x60_init_irq,
10468 .init_machine = msm8x60_fluid_init,
10469 .timer = &msm_timer,
10470 .init_early = msm8x60_charm_init_early,
10471MACHINE_END
10472
10473MACHINE_START(MSM8X60_FUSION, "QCT MSM8X60 FUSION SURF")
10474 .map_io = msm8x60_map_io,
10475 .reserve = msm8x60_reserve,
10476 .init_irq = msm8x60_init_irq,
10477 .init_machine = msm8x60_charm_surf_init,
10478 .timer = &msm_timer,
10479 .init_early = msm8x60_charm_init_early,
10480MACHINE_END
10481
10482MACHINE_START(MSM8X60_FUSN_FFA, "QCT MSM8X60 FUSION FFA")
10483 .map_io = msm8x60_map_io,
10484 .reserve = msm8x60_reserve,
10485 .init_irq = msm8x60_init_irq,
10486 .init_machine = msm8x60_charm_ffa_init,
10487 .timer = &msm_timer,
10488 .init_early = msm8x60_charm_init_early,
Gregory Bean69b7f6f2010-04-04 22:29:02 -070010489MACHINE_END
Zhang Chang Kenef05b172011-07-27 15:28:13 -040010490
10491MACHINE_START(MSM8X60_DRAGON, "QCT MSM8X60 DRAGON")
10492 .map_io = msm8x60_map_io,
10493 .reserve = msm8x60_reserve,
10494 .init_irq = msm8x60_init_irq,
10495 .init_machine = msm8x60_dragon_init,
10496 .timer = &msm_timer,
10497 .init_early = msm8x60_charm_init_early,
10498MACHINE_END