Nicolas Pitre | 6b5cdf0 | 2008-06-27 18:56:22 -0400 | [diff] [blame^] | 1 | /* |
| 2 | * arch/arm/mach-orion5x/rd88f5181l-fxo-setup.c |
| 3 | * |
| 4 | * Marvell Orion-VoIP FXO Reference Design Setup |
| 5 | * |
| 6 | * This file is licensed under the terms of the GNU General Public |
| 7 | * License version 2. This program is licensed "as is" without any |
| 8 | * warranty of any kind, whether express or implied. |
| 9 | */ |
| 10 | |
| 11 | #include <linux/kernel.h> |
| 12 | #include <linux/init.h> |
| 13 | #include <linux/platform_device.h> |
| 14 | #include <linux/pci.h> |
| 15 | #include <linux/irq.h> |
| 16 | #include <linux/mtd/physmap.h> |
| 17 | #include <linux/mv643xx_eth.h> |
| 18 | #include <asm/mach-types.h> |
| 19 | #include <asm/gpio.h> |
| 20 | #include <asm/leds.h> |
| 21 | #include <asm/mach/arch.h> |
| 22 | #include <asm/mach/pci.h> |
| 23 | #include <asm/arch/orion5x.h> |
| 24 | #include "common.h" |
| 25 | #include "mpp.h" |
| 26 | |
| 27 | /***************************************************************************** |
| 28 | * RD-88F5181L FXO Info |
| 29 | ****************************************************************************/ |
| 30 | /* |
| 31 | * 8M NOR flash Device bus boot chip select |
| 32 | */ |
| 33 | #define RD88F5181L_FXO_NOR_BOOT_BASE 0xff800000 |
| 34 | #define RD88F5181L_FXO_NOR_BOOT_SIZE SZ_8M |
| 35 | |
| 36 | |
| 37 | /***************************************************************************** |
| 38 | * 8M NOR Flash on Device bus Boot chip select |
| 39 | ****************************************************************************/ |
| 40 | static struct physmap_flash_data rd88f5181l_fxo_nor_boot_flash_data = { |
| 41 | .width = 1, |
| 42 | }; |
| 43 | |
| 44 | static struct resource rd88f5181l_fxo_nor_boot_flash_resource = { |
| 45 | .flags = IORESOURCE_MEM, |
| 46 | .start = RD88F5181L_FXO_NOR_BOOT_BASE, |
| 47 | .end = RD88F5181L_FXO_NOR_BOOT_BASE + |
| 48 | RD88F5181L_FXO_NOR_BOOT_SIZE - 1, |
| 49 | }; |
| 50 | |
| 51 | static struct platform_device rd88f5181l_fxo_nor_boot_flash = { |
| 52 | .name = "physmap-flash", |
| 53 | .id = 0, |
| 54 | .dev = { |
| 55 | .platform_data = &rd88f5181l_fxo_nor_boot_flash_data, |
| 56 | }, |
| 57 | .num_resources = 1, |
| 58 | .resource = &rd88f5181l_fxo_nor_boot_flash_resource, |
| 59 | }; |
| 60 | |
| 61 | |
| 62 | /***************************************************************************** |
| 63 | * General Setup |
| 64 | ****************************************************************************/ |
| 65 | static struct orion5x_mpp_mode rd88f5181l_fxo_mpp_modes[] __initdata = { |
| 66 | { 0, MPP_GPIO }, /* LED1 CardBus LED (front panel) */ |
| 67 | { 1, MPP_GPIO }, /* PCI_intA */ |
| 68 | { 2, MPP_GPIO }, /* Hard Reset / Factory Init*/ |
| 69 | { 3, MPP_GPIO }, /* FXS or DAA select */ |
| 70 | { 4, MPP_GPIO }, /* LED6 - phone LED (front panel) */ |
| 71 | { 5, MPP_GPIO }, /* LED5 - phone LED (front panel) */ |
| 72 | { 6, MPP_PCI_CLK }, /* CPU PCI refclk */ |
| 73 | { 7, MPP_PCI_CLK }, /* PCI/PCIe refclk */ |
| 74 | { 8, MPP_GPIO }, /* CardBus reset */ |
| 75 | { 9, MPP_GPIO }, /* GE_RXERR */ |
| 76 | { 10, MPP_GPIO }, /* LED2 MiniPCI LED (front panel) */ |
| 77 | { 11, MPP_GPIO }, /* Lifeline control */ |
| 78 | { 12, MPP_GIGE }, /* GE_TXD[4] */ |
| 79 | { 13, MPP_GIGE }, /* GE_TXD[5] */ |
| 80 | { 14, MPP_GIGE }, /* GE_TXD[6] */ |
| 81 | { 15, MPP_GIGE }, /* GE_TXD[7] */ |
| 82 | { 16, MPP_GIGE }, /* GE_RXD[4] */ |
| 83 | { 17, MPP_GIGE }, /* GE_RXD[5] */ |
| 84 | { 18, MPP_GIGE }, /* GE_RXD[6] */ |
| 85 | { 19, MPP_GIGE }, /* GE_RXD[7] */ |
| 86 | { -1 }, |
| 87 | }; |
| 88 | |
| 89 | static struct mv643xx_eth_platform_data rd88f5181l_fxo_eth_data = { |
| 90 | .phy_addr = -1, |
| 91 | }; |
| 92 | |
| 93 | static void __init rd88f5181l_fxo_init(void) |
| 94 | { |
| 95 | /* |
| 96 | * Setup basic Orion functions. Need to be called early. |
| 97 | */ |
| 98 | orion5x_init(); |
| 99 | |
| 100 | orion5x_mpp_conf(rd88f5181l_fxo_mpp_modes); |
| 101 | |
| 102 | /* |
| 103 | * Configure peripherals. |
| 104 | */ |
| 105 | orion5x_ehci0_init(); |
| 106 | orion5x_eth_init(&rd88f5181l_fxo_eth_data); |
| 107 | orion5x_uart0_init(); |
| 108 | |
| 109 | orion5x_setup_dev_boot_win(RD88F5181L_FXO_NOR_BOOT_BASE, |
| 110 | RD88F5181L_FXO_NOR_BOOT_SIZE); |
| 111 | platform_device_register(&rd88f5181l_fxo_nor_boot_flash); |
| 112 | } |
| 113 | |
| 114 | static int __init |
| 115 | rd88f5181l_fxo_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin) |
| 116 | { |
| 117 | int irq; |
| 118 | |
| 119 | /* |
| 120 | * Check for devices with hard-wired IRQs. |
| 121 | */ |
| 122 | irq = orion5x_pci_map_irq(dev, slot, pin); |
| 123 | if (irq != -1) |
| 124 | return irq; |
| 125 | |
| 126 | /* |
| 127 | * Mini-PCI / Cardbus slot. |
| 128 | */ |
| 129 | return gpio_to_irq(1); |
| 130 | } |
| 131 | |
| 132 | static struct hw_pci rd88f5181l_fxo_pci __initdata = { |
| 133 | .nr_controllers = 2, |
| 134 | .swizzle = pci_std_swizzle, |
| 135 | .setup = orion5x_pci_sys_setup, |
| 136 | .scan = orion5x_pci_sys_scan_bus, |
| 137 | .map_irq = rd88f5181l_fxo_pci_map_irq, |
| 138 | }; |
| 139 | |
| 140 | static int __init rd88f5181l_fxo_pci_init(void) |
| 141 | { |
| 142 | if (machine_is_rd88f5181l_fxo()) { |
| 143 | orion5x_pci_set_cardbus_mode(); |
| 144 | pci_common_init(&rd88f5181l_fxo_pci); |
| 145 | } |
| 146 | |
| 147 | return 0; |
| 148 | } |
| 149 | subsys_initcall(rd88f5181l_fxo_pci_init); |
| 150 | |
| 151 | MACHINE_START(RD88F5181L_FXO, "Marvell Orion-VoIP FXO Reference Design") |
| 152 | /* Maintainer: Nicolas Pitre <nico@marvell.com> */ |
| 153 | .phys_io = ORION5X_REGS_PHYS_BASE, |
| 154 | .io_pg_offst = ((ORION5X_REGS_VIRT_BASE) >> 18) & 0xFFFC, |
| 155 | .boot_params = 0x00000100, |
| 156 | .init_machine = rd88f5181l_fxo_init, |
| 157 | .map_io = orion5x_map_io, |
| 158 | .init_irq = orion5x_init_irq, |
| 159 | .timer = &orion5x_timer, |
| 160 | .fixup = tag_fixup_mem32, |
| 161 | MACHINE_END |