blob: edebbd852ccfc1e8aee655f41aa34441294abf6b [file] [log] [blame]
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001/* Copyright (c) 2009-2011, Code Aurora Forum. All rights reserved.
Daniel Walker8d747cd2010-02-25 11:37:43 -08002 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 *
Daniel Walker8d747cd2010-02-25 11:37:43 -080012 */
13
14#include <linux/kernel.h>
15#include <linux/irq.h>
16#include <linux/gpio.h>
17#include <linux/platform_device.h>
18#include <linux/delay.h>
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070019#include <linux/bootmem.h>
Daniel Walker8d747cd2010-02-25 11:37:43 -080020#include <linux/io.h>
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070021#ifdef CONFIG_SPI_QSD
22#include <linux/spi/spi.h>
23#endif
24#include <linux/mfd/pmic8058.h>
25#include <linux/mfd/marimba.h>
26#include <linux/i2c.h>
27#include <linux/input.h>
Daniel Walker8d747cd2010-02-25 11:37:43 -080028#include <linux/smsc911x.h>
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070029#include <linux/ofn_atlab.h>
30#include <linux/power_supply.h>
31#include <linux/input/pmic8058-keypad.h>
32#include <linux/i2c/isa1200.h>
33#include <linux/pwm.h>
34#include <linux/pmic8058-pwm.h>
35#include <linux/i2c/tsc2007.h>
36#include <linux/input/kp_flip_switch.h>
37#include <linux/leds-pmic8058.h>
38#include <linux/input/cy8c_ts.h>
39#include <linux/msm_adc.h>
40#include <linux/dma-mapping.h>
Daniel Walker8d747cd2010-02-25 11:37:43 -080041
42#include <asm/mach-types.h>
43#include <asm/mach/arch.h>
44#include <asm/setup.h>
45
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070046#include <mach/mpp.h>
Daniel Walker8d747cd2010-02-25 11:37:43 -080047#include <mach/board.h>
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070048#include <mach/camera.h>
49#include <mach/memory.h>
Daniel Walker8d747cd2010-02-25 11:37:43 -080050#include <mach/msm_iomap.h>
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070051#include <mach/msm_hsusb.h>
52#include <mach/rpc_hsusb.h>
53#include <mach/msm_spi.h>
54#include <mach/qdsp5v2/msm_lpa.h>
Daniel Walker8d747cd2010-02-25 11:37:43 -080055#include <mach/dma.h>
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070056#include <linux/android_pmem.h>
57#include <linux/input/msm_ts.h>
58#include <mach/pmic.h>
59#include <mach/rpc_pmapp.h>
60#include <mach/qdsp5v2/aux_pcm.h>
61#include <mach/qdsp5v2/mi2s.h>
62#include <mach/qdsp5v2/audio_dev_ctl.h>
63#include <mach/msm_battery.h>
64#include <mach/rpc_server_handset.h>
65#include <mach/msm_tsif.h>
66#include <mach/socinfo.h>
67#include <mach/msm_memtypes.h>
68#include <linux/cyttsp.h>
Daniel Walker8d747cd2010-02-25 11:37:43 -080069
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070070#include <asm/mach/mmc.h>
71#include <asm/mach/flash.h>
Daniel Walker8d747cd2010-02-25 11:37:43 -080072#include <mach/vreg.h>
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070073#include <linux/platform_data/qcom_crypto_device.h>
74
Daniel Walker8d747cd2010-02-25 11:37:43 -080075#include "devices.h"
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070076#include "timer.h"
77#ifdef CONFIG_USB_G_ANDROID
78#include <linux/usb/android.h>
79#include <mach/usbdiag.h>
80#endif
81#include "pm.h"
82#include "spm.h"
Matt Wagantall6d9ebee2011-08-26 12:15:24 -070083#include "acpuclock.h"
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070084#include <mach/dal_axi.h>
85#include <mach/msm_serial_hs.h>
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070086#include <mach/qdsp5v2/mi2s.h>
87#include <mach/qdsp5v2/audio_dev_ctl.h>
88#include <mach/sdio_al.h>
89#include "smd_private.h"
90#include <linux/bma150.h>
Daniel Walker8d747cd2010-02-25 11:37:43 -080091
Justin Paupore637a25d2011-07-14 17:11:04 -070092#include "board-msm7x30-regulator.h"
93
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070094#define MSM_PMEM_SF_SIZE 0x1700000
95#ifdef CONFIG_FB_MSM_TRIPLE_BUFFER
96#define MSM_FB_SIZE 0x780000
97#else
98#define MSM_FB_SIZE 0x500000
99#endif
100#define MSM_PMEM_ADSP_SIZE 0x1E00000
101#define MSM_FLUID_PMEM_ADSP_SIZE 0x2800000
102#define PMEM_KERNEL_EBI0_SIZE 0x600000
103#define MSM_PMEM_AUDIO_SIZE 0x200000
Daniel Walker90e37c52010-05-12 14:24:15 -0700104
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700105#define PMIC_GPIO_INT 27
106#define PMIC_VREG_WLAN_LEVEL 2900
107#define PMIC_GPIO_SD_DET 36
108#define PMIC_GPIO_SDC4_EN_N 17 /* PMIC GPIO Number 18 */
109#define PMIC_GPIO_HDMI_5V_EN_V3 32 /* PMIC GPIO for V3 H/W */
110#define PMIC_GPIO_HDMI_5V_EN_V2 39 /* PMIC GPIO for V2 H/W */
111
112#define ADV7520_I2C_ADDR 0x39
113
114#define FPGA_SDCC_STATUS 0x8E0001A8
115
116#define FPGA_OPTNAV_GPIO_ADDR 0x8E000026
117#define OPTNAV_I2C_SLAVE_ADDR (0xB0 >> 1)
118#define OPTNAV_IRQ 20
119#define OPTNAV_CHIP_SELECT 19
120
121/* Macros assume PMIC GPIOs start at 0 */
122#define PM8058_GPIO_PM_TO_SYS(pm_gpio) (pm_gpio + NR_GPIO_IRQS)
123#define PM8058_GPIO_SYS_TO_PM(sys_gpio) (sys_gpio - NR_GPIO_IRQS)
124
125#define PMIC_GPIO_FLASH_BOOST_ENABLE 15 /* PMIC GPIO Number 16 */
126#define PMIC_GPIO_HAP_ENABLE 16 /* PMIC GPIO Number 17 */
127
128#define PMIC_GPIO_WLAN_EXT_POR 22 /* PMIC GPIO NUMBER 23 */
129
130#define BMA150_GPIO_INT 1
131
132#define HAP_LVL_SHFT_MSM_GPIO 24
133
134#define PMIC_GPIO_QUICKVX_CLK 37 /* PMIC GPIO 38 */
135
136#define PM_FLIP_MPP 5 /* PMIC MPP 06 */
137static int pm8058_gpios_init(void)
138{
139 int rc;
140 int pmic_gpio_hdmi_5v_en;
141
142#ifdef CONFIG_MMC_MSM_CARD_HW_DETECTION
143 struct pm8058_gpio sdcc_det = {
144 .direction = PM_GPIO_DIR_IN,
145 .pull = PM_GPIO_PULL_UP_1P5,
146 .vin_sel = 2,
147 .function = PM_GPIO_FUNC_NORMAL,
148 .inv_int_pol = 0,
149 };
150#endif
151 struct pm8058_gpio sdc4_en = {
152 .direction = PM_GPIO_DIR_OUT,
153 .pull = PM_GPIO_PULL_NO,
154 .vin_sel = PM_GPIO_VIN_L5,
155 .function = PM_GPIO_FUNC_NORMAL,
156 .inv_int_pol = 0,
157 .out_strength = PM_GPIO_STRENGTH_LOW,
158 .output_value = 0,
159 };
160
161 struct pm8058_gpio haptics_enable = {
162 .direction = PM_GPIO_DIR_OUT,
163 .pull = PM_GPIO_PULL_NO,
164 .out_strength = PM_GPIO_STRENGTH_HIGH,
165 .function = PM_GPIO_FUNC_NORMAL,
166 .inv_int_pol = 0,
167 .vin_sel = 2,
168 .output_buffer = PM_GPIO_OUT_BUF_CMOS,
169 .output_value = 0,
170 };
171
172 struct pm8058_gpio hdmi_5V_en = {
173 .direction = PM_GPIO_DIR_OUT,
174 .pull = PM_GPIO_PULL_NO,
175 .vin_sel = PM_GPIO_VIN_VPH,
176 .function = PM_GPIO_FUNC_NORMAL,
177 .out_strength = PM_GPIO_STRENGTH_LOW,
178 .output_value = 0,
179 };
180
181 struct pm8058_gpio flash_boost_enable = {
182 .direction = PM_GPIO_DIR_OUT,
183 .output_buffer = PM_GPIO_OUT_BUF_CMOS,
184 .output_value = 0,
185 .pull = PM_GPIO_PULL_NO,
186 .vin_sel = PM_GPIO_VIN_S3,
187 .out_strength = PM_GPIO_STRENGTH_HIGH,
188 .function = PM_GPIO_FUNC_2,
189 };
190
191 struct pm8058_gpio gpio23 = {
192 .direction = PM_GPIO_DIR_OUT,
193 .output_buffer = PM_GPIO_OUT_BUF_CMOS,
194 .output_value = 0,
195 .pull = PM_GPIO_PULL_NO,
196 .vin_sel = 2,
197 .out_strength = PM_GPIO_STRENGTH_LOW,
198 .function = PM_GPIO_FUNC_NORMAL,
199 };
200
201
202 if (machine_is_msm8x55_svlte_surf() || machine_is_msm8x55_svlte_ffa() ||
203 machine_is_msm7x30_fluid())
204 pmic_gpio_hdmi_5v_en = PMIC_GPIO_HDMI_5V_EN_V2 ;
205 else
206 pmic_gpio_hdmi_5v_en = PMIC_GPIO_HDMI_5V_EN_V3 ;
207
208 if (machine_is_msm7x30_fluid()) {
209 rc = pm8058_gpio_config(PMIC_GPIO_HAP_ENABLE, &haptics_enable);
210 if (rc) {
211 pr_err("%s: PMIC GPIO %d write failed\n", __func__,
212 (PMIC_GPIO_HAP_ENABLE + 1));
213 return rc;
214 }
215 rc = pm8058_gpio_config(PMIC_GPIO_FLASH_BOOST_ENABLE,
216 &flash_boost_enable);
217 if (rc) {
218 pr_err("%s: PMIC GPIO %d write failed\n", __func__,
219 (PMIC_GPIO_FLASH_BOOST_ENABLE + 1));
220 return rc;
221 }
222 }
223
224#ifdef CONFIG_MMC_MSM_CARD_HW_DETECTION
225 if (machine_is_msm7x30_fluid())
226 sdcc_det.inv_int_pol = 1;
227
228 rc = pm8058_gpio_config(PMIC_GPIO_SD_DET - 1, &sdcc_det);
229 if (rc) {
230 pr_err("%s PMIC_GPIO_SD_DET config failed\n", __func__);
231 return rc;
232 }
233#endif
234
235 rc = pm8058_gpio_config(pmic_gpio_hdmi_5v_en, &hdmi_5V_en);
236 if (rc) {
237 pr_err("%s PMIC_GPIO_HDMI_5V_EN config failed\n", __func__);
238 return rc;
239 }
240
241 /* Deassert GPIO#23 (source for Ext_POR on WLAN-Volans) */
242 rc = pm8058_gpio_config(PMIC_GPIO_WLAN_EXT_POR, &gpio23);
243 if (rc) {
244 pr_err("%s PMIC_GPIO_WLAN_EXT_POR config failed\n", __func__);
245 return rc;
246 }
247
248 if (machine_is_msm7x30_fluid()) {
249 rc = pm8058_gpio_config(PMIC_GPIO_SDC4_EN_N, &sdc4_en);
250 if (rc) {
251 pr_err("%s PMIC_GPIO_SDC4_EN_N config failed\n",
252 __func__);
253 return rc;
254 }
255 rc = gpio_request(PM8058_GPIO_PM_TO_SYS(PMIC_GPIO_SDC4_EN_N),
256 "sdc4_en");
257 if (rc) {
258 pr_err("%s PMIC_GPIO_SDC4_EN_N gpio_request failed\n",
259 __func__);
260 return rc;
261 }
262 gpio_set_value_cansleep(
263 PM8058_GPIO_PM_TO_SYS(PMIC_GPIO_SDC4_EN_N), 0);
264 }
265
266 return 0;
267}
268
Justin Paupore637a25d2011-07-14 17:11:04 -0700269/* Regulator API support */
270
271#ifdef CONFIG_MSM_PROC_COMM_REGULATOR
272static struct platform_device msm_proccomm_regulator_dev = {
273 .name = PROCCOMM_REGULATOR_DEV_NAME,
274 .id = -1,
275 .dev = {
276 .platform_data = &msm7x30_proccomm_regulator_data
277 }
278};
279#endif
280
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700281/*virtual key support */
282static ssize_t tma300_vkeys_show(struct kobject *kobj,
283 struct kobj_attribute *attr, char *buf)
284{
285 return sprintf(buf,
286 __stringify(EV_KEY) ":" __stringify(KEY_BACK) ":50:842:80:100"
287 ":" __stringify(EV_KEY) ":" __stringify(KEY_MENU) ":170:842:80:100"
288 ":" __stringify(EV_KEY) ":" __stringify(KEY_HOME) ":290:842:80:100"
289 ":" __stringify(EV_KEY) ":" __stringify(KEY_SEARCH) ":410:842:80:100"
290 "\n");
291}
292
293static struct kobj_attribute tma300_vkeys_attr = {
294 .attr = {
295 .mode = S_IRUGO,
296 },
297 .show = &tma300_vkeys_show,
Pavankumar Kondeti5155e2c2010-12-08 13:37:08 +0530298};
299
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700300static struct attribute *tma300_properties_attrs[] = {
301 &tma300_vkeys_attr.attr,
302 NULL
Pavankumar Kondeti5155e2c2010-12-08 13:37:08 +0530303};
304
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700305static struct attribute_group tma300_properties_attr_group = {
306 .attrs = tma300_properties_attrs,
307};
308
309static struct kobject *properties_kobj;
310
311#define CYTTSP_TS_GPIO_IRQ 150
312static int cyttsp_platform_init(struct i2c_client *client)
313{
314 int rc = -EINVAL;
315 struct vreg *vreg_ldo8, *vreg_ldo15;
316
317 vreg_ldo8 = vreg_get(NULL, "gp7");
318
319 if (!vreg_ldo8) {
320 pr_err("%s: VREG L8 get failed\n", __func__);
321 return rc;
322 }
323
324 rc = vreg_set_level(vreg_ldo8, 1800);
325 if (rc) {
326 pr_err("%s: VREG L8 set failed\n", __func__);
327 goto l8_put;
328 }
329
330 rc = vreg_enable(vreg_ldo8);
331 if (rc) {
332 pr_err("%s: VREG L8 enable failed\n", __func__);
333 goto l8_put;
334 }
335
336 vreg_ldo15 = vreg_get(NULL, "gp6");
337
338 if (!vreg_ldo15) {
339 pr_err("%s: VREG L15 get failed\n", __func__);
340 goto l8_disable;
341 }
342
343 rc = vreg_set_level(vreg_ldo15, 3050);
344 if (rc) {
345 pr_err("%s: VREG L15 set failed\n", __func__);
346 goto l8_disable;
347 }
348
349 rc = vreg_enable(vreg_ldo15);
350 if (rc) {
351 pr_err("%s: VREG L15 enable failed\n", __func__);
352 goto l8_disable;
353 }
354
355 /* check this device active by reading first byte/register */
356 rc = i2c_smbus_read_byte_data(client, 0x01);
357 if (rc < 0) {
358 pr_err("%s: i2c sanity check failed\n", __func__);
359 goto l8_disable;
360 }
361
362 rc = gpio_tlmm_config(GPIO_CFG(CYTTSP_TS_GPIO_IRQ, 0, GPIO_CFG_INPUT,
363 GPIO_CFG_PULL_UP, GPIO_CFG_6MA), GPIO_CFG_ENABLE);
364 if (rc) {
365 pr_err("%s: Could not configure gpio %d\n",
366 __func__, CYTTSP_TS_GPIO_IRQ);
367 goto l8_disable;
368 }
369
370 /* virtual keys */
371 tma300_vkeys_attr.attr.name = "virtualkeys.cyttsp-i2c";
372 properties_kobj = kobject_create_and_add("board_properties",
373 NULL);
374 if (properties_kobj)
375 rc = sysfs_create_group(properties_kobj,
376 &tma300_properties_attr_group);
377 if (!properties_kobj || rc)
378 pr_err("%s: failed to create board_properties\n",
379 __func__);
380
381 return CY_OK;
382
383l8_disable:
384 vreg_disable(vreg_ldo8);
385l8_put:
386 vreg_put(vreg_ldo8);
387 return rc;
388}
389
390static int cyttsp_platform_resume(struct i2c_client *client)
391{
392 /* add any special code to strobe a wakeup pin or chip reset */
393 mdelay(10);
394
395 return CY_OK;
396}
397
398static struct cyttsp_platform_data cyttsp_data = {
399 .fw_fname = "cyttsp_7630_fluid.hex",
400 .panel_maxx = 479,
401 .panel_maxy = 799,
402 .disp_maxx = 469,
403 .disp_maxy = 799,
404 .disp_minx = 10,
405 .disp_miny = 0,
406 .flags = 0,
407 .gen = CY_GEN3, /* or */
408 .use_st = CY_USE_ST,
409 .use_mt = CY_USE_MT,
410 .use_hndshk = CY_SEND_HNDSHK,
411 .use_trk_id = CY_USE_TRACKING_ID,
Anirudh Ghayal15187772011-06-22 17:39:41 +0530412 .use_sleep = CY_USE_DEEP_SLEEP_SEL | CY_USE_LOW_POWER_SEL,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700413 .use_gestures = CY_USE_GESTURES,
414 /* activate up to 4 groups
415 * and set active distance
416 */
417 .gest_set = CY_GEST_GRP1 | CY_GEST_GRP2 |
418 CY_GEST_GRP3 | CY_GEST_GRP4 |
419 CY_ACT_DIST,
420 /* change act_intrvl to customize the Active power state
421 * scanning/processing refresh interval for Operating mode
422 */
423 .act_intrvl = CY_ACT_INTRVL_DFLT,
424 /* change tch_tmout to customize the touch timeout for the
425 * Active power state for Operating mode
426 */
427 .tch_tmout = CY_TCH_TMOUT_DFLT,
428 /* change lp_intrvl to customize the Low Power power state
429 * scanning/processing refresh interval for Operating mode
430 */
431 .lp_intrvl = CY_LP_INTRVL_DFLT,
432 .resume = cyttsp_platform_resume,
433 .init = cyttsp_platform_init,
434 .sleep_gpio = -1,
435 .resout_gpio = -1,
436 .irq_gpio = CYTTSP_TS_GPIO_IRQ,
Mohan Pallaka49c37d62011-08-01 11:52:00 +0530437 .correct_fw_ver = 2,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700438};
439
440static int pm8058_pwm_config(struct pwm_device *pwm, int ch, int on)
441{
442 struct pm8058_gpio pwm_gpio_config = {
443 .direction = PM_GPIO_DIR_OUT,
444 .output_buffer = PM_GPIO_OUT_BUF_CMOS,
445 .output_value = 0,
446 .pull = PM_GPIO_PULL_NO,
447 .vin_sel = PM_GPIO_VIN_S3,
448 .out_strength = PM_GPIO_STRENGTH_HIGH,
449 .function = PM_GPIO_FUNC_2,
450 };
451 int rc = -EINVAL;
452 int id, mode, max_mA;
453
454 id = mode = max_mA = 0;
455 switch (ch) {
456 case 0:
457 case 1:
458 case 2:
459 if (on) {
460 id = 24 + ch;
461 rc = pm8058_gpio_config(id - 1, &pwm_gpio_config);
462 if (rc)
463 pr_err("%s: pm8058_gpio_config(%d): rc=%d\n",
464 __func__, id, rc);
465 }
466 break;
467
468 case 3:
469 id = PM_PWM_LED_KPD;
470 mode = PM_PWM_CONF_DTEST3;
471 max_mA = 200;
472 break;
473
474 case 4:
475 id = PM_PWM_LED_0;
476 mode = PM_PWM_CONF_PWM1;
477 max_mA = 40;
478 break;
479
480 case 5:
481 id = PM_PWM_LED_2;
482 mode = PM_PWM_CONF_PWM2;
483 max_mA = 40;
484 break;
485
486 case 6:
487 id = PM_PWM_LED_FLASH;
488 mode = PM_PWM_CONF_DTEST3;
489 max_mA = 200;
490 break;
491
492 default:
493 break;
494 }
495
496 if (ch >= 3 && ch <= 6) {
497 if (!on) {
498 mode = PM_PWM_CONF_NONE;
499 max_mA = 0;
500 }
501 rc = pm8058_pwm_config_led(pwm, id, mode, max_mA);
502 if (rc)
503 pr_err("%s: pm8058_pwm_config_led(ch=%d): rc=%d\n",
504 __func__, ch, rc);
505 }
506
507 return rc;
508}
509
510static int pm8058_pwm_enable(struct pwm_device *pwm, int ch, int on)
511{
512 int rc;
513
514 switch (ch) {
515 case 7:
516 rc = pm8058_pwm_set_dtest(pwm, on);
517 if (rc)
518 pr_err("%s: pwm_set_dtest(%d): rc=%d\n",
519 __func__, on, rc);
520 break;
521 default:
522 rc = -EINVAL;
523 break;
524 }
525 return rc;
526}
527
528static const unsigned int fluid_keymap[] = {
529 KEY(0, 0, KEY_7),
530 KEY(0, 1, KEY_ENTER),
531 KEY(0, 2, KEY_UP),
532 /* drop (0,3) as it always shows up in pair with(0,2) */
533 KEY(0, 4, KEY_DOWN),
534
535 KEY(1, 0, KEY_CAMERA_SNAPSHOT),
536 KEY(1, 1, KEY_SELECT),
537 KEY(1, 2, KEY_1),
538 KEY(1, 3, KEY_VOLUMEUP),
539 KEY(1, 4, KEY_VOLUMEDOWN),
540};
541
542static const unsigned int surf_keymap[] = {
543 KEY(0, 0, KEY_7),
544 KEY(0, 1, KEY_DOWN),
545 KEY(0, 2, KEY_UP),
546 KEY(0, 3, KEY_RIGHT),
547 KEY(0, 4, KEY_ENTER),
548 KEY(0, 5, KEY_L),
549 KEY(0, 6, KEY_BACK),
550 KEY(0, 7, KEY_M),
551
552 KEY(1, 0, KEY_LEFT),
553 KEY(1, 1, KEY_SEND),
554 KEY(1, 2, KEY_1),
555 KEY(1, 3, KEY_4),
556 KEY(1, 4, KEY_CLEAR),
557 KEY(1, 5, KEY_MSDOS),
558 KEY(1, 6, KEY_SPACE),
559 KEY(1, 7, KEY_COMMA),
560
561 KEY(2, 0, KEY_6),
562 KEY(2, 1, KEY_5),
563 KEY(2, 2, KEY_8),
564 KEY(2, 3, KEY_3),
565 KEY(2, 4, KEY_NUMERIC_STAR),
566 KEY(2, 5, KEY_UP),
567 KEY(2, 6, KEY_DOWN), /* SYN */
568 KEY(2, 7, KEY_LEFTSHIFT),
569
570 KEY(3, 0, KEY_9),
571 KEY(3, 1, KEY_NUMERIC_POUND),
572 KEY(3, 2, KEY_0),
573 KEY(3, 3, KEY_2),
574 KEY(3, 4, KEY_SLEEP),
575 KEY(3, 5, KEY_F1),
576 KEY(3, 6, KEY_F2),
577 KEY(3, 7, KEY_F3),
578
579 KEY(4, 0, KEY_BACK),
580 KEY(4, 1, KEY_HOME),
581 KEY(4, 2, KEY_MENU),
582 KEY(4, 3, KEY_VOLUMEUP),
583 KEY(4, 4, KEY_VOLUMEDOWN),
584 KEY(4, 5, KEY_F4),
585 KEY(4, 6, KEY_F5),
586 KEY(4, 7, KEY_F6),
587
588 KEY(5, 0, KEY_R),
589 KEY(5, 1, KEY_T),
590 KEY(5, 2, KEY_Y),
591 KEY(5, 3, KEY_LEFTALT),
592 KEY(5, 4, KEY_KPENTER),
593 KEY(5, 5, KEY_Q),
594 KEY(5, 6, KEY_W),
595 KEY(5, 7, KEY_E),
596
597 KEY(6, 0, KEY_F),
598 KEY(6, 1, KEY_G),
599 KEY(6, 2, KEY_H),
600 KEY(6, 3, KEY_CAPSLOCK),
601 KEY(6, 4, KEY_PAGEUP),
602 KEY(6, 5, KEY_A),
603 KEY(6, 6, KEY_S),
604 KEY(6, 7, KEY_D),
605
606 KEY(7, 0, KEY_V),
607 KEY(7, 1, KEY_B),
608 KEY(7, 2, KEY_N),
609 KEY(7, 3, KEY_MENU), /* REVISIT - SYM */
610 KEY(7, 4, KEY_PAGEDOWN),
611 KEY(7, 5, KEY_Z),
612 KEY(7, 6, KEY_X),
613 KEY(7, 7, KEY_C),
614
615 KEY(8, 0, KEY_P),
616 KEY(8, 1, KEY_J),
617 KEY(8, 2, KEY_K),
618 KEY(8, 3, KEY_INSERT),
619 KEY(8, 4, KEY_LINEFEED),
620 KEY(8, 5, KEY_U),
621 KEY(8, 6, KEY_I),
622 KEY(8, 7, KEY_O),
623
624 KEY(9, 0, KEY_4),
625 KEY(9, 1, KEY_5),
626 KEY(9, 2, KEY_6),
627 KEY(9, 3, KEY_7),
628 KEY(9, 4, KEY_8),
629 KEY(9, 5, KEY_1),
630 KEY(9, 6, KEY_2),
631 KEY(9, 7, KEY_3),
632
633 KEY(10, 0, KEY_F7),
634 KEY(10, 1, KEY_F8),
635 KEY(10, 2, KEY_F9),
636 KEY(10, 3, KEY_F10),
637 KEY(10, 4, KEY_FN),
638 KEY(10, 5, KEY_9),
639 KEY(10, 6, KEY_0),
640 KEY(10, 7, KEY_DOT),
641
642 KEY(11, 0, KEY_LEFTCTRL),
643 KEY(11, 1, KEY_F11), /* START */
644 KEY(11, 2, KEY_ENTER),
645 KEY(11, 3, KEY_SEARCH),
646 KEY(11, 4, KEY_DELETE),
647 KEY(11, 5, KEY_RIGHT),
648 KEY(11, 6, KEY_LEFT),
649 KEY(11, 7, KEY_RIGHTSHIFT),
650};
651
652static struct resource resources_keypad[] = {
653 {
654 .start = PM8058_KEYPAD_IRQ(PMIC8058_IRQ_BASE),
655 .end = PM8058_KEYPAD_IRQ(PMIC8058_IRQ_BASE),
656 .flags = IORESOURCE_IRQ,
Dima Zavinba5499e2011-01-10 11:00:30 -0800657 },
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700658 {
659 .start = PM8058_KEYSTUCK_IRQ(PMIC8058_IRQ_BASE),
660 .end = PM8058_KEYSTUCK_IRQ(PMIC8058_IRQ_BASE),
661 .flags = IORESOURCE_IRQ,
Dima Zavinba5499e2011-01-10 11:00:30 -0800662 },
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700663};
664
665static struct matrix_keymap_data surf_keymap_data = {
666 .keymap_size = ARRAY_SIZE(surf_keymap),
667 .keymap = surf_keymap,
668};
669
670
671static struct pmic8058_keypad_data surf_keypad_data = {
672 .input_name = "surf_keypad",
673 .input_phys_device = "surf_keypad/input0",
674 .num_rows = 12,
675 .num_cols = 8,
676 .rows_gpio_start = 8,
677 .cols_gpio_start = 0,
678 .debounce_ms = {8, 10},
679 .scan_delay_ms = 32,
680 .row_hold_ns = 91500,
681 .wakeup = 1,
682 .keymap_data = &surf_keymap_data,
683};
684
685static struct matrix_keymap_data fluid_keymap_data = {
686 .keymap_size = ARRAY_SIZE(fluid_keymap),
687 .keymap = fluid_keymap,
688};
689
690
691
692static struct pmic8058_keypad_data fluid_keypad_data = {
693 .input_name = "fluid-keypad",
694 .input_phys_device = "fluid-keypad/input0",
695 .num_rows = 5,
696 .num_cols = 5,
697 .rows_gpio_start = 8,
698 .cols_gpio_start = 0,
699 .debounce_ms = {8, 10},
700 .scan_delay_ms = 32,
701 .row_hold_ns = 91500,
702 .wakeup = 1,
703 .keymap_data = &fluid_keymap_data,
704};
705
706static struct pm8058_pwm_pdata pm8058_pwm_data = {
707 .config = pm8058_pwm_config,
708 .enable = pm8058_pwm_enable,
709};
710
711/* Put sub devices with fixed location first in sub_devices array */
712#define PM8058_SUBDEV_KPD 0
713#define PM8058_SUBDEV_LED 1
714
715static struct pm8058_gpio_platform_data pm8058_gpio_data = {
716 .gpio_base = PM8058_GPIO_PM_TO_SYS(0),
717 .irq_base = PM8058_GPIO_IRQ(PMIC8058_IRQ_BASE, 0),
718 .init = pm8058_gpios_init,
719};
720
721static struct pm8058_gpio_platform_data pm8058_mpp_data = {
722 .gpio_base = PM8058_GPIO_PM_TO_SYS(PM8058_GPIOS),
723 .irq_base = PM8058_MPP_IRQ(PMIC8058_IRQ_BASE, 0),
724};
725
726static struct pmic8058_led pmic8058_ffa_leds[] = {
727 [0] = {
728 .name = "keyboard-backlight",
729 .max_brightness = 15,
730 .id = PMIC8058_ID_LED_KB_LIGHT,
Dima Zavinba5499e2011-01-10 11:00:30 -0800731 },
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700732};
733
734static struct pmic8058_leds_platform_data pm8058_ffa_leds_data = {
735 .num_leds = ARRAY_SIZE(pmic8058_ffa_leds),
736 .leds = pmic8058_ffa_leds,
737};
738
739static struct pmic8058_led pmic8058_surf_leds[] = {
740 [0] = {
741 .name = "keyboard-backlight",
742 .max_brightness = 15,
743 .id = PMIC8058_ID_LED_KB_LIGHT,
744 },
745 [1] = {
746 .name = "voice:red",
747 .max_brightness = 20,
748 .id = PMIC8058_ID_LED_0,
749 },
750 [2] = {
751 .name = "wlan:green",
752 .max_brightness = 20,
753 .id = PMIC8058_ID_LED_2,
754 },
755};
756
757static struct mfd_cell pm8058_subdevs[] = {
758 { .name = "pm8058-keypad",
759 .id = -1,
760 .num_resources = ARRAY_SIZE(resources_keypad),
761 .resources = resources_keypad,
762 },
763 { .name = "pm8058-led",
764 .id = -1,
765 },
766 { .name = "pm8058-gpio",
767 .id = -1,
768 .platform_data = &pm8058_gpio_data,
769 .pdata_size = sizeof(pm8058_gpio_data),
770 },
771 { .name = "pm8058-mpp",
772 .id = -1,
773 .platform_data = &pm8058_mpp_data,
774 .pdata_size = sizeof(pm8058_mpp_data),
775 },
776 { .name = "pm8058-pwm",
777 .id = -1,
778 .platform_data = &pm8058_pwm_data,
779 .pdata_size = sizeof(pm8058_pwm_data),
780 },
781 { .name = "pm8058-nfc",
782 .id = -1,
783 },
784 { .name = "pm8058-upl",
785 .id = -1,
786 },
787};
788
789static struct pmic8058_leds_platform_data pm8058_surf_leds_data = {
790 .num_leds = ARRAY_SIZE(pmic8058_surf_leds),
791 .leds = pmic8058_surf_leds,
792};
793
794static struct pmic8058_led pmic8058_fluid_leds[] = {
795 [0] = {
796 .name = "keyboard-backlight",
797 .max_brightness = 15,
798 .id = PMIC8058_ID_LED_KB_LIGHT,
799 },
800 [1] = {
801 .name = "flash:led_0",
802 .max_brightness = 15,
803 .id = PMIC8058_ID_FLASH_LED_0,
804 },
805 [2] = {
806 .name = "flash:led_1",
807 .max_brightness = 15,
808 .id = PMIC8058_ID_FLASH_LED_1,
809 },
810};
811
812static struct pmic8058_leds_platform_data pm8058_fluid_leds_data = {
813 .num_leds = ARRAY_SIZE(pmic8058_fluid_leds),
814 .leds = pmic8058_fluid_leds,
815};
816
817static struct pm8058_platform_data pm8058_7x30_data = {
818 .irq_base = PMIC8058_IRQ_BASE,
819
820 .num_subdevs = ARRAY_SIZE(pm8058_subdevs),
821 .sub_devices = pm8058_subdevs,
822 .irq_trigger_flags = IRQF_TRIGGER_LOW,
823};
824
825static struct i2c_board_info pm8058_boardinfo[] __initdata = {
826 {
827 I2C_BOARD_INFO("pm8058-core", 0x55),
828 .irq = MSM_GPIO_TO_INT(PMIC_GPIO_INT),
829 .platform_data = &pm8058_7x30_data,
830 },
831};
832
833static struct i2c_board_info cy8info[] __initdata = {
834 {
835 I2C_BOARD_INFO(CY_I2C_NAME, 0x24),
836 .platform_data = &cyttsp_data,
837#ifndef CY_USE_TIMER
838 .irq = MSM_GPIO_TO_INT(CYTTSP_TS_GPIO_IRQ),
839#endif /* CY_USE_TIMER */
840 },
841};
842
843static struct i2c_board_info msm_camera_boardinfo[] __initdata = {
844#ifdef CONFIG_MT9D112
845 {
846 I2C_BOARD_INFO("mt9d112", 0x78 >> 1),
Dima Zavinba5499e2011-01-10 11:00:30 -0800847 },
848#endif
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700849#ifdef CONFIG_WEBCAM_OV9726
850 {
851 I2C_BOARD_INFO("ov9726", 0x10),
852 },
853#endif
854#ifdef CONFIG_S5K3E2FX
855 {
856 I2C_BOARD_INFO("s5k3e2fx", 0x20 >> 1),
857 },
858#endif
859#ifdef CONFIG_MT9P012
860 {
861 I2C_BOARD_INFO("mt9p012", 0x6C >> 1),
862 },
863#endif
864#ifdef CONFIG_VX6953
865 {
866 I2C_BOARD_INFO("vx6953", 0x20),
867 },
868#endif
869#ifdef CONFIG_MT9E013
870 {
871 I2C_BOARD_INFO("mt9e013", 0x6C >> 2),
872 },
873#endif
874#ifdef CONFIG_SN12M0PZ
875 {
876 I2C_BOARD_INFO("sn12m0pz", 0x34 >> 1),
877 },
878#endif
879#if defined(CONFIG_MT9T013) || defined(CONFIG_SENSORS_MT9T013)
880 {
881 I2C_BOARD_INFO("mt9t013", 0x6C),
882 },
883#endif
884
Dima Zavinba5499e2011-01-10 11:00:30 -0800885};
886
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700887#ifdef CONFIG_MSM_CAMERA
888#define CAM_STNDBY 143
889static uint32_t camera_off_vcm_gpio_table[] = {
890GPIO_CFG(1, 0, GPIO_CFG_OUTPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA), /* VCM */
891};
892
893static uint32_t camera_off_gpio_table[] = {
894 /* parallel CAMERA interfaces */
895 GPIO_CFG(0, 0, GPIO_CFG_OUTPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA), /* RST */
896 GPIO_CFG(2, 0, GPIO_CFG_INPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA), /* DAT2 */
897 GPIO_CFG(3, 0, GPIO_CFG_INPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA), /* DAT3 */
898 GPIO_CFG(4, 0, GPIO_CFG_INPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA), /* DAT4 */
899 GPIO_CFG(5, 0, GPIO_CFG_INPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA), /* DAT5 */
900 GPIO_CFG(6, 0, GPIO_CFG_INPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA), /* DAT6 */
901 GPIO_CFG(7, 0, GPIO_CFG_INPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA), /* DAT7 */
902 GPIO_CFG(8, 0, GPIO_CFG_INPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA), /* DAT8 */
903 GPIO_CFG(9, 0, GPIO_CFG_INPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA), /* DAT9 */
904 GPIO_CFG(10, 0, GPIO_CFG_INPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA), /* DAT10 */
905 GPIO_CFG(11, 0, GPIO_CFG_INPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA), /* DAT11 */
906 GPIO_CFG(12, 0, GPIO_CFG_INPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA), /* PCLK */
907 GPIO_CFG(13, 0, GPIO_CFG_INPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA), /* HSYNC_IN */
908 GPIO_CFG(14, 0, GPIO_CFG_INPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA), /* VSYNC_IN */
909 GPIO_CFG(15, 0, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), /* MCLK */
910};
911
912static uint32_t camera_on_vcm_gpio_table[] = {
913GPIO_CFG(1, 0, GPIO_CFG_OUTPUT, GPIO_CFG_PULL_UP, GPIO_CFG_2MA), /* VCM */
914};
915
916static uint32_t camera_on_gpio_table[] = {
917 /* parallel CAMERA interfaces */
918 GPIO_CFG(0, 0, GPIO_CFG_OUTPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA), /* RST */
919 GPIO_CFG(2, 1, GPIO_CFG_INPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA), /* DAT2 */
920 GPIO_CFG(3, 1, GPIO_CFG_INPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA), /* DAT3 */
921 GPIO_CFG(4, 1, GPIO_CFG_INPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA), /* DAT4 */
922 GPIO_CFG(5, 1, GPIO_CFG_INPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA), /* DAT5 */
923 GPIO_CFG(6, 1, GPIO_CFG_INPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA), /* DAT6 */
924 GPIO_CFG(7, 1, GPIO_CFG_INPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA), /* DAT7 */
925 GPIO_CFG(8, 1, GPIO_CFG_INPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA), /* DAT8 */
926 GPIO_CFG(9, 1, GPIO_CFG_INPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA), /* DAT9 */
927 GPIO_CFG(10, 1, GPIO_CFG_INPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA), /* DAT10 */
928 GPIO_CFG(11, 1, GPIO_CFG_INPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA), /* DAT11 */
929 GPIO_CFG(12, 1, GPIO_CFG_INPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA), /* PCLK */
930 GPIO_CFG(13, 1, GPIO_CFG_INPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA), /* HSYNC_IN */
931 GPIO_CFG(14, 1, GPIO_CFG_INPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA), /* VSYNC_IN */
932 GPIO_CFG(15, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), /* MCLK */
933};
934
935static uint32_t camera_off_gpio_fluid_table[] = {
936 /* FLUID: CAM_VGA_RST_N */
937 GPIO_CFG(31, 0, GPIO_CFG_OUTPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA),
938 /* FLUID: CAMIF_STANDBY */
939 GPIO_CFG(CAM_STNDBY, 0, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA)
940};
941
942static uint32_t camera_on_gpio_fluid_table[] = {
943 /* FLUID: CAM_VGA_RST_N */
944 GPIO_CFG(31, 0, GPIO_CFG_OUTPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA),
945 /* FLUID: CAMIF_STANDBY */
946 GPIO_CFG(CAM_STNDBY, 0, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA)
947};
948
949static void config_gpio_table(uint32_t *table, int len)
950{
951 int n, rc;
952 for (n = 0; n < len; n++) {
953 rc = gpio_tlmm_config(table[n], GPIO_CFG_ENABLE);
954 if (rc) {
955 pr_err("%s: gpio_tlmm_config(%#x)=%d\n",
956 __func__, table[n], rc);
957 break;
958 }
959 }
960}
961static int config_camera_on_gpios(void)
962{
963 config_gpio_table(camera_on_gpio_table,
964 ARRAY_SIZE(camera_on_gpio_table));
965
966 if (adie_get_detected_codec_type() != TIMPANI_ID)
967 /* GPIO1 is shared also used in Timpani RF card so
968 only configure it for non-Timpani RF card */
969 config_gpio_table(camera_on_vcm_gpio_table,
970 ARRAY_SIZE(camera_on_vcm_gpio_table));
971
972 if (machine_is_msm7x30_fluid()) {
973 config_gpio_table(camera_on_gpio_fluid_table,
974 ARRAY_SIZE(camera_on_gpio_fluid_table));
975 /* FLUID: turn on 5V booster */
976 gpio_set_value(
977 PM8058_GPIO_PM_TO_SYS(PMIC_GPIO_FLASH_BOOST_ENABLE), 1);
978 /* FLUID: drive high to put secondary sensor to STANDBY */
979 gpio_set_value(CAM_STNDBY, 1);
980 }
981 return 0;
982}
983
984static void config_camera_off_gpios(void)
985{
986 config_gpio_table(camera_off_gpio_table,
987 ARRAY_SIZE(camera_off_gpio_table));
988
989 if (adie_get_detected_codec_type() != TIMPANI_ID)
990 /* GPIO1 is shared also used in Timpani RF card so
991 only configure it for non-Timpani RF card */
992 config_gpio_table(camera_off_vcm_gpio_table,
993 ARRAY_SIZE(camera_off_vcm_gpio_table));
994
995 if (machine_is_msm7x30_fluid()) {
996 config_gpio_table(camera_off_gpio_fluid_table,
997 ARRAY_SIZE(camera_off_gpio_fluid_table));
998 /* FLUID: turn off 5V booster */
999 gpio_set_value(
1000 PM8058_GPIO_PM_TO_SYS(PMIC_GPIO_FLASH_BOOST_ENABLE), 0);
1001 }
1002}
1003
1004struct resource msm_camera_resources[] = {
1005 {
1006 .start = 0xA6000000,
1007 .end = 0xA6000000 + SZ_1M - 1,
1008 .flags = IORESOURCE_MEM,
1009 },
1010 {
1011 .start = INT_VFE,
1012 .end = INT_VFE,
1013 .flags = IORESOURCE_IRQ,
1014 },
1015 {
1016 .flags = IORESOURCE_DMA,
1017 }
1018};
1019
1020struct msm_camera_device_platform_data msm_camera_device_data = {
1021 .camera_gpio_on = config_camera_on_gpios,
1022 .camera_gpio_off = config_camera_off_gpios,
1023 .ioext.camifpadphy = 0xAB000000,
1024 .ioext.camifpadsz = 0x00000400,
1025 .ioext.csiphy = 0xA6100000,
1026 .ioext.csisz = 0x00000400,
1027 .ioext.csiirq = INT_CSI,
1028 .ioclk.mclk_clk_rate = 24000000,
1029 .ioclk.vfe_clk_rate = 147456000,
1030};
1031
1032static struct msm_camera_sensor_flash_src msm_flash_src_pwm = {
1033 .flash_sr_type = MSM_CAMERA_FLASH_SRC_PWM,
1034 ._fsrc.pwm_src.freq = 1000,
1035 ._fsrc.pwm_src.max_load = 300,
1036 ._fsrc.pwm_src.low_load = 30,
1037 ._fsrc.pwm_src.high_load = 100,
1038 ._fsrc.pwm_src.channel = 7,
1039};
1040
1041#ifdef CONFIG_MT9D112
1042static struct msm_camera_sensor_flash_data flash_mt9d112 = {
1043 .flash_type = MSM_CAMERA_FLASH_LED,
1044 .flash_src = &msm_flash_src_pwm
1045};
1046
1047static struct msm_camera_sensor_info msm_camera_sensor_mt9d112_data = {
1048 .sensor_name = "mt9d112",
1049 .sensor_reset = 0,
1050 .sensor_pwd = 85,
1051 .vcm_pwd = 1,
1052 .vcm_enable = 0,
1053 .pdata = &msm_camera_device_data,
1054 .resource = msm_camera_resources,
1055 .num_resources = ARRAY_SIZE(msm_camera_resources),
1056 .flash_data = &flash_mt9d112,
1057 .csi_if = 0
1058};
1059
1060static struct platform_device msm_camera_sensor_mt9d112 = {
1061 .name = "msm_camera_mt9d112",
1062 .dev = {
1063 .platform_data = &msm_camera_sensor_mt9d112_data,
1064 },
1065};
1066#endif
1067
1068#ifdef CONFIG_WEBCAM_OV9726
1069
1070static struct msm_camera_sensor_platform_info ov9726_sensor_7630_info = {
1071 .mount_angle = 90
1072};
1073
1074static struct msm_camera_sensor_flash_data flash_ov9726 = {
1075 .flash_type = MSM_CAMERA_FLASH_LED,
1076 .flash_src = &msm_flash_src_pwm
1077};
1078static struct msm_camera_sensor_info msm_camera_sensor_ov9726_data = {
1079 .sensor_name = "ov9726",
1080 .sensor_reset = 0,
1081 .sensor_pwd = 85,
1082 .vcm_pwd = 1,
1083 .vcm_enable = 0,
1084 .pdata = &msm_camera_device_data,
1085 .resource = msm_camera_resources,
1086 .num_resources = ARRAY_SIZE(msm_camera_resources),
1087 .flash_data = &flash_ov9726,
1088 .sensor_platform_info = &ov9726_sensor_7630_info,
1089 .csi_if = 1
1090};
1091struct platform_device msm_camera_sensor_ov9726 = {
1092 .name = "msm_camera_ov9726",
1093 .dev = {
1094 .platform_data = &msm_camera_sensor_ov9726_data,
1095 },
1096};
1097#endif
1098
1099#ifdef CONFIG_S5K3E2FX
1100static struct msm_camera_sensor_flash_data flash_s5k3e2fx = {
1101 .flash_type = MSM_CAMERA_FLASH_LED,
1102 .flash_src = &msm_flash_src_pwm,
1103};
1104
1105static struct msm_camera_sensor_info msm_camera_sensor_s5k3e2fx_data = {
1106 .sensor_name = "s5k3e2fx",
1107 .sensor_reset = 0,
1108 .sensor_pwd = 85,
1109 .vcm_pwd = 1,
1110 .vcm_enable = 0,
1111 .pdata = &msm_camera_device_data,
1112 .resource = msm_camera_resources,
1113 .num_resources = ARRAY_SIZE(msm_camera_resources),
1114 .flash_data = &flash_s5k3e2fx,
1115 .csi_if = 0
1116};
1117
1118static struct platform_device msm_camera_sensor_s5k3e2fx = {
1119 .name = "msm_camera_s5k3e2fx",
1120 .dev = {
1121 .platform_data = &msm_camera_sensor_s5k3e2fx_data,
1122 },
1123};
1124#endif
1125
1126#ifdef CONFIG_MT9P012
1127static struct msm_camera_sensor_flash_data flash_mt9p012 = {
1128 .flash_type = MSM_CAMERA_FLASH_LED,
1129 .flash_src = &msm_flash_src_pwm
1130};
1131
1132static struct msm_camera_sensor_info msm_camera_sensor_mt9p012_data = {
1133 .sensor_name = "mt9p012",
1134 .sensor_reset = 0,
1135 .sensor_pwd = 85,
1136 .vcm_pwd = 1,
1137 .vcm_enable = 1,
1138 .pdata = &msm_camera_device_data,
1139 .resource = msm_camera_resources,
1140 .num_resources = ARRAY_SIZE(msm_camera_resources),
1141 .flash_data = &flash_mt9p012,
1142 .csi_if = 0
1143};
1144
1145static struct platform_device msm_camera_sensor_mt9p012 = {
1146 .name = "msm_camera_mt9p012",
1147 .dev = {
1148 .platform_data = &msm_camera_sensor_mt9p012_data,
1149 },
1150};
1151#endif
1152
1153#ifdef CONFIG_MT9E013
1154static struct msm_camera_sensor_platform_info mt9e013_sensor_7630_info = {
1155 .mount_angle = 0
1156};
1157
1158static struct msm_camera_sensor_flash_data flash_mt9e013 = {
1159 .flash_type = MSM_CAMERA_FLASH_LED,
1160 .flash_src = &msm_flash_src_pwm
1161};
1162
1163static struct msm_camera_sensor_info msm_camera_sensor_mt9e013_data = {
1164 .sensor_name = "mt9e013",
1165 .sensor_reset = 0,
1166 .sensor_pwd = 85,
1167 .vcm_pwd = 1,
1168 .vcm_enable = 1,
1169 .pdata = &msm_camera_device_data,
1170 .resource = msm_camera_resources,
1171 .num_resources = ARRAY_SIZE(msm_camera_resources),
1172 .flash_data = &flash_mt9e013,
1173 .sensor_platform_info = &mt9e013_sensor_7630_info,
1174 .csi_if = 1
1175};
1176
1177static struct platform_device msm_camera_sensor_mt9e013 = {
1178 .name = "msm_camera_mt9e013",
1179 .dev = {
1180 .platform_data = &msm_camera_sensor_mt9e013_data,
1181 },
1182};
1183#endif
1184
1185#ifdef CONFIG_VX6953
Jilai Wang971f97f2011-07-13 14:25:25 -04001186static struct msm_camera_sensor_platform_info vx6953_sensor_7630_info = {
1187 .mount_angle = 0
1188};
1189
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001190static struct msm_camera_sensor_flash_data flash_vx6953 = {
1191 .flash_type = MSM_CAMERA_FLASH_LED,
1192 .flash_src = &msm_flash_src_pwm
1193};
1194static struct msm_camera_sensor_info msm_camera_sensor_vx6953_data = {
1195 .sensor_name = "vx6953",
1196 .sensor_reset = 0,
1197 .sensor_pwd = 85,
1198 .vcm_pwd = 1,
1199 .vcm_enable = 0,
1200 .pdata = &msm_camera_device_data,
1201 .resource = msm_camera_resources,
1202 .num_resources = ARRAY_SIZE(msm_camera_resources),
Jilai Wang971f97f2011-07-13 14:25:25 -04001203 .sensor_platform_info = &vx6953_sensor_7630_info,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001204 .flash_data = &flash_vx6953,
1205 .csi_if = 1
1206};
1207static struct platform_device msm_camera_sensor_vx6953 = {
1208 .name = "msm_camera_vx6953",
1209 .dev = {
1210 .platform_data = &msm_camera_sensor_vx6953_data,
1211 },
1212};
1213#endif
1214
1215#ifdef CONFIG_SN12M0PZ
1216static struct msm_camera_sensor_flash_src msm_flash_src_current_driver = {
1217 .flash_sr_type = MSM_CAMERA_FLASH_SRC_CURRENT_DRIVER,
1218 ._fsrc.current_driver_src.low_current = 210,
1219 ._fsrc.current_driver_src.high_current = 700,
1220 ._fsrc.current_driver_src.driver_channel = &pm8058_fluid_leds_data,
1221};
1222
1223static struct msm_camera_sensor_flash_data flash_sn12m0pz = {
1224 .flash_type = MSM_CAMERA_FLASH_LED,
1225 .flash_src = &msm_flash_src_current_driver
1226};
1227static struct msm_camera_sensor_info msm_camera_sensor_sn12m0pz_data = {
1228 .sensor_name = "sn12m0pz",
1229 .sensor_reset = 0,
1230 .sensor_pwd = 85,
1231 .vcm_pwd = 1,
1232 .vcm_enable = 1,
1233 .pdata = &msm_camera_device_data,
1234 .flash_data = &flash_sn12m0pz,
1235 .resource = msm_camera_resources,
1236 .num_resources = ARRAY_SIZE(msm_camera_resources),
1237 .csi_if = 0
1238};
1239
1240static struct platform_device msm_camera_sensor_sn12m0pz = {
1241 .name = "msm_camera_sn12m0pz",
1242 .dev = {
1243 .platform_data = &msm_camera_sensor_sn12m0pz_data,
1244 },
1245};
1246#endif
1247
1248#ifdef CONFIG_MT9T013
1249static struct msm_camera_sensor_flash_data flash_mt9t013 = {
1250 .flash_type = MSM_CAMERA_FLASH_LED,
1251 .flash_src = &msm_flash_src_pwm
1252};
1253
1254static struct msm_camera_sensor_info msm_camera_sensor_mt9t013_data = {
1255 .sensor_name = "mt9t013",
1256 .sensor_reset = 0,
1257 .sensor_pwd = 85,
1258 .vcm_pwd = 1,
1259 .vcm_enable = 0,
1260 .pdata = &msm_camera_device_data,
1261 .resource = msm_camera_resources,
1262 .num_resources = ARRAY_SIZE(msm_camera_resources),
1263 .flash_data = &flash_mt9t013,
1264 .csi_if = 1
1265};
1266
1267static struct platform_device msm_camera_sensor_mt9t013 = {
1268 .name = "msm_camera_mt9t013",
1269 .dev = {
1270 .platform_data = &msm_camera_sensor_mt9t013_data,
1271 },
1272};
1273#endif
1274
1275#ifdef CONFIG_MSM_GEMINI
1276static struct resource msm_gemini_resources[] = {
1277 {
1278 .start = 0xA3A00000,
1279 .end = 0xA3A00000 + 0x0150 - 1,
1280 .flags = IORESOURCE_MEM,
1281 },
1282 {
1283 .start = INT_JPEG,
1284 .end = INT_JPEG,
1285 .flags = IORESOURCE_IRQ,
1286 },
1287};
1288
1289static struct platform_device msm_gemini_device = {
1290 .name = "msm_gemini",
1291 .resource = msm_gemini_resources,
1292 .num_resources = ARRAY_SIZE(msm_gemini_resources),
1293};
1294#endif
1295
1296#ifdef CONFIG_MSM_VPE
1297static struct resource msm_vpe_resources[] = {
1298 {
1299 .start = 0xAD200000,
1300 .end = 0xAD200000 + SZ_1M - 1,
1301 .flags = IORESOURCE_MEM,
1302 },
1303 {
1304 .start = INT_VPE,
1305 .end = INT_VPE,
1306 .flags = IORESOURCE_IRQ,
1307 },
1308};
1309
1310static struct platform_device msm_vpe_device = {
1311 .name = "msm_vpe",
1312 .id = 0,
1313 .num_resources = ARRAY_SIZE(msm_vpe_resources),
1314 .resource = msm_vpe_resources,
1315};
1316#endif
1317
1318#endif /*CONFIG_MSM_CAMERA*/
1319
1320#ifdef CONFIG_MSM7KV2_AUDIO
1321static uint32_t audio_pamp_gpio_config =
1322 GPIO_CFG(82, 0, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA);
1323
1324static uint32_t audio_fluid_icodec_tx_config =
1325 GPIO_CFG(85, 0, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA);
1326
1327static int __init snddev_poweramp_gpio_init(void)
1328{
1329 int rc;
1330
1331 pr_info("snddev_poweramp_gpio_init \n");
1332 rc = gpio_tlmm_config(audio_pamp_gpio_config, GPIO_CFG_ENABLE);
1333 if (rc) {
1334 printk(KERN_ERR
1335 "%s: gpio_tlmm_config(%#x)=%d\n",
1336 __func__, audio_pamp_gpio_config, rc);
1337 }
1338 return rc;
1339}
1340
1341void msm_snddev_tx_route_config(void)
1342{
1343 int rc;
1344
1345 pr_debug("%s()\n", __func__);
1346
1347 if (machine_is_msm7x30_fluid()) {
1348 rc = gpio_tlmm_config(audio_fluid_icodec_tx_config,
1349 GPIO_CFG_ENABLE);
1350 if (rc) {
1351 printk(KERN_ERR
1352 "%s: gpio_tlmm_config(%#x)=%d\n",
1353 __func__, audio_fluid_icodec_tx_config, rc);
1354 } else
1355 gpio_set_value(85, 0);
1356 }
1357}
1358
1359void msm_snddev_tx_route_deconfig(void)
1360{
1361 int rc;
1362
1363 pr_debug("%s()\n", __func__);
1364
1365 if (machine_is_msm7x30_fluid()) {
1366 rc = gpio_tlmm_config(audio_fluid_icodec_tx_config,
1367 GPIO_CFG_DISABLE);
1368 if (rc) {
1369 printk(KERN_ERR
1370 "%s: gpio_tlmm_config(%#x)=%d\n",
1371 __func__, audio_fluid_icodec_tx_config, rc);
1372 }
1373 }
1374}
1375
1376void msm_snddev_poweramp_on(void)
1377{
1378 gpio_set_value(82, 1); /* enable spkr poweramp */
1379 pr_info("%s: power on amplifier\n", __func__);
1380}
1381
1382void msm_snddev_poweramp_off(void)
1383{
1384 gpio_set_value(82, 0); /* disable spkr poweramp */
1385 pr_info("%s: power off amplifier\n", __func__);
1386}
1387
1388static struct vreg *snddev_vreg_ncp, *snddev_vreg_gp4;
1389
1390void msm_snddev_hsed_voltage_on(void)
1391{
1392 int rc;
1393
1394 snddev_vreg_gp4 = vreg_get(NULL, "gp4");
1395 if (IS_ERR(snddev_vreg_gp4)) {
1396 pr_err("%s: vreg_get(%s) failed (%ld)\n",
1397 __func__, "gp4", PTR_ERR(snddev_vreg_gp4));
1398 return;
1399 }
1400 rc = vreg_enable(snddev_vreg_gp4);
1401 if (rc)
1402 pr_err("%s: vreg_enable(gp4) failed (%d)\n", __func__, rc);
1403
1404 snddev_vreg_ncp = vreg_get(NULL, "ncp");
1405 if (IS_ERR(snddev_vreg_ncp)) {
1406 pr_err("%s: vreg_get(%s) failed (%ld)\n",
1407 __func__, "ncp", PTR_ERR(snddev_vreg_ncp));
1408 return;
1409 }
1410 rc = vreg_enable(snddev_vreg_ncp);
1411 if (rc)
1412 pr_err("%s: vreg_enable(ncp) failed (%d)\n", __func__, rc);
1413}
1414
1415void msm_snddev_hsed_voltage_off(void)
1416{
1417 int rc;
1418
1419 if (IS_ERR(snddev_vreg_ncp)) {
1420 pr_err("%s: vreg_get(%s) failed (%ld)\n",
1421 __func__, "ncp", PTR_ERR(snddev_vreg_ncp));
1422 return;
1423 }
1424 rc = vreg_disable(snddev_vreg_ncp);
1425 if (rc)
1426 pr_err("%s: vreg_disable(ncp) failed (%d)\n", __func__, rc);
1427 vreg_put(snddev_vreg_ncp);
1428
1429 if (IS_ERR(snddev_vreg_gp4)) {
1430 pr_err("%s: vreg_get(%s) failed (%ld)\n",
1431 __func__, "gp4", PTR_ERR(snddev_vreg_gp4));
1432 return;
1433 }
1434 rc = vreg_disable(snddev_vreg_gp4);
1435 if (rc)
1436 pr_err("%s: vreg_disable(gp4) failed (%d)\n", __func__, rc);
1437
1438 vreg_put(snddev_vreg_gp4);
1439
1440}
1441
1442static unsigned aux_pcm_gpio_on[] = {
1443 GPIO_CFG(138, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), /* PCM_DOUT */
1444 GPIO_CFG(139, 1, GPIO_CFG_INPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), /* PCM_DIN */
1445 GPIO_CFG(140, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), /* PCM_SYNC */
1446 GPIO_CFG(141, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), /* PCM_CLK */
1447};
1448
1449static int __init aux_pcm_gpio_init(void)
1450{
1451 int pin, rc;
1452
1453 pr_info("aux_pcm_gpio_init \n");
1454 for (pin = 0; pin < ARRAY_SIZE(aux_pcm_gpio_on); pin++) {
1455 rc = gpio_tlmm_config(aux_pcm_gpio_on[pin],
1456 GPIO_CFG_ENABLE);
1457 if (rc) {
1458 printk(KERN_ERR
1459 "%s: gpio_tlmm_config(%#x)=%d\n",
1460 __func__, aux_pcm_gpio_on[pin], rc);
1461 }
1462 }
1463 return rc;
1464}
1465
1466static struct msm_gpio mi2s_clk_gpios[] = {
1467 { GPIO_CFG(145, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA),
1468 "MI2S_SCLK"},
1469 { GPIO_CFG(144, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA),
1470 "MI2S_WS"},
1471 { GPIO_CFG(120, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA),
1472 "MI2S_MCLK_A"},
1473};
1474
1475static struct msm_gpio mi2s_rx_data_lines_gpios[] = {
1476 { GPIO_CFG(121, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA),
1477 "MI2S_DATA_SD0_A"},
1478 { GPIO_CFG(122, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA),
1479 "MI2S_DATA_SD1_A"},
1480 { GPIO_CFG(123, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA),
1481 "MI2S_DATA_SD2_A"},
1482 { GPIO_CFG(146, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA),
1483 "MI2S_DATA_SD3"},
1484};
1485
1486static struct msm_gpio mi2s_tx_data_lines_gpios[] = {
1487 { GPIO_CFG(146, 1, GPIO_CFG_INPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA),
1488 "MI2S_DATA_SD3"},
1489};
1490
1491int mi2s_config_clk_gpio(void)
1492{
1493 int rc = 0;
1494
1495 rc = msm_gpios_request_enable(mi2s_clk_gpios,
1496 ARRAY_SIZE(mi2s_clk_gpios));
1497 if (rc) {
1498 pr_err("%s: enable mi2s clk gpios failed\n",
1499 __func__);
1500 return rc;
1501 }
1502 return 0;
1503}
1504
1505int mi2s_unconfig_data_gpio(u32 direction, u8 sd_line_mask)
1506{
1507 int i, rc = 0;
1508 sd_line_mask &= MI2S_SD_LINE_MASK;
1509
1510 switch (direction) {
1511 case DIR_TX:
1512 msm_gpios_disable_free(mi2s_tx_data_lines_gpios, 1);
1513 break;
1514 case DIR_RX:
1515 i = 0;
1516 while (sd_line_mask) {
1517 if (sd_line_mask & 0x1)
1518 msm_gpios_disable_free(
1519 mi2s_rx_data_lines_gpios + i , 1);
1520 sd_line_mask = sd_line_mask >> 1;
1521 i++;
1522 }
1523 break;
1524 default:
1525 pr_err("%s: Invaild direction direction = %u\n",
1526 __func__, direction);
1527 rc = -EINVAL;
1528 break;
1529 }
1530 return rc;
1531}
1532
1533int mi2s_config_data_gpio(u32 direction, u8 sd_line_mask)
1534{
1535 int i , rc = 0;
1536 u8 sd_config_done_mask = 0;
1537
1538 sd_line_mask &= MI2S_SD_LINE_MASK;
1539
1540 switch (direction) {
1541 case DIR_TX:
1542 if ((sd_line_mask & MI2S_SD_0) || (sd_line_mask & MI2S_SD_1) ||
1543 (sd_line_mask & MI2S_SD_2) || !(sd_line_mask & MI2S_SD_3)) {
1544 pr_err("%s: can not use SD0 or SD1 or SD2 for TX"
1545 ".only can use SD3. sd_line_mask = 0x%x\n",
1546 __func__ , sd_line_mask);
1547 rc = -EINVAL;
1548 } else {
1549 rc = msm_gpios_request_enable(mi2s_tx_data_lines_gpios,
1550 1);
1551 if (rc)
1552 pr_err("%s: enable mi2s gpios for TX failed\n",
1553 __func__);
1554 }
1555 break;
1556 case DIR_RX:
1557 i = 0;
1558 while (sd_line_mask && (rc == 0)) {
1559 if (sd_line_mask & 0x1) {
1560 rc = msm_gpios_request_enable(
1561 mi2s_rx_data_lines_gpios + i , 1);
1562 if (rc) {
1563 pr_err("%s: enable mi2s gpios for"
1564 "RX failed. SD line = %s\n",
1565 __func__,
1566 (mi2s_rx_data_lines_gpios + i)->label);
1567 mi2s_unconfig_data_gpio(DIR_RX,
1568 sd_config_done_mask);
1569 } else
1570 sd_config_done_mask |= (1 << i);
1571 }
1572 sd_line_mask = sd_line_mask >> 1;
1573 i++;
1574 }
1575 break;
1576 default:
1577 pr_err("%s: Invaild direction direction = %u\n",
1578 __func__, direction);
1579 rc = -EINVAL;
1580 break;
1581 }
1582 return rc;
1583}
1584
1585int mi2s_unconfig_clk_gpio(void)
1586{
1587 msm_gpios_disable_free(mi2s_clk_gpios, ARRAY_SIZE(mi2s_clk_gpios));
1588 return 0;
1589}
1590
1591#endif /* CONFIG_MSM7KV2_AUDIO */
1592
1593static int __init buses_init(void)
1594{
1595 if (gpio_tlmm_config(GPIO_CFG(PMIC_GPIO_INT, 1, GPIO_CFG_INPUT,
1596 GPIO_CFG_NO_PULL, GPIO_CFG_2MA), GPIO_CFG_ENABLE))
1597 pr_err("%s: gpio_tlmm_config (gpio=%d) failed\n",
1598 __func__, PMIC_GPIO_INT);
1599
1600 if (machine_is_msm7x30_fluid()) {
1601 pm8058_7x30_data.sub_devices[PM8058_SUBDEV_KPD].platform_data
1602 = &fluid_keypad_data;
1603 } else {
1604 pm8058_7x30_data.sub_devices[PM8058_SUBDEV_KPD].platform_data
1605 = &surf_keypad_data;
1606 pm8058_7x30_data.sub_devices[PM8058_SUBDEV_KPD].pdata_size
1607 = sizeof(surf_keypad_data);
1608 }
1609
1610 i2c_register_board_info(6 /* I2C_SSBI ID */, pm8058_boardinfo,
1611 ARRAY_SIZE(pm8058_boardinfo));
1612
1613 return 0;
1614}
1615
1616#define TIMPANI_RESET_GPIO 1
1617
1618struct bahama_config_register{
1619 u8 reg;
1620 u8 value;
1621 u8 mask;
1622};
1623
1624enum version{
1625 VER_1_0,
1626 VER_2_0,
1627 VER_UNSUPPORTED = 0xFF
1628};
1629
1630
1631static struct vreg *vreg_marimba_1;
1632static struct vreg *vreg_marimba_2;
1633static struct vreg *vreg_marimba_3;
1634
1635static struct msm_gpio timpani_reset_gpio_cfg[] = {
1636{ GPIO_CFG(TIMPANI_RESET_GPIO, 0, GPIO_CFG_OUTPUT,
1637 GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "timpani_reset"} };
1638
1639static u8 read_bahama_ver(void)
1640{
1641 int rc;
1642 struct marimba config = { .mod_id = SLAVE_ID_BAHAMA };
1643 u8 bahama_version;
1644
1645 rc = marimba_read_bit_mask(&config, 0x00, &bahama_version, 1, 0x1F);
1646 if (rc < 0) {
1647 printk(KERN_ERR
1648 "%s: version read failed: %d\n",
1649 __func__, rc);
1650 return rc;
1651 } else {
1652 printk(KERN_INFO
1653 "%s: version read got: 0x%x\n",
1654 __func__, bahama_version);
1655 }
1656
1657 switch (bahama_version) {
1658 case 0x08: /* varient of bahama v1 */
1659 case 0x10:
1660 case 0x00:
1661 return VER_1_0;
1662 case 0x09: /* variant of bahama v2 */
1663 return VER_2_0;
1664 default:
1665 return VER_UNSUPPORTED;
1666 }
1667}
1668
1669static int config_timpani_reset(void)
1670{
1671 int rc;
1672
1673 rc = msm_gpios_request_enable(timpani_reset_gpio_cfg,
1674 ARRAY_SIZE(timpani_reset_gpio_cfg));
1675 if (rc < 0) {
1676 printk(KERN_ERR
1677 "%s: msm_gpios_request_enable failed (%d)\n",
1678 __func__, rc);
1679 }
1680 return rc;
1681}
1682
1683static unsigned int msm_timpani_setup_power(void)
1684{
1685 int rc;
1686
1687 rc = config_timpani_reset();
1688 if (rc < 0)
1689 goto out;
1690
1691 rc = vreg_enable(vreg_marimba_1);
1692 if (rc) {
1693 printk(KERN_ERR "%s: vreg_enable() = %d\n",
1694 __func__, rc);
1695 goto out;
1696 }
1697 rc = vreg_enable(vreg_marimba_2);
1698 if (rc) {
1699 printk(KERN_ERR "%s: vreg_enable() = %d\n",
1700 __func__, rc);
1701 goto fail_disable_vreg_marimba_1;
1702 }
1703
1704 rc = gpio_direction_output(TIMPANI_RESET_GPIO, 1);
1705 if (rc < 0) {
1706 printk(KERN_ERR
1707 "%s: gpio_direction_output failed (%d)\n",
1708 __func__, rc);
1709 msm_gpios_free(timpani_reset_gpio_cfg,
1710 ARRAY_SIZE(timpani_reset_gpio_cfg));
1711 vreg_disable(vreg_marimba_2);
1712 } else
1713 goto out;
1714
1715
1716fail_disable_vreg_marimba_1:
1717 vreg_disable(vreg_marimba_1);
1718
1719out:
1720 return rc;
1721};
1722
1723static void msm_timpani_shutdown_power(void)
1724{
1725 int rc;
1726
1727 rc = vreg_disable(vreg_marimba_1);
1728 if (rc) {
1729 printk(KERN_ERR "%s: return val: %d\n",
1730 __func__, rc);
1731 }
1732 rc = vreg_disable(vreg_marimba_2);
1733 if (rc) {
1734 printk(KERN_ERR "%s: return val: %d\n",
1735 __func__, rc);
1736 }
1737
1738 rc = gpio_direction_output(TIMPANI_RESET_GPIO, 0);
1739 if (rc < 0) {
1740 printk(KERN_ERR
1741 "%s: gpio_direction_output failed (%d)\n",
1742 __func__, rc);
1743 }
1744
1745 msm_gpios_free(timpani_reset_gpio_cfg,
1746 ARRAY_SIZE(timpani_reset_gpio_cfg));
1747};
1748
1749static unsigned int msm_bahama_core_config(int type)
1750{
1751 int rc = 0;
1752
1753 if (type == BAHAMA_ID) {
1754
1755 int i;
1756 struct marimba config = { .mod_id = SLAVE_ID_BAHAMA };
1757
1758 const struct bahama_config_register v20_init[] = {
1759 /* reg, value, mask */
1760 { 0xF4, 0x84, 0xFF }, /* AREG */
1761 { 0xF0, 0x04, 0xFF } /* DREG */
1762 };
1763
1764 if (read_bahama_ver() == VER_2_0) {
1765 for (i = 0; i < ARRAY_SIZE(v20_init); i++) {
1766 u8 value = v20_init[i].value;
1767 rc = marimba_write_bit_mask(&config,
1768 v20_init[i].reg,
1769 &value,
1770 sizeof(v20_init[i].value),
1771 v20_init[i].mask);
1772 if (rc < 0) {
1773 printk(KERN_ERR
1774 "%s: reg %d write failed: %d\n",
1775 __func__, v20_init[i].reg, rc);
1776 return rc;
1777 }
1778 printk(KERN_INFO "%s: reg 0x%02x value 0x%02x"
1779 " mask 0x%02x\n",
1780 __func__, v20_init[i].reg,
1781 v20_init[i].value, v20_init[i].mask);
1782 }
1783 }
1784 }
1785 printk(KERN_INFO "core type: %d\n", type);
1786
1787 return rc;
1788}
1789
1790static unsigned int msm_bahama_setup_power(void)
1791{
1792 int rc;
1793
1794 rc = vreg_enable(vreg_marimba_3);
1795 if (rc) {
1796 printk(KERN_ERR "%s: vreg_enable() = %d\n",
1797 __func__, rc);
1798 }
1799
1800 return rc;
1801};
1802
1803static unsigned int msm_bahama_shutdown_power(int value)
1804{
1805 int rc = 0;
1806
1807 if (value != BAHAMA_ID) {
1808 rc = vreg_disable(vreg_marimba_3);
1809 if (rc) {
1810 printk(KERN_ERR "%s: return val: %d\n",
1811 __func__, rc);
1812 }
1813 }
1814
1815 return rc;
1816};
1817
1818static struct msm_gpio marimba_svlte_config_clock[] = {
1819 { GPIO_CFG(34, 0, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA),
1820 "MARIMBA_SVLTE_CLOCK_ENABLE" },
1821};
1822
1823static unsigned int msm_marimba_gpio_config_svlte(int gpio_cfg_marimba)
1824{
1825 if (machine_is_msm8x55_svlte_surf() ||
1826 machine_is_msm8x55_svlte_ffa()) {
1827 if (gpio_cfg_marimba)
1828 gpio_set_value(GPIO_PIN
1829 (marimba_svlte_config_clock->gpio_cfg), 1);
1830 else
1831 gpio_set_value(GPIO_PIN
1832 (marimba_svlte_config_clock->gpio_cfg), 0);
1833 }
1834
1835 return 0;
1836};
1837
1838static unsigned int msm_marimba_setup_power(void)
1839{
1840 int rc;
1841
1842 rc = vreg_enable(vreg_marimba_1);
1843 if (rc) {
1844 printk(KERN_ERR "%s: vreg_enable() = %d \n",
1845 __func__, rc);
1846 goto out;
1847 }
1848 rc = vreg_enable(vreg_marimba_2);
1849 if (rc) {
1850 printk(KERN_ERR "%s: vreg_enable() = %d \n",
1851 __func__, rc);
1852 goto out;
1853 }
1854
1855 if (machine_is_msm8x55_svlte_surf() || machine_is_msm8x55_svlte_ffa()) {
1856 rc = msm_gpios_request_enable(marimba_svlte_config_clock,
1857 ARRAY_SIZE(marimba_svlte_config_clock));
1858 if (rc < 0) {
1859 printk(KERN_ERR
1860 "%s: msm_gpios_request_enable failed (%d)\n",
1861 __func__, rc);
1862 return rc;
1863 }
1864
1865 rc = gpio_direction_output(GPIO_PIN
1866 (marimba_svlte_config_clock->gpio_cfg), 0);
1867 if (rc < 0) {
1868 printk(KERN_ERR
1869 "%s: gpio_direction_output failed (%d)\n",
1870 __func__, rc);
1871 return rc;
1872 }
1873 }
1874
1875out:
1876 return rc;
1877};
1878
1879static void msm_marimba_shutdown_power(void)
1880{
1881 int rc;
1882
1883 rc = vreg_disable(vreg_marimba_1);
1884 if (rc) {
1885 printk(KERN_ERR "%s: return val: %d\n",
1886 __func__, rc);
1887 }
1888 rc = vreg_disable(vreg_marimba_2);
1889 if (rc) {
1890 printk(KERN_ERR "%s: return val: %d \n",
1891 __func__, rc);
1892 }
1893};
1894
1895static int bahama_present(void)
1896{
1897 int id;
1898 switch (id = adie_get_detected_connectivity_type()) {
1899 case BAHAMA_ID:
1900 return 1;
1901
1902 case MARIMBA_ID:
1903 return 0;
1904
1905 case TIMPANI_ID:
1906 default:
1907 printk(KERN_ERR "%s: unexpected adie connectivity type: %d\n",
1908 __func__, id);
1909 return -ENODEV;
1910 }
1911}
1912
1913struct vreg *fm_regulator;
1914static int fm_radio_setup(struct marimba_fm_platform_data *pdata)
1915{
1916 int rc;
1917 uint32_t irqcfg;
1918 const char *id = "FMPW";
1919
1920 int bahama_not_marimba = bahama_present();
1921
1922 if (bahama_not_marimba == -1) {
1923 printk(KERN_WARNING "%s: bahama_present: %d\n",
1924 __func__, bahama_not_marimba);
1925 return -ENODEV;
1926 }
1927 if (bahama_not_marimba)
1928 fm_regulator = vreg_get(NULL, "s3");
1929 else
1930 fm_regulator = vreg_get(NULL, "s2");
1931
1932 if (IS_ERR(fm_regulator)) {
1933 printk(KERN_ERR "%s: vreg get failed (%ld)\n",
1934 __func__, PTR_ERR(fm_regulator));
1935 return -1;
1936 }
1937 if (!bahama_not_marimba) {
1938
1939 rc = pmapp_vreg_level_vote(id, PMAPP_VREG_S2, 1300);
1940
1941 if (rc < 0) {
1942 printk(KERN_ERR "%s: voltage level vote failed (%d)\n",
1943 __func__, rc);
1944 return rc;
1945 }
1946 }
1947 rc = vreg_enable(fm_regulator);
1948 if (rc) {
1949 printk(KERN_ERR "%s: vreg_enable() = %d\n",
1950 __func__, rc);
1951 return rc;
1952 }
1953
1954 rc = pmapp_clock_vote(id, PMAPP_CLOCK_ID_DO,
1955 PMAPP_CLOCK_VOTE_ON);
1956 if (rc < 0) {
1957 printk(KERN_ERR "%s: clock vote failed (%d)\n",
1958 __func__, rc);
1959 goto fm_clock_vote_fail;
1960 }
1961 /*Request the Clock Using GPIO34/AP2MDM_MRMBCK_EN in case
1962 of svlte*/
1963 if (machine_is_msm8x55_svlte_surf() ||
1964 machine_is_msm8x55_svlte_ffa()) {
1965 rc = marimba_gpio_config(1);
1966 if (rc < 0)
1967 printk(KERN_ERR "%s: clock enable for svlte : %d\n",
1968 __func__, rc);
1969 }
1970 irqcfg = GPIO_CFG(147, 0, GPIO_CFG_INPUT, GPIO_CFG_NO_PULL,
1971 GPIO_CFG_2MA);
1972 rc = gpio_tlmm_config(irqcfg, GPIO_CFG_ENABLE);
1973 if (rc) {
1974 printk(KERN_ERR "%s: gpio_tlmm_config(%#x)=%d\n",
1975 __func__, irqcfg, rc);
1976 rc = -EIO;
1977 goto fm_gpio_config_fail;
1978
1979 }
1980 return 0;
1981fm_gpio_config_fail:
1982 pmapp_clock_vote(id, PMAPP_CLOCK_ID_DO,
1983 PMAPP_CLOCK_VOTE_OFF);
1984fm_clock_vote_fail:
1985 vreg_disable(fm_regulator);
1986 return rc;
1987
1988};
1989
1990static void fm_radio_shutdown(struct marimba_fm_platform_data *pdata)
1991{
1992 int rc;
1993 const char *id = "FMPW";
1994 uint32_t irqcfg = GPIO_CFG(147, 0, GPIO_CFG_INPUT, GPIO_CFG_PULL_UP,
1995 GPIO_CFG_2MA);
1996
1997 int bahama_not_marimba = bahama_present();
1998 if (bahama_not_marimba == -1) {
1999 printk(KERN_WARNING "%s: bahama_present: %d\n",
2000 __func__, bahama_not_marimba);
2001 return;
2002 }
2003
2004 rc = gpio_tlmm_config(irqcfg, GPIO_CFG_ENABLE);
2005 if (rc) {
2006 printk(KERN_ERR "%s: gpio_tlmm_config(%#x)=%d\n",
2007 __func__, irqcfg, rc);
2008 }
2009 if (fm_regulator != NULL) {
2010 rc = vreg_disable(fm_regulator);
2011
2012 if (rc) {
2013 printk(KERN_ERR "%s: return val: %d\n",
2014 __func__, rc);
2015 }
2016 fm_regulator = NULL;
2017 }
2018 rc = pmapp_clock_vote(id, PMAPP_CLOCK_ID_DO,
2019 PMAPP_CLOCK_VOTE_OFF);
2020 if (rc < 0)
2021 printk(KERN_ERR "%s: clock_vote return val: %d\n",
2022 __func__, rc);
2023
2024 /*Disable the Clock Using GPIO34/AP2MDM_MRMBCK_EN in case
2025 of svlte*/
2026 if (machine_is_msm8x55_svlte_surf() ||
2027 machine_is_msm8x55_svlte_ffa()) {
2028 rc = marimba_gpio_config(0);
2029 if (rc < 0)
2030 printk(KERN_ERR "%s: clock disable for svlte : %d\n",
2031 __func__, rc);
2032 }
2033
2034
2035 if (!bahama_not_marimba) {
2036 rc = pmapp_vreg_level_vote(id, PMAPP_VREG_S2, 0);
2037
2038 if (rc < 0)
2039 printk(KERN_ERR "%s: vreg level vote return val: %d\n",
2040 __func__, rc);
2041 }
2042}
2043
2044static struct marimba_fm_platform_data marimba_fm_pdata = {
2045 .fm_setup = fm_radio_setup,
2046 .fm_shutdown = fm_radio_shutdown,
2047 .irq = MSM_GPIO_TO_INT(147),
2048 .vreg_s2 = NULL,
2049 .vreg_xo_out = NULL,
2050 .is_fm_soc_i2s_master = false,
2051 .config_i2s_gpio = NULL,
2052};
2053
2054
2055/* Slave id address for FM/CDC/QMEMBIST
2056 * Values can be programmed using Marimba slave id 0
2057 * should there be a conflict with other I2C devices
2058 * */
2059#define MARIMBA_SLAVE_ID_FM_ADDR 0x2A
2060#define MARIMBA_SLAVE_ID_CDC_ADDR 0x77
2061#define MARIMBA_SLAVE_ID_QMEMBIST_ADDR 0X66
2062
2063#define BAHAMA_SLAVE_ID_FM_ADDR 0x2A
2064#define BAHAMA_SLAVE_ID_QMEMBIST_ADDR 0x7B
2065
2066static const char *tsadc_id = "MADC";
2067static const char *vregs_tsadc_name[] = {
2068 "gp12",
2069 "s2",
2070};
2071static struct vreg *vregs_tsadc[ARRAY_SIZE(vregs_tsadc_name)];
2072
2073static const char *vregs_timpani_tsadc_name[] = {
2074 "s3",
2075 "gp12",
2076 "gp16"
2077};
2078static struct vreg *vregs_timpani_tsadc[ARRAY_SIZE(vregs_timpani_tsadc_name)];
2079
2080static int marimba_tsadc_power(int vreg_on)
2081{
2082 int i, rc = 0;
2083 int tsadc_adie_type = adie_get_detected_codec_type();
2084
2085 if (tsadc_adie_type == TIMPANI_ID) {
2086 for (i = 0; i < ARRAY_SIZE(vregs_timpani_tsadc_name); i++) {
2087 if (!vregs_timpani_tsadc[i]) {
2088 pr_err("%s: vreg_get %s failed(%d)\n",
2089 __func__, vregs_timpani_tsadc_name[i], rc);
2090 goto vreg_fail;
2091 }
2092
2093 rc = vreg_on ? vreg_enable(vregs_timpani_tsadc[i]) :
2094 vreg_disable(vregs_timpani_tsadc[i]);
2095 if (rc < 0) {
2096 pr_err("%s: vreg %s %s failed(%d)\n",
2097 __func__, vregs_timpani_tsadc_name[i],
2098 vreg_on ? "enable" : "disable", rc);
2099 goto vreg_fail;
2100 }
2101 }
2102 /* Vote for D0 and D1 buffer */
2103 rc = pmapp_clock_vote(tsadc_id, PMAPP_CLOCK_ID_D1,
2104 vreg_on ? PMAPP_CLOCK_VOTE_ON : PMAPP_CLOCK_VOTE_OFF);
2105 if (rc) {
2106 pr_err("%s: unable to %svote for d1 clk\n",
2107 __func__, vreg_on ? "" : "de-");
2108 goto do_vote_fail;
2109 }
2110 rc = pmapp_clock_vote(tsadc_id, PMAPP_CLOCK_ID_DO,
2111 vreg_on ? PMAPP_CLOCK_VOTE_ON : PMAPP_CLOCK_VOTE_OFF);
2112 if (rc) {
2113 pr_err("%s: unable to %svote for d1 clk\n",
2114 __func__, vreg_on ? "" : "de-");
2115 goto do_vote_fail;
2116 }
2117 } else if (tsadc_adie_type == MARIMBA_ID) {
2118 for (i = 0; i < ARRAY_SIZE(vregs_tsadc_name); i++) {
2119 if (!vregs_tsadc[i]) {
2120 pr_err("%s: vreg_get %s failed (%d)\n",
2121 __func__, vregs_tsadc_name[i], rc);
2122 goto vreg_fail;
2123 }
2124
2125 rc = vreg_on ? vreg_enable(vregs_tsadc[i]) :
2126 vreg_disable(vregs_tsadc[i]);
2127 if (rc < 0) {
2128 pr_err("%s: vreg %s %s failed (%d)\n",
2129 __func__, vregs_tsadc_name[i],
2130 vreg_on ? "enable" : "disable", rc);
2131 goto vreg_fail;
2132 }
2133 }
2134 /* If marimba vote for DO buffer */
2135 rc = pmapp_clock_vote(tsadc_id, PMAPP_CLOCK_ID_DO,
2136 vreg_on ? PMAPP_CLOCK_VOTE_ON : PMAPP_CLOCK_VOTE_OFF);
2137 if (rc) {
2138 pr_err("%s: unable to %svote for d0 clk\n",
2139 __func__, vreg_on ? "" : "de-");
2140 goto do_vote_fail;
2141 }
2142 } else {
2143 pr_err("%s:Adie %d not supported\n",
2144 __func__, tsadc_adie_type);
2145 return -ENODEV;
2146 }
2147
2148 msleep(5); /* ensure power is stable */
2149
2150 return 0;
2151
2152do_vote_fail:
2153vreg_fail:
2154 while (i) {
2155 if (vreg_on) {
2156 if (tsadc_adie_type == TIMPANI_ID)
2157 vreg_disable(vregs_timpani_tsadc[--i]);
2158 else if (tsadc_adie_type == MARIMBA_ID)
2159 vreg_disable(vregs_tsadc[--i]);
2160 } else {
2161 if (tsadc_adie_type == TIMPANI_ID)
2162 vreg_enable(vregs_timpani_tsadc[--i]);
2163 else if (tsadc_adie_type == MARIMBA_ID)
2164 vreg_enable(vregs_tsadc[--i]);
2165 }
2166 }
2167
2168 return rc;
2169}
2170
2171static int marimba_tsadc_vote(int vote_on)
2172{
2173 int rc = 0;
2174
2175 if (adie_get_detected_codec_type() == MARIMBA_ID) {
2176 int level = vote_on ? 1300 : 0;
2177 rc = pmapp_vreg_level_vote(tsadc_id, PMAPP_VREG_S2, level);
2178 if (rc < 0)
2179 pr_err("%s: vreg level %s failed (%d)\n",
2180 __func__, vote_on ? "on" : "off", rc);
2181 }
2182
2183 return rc;
2184}
2185
2186static int marimba_tsadc_init(void)
2187{
2188 int i, rc = 0;
2189 int tsadc_adie_type = adie_get_detected_codec_type();
2190
2191 if (tsadc_adie_type == TIMPANI_ID) {
2192 for (i = 0; i < ARRAY_SIZE(vregs_timpani_tsadc_name); i++) {
2193 vregs_timpani_tsadc[i] = vreg_get(NULL,
2194 vregs_timpani_tsadc_name[i]);
2195 if (IS_ERR(vregs_timpani_tsadc[i])) {
2196 pr_err("%s: vreg get %s failed (%ld)\n",
2197 __func__, vregs_timpani_tsadc_name[i],
2198 PTR_ERR(vregs_timpani_tsadc[i]));
2199 rc = PTR_ERR(vregs_timpani_tsadc[i]);
2200 goto vreg_get_fail;
2201 }
2202 }
2203 } else if (tsadc_adie_type == MARIMBA_ID) {
2204 for (i = 0; i < ARRAY_SIZE(vregs_tsadc_name); i++) {
2205 vregs_tsadc[i] = vreg_get(NULL, vregs_tsadc_name[i]);
2206 if (IS_ERR(vregs_tsadc[i])) {
2207 pr_err("%s: vreg get %s failed (%ld)\n",
2208 __func__, vregs_tsadc_name[i],
2209 PTR_ERR(vregs_tsadc[i]));
2210 rc = PTR_ERR(vregs_tsadc[i]);
2211 goto vreg_get_fail;
2212 }
2213 }
2214 } else {
2215 pr_err("%s:Adie %d not supported\n",
2216 __func__, tsadc_adie_type);
2217 return -ENODEV;
2218 }
2219
2220 return 0;
2221
2222vreg_get_fail:
2223 while (i) {
2224 if (tsadc_adie_type == TIMPANI_ID)
2225 vreg_put(vregs_timpani_tsadc[--i]);
2226 else if (tsadc_adie_type == MARIMBA_ID)
2227 vreg_put(vregs_tsadc[--i]);
2228 }
2229 return rc;
2230}
2231
2232static int marimba_tsadc_exit(void)
2233{
2234 int i, rc = 0;
2235 int tsadc_adie_type = adie_get_detected_codec_type();
2236
2237 if (tsadc_adie_type == TIMPANI_ID) {
2238 for (i = 0; i < ARRAY_SIZE(vregs_timpani_tsadc_name); i++) {
2239 if (vregs_tsadc[i])
2240 vreg_put(vregs_timpani_tsadc[i]);
2241 }
2242 } else if (tsadc_adie_type == MARIMBA_ID) {
2243 for (i = 0; i < ARRAY_SIZE(vregs_tsadc_name); i++) {
2244 if (vregs_tsadc[i])
2245 vreg_put(vregs_tsadc[i]);
2246 }
2247 rc = pmapp_vreg_level_vote(tsadc_id, PMAPP_VREG_S2, 0);
2248 if (rc < 0)
2249 pr_err("%s: vreg level off failed (%d)\n",
2250 __func__, rc);
2251 } else {
2252 pr_err("%s:Adie %d not supported\n",
2253 __func__, tsadc_adie_type);
2254 rc = -ENODEV;
2255 }
2256
2257 return rc;
2258}
2259
2260
2261static struct msm_ts_platform_data msm_ts_data = {
2262 .min_x = 0,
2263 .max_x = 4096,
2264 .min_y = 0,
2265 .max_y = 4096,
2266 .min_press = 0,
2267 .max_press = 255,
2268 .inv_x = 4096,
2269 .inv_y = 4096,
2270 .can_wakeup = false,
2271};
2272
2273static struct marimba_tsadc_platform_data marimba_tsadc_pdata = {
2274 .marimba_tsadc_power = marimba_tsadc_power,
2275 .init = marimba_tsadc_init,
2276 .exit = marimba_tsadc_exit,
2277 .level_vote = marimba_tsadc_vote,
2278 .tsadc_prechg_en = true,
2279 .can_wakeup = false,
2280 .setup = {
2281 .pen_irq_en = true,
2282 .tsadc_en = true,
2283 },
2284 .params2 = {
2285 .input_clk_khz = 2400,
2286 .sample_prd = TSADC_CLK_3,
2287 },
2288 .params3 = {
2289 .prechg_time_nsecs = 6400,
2290 .stable_time_nsecs = 6400,
2291 .tsadc_test_mode = 0,
2292 },
2293 .tssc_data = &msm_ts_data,
2294};
2295
2296static struct vreg *vreg_codec_s4;
2297static int msm_marimba_codec_power(int vreg_on)
2298{
2299 int rc = 0;
2300
2301 if (!vreg_codec_s4) {
2302
2303 vreg_codec_s4 = vreg_get(NULL, "s4");
2304
2305 if (IS_ERR(vreg_codec_s4)) {
2306 printk(KERN_ERR "%s: vreg_get() failed (%ld)\n",
2307 __func__, PTR_ERR(vreg_codec_s4));
2308 rc = PTR_ERR(vreg_codec_s4);
2309 goto vreg_codec_s4_fail;
2310 }
2311 }
2312
2313 if (vreg_on) {
2314 rc = vreg_enable(vreg_codec_s4);
2315 if (rc)
2316 printk(KERN_ERR "%s: vreg_enable() = %d \n",
2317 __func__, rc);
2318 goto vreg_codec_s4_fail;
2319 } else {
2320 rc = vreg_disable(vreg_codec_s4);
2321 if (rc)
2322 printk(KERN_ERR "%s: vreg_disable() = %d \n",
2323 __func__, rc);
2324 goto vreg_codec_s4_fail;
2325 }
2326
2327vreg_codec_s4_fail:
2328 return rc;
2329}
2330
2331static struct marimba_codec_platform_data mariba_codec_pdata = {
2332 .marimba_codec_power = msm_marimba_codec_power,
2333#ifdef CONFIG_MARIMBA_CODEC
2334 .snddev_profile_init = msm_snddev_init,
2335#endif
2336};
2337
2338static struct marimba_platform_data marimba_pdata = {
2339 .slave_id[MARIMBA_SLAVE_ID_FM] = MARIMBA_SLAVE_ID_FM_ADDR,
2340 .slave_id[MARIMBA_SLAVE_ID_CDC] = MARIMBA_SLAVE_ID_CDC_ADDR,
2341 .slave_id[MARIMBA_SLAVE_ID_QMEMBIST] = MARIMBA_SLAVE_ID_QMEMBIST_ADDR,
2342 .slave_id[SLAVE_ID_BAHAMA_FM] = BAHAMA_SLAVE_ID_FM_ADDR,
2343 .slave_id[SLAVE_ID_BAHAMA_QMEMBIST] = BAHAMA_SLAVE_ID_QMEMBIST_ADDR,
2344 .marimba_setup = msm_marimba_setup_power,
2345 .marimba_shutdown = msm_marimba_shutdown_power,
2346 .bahama_setup = msm_bahama_setup_power,
2347 .bahama_shutdown = msm_bahama_shutdown_power,
2348 .marimba_gpio_config = msm_marimba_gpio_config_svlte,
2349 .bahama_core_config = msm_bahama_core_config,
2350 .fm = &marimba_fm_pdata,
2351 .codec = &mariba_codec_pdata,
2352 .tsadc_ssbi_adap = MARIMBA_SSBI_ADAP,
2353};
2354
2355static void __init msm7x30_init_marimba(void)
2356{
2357 int rc;
2358
2359 vreg_marimba_1 = vreg_get(NULL, "s3");
2360 if (IS_ERR(vreg_marimba_1)) {
2361 printk(KERN_ERR "%s: vreg get failed (%ld)\n",
2362 __func__, PTR_ERR(vreg_marimba_1));
2363 return;
2364 }
2365 rc = vreg_set_level(vreg_marimba_1, 1800);
2366
2367 vreg_marimba_2 = vreg_get(NULL, "gp16");
2368 if (IS_ERR(vreg_marimba_1)) {
2369 printk(KERN_ERR "%s: vreg get failed (%ld)\n",
2370 __func__, PTR_ERR(vreg_marimba_1));
2371 return;
2372 }
2373 rc = vreg_set_level(vreg_marimba_2, 1200);
2374
2375 vreg_marimba_3 = vreg_get(NULL, "usb2");
2376 if (IS_ERR(vreg_marimba_3)) {
2377 printk(KERN_ERR "%s: vreg get failed (%ld)\n",
2378 __func__, PTR_ERR(vreg_marimba_3));
2379 return;
2380 }
2381 rc = vreg_set_level(vreg_marimba_3, 1800);
2382}
2383
2384static struct marimba_codec_platform_data timpani_codec_pdata = {
2385 .marimba_codec_power = msm_marimba_codec_power,
2386#ifdef CONFIG_TIMPANI_CODEC
2387 .snddev_profile_init = msm_snddev_init_timpani,
2388#endif
2389};
2390
2391static struct marimba_platform_data timpani_pdata = {
2392 .slave_id[MARIMBA_SLAVE_ID_CDC] = MARIMBA_SLAVE_ID_CDC_ADDR,
2393 .slave_id[MARIMBA_SLAVE_ID_QMEMBIST] = MARIMBA_SLAVE_ID_QMEMBIST_ADDR,
2394 .marimba_setup = msm_timpani_setup_power,
2395 .marimba_shutdown = msm_timpani_shutdown_power,
2396 .codec = &timpani_codec_pdata,
2397 .tsadc = &marimba_tsadc_pdata,
2398 .tsadc_ssbi_adap = MARIMBA_SSBI_ADAP,
2399};
2400
2401#define TIMPANI_I2C_SLAVE_ADDR 0xD
2402
2403static struct i2c_board_info msm_i2c_gsbi7_timpani_info[] = {
2404 {
2405 I2C_BOARD_INFO("timpani", TIMPANI_I2C_SLAVE_ADDR),
2406 .platform_data = &timpani_pdata,
2407 },
2408};
2409
2410#ifdef CONFIG_MSM7KV2_AUDIO
2411static struct resource msm_aictl_resources[] = {
2412 {
2413 .name = "aictl",
2414 .start = 0xa5000100,
2415 .end = 0xa5000100,
2416 .flags = IORESOURCE_MEM,
2417 }
2418};
2419
2420static struct resource msm_mi2s_resources[] = {
2421 {
2422 .name = "hdmi",
2423 .start = 0xac900000,
2424 .end = 0xac900038,
2425 .flags = IORESOURCE_MEM,
2426 },
2427 {
2428 .name = "codec_rx",
2429 .start = 0xac940040,
2430 .end = 0xac940078,
2431 .flags = IORESOURCE_MEM,
2432 },
2433 {
2434 .name = "codec_tx",
2435 .start = 0xac980080,
2436 .end = 0xac9800B8,
2437 .flags = IORESOURCE_MEM,
2438 }
2439
2440};
2441
2442static struct msm_lpa_platform_data lpa_pdata = {
2443 .obuf_hlb_size = 0x2BFF8,
2444 .dsp_proc_id = 0,
2445 .app_proc_id = 2,
2446 .nosb_config = {
2447 .llb_min_addr = 0,
2448 .llb_max_addr = 0x3ff8,
2449 .sb_min_addr = 0,
2450 .sb_max_addr = 0,
2451 },
2452 .sb_config = {
2453 .llb_min_addr = 0,
2454 .llb_max_addr = 0x37f8,
2455 .sb_min_addr = 0x3800,
2456 .sb_max_addr = 0x3ff8,
2457 }
2458};
2459
2460static struct resource msm_lpa_resources[] = {
2461 {
2462 .name = "lpa",
2463 .start = 0xa5000000,
2464 .end = 0xa50000a0,
2465 .flags = IORESOURCE_MEM,
2466 }
2467};
2468
2469static struct resource msm_aux_pcm_resources[] = {
2470
2471 {
2472 .name = "aux_codec_reg_addr",
2473 .start = 0xac9c00c0,
2474 .end = 0xac9c00c8,
2475 .flags = IORESOURCE_MEM,
2476 },
2477 {
2478 .name = "aux_pcm_dout",
2479 .start = 138,
2480 .end = 138,
2481 .flags = IORESOURCE_IO,
2482 },
2483 {
2484 .name = "aux_pcm_din",
2485 .start = 139,
2486 .end = 139,
2487 .flags = IORESOURCE_IO,
2488 },
2489 {
2490 .name = "aux_pcm_syncout",
2491 .start = 140,
2492 .end = 140,
2493 .flags = IORESOURCE_IO,
2494 },
2495 {
2496 .name = "aux_pcm_clkin_a",
2497 .start = 141,
2498 .end = 141,
2499 .flags = IORESOURCE_IO,
2500 },
2501};
2502
2503static struct platform_device msm_aux_pcm_device = {
2504 .name = "msm_aux_pcm",
2505 .id = 0,
2506 .num_resources = ARRAY_SIZE(msm_aux_pcm_resources),
2507 .resource = msm_aux_pcm_resources,
2508};
2509
2510struct platform_device msm_aictl_device = {
2511 .name = "audio_interct",
2512 .id = 0,
2513 .num_resources = ARRAY_SIZE(msm_aictl_resources),
2514 .resource = msm_aictl_resources,
2515};
2516
2517struct platform_device msm_mi2s_device = {
2518 .name = "mi2s",
2519 .id = 0,
2520 .num_resources = ARRAY_SIZE(msm_mi2s_resources),
2521 .resource = msm_mi2s_resources,
2522};
2523
2524struct platform_device msm_lpa_device = {
2525 .name = "lpa",
2526 .id = 0,
2527 .num_resources = ARRAY_SIZE(msm_lpa_resources),
2528 .resource = msm_lpa_resources,
2529 .dev = {
2530 .platform_data = &lpa_pdata,
2531 },
2532};
2533#endif /* CONFIG_MSM7KV2_AUDIO */
2534
2535#define DEC0_FORMAT ((1<<MSM_ADSP_CODEC_MP3)| \
2536 (1<<MSM_ADSP_CODEC_AAC)|(1<<MSM_ADSP_CODEC_WMA)| \
2537 (1<<MSM_ADSP_CODEC_WMAPRO)|(1<<MSM_ADSP_CODEC_AMRWB)| \
2538 (1<<MSM_ADSP_CODEC_AMRNB)|(1<<MSM_ADSP_CODEC_WAV)| \
2539 (1<<MSM_ADSP_CODEC_ADPCM)|(1<<MSM_ADSP_CODEC_YADPCM)| \
2540 (1<<MSM_ADSP_CODEC_EVRC)|(1<<MSM_ADSP_CODEC_QCELP))
2541#define DEC1_FORMAT ((1<<MSM_ADSP_CODEC_MP3)| \
2542 (1<<MSM_ADSP_CODEC_AAC)|(1<<MSM_ADSP_CODEC_WMA)| \
2543 (1<<MSM_ADSP_CODEC_WMAPRO)|(1<<MSM_ADSP_CODEC_AMRWB)| \
2544 (1<<MSM_ADSP_CODEC_AMRNB)|(1<<MSM_ADSP_CODEC_WAV)| \
2545 (1<<MSM_ADSP_CODEC_ADPCM)|(1<<MSM_ADSP_CODEC_YADPCM)| \
2546 (1<<MSM_ADSP_CODEC_EVRC)|(1<<MSM_ADSP_CODEC_QCELP))
2547 #define DEC2_FORMAT ((1<<MSM_ADSP_CODEC_MP3)| \
2548 (1<<MSM_ADSP_CODEC_AAC)|(1<<MSM_ADSP_CODEC_WMA)| \
2549 (1<<MSM_ADSP_CODEC_WMAPRO)|(1<<MSM_ADSP_CODEC_AMRWB)| \
2550 (1<<MSM_ADSP_CODEC_AMRNB)|(1<<MSM_ADSP_CODEC_WAV)| \
2551 (1<<MSM_ADSP_CODEC_ADPCM)|(1<<MSM_ADSP_CODEC_YADPCM)| \
2552 (1<<MSM_ADSP_CODEC_EVRC)|(1<<MSM_ADSP_CODEC_QCELP))
2553 #define DEC3_FORMAT ((1<<MSM_ADSP_CODEC_MP3)| \
2554 (1<<MSM_ADSP_CODEC_AAC)|(1<<MSM_ADSP_CODEC_WMA)| \
2555 (1<<MSM_ADSP_CODEC_WMAPRO)|(1<<MSM_ADSP_CODEC_AMRWB)| \
2556 (1<<MSM_ADSP_CODEC_AMRNB)|(1<<MSM_ADSP_CODEC_WAV)| \
2557 (1<<MSM_ADSP_CODEC_ADPCM)|(1<<MSM_ADSP_CODEC_YADPCM)| \
2558 (1<<MSM_ADSP_CODEC_EVRC)|(1<<MSM_ADSP_CODEC_QCELP))
2559#define DEC4_FORMAT (1<<MSM_ADSP_CODEC_MIDI)
2560
2561static unsigned int dec_concurrency_table[] = {
2562 /* Audio LP */
2563 0,
2564 (DEC3_FORMAT|(1<<MSM_ADSP_MODE_NONTUNNEL)|(1<<MSM_ADSP_OP_DM)),
2565 (DEC2_FORMAT|(1<<MSM_ADSP_MODE_NONTUNNEL)|(1<<MSM_ADSP_OP_DM)),
2566 (DEC1_FORMAT|(1<<MSM_ADSP_MODE_NONTUNNEL)|(1<<MSM_ADSP_OP_DM)),
2567 (DEC0_FORMAT|(1<<MSM_ADSP_MODE_TUNNEL)|(1<<MSM_ADSP_MODE_LP)|
2568 (1<<MSM_ADSP_OP_DM)),
2569
2570 /* Concurrency 1 */
2571 (DEC4_FORMAT),
2572 (DEC3_FORMAT|(1<<MSM_ADSP_MODE_TUNNEL)|(1<<MSM_ADSP_OP_DM)),
2573 (DEC2_FORMAT|(1<<MSM_ADSP_MODE_TUNNEL)|(1<<MSM_ADSP_OP_DM)),
2574 (DEC1_FORMAT|(1<<MSM_ADSP_MODE_TUNNEL)|(1<<MSM_ADSP_OP_DM)),
2575 (DEC0_FORMAT|(1<<MSM_ADSP_MODE_TUNNEL)|(1<<MSM_ADSP_OP_DM)),
2576
2577 /* Concurrency 2 */
2578 (DEC4_FORMAT),
2579 (DEC3_FORMAT|(1<<MSM_ADSP_MODE_TUNNEL)|(1<<MSM_ADSP_OP_DM)),
2580 (DEC2_FORMAT|(1<<MSM_ADSP_MODE_TUNNEL)|(1<<MSM_ADSP_OP_DM)),
2581 (DEC1_FORMAT|(1<<MSM_ADSP_MODE_TUNNEL)|(1<<MSM_ADSP_OP_DM)),
2582 (DEC0_FORMAT|(1<<MSM_ADSP_MODE_TUNNEL)|(1<<MSM_ADSP_OP_DM)),
2583
2584 /* Concurrency 3 */
2585 (DEC4_FORMAT),
2586 (DEC3_FORMAT|(1<<MSM_ADSP_MODE_TUNNEL)|(1<<MSM_ADSP_OP_DM)),
2587 (DEC2_FORMAT|(1<<MSM_ADSP_MODE_TUNNEL)|(1<<MSM_ADSP_OP_DM)),
2588 (DEC1_FORMAT|(1<<MSM_ADSP_MODE_TUNNEL)|(1<<MSM_ADSP_OP_DM)),
2589 (DEC0_FORMAT|(1<<MSM_ADSP_MODE_NONTUNNEL)|(1<<MSM_ADSP_OP_DM)),
2590
2591 /* Concurrency 4 */
2592 (DEC4_FORMAT),
2593 (DEC3_FORMAT|(1<<MSM_ADSP_MODE_TUNNEL)|(1<<MSM_ADSP_OP_DM)),
2594 (DEC2_FORMAT|(1<<MSM_ADSP_MODE_TUNNEL)|(1<<MSM_ADSP_OP_DM)),
2595 (DEC1_FORMAT|(1<<MSM_ADSP_MODE_NONTUNNEL)|(1<<MSM_ADSP_OP_DM)),
2596 (DEC0_FORMAT|(1<<MSM_ADSP_MODE_NONTUNNEL)|(1<<MSM_ADSP_OP_DM)),
2597
2598 /* Concurrency 5 */
2599 (DEC4_FORMAT),
2600 (DEC3_FORMAT|(1<<MSM_ADSP_MODE_TUNNEL)|(1<<MSM_ADSP_OP_DM)),
2601 (DEC2_FORMAT|(1<<MSM_ADSP_MODE_NONTUNNEL)|(1<<MSM_ADSP_OP_DM)),
2602 (DEC1_FORMAT|(1<<MSM_ADSP_MODE_NONTUNNEL)|(1<<MSM_ADSP_OP_DM)),
2603 (DEC0_FORMAT|(1<<MSM_ADSP_MODE_NONTUNNEL)|(1<<MSM_ADSP_OP_DM)),
2604
2605 /* Concurrency 6 */
2606 (DEC4_FORMAT),
2607 (DEC3_FORMAT|(1<<MSM_ADSP_MODE_NONTUNNEL)|(1<<MSM_ADSP_OP_DM)),
2608 (DEC2_FORMAT|(1<<MSM_ADSP_MODE_NONTUNNEL)|(1<<MSM_ADSP_OP_DM)),
2609 (DEC1_FORMAT|(1<<MSM_ADSP_MODE_NONTUNNEL)|(1<<MSM_ADSP_OP_DM)),
2610 (DEC0_FORMAT|(1<<MSM_ADSP_MODE_NONTUNNEL)|(1<<MSM_ADSP_OP_DM)),
2611};
2612
2613#define DEC_INFO(name, queueid, decid, nr_codec) { .module_name = name, \
2614 .module_queueid = queueid, .module_decid = decid, \
2615 .nr_codec_support = nr_codec}
2616
2617#define DEC_INSTANCE(max_instance_same, max_instance_diff) { \
2618 .max_instances_same_dec = max_instance_same, \
2619 .max_instances_diff_dec = max_instance_diff}
2620
2621static struct msm_adspdec_info dec_info_list[] = {
2622 DEC_INFO("AUDPLAY4TASK", 17, 4, 1), /* AudPlay4BitStreamCtrlQueue */
2623 DEC_INFO("AUDPLAY3TASK", 16, 3, 11), /* AudPlay3BitStreamCtrlQueue */
2624 DEC_INFO("AUDPLAY2TASK", 15, 2, 11), /* AudPlay2BitStreamCtrlQueue */
2625 DEC_INFO("AUDPLAY1TASK", 14, 1, 11), /* AudPlay1BitStreamCtrlQueue */
2626 DEC_INFO("AUDPLAY0TASK", 13, 0, 11), /* AudPlay0BitStreamCtrlQueue */
2627};
2628
2629static struct dec_instance_table dec_instance_list[][MSM_MAX_DEC_CNT] = {
2630 /* Non Turbo Mode */
2631 {
2632 DEC_INSTANCE(4, 3), /* WAV */
2633 DEC_INSTANCE(4, 3), /* ADPCM */
2634 DEC_INSTANCE(4, 2), /* MP3 */
2635 DEC_INSTANCE(0, 0), /* Real Audio */
2636 DEC_INSTANCE(4, 2), /* WMA */
2637 DEC_INSTANCE(3, 2), /* AAC */
2638 DEC_INSTANCE(0, 0), /* Reserved */
2639 DEC_INSTANCE(0, 0), /* MIDI */
2640 DEC_INSTANCE(4, 3), /* YADPCM */
2641 DEC_INSTANCE(4, 3), /* QCELP */
2642 DEC_INSTANCE(4, 3), /* AMRNB */
2643 DEC_INSTANCE(1, 1), /* AMRWB/WB+ */
2644 DEC_INSTANCE(4, 3), /* EVRC */
2645 DEC_INSTANCE(1, 1), /* WMAPRO */
2646 },
2647 /* Turbo Mode */
2648 {
2649 DEC_INSTANCE(4, 3), /* WAV */
2650 DEC_INSTANCE(4, 3), /* ADPCM */
2651 DEC_INSTANCE(4, 3), /* MP3 */
2652 DEC_INSTANCE(0, 0), /* Real Audio */
2653 DEC_INSTANCE(4, 3), /* WMA */
2654 DEC_INSTANCE(4, 3), /* AAC */
2655 DEC_INSTANCE(0, 0), /* Reserved */
2656 DEC_INSTANCE(0, 0), /* MIDI */
2657 DEC_INSTANCE(4, 3), /* YADPCM */
2658 DEC_INSTANCE(4, 3), /* QCELP */
2659 DEC_INSTANCE(4, 3), /* AMRNB */
2660 DEC_INSTANCE(2, 3), /* AMRWB/WB+ */
2661 DEC_INSTANCE(4, 3), /* EVRC */
2662 DEC_INSTANCE(1, 2), /* WMAPRO */
2663 },
2664};
2665
2666static struct msm_adspdec_database msm_device_adspdec_database = {
2667 .num_dec = ARRAY_SIZE(dec_info_list),
2668 .num_concurrency_support = (ARRAY_SIZE(dec_concurrency_table) / \
2669 ARRAY_SIZE(dec_info_list)),
2670 .dec_concurrency_table = dec_concurrency_table,
2671 .dec_info_list = dec_info_list,
2672 .dec_instance_list = &dec_instance_list[0][0],
2673};
2674
2675static struct platform_device msm_device_adspdec = {
2676 .name = "msm_adspdec",
2677 .id = -1,
2678 .dev = {
2679 .platform_data = &msm_device_adspdec_database
2680 },
2681};
2682
2683static struct resource smc91x_resources[] = {
2684 [0] = {
2685 .start = 0x8A000300,
2686 .end = 0x8A0003ff,
2687 .flags = IORESOURCE_MEM,
2688 },
2689 [1] = {
2690 .start = MSM_GPIO_TO_INT(156),
2691 .end = MSM_GPIO_TO_INT(156),
2692 .flags = IORESOURCE_IRQ,
2693 },
2694};
2695
2696static struct platform_device smc91x_device = {
2697 .name = "smc91x",
2698 .id = 0,
2699 .num_resources = ARRAY_SIZE(smc91x_resources),
2700 .resource = smc91x_resources,
2701};
2702
2703static struct smsc911x_platform_config smsc911x_config = {
2704 .phy_interface = PHY_INTERFACE_MODE_MII,
2705 .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
2706 .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL,
2707 .flags = SMSC911X_USE_32BIT,
2708};
2709
2710static struct resource smsc911x_resources[] = {
2711 [0] = {
2712 .start = 0x8D000000,
2713 .end = 0x8D000100,
2714 .flags = IORESOURCE_MEM,
2715 },
2716 [1] = {
2717 .start = MSM_GPIO_TO_INT(88),
2718 .end = MSM_GPIO_TO_INT(88),
2719 .flags = IORESOURCE_IRQ,
2720 },
2721};
2722
2723static struct platform_device smsc911x_device = {
2724 .name = "smsc911x",
2725 .id = -1,
2726 .num_resources = ARRAY_SIZE(smsc911x_resources),
2727 .resource = smsc911x_resources,
2728 .dev = {
2729 .platform_data = &smsc911x_config,
2730 },
2731};
2732
2733static struct msm_gpio smsc911x_gpios[] = {
2734 { GPIO_CFG(172, 2, GPIO_CFG_OUTPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA), "ebi2_addr6" },
2735 { GPIO_CFG(173, 2, GPIO_CFG_OUTPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA), "ebi2_addr5" },
2736 { GPIO_CFG(174, 2, GPIO_CFG_OUTPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA), "ebi2_addr4" },
2737 { GPIO_CFG(175, 2, GPIO_CFG_OUTPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA), "ebi2_addr3" },
2738 { GPIO_CFG(176, 2, GPIO_CFG_OUTPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA), "ebi2_addr2" },
2739 { GPIO_CFG(177, 2, GPIO_CFG_OUTPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA), "ebi2_addr1" },
2740 { GPIO_CFG(178, 2, GPIO_CFG_OUTPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA), "ebi2_addr0" },
2741 { GPIO_CFG(88, 2, GPIO_CFG_INPUT, GPIO_CFG_PULL_UP, GPIO_CFG_2MA), "smsc911x_irq" },
2742};
2743
2744static void msm7x30_cfg_smsc911x(void)
2745{
2746 int rc;
2747
2748 rc = msm_gpios_request_enable(smsc911x_gpios,
2749 ARRAY_SIZE(smsc911x_gpios));
2750 if (rc)
2751 pr_err("%s: unable to enable gpios\n", __func__);
2752}
2753
2754#ifdef CONFIG_USB_G_ANDROID
2755static struct android_usb_platform_data android_usb_pdata = {
2756 .update_pid_and_serial_num = usb_diag_update_pid_and_serial_num,
2757};
2758
2759static struct platform_device android_usb_device = {
2760 .name = "android_usb",
2761 .id = -1,
2762 .dev = {
2763 .platform_data = &android_usb_pdata,
2764 },
2765};
2766#endif
2767
2768static struct msm_gpio optnav_config_data[] = {
2769 { GPIO_CFG(OPTNAV_CHIP_SELECT, 0, GPIO_CFG_OUTPUT, GPIO_CFG_PULL_UP, GPIO_CFG_8MA),
2770 "optnav_chip_select" },
2771};
2772
2773static void __iomem *virtual_optnav;
2774
2775static int optnav_gpio_setup(void)
2776{
2777 int rc = -ENODEV;
2778 rc = msm_gpios_request_enable(optnav_config_data,
2779 ARRAY_SIZE(optnav_config_data));
2780
2781 /* Configure the FPGA for GPIOs */
2782 virtual_optnav = ioremap(FPGA_OPTNAV_GPIO_ADDR, 0x4);
2783 if (!virtual_optnav) {
2784 pr_err("%s:Could not ioremap region\n", __func__);
2785 return -ENOMEM;
2786 }
2787 /*
2788 * Configure the FPGA to set GPIO 19 as
2789 * normal, active(enabled), output(MSM to SURF)
2790 */
2791 writew(0x311E, virtual_optnav);
2792 return rc;
2793}
2794
2795static void optnav_gpio_release(void)
2796{
2797 msm_gpios_disable_free(optnav_config_data,
2798 ARRAY_SIZE(optnav_config_data));
2799 iounmap(virtual_optnav);
2800}
2801
2802static struct vreg *vreg_gp7;
2803static struct vreg *vreg_gp4;
2804static struct vreg *vreg_gp9;
2805static struct vreg *vreg_usb3_3;
2806
2807static int optnav_enable(void)
2808{
2809 int rc;
2810 /*
2811 * Enable the VREGs L8(gp7), L10(gp4), L12(gp9), L6(usb)
2812 * for I2C communication with keyboard.
2813 */
2814 vreg_gp7 = vreg_get(NULL, "gp7");
2815 rc = vreg_set_level(vreg_gp7, 1800);
2816 if (rc) {
2817 pr_err("%s: vreg_set_level failed \n", __func__);
2818 goto fail_vreg_gp7;
2819 }
2820
2821 rc = vreg_enable(vreg_gp7);
2822 if (rc) {
2823 pr_err("%s: vreg_enable failed \n", __func__);
2824 goto fail_vreg_gp7;
2825 }
2826
2827 vreg_gp4 = vreg_get(NULL, "gp4");
2828 rc = vreg_set_level(vreg_gp4, 2600);
2829 if (rc) {
2830 pr_err("%s: vreg_set_level failed \n", __func__);
2831 goto fail_vreg_gp4;
2832 }
2833
2834 rc = vreg_enable(vreg_gp4);
2835 if (rc) {
2836 pr_err("%s: vreg_enable failed \n", __func__);
2837 goto fail_vreg_gp4;
2838 }
2839
2840 vreg_gp9 = vreg_get(NULL, "gp9");
2841 rc = vreg_set_level(vreg_gp9, 1800);
2842 if (rc) {
2843 pr_err("%s: vreg_set_level failed \n", __func__);
2844 goto fail_vreg_gp9;
2845 }
2846
2847 rc = vreg_enable(vreg_gp9);
2848 if (rc) {
2849 pr_err("%s: vreg_enable failed \n", __func__);
2850 goto fail_vreg_gp9;
2851 }
2852
2853 vreg_usb3_3 = vreg_get(NULL, "usb");
2854 rc = vreg_set_level(vreg_usb3_3, 3300);
2855 if (rc) {
2856 pr_err("%s: vreg_set_level failed \n", __func__);
2857 goto fail_vreg_3_3;
2858 }
2859
2860 rc = vreg_enable(vreg_usb3_3);
2861 if (rc) {
2862 pr_err("%s: vreg_enable failed \n", __func__);
2863 goto fail_vreg_3_3;
2864 }
2865
2866 /* Enable the chip select GPIO */
2867 gpio_set_value(OPTNAV_CHIP_SELECT, 1);
2868 gpio_set_value(OPTNAV_CHIP_SELECT, 0);
2869
2870 return 0;
2871
2872fail_vreg_3_3:
2873 vreg_disable(vreg_gp9);
2874fail_vreg_gp9:
2875 vreg_disable(vreg_gp4);
2876fail_vreg_gp4:
2877 vreg_disable(vreg_gp7);
2878fail_vreg_gp7:
2879 return rc;
2880}
2881
2882static void optnav_disable(void)
2883{
2884 vreg_disable(vreg_usb3_3);
2885 vreg_disable(vreg_gp9);
2886 vreg_disable(vreg_gp4);
2887 vreg_disable(vreg_gp7);
2888
2889 gpio_set_value(OPTNAV_CHIP_SELECT, 1);
2890}
2891
2892static struct ofn_atlab_platform_data optnav_data = {
2893 .gpio_setup = optnav_gpio_setup,
2894 .gpio_release = optnav_gpio_release,
2895 .optnav_on = optnav_enable,
2896 .optnav_off = optnav_disable,
2897 .rotate_xy = 0,
2898 .function1 = {
2899 .no_motion1_en = true,
2900 .touch_sensor_en = true,
2901 .ofn_en = true,
2902 .clock_select_khz = 1500,
2903 .cpi_selection = 1200,
2904 },
2905 .function2 = {
2906 .invert_y = false,
2907 .invert_x = true,
2908 .swap_x_y = false,
2909 .hold_a_b_en = true,
2910 .motion_filter_en = true,
2911 },
2912};
2913
2914static int hdmi_comm_power(int on, int show);
2915static int hdmi_init_irq(void);
2916static int hdmi_enable_5v(int on);
2917static int hdmi_core_power(int on, int show);
2918static int hdmi_cec_power(int on);
2919static bool hdmi_check_hdcp_hw_support(void);
2920
2921static struct msm_hdmi_platform_data adv7520_hdmi_data = {
2922 .irq = MSM_GPIO_TO_INT(18),
2923 .comm_power = hdmi_comm_power,
2924 .init_irq = hdmi_init_irq,
2925 .enable_5v = hdmi_enable_5v,
2926 .core_power = hdmi_core_power,
2927 .cec_power = hdmi_cec_power,
2928 .check_hdcp_hw_support = hdmi_check_hdcp_hw_support,
2929};
2930
2931#ifdef CONFIG_BOSCH_BMA150
2932static struct vreg *vreg_gp6;
2933static int sensors_ldo_enable(void)
2934{
2935 int rc;
2936
2937 /*
2938 * Enable the VREGs L8(gp7), L15(gp6)
2939 * for I2C communication with sensors.
2940 */
2941 pr_info("sensors_ldo_enable called!!\n");
2942 vreg_gp7 = vreg_get(NULL, "gp7");
2943 if (IS_ERR(vreg_gp7)) {
2944 pr_err("%s: vreg_get gp7 failed\n", __func__);
2945 rc = PTR_ERR(vreg_gp7);
2946 goto fail_gp7_get;
2947 }
2948
2949 rc = vreg_set_level(vreg_gp7, 1800);
2950 if (rc) {
2951 pr_err("%s: vreg_set_level gp7 failed\n", __func__);
2952 goto fail_gp7_level;
2953 }
2954
2955 rc = vreg_enable(vreg_gp7);
2956 if (rc) {
2957 pr_err("%s: vreg_enable gp7 failed\n", __func__);
2958 goto fail_gp7_level;
2959 }
2960
2961 vreg_gp6 = vreg_get(NULL, "gp6");
2962 if (IS_ERR(vreg_gp6)) {
2963 pr_err("%s: vreg_get gp6 failed\n", __func__);
2964 rc = PTR_ERR(vreg_gp6);
2965 goto fail_gp6_get;
2966 }
2967
2968 rc = vreg_set_level(vreg_gp6, 3050);
2969 if (rc) {
2970 pr_err("%s: vreg_set_level gp6 failed\n", __func__);
2971 goto fail_gp6_level;
2972 }
2973
2974 rc = vreg_enable(vreg_gp6);
2975 if (rc) {
2976 pr_err("%s: vreg_enable gp6 failed\n", __func__);
2977 goto fail_gp6_level;
2978 }
2979
2980 return 0;
2981
2982fail_gp6_level:
2983 vreg_put(vreg_gp6);
2984fail_gp6_get:
2985 vreg_disable(vreg_gp7);
2986fail_gp7_level:
2987 vreg_put(vreg_gp7);
2988fail_gp7_get:
2989 return rc;
2990}
2991
2992static void sensors_ldo_disable(void)
2993{
2994 pr_info("sensors_ldo_disable called!!\n");
2995 vreg_disable(vreg_gp6);
2996 vreg_put(vreg_gp6);
2997 vreg_disable(vreg_gp7);
2998 vreg_put(vreg_gp7);
2999}
3000static struct bma150_platform_data bma150_data = {
3001 .power_on = sensors_ldo_enable,
3002 .power_off = sensors_ldo_disable,
3003};
3004
3005static struct i2c_board_info bma150_board_info[] __initdata = {
3006 {
3007 I2C_BOARD_INFO("bma150", 0x38),
3008 .flags = I2C_CLIENT_WAKE,
3009 .irq = MSM_GPIO_TO_INT(BMA150_GPIO_INT),
3010 .platform_data = &bma150_data,
3011 },
3012};
3013#endif
3014
3015static struct i2c_board_info msm_i2c_board_info[] = {
3016 {
3017 I2C_BOARD_INFO("m33c01", OPTNAV_I2C_SLAVE_ADDR),
3018 .irq = MSM_GPIO_TO_INT(OPTNAV_IRQ),
3019 .platform_data = &optnav_data,
3020 },
3021 {
3022 I2C_BOARD_INFO("adv7520", ADV7520_I2C_ADDR),
3023 .platform_data = &adv7520_hdmi_data,
3024 },
3025};
3026
3027static struct i2c_board_info msm_marimba_board_info[] = {
3028 {
3029 I2C_BOARD_INFO("marimba", 0xc),
3030 .platform_data = &marimba_pdata,
3031 }
3032};
3033
3034
3035static struct msm_handset_platform_data hs_platform_data = {
3036 .hs_name = "7k_handset",
3037 .pwr_key_delay_ms = 500, /* 0 will disable end key */
3038};
3039
3040static struct platform_device hs_device = {
3041 .name = "msm-handset",
3042 .id = -1,
3043 .dev = {
3044 .platform_data = &hs_platform_data,
3045 },
3046};
3047
3048static struct msm_pm_platform_data msm_pm_data[MSM_PM_SLEEP_MODE_NR] = {
3049 [MSM_PM_SLEEP_MODE_POWER_COLLAPSE] = {
3050 .idle_supported = 1,
3051 .suspend_supported = 1,
3052 .idle_enabled = 1,
3053 .suspend_enabled = 1,
3054 .latency = 8594,
3055 .residency = 23740,
3056 },
3057 [MSM_PM_SLEEP_MODE_POWER_COLLAPSE_NO_XO_SHUTDOWN] = {
3058 .idle_supported = 1,
3059 .suspend_supported = 1,
3060 .idle_enabled = 1,
3061 .suspend_enabled = 1,
3062 .latency = 4594,
3063 .residency = 23740,
3064 },
3065 [MSM_PM_SLEEP_MODE_POWER_COLLAPSE_STANDALONE] = {
3066#ifdef CONFIG_MSM_STANDALONE_POWER_COLLAPSE
3067 .idle_supported = 1,
3068 .suspend_supported = 1,
3069 .idle_enabled = 1,
3070 .suspend_enabled = 0,
3071#else /*CONFIG_MSM_STANDALONE_POWER_COLLAPSE*/
3072 .idle_supported = 0,
3073 .suspend_supported = 0,
3074 .idle_enabled = 0,
3075 .suspend_enabled = 0,
3076#endif /*CONFIG_MSM_STANDALONE_POWER_COLLAPSE*/
3077 .latency = 500,
3078 .residency = 6000,
3079 },
3080 [MSM_PM_SLEEP_MODE_RAMP_DOWN_AND_WAIT_FOR_INTERRUPT] = {
3081 .idle_supported = 1,
3082 .suspend_supported = 1,
3083 .idle_enabled = 0,
3084 .suspend_enabled = 1,
3085 .latency = 443,
3086 .residency = 1098,
3087 },
3088 [MSM_PM_SLEEP_MODE_WAIT_FOR_INTERRUPT] = {
3089 .idle_supported = 1,
3090 .suspend_supported = 1,
3091 .idle_enabled = 1,
3092 .suspend_enabled = 1,
3093 .latency = 2,
3094 .residency = 0,
3095 },
3096};
3097
3098static struct resource qsd_spi_resources[] = {
3099 {
3100 .name = "spi_irq_in",
3101 .start = INT_SPI_INPUT,
3102 .end = INT_SPI_INPUT,
3103 .flags = IORESOURCE_IRQ,
3104 },
3105 {
3106 .name = "spi_irq_out",
3107 .start = INT_SPI_OUTPUT,
3108 .end = INT_SPI_OUTPUT,
3109 .flags = IORESOURCE_IRQ,
3110 },
3111 {
3112 .name = "spi_irq_err",
3113 .start = INT_SPI_ERROR,
3114 .end = INT_SPI_ERROR,
3115 .flags = IORESOURCE_IRQ,
3116 },
3117 {
3118 .name = "spi_base",
3119 .start = 0xA8000000,
3120 .end = 0xA8000000 + SZ_4K - 1,
3121 .flags = IORESOURCE_MEM,
3122 },
3123 {
3124 .name = "spidm_channels",
3125 .flags = IORESOURCE_DMA,
3126 },
3127 {
3128 .name = "spidm_crci",
3129 .flags = IORESOURCE_DMA,
3130 },
3131};
3132
3133#define AMDH0_BASE_PHYS 0xAC200000
3134#define ADMH0_GP_CTL (ct_adm_base + 0x3D8)
3135static int msm_qsd_spi_dma_config(void)
3136{
3137 void __iomem *ct_adm_base = 0;
3138 u32 spi_mux = 0;
3139 int ret = 0;
3140
3141 ct_adm_base = ioremap(AMDH0_BASE_PHYS, PAGE_SIZE);
3142 if (!ct_adm_base) {
3143 pr_err("%s: Could not remap %x\n", __func__, AMDH0_BASE_PHYS);
3144 return -ENOMEM;
3145 }
3146
3147 spi_mux = (ioread32(ADMH0_GP_CTL) & (0x3 << 12)) >> 12;
3148
3149 qsd_spi_resources[4].start = DMOV_USB_CHAN;
3150 qsd_spi_resources[4].end = DMOV_TSIF_CHAN;
3151
3152 switch (spi_mux) {
3153 case (1):
3154 qsd_spi_resources[5].start = DMOV_HSUART1_RX_CRCI;
3155 qsd_spi_resources[5].end = DMOV_HSUART1_TX_CRCI;
3156 break;
3157 case (2):
3158 qsd_spi_resources[5].start = DMOV_HSUART2_RX_CRCI;
3159 qsd_spi_resources[5].end = DMOV_HSUART2_TX_CRCI;
3160 break;
3161 case (3):
3162 qsd_spi_resources[5].start = DMOV_CE_OUT_CRCI;
3163 qsd_spi_resources[5].end = DMOV_CE_IN_CRCI;
3164 break;
3165 default:
3166 ret = -ENOENT;
3167 }
3168
3169 iounmap(ct_adm_base);
3170
3171 return ret;
3172}
3173
3174static struct platform_device qsd_device_spi = {
3175 .name = "spi_qsd",
3176 .id = 0,
3177 .num_resources = ARRAY_SIZE(qsd_spi_resources),
3178 .resource = qsd_spi_resources,
3179};
3180
3181#ifdef CONFIG_SPI_QSD
3182static struct spi_board_info lcdc_sharp_spi_board_info[] __initdata = {
3183 {
3184 .modalias = "lcdc_sharp_ls038y7dx01",
3185 .mode = SPI_MODE_1,
3186 .bus_num = 0,
3187 .chip_select = 0,
3188 .max_speed_hz = 26331429,
3189 }
3190};
3191static struct spi_board_info lcdc_toshiba_spi_board_info[] __initdata = {
3192 {
3193 .modalias = "lcdc_toshiba_ltm030dd40",
3194 .mode = SPI_MODE_3|SPI_CS_HIGH,
3195 .bus_num = 0,
3196 .chip_select = 0,
3197 .max_speed_hz = 9963243,
3198 }
3199};
3200#endif
3201
3202static struct msm_gpio qsd_spi_gpio_config_data[] = {
3203 { GPIO_CFG(45, 1, GPIO_CFG_INPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "spi_clk" },
3204 { GPIO_CFG(46, 1, GPIO_CFG_INPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "spi_cs0" },
3205 { GPIO_CFG(47, 1, GPIO_CFG_INPUT, GPIO_CFG_NO_PULL, GPIO_CFG_8MA), "spi_mosi" },
3206 { GPIO_CFG(48, 1, GPIO_CFG_INPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "spi_miso" },
3207};
3208
3209static int msm_qsd_spi_gpio_config(void)
3210{
3211 return msm_gpios_request_enable(qsd_spi_gpio_config_data,
3212 ARRAY_SIZE(qsd_spi_gpio_config_data));
3213}
3214
3215static void msm_qsd_spi_gpio_release(void)
3216{
3217 msm_gpios_disable_free(qsd_spi_gpio_config_data,
3218 ARRAY_SIZE(qsd_spi_gpio_config_data));
3219}
3220
3221static struct msm_spi_platform_data qsd_spi_pdata = {
3222 .max_clock_speed = 26331429,
3223 .gpio_config = msm_qsd_spi_gpio_config,
3224 .gpio_release = msm_qsd_spi_gpio_release,
3225 .dma_config = msm_qsd_spi_dma_config,
3226};
3227
3228static void __init msm_qsd_spi_init(void)
3229{
3230 qsd_device_spi.dev.platform_data = &qsd_spi_pdata;
3231}
3232
3233#ifdef CONFIG_USB_EHCI_MSM_72K
3234static void msm_hsusb_vbus_power(unsigned phy_info, int on)
3235{
3236 int rc;
3237 static int vbus_is_on;
3238 struct pm8058_gpio usb_vbus = {
3239 .direction = PM_GPIO_DIR_OUT,
3240 .pull = PM_GPIO_PULL_NO,
3241 .output_buffer = PM_GPIO_OUT_BUF_CMOS,
3242 .output_value = 1,
3243 .vin_sel = 2,
3244 .out_strength = PM_GPIO_STRENGTH_MED,
3245 .function = PM_GPIO_FUNC_NORMAL,
3246 .inv_int_pol = 0,
3247 };
3248
3249 /* If VBUS is already on (or off), do nothing. */
3250 if (unlikely(on == vbus_is_on))
3251 return;
3252
3253 if (on) {
3254 rc = pm8058_gpio_config(36, &usb_vbus);
3255 if (rc) {
3256 pr_err("%s PMIC GPIO 36 write failed\n", __func__);
3257 return;
3258 }
3259 } else {
3260 gpio_set_value_cansleep(PM8058_GPIO_PM_TO_SYS(36), 0);
3261 }
3262
3263 vbus_is_on = on;
3264}
3265
3266static struct msm_usb_host_platform_data msm_usb_host_pdata = {
3267 .phy_info = (USB_PHY_INTEGRATED | USB_PHY_MODEL_45NM),
3268 .vbus_power = msm_hsusb_vbus_power,
3269 .power_budget = 180,
3270};
3271#endif
3272
3273#ifdef CONFIG_USB_MSM_OTG_72K
3274static int hsusb_rpc_connect(int connect)
3275{
3276 if (connect)
3277 return msm_hsusb_rpc_connect();
3278 else
3279 return msm_hsusb_rpc_close();
3280}
3281#endif
3282
3283#ifdef CONFIG_USB_MSM_OTG_72K
3284static struct vreg *vreg_3p3;
3285static int msm_hsusb_ldo_init(int init)
3286{
3287 uint32_t version = 0;
3288 int def_vol = 3400;
3289
3290 version = socinfo_get_version();
3291
3292 if (SOCINFO_VERSION_MAJOR(version) >= 2 &&
3293 SOCINFO_VERSION_MINOR(version) >= 1) {
3294 def_vol = 3075;
3295 pr_debug("%s: default voltage:%d\n", __func__, def_vol);
3296 }
3297
3298 if (init) {
3299 vreg_3p3 = vreg_get(NULL, "usb");
3300 if (IS_ERR(vreg_3p3))
3301 return PTR_ERR(vreg_3p3);
3302 vreg_set_level(vreg_3p3, def_vol);
3303 } else
3304 vreg_put(vreg_3p3);
3305
3306 return 0;
3307}
3308
3309static int msm_hsusb_ldo_enable(int enable)
3310{
3311 static int ldo_status;
3312
3313 if (!vreg_3p3 || IS_ERR(vreg_3p3))
3314 return -ENODEV;
3315
3316 if (ldo_status == enable)
3317 return 0;
3318
3319 ldo_status = enable;
3320
3321 if (enable)
3322 return vreg_enable(vreg_3p3);
3323
3324 return vreg_disable(vreg_3p3);
3325}
3326
3327static int msm_hsusb_ldo_set_voltage(int mV)
3328{
3329 static int cur_voltage = 3400;
3330
3331 if (!vreg_3p3 || IS_ERR(vreg_3p3))
3332 return -ENODEV;
3333
3334 if (cur_voltage == mV)
3335 return 0;
3336
3337 cur_voltage = mV;
3338
3339 pr_debug("%s: (%d)\n", __func__, mV);
3340
3341 return vreg_set_level(vreg_3p3, mV);
3342}
3343#endif
3344
3345#ifndef CONFIG_USB_EHCI_MSM_72K
3346static int msm_hsusb_pmic_notif_init(void (*callback)(int online), int init);
3347#endif
3348static struct msm_otg_platform_data msm_otg_pdata = {
3349 .rpc_connect = hsusb_rpc_connect,
3350
3351#ifndef CONFIG_USB_EHCI_MSM_72K
3352 .pmic_vbus_notif_init = msm_hsusb_pmic_notif_init,
3353#else
3354 .vbus_power = msm_hsusb_vbus_power,
3355#endif
3356 .core_clk = 1,
3357 .pemp_level = PRE_EMPHASIS_WITH_20_PERCENT,
3358 .cdr_autoreset = CDR_AUTO_RESET_DISABLE,
3359 .drv_ampl = HS_DRV_AMPLITUDE_DEFAULT,
3360 .se1_gating = SE1_GATING_DISABLE,
3361 .chg_vbus_draw = hsusb_chg_vbus_draw,
3362 .chg_connected = hsusb_chg_connected,
3363 .chg_init = hsusb_chg_init,
3364 .ldo_enable = msm_hsusb_ldo_enable,
3365 .ldo_init = msm_hsusb_ldo_init,
3366 .ldo_set_voltage = msm_hsusb_ldo_set_voltage,
3367};
3368
3369#ifdef CONFIG_USB_GADGET
3370static struct msm_hsusb_gadget_platform_data msm_gadget_pdata = {
3371 .is_phy_status_timer_on = 1,
3372};
3373#endif
3374#ifndef CONFIG_USB_EHCI_MSM_72K
3375typedef void (*notify_vbus_state) (int);
3376notify_vbus_state notify_vbus_state_func_ptr;
3377int vbus_on_irq;
3378static irqreturn_t pmic_vbus_on_irq(int irq, void *data)
3379{
3380 pr_info("%s: vbus notification from pmic\n", __func__);
3381
3382 (*notify_vbus_state_func_ptr) (1);
3383
3384 return IRQ_HANDLED;
3385}
3386static int msm_hsusb_pmic_notif_init(void (*callback)(int online), int init)
3387{
3388 int ret;
3389
3390 if (init) {
3391 if (!callback)
3392 return -ENODEV;
3393
3394 notify_vbus_state_func_ptr = callback;
3395 vbus_on_irq = platform_get_irq_byname(&msm_device_otg,
3396 "vbus_on");
3397 if (vbus_on_irq <= 0) {
3398 pr_err("%s: unable to get vbus on irq\n", __func__);
3399 return -ENODEV;
3400 }
3401
3402 ret = request_any_context_irq(vbus_on_irq, pmic_vbus_on_irq,
3403 IRQF_TRIGGER_RISING, "msm_otg_vbus_on", NULL);
3404 if (ret < 0) {
3405 pr_info("%s: request_irq for vbus_on"
3406 "interrupt failed\n", __func__);
3407 return ret;
3408 }
3409 msm_otg_pdata.pmic_vbus_irq = vbus_on_irq;
3410 return 0;
3411 } else {
3412 free_irq(vbus_on_irq, 0);
3413 notify_vbus_state_func_ptr = NULL;
3414 return 0;
3415 }
3416}
3417#endif
3418
3419static struct android_pmem_platform_data android_pmem_pdata = {
3420 .name = "pmem",
3421 .allocator_type = PMEM_ALLOCATORTYPE_ALLORNOTHING,
3422 .cached = 1,
3423 .memory_type = MEMTYPE_EBI0,
3424};
3425
3426static struct platform_device android_pmem_device = {
3427 .name = "android_pmem",
3428 .id = 0,
3429 .dev = { .platform_data = &android_pmem_pdata },
3430};
3431
3432#ifndef CONFIG_SPI_QSD
3433static int lcdc_gpio_array_num[] = {
3434 45, /* spi_clk */
3435 46, /* spi_cs */
3436 47, /* spi_mosi */
3437 48, /* spi_miso */
3438 };
3439
3440static struct msm_gpio lcdc_gpio_config_data[] = {
3441 { GPIO_CFG(45, 0, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "spi_clk" },
3442 { GPIO_CFG(46, 0, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "spi_cs0" },
3443 { GPIO_CFG(47, 0, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "spi_mosi" },
3444 { GPIO_CFG(48, 0, GPIO_CFG_INPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "spi_miso" },
3445};
3446
3447static void lcdc_config_gpios(int enable)
3448{
3449 if (enable) {
3450 msm_gpios_request_enable(lcdc_gpio_config_data,
3451 ARRAY_SIZE(
3452 lcdc_gpio_config_data));
3453 } else
3454 msm_gpios_disable_free(lcdc_gpio_config_data,
3455 ARRAY_SIZE(
3456 lcdc_gpio_config_data));
3457}
3458#endif
3459
3460static struct msm_panel_common_pdata lcdc_sharp_panel_data = {
3461#ifndef CONFIG_SPI_QSD
3462 .panel_config_gpio = lcdc_config_gpios,
3463 .gpio_num = lcdc_gpio_array_num,
3464#endif
3465 .gpio = 2, /* LPG PMIC_GPIO26 channel number */
3466};
3467
3468static struct platform_device lcdc_sharp_panel_device = {
3469 .name = "lcdc_sharp_wvga",
3470 .id = 0,
3471 .dev = {
3472 .platform_data = &lcdc_sharp_panel_data,
3473 }
3474};
3475
3476static struct msm_gpio dtv_panel_irq_gpios[] = {
3477 { GPIO_CFG(18, 0, GPIO_CFG_INPUT, GPIO_CFG_NO_PULL, GPIO_CFG_4MA),
3478 "hdmi_int" },
3479};
3480
3481static struct msm_gpio dtv_panel_gpios[] = {
3482 { GPIO_CFG(120, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_4MA), "wca_mclk" },
3483 { GPIO_CFG(121, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_4MA), "wca_sd0" },
3484 { GPIO_CFG(122, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_4MA), "wca_sd1" },
3485 { GPIO_CFG(123, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_4MA), "wca_sd2" },
3486 { GPIO_CFG(124, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_8MA), "dtv_pclk" },
3487 { GPIO_CFG(125, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_4MA), "dtv_en" },
3488 { GPIO_CFG(126, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_4MA), "dtv_vsync" },
3489 { GPIO_CFG(127, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_4MA), "dtv_hsync" },
3490 { GPIO_CFG(128, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_4MA), "dtv_data0" },
3491 { GPIO_CFG(129, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_4MA), "dtv_data1" },
3492 { GPIO_CFG(130, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_4MA), "dtv_data2" },
3493 { GPIO_CFG(131, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_4MA), "dtv_data3" },
3494 { GPIO_CFG(132, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_4MA), "dtv_data4" },
3495 { GPIO_CFG(160, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_4MA), "dtv_data5" },
3496 { GPIO_CFG(161, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_4MA), "dtv_data6" },
3497 { GPIO_CFG(162, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_4MA), "dtv_data7" },
3498 { GPIO_CFG(163, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_4MA), "dtv_data8" },
3499 { GPIO_CFG(164, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_4MA), "dtv_data9" },
3500 { GPIO_CFG(165, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_4MA), "dtv_dat10" },
3501 { GPIO_CFG(166, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_4MA), "dtv_dat11" },
3502 { GPIO_CFG(167, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_4MA), "dtv_dat12" },
3503 { GPIO_CFG(168, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_4MA), "dtv_dat13" },
3504 { GPIO_CFG(169, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_4MA), "dtv_dat14" },
3505 { GPIO_CFG(170, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_4MA), "dtv_dat15" },
3506 { GPIO_CFG(171, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_4MA), "dtv_dat16" },
3507 { GPIO_CFG(172, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_4MA), "dtv_dat17" },
3508 { GPIO_CFG(173, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_4MA), "dtv_dat18" },
3509 { GPIO_CFG(174, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_4MA), "dtv_dat19" },
3510 { GPIO_CFG(175, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_4MA), "dtv_dat20" },
3511 { GPIO_CFG(176, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_4MA), "dtv_dat21" },
3512 { GPIO_CFG(177, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_4MA), "dtv_dat22" },
3513 { GPIO_CFG(178, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_4MA), "dtv_dat23" },
3514};
3515
3516
3517#ifdef HDMI_RESET
3518static unsigned dtv_reset_gpio =
3519 GPIO_CFG(37, 0, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA);
3520#endif
3521
3522static int gpio_set(const char *label, const char *name, int level, int on)
3523{
3524 struct vreg *vreg = vreg_get(NULL, label);
3525 int rc;
3526
3527 if (IS_ERR(vreg)) {
3528 rc = PTR_ERR(vreg);
3529 pr_err("%s: vreg %s get failed (%d)\n",
3530 __func__, name, rc);
3531 return rc;
3532 }
3533
3534 rc = vreg_set_level(vreg, level);
3535 if (rc) {
3536 pr_err("%s: vreg %s set level failed (%d)\n",
3537 __func__, name, rc);
3538 return rc;
3539 }
3540
3541 if (on)
3542 rc = vreg_enable(vreg);
3543 else
3544 rc = vreg_disable(vreg);
3545 if (rc)
3546 pr_err("%s: vreg %s enable failed (%d)\n",
3547 __func__, name, rc);
3548 return rc;
3549}
3550
3551#if defined(CONFIG_FB_MSM_HDMI_ADV7520_PANEL) || defined(CONFIG_BOSCH_BMA150)
3552/* there is an i2c address conflict between adv7520 and bma150 sensor after
3553 * power up on fluid. As a solution, the default address of adv7520's packet
3554 * memory is changed as soon as possible
3555 */
3556static int __init fluid_i2c_address_fixup(void)
3557{
3558 unsigned char wBuff[16];
3559 unsigned char rBuff[16];
3560 struct i2c_msg msgs[3];
3561 int res;
3562 int rc = -EINVAL;
3563 struct vreg *vreg_ldo8;
3564 struct i2c_adapter *adapter;
3565
3566 if (machine_is_msm7x30_fluid()) {
3567 adapter = i2c_get_adapter(0);
3568 if (!adapter) {
3569 pr_err("%s: invalid i2c adapter\n", __func__);
3570 return PTR_ERR(adapter);
3571 }
3572
3573 /* turn on LDO8 */
3574 vreg_ldo8 = vreg_get(NULL, "gp7");
3575 if (!vreg_ldo8) {
3576 pr_err("%s: VREG L8 get failed\n", __func__);
3577 goto adapter_put;
3578 }
3579
3580 rc = vreg_set_level(vreg_ldo8, 1800);
3581 if (rc) {
3582 pr_err("%s: VREG L8 set failed\n", __func__);
3583 goto ldo8_put;
3584 }
3585
3586 rc = vreg_enable(vreg_ldo8);
3587 if (rc) {
3588 pr_err("%s: VREG L8 enable failed\n", __func__);
3589 goto ldo8_put;
3590 }
3591
3592 /* change packet memory address to 0x74 */
3593 wBuff[0] = 0x45;
3594 wBuff[1] = 0x74;
3595
3596 msgs[0].addr = ADV7520_I2C_ADDR;
3597 msgs[0].flags = 0;
3598 msgs[0].buf = (unsigned char *) wBuff;
3599 msgs[0].len = 2;
3600
3601 res = i2c_transfer(adapter, msgs, 1);
3602 if (res != 1) {
3603 pr_err("%s: error writing adv7520\n", __func__);
3604 goto ldo8_disable;
3605 }
3606
3607 /* powerdown adv7520 using bit 6 */
3608 /* i2c read first */
3609 wBuff[0] = 0x41;
3610
3611 msgs[0].addr = ADV7520_I2C_ADDR;
3612 msgs[0].flags = 0;
3613 msgs[0].buf = (unsigned char *) wBuff;
3614 msgs[0].len = 1;
3615
3616 msgs[1].addr = ADV7520_I2C_ADDR;
3617 msgs[1].flags = I2C_M_RD;
3618 msgs[1].buf = rBuff;
3619 msgs[1].len = 1;
3620 res = i2c_transfer(adapter, msgs, 2);
3621 if (res != 2) {
3622 pr_err("%s: error reading adv7520\n", __func__);
3623 goto ldo8_disable;
3624 }
3625
3626 /* i2c write back */
3627 wBuff[0] = 0x41;
3628 wBuff[1] = rBuff[0] | 0x40;
3629
3630 msgs[0].addr = ADV7520_I2C_ADDR;
3631 msgs[0].flags = 0;
3632 msgs[0].buf = (unsigned char *) wBuff;
3633 msgs[0].len = 2;
3634
3635 res = i2c_transfer(adapter, msgs, 1);
3636 if (res != 1) {
3637 pr_err("%s: error writing adv7520\n", __func__);
3638 goto ldo8_disable;
3639 }
3640
3641 /* for successful fixup, we release the i2c adapter */
3642 /* but leave ldo8 on so that the adv7520 is not repowered */
3643 i2c_put_adapter(adapter);
3644 pr_info("%s: fluid i2c address conflict resolved\n", __func__);
3645 }
3646 return 0;
3647
3648ldo8_disable:
3649 vreg_disable(vreg_ldo8);
3650ldo8_put:
3651 vreg_put(vreg_ldo8);
3652adapter_put:
3653 i2c_put_adapter(adapter);
3654 return rc;
3655}
3656fs_initcall_sync(fluid_i2c_address_fixup);
3657#endif
3658
3659static int hdmi_comm_power(int on, int show)
3660{
3661 int rc = gpio_set("gp7", "LDO8", 1800, on);
3662 if (rc) {
3663 pr_warning("hdmi_comm_power: LDO8 gpio failed: rc=%d\n", rc);
3664 return rc;
3665 }
3666 rc = gpio_set("gp4", "LDO10", 2600, on);
3667 if (rc)
3668 pr_warning("hdmi_comm_power: LDO10 gpio failed: rc=%d\n", rc);
3669 if (show)
3670 pr_info("%s: i2c comm: %d <LDO8+LDO10>\n", __func__, on);
3671 return rc;
3672}
3673
3674static int hdmi_init_irq(void)
3675{
3676 int rc = msm_gpios_enable(dtv_panel_irq_gpios,
3677 ARRAY_SIZE(dtv_panel_irq_gpios));
3678 if (rc < 0) {
3679 pr_err("%s: gpio enable failed: %d\n", __func__, rc);
3680 return rc;
3681 }
3682 pr_info("%s\n", __func__);
3683
3684 return 0;
3685}
3686
3687static int hdmi_enable_5v(int on)
3688{
3689 int pmic_gpio_hdmi_5v_en ;
3690
3691 if (machine_is_msm8x55_svlte_surf() || machine_is_msm8x55_svlte_ffa() ||
3692 machine_is_msm7x30_fluid())
3693 pmic_gpio_hdmi_5v_en = PMIC_GPIO_HDMI_5V_EN_V2 ;
3694 else
3695 pmic_gpio_hdmi_5v_en = PMIC_GPIO_HDMI_5V_EN_V3 ;
3696
3697 pr_info("%s: %d\n", __func__, on);
3698 if (on) {
3699 int rc;
3700 rc = gpio_request(PM8058_GPIO_PM_TO_SYS(pmic_gpio_hdmi_5v_en),
3701 "hdmi_5V_en");
3702 if (rc) {
3703 pr_err("%s PMIC_GPIO_HDMI_5V_EN gpio_request failed\n",
3704 __func__);
3705 return rc;
3706 }
3707 gpio_set_value_cansleep(
3708 PM8058_GPIO_PM_TO_SYS(pmic_gpio_hdmi_5v_en), 1);
3709 } else {
3710 gpio_set_value_cansleep(
3711 PM8058_GPIO_PM_TO_SYS(pmic_gpio_hdmi_5v_en), 0);
3712 gpio_free(PM8058_GPIO_PM_TO_SYS(pmic_gpio_hdmi_5v_en));
3713 }
3714 return 0;
3715}
3716
3717static int hdmi_core_power(int on, int show)
3718{
3719 if (show)
3720 pr_info("%s: %d <LDO8>\n", __func__, on);
3721 return gpio_set("gp7", "LDO8", 1800, on);
3722}
3723
3724static int hdmi_cec_power(int on)
3725{
3726 pr_info("%s: %d <LDO17>\n", __func__, on);
3727 return gpio_set("gp11", "LDO17", 2600, on);
3728}
3729
3730static bool hdmi_check_hdcp_hw_support(void)
3731{
3732 if (machine_is_msm7x30_fluid())
3733 return false;
3734 else
3735 return true;
3736}
3737
3738static int dtv_panel_power(int on)
3739{
3740 int flag_on = !!on;
3741 static int dtv_power_save_on;
3742 int rc;
3743
3744 if (dtv_power_save_on == flag_on)
3745 return 0;
3746
3747 dtv_power_save_on = flag_on;
3748 pr_info("%s: %d\n", __func__, on);
3749
3750#ifdef HDMI_RESET
3751 if (on) {
3752 /* reset Toshiba WeGA chip -- toggle reset pin -- gpio_180 */
3753 rc = gpio_tlmm_config(dtv_reset_gpio, GPIO_CFG_ENABLE);
3754 if (rc) {
3755 pr_err("%s: gpio_tlmm_config(%#x)=%d\n",
3756 __func__, dtv_reset_gpio, rc);
3757 return rc;
3758 }
3759
3760 /* bring reset line low to hold reset*/
3761 gpio_set_value(37, 0);
3762 }
3763#endif
3764
3765 if (on) {
3766 rc = msm_gpios_enable(dtv_panel_gpios,
3767 ARRAY_SIZE(dtv_panel_gpios));
3768 if (rc < 0) {
3769 printk(KERN_ERR "%s: gpio enable failed: %d\n",
3770 __func__, rc);
3771 return rc;
3772 }
3773 } else {
3774 rc = msm_gpios_disable(dtv_panel_gpios,
3775 ARRAY_SIZE(dtv_panel_gpios));
3776 if (rc < 0) {
3777 printk(KERN_ERR "%s: gpio disable failed: %d\n",
3778 __func__, rc);
3779 return rc;
3780 }
3781 }
3782
3783 mdelay(5); /* ensure power is stable */
3784
3785#ifdef HDMI_RESET
3786 if (on) {
3787 gpio_set_value(37, 1); /* bring reset line high */
3788 mdelay(10); /* 10 msec before IO can be accessed */
3789 }
3790#endif
3791
3792 return rc;
3793}
3794
3795static struct lcdc_platform_data dtv_pdata = {
3796 .lcdc_power_save = dtv_panel_power,
3797};
3798
3799static struct msm_serial_hs_platform_data msm_uart_dm1_pdata = {
3800 .inject_rx_on_wakeup = 1,
3801 .rx_to_inject = 0xFD,
3802};
3803
3804static struct resource msm_fb_resources[] = {
3805 {
3806 .flags = IORESOURCE_DMA,
3807 }
3808};
3809
3810static int msm_fb_detect_panel(const char *name)
3811{
3812 if (machine_is_msm7x30_fluid()) {
3813 if (!strcmp(name, "lcdc_sharp_wvga_pt"))
3814 return 0;
3815 } else {
3816 if (!strncmp(name, "mddi_toshiba_wvga_pt", 20))
3817 return -EPERM;
3818 else if (!strncmp(name, "lcdc_toshiba_wvga_pt", 20))
3819 return 0;
3820 else if (!strcmp(name, "mddi_orise"))
3821 return -EPERM;
3822 else if (!strcmp(name, "mddi_quickvx"))
3823 return -EPERM;
3824 }
3825 return -ENODEV;
3826}
3827
3828static struct msm_fb_platform_data msm_fb_pdata = {
3829 .detect_client = msm_fb_detect_panel,
3830 .mddi_prescan = 1,
3831};
3832
3833static struct platform_device msm_fb_device = {
3834 .name = "msm_fb",
3835 .id = 0,
3836 .num_resources = ARRAY_SIZE(msm_fb_resources),
3837 .resource = msm_fb_resources,
3838 .dev = {
3839 .platform_data = &msm_fb_pdata,
3840 }
3841};
3842
3843static struct platform_device msm_migrate_pages_device = {
3844 .name = "msm_migrate_pages",
3845 .id = -1,
3846};
3847
3848static struct android_pmem_platform_data android_pmem_adsp_pdata = {
3849 .name = "pmem_adsp",
3850 .allocator_type = PMEM_ALLOCATORTYPE_BITMAP,
3851 .cached = 0,
3852 .memory_type = MEMTYPE_EBI0,
3853};
3854
3855static struct android_pmem_platform_data android_pmem_audio_pdata = {
3856 .name = "pmem_audio",
3857 .allocator_type = PMEM_ALLOCATORTYPE_BITMAP,
3858 .cached = 0,
3859 .memory_type = MEMTYPE_EBI0,
3860};
3861
3862static struct platform_device android_pmem_adsp_device = {
3863 .name = "android_pmem",
3864 .id = 2,
3865 .dev = { .platform_data = &android_pmem_adsp_pdata },
3866};
3867
3868static struct platform_device android_pmem_audio_device = {
3869 .name = "android_pmem",
3870 .id = 4,
3871 .dev = { .platform_data = &android_pmem_audio_pdata },
3872};
3873
3874#if defined(CONFIG_CRYPTO_DEV_QCRYPTO) || \
3875 defined(CONFIG_CRYPTO_DEV_QCRYPTO_MODULE) || \
3876 defined(CONFIG_CRYPTO_DEV_QCEDEV) || \
3877 defined(CONFIG_CRYPTO_DEV_QCEDEV_MODULE)
3878
3879#define QCE_SIZE 0x10000
3880#define QCE_0_BASE 0xA8400000
3881
3882#define QCE_HW_KEY_SUPPORT 1
3883#define QCE_SHA_HMAC_SUPPORT 0
3884#define QCE_SHARE_CE_RESOURCE 0
3885#define QCE_CE_SHARED 0
3886
3887static struct resource qcrypto_resources[] = {
3888 [0] = {
3889 .start = QCE_0_BASE,
3890 .end = QCE_0_BASE + QCE_SIZE - 1,
3891 .flags = IORESOURCE_MEM,
3892 },
3893 [1] = {
3894 .name = "crypto_channels",
3895 .start = DMOV_CE_IN_CHAN,
3896 .end = DMOV_CE_OUT_CHAN,
3897 .flags = IORESOURCE_DMA,
3898 },
3899 [2] = {
3900 .name = "crypto_crci_in",
3901 .start = DMOV_CE_IN_CRCI,
3902 .end = DMOV_CE_IN_CRCI,
3903 .flags = IORESOURCE_DMA,
3904 },
3905 [3] = {
3906 .name = "crypto_crci_out",
3907 .start = DMOV_CE_OUT_CRCI,
3908 .end = DMOV_CE_OUT_CRCI,
3909 .flags = IORESOURCE_DMA,
3910 },
3911 [4] = {
3912 .name = "crypto_crci_hash",
3913 .start = DMOV_CE_HASH_CRCI,
3914 .end = DMOV_CE_HASH_CRCI,
3915 .flags = IORESOURCE_DMA,
3916 },
3917};
3918
3919static struct resource qcedev_resources[] = {
3920 [0] = {
3921 .start = QCE_0_BASE,
3922 .end = QCE_0_BASE + QCE_SIZE - 1,
3923 .flags = IORESOURCE_MEM,
3924 },
3925 [1] = {
3926 .name = "crypto_channels",
3927 .start = DMOV_CE_IN_CHAN,
3928 .end = DMOV_CE_OUT_CHAN,
3929 .flags = IORESOURCE_DMA,
3930 },
3931 [2] = {
3932 .name = "crypto_crci_in",
3933 .start = DMOV_CE_IN_CRCI,
3934 .end = DMOV_CE_IN_CRCI,
3935 .flags = IORESOURCE_DMA,
3936 },
3937 [3] = {
3938 .name = "crypto_crci_out",
3939 .start = DMOV_CE_OUT_CRCI,
3940 .end = DMOV_CE_OUT_CRCI,
3941 .flags = IORESOURCE_DMA,
3942 },
3943 [4] = {
3944 .name = "crypto_crci_hash",
3945 .start = DMOV_CE_HASH_CRCI,
3946 .end = DMOV_CE_HASH_CRCI,
3947 .flags = IORESOURCE_DMA,
3948 },
3949};
3950
3951#endif
3952
3953#if defined(CONFIG_CRYPTO_DEV_QCRYPTO) || \
3954 defined(CONFIG_CRYPTO_DEV_QCRYPTO_MODULE)
3955
3956static struct msm_ce_hw_support qcrypto_ce_hw_suppport = {
3957 .ce_shared = QCE_CE_SHARED,
3958 .shared_ce_resource = QCE_SHARE_CE_RESOURCE,
3959 .hw_key_support = QCE_HW_KEY_SUPPORT,
3960 .sha_hmac = QCE_SHA_HMAC_SUPPORT,
3961};
3962
3963static struct platform_device qcrypto_device = {
3964 .name = "qcrypto",
3965 .id = 0,
3966 .num_resources = ARRAY_SIZE(qcrypto_resources),
3967 .resource = qcrypto_resources,
3968 .dev = {
3969 .coherent_dma_mask = DMA_BIT_MASK(32),
3970 .platform_data = &qcrypto_ce_hw_suppport,
3971 },
3972};
3973#endif
3974
3975#if defined(CONFIG_CRYPTO_DEV_QCEDEV) || \
3976 defined(CONFIG_CRYPTO_DEV_QCEDEV_MODULE)
3977
3978static struct msm_ce_hw_support qcedev_ce_hw_suppport = {
3979 .ce_shared = QCE_CE_SHARED,
3980 .shared_ce_resource = QCE_SHARE_CE_RESOURCE,
3981 .hw_key_support = QCE_HW_KEY_SUPPORT,
3982 .sha_hmac = QCE_SHA_HMAC_SUPPORT,
3983};
3984static struct platform_device qcedev_device = {
3985 .name = "qce",
3986 .id = 0,
3987 .num_resources = ARRAY_SIZE(qcedev_resources),
3988 .resource = qcedev_resources,
3989 .dev = {
3990 .coherent_dma_mask = DMA_BIT_MASK(32),
3991 .platform_data = &qcedev_ce_hw_suppport,
3992 },
3993};
3994#endif
3995
3996static int mddi_toshiba_pmic_bl(int level)
3997{
3998 int ret = -EPERM;
3999
4000 ret = pmic_set_led_intensity(LED_LCD, level);
4001
4002 if (ret)
4003 printk(KERN_WARNING "%s: can't set lcd backlight!\n",
4004 __func__);
4005 return ret;
4006}
4007
4008static struct msm_panel_common_pdata mddi_toshiba_pdata = {
4009 .pmic_backlight = mddi_toshiba_pmic_bl,
4010};
4011
4012static struct platform_device mddi_toshiba_device = {
4013 .name = "mddi_toshiba",
4014 .id = 0,
4015 .dev = {
4016 .platform_data = &mddi_toshiba_pdata,
4017 }
4018};
4019
4020static unsigned wega_reset_gpio =
4021 GPIO_CFG(180, 0, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA);
4022
4023static struct msm_gpio fluid_vee_reset_gpio[] = {
4024 { GPIO_CFG(20, 0, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "vee_reset" },
4025};
4026
4027static unsigned char quickvx_mddi_client = 1, other_mddi_client = 1;
4028static unsigned char quickvx_ldo_enabled;
4029
4030static unsigned quickvx_vlp_gpio =
4031 GPIO_CFG(97, 0, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA);
4032
4033static struct pm8058_gpio pmic_quickvx_clk_gpio = {
4034 .direction = PM_GPIO_DIR_OUT,
4035 .output_buffer = PM_GPIO_OUT_BUF_CMOS,
4036 .output_value = 1,
4037 .pull = PM_GPIO_PULL_NO,
4038 .vin_sel = PM_GPIO_VIN_S3,
4039 .out_strength = PM_GPIO_STRENGTH_HIGH,
4040 .function = PM_GPIO_FUNC_2,
4041};
4042
4043static int display_common_power(int on)
4044{
4045 int rc = 0, flag_on = !!on;
4046 static int display_common_power_save_on;
4047 struct vreg *vreg_ldo12, *vreg_ldo15 = NULL, *vreg_ldo6;
4048 struct vreg *vreg_ldo20, *vreg_ldo16, *vreg_ldo8 = NULL;
4049
4050 if (display_common_power_save_on == flag_on)
4051 return 0;
4052
4053 display_common_power_save_on = flag_on;
4054
4055 if (on) {
4056 /* reset Toshiba WeGA chip -- toggle reset pin -- gpio_180 */
4057 rc = gpio_tlmm_config(wega_reset_gpio, GPIO_CFG_ENABLE);
4058 if (rc) {
4059 pr_err("%s: gpio_tlmm_config(%#x)=%d\n",
4060 __func__, wega_reset_gpio, rc);
4061 return rc;
4062 }
4063
4064 /* bring reset line low to hold reset*/
4065 gpio_set_value(180, 0);
4066
4067 if (quickvx_mddi_client) {
4068 /* QuickVX chip -- VLP pin -- gpio 97 */
4069 rc = gpio_tlmm_config(quickvx_vlp_gpio,
4070 GPIO_CFG_ENABLE);
4071 if (rc) {
4072 pr_err("%s: gpio_tlmm_config(%#x)=%d\n",
4073 __func__, quickvx_vlp_gpio, rc);
4074 return rc;
4075 }
4076
4077 /* bring QuickVX VLP line low */
4078 gpio_set_value(97, 0);
4079
4080 rc = pm8058_gpio_config(PMIC_GPIO_QUICKVX_CLK,
4081 &pmic_quickvx_clk_gpio);
4082 if (rc) {
4083 pr_err("%s: pm8058_gpio_config(%#x)=%d\n",
4084 __func__, PMIC_GPIO_QUICKVX_CLK + 1,
4085 rc);
4086 return rc;
4087 }
4088
4089 gpio_set_value_cansleep(PM8058_GPIO_PM_TO_SYS(
4090 PMIC_GPIO_QUICKVX_CLK), 0);
4091 }
4092 }
4093
4094 /* Toshiba WeGA power -- has 3 power source */
4095 /* 1.5V -- LDO20*/
4096 vreg_ldo20 = vreg_get(NULL, "gp13");
4097
4098 if (IS_ERR(vreg_ldo20)) {
4099 rc = PTR_ERR(vreg_ldo20);
4100 pr_err("%s: gp13 vreg get failed (%d)\n",
4101 __func__, rc);
4102 return rc;
4103 }
4104
4105 /* 1.8V -- LDO12 */
4106 vreg_ldo12 = vreg_get(NULL, "gp9");
4107
4108 if (IS_ERR(vreg_ldo12)) {
4109 rc = PTR_ERR(vreg_ldo12);
4110 pr_err("%s: gp9 vreg get failed (%d)\n",
4111 __func__, rc);
4112 return rc;
4113 }
4114
4115 /* 2.6V -- LDO16 */
4116 vreg_ldo16 = vreg_get(NULL, "gp10");
4117
4118 if (IS_ERR(vreg_ldo16)) {
4119 rc = PTR_ERR(vreg_ldo16);
4120 pr_err("%s: gp10 vreg get failed (%d)\n",
4121 __func__, rc);
4122 return rc;
4123 }
4124
4125 /* 3.075V -- LDO6 */
4126 vreg_ldo6 = vreg_get(NULL, "usb");
4127
4128 if (IS_ERR(vreg_ldo6)) {
4129 rc = PTR_ERR(vreg_ldo6);
4130 pr_err("%s: usb vreg get failed (%d)\n",
4131 __func__, rc);
4132 return rc;
4133 }
4134
4135 if (machine_is_msm7x30_fluid()) {
4136 /* 1.8V -- LDO8 */
4137 vreg_ldo8 = vreg_get(NULL, "gp7");
4138
4139 if (IS_ERR(vreg_ldo8)) {
4140 rc = PTR_ERR(vreg_ldo8);
4141 pr_err("%s: gp7 vreg get failed (%d)\n",
4142 __func__, rc);
4143 return rc;
4144 }
4145 } else {
4146 /* lcd panel power */
4147 /* 3.1V -- LDO15 */
4148 vreg_ldo15 = vreg_get(NULL, "gp6");
4149
4150 if (IS_ERR(vreg_ldo15)) {
4151 rc = PTR_ERR(vreg_ldo15);
4152 pr_err("%s: gp6 vreg get failed (%d)\n",
4153 __func__, rc);
4154 return rc;
4155 }
4156 }
4157
4158 /* For QuickLogic chip, LDO20 requires 1.8V */
4159 /* Toshiba chip requires 1.5V, but can tolerate 1.8V since max is 3V */
4160 if (quickvx_mddi_client)
4161 rc = vreg_set_level(vreg_ldo20, 1800);
4162 else
4163 rc = vreg_set_level(vreg_ldo20, 1500);
4164 if (rc) {
4165 pr_err("%s: vreg LDO20 set level failed (%d)\n",
4166 __func__, rc);
4167 return rc;
4168 }
4169
4170 rc = vreg_set_level(vreg_ldo12, 1800);
4171 if (rc) {
4172 pr_err("%s: vreg LDO12 set level failed (%d)\n",
4173 __func__, rc);
4174 return rc;
4175 }
4176
4177 if (other_mddi_client) {
4178 rc = vreg_set_level(vreg_ldo16, 2600);
4179 if (rc) {
4180 pr_err("%s: vreg LDO16 set level failed (%d)\n",
4181 __func__, rc);
4182 return rc;
4183 }
4184 }
4185
4186 if (quickvx_mddi_client) {
4187 rc = vreg_set_level(vreg_ldo6, 3075);
4188 if (rc) {
4189 pr_err("%s: vreg LDO6 set level failed (%d)\n",
4190 __func__, rc);
4191 return rc;
4192 }
4193 }
4194
4195 if (machine_is_msm7x30_fluid()) {
4196 rc = vreg_set_level(vreg_ldo8, 1800);
4197 if (rc) {
4198 pr_err("%s: vreg LDO8 set level failed (%d)\n",
4199 __func__, rc);
4200 return rc;
4201 }
4202 } else {
4203 rc = vreg_set_level(vreg_ldo15, 3100);
4204 if (rc) {
4205 pr_err("%s: vreg LDO15 set level failed (%d)\n",
4206 __func__, rc);
4207 return rc;
4208 }
4209 }
4210
4211 if (on) {
4212 rc = vreg_enable(vreg_ldo20);
4213 if (rc) {
4214 pr_err("%s: LDO20 vreg enable failed (%d)\n",
4215 __func__, rc);
4216 return rc;
4217 }
4218
4219 rc = vreg_enable(vreg_ldo12);
4220 if (rc) {
4221 pr_err("%s: LDO12 vreg enable failed (%d)\n",
4222 __func__, rc);
4223 return rc;
4224 }
4225
4226 if (other_mddi_client) {
4227 rc = vreg_enable(vreg_ldo16);
4228 if (rc) {
4229 pr_err("%s: LDO16 vreg enable failed (%d)\n",
4230 __func__, rc);
4231 return rc;
4232 }
4233 }
4234
4235 if (quickvx_mddi_client && quickvx_ldo_enabled) {
4236 /* Disable LDO6 during display ON */
4237 rc = vreg_disable(vreg_ldo6);
4238 if (rc) {
4239 pr_err("%s: LDO6 vreg disable failed (%d)\n",
4240 __func__, rc);
4241 return rc;
4242 }
4243 quickvx_ldo_enabled = 0;
4244 }
4245
4246 if (machine_is_msm7x30_fluid()) {
4247 rc = vreg_enable(vreg_ldo8);
4248 if (rc) {
4249 pr_err("%s: LDO8 vreg enable failed (%d)\n",
4250 __func__, rc);
4251 return rc;
4252 }
4253 } else {
4254 rc = vreg_enable(vreg_ldo15);
4255 if (rc) {
4256 pr_err("%s: LDO15 vreg enable failed (%d)\n",
4257 __func__, rc);
4258 return rc;
4259 }
4260 }
4261
4262 mdelay(5); /* ensure power is stable */
4263
4264 if (machine_is_msm7x30_fluid()) {
4265 rc = msm_gpios_request_enable(fluid_vee_reset_gpio,
4266 ARRAY_SIZE(fluid_vee_reset_gpio));
4267 if (rc)
4268 pr_err("%s gpio_request_enable failed rc=%d\n",
4269 __func__, rc);
4270 else {
4271 /* assert vee reset_n */
4272 gpio_set_value(20, 1);
4273 gpio_set_value(20, 0);
4274 mdelay(1);
4275 gpio_set_value(20, 1);
4276 }
4277 }
4278
4279 gpio_set_value(180, 1); /* bring reset line high */
4280 mdelay(10); /* 10 msec before IO can be accessed */
4281
4282 if (quickvx_mddi_client) {
4283 gpio_set_value(97, 1);
4284 msleep(2);
4285 gpio_set_value_cansleep(PM8058_GPIO_PM_TO_SYS(
4286 PMIC_GPIO_QUICKVX_CLK), 1);
4287 msleep(2);
4288 }
4289
4290 rc = pmapp_display_clock_config(1);
4291 if (rc) {
4292 pr_err("%s pmapp_display_clock_config rc=%d\n",
4293 __func__, rc);
4294 return rc;
4295 }
4296
4297 } else {
4298 rc = vreg_disable(vreg_ldo20);
4299 if (rc) {
4300 pr_err("%s: LDO20 vreg disable failed (%d)\n",
4301 __func__, rc);
4302 return rc;
4303 }
4304
4305
4306 if (other_mddi_client) {
4307 rc = vreg_disable(vreg_ldo16);
4308 if (rc) {
4309 pr_err("%s: LDO16 vreg disable failed (%d)\n",
4310 __func__, rc);
4311 return rc;
4312 }
4313 }
4314
4315 if (quickvx_mddi_client && !quickvx_ldo_enabled) {
4316 /* Enable LDO6 during display OFF for
4317 Quicklogic chip to sleep with data retention */
4318 rc = vreg_enable(vreg_ldo6);
4319 if (rc) {
4320 pr_err("%s: LDO6 vreg enable failed (%d)\n",
4321 __func__, rc);
4322 return rc;
4323 }
4324 quickvx_ldo_enabled = 1;
4325 }
4326
4327 gpio_set_value(180, 0); /* bring reset line low */
4328
4329 if (quickvx_mddi_client) {
4330 gpio_set_value(97, 0);
4331 gpio_set_value_cansleep(PM8058_GPIO_PM_TO_SYS(
4332 PMIC_GPIO_QUICKVX_CLK), 0);
4333 }
4334
4335 if (machine_is_msm7x30_fluid()) {
4336 rc = vreg_disable(vreg_ldo8);
4337 if (rc) {
4338 pr_err("%s: LDO8 vreg disable failed (%d)\n",
4339 __func__, rc);
4340 return rc;
4341 }
4342 } else {
4343 rc = vreg_disable(vreg_ldo15);
4344 if (rc) {
4345 pr_err("%s: LDO15 vreg disable failed (%d)\n",
4346 __func__, rc);
4347 return rc;
4348 }
4349 }
4350
4351 mdelay(5); /* ensure power is stable */
4352
4353 rc = vreg_disable(vreg_ldo12);
4354 if (rc) {
4355 pr_err("%s: LDO12 vreg disable failed (%d)\n",
4356 __func__, rc);
4357 return rc;
4358 }
4359
4360 if (machine_is_msm7x30_fluid()) {
4361 msm_gpios_disable_free(fluid_vee_reset_gpio,
4362 ARRAY_SIZE(fluid_vee_reset_gpio));
4363 }
4364
4365 rc = pmapp_display_clock_config(0);
4366 if (rc) {
4367 pr_err("%s pmapp_display_clock_config rc=%d\n",
4368 __func__, rc);
4369 return rc;
4370 }
4371 }
4372
4373 return rc;
4374}
4375
4376static int msm_fb_mddi_sel_clk(u32 *clk_rate)
4377{
4378 *clk_rate *= 2;
4379 return 0;
4380}
4381
4382static int msm_fb_mddi_client_power(u32 client_id)
4383{
4384 struct vreg *vreg_ldo20, *vreg_ldo16;
4385 int rc;
4386
4387 printk(KERN_NOTICE "\n client_id = 0x%x", client_id);
4388 /* Check if it is Quicklogic client */
4389 if (client_id == 0xc5835800) {
4390 printk(KERN_NOTICE "\n Quicklogic MDDI client");
4391 other_mddi_client = 0;
4392 vreg_ldo16 = vreg_get(NULL, "gp10");
4393
4394 if (IS_ERR(vreg_ldo16)) {
4395 rc = PTR_ERR(vreg_ldo16);
4396 pr_err("%s: gp10 vreg get failed (%d)\n",
4397 __func__, rc);
4398 return rc;
4399 }
4400
4401 rc = vreg_disable(vreg_ldo16);
4402 if (rc) {
4403 pr_err("%s: LDO16 vreg enable failed (%d)\n",
4404 __func__, rc);
4405 return rc;
4406 }
4407 } else {
4408 printk(KERN_NOTICE "\n Non-Quicklogic MDDI client");
4409 quickvx_mddi_client = 0;
4410 gpio_set_value(97, 0);
4411 gpio_set_value_cansleep(PM8058_GPIO_PM_TO_SYS(
4412 PMIC_GPIO_QUICKVX_CLK), 0);
4413
4414 vreg_ldo20 = vreg_get(NULL, "gp13");
4415
4416 if (IS_ERR(vreg_ldo20)) {
4417 rc = PTR_ERR(vreg_ldo20);
4418 pr_err("%s: gp13 vreg get failed (%d)\n",
4419 __func__, rc);
4420 return rc;
4421 }
4422 rc = vreg_set_level(vreg_ldo20, 1500);
4423 if (rc) {
4424 pr_err("%s: vreg LDO20 set level failed (%d)\n",
4425 __func__, rc);
4426 return rc;
4427 }
4428 }
4429 return 0;
4430}
4431
4432static struct mddi_platform_data mddi_pdata = {
4433 .mddi_power_save = display_common_power,
4434 .mddi_sel_clk = msm_fb_mddi_sel_clk,
4435 .mddi_client_power = msm_fb_mddi_client_power,
4436};
4437
4438int mdp_core_clk_rate_table[] = {
4439 122880000,
4440 122880000,
4441 122880000,
4442 192000000,
4443};
4444
4445static struct msm_panel_common_pdata mdp_pdata = {
4446 .hw_revision_addr = 0xac001270,
4447 .gpio = 30,
4448 .mdp_core_clk_rate = 122880000,
4449 .mdp_core_clk_table = mdp_core_clk_rate_table,
4450 .num_mdp_clk = ARRAY_SIZE(mdp_core_clk_rate_table),
Ravishangar Kalyanam07ef7882011-08-09 15:50:48 -07004451 .mdp_rev = MDP_REV_40,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004452};
4453
4454static int lcd_panel_spi_gpio_num[] = {
4455 45, /* spi_clk */
4456 46, /* spi_cs */
4457 47, /* spi_mosi */
4458 48, /* spi_miso */
4459 };
4460
4461static struct msm_gpio lcd_panel_gpios[] = {
4462/* Workaround, since HDMI_INT is using the same GPIO line (18), and is used as
4463 * input. if there is a hardware revision; we should reassign this GPIO to a
4464 * new open line; and removing it will just ensure that this will be missed in
4465 * the future.
4466 { GPIO_CFG(18, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "lcdc_grn0" },
4467 */
4468 { GPIO_CFG(19, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "lcdc_grn1" },
4469 { GPIO_CFG(20, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "lcdc_blu0" },
4470 { GPIO_CFG(21, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "lcdc_blu1" },
4471 { GPIO_CFG(22, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "lcdc_blu2" },
4472 { GPIO_CFG(23, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "lcdc_red0" },
4473 { GPIO_CFG(24, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "lcdc_red1" },
4474 { GPIO_CFG(25, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "lcdc_red2" },
4475#ifndef CONFIG_SPI_QSD
4476 { GPIO_CFG(45, 0, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "spi_clk" },
4477 { GPIO_CFG(46, 0, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "spi_cs0" },
4478 { GPIO_CFG(47, 0, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "spi_mosi" },
4479 { GPIO_CFG(48, 0, GPIO_CFG_INPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "spi_miso" },
4480#endif
4481 { GPIO_CFG(90, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "lcdc_pclk" },
4482 { GPIO_CFG(91, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "lcdc_en" },
4483 { GPIO_CFG(92, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "lcdc_vsync" },
4484 { GPIO_CFG(93, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "lcdc_hsync" },
4485 { GPIO_CFG(94, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "lcdc_grn2" },
4486 { GPIO_CFG(95, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "lcdc_grn3" },
4487 { GPIO_CFG(96, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "lcdc_grn4" },
4488 { GPIO_CFG(97, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "lcdc_grn5" },
4489 { GPIO_CFG(98, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "lcdc_grn6" },
4490 { GPIO_CFG(99, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "lcdc_grn7" },
4491 { GPIO_CFG(100, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "lcdc_blu3" },
4492 { GPIO_CFG(101, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "lcdc_blu4" },
4493 { GPIO_CFG(102, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "lcdc_blu5" },
4494 { GPIO_CFG(103, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "lcdc_blu6" },
4495 { GPIO_CFG(104, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "lcdc_blu7" },
4496 { GPIO_CFG(105, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "lcdc_red3" },
4497 { GPIO_CFG(106, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "lcdc_red4" },
4498 { GPIO_CFG(107, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "lcdc_red5" },
4499 { GPIO_CFG(108, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "lcdc_red6" },
4500 { GPIO_CFG(109, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "lcdc_red7" },
4501};
4502
4503static struct msm_gpio lcd_sharp_panel_gpios[] = {
4504 { GPIO_CFG(22, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "lcdc_blu2" },
4505 { GPIO_CFG(25, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "lcdc_red2" },
4506 { GPIO_CFG(90, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "lcdc_pclk" },
4507 { GPIO_CFG(91, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "lcdc_en" },
4508 { GPIO_CFG(92, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "lcdc_vsync" },
4509 { GPIO_CFG(93, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "lcdc_hsync" },
4510 { GPIO_CFG(94, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "lcdc_grn2" },
4511 { GPIO_CFG(95, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "lcdc_grn3" },
4512 { GPIO_CFG(96, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "lcdc_grn4" },
4513 { GPIO_CFG(97, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "lcdc_grn5" },
4514 { GPIO_CFG(98, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "lcdc_grn6" },
4515 { GPIO_CFG(99, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "lcdc_grn7" },
4516 { GPIO_CFG(100, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "lcdc_blu3" },
4517 { GPIO_CFG(101, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "lcdc_blu4" },
4518 { GPIO_CFG(102, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "lcdc_blu5" },
4519 { GPIO_CFG(103, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "lcdc_blu6" },
4520 { GPIO_CFG(104, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "lcdc_blu7" },
4521 { GPIO_CFG(105, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "lcdc_red3" },
4522 { GPIO_CFG(106, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "lcdc_red4" },
4523 { GPIO_CFG(107, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "lcdc_red5" },
4524 { GPIO_CFG(108, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "lcdc_red6" },
4525 { GPIO_CFG(109, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "lcdc_red7" },
4526};
4527
4528static int lcdc_toshiba_panel_power(int on)
4529{
4530 int rc, i;
4531 struct msm_gpio *gp;
4532
4533 rc = display_common_power(on);
4534 if (rc < 0) {
4535 printk(KERN_ERR "%s display_common_power failed: %d\n",
4536 __func__, rc);
4537 return rc;
4538 }
4539
4540 if (on) {
4541 rc = msm_gpios_enable(lcd_panel_gpios,
4542 ARRAY_SIZE(lcd_panel_gpios));
4543 if (rc < 0) {
4544 printk(KERN_ERR "%s: gpio enable failed: %d\n",
4545 __func__, rc);
4546 }
4547 } else { /* off */
4548 gp = lcd_panel_gpios;
4549 for (i = 0; i < ARRAY_SIZE(lcd_panel_gpios); i++) {
4550 /* ouput low */
4551 gpio_set_value(GPIO_PIN(gp->gpio_cfg), 0);
4552 gp++;
4553 }
4554 }
4555
4556 return rc;
4557}
4558
4559static int lcdc_sharp_panel_power(int on)
4560{
4561 int rc, i;
4562 struct msm_gpio *gp;
4563
4564 rc = display_common_power(on);
4565 if (rc < 0) {
4566 printk(KERN_ERR "%s display_common_power failed: %d\n",
4567 __func__, rc);
4568 return rc;
4569 }
4570
4571 if (on) {
4572 rc = msm_gpios_enable(lcd_sharp_panel_gpios,
4573 ARRAY_SIZE(lcd_sharp_panel_gpios));
4574 if (rc < 0) {
4575 printk(KERN_ERR "%s: gpio enable failed: %d\n",
4576 __func__, rc);
4577 }
4578 } else { /* off */
4579 gp = lcd_sharp_panel_gpios;
4580 for (i = 0; i < ARRAY_SIZE(lcd_sharp_panel_gpios); i++) {
4581 /* ouput low */
4582 gpio_set_value(GPIO_PIN(gp->gpio_cfg), 0);
4583 gp++;
4584 }
4585 }
4586
4587 return rc;
4588}
4589
4590static int lcdc_panel_power(int on)
4591{
4592 int flag_on = !!on;
4593 static int lcdc_power_save_on;
4594
4595 if (lcdc_power_save_on == flag_on)
4596 return 0;
4597
4598 lcdc_power_save_on = flag_on;
4599 quickvx_mddi_client = 0;
4600
4601 if (machine_is_msm7x30_fluid())
4602 return lcdc_sharp_panel_power(on);
4603 else
4604 return lcdc_toshiba_panel_power(on);
4605}
4606
4607static struct lcdc_platform_data lcdc_pdata = {
4608 .lcdc_power_save = lcdc_panel_power,
4609};
4610
4611static int atv_dac_power(int on)
4612{
4613 int rc = 0;
4614 struct vreg *vreg_s4, *vreg_ldo9;
4615
4616 vreg_s4 = vreg_get(NULL, "s4");
4617 if (IS_ERR(vreg_s4)) {
4618 rc = PTR_ERR(vreg_s4);
4619 pr_err("%s: s4 vreg get failed (%d)\n",
4620 __func__, rc);
4621 return -1;
4622 }
4623 vreg_ldo9 = vreg_get(NULL, "gp1");
4624 if (IS_ERR(vreg_ldo9)) {
4625 rc = PTR_ERR(vreg_ldo9);
4626 pr_err("%s: ldo9 vreg get failed (%d)\n",
4627 __func__, rc);
4628 return rc;
4629 }
4630
4631 if (on) {
4632 rc = vreg_enable(vreg_s4);
4633 if (rc) {
4634 pr_err("%s: s4 vreg enable failed (%d)\n",
4635 __func__, rc);
4636 return rc;
4637 }
4638 rc = vreg_enable(vreg_ldo9);
4639 if (rc) {
4640 pr_err("%s: ldo9 vreg enable failed (%d)\n",
4641 __func__, rc);
4642 return rc;
4643 }
4644 } else {
4645 rc = vreg_disable(vreg_ldo9);
4646 if (rc) {
4647 pr_err("%s: ldo9 vreg disable failed (%d)\n",
4648 __func__, rc);
4649 return rc;
4650 }
4651 rc = vreg_disable(vreg_s4);
4652 if (rc) {
4653 pr_err("%s: s4 vreg disable failed (%d)\n",
4654 __func__, rc);
4655 return rc;
4656 }
4657 }
4658 return rc;
4659}
4660
4661static struct tvenc_platform_data atv_pdata = {
4662 .poll = 1,
4663 .pm_vid_en = atv_dac_power,
4664};
4665
4666static void __init msm_fb_add_devices(void)
4667{
4668 msm_fb_register_device("mdp", &mdp_pdata);
4669 msm_fb_register_device("pmdh", &mddi_pdata);
4670 msm_fb_register_device("lcdc", &lcdc_pdata);
4671 msm_fb_register_device("dtv", &dtv_pdata);
4672 msm_fb_register_device("tvenc", &atv_pdata);
4673#ifdef CONFIG_FB_MSM_TVOUT
4674 msm_fb_register_device("tvout_device", NULL);
4675#endif
4676}
4677
4678static struct msm_panel_common_pdata lcdc_toshiba_panel_data = {
4679 .gpio_num = lcd_panel_spi_gpio_num,
4680};
4681
4682static struct platform_device lcdc_toshiba_panel_device = {
4683 .name = "lcdc_toshiba_wvga",
4684 .id = 0,
4685 .dev = {
4686 .platform_data = &lcdc_toshiba_panel_data,
4687 }
4688};
4689
4690#if defined(CONFIG_MARIMBA_CORE) && \
4691 (defined(CONFIG_MSM_BT_POWER) || defined(CONFIG_MSM_BT_POWER_MODULE))
4692static struct platform_device msm_bt_power_device = {
4693 .name = "bt_power",
4694 .id = -1
4695};
4696
4697enum {
4698 BT_RFR,
4699 BT_CTS,
4700 BT_RX,
4701 BT_TX,
4702};
4703
4704static struct msm_gpio bt_config_power_on[] = {
4705 { GPIO_CFG(134, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA),
4706 "UART1DM_RFR" },
4707 { GPIO_CFG(135, 1, GPIO_CFG_INPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA),
4708 "UART1DM_CTS" },
4709 { GPIO_CFG(136, 1, GPIO_CFG_INPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA),
4710 "UART1DM_Rx" },
4711 { GPIO_CFG(137, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA),
4712 "UART1DM_Tx" }
4713};
4714
4715static struct msm_gpio bt_config_power_off[] = {
4716 { GPIO_CFG(134, 0, GPIO_CFG_INPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA),
4717 "UART1DM_RFR" },
4718 { GPIO_CFG(135, 0, GPIO_CFG_INPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA),
4719 "UART1DM_CTS" },
4720 { GPIO_CFG(136, 0, GPIO_CFG_INPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA),
4721 "UART1DM_Rx" },
4722 { GPIO_CFG(137, 0, GPIO_CFG_INPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA),
4723 "UART1DM_Tx" }
4724};
4725
4726static const char *vregs_bt_marimba_name[] = {
4727 "s3",
4728 "s2",
4729 "gp16",
4730 "wlan"
4731};
4732static struct vreg *vregs_bt_marimba[ARRAY_SIZE(vregs_bt_marimba_name)];
4733
4734static const char *vregs_bt_bahama_name[] = {
4735 "s3",
4736 "usb2",
4737 "s2",
4738 "wlan"
4739};
4740static struct vreg *vregs_bt_bahama[ARRAY_SIZE(vregs_bt_bahama_name)];
4741
4742static u8 bahama_version;
4743
4744static int marimba_bt(int on)
4745{
4746 int rc;
4747 int i;
4748 struct marimba config = { .mod_id = MARIMBA_SLAVE_ID_MARIMBA };
4749
4750 struct marimba_config_register {
4751 u8 reg;
4752 u8 value;
4753 u8 mask;
4754 };
4755
4756 struct marimba_variant_register {
4757 const size_t size;
4758 const struct marimba_config_register *set;
4759 };
4760
4761 const struct marimba_config_register *p;
4762
4763 u8 version;
4764
4765 const struct marimba_config_register v10_bt_on[] = {
4766 { 0xE5, 0x0B, 0x0F },
4767 { 0x05, 0x02, 0x07 },
4768 { 0x06, 0x88, 0xFF },
4769 { 0xE7, 0x21, 0x21 },
4770 { 0xE3, 0x38, 0xFF },
4771 { 0xE4, 0x06, 0xFF },
4772 };
4773
4774 const struct marimba_config_register v10_bt_off[] = {
4775 { 0xE5, 0x0B, 0x0F },
4776 { 0x05, 0x08, 0x0F },
4777 { 0x06, 0x88, 0xFF },
4778 { 0xE7, 0x00, 0x21 },
4779 { 0xE3, 0x00, 0xFF },
4780 { 0xE4, 0x00, 0xFF },
4781 };
4782
4783 const struct marimba_config_register v201_bt_on[] = {
4784 { 0x05, 0x08, 0x07 },
4785 { 0x06, 0x88, 0xFF },
4786 { 0xE7, 0x21, 0x21 },
4787 { 0xE3, 0x38, 0xFF },
4788 { 0xE4, 0x06, 0xFF },
4789 };
4790
4791 const struct marimba_config_register v201_bt_off[] = {
4792 { 0x05, 0x08, 0x07 },
4793 { 0x06, 0x88, 0xFF },
4794 { 0xE7, 0x00, 0x21 },
4795 { 0xE3, 0x00, 0xFF },
4796 { 0xE4, 0x00, 0xFF },
4797 };
4798
4799 const struct marimba_config_register v210_bt_on[] = {
4800 { 0xE9, 0x01, 0x01 },
4801 { 0x06, 0x88, 0xFF },
4802 { 0xE7, 0x21, 0x21 },
4803 { 0xE3, 0x38, 0xFF },
4804 { 0xE4, 0x06, 0xFF },
4805 };
4806
4807 const struct marimba_config_register v210_bt_off[] = {
4808 { 0x06, 0x88, 0xFF },
4809 { 0xE7, 0x00, 0x21 },
4810 { 0xE9, 0x00, 0x01 },
4811 { 0xE3, 0x00, 0xFF },
4812 { 0xE4, 0x00, 0xFF },
4813 };
4814
4815 const struct marimba_variant_register bt_marimba[2][4] = {
4816 {
4817 { ARRAY_SIZE(v10_bt_off), v10_bt_off },
4818 { 0, NULL },
4819 { ARRAY_SIZE(v201_bt_off), v201_bt_off },
4820 { ARRAY_SIZE(v210_bt_off), v210_bt_off }
4821 },
4822 {
4823 { ARRAY_SIZE(v10_bt_on), v10_bt_on },
4824 { 0, NULL },
4825 { ARRAY_SIZE(v201_bt_on), v201_bt_on },
4826 { ARRAY_SIZE(v210_bt_on), v210_bt_on }
4827 }
4828 };
4829
4830 on = on ? 1 : 0;
4831
4832 rc = marimba_read_bit_mask(&config, 0x11, &version, 1, 0x1F);
4833 if (rc < 0) {
4834 printk(KERN_ERR
4835 "%s: version read failed: %d\n",
4836 __func__, rc);
4837 return rc;
4838 }
4839
4840 if ((version >= ARRAY_SIZE(bt_marimba[on])) ||
4841 (bt_marimba[on][version].size == 0)) {
4842 printk(KERN_ERR
4843 "%s: unsupported version\n",
4844 __func__);
4845 return -EIO;
4846 }
4847
4848 p = bt_marimba[on][version].set;
4849
4850 printk(KERN_INFO "%s: found version %d\n", __func__, version);
4851
4852 for (i = 0; i < bt_marimba[on][version].size; i++) {
4853 u8 value = (p+i)->value;
4854 rc = marimba_write_bit_mask(&config,
4855 (p+i)->reg,
4856 &value,
4857 sizeof((p+i)->value),
4858 (p+i)->mask);
4859 if (rc < 0) {
4860 printk(KERN_ERR
4861 "%s: reg %d write failed: %d\n",
4862 __func__, (p+i)->reg, rc);
4863 return rc;
4864 }
4865 printk(KERN_INFO "%s: reg 0x%02x value 0x%02x mask 0x%02x\n",
4866 __func__, (p+i)->reg,
4867 value, (p+i)->mask);
4868 }
4869 return 0;
4870}
4871
4872static int bahama_bt(int on)
4873{
4874 int rc;
4875 int i;
4876 struct marimba config = { .mod_id = SLAVE_ID_BAHAMA };
4877
4878 struct bahama_variant_register {
4879 const size_t size;
4880 const struct bahama_config_register *set;
4881 };
4882
4883 const struct bahama_config_register *p;
4884
4885
4886 const struct bahama_config_register v10_bt_on[] = {
4887 { 0xE9, 0x00, 0xFF },
4888 { 0xF4, 0x80, 0xFF },
4889 { 0xF0, 0x06, 0xFF },
4890 { 0xE4, 0x00, 0xFF },
4891 { 0xE5, 0x00, 0x0F },
4892#ifdef CONFIG_WLAN
4893 { 0xE6, 0x38, 0x7F },
4894 { 0xE7, 0x06, 0xFF },
4895#endif
4896 { 0x11, 0x13, 0xFF },
4897 { 0xE9, 0x21, 0xFF },
4898 { 0x01, 0x0C, 0x1F },
4899 { 0x01, 0x08, 0x1F },
4900 };
4901
4902 const struct bahama_config_register v20_bt_on_fm_off[] = {
4903 { 0x11, 0x0C, 0xFF },
4904 { 0x13, 0x01, 0xFF },
4905 { 0xF4, 0x80, 0xFF },
4906 { 0xF0, 0x00, 0xFF },
4907 { 0xE9, 0x00, 0xFF },
4908#ifdef CONFIG_WLAN
4909 { 0x81, 0x00, 0xFF },
4910 { 0x82, 0x00, 0xFF },
4911 { 0xE6, 0x38, 0x7F },
4912 { 0xE7, 0x06, 0xFF },
4913#endif
4914 { 0xE9, 0x21, 0xFF }
4915 };
4916
4917 const struct bahama_config_register v20_bt_on_fm_on[] = {
4918 { 0x11, 0x0C, 0xFF },
4919 { 0x13, 0x01, 0xFF },
4920 { 0xF4, 0x86, 0xFF },
4921 { 0xF0, 0x06, 0xFF },
4922 { 0xE9, 0x00, 0xFF },
4923#ifdef CONFIG_WLAN
4924 { 0x81, 0x00, 0xFF },
4925 { 0x82, 0x00, 0xFF },
4926 { 0xE6, 0x38, 0x7F },
4927 { 0xE7, 0x06, 0xFF },
4928#endif
4929 { 0xE9, 0x21, 0xFF }
4930 };
4931
4932 const struct bahama_config_register v10_bt_off[] = {
4933 { 0xE9, 0x00, 0xFF },
4934 };
4935
4936 const struct bahama_config_register v20_bt_off_fm_off[] = {
4937 { 0xF4, 0x84, 0xFF },
4938 { 0xF0, 0x04, 0xFF },
4939 { 0xE9, 0x00, 0xFF }
4940 };
4941
4942 const struct bahama_config_register v20_bt_off_fm_on[] = {
4943 { 0xF4, 0x86, 0xFF },
4944 { 0xF0, 0x06, 0xFF },
4945 { 0xE9, 0x00, 0xFF }
4946 };
4947
4948 const struct bahama_variant_register bt_bahama[2][3] = {
4949 {
4950 { ARRAY_SIZE(v10_bt_off), v10_bt_off },
4951 { ARRAY_SIZE(v20_bt_off_fm_off), v20_bt_off_fm_off },
4952 { ARRAY_SIZE(v20_bt_off_fm_on), v20_bt_off_fm_on }
4953 },
4954 {
4955 { ARRAY_SIZE(v10_bt_on), v10_bt_on },
4956 { ARRAY_SIZE(v20_bt_on_fm_off), v20_bt_on_fm_off },
4957 { ARRAY_SIZE(v20_bt_on_fm_on), v20_bt_on_fm_on }
4958 }
4959 };
4960
4961 u8 offset = 0; /* index into bahama configs */
4962
4963 on = on ? 1 : 0;
4964
4965 bahama_version = read_bahama_ver();
4966
4967 if (((int)bahama_version) < 0 ||
4968 bahama_version == VER_UNSUPPORTED) {
4969 dev_err(&msm_bt_power_device.dev,
4970 "%s: i2c failure or unsupported version: %d\n",
4971 __func__, bahama_version);
4972 return -EIO;
4973 }
4974
4975 if (bahama_version == VER_2_0) {
4976 if (marimba_get_fm_status(&config))
4977 offset = 0x01;
4978 }
4979
4980 p = bt_bahama[on][bahama_version + offset].set;
4981
4982 dev_info(&msm_bt_power_device.dev,
4983 "%s: found version %d\n", __func__, bahama_version);
4984
4985 for (i = 0; i < bt_bahama[on][bahama_version + offset].size; i++) {
4986 u8 value = (p+i)->value;
4987 rc = marimba_write_bit_mask(&config,
4988 (p+i)->reg,
4989 &value,
4990 sizeof((p+i)->value),
4991 (p+i)->mask);
4992 if (rc < 0) {
4993 dev_err(&msm_bt_power_device.dev,
4994 "%s: reg %d write failed: %d\n",
4995 __func__, (p+i)->reg, rc);
4996 return rc;
4997 }
4998 dev_info(&msm_bt_power_device.dev,
4999 "%s: reg 0x%02x write value 0x%02x mask 0x%02x\n",
5000 __func__, (p+i)->reg,
5001 value, (p+i)->mask);
5002 }
5003 /* Update BT status */
5004 if (on)
5005 marimba_set_bt_status(&config, true);
5006 else
5007 marimba_set_bt_status(&config, false);
5008
5009 if (bahama_version == VER_2_0 && on) { /* variant of bahama v2 */
5010 /* Disable s2 as bahama v2 uses internal LDO regulator */
5011 for (i = 0; i < ARRAY_SIZE(vregs_bt_bahama_name); i++) {
5012 if (!strcmp(vregs_bt_bahama_name[i], "s2")) {
5013 rc = vreg_disable(vregs_bt_bahama[i]);
5014 if (rc < 0) {
5015 printk(KERN_ERR
5016 "%s: vreg %s disable "
5017 "failed (%d)\n",
5018 __func__,
5019 vregs_bt_bahama_name[i], rc);
5020 return -EIO;
5021 }
5022 rc = pmapp_vreg_level_vote("BTPW",
5023 PMAPP_VREG_S2,
5024 0);
5025 if (rc < 0) {
5026 printk(KERN_ERR "%s: vreg "
5027 "level off failed (%d)\n",
5028 __func__, rc);
5029 return -EIO;
5030 }
5031 printk(KERN_INFO "%s: vreg disable & "
5032 "level off successful (%d)\n",
5033 __func__, rc);
5034 }
5035 }
5036 }
5037
5038 return 0;
5039}
5040
5041static int bluetooth_power_regulators(int on, int bahama_not_marimba)
5042{
5043 int i, rc;
5044 const char **vregs_name;
5045 struct vreg **vregs;
5046 int vregs_size;
5047
5048 if (bahama_not_marimba) {
5049 vregs_name = vregs_bt_bahama_name;
5050 vregs = vregs_bt_bahama;
5051 vregs_size = ARRAY_SIZE(vregs_bt_bahama_name);
5052 } else {
5053 vregs_name = vregs_bt_marimba_name;
5054 vregs = vregs_bt_marimba;
5055 vregs_size = ARRAY_SIZE(vregs_bt_marimba_name);
5056 }
5057
5058 for (i = 0; i < vregs_size; i++) {
5059 if (bahama_not_marimba && (bahama_version == VER_2_0) &&
5060 !on && !strcmp(vregs_bt_bahama_name[i], "s2"))
5061 continue;
5062 rc = on ? vreg_enable(vregs[i]) :
5063 vreg_disable(vregs[i]);
5064 if (rc < 0) {
5065 printk(KERN_ERR "%s: vreg %s %s failed (%d)\n",
5066 __func__, vregs_name[i],
5067 on ? "enable" : "disable", rc);
5068 return -EIO;
5069 }
5070 }
5071 return 0;
5072}
5073
5074static int bluetooth_power(int on)
5075{
5076 int rc;
5077 const char *id = "BTPW";
5078
5079 int bahama_not_marimba = bahama_present();
5080
5081 if (bahama_not_marimba == -1) {
5082 printk(KERN_WARNING "%s: bahama_present: %d\n",
5083 __func__, bahama_not_marimba);
5084 return -ENODEV;
5085 }
5086
5087 if (on) {
5088 rc = pmapp_vreg_level_vote(id, PMAPP_VREG_S2, 1300);
5089 if (rc < 0) {
5090 printk(KERN_ERR "%s: vreg level on failed (%d)\n",
5091 __func__, rc);
5092 return rc;
5093 }
5094
5095 rc = bluetooth_power_regulators(on, bahama_not_marimba);
5096 if (rc < 0)
5097 return -EIO;
5098
5099 rc = pmapp_clock_vote(id, PMAPP_CLOCK_ID_DO,
5100 PMAPP_CLOCK_VOTE_ON);
5101 if (rc < 0)
5102 return -EIO;
5103
5104 if (machine_is_msm8x55_svlte_surf() ||
5105 machine_is_msm8x55_svlte_ffa()) {
5106 rc = marimba_gpio_config(1);
5107 if (rc < 0)
5108 return -EIO;
5109 }
5110
5111 rc = (bahama_not_marimba ? bahama_bt(on) : marimba_bt(on));
5112 if (rc < 0)
5113 return -EIO;
5114
5115 msleep(10);
5116
5117 rc = pmapp_clock_vote(id, PMAPP_CLOCK_ID_DO,
5118 PMAPP_CLOCK_VOTE_PIN_CTRL);
5119 if (rc < 0)
5120 return -EIO;
5121
5122 if (machine_is_msm8x55_svlte_surf() ||
5123 machine_is_msm8x55_svlte_ffa()) {
5124 rc = marimba_gpio_config(0);
5125 if (rc < 0)
5126 return -EIO;
5127 }
5128
5129 rc = msm_gpios_enable(bt_config_power_on,
5130 ARRAY_SIZE(bt_config_power_on));
5131
5132 if (rc < 0)
5133 return rc;
5134
5135 } else {
5136 rc = msm_gpios_enable(bt_config_power_off,
5137 ARRAY_SIZE(bt_config_power_off));
5138 if (rc < 0)
5139 return rc;
5140
5141 /* check for initial RFKILL block (power off) */
5142 if (platform_get_drvdata(&msm_bt_power_device) == NULL)
5143 goto out;
5144
5145 rc = (bahama_not_marimba ? bahama_bt(on) : marimba_bt(on));
5146 if (rc < 0)
5147 return -EIO;
5148
5149 rc = pmapp_clock_vote(id, PMAPP_CLOCK_ID_DO,
5150 PMAPP_CLOCK_VOTE_OFF);
5151 if (rc < 0)
5152 return -EIO;
5153
5154 rc = bluetooth_power_regulators(on, bahama_not_marimba);
5155 if (rc < 0)
5156 return -EIO;
5157
5158 if (bahama_version == VER_1_0) {
5159 rc = pmapp_vreg_level_vote(id, PMAPP_VREG_S2, 0);
5160 if (rc < 0) {
5161 printk(KERN_ERR "%s: vreg level off failed "
5162 "(%d)\n", __func__, rc);
5163 return -EIO;
5164 }
5165 }
5166 }
5167
5168out:
5169 printk(KERN_DEBUG "Bluetooth power switch: %d\n", on);
5170
5171 return 0;
5172}
5173
5174static void __init bt_power_init(void)
5175{
5176 int i;
5177
5178 for (i = 0; i < ARRAY_SIZE(vregs_bt_marimba_name); i++) {
5179 vregs_bt_marimba[i] = vreg_get(NULL, vregs_bt_marimba_name[i]);
5180 if (IS_ERR(vregs_bt_marimba[i])) {
5181 printk(KERN_ERR "%s: vreg get %s failed (%ld)\n",
5182 __func__, vregs_bt_marimba_name[i],
5183 PTR_ERR(vregs_bt_marimba[i]));
5184 return;
5185 }
5186 }
5187
5188 for (i = 0; i < ARRAY_SIZE(vregs_bt_bahama_name); i++) {
5189 vregs_bt_bahama[i] = vreg_get(NULL, vregs_bt_bahama_name[i]);
5190 if (IS_ERR(vregs_bt_bahama[i])) {
5191 printk(KERN_ERR "%s: vreg get %s failed (%ld)\n",
5192 __func__, vregs_bt_bahama_name[i],
5193 PTR_ERR(vregs_bt_bahama[i]));
5194 return;
5195 }
5196 }
5197
5198 msm_bt_power_device.dev.platform_data = &bluetooth_power;
5199}
5200#else
5201#define bt_power_init(x) do {} while (0)
5202#endif
5203
5204static struct msm_psy_batt_pdata msm_psy_batt_data = {
5205 .voltage_min_design = 2800,
5206 .voltage_max_design = 4300,
5207 .avail_chg_sources = AC_CHG | USB_CHG ,
5208 .batt_technology = POWER_SUPPLY_TECHNOLOGY_LION,
5209};
5210
5211static struct platform_device msm_batt_device = {
5212 .name = "msm-battery",
5213 .id = -1,
5214 .dev.platform_data = &msm_psy_batt_data,
5215};
5216
5217static char *msm_adc_fluid_device_names[] = {
5218 "LTC_ADC1",
5219 "LTC_ADC2",
5220 "LTC_ADC3",
5221};
5222
5223static char *msm_adc_surf_device_names[] = {
5224 "XO_ADC",
5225};
5226
5227static struct msm_adc_platform_data msm_adc_pdata;
5228
5229static struct platform_device msm_adc_device = {
5230 .name = "msm_adc",
5231 .id = -1,
5232 .dev = {
5233 .platform_data = &msm_adc_pdata,
5234 },
5235};
5236
5237#ifdef CONFIG_MSM_SDIO_AL
5238static struct msm_gpio mdm2ap_status = {
5239 GPIO_CFG(77, 0, GPIO_CFG_INPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA),
5240 "mdm2ap_status"
5241};
5242
5243
5244static int configure_mdm2ap_status(int on)
5245{
5246 if (on)
5247 return msm_gpios_request_enable(&mdm2ap_status, 1);
5248 else {
5249 msm_gpios_disable_free(&mdm2ap_status, 1);
5250 return 0;
5251 }
5252}
5253
5254static int get_mdm2ap_status(void)
5255{
5256 return gpio_get_value(GPIO_PIN(mdm2ap_status.gpio_cfg));
5257}
5258
5259static struct sdio_al_platform_data sdio_al_pdata = {
5260 .config_mdm2ap_status = configure_mdm2ap_status,
5261 .get_mdm2ap_status = get_mdm2ap_status,
5262 .allow_sdioc_version_major_2 = 1,
5263 .peer_sdioc_version_minor = 0x0001,
5264 .peer_sdioc_version_major = 0x0003,
5265 .peer_sdioc_boot_version_minor = 0x0001,
5266 .peer_sdioc_boot_version_major = 0x0003,
5267};
5268
5269struct platform_device msm_device_sdio_al = {
5270 .name = "msm_sdio_al",
5271 .id = -1,
5272 .dev = {
5273 .platform_data = &sdio_al_pdata,
5274 },
5275};
5276
5277#endif /* CONFIG_MSM_SDIO_AL */
5278
Daniel Walker8d747cd2010-02-25 11:37:43 -08005279static struct platform_device *devices[] __initdata = {
Daniel Walker90e37c52010-05-12 14:24:15 -07005280#if defined(CONFIG_SERIAL_MSM) || defined(CONFIG_MSM_SERIAL_DEBUGGER)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005281 &msm_device_uart2,
5282#endif
Justin Paupore637a25d2011-07-14 17:11:04 -07005283#ifdef CONFIG_MSM_PROC_COMM_REGULATOR
5284 &msm_proccomm_regulator_dev,
5285#endif
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005286 &asoc_msm_pcm,
5287 &asoc_msm_dai0,
5288 &asoc_msm_dai1,
5289#if defined (CONFIG_SND_MSM_MVS_DAI_SOC)
5290 &asoc_msm_mvs,
5291 &asoc_mvs_dai0,
5292 &asoc_mvs_dai1,
Daniel Walker90e37c52010-05-12 14:24:15 -07005293#endif
Niranjana Vishwanathapuraa8855e92010-10-06 13:52:10 -07005294 &msm_device_smd,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005295 &msm_device_dmov,
5296 &smc91x_device,
5297 &smsc911x_device,
5298 &msm_device_nand,
5299#ifdef CONFIG_USB_MSM_OTG_72K
Pavankumar Kondeti5155e2c2010-12-08 13:37:08 +05305300 &msm_device_otg,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005301#ifdef CONFIG_USB_GADGET
5302 &msm_device_gadget_peripheral,
5303#endif
5304#endif
5305#ifdef CONFIG_USB_G_ANDROID
5306 &android_usb_device,
5307#endif
5308 &qsd_device_spi,
5309#ifdef CONFIG_I2C_SSBI
5310 &msm_device_ssbi6,
5311 &msm_device_ssbi7,
5312#endif
5313 &android_pmem_device,
5314 &msm_fb_device,
5315 &msm_migrate_pages_device,
5316 &mddi_toshiba_device,
5317 &lcdc_toshiba_panel_device,
5318#ifdef CONFIG_MSM_ROTATOR
5319 &msm_rotator_device,
5320#endif
5321 &lcdc_sharp_panel_device,
5322 &android_pmem_adsp_device,
5323 &android_pmem_audio_device,
5324 &msm_device_i2c,
5325 &msm_device_i2c_2,
5326 &msm_device_uart_dm1,
5327 &hs_device,
5328#ifdef CONFIG_MSM7KV2_AUDIO
5329 &msm_aictl_device,
5330 &msm_mi2s_device,
5331 &msm_lpa_device,
5332 &msm_aux_pcm_device,
5333#endif
5334 &msm_device_adspdec,
5335 &qup_device_i2c,
5336#if defined(CONFIG_MARIMBA_CORE) && \
5337 (defined(CONFIG_MSM_BT_POWER) || defined(CONFIG_MSM_BT_POWER_MODULE))
5338 &msm_bt_power_device,
5339#endif
5340 &msm_kgsl_3d0,
5341 &msm_kgsl_2d0,
5342#ifdef CONFIG_MT9T013
5343 &msm_camera_sensor_mt9t013,
5344#endif
5345#ifdef CONFIG_MT9D112
5346 &msm_camera_sensor_mt9d112,
5347#endif
5348#ifdef CONFIG_WEBCAM_OV9726
5349 &msm_camera_sensor_ov9726,
5350#endif
5351#ifdef CONFIG_S5K3E2FX
5352 &msm_camera_sensor_s5k3e2fx,
5353#endif
5354#ifdef CONFIG_MT9P012
5355 &msm_camera_sensor_mt9p012,
5356#endif
5357#ifdef CONFIG_MT9E013
5358 &msm_camera_sensor_mt9e013,
5359#endif
5360#ifdef CONFIG_VX6953
5361 &msm_camera_sensor_vx6953,
5362#endif
5363#ifdef CONFIG_SN12M0PZ
5364 &msm_camera_sensor_sn12m0pz,
5365#endif
5366 &msm_device_vidc_720p,
5367#ifdef CONFIG_MSM_GEMINI
5368 &msm_gemini_device,
5369#endif
5370#ifdef CONFIG_MSM_VPE
5371 &msm_vpe_device,
5372#endif
5373#if defined(CONFIG_TSIF) || defined(CONFIG_TSIF_MODULE)
5374 &msm_device_tsif,
5375#endif
5376#ifdef CONFIG_MSM_SDIO_AL
5377 &msm_device_sdio_al,
5378#endif
5379
5380#if defined(CONFIG_CRYPTO_DEV_QCRYPTO) || \
5381 defined(CONFIG_CRYPTO_DEV_QCRYPTO_MODULE)
5382 &qcrypto_device,
5383#endif
5384
5385#if defined(CONFIG_CRYPTO_DEV_QCEDEV) || \
5386 defined(CONFIG_CRYPTO_DEV_QCEDEV_MODULE)
5387 &qcedev_device,
5388#endif
5389
5390 &msm_batt_device,
5391 &msm_adc_device,
5392 &msm_ebi0_thermal,
5393 &msm_ebi1_thermal
5394};
5395
5396static struct msm_gpio msm_i2c_gpios_hw[] = {
5397 { GPIO_CFG(70, 1, GPIO_CFG_INPUT, GPIO_CFG_NO_PULL, GPIO_CFG_16MA), "i2c_scl" },
5398 { GPIO_CFG(71, 1, GPIO_CFG_INPUT, GPIO_CFG_NO_PULL, GPIO_CFG_16MA), "i2c_sda" },
5399};
5400
5401static struct msm_gpio msm_i2c_gpios_io[] = {
5402 { GPIO_CFG(70, 0, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_16MA), "i2c_scl" },
5403 { GPIO_CFG(71, 0, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_16MA), "i2c_sda" },
5404};
5405
5406static struct msm_gpio qup_i2c_gpios_io[] = {
5407 { GPIO_CFG(16, 0, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_16MA), "qup_scl" },
5408 { GPIO_CFG(17, 0, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_16MA), "qup_sda" },
5409};
5410static struct msm_gpio qup_i2c_gpios_hw[] = {
5411 { GPIO_CFG(16, 2, GPIO_CFG_INPUT, GPIO_CFG_NO_PULL, GPIO_CFG_16MA), "qup_scl" },
5412 { GPIO_CFG(17, 2, GPIO_CFG_INPUT, GPIO_CFG_NO_PULL, GPIO_CFG_16MA), "qup_sda" },
5413};
5414
5415static void
5416msm_i2c_gpio_config(int adap_id, int config_type)
5417{
5418 struct msm_gpio *msm_i2c_table;
5419
5420 /* Each adapter gets 2 lines from the table */
5421 if (adap_id > 0)
5422 return;
5423 if (config_type)
5424 msm_i2c_table = &msm_i2c_gpios_hw[adap_id*2];
5425 else
5426 msm_i2c_table = &msm_i2c_gpios_io[adap_id*2];
5427 msm_gpios_enable(msm_i2c_table, 2);
5428}
5429/*This needs to be enabled only for OEMS*/
5430#ifndef CONFIG_QUP_EXCLUSIVE_TO_CAMERA
5431static struct vreg *qup_vreg;
5432#endif
5433static void
5434qup_i2c_gpio_config(int adap_id, int config_type)
5435{
5436 int rc = 0;
5437 struct msm_gpio *qup_i2c_table;
5438 /* Each adapter gets 2 lines from the table */
5439 if (adap_id != 4)
5440 return;
5441 if (config_type)
5442 qup_i2c_table = qup_i2c_gpios_hw;
5443 else
5444 qup_i2c_table = qup_i2c_gpios_io;
5445 rc = msm_gpios_enable(qup_i2c_table, 2);
5446 if (rc < 0)
5447 printk(KERN_ERR "QUP GPIO enable failed: %d\n", rc);
5448 /*This needs to be enabled only for OEMS*/
5449#ifndef CONFIG_QUP_EXCLUSIVE_TO_CAMERA
5450 if (qup_vreg) {
5451 int rc = vreg_set_level(qup_vreg, 1800);
5452 if (rc) {
5453 pr_err("%s: vreg LVS1 set level failed (%d)\n",
5454 __func__, rc);
5455 }
5456 rc = vreg_enable(qup_vreg);
5457 if (rc) {
5458 pr_err("%s: vreg_enable() = %d \n",
5459 __func__, rc);
5460 }
5461 }
5462#endif
5463}
5464
5465static struct msm_i2c_platform_data msm_i2c_pdata = {
5466 .clk_freq = 100000,
5467 .pri_clk = 70,
5468 .pri_dat = 71,
5469 .rmutex = 1,
5470 .rsl_id = "D:I2C02000021",
5471 .msm_i2c_config_gpio = msm_i2c_gpio_config,
5472};
5473
5474static void __init msm_device_i2c_init(void)
5475{
5476 if (msm_gpios_request(msm_i2c_gpios_hw, ARRAY_SIZE(msm_i2c_gpios_hw)))
5477 pr_err("failed to request I2C gpios\n");
5478
5479 msm_device_i2c.dev.platform_data = &msm_i2c_pdata;
5480}
5481
5482static struct msm_i2c_platform_data msm_i2c_2_pdata = {
5483 .clk_freq = 100000,
5484 .rmutex = 1,
5485 .rsl_id = "D:I2C02000022",
5486 .msm_i2c_config_gpio = msm_i2c_gpio_config,
5487};
5488
5489static void __init msm_device_i2c_2_init(void)
5490{
5491 msm_device_i2c_2.dev.platform_data = &msm_i2c_2_pdata;
5492}
5493
5494static struct msm_i2c_platform_data qup_i2c_pdata = {
5495 .clk_freq = 384000,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005496 .msm_i2c_config_gpio = qup_i2c_gpio_config,
5497};
5498
5499static void __init qup_device_i2c_init(void)
5500{
5501 if (msm_gpios_request(qup_i2c_gpios_hw, ARRAY_SIZE(qup_i2c_gpios_hw)))
5502 pr_err("failed to request I2C gpios\n");
5503
5504 qup_device_i2c.dev.platform_data = &qup_i2c_pdata;
5505 /*This needs to be enabled only for OEMS*/
5506#ifndef CONFIG_QUP_EXCLUSIVE_TO_CAMERA
5507 qup_vreg = vreg_get(NULL, "lvsw1");
5508 if (IS_ERR(qup_vreg)) {
5509 printk(KERN_ERR "%s: vreg get failed (%ld)\n",
5510 __func__, PTR_ERR(qup_vreg));
5511 }
5512#endif
5513}
5514
5515#ifdef CONFIG_I2C_SSBI
5516static struct msm_i2c_ssbi_platform_data msm_i2c_ssbi6_pdata = {
5517 .rsl_id = "D:PMIC_SSBI",
5518 .controller_type = MSM_SBI_CTRL_SSBI2,
5519};
5520
5521static struct msm_i2c_ssbi_platform_data msm_i2c_ssbi7_pdata = {
5522 .rsl_id = "D:CODEC_SSBI",
5523 .controller_type = MSM_SBI_CTRL_SSBI,
5524};
5525#endif
5526
Matt Wagantall6d9ebee2011-08-26 12:15:24 -07005527static struct acpuclk_platform_data msm7x30_clock_data __initdata = {
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005528 .acpu_switch_time_us = 50,
5529 .vdd_switch_time_us = 62,
Matt Wagantall6d9ebee2011-08-26 12:15:24 -07005530 .init = acpuclk_7x30_init,
Daniel Walker8d747cd2010-02-25 11:37:43 -08005531};
5532
5533static void __init msm7x30_init_irq(void)
5534{
5535 msm_init_irq();
5536}
5537
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005538static struct msm_gpio msm_nand_ebi2_cfg_data[] = {
5539 {GPIO_CFG(86, 1, GPIO_CFG_OUTPUT, GPIO_CFG_PULL_UP, GPIO_CFG_8MA), "ebi2_cs1"},
5540 {GPIO_CFG(115, 2, GPIO_CFG_OUTPUT, GPIO_CFG_PULL_UP, GPIO_CFG_8MA), "ebi2_busy1"},
5541};
5542
5543struct vreg *vreg_s3;
5544struct vreg *vreg_mmc;
5545
5546#if (defined(CONFIG_MMC_MSM_SDC1_SUPPORT)\
5547 || defined(CONFIG_MMC_MSM_SDC2_SUPPORT)\
5548 || defined(CONFIG_MMC_MSM_SDC3_SUPPORT)\
5549 || defined(CONFIG_MMC_MSM_SDC4_SUPPORT))
5550
5551struct sdcc_gpio {
5552 struct msm_gpio *cfg_data;
5553 uint32_t size;
5554 struct msm_gpio *sleep_cfg_data;
5555};
5556#if defined(CONFIG_MMC_MSM_SDC1_SUPPORT)
5557static struct msm_gpio sdc1_lvlshft_cfg_data[] = {
5558 {GPIO_CFG(35, 1, GPIO_CFG_OUTPUT, GPIO_CFG_PULL_UP, GPIO_CFG_16MA), "sdc1_lvlshft"},
5559};
5560#endif
5561static struct msm_gpio sdc1_cfg_data[] = {
5562 {GPIO_CFG(38, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_16MA), "sdc1_clk"},
5563 {GPIO_CFG(39, 1, GPIO_CFG_OUTPUT, GPIO_CFG_PULL_UP, GPIO_CFG_8MA), "sdc1_cmd"},
5564 {GPIO_CFG(40, 1, GPIO_CFG_OUTPUT, GPIO_CFG_PULL_UP, GPIO_CFG_8MA), "sdc1_dat_3"},
5565 {GPIO_CFG(41, 1, GPIO_CFG_OUTPUT, GPIO_CFG_PULL_UP, GPIO_CFG_8MA), "sdc1_dat_2"},
5566 {GPIO_CFG(42, 1, GPIO_CFG_OUTPUT, GPIO_CFG_PULL_UP, GPIO_CFG_8MA), "sdc1_dat_1"},
5567 {GPIO_CFG(43, 1, GPIO_CFG_OUTPUT, GPIO_CFG_PULL_UP, GPIO_CFG_8MA), "sdc1_dat_0"},
5568};
5569
5570static struct msm_gpio sdc2_cfg_data[] = {
5571 {GPIO_CFG(64, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_16MA), "sdc2_clk"},
5572 {GPIO_CFG(65, 1, GPIO_CFG_OUTPUT, GPIO_CFG_PULL_UP, GPIO_CFG_8MA), "sdc2_cmd"},
5573 {GPIO_CFG(66, 1, GPIO_CFG_OUTPUT, GPIO_CFG_PULL_UP, GPIO_CFG_8MA), "sdc2_dat_3"},
5574 {GPIO_CFG(67, 1, GPIO_CFG_OUTPUT, GPIO_CFG_PULL_UP, GPIO_CFG_8MA), "sdc2_dat_2"},
5575 {GPIO_CFG(68, 1, GPIO_CFG_OUTPUT, GPIO_CFG_PULL_UP, GPIO_CFG_8MA), "sdc2_dat_1"},
5576 {GPIO_CFG(69, 1, GPIO_CFG_OUTPUT, GPIO_CFG_PULL_UP, GPIO_CFG_8MA), "sdc2_dat_0"},
5577
5578#ifdef CONFIG_MMC_MSM_SDC2_8_BIT_SUPPORT
5579 {GPIO_CFG(115, 1, GPIO_CFG_OUTPUT, GPIO_CFG_PULL_UP, GPIO_CFG_8MA), "sdc2_dat_4"},
5580 {GPIO_CFG(114, 1, GPIO_CFG_OUTPUT, GPIO_CFG_PULL_UP, GPIO_CFG_8MA), "sdc2_dat_5"},
5581 {GPIO_CFG(113, 1, GPIO_CFG_OUTPUT, GPIO_CFG_PULL_UP, GPIO_CFG_8MA), "sdc2_dat_6"},
5582 {GPIO_CFG(112, 1, GPIO_CFG_OUTPUT, GPIO_CFG_PULL_UP, GPIO_CFG_8MA), "sdc2_dat_7"},
5583#endif
5584};
5585
5586static struct msm_gpio sdc3_cfg_data[] = {
5587 {GPIO_CFG(110, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_16MA), "sdc3_clk"},
5588 {GPIO_CFG(111, 1, GPIO_CFG_OUTPUT, GPIO_CFG_PULL_UP, GPIO_CFG_8MA), "sdc3_cmd"},
5589 {GPIO_CFG(116, 1, GPIO_CFG_OUTPUT, GPIO_CFG_PULL_UP, GPIO_CFG_8MA), "sdc3_dat_3"},
5590 {GPIO_CFG(117, 1, GPIO_CFG_OUTPUT, GPIO_CFG_PULL_UP, GPIO_CFG_8MA), "sdc3_dat_2"},
5591 {GPIO_CFG(118, 1, GPIO_CFG_OUTPUT, GPIO_CFG_PULL_UP, GPIO_CFG_8MA), "sdc3_dat_1"},
5592 {GPIO_CFG(119, 1, GPIO_CFG_OUTPUT, GPIO_CFG_PULL_UP, GPIO_CFG_8MA), "sdc3_dat_0"},
5593};
5594
5595static struct msm_gpio sdc3_sleep_cfg_data[] = {
5596 {GPIO_CFG(110, 0, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA),
5597 "sdc3_clk"},
5598 {GPIO_CFG(111, 0, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA),
5599 "sdc3_cmd"},
5600 {GPIO_CFG(116, 0, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA),
5601 "sdc3_dat_3"},
5602 {GPIO_CFG(117, 0, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA),
5603 "sdc3_dat_2"},
5604 {GPIO_CFG(118, 0, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA),
5605 "sdc3_dat_1"},
5606 {GPIO_CFG(119, 0, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA),
5607 "sdc3_dat_0"},
5608};
5609
5610static struct msm_gpio sdc4_cfg_data[] = {
5611 {GPIO_CFG(58, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_16MA), "sdc4_clk"},
5612 {GPIO_CFG(59, 1, GPIO_CFG_OUTPUT, GPIO_CFG_PULL_UP, GPIO_CFG_8MA), "sdc4_cmd"},
5613 {GPIO_CFG(60, 1, GPIO_CFG_OUTPUT, GPIO_CFG_PULL_UP, GPIO_CFG_8MA), "sdc4_dat_3"},
5614 {GPIO_CFG(61, 1, GPIO_CFG_OUTPUT, GPIO_CFG_PULL_UP, GPIO_CFG_8MA), "sdc4_dat_2"},
5615 {GPIO_CFG(62, 1, GPIO_CFG_OUTPUT, GPIO_CFG_PULL_UP, GPIO_CFG_8MA), "sdc4_dat_1"},
5616 {GPIO_CFG(63, 1, GPIO_CFG_OUTPUT, GPIO_CFG_PULL_UP, GPIO_CFG_8MA), "sdc4_dat_0"},
5617};
5618
5619static struct sdcc_gpio sdcc_cfg_data[] = {
5620 {
5621 .cfg_data = sdc1_cfg_data,
5622 .size = ARRAY_SIZE(sdc1_cfg_data),
5623 .sleep_cfg_data = NULL,
5624 },
5625 {
5626 .cfg_data = sdc2_cfg_data,
5627 .size = ARRAY_SIZE(sdc2_cfg_data),
5628 .sleep_cfg_data = NULL,
5629 },
5630 {
5631 .cfg_data = sdc3_cfg_data,
5632 .size = ARRAY_SIZE(sdc3_cfg_data),
5633 .sleep_cfg_data = sdc3_sleep_cfg_data,
5634 },
5635 {
5636 .cfg_data = sdc4_cfg_data,
5637 .size = ARRAY_SIZE(sdc4_cfg_data),
5638 .sleep_cfg_data = NULL,
5639 },
5640};
5641
5642struct sdcc_vreg {
5643 struct vreg *vreg_data;
5644 unsigned level;
5645};
5646
5647static struct sdcc_vreg sdcc_vreg_data[4];
5648
5649static unsigned long vreg_sts, gpio_sts;
5650
5651static uint32_t msm_sdcc_setup_gpio(int dev_id, unsigned int enable)
5652{
5653 int rc = 0;
5654 struct sdcc_gpio *curr;
5655
5656 curr = &sdcc_cfg_data[dev_id - 1];
5657
5658 if (!(test_bit(dev_id, &gpio_sts)^enable))
5659 return rc;
5660
5661 if (enable) {
5662 set_bit(dev_id, &gpio_sts);
5663 rc = msm_gpios_request_enable(curr->cfg_data, curr->size);
5664 if (rc)
5665 printk(KERN_ERR "%s: Failed to turn on GPIOs for slot %d\n",
5666 __func__, dev_id);
5667 } else {
5668 clear_bit(dev_id, &gpio_sts);
5669 if (curr->sleep_cfg_data) {
5670 msm_gpios_enable(curr->sleep_cfg_data, curr->size);
5671 msm_gpios_free(curr->sleep_cfg_data, curr->size);
5672 } else {
5673 msm_gpios_disable_free(curr->cfg_data, curr->size);
5674 }
5675 }
5676
5677 return rc;
5678}
5679
5680static uint32_t msm_sdcc_setup_vreg(int dev_id, unsigned int enable)
5681{
5682 int rc = 0;
5683 struct sdcc_vreg *curr;
5684 static int enabled_once[] = {0, 0, 0, 0};
5685
5686 curr = &sdcc_vreg_data[dev_id - 1];
5687
5688 if (!(test_bit(dev_id, &vreg_sts)^enable))
5689 return rc;
5690
5691 if (!enable || enabled_once[dev_id - 1])
5692 return 0;
5693
5694 if (enable) {
5695 set_bit(dev_id, &vreg_sts);
5696 rc = vreg_set_level(curr->vreg_data, curr->level);
5697 if (rc) {
5698 printk(KERN_ERR "%s: vreg_set_level() = %d \n",
5699 __func__, rc);
5700 }
5701 rc = vreg_enable(curr->vreg_data);
5702 if (rc) {
5703 printk(KERN_ERR "%s: vreg_enable() = %d \n",
5704 __func__, rc);
5705 }
5706 enabled_once[dev_id - 1] = 1;
5707 } else {
5708 clear_bit(dev_id, &vreg_sts);
5709 rc = vreg_disable(curr->vreg_data);
5710 if (rc) {
5711 printk(KERN_ERR "%s: vreg_disable() = %d \n",
5712 __func__, rc);
5713 }
5714 }
5715 return rc;
5716}
5717
5718static uint32_t msm_sdcc_setup_power(struct device *dv, unsigned int vdd)
5719{
5720 int rc = 0;
5721 struct platform_device *pdev;
5722
5723 pdev = container_of(dv, struct platform_device, dev);
5724 rc = msm_sdcc_setup_gpio(pdev->id, (vdd ? 1 : 0));
5725 if (rc)
5726 goto out;
5727
5728 if (pdev->id == 4) /* S3 is always ON and cannot be disabled */
5729 rc = msm_sdcc_setup_vreg(pdev->id, (vdd ? 1 : 0));
5730out:
5731 return rc;
5732}
5733
5734#if defined(CONFIG_MMC_MSM_SDC1_SUPPORT) && \
5735 defined(CONFIG_CSDIO_VENDOR_ID) && \
5736 defined(CONFIG_CSDIO_DEVICE_ID) && \
5737 (CONFIG_CSDIO_VENDOR_ID == 0x70 && CONFIG_CSDIO_DEVICE_ID == 0x1117)
5738
5739#define MBP_ON 1
5740#define MBP_OFF 0
5741
5742#define MBP_RESET_N \
5743 GPIO_CFG(44, 0, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_8MA)
5744#define MBP_INT0 \
5745 GPIO_CFG(46, 0, GPIO_CFG_INPUT, GPIO_CFG_PULL_UP, GPIO_CFG_8MA)
5746
5747#define MBP_MODE_CTRL_0 \
5748 GPIO_CFG(35, 0, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA)
5749#define MBP_MODE_CTRL_1 \
5750 GPIO_CFG(36, 0, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA)
5751#define MBP_MODE_CTRL_2 \
5752 GPIO_CFG(34, 0, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA)
5753#define TSIF_EN \
5754 GPIO_CFG(35, 1, GPIO_CFG_INPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA)
5755#define TSIF_DATA \
5756 GPIO_CFG(36, 1, GPIO_CFG_INPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA)
5757#define TSIF_CLK \
5758 GPIO_CFG(34, 1, GPIO_CFG_INPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA)
5759
5760static struct msm_gpio mbp_cfg_data[] = {
5761 {GPIO_CFG(44, 0, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_16MA),
5762 "mbp_reset"},
5763 {GPIO_CFG(85, 0, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_16MA),
5764 "mbp_io_voltage"},
5765};
5766
5767static int mbp_config_gpios_pre_init(int enable)
5768{
5769 int rc = 0;
5770
5771 if (enable) {
5772 rc = msm_gpios_request_enable(mbp_cfg_data,
5773 ARRAY_SIZE(mbp_cfg_data));
5774 if (rc) {
5775 printk(KERN_ERR
5776 "%s: Failed to turnon GPIOs for mbp chip(%d)\n",
5777 __func__, rc);
5778 }
5779 } else
5780 msm_gpios_disable_free(mbp_cfg_data, ARRAY_SIZE(mbp_cfg_data));
5781 return rc;
5782}
5783
5784static int mbp_setup_rf_vregs(int state)
5785{
5786 struct vreg *vreg_rf = NULL;
5787 struct vreg *vreg_rf_switch = NULL;
5788 int rc;
5789
5790 vreg_rf = vreg_get(NULL, "s2");
5791 if (IS_ERR(vreg_rf)) {
5792 pr_err("%s: s2 vreg get failed (%ld)",
5793 __func__, PTR_ERR(vreg_rf));
5794 return -EFAULT;
5795 }
5796 vreg_rf_switch = vreg_get(NULL, "rf");
5797 if (IS_ERR(vreg_rf_switch)) {
5798 pr_err("%s: rf vreg get failed (%ld)",
5799 __func__, PTR_ERR(vreg_rf_switch));
5800 return -EFAULT;
5801 }
5802
5803 if (state) {
5804 rc = vreg_set_level(vreg_rf, 1300);
5805 if (rc) {
5806 pr_err("%s: vreg s2 set level failed (%d)\n",
5807 __func__, rc);
5808 return rc;
5809 }
5810
5811 rc = vreg_enable(vreg_rf);
5812 if (rc) {
5813 printk(KERN_ERR "%s: vreg_enable(s2) = %d\n",
5814 __func__, rc);
5815 }
5816
5817 rc = vreg_set_level(vreg_rf_switch, 2600);
5818 if (rc) {
5819 pr_err("%s: vreg rf switch set level failed (%d)\n",
5820 __func__, rc);
5821 return rc;
5822 }
5823 rc = vreg_enable(vreg_rf_switch);
5824 if (rc) {
5825 printk(KERN_ERR "%s: vreg_enable(rf) = %d\n",
5826 __func__, rc);
5827 }
5828 } else {
5829 (void) vreg_disable(vreg_rf);
5830 (void) vreg_disable(vreg_rf_switch);
5831 }
5832 return 0;
5833}
5834
5835static int mbp_setup_vregs(int state)
5836{
5837 struct vreg *vreg_analog = NULL;
5838 struct vreg *vreg_io = NULL;
5839 int rc;
5840
5841 vreg_analog = vreg_get(NULL, "gp4");
5842 if (IS_ERR(vreg_analog)) {
5843 pr_err("%s: gp4 vreg get failed (%ld)",
5844 __func__, PTR_ERR(vreg_analog));
5845 return -EFAULT;
5846 }
5847 vreg_io = vreg_get(NULL, "s3");
5848 if (IS_ERR(vreg_io)) {
5849 pr_err("%s: s3 vreg get failed (%ld)",
5850 __func__, PTR_ERR(vreg_io));
5851 return -EFAULT;
5852 }
5853 if (state) {
5854 rc = vreg_set_level(vreg_analog, 2600);
5855 if (rc) {
5856 pr_err("%s: vreg_set_level failed (%d)",
5857 __func__, rc);
5858 }
5859 rc = vreg_enable(vreg_analog);
5860 if (rc) {
5861 pr_err("%s: analog vreg enable failed (%d)",
5862 __func__, rc);
5863 }
5864 rc = vreg_set_level(vreg_io, 1800);
5865 if (rc) {
5866 pr_err("%s: vreg_set_level failed (%d)",
5867 __func__, rc);
5868 }
5869 rc = vreg_enable(vreg_io);
5870 if (rc) {
5871 pr_err("%s: io vreg enable failed (%d)",
5872 __func__, rc);
5873 }
5874 } else {
5875 rc = vreg_disable(vreg_analog);
5876 if (rc) {
5877 pr_err("%s: analog vreg disable failed (%d)",
5878 __func__, rc);
5879 }
5880 rc = vreg_disable(vreg_io);
5881 if (rc) {
5882 pr_err("%s: io vreg disable failed (%d)",
5883 __func__, rc);
5884 }
5885 }
5886 return rc;
5887}
5888
5889static int mbp_set_tcxo_en(int enable)
5890{
5891 int rc;
5892 const char *id = "UBMC";
5893 struct vreg *vreg_analog = NULL;
5894
5895 rc = pmapp_clock_vote(id, PMAPP_CLOCK_ID_A1,
5896 enable ? PMAPP_CLOCK_VOTE_ON : PMAPP_CLOCK_VOTE_OFF);
5897 if (rc < 0) {
5898 printk(KERN_ERR "%s: unable to %svote for a1 clk\n",
5899 __func__, enable ? "" : "de-");
5900 return -EIO;
5901 }
5902 if (!enable) {
5903 vreg_analog = vreg_get(NULL, "gp4");
5904 if (IS_ERR(vreg_analog)) {
5905 pr_err("%s: gp4 vreg get failed (%ld)",
5906 __func__, PTR_ERR(vreg_analog));
5907 return -EFAULT;
5908 }
5909
5910 (void) vreg_disable(vreg_analog);
5911 }
5912 return rc;
5913}
5914
5915static void mbp_set_freeze_io(int state)
5916{
5917 if (state)
5918 gpio_set_value(85, 0);
5919 else
5920 gpio_set_value(85, 1);
5921}
5922
5923static int mbp_set_core_voltage_en(int enable)
5924{
5925 int rc;
5926 struct vreg *vreg_core1p2 = NULL;
5927
5928 vreg_core1p2 = vreg_get(NULL, "gp16");
5929 if (IS_ERR(vreg_core1p2)) {
5930 pr_err("%s: gp16 vreg get failed (%ld)",
5931 __func__, PTR_ERR(vreg_core1p2));
5932 return -EFAULT;
5933 }
5934 if (enable) {
5935 rc = vreg_set_level(vreg_core1p2, 1200);
5936 if (rc) {
5937 pr_err("%s: vreg_set_level failed (%d)",
5938 __func__, rc);
5939 }
5940 (void) vreg_enable(vreg_core1p2);
5941
5942 return 80;
5943 } else {
5944 gpio_set_value(85, 1);
5945 return 0;
5946 }
5947 return rc;
5948}
5949
5950static void mbp_set_reset(int state)
5951{
5952 if (state)
5953 gpio_set_value(GPIO_PIN(MBP_RESET_N), 0);
5954 else
5955 gpio_set_value(GPIO_PIN(MBP_RESET_N), 1);
5956}
5957
5958static int mbp_config_interface_mode(int state)
5959{
5960 if (state) {
5961 gpio_tlmm_config(MBP_MODE_CTRL_0, GPIO_CFG_ENABLE);
5962 gpio_tlmm_config(MBP_MODE_CTRL_1, GPIO_CFG_ENABLE);
5963 gpio_tlmm_config(MBP_MODE_CTRL_2, GPIO_CFG_ENABLE);
5964 gpio_set_value(GPIO_PIN(MBP_MODE_CTRL_0), 0);
5965 gpio_set_value(GPIO_PIN(MBP_MODE_CTRL_1), 1);
5966 gpio_set_value(GPIO_PIN(MBP_MODE_CTRL_2), 0);
5967 } else {
5968 gpio_tlmm_config(MBP_MODE_CTRL_0, GPIO_CFG_DISABLE);
5969 gpio_tlmm_config(MBP_MODE_CTRL_1, GPIO_CFG_DISABLE);
5970 gpio_tlmm_config(MBP_MODE_CTRL_2, GPIO_CFG_DISABLE);
5971 }
5972 return 0;
5973}
5974
5975static int mbp_setup_adc_vregs(int state)
5976{
5977 struct vreg *vreg_adc = NULL;
5978 int rc;
5979
5980 vreg_adc = vreg_get(NULL, "s4");
5981 if (IS_ERR(vreg_adc)) {
5982 pr_err("%s: s4 vreg get failed (%ld)",
5983 __func__, PTR_ERR(vreg_adc));
5984 return -EFAULT;
5985 }
5986 if (state) {
5987 rc = vreg_set_level(vreg_adc, 2200);
5988 if (rc) {
5989 pr_err("%s: vreg_set_level failed (%d)",
5990 __func__, rc);
5991 }
5992 rc = vreg_enable(vreg_adc);
5993 if (rc) {
5994 pr_err("%s: enable vreg adc failed (%d)",
5995 __func__, rc);
5996 }
5997 } else {
5998 rc = vreg_disable(vreg_adc);
5999 if (rc) {
6000 pr_err("%s: disable vreg adc failed (%d)",
6001 __func__, rc);
6002 }
6003 }
6004 return rc;
6005}
6006
6007static int mbp_power_up(void)
6008{
6009 int rc;
6010
6011 rc = mbp_config_gpios_pre_init(MBP_ON);
6012 if (rc)
6013 goto exit;
6014 pr_debug("%s: mbp_config_gpios_pre_init() done\n", __func__);
6015
6016 rc = mbp_setup_vregs(MBP_ON);
6017 if (rc)
6018 goto exit;
6019 pr_debug("%s: gp4 (2.6) and s3 (1.8) done\n", __func__);
6020
6021 rc = mbp_set_tcxo_en(MBP_ON);
6022 if (rc)
6023 goto exit;
6024 pr_debug("%s: tcxo clock done\n", __func__);
6025
6026 mbp_set_freeze_io(MBP_OFF);
6027 pr_debug("%s: set gpio 85 to 1 done\n", __func__);
6028
6029 udelay(100);
6030 mbp_set_reset(MBP_ON);
6031
6032 udelay(300);
6033 rc = mbp_config_interface_mode(MBP_ON);
6034 if (rc)
6035 goto exit;
6036 pr_debug("%s: mbp_config_interface_mode() done\n", __func__);
6037
6038 udelay(100 + mbp_set_core_voltage_en(MBP_ON));
6039 pr_debug("%s: power gp16 1.2V done\n", __func__);
6040
6041 mbp_set_freeze_io(MBP_ON);
6042 pr_debug("%s: set gpio 85 to 0 done\n", __func__);
6043
6044 udelay(100);
6045
6046 rc = mbp_setup_rf_vregs(MBP_ON);
6047 if (rc)
6048 goto exit;
6049 pr_debug("%s: s2 1.3V and rf 2.6V done\n", __func__);
6050
6051 rc = mbp_setup_adc_vregs(MBP_ON);
6052 if (rc)
6053 goto exit;
6054 pr_debug("%s: s4 2.2V done\n", __func__);
6055
6056 udelay(200);
6057
6058 mbp_set_reset(MBP_OFF);
6059 pr_debug("%s: close gpio 44 done\n", __func__);
6060
6061 msleep(20);
6062exit:
6063 return rc;
6064}
6065
6066static int mbp_power_down(void)
6067{
6068 int rc;
6069 struct vreg *vreg_adc = NULL;
6070
6071 vreg_adc = vreg_get(NULL, "s4");
6072 if (IS_ERR(vreg_adc)) {
6073 pr_err("%s: s4 vreg get failed (%ld)",
6074 __func__, PTR_ERR(vreg_adc));
6075 return -EFAULT;
6076 }
6077
6078 mbp_set_reset(MBP_ON);
6079 pr_debug("%s: mbp_set_reset(MBP_ON) done\n", __func__);
6080
6081 udelay(100);
6082
6083 rc = mbp_setup_adc_vregs(MBP_OFF);
6084 if (rc)
6085 goto exit;
6086 pr_debug("%s: vreg_disable(vreg_adc) done\n", __func__);
6087
6088 udelay(5);
6089
6090 rc = mbp_setup_rf_vregs(MBP_OFF);
6091 if (rc)
6092 goto exit;
6093 pr_debug("%s: mbp_setup_rf_vregs(MBP_OFF) done\n", __func__);
6094
6095 udelay(5);
6096
6097 mbp_set_freeze_io(MBP_OFF);
6098 pr_debug("%s: mbp_set_freeze_io(MBP_OFF) done\n", __func__);
6099
6100 udelay(100);
6101 rc = mbp_set_core_voltage_en(MBP_OFF);
6102 if (rc)
6103 goto exit;
6104 pr_debug("%s: mbp_set_core_voltage_en(MBP_OFF) done\n", __func__);
6105
6106 gpio_set_value(85, 1);
6107
6108 rc = mbp_set_tcxo_en(MBP_OFF);
6109 if (rc)
6110 goto exit;
6111 pr_debug("%s: mbp_set_tcxo_en(MBP_OFF) done\n", __func__);
6112
6113 rc = mbp_config_gpios_pre_init(MBP_OFF);
6114 if (rc)
6115 goto exit;
6116exit:
6117 return rc;
6118}
6119
6120static void (*mbp_status_notify_cb)(int card_present, void *dev_id);
6121static void *mbp_status_notify_cb_devid;
6122static int mbp_power_status;
6123static int mbp_power_init_done;
6124
6125static uint32_t mbp_setup_power(struct device *dv,
6126 unsigned int power_status)
6127{
6128 int rc = 0;
6129 struct platform_device *pdev;
6130
6131 pdev = container_of(dv, struct platform_device, dev);
6132
6133 if (power_status == mbp_power_status)
6134 goto exit;
6135 if (power_status) {
6136 pr_debug("turn on power of mbp slot");
6137 rc = mbp_power_up();
6138 mbp_power_status = 1;
6139 } else {
6140 pr_debug("turn off power of mbp slot");
6141 rc = mbp_power_down();
6142 mbp_power_status = 0;
6143 }
6144exit:
6145 return rc;
6146};
6147
6148int mbp_register_status_notify(void (*callback)(int, void *),
6149 void *dev_id)
6150{
6151 mbp_status_notify_cb = callback;
6152 mbp_status_notify_cb_devid = dev_id;
6153 return 0;
6154}
6155
6156static unsigned int mbp_status(struct device *dev)
6157{
6158 return mbp_power_status;
6159}
6160
6161static uint32_t msm_sdcc_setup_power_mbp(struct device *dv, unsigned int vdd)
6162{
6163 struct platform_device *pdev;
6164 uint32_t rc = 0;
6165
6166 pdev = container_of(dv, struct platform_device, dev);
6167 rc = msm_sdcc_setup_power(dv, vdd);
6168 if (rc) {
6169 pr_err("%s: Failed to setup power (%d)\n",
6170 __func__, rc);
6171 goto out;
6172 }
6173 if (!mbp_power_init_done) {
6174 mbp_setup_power(dv, 1);
6175 mbp_setup_power(dv, 0);
6176 mbp_power_init_done = 1;
6177 }
6178 if (vdd >= 0x8000) {
6179 rc = mbp_setup_power(dv, (0x8000 == vdd) ? 0 : 1);
6180 if (rc) {
6181 pr_err("%s: Failed to config mbp chip power (%d)\n",
6182 __func__, rc);
6183 goto out;
6184 }
6185 if (mbp_status_notify_cb) {
6186 mbp_status_notify_cb(mbp_power_status,
6187 mbp_status_notify_cb_devid);
6188 }
6189 }
6190out:
6191 /* should return 0 only */
6192 return 0;
6193}
6194
6195#endif
6196
6197#endif
6198
6199#ifdef CONFIG_MMC_MSM_SDC4_SUPPORT
6200#ifdef CONFIG_MMC_MSM_CARD_HW_DETECTION
6201static unsigned int msm7x30_sdcc_slot_status(struct device *dev)
6202{
6203 return (unsigned int)
6204 gpio_get_value_cansleep(
6205 PM8058_GPIO_PM_TO_SYS(PMIC_GPIO_SD_DET - 1));
6206}
6207#endif
6208
6209static int msm_sdcc_get_wpswitch(struct device *dv)
6210{
6211 void __iomem *wp_addr = 0;
6212 uint32_t ret = 0;
6213 struct platform_device *pdev;
6214
6215 if (!(machine_is_msm7x30_surf()))
6216 return -1;
6217 pdev = container_of(dv, struct platform_device, dev);
6218
6219 wp_addr = ioremap(FPGA_SDCC_STATUS, 4);
6220 if (!wp_addr) {
6221 pr_err("%s: Could not remap %x\n", __func__, FPGA_SDCC_STATUS);
6222 return -ENOMEM;
6223 }
6224
6225 ret = (((readl(wp_addr) >> 4) >> (pdev->id-1)) & 0x01);
6226 pr_info("%s: WP Status for Slot %d = 0x%x \n", __func__,
6227 pdev->id, ret);
6228 iounmap(wp_addr);
6229
6230 return ret;
6231}
6232#endif
6233
6234#if defined(CONFIG_MMC_MSM_SDC1_SUPPORT)
6235#if defined(CONFIG_CSDIO_VENDOR_ID) && \
6236 defined(CONFIG_CSDIO_DEVICE_ID) && \
6237 (CONFIG_CSDIO_VENDOR_ID == 0x70 && CONFIG_CSDIO_DEVICE_ID == 0x1117)
6238static struct mmc_platform_data msm7x30_sdc1_data = {
6239 .ocr_mask = MMC_VDD_165_195 | MMC_VDD_27_28 | MMC_VDD_28_29,
6240 .translate_vdd = msm_sdcc_setup_power_mbp,
6241 .mmc_bus_width = MMC_CAP_4_BIT_DATA,
6242 .status = mbp_status,
6243 .register_status_notify = mbp_register_status_notify,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07006244 .msmsdcc_fmin = 144000,
6245 .msmsdcc_fmid = 24576000,
6246 .msmsdcc_fmax = 24576000,
6247 .nonremovable = 0,
6248};
6249#else
6250static struct mmc_platform_data msm7x30_sdc1_data = {
6251 .ocr_mask = MMC_VDD_165_195,
6252 .translate_vdd = msm_sdcc_setup_power,
6253 .mmc_bus_width = MMC_CAP_4_BIT_DATA,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07006254 .msmsdcc_fmin = 144000,
6255 .msmsdcc_fmid = 24576000,
6256 .msmsdcc_fmax = 49152000,
6257 .nonremovable = 0,
6258};
6259#endif
6260#endif
6261
6262#ifdef CONFIG_MMC_MSM_SDC2_SUPPORT
6263static struct mmc_platform_data msm7x30_sdc2_data = {
6264 .ocr_mask = MMC_VDD_165_195 | MMC_VDD_27_28,
6265 .translate_vdd = msm_sdcc_setup_power,
6266#ifdef CONFIG_MMC_MSM_SDC2_8_BIT_SUPPORT
6267 .mmc_bus_width = MMC_CAP_8_BIT_DATA,
6268#else
6269 .mmc_bus_width = MMC_CAP_4_BIT_DATA,
6270#endif
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07006271 .msmsdcc_fmin = 144000,
6272 .msmsdcc_fmid = 24576000,
6273 .msmsdcc_fmax = 49152000,
6274 .nonremovable = 1,
6275};
6276#endif
6277
6278#ifdef CONFIG_MMC_MSM_SDC3_SUPPORT
6279static struct mmc_platform_data msm7x30_sdc3_data = {
6280 .ocr_mask = MMC_VDD_27_28 | MMC_VDD_28_29,
6281 .translate_vdd = msm_sdcc_setup_power,
6282 .mmc_bus_width = MMC_CAP_4_BIT_DATA,
6283#ifdef CONFIG_MMC_MSM_SDIO_SUPPORT
6284 .sdiowakeup_irq = MSM_GPIO_TO_INT(118),
6285#endif
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07006286 .msmsdcc_fmin = 144000,
6287 .msmsdcc_fmid = 24576000,
6288 .msmsdcc_fmax = 49152000,
6289 .nonremovable = 0,
6290};
6291#endif
6292
6293#ifdef CONFIG_MMC_MSM_SDC4_SUPPORT
6294static struct mmc_platform_data msm7x30_sdc4_data = {
6295 .ocr_mask = MMC_VDD_27_28 | MMC_VDD_28_29,
6296 .translate_vdd = msm_sdcc_setup_power,
6297 .mmc_bus_width = MMC_CAP_4_BIT_DATA,
6298#ifdef CONFIG_MMC_MSM_CARD_HW_DETECTION
6299 .status = msm7x30_sdcc_slot_status,
6300 .status_irq = PM8058_GPIO_IRQ(PMIC8058_IRQ_BASE, PMIC_GPIO_SD_DET - 1),
6301 .irq_flags = IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING,
6302#endif
6303 .wpswitch = msm_sdcc_get_wpswitch,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07006304 .msmsdcc_fmin = 144000,
6305 .msmsdcc_fmid = 24576000,
6306 .msmsdcc_fmax = 49152000,
6307 .nonremovable = 0,
6308};
6309#endif
6310
6311#ifdef CONFIG_MMC_MSM_SDC1_SUPPORT
6312static void msm_sdc1_lvlshft_enable(void)
6313{
6314 int rc;
6315
6316 /* Enable LDO5, an input to the FET that powers slot 1 */
6317 rc = vreg_set_level(vreg_mmc, 2850);
6318 if (rc)
6319 printk(KERN_ERR "%s: vreg_set_level() = %d \n", __func__, rc);
6320
6321 rc = vreg_enable(vreg_mmc);
6322 if (rc)
6323 printk(KERN_ERR "%s: vreg_enable() = %d \n", __func__, rc);
6324
6325 /* Enable GPIO 35, to turn on the FET that powers slot 1 */
6326 rc = msm_gpios_request_enable(sdc1_lvlshft_cfg_data,
6327 ARRAY_SIZE(sdc1_lvlshft_cfg_data));
6328 if (rc)
6329 printk(KERN_ERR "%s: Failed to enable GPIO 35\n", __func__);
6330
6331 rc = gpio_direction_output(GPIO_PIN(sdc1_lvlshft_cfg_data[0].gpio_cfg),
6332 1);
6333 if (rc)
6334 printk(KERN_ERR "%s: Failed to turn on GPIO 35\n", __func__);
6335}
6336#endif
6337
6338static void __init msm7x30_init_mmc(void)
6339{
6340 vreg_s3 = vreg_get(NULL, "s3");
6341 if (IS_ERR(vreg_s3)) {
6342 printk(KERN_ERR "%s: vreg get failed (%ld)\n",
6343 __func__, PTR_ERR(vreg_s3));
6344 return;
6345 }
6346
6347 vreg_mmc = vreg_get(NULL, "mmc");
6348 if (IS_ERR(vreg_mmc)) {
6349 printk(KERN_ERR "%s: vreg get failed (%ld)\n",
6350 __func__, PTR_ERR(vreg_mmc));
6351 return;
6352 }
6353
6354#ifdef CONFIG_MMC_MSM_SDC1_SUPPORT
6355 if (machine_is_msm7x30_fluid()) {
6356 msm7x30_sdc1_data.ocr_mask = MMC_VDD_27_28 | MMC_VDD_28_29;
6357 msm_sdc1_lvlshft_enable();
6358 }
6359 sdcc_vreg_data[0].vreg_data = vreg_s3;
6360 sdcc_vreg_data[0].level = 1800;
6361 msm_add_sdcc(1, &msm7x30_sdc1_data);
6362#endif
6363#ifdef CONFIG_MMC_MSM_SDC2_SUPPORT
6364 if (machine_is_msm8x55_svlte_surf())
6365 msm7x30_sdc2_data.msmsdcc_fmax = 24576000;
6366 sdcc_vreg_data[1].vreg_data = vreg_s3;
6367 sdcc_vreg_data[1].level = 1800;
6368 msm_add_sdcc(2, &msm7x30_sdc2_data);
6369#endif
6370#ifdef CONFIG_MMC_MSM_SDC3_SUPPORT
6371 sdcc_vreg_data[2].vreg_data = vreg_s3;
6372 sdcc_vreg_data[2].level = 1800;
6373 msm_sdcc_setup_gpio(3, 1);
6374 msm_add_sdcc(3, &msm7x30_sdc3_data);
6375#endif
6376#ifdef CONFIG_MMC_MSM_SDC4_SUPPORT
6377 sdcc_vreg_data[3].vreg_data = vreg_mmc;
6378 sdcc_vreg_data[3].level = 2850;
6379 msm_add_sdcc(4, &msm7x30_sdc4_data);
6380#endif
6381
6382}
6383
6384static void __init msm7x30_init_nand(void)
6385{
6386 char *build_id;
6387 struct flash_platform_data *plat_data;
6388
6389 build_id = socinfo_get_build_id();
6390 if (build_id == NULL) {
6391 pr_err("%s: Build ID not available from socinfo\n", __func__);
6392 return;
6393 }
6394
6395 if (build_id[8] == 'C' &&
6396 !msm_gpios_request_enable(msm_nand_ebi2_cfg_data,
6397 ARRAY_SIZE(msm_nand_ebi2_cfg_data))) {
6398 plat_data = msm_device_nand.dev.platform_data;
6399 plat_data->interleave = 1;
6400 printk(KERN_INFO "%s: Interleave mode Build ID found\n",
6401 __func__);
6402 }
6403}
6404
6405#ifdef CONFIG_SERIAL_MSM_CONSOLE
6406static struct msm_gpio uart2_config_data[] = {
6407 { GPIO_CFG(49, 2, GPIO_CFG_OUTPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA), "UART2_RFR"},
6408 { GPIO_CFG(50, 2, GPIO_CFG_INPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA), "UART2_CTS"},
6409 { GPIO_CFG(51, 2, GPIO_CFG_INPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA), "UART2_Rx"},
6410 { GPIO_CFG(52, 2, GPIO_CFG_OUTPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA), "UART2_Tx"},
6411};
6412
6413static void msm7x30_init_uart2(void)
6414{
6415 msm_gpios_request_enable(uart2_config_data,
6416 ARRAY_SIZE(uart2_config_data));
6417
6418}
6419#endif
6420
6421/* TSIF begin */
6422#if defined(CONFIG_TSIF) || defined(CONFIG_TSIF_MODULE)
6423
6424#define TSIF_B_SYNC GPIO_CFG(37, 1, GPIO_CFG_INPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA)
6425#define TSIF_B_DATA GPIO_CFG(36, 1, GPIO_CFG_INPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA)
6426#define TSIF_B_EN GPIO_CFG(35, 1, GPIO_CFG_INPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA)
6427#define TSIF_B_CLK GPIO_CFG(34, 1, GPIO_CFG_INPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA)
6428
6429static const struct msm_gpio tsif_gpios[] = {
6430 { .gpio_cfg = TSIF_B_CLK, .label = "tsif_clk", },
6431 { .gpio_cfg = TSIF_B_EN, .label = "tsif_en", },
6432 { .gpio_cfg = TSIF_B_DATA, .label = "tsif_data", },
6433 { .gpio_cfg = TSIF_B_SYNC, .label = "tsif_sync", },
6434};
6435
6436static struct msm_tsif_platform_data tsif_platform_data = {
6437 .num_gpios = ARRAY_SIZE(tsif_gpios),
6438 .gpios = tsif_gpios,
6439 .tsif_pclk = "tsif_pclk",
6440 .tsif_ref_clk = "tsif_ref_clk",
6441};
6442#endif /* defined(CONFIG_TSIF) || defined(CONFIG_TSIF_MODULE) */
6443/* TSIF end */
6444
6445static void __init pmic8058_leds_init(void)
6446{
6447 if (machine_is_msm7x30_surf()) {
6448 pm8058_7x30_data.sub_devices[PM8058_SUBDEV_LED].platform_data
6449 = &pm8058_surf_leds_data;
6450 } else if (!machine_is_msm7x30_fluid()) {
6451 pm8058_7x30_data.sub_devices[PM8058_SUBDEV_LED].platform_data
6452 = &pm8058_ffa_leds_data;
6453 } else if (machine_is_msm7x30_fluid()) {
6454 pm8058_7x30_data.sub_devices[PM8058_SUBDEV_LED].platform_data
6455 = &pm8058_fluid_leds_data;
6456 }
6457}
6458
6459static struct msm_spm_platform_data msm_spm_data __initdata = {
6460 .reg_base_addr = MSM_SAW_BASE,
6461
6462 .reg_init_values[MSM_SPM_REG_SAW_CFG] = 0x05,
6463 .reg_init_values[MSM_SPM_REG_SAW_SPM_CTL] = 0x18,
6464 .reg_init_values[MSM_SPM_REG_SAW_SPM_SLP_TMR_DLY] = 0x00006666,
6465 .reg_init_values[MSM_SPM_REG_SAW_SPM_WAKE_TMR_DLY] = 0xFF000666,
6466
6467 .reg_init_values[MSM_SPM_REG_SAW_SLP_CLK_EN] = 0x01,
6468 .reg_init_values[MSM_SPM_REG_SAW_SLP_HSFS_PRECLMP_EN] = 0x03,
6469 .reg_init_values[MSM_SPM_REG_SAW_SLP_HSFS_POSTCLMP_EN] = 0x00,
6470
6471 .reg_init_values[MSM_SPM_REG_SAW_SLP_CLMP_EN] = 0x01,
6472 .reg_init_values[MSM_SPM_REG_SAW_SLP_RST_EN] = 0x00,
6473 .reg_init_values[MSM_SPM_REG_SAW_SPM_MPM_CFG] = 0x00,
6474
6475 .awake_vlevel = 0xF2,
6476 .retention_vlevel = 0xE0,
6477 .collapse_vlevel = 0x72,
6478 .retention_mid_vlevel = 0xE0,
6479 .collapse_mid_vlevel = 0xE0,
6480
6481 .vctl_timeout_us = 50,
6482};
6483
6484#if defined(CONFIG_TOUCHSCREEN_TSC2007) || \
6485 defined(CONFIG_TOUCHSCREEN_TSC2007_MODULE)
6486
6487#define TSC2007_TS_PEN_INT 20
6488
6489static struct msm_gpio tsc2007_config_data[] = {
6490 { GPIO_CFG(TSC2007_TS_PEN_INT, 0, GPIO_CFG_INPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA),
6491 "tsc2007_irq" },
6492};
6493
6494static struct vreg *vreg_tsc_s3;
6495static struct vreg *vreg_tsc_s2;
6496
6497static int tsc2007_init(void)
6498{
6499 int rc;
6500
6501 vreg_tsc_s3 = vreg_get(NULL, "s3");
6502 if (IS_ERR(vreg_tsc_s3)) {
6503 printk(KERN_ERR "%s: vreg get failed (%ld)\n",
6504 __func__, PTR_ERR(vreg_tsc_s3));
6505 return -ENODEV;
6506 }
6507
6508 rc = vreg_set_level(vreg_tsc_s3, 1800);
6509 if (rc) {
6510 pr_err("%s: vreg_set_level failed \n", __func__);
6511 goto fail_vreg_set_level;
6512 }
6513
6514 rc = vreg_enable(vreg_tsc_s3);
6515 if (rc) {
6516 pr_err("%s: vreg_enable failed \n", __func__);
6517 goto fail_vreg_set_level;
6518 }
6519
6520 vreg_tsc_s2 = vreg_get(NULL, "s2");
6521 if (IS_ERR(vreg_tsc_s2)) {
6522 printk(KERN_ERR "%s: vreg get failed (%ld)\n",
6523 __func__, PTR_ERR(vreg_tsc_s2));
6524 goto fail_vreg_get;
6525 }
6526
6527 rc = vreg_set_level(vreg_tsc_s2, 1300);
6528 if (rc) {
6529 pr_err("%s: vreg_set_level failed \n", __func__);
6530 goto fail_vreg_s2_level;
6531 }
6532
6533 rc = vreg_enable(vreg_tsc_s2);
6534 if (rc) {
6535 pr_err("%s: vreg_enable failed \n", __func__);
6536 goto fail_vreg_s2_level;
6537 }
6538
6539 rc = msm_gpios_request_enable(tsc2007_config_data,
6540 ARRAY_SIZE(tsc2007_config_data));
6541 if (rc) {
6542 pr_err("%s: Unable to request gpios\n", __func__);
6543 goto fail_gpio_req;
6544 }
6545
6546 return 0;
6547
6548fail_gpio_req:
6549 vreg_disable(vreg_tsc_s2);
6550fail_vreg_s2_level:
6551 vreg_put(vreg_tsc_s2);
6552fail_vreg_get:
6553 vreg_disable(vreg_tsc_s3);
6554fail_vreg_set_level:
6555 vreg_put(vreg_tsc_s3);
6556 return rc;
6557}
6558
6559static int tsc2007_get_pendown_state(void)
6560{
6561 int rc;
6562
6563 rc = gpio_get_value(TSC2007_TS_PEN_INT);
6564 if (rc < 0) {
6565 pr_err("%s: MSM GPIO %d read failed\n", __func__,
6566 TSC2007_TS_PEN_INT);
6567 return rc;
6568 }
6569
6570 return (rc == 0 ? 1 : 0);
6571}
6572
6573static void tsc2007_exit(void)
6574{
6575 vreg_disable(vreg_tsc_s3);
6576 vreg_put(vreg_tsc_s3);
6577 vreg_disable(vreg_tsc_s2);
6578 vreg_put(vreg_tsc_s2);
6579
6580 msm_gpios_disable_free(tsc2007_config_data,
6581 ARRAY_SIZE(tsc2007_config_data));
6582}
6583
6584static int tsc2007_power_shutdown(bool enable)
6585{
6586 int rc;
6587
6588 if (enable == false) {
6589 rc = vreg_enable(vreg_tsc_s2);
6590 if (rc) {
6591 pr_err("%s: vreg_enable failed\n", __func__);
6592 return rc;
6593 }
6594 rc = vreg_enable(vreg_tsc_s3);
6595 if (rc) {
6596 pr_err("%s: vreg_enable failed\n", __func__);
6597 vreg_disable(vreg_tsc_s2);
6598 return rc;
6599 }
6600 /* Voltage settling delay */
6601 msleep(20);
6602 } else {
6603 rc = vreg_disable(vreg_tsc_s2);
6604 if (rc) {
6605 pr_err("%s: vreg_disable failed\n", __func__);
6606 return rc;
6607 }
6608 rc = vreg_disable(vreg_tsc_s3);
6609 if (rc) {
6610 pr_err("%s: vreg_disable failed\n", __func__);
6611 vreg_enable(vreg_tsc_s2);
6612 return rc;
6613 }
6614 }
6615
6616 return rc;
6617}
6618
6619static struct tsc2007_platform_data tsc2007_ts_data = {
6620 .model = 2007,
6621 .x_plate_ohms = 300,
6622 .irq_flags = IRQF_TRIGGER_LOW,
6623 .init_platform_hw = tsc2007_init,
6624 .exit_platform_hw = tsc2007_exit,
6625 .power_shutdown = tsc2007_power_shutdown,
6626 .invert_x = true,
6627 .invert_y = true,
6628 /* REVISIT: Temporary fix for reversed pressure */
6629 .invert_z1 = true,
6630 .invert_z2 = true,
6631 .get_pendown_state = tsc2007_get_pendown_state,
6632};
6633
6634static struct i2c_board_info tsc_i2c_board_info[] = {
6635 {
6636 I2C_BOARD_INFO("tsc2007", 0x48),
6637 .irq = MSM_GPIO_TO_INT(TSC2007_TS_PEN_INT),
6638 .platform_data = &tsc2007_ts_data,
6639 },
6640};
6641#endif
6642
6643static const char *vregs_isa1200_name[] = {
6644 "gp7",
6645 "gp10",
6646};
6647
6648static const int vregs_isa1200_val[] = {
6649 1800,
6650 2600,
6651};
6652static struct vreg *vregs_isa1200[ARRAY_SIZE(vregs_isa1200_name)];
6653
6654static int isa1200_power(int vreg_on)
6655{
6656 int i, rc = 0;
6657
6658 for (i = 0; i < ARRAY_SIZE(vregs_isa1200_name); i++) {
6659 if (!vregs_isa1200[i]) {
6660 pr_err("%s: vreg_get %s failed (%d)\n",
6661 __func__, vregs_isa1200_name[i], rc);
6662 goto vreg_fail;
6663 }
6664
6665 rc = vreg_on ? vreg_enable(vregs_isa1200[i]) :
6666 vreg_disable(vregs_isa1200[i]);
6667 if (rc < 0) {
6668 pr_err("%s: vreg %s %s failed (%d)\n",
6669 __func__, vregs_isa1200_name[i],
6670 vreg_on ? "enable" : "disable", rc);
6671 goto vreg_fail;
6672 }
6673 }
6674
6675 /* vote for DO buffer */
6676 rc = pmapp_clock_vote("VIBR", PMAPP_CLOCK_ID_DO,
6677 vreg_on ? PMAPP_CLOCK_VOTE_ON : PMAPP_CLOCK_VOTE_OFF);
6678 if (rc) {
6679 pr_err("%s: unable to %svote for d0 clk\n",
6680 __func__, vreg_on ? "" : "de-");
6681 goto vreg_fail;
6682 }
6683
6684 return 0;
6685
6686vreg_fail:
6687 while (i)
6688 vreg_disable(vregs_isa1200[--i]);
6689 return rc;
6690}
6691
6692static int isa1200_dev_setup(bool enable)
6693{
6694 int i, rc;
6695
6696 if (enable == true) {
6697 for (i = 0; i < ARRAY_SIZE(vregs_isa1200_name); i++) {
6698 vregs_isa1200[i] = vreg_get(NULL,
6699 vregs_isa1200_name[i]);
6700 if (IS_ERR(vregs_isa1200[i])) {
6701 pr_err("%s: vreg get %s failed (%ld)\n",
6702 __func__, vregs_isa1200_name[i],
6703 PTR_ERR(vregs_isa1200[i]));
6704 rc = PTR_ERR(vregs_isa1200[i]);
6705 goto vreg_get_fail;
6706 }
6707 rc = vreg_set_level(vregs_isa1200[i],
6708 vregs_isa1200_val[i]);
6709 if (rc) {
6710 pr_err("%s: vreg_set_level() = %d\n",
6711 __func__, rc);
6712 goto vreg_get_fail;
6713 }
6714 }
6715
6716 rc = gpio_tlmm_config(GPIO_CFG(HAP_LVL_SHFT_MSM_GPIO, 0,
6717 GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL,
6718 GPIO_CFG_2MA), GPIO_CFG_ENABLE);
6719 if (rc) {
6720 pr_err("%s: Could not configure gpio %d\n",
6721 __func__, HAP_LVL_SHFT_MSM_GPIO);
6722 goto vreg_get_fail;
6723 }
6724
6725 rc = gpio_request(HAP_LVL_SHFT_MSM_GPIO, "haptics_shft_lvl_oe");
6726 if (rc) {
6727 pr_err("%s: unable to request gpio %d (%d)\n",
6728 __func__, HAP_LVL_SHFT_MSM_GPIO, rc);
6729 goto vreg_get_fail;
6730 }
6731
6732 gpio_set_value(HAP_LVL_SHFT_MSM_GPIO, 1);
6733 } else {
6734 for (i = 0; i < ARRAY_SIZE(vregs_isa1200_name); i++)
6735 vreg_put(vregs_isa1200[i]);
6736
6737 gpio_free(HAP_LVL_SHFT_MSM_GPIO);
6738 }
6739
6740 return 0;
6741vreg_get_fail:
6742 while (i)
6743 vreg_put(vregs_isa1200[--i]);
6744 return rc;
6745}
6746static struct isa1200_platform_data isa1200_1_pdata = {
6747 .name = "vibrator",
6748 .power_on = isa1200_power,
6749 .dev_setup = isa1200_dev_setup,
6750 .pwm_ch_id = 1, /*channel id*/
6751 /*gpio to enable haptic*/
6752 .hap_en_gpio = PM8058_GPIO_PM_TO_SYS(PMIC_GPIO_HAP_ENABLE),
6753 .max_timeout = 15000,
6754 .mode_ctrl = PWM_GEN_MODE,
6755 .pwm_fd = {
6756 .pwm_div = 256,
6757 },
6758 .is_erm = false,
6759 .smart_en = true,
6760 .ext_clk_en = true,
6761 .chip_en = 1,
6762};
6763
6764static struct i2c_board_info msm_isa1200_board_info[] = {
6765 {
6766 I2C_BOARD_INFO("isa1200_1", 0x90>>1),
6767 .platform_data = &isa1200_1_pdata,
6768 },
6769};
6770
6771
6772static int kp_flip_mpp_config(void)
6773{
6774 return pm8058_mpp_config_digital_in(PM_FLIP_MPP,
6775 PM8058_MPP_DIG_LEVEL_S3, PM_MPP_DIN_TO_INT);
6776}
6777
6778static struct flip_switch_pdata flip_switch_data = {
6779 .name = "kp_flip_switch",
6780 .flip_gpio = PM8058_GPIO_PM_TO_SYS(PM8058_GPIOS) + PM_FLIP_MPP,
6781 .left_key = KEY_OPEN,
6782 .right_key = KEY_CLOSE,
6783 .active_low = 0,
6784 .wakeup = 1,
6785 .flip_mpp_config = kp_flip_mpp_config,
6786};
6787
6788static struct platform_device flip_switch_device = {
6789 .name = "kp_flip_switch",
6790 .id = -1,
6791 .dev = {
6792 .platform_data = &flip_switch_data,
6793 }
6794};
6795
6796static const char *vregs_tma300_name[] = {
6797 "gp6",
6798 "gp7",
6799};
6800
6801static const int vregs_tma300_val[] = {
6802 3050,
6803 1800,
6804};
6805static struct vreg *vregs_tma300[ARRAY_SIZE(vregs_tma300_name)];
6806
6807static int tma300_power(int vreg_on)
6808{
6809 int i, rc = -EINVAL;
6810
6811 for (i = 0; i < ARRAY_SIZE(vregs_tma300_name); i++) {
6812 /* Never disable gp6 for fluid as lcd has a problem with it */
6813 if (!i && !vreg_on)
6814 continue;
6815 if (!vregs_tma300[i]) {
6816 printk(KERN_ERR "%s: vreg_get %s failed (%d)\n",
6817 __func__, vregs_tma300_name[i], rc);
6818 return rc;
6819 }
6820
6821 rc = vreg_on ? vreg_enable(vregs_tma300[i]) :
6822 vreg_disable(vregs_tma300[i]);
6823 if (rc < 0) {
6824 printk(KERN_ERR "%s: vreg %s %s failed (%d)\n",
6825 __func__, vregs_tma300_name[i],
6826 vreg_on ? "enable" : "disable", rc);
6827 return rc;
6828 }
6829 }
6830
6831 return 0;
6832}
6833
6834#define TS_GPIO_IRQ 150
6835
6836static int tma300_dev_setup(bool enable)
6837{
6838 int i, rc;
6839
6840 if (enable) {
6841 /* get voltage sources */
6842 for (i = 0; i < ARRAY_SIZE(vregs_tma300_name); i++) {
6843 vregs_tma300[i] = vreg_get(NULL, vregs_tma300_name[i]);
6844 if (IS_ERR(vregs_tma300[i])) {
6845 pr_err("%s: vreg get %s failed (%ld)\n",
6846 __func__, vregs_tma300_name[i],
6847 PTR_ERR(vregs_tma300[i]));
6848 rc = PTR_ERR(vregs_tma300[i]);
6849 goto vreg_get_fail;
6850 }
6851 rc = vreg_set_level(vregs_tma300[i],
6852 vregs_tma300_val[i]);
6853 if (rc) {
6854 pr_err("%s: vreg_set_level() = %d\n",
6855 __func__, rc);
6856 i++;
6857 goto vreg_get_fail;
6858 }
6859 }
6860
6861 /* enable interrupt gpio */
6862 rc = gpio_tlmm_config(GPIO_CFG(TS_GPIO_IRQ, 0, GPIO_CFG_INPUT,
6863 GPIO_CFG_PULL_UP, GPIO_CFG_6MA), GPIO_CFG_ENABLE);
6864 if (rc) {
6865 pr_err("%s: Could not configure gpio %d\n",
6866 __func__, TS_GPIO_IRQ);
6867 goto vreg_get_fail;
6868 }
6869
6870 /* virtual keys */
6871 tma300_vkeys_attr.attr.name = "virtualkeys.msm_tma300_ts";
6872 properties_kobj = kobject_create_and_add("board_properties",
6873 NULL);
6874 if (!properties_kobj) {
6875 pr_err("%s: failed to create a kobject"
6876 "for board_properites\n", __func__);
6877 rc = -ENOMEM;
6878 goto vreg_get_fail;
6879 }
6880 rc = sysfs_create_group(properties_kobj,
6881 &tma300_properties_attr_group);
6882 if (rc) {
6883 pr_err("%s: failed to create a sysfs entry %s\n",
6884 __func__, tma300_vkeys_attr.attr.name);
6885 kobject_put(properties_kobj);
6886 goto vreg_get_fail;
6887 }
6888 } else {
6889 /* put voltage sources */
6890 for (i = 0; i < ARRAY_SIZE(vregs_tma300_name); i++)
6891 vreg_put(vregs_tma300[i]);
6892 /* destroy virtual keys */
6893 if (properties_kobj) {
6894 sysfs_remove_group(properties_kobj,
6895 &tma300_properties_attr_group);
6896 kobject_put(properties_kobj);
6897 }
6898 }
6899 return 0;
6900
6901vreg_get_fail:
6902 while (i)
6903 vreg_put(vregs_tma300[--i]);
6904 return rc;
6905}
6906
6907static struct cy8c_ts_platform_data cy8ctma300_pdata = {
6908 .power_on = tma300_power,
6909 .dev_setup = tma300_dev_setup,
6910 .ts_name = "msm_tma300_ts",
6911 .dis_min_x = 0,
6912 .dis_max_x = 479,
6913 .dis_min_y = 0,
6914 .dis_max_y = 799,
6915 .res_x = 479,
6916 .res_y = 1009,
6917 .min_tid = 1,
6918 .max_tid = 255,
6919 .min_touch = 0,
6920 .max_touch = 255,
6921 .min_width = 0,
6922 .max_width = 255,
6923 .invert_y = 1,
6924 .nfingers = 4,
6925 .irq_gpio = TS_GPIO_IRQ,
6926 .resout_gpio = -1,
6927};
6928
6929static struct i2c_board_info cy8ctma300_board_info[] = {
6930 {
6931 I2C_BOARD_INFO("cy8ctma300", 0x2),
6932 .platform_data = &cy8ctma300_pdata,
6933 }
6934};
6935
Daniel Walker8d747cd2010-02-25 11:37:43 -08006936static void __init msm7x30_init(void)
6937{
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07006938 int rc;
6939 unsigned smem_size;
6940 uint32_t usb_hub_gpio_cfg_value = GPIO_CFG(56,
6941 0,
6942 GPIO_CFG_OUTPUT,
6943 GPIO_CFG_NO_PULL,
6944 GPIO_CFG_2MA);
6945 uint32_t soc_version = 0;
Pavankumar Kondeti5155e2c2010-12-08 13:37:08 +05306946
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07006947 if (socinfo_init() < 0)
6948 printk(KERN_ERR "%s: socinfo_init() failed!\n",
6949 __func__);
6950
6951 soc_version = socinfo_get_version();
6952
Stephen Boydbb600ae2011-08-02 20:11:40 -07006953 msm_clock_init(&msm7x30_clock_init_data);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07006954#ifdef CONFIG_SERIAL_MSM_CONSOLE
6955 msm7x30_init_uart2();
6956#endif
6957 msm_spm_init(&msm_spm_data, 1);
Matt Wagantall6d9ebee2011-08-26 12:15:24 -07006958 acpuclk_init(&msm7x30_clock_data);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07006959 if (machine_is_msm7x30_surf() || machine_is_msm7x30_fluid())
6960 msm7x30_cfg_smsc911x();
6961
6962#ifdef CONFIG_USB_MSM_OTG_72K
6963 if (SOCINFO_VERSION_MAJOR(soc_version) >= 2 &&
6964 SOCINFO_VERSION_MINOR(soc_version) >= 1) {
6965 pr_debug("%s: SOC Version:2.(1 or more)\n", __func__);
6966 msm_otg_pdata.ldo_set_voltage = 0;
6967 }
6968
6969 msm_device_otg.dev.platform_data = &msm_otg_pdata;
6970#ifdef CONFIG_USB_GADGET
6971 msm_otg_pdata.swfi_latency =
6972 msm_pm_data
6973 [MSM_PM_SLEEP_MODE_RAMP_DOWN_AND_WAIT_FOR_INTERRUPT].latency;
6974 msm_device_gadget_peripheral.dev.platform_data = &msm_gadget_pdata;
6975#endif
6976#endif
6977 msm_uart_dm1_pdata.wakeup_irq = gpio_to_irq(136);
6978 msm_device_uart_dm1.dev.platform_data = &msm_uart_dm1_pdata;
6979#if defined(CONFIG_TSIF) || defined(CONFIG_TSIF_MODULE)
6980 msm_device_tsif.dev.platform_data = &tsif_platform_data;
6981#endif
6982 if (machine_is_msm7x30_fluid()) {
6983 msm_adc_pdata.dev_names = msm_adc_fluid_device_names;
6984 msm_adc_pdata.num_adc = ARRAY_SIZE(msm_adc_fluid_device_names);
6985 } else {
6986 msm_adc_pdata.dev_names = msm_adc_surf_device_names;
6987 msm_adc_pdata.num_adc = ARRAY_SIZE(msm_adc_surf_device_names);
6988 }
6989
6990 platform_add_devices(msm_footswitch_devices,
6991 msm_num_footswitch_devices);
Daniel Walker8d747cd2010-02-25 11:37:43 -08006992 platform_add_devices(devices, ARRAY_SIZE(devices));
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07006993#ifdef CONFIG_USB_EHCI_MSM_72K
6994 msm_add_host(0, &msm_usb_host_pdata);
6995#endif
6996 msm7x30_init_mmc();
6997 msm7x30_init_nand();
6998 msm_qsd_spi_init();
6999
7000#ifdef CONFIG_SPI_QSD
7001 if (machine_is_msm7x30_fluid())
7002 spi_register_board_info(lcdc_sharp_spi_board_info,
7003 ARRAY_SIZE(lcdc_sharp_spi_board_info));
7004 else
7005 spi_register_board_info(lcdc_toshiba_spi_board_info,
7006 ARRAY_SIZE(lcdc_toshiba_spi_board_info));
7007#endif
7008
7009 msm_fb_add_devices();
7010 msm_pm_set_platform_data(msm_pm_data, ARRAY_SIZE(msm_pm_data));
7011 msm_device_i2c_init();
7012 msm_device_i2c_2_init();
7013 qup_device_i2c_init();
7014 buses_init();
7015 msm7x30_init_marimba();
7016#ifdef CONFIG_MSM7KV2_AUDIO
7017 snddev_poweramp_gpio_init();
7018 aux_pcm_gpio_init();
7019#endif
7020
7021 i2c_register_board_info(0, msm_i2c_board_info,
7022 ARRAY_SIZE(msm_i2c_board_info));
7023
7024 if (!machine_is_msm8x55_svlte_ffa() && !machine_is_msm7x30_fluid())
7025 marimba_pdata.tsadc = &marimba_tsadc_pdata;
7026
7027 if (machine_is_msm7x30_fluid())
7028 i2c_register_board_info(0, cy8info,
7029 ARRAY_SIZE(cy8info));
7030#ifdef CONFIG_BOSCH_BMA150
7031 if (machine_is_msm7x30_fluid())
7032 i2c_register_board_info(0, bma150_board_info,
7033 ARRAY_SIZE(bma150_board_info));
7034#endif
7035
7036 i2c_register_board_info(2, msm_marimba_board_info,
7037 ARRAY_SIZE(msm_marimba_board_info));
7038
7039 i2c_register_board_info(2, msm_i2c_gsbi7_timpani_info,
7040 ARRAY_SIZE(msm_i2c_gsbi7_timpani_info));
7041
7042 i2c_register_board_info(4 /* QUP ID */, msm_camera_boardinfo,
7043 ARRAY_SIZE(msm_camera_boardinfo));
7044
7045 bt_power_init();
7046#ifdef CONFIG_I2C_SSBI
7047 msm_device_ssbi6.dev.platform_data = &msm_i2c_ssbi6_pdata;
7048 msm_device_ssbi7.dev.platform_data = &msm_i2c_ssbi7_pdata;
7049#endif
7050 if (machine_is_msm7x30_fluid())
7051 i2c_register_board_info(0, msm_isa1200_board_info,
7052 ARRAY_SIZE(msm_isa1200_board_info));
7053
7054#if defined(CONFIG_TOUCHSCREEN_TSC2007) || \
7055 defined(CONFIG_TOUCHSCREEN_TSC2007_MODULE)
7056 if (machine_is_msm8x55_svlte_ffa())
7057 i2c_register_board_info(2, tsc_i2c_board_info,
7058 ARRAY_SIZE(tsc_i2c_board_info));
7059#endif
7060
7061 if (machine_is_msm7x30_surf())
7062 platform_device_register(&flip_switch_device);
7063 pmic8058_leds_init();
7064
7065 if (machine_is_msm7x30_fluid()) {
7066 /* Initialize platform data for fluid v2 hardware */
7067 if (SOCINFO_VERSION_MAJOR(
7068 socinfo_get_platform_version()) == 2) {
7069 cy8ctma300_pdata.res_y = 920;
7070 cy8ctma300_pdata.invert_y = 0;
7071 }
7072 i2c_register_board_info(0, cy8ctma300_board_info,
7073 ARRAY_SIZE(cy8ctma300_board_info));
7074 }
7075
7076 if (machine_is_msm8x55_svlte_surf() || machine_is_msm8x55_svlte_ffa()) {
7077 rc = gpio_tlmm_config(usb_hub_gpio_cfg_value, GPIO_CFG_ENABLE);
7078 if (rc)
7079 pr_err("%s: gpio_tlmm_config(%#x)=%d\n",
7080 __func__, usb_hub_gpio_cfg_value, rc);
7081 }
7082
7083 boot_reason = *(unsigned int *)
7084 (smem_get_entry(SMEM_POWER_ON_STATUS_INFO, &smem_size));
7085 printk(KERN_NOTICE "Boot Reason = 0x%02x\n", boot_reason);
7086}
7087
7088static unsigned pmem_sf_size = MSM_PMEM_SF_SIZE;
7089static int __init pmem_sf_size_setup(char *p)
7090{
7091 pmem_sf_size = memparse(p, NULL);
7092 return 0;
7093}
7094early_param("pmem_sf_size", pmem_sf_size_setup);
7095
7096static unsigned fb_size = MSM_FB_SIZE;
7097static int __init fb_size_setup(char *p)
7098{
7099 fb_size = memparse(p, NULL);
7100 return 0;
7101}
7102early_param("fb_size", fb_size_setup);
7103
7104static unsigned pmem_adsp_size = MSM_PMEM_ADSP_SIZE;
7105static int __init pmem_adsp_size_setup(char *p)
7106{
7107 pmem_adsp_size = memparse(p, NULL);
7108 return 0;
7109}
7110early_param("pmem_adsp_size", pmem_adsp_size_setup);
7111
7112static unsigned fluid_pmem_adsp_size = MSM_FLUID_PMEM_ADSP_SIZE;
7113static int __init fluid_pmem_adsp_size_setup(char *p)
7114{
7115 fluid_pmem_adsp_size = memparse(p, NULL);
7116 return 0;
7117}
7118early_param("fluid_pmem_adsp_size", fluid_pmem_adsp_size_setup);
7119
7120static unsigned pmem_audio_size = MSM_PMEM_AUDIO_SIZE;
7121static int __init pmem_audio_size_setup(char *p)
7122{
7123 pmem_audio_size = memparse(p, NULL);
7124 return 0;
7125}
7126early_param("pmem_audio_size", pmem_audio_size_setup);
7127
7128static unsigned pmem_kernel_ebi0_size = PMEM_KERNEL_EBI0_SIZE;
7129static int __init pmem_kernel_ebi0_size_setup(char *p)
7130{
7131 pmem_kernel_ebi0_size = memparse(p, NULL);
7132 return 0;
7133}
7134early_param("pmem_kernel_ebi0_size", pmem_kernel_ebi0_size_setup);
7135
7136static struct memtype_reserve msm7x30_reserve_table[] __initdata = {
7137 [MEMTYPE_SMI] = {
7138 },
7139 [MEMTYPE_EBI0] = {
7140 .flags = MEMTYPE_FLAGS_1M_ALIGN,
7141 },
7142 [MEMTYPE_EBI1] = {
7143 .flags = MEMTYPE_FLAGS_1M_ALIGN,
7144 },
7145};
7146
7147static void __init size_pmem_devices(void)
7148{
7149#ifdef CONFIG_ANDROID_PMEM
7150 unsigned long size;
7151
7152 if machine_is_msm7x30_fluid()
7153 size = fluid_pmem_adsp_size;
7154 else
7155 size = pmem_adsp_size;
7156 android_pmem_adsp_pdata.size = size;
7157 android_pmem_audio_pdata.size = pmem_audio_size;
7158 android_pmem_pdata.size = pmem_sf_size;
7159#endif
7160}
7161
7162static void __init reserve_memory_for(struct android_pmem_platform_data *p)
7163{
7164 msm7x30_reserve_table[p->memory_type].size += p->size;
7165}
7166
7167static void __init reserve_pmem_memory(void)
7168{
7169#ifdef CONFIG_ANDROID_PMEM
7170 reserve_memory_for(&android_pmem_adsp_pdata);
7171 reserve_memory_for(&android_pmem_audio_pdata);
7172 reserve_memory_for(&android_pmem_pdata);
7173 msm7x30_reserve_table[MEMTYPE_EBI0].size += pmem_kernel_ebi0_size;
7174#endif
7175}
7176
7177static void __init msm7x30_calculate_reserve_sizes(void)
7178{
7179 size_pmem_devices();
7180 reserve_pmem_memory();
7181}
7182
7183static int msm7x30_paddr_to_memtype(unsigned int paddr)
7184{
7185 if (paddr < 0x40000000)
7186 return MEMTYPE_EBI0;
7187 if (paddr >= 0x40000000 && paddr < 0x80000000)
7188 return MEMTYPE_EBI1;
7189 return MEMTYPE_NONE;
7190}
7191
7192static struct reserve_info msm7x30_reserve_info __initdata = {
7193 .memtype_reserve_table = msm7x30_reserve_table,
7194 .calculate_reserve_sizes = msm7x30_calculate_reserve_sizes,
7195 .paddr_to_memtype = msm7x30_paddr_to_memtype,
7196};
7197
7198static void __init msm7x30_reserve(void)
7199{
7200 reserve_info = &msm7x30_reserve_info;
7201 msm_reserve();
7202}
7203
7204static void __init msm7x30_allocate_memory_regions(void)
7205{
7206 void *addr;
7207 unsigned long size;
7208
7209 size = fb_size ? : MSM_FB_SIZE;
7210 addr = alloc_bootmem_align(size, 0x1000);
7211 msm_fb_resources[0].start = __pa(addr);
7212 msm_fb_resources[0].end = msm_fb_resources[0].start + size - 1;
7213 pr_info("allocating %lu bytes at %p (%lx physical) for fb\n",
7214 size, addr, __pa(addr));
Daniel Walker8d747cd2010-02-25 11:37:43 -08007215}
7216
7217static void __init msm7x30_map_io(void)
7218{
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07007219 msm_shared_ram_phys = 0x00100000;
Daniel Walker8d747cd2010-02-25 11:37:43 -08007220 msm_map_msm7x30_io();
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07007221}
7222
7223static void __init msm7x30_init_early(void)
7224{
7225 msm7x30_allocate_memory_regions();
Daniel Walker8d747cd2010-02-25 11:37:43 -08007226}
7227
7228MACHINE_START(MSM7X30_SURF, "QCT MSM7X30 SURF")
Russell Kingb75c1782011-01-04 19:03:16 +00007229 .boot_params = PLAT_PHYS_OFFSET + 0x100,
Daniel Walker8d747cd2010-02-25 11:37:43 -08007230 .map_io = msm7x30_map_io,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07007231 .reserve = msm7x30_reserve,
Daniel Walker8d747cd2010-02-25 11:37:43 -08007232 .init_irq = msm7x30_init_irq,
7233 .init_machine = msm7x30_init,
7234 .timer = &msm_timer,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07007235 .init_early = msm7x30_init_early,
Daniel Walker8d747cd2010-02-25 11:37:43 -08007236MACHINE_END
7237
7238MACHINE_START(MSM7X30_FFA, "QCT MSM7X30 FFA")
Russell Kingb75c1782011-01-04 19:03:16 +00007239 .boot_params = PLAT_PHYS_OFFSET + 0x100,
Daniel Walker8d747cd2010-02-25 11:37:43 -08007240 .map_io = msm7x30_map_io,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07007241 .reserve = msm7x30_reserve,
Daniel Walker8d747cd2010-02-25 11:37:43 -08007242 .init_irq = msm7x30_init_irq,
7243 .init_machine = msm7x30_init,
7244 .timer = &msm_timer,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07007245 .init_early = msm7x30_init_early,
Daniel Walker8d747cd2010-02-25 11:37:43 -08007246MACHINE_END
7247
7248MACHINE_START(MSM7X30_FLUID, "QCT MSM7X30 FLUID")
Russell Kingb75c1782011-01-04 19:03:16 +00007249 .boot_params = PLAT_PHYS_OFFSET + 0x100,
Daniel Walker8d747cd2010-02-25 11:37:43 -08007250 .map_io = msm7x30_map_io,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07007251 .reserve = msm7x30_reserve,
Daniel Walker8d747cd2010-02-25 11:37:43 -08007252 .init_irq = msm7x30_init_irq,
7253 .init_machine = msm7x30_init,
7254 .timer = &msm_timer,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07007255 .init_early = msm7x30_init_early,
7256MACHINE_END
7257
7258MACHINE_START(MSM8X55_SURF, "QCT MSM8X55 SURF")
7259 .boot_params = PHYS_OFFSET + 0x100,
7260 .map_io = msm7x30_map_io,
7261 .reserve = msm7x30_reserve,
7262 .init_irq = msm7x30_init_irq,
7263 .init_machine = msm7x30_init,
7264 .timer = &msm_timer,
7265 .init_early = msm7x30_init_early,
7266MACHINE_END
7267
7268MACHINE_START(MSM8X55_FFA, "QCT MSM8X55 FFA")
7269 .boot_params = PHYS_OFFSET + 0x100,
7270 .map_io = msm7x30_map_io,
7271 .reserve = msm7x30_reserve,
7272 .init_irq = msm7x30_init_irq,
7273 .init_machine = msm7x30_init,
7274 .timer = &msm_timer,
7275 .init_early = msm7x30_init_early,
7276MACHINE_END
7277MACHINE_START(MSM8X55_SVLTE_SURF, "QCT MSM8X55 SVLTE SURF")
7278 .boot_params = PHYS_OFFSET + 0x100,
7279 .map_io = msm7x30_map_io,
7280 .reserve = msm7x30_reserve,
7281 .init_irq = msm7x30_init_irq,
7282 .init_machine = msm7x30_init,
7283 .timer = &msm_timer,
7284 .init_early = msm7x30_init_early,
7285MACHINE_END
7286MACHINE_START(MSM8X55_SVLTE_FFA, "QCT MSM8X55 SVLTE FFA")
7287 .boot_params = PHYS_OFFSET + 0x100,
7288 .map_io = msm7x30_map_io,
7289 .reserve = msm7x30_reserve,
7290 .init_irq = msm7x30_init_irq,
7291 .init_machine = msm7x30_init,
7292 .timer = &msm_timer,
7293 .init_early = msm7x30_init_early,
Daniel Walker8d747cd2010-02-25 11:37:43 -08007294MACHINE_END