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Sathish Ambley9d69ac32012-03-21 10:28:26 -07001/* Copyright (c) 2012, Code Aurora Forum. All rights reserved.
2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 */
Sathish Ambley4df614c2011-10-07 16:30:46 -070012
13/include/ "skeleton.dtsi"
Praveen Chidambaramaa9d52b2012-04-02 11:09:47 -060014/include/ "msmcopper_pm.dtsi"
David Collins153d45a2012-03-26 11:57:50 -070015/include/ "msm-pm8841.dtsi"
16/include/ "msm-pm8941.dtsi"
17/include/ "msmcopper-regulator.dtsi"
Michael Bohan8b909b42012-04-18 17:39:12 -070018/include/ "msmcopper-gpio.dtsi"
Sathish Ambley4df614c2011-10-07 16:30:46 -070019
20/ {
21 model = "Qualcomm MSM Copper";
Sathish Ambley9d69ac32012-03-21 10:28:26 -070022 compatible = "qcom,msmcopper";
Sathish Ambley4df614c2011-10-07 16:30:46 -070023 interrupt-parent = <&intc>;
24
25 intc: interrupt-controller@F9000000 {
26 compatible = "qcom,msm-qgic2";
27 interrupt-controller;
Michael Bohanc7224532012-01-06 16:02:52 -080028 #interrupt-cells = <3>;
Sathish Ambley4df614c2011-10-07 16:30:46 -070029 reg = <0xF9000000 0x1000>,
30 <0xF9002000 0x1000>;
31 };
Sathish Ambley3d50c762011-10-25 15:26:00 -070032
Sathish Ambleye046b242012-04-09 12:38:05 -070033 msmgpio: gpio@fd510000 {
Michael Bohan0425f6f2012-01-17 14:36:39 -080034 compatible = "qcom,msm-gpio";
35 interrupt-controller;
36 #interrupt-cells = <2>;
Sathish Ambleye046b242012-04-09 12:38:05 -070037 reg = <0xfd510000 0x4000>;
38 #gpio-cells = <2>;
Michael Bohan0425f6f2012-01-17 14:36:39 -080039 };
40
Sathish Ambley098f9bd2011-11-09 16:32:53 -080041 timer {
Sathish Ambley2f27a172012-03-16 10:46:28 -070042 compatible = "qcom,msm-qtimer", "arm,armv7-timer";
Sathish Ambleyddd099e2012-04-25 13:24:47 -070043 interrupts = <1 2 0 1 3 0>;
Sathish Ambley2f27a172012-03-16 10:46:28 -070044 clock-frequency = <19200000>;
Sathish Ambley098f9bd2011-11-09 16:32:53 -080045 };
46
Praneeth Paladugu4b73ec82012-02-08 12:55:59 -080047 qcom,vidc@fdc00000 {
48 compatible = "qcom,msm-vidc";
49 reg = <0xfdc00000 0xff000>;
50 interrupts = <0 44 0>;
51 };
52
David Brown225abee2012-02-09 22:28:50 -080053 serial@f991f000 {
Sathish Ambley3d50c762011-10-25 15:26:00 -070054 compatible = "qcom,msm-lsuart-v14";
David Brown225abee2012-02-09 22:28:50 -080055 reg = <0xf991f000 0x1000>;
Michael Bohanc7224532012-01-06 16:02:52 -080056 interrupts = <0 109 0>;
Sathish Ambley3d50c762011-10-25 15:26:00 -070057 };
Pavankumar Kondetieaea7fe2011-10-27 14:46:45 +053058
Sathish Ambley9d69ac32012-03-21 10:28:26 -070059 serial@f995e000 {
60 compatible = "qcom,msm-lsuart-v14";
61 reg = <0xf995e000 0x1000>;
62 interrupts = <0 114 0>;
63 };
64
David Brown225abee2012-02-09 22:28:50 -080065 usb@f9a55000 {
Pavankumar Kondetieaea7fe2011-10-27 14:46:45 +053066 compatible = "qcom,hsusb-otg";
David Brown225abee2012-02-09 22:28:50 -080067 reg = <0xf9a55000 0x400>;
Michael Bohanc7224532012-01-06 16:02:52 -080068 interrupts = <0 134 0>;
Michael Bohane66a3a92012-03-26 12:47:28 -070069 HSUSB_VDDCX-supply = <&pm8841_s2>;
70 HSUSB_1p8-supply = <&pm8941_l6>;
71 HSUSB_3p3-supply = <&pm8941_l24>;
Pavankumar Kondetieaea7fe2011-10-27 14:46:45 +053072
73 qcom,hsusb-otg-phy-type = <2>;
74 qcom,hsusb-otg-mode = <1>;
75 qcom,hsusb-otg-otg-control = <1>;
76 };
Sujit Reddy Thumma7285c2e2011-11-04 10:18:15 +053077
Sujit Reddy Thumma85fc52c2012-05-02 12:53:45 +053078 qcom,sdcc@f9824000 {
Sujit Reddy Thumma7285c2e2011-11-04 10:18:15 +053079 cell-index = <1>;
80 compatible = "qcom,msm-sdcc";
Sujit Reddy Thumma85fc52c2012-05-02 12:53:45 +053081 reg = <0xf9824000 0x1000>;
Michael Bohanc7224532012-01-06 16:02:52 -080082 interrupts = <0 123 0>;
Sujit Reddy Thumma7285c2e2011-11-04 10:18:15 +053083
Sujit Reddy Thumma85fc52c2012-05-02 12:53:45 +053084 qcom,sdcc-clk-rates = <400000 25000000 50000000 100000000 200000000>;
85 qcom,sdcc-sup-voltages = <2950 2950>;
Sujit Reddy Thumma7285c2e2011-11-04 10:18:15 +053086 qcom,sdcc-bus-width = <8>;
Subhash Jadavani56e0eaa2012-03-13 18:06:04 +053087 qcom,sdcc-hs200;
Sujit Reddy Thumma7285c2e2011-11-04 10:18:15 +053088 qcom,sdcc-nonremovable;
Sujit Reddy Thumma7285c2e2011-11-04 10:18:15 +053089 };
90
Sujit Reddy Thumma85fc52c2012-05-02 12:53:45 +053091 qcom,sdcc@f98a4000 {
92 cell-index = <2>;
93 compatible = "qcom,msm-sdcc";
94 reg = <0xf98a4000 0x1000>;
95 interrupts = <0 125 0>;
96
97 qcom,sdcc-clk-rates = <400000 25000000 50000000 100000000 200000000>;
98 qcom,sdcc-sup-voltages = <2950 2950>;
99 qcom,sdcc-bus-width = <4>;
100 };
101
102 qcom,sdcc@f9864000 {
Sujit Reddy Thumma7285c2e2011-11-04 10:18:15 +0530103 cell-index = <3>;
104 compatible = "qcom,msm-sdcc";
Sujit Reddy Thumma85fc52c2012-05-02 12:53:45 +0530105 reg = <0xf9864000 0x1000>;
Michael Bohanc7224532012-01-06 16:02:52 -0800106 interrupts = <0 127 0>;
Sujit Reddy Thumma7285c2e2011-11-04 10:18:15 +0530107
Sujit Reddy Thumma85fc52c2012-05-02 12:53:45 +0530108 qcom,sdcc-clk-rates = <400000 25000000 50000000 100000000>;
109 qcom,sdcc-sup-voltages = <1800 1800>;
Sujit Reddy Thumma7285c2e2011-11-04 10:18:15 +0530110 qcom,sdcc-bus-width = <4>;
Sujit Reddy Thumma85fc52c2012-05-02 12:53:45 +0530111 };
112
113 qcom,sdcc@f98e4000 {
114 cell-index = <4>;
115 compatible = "qcom,msm-sdcc";
116 reg = <0xf98e4000 0x1000>;
117 interrupts = <0 129 0>;
118
119 qcom,sdcc-clk-rates = <400000 25000000 50000000 100000000>;
120 qcom,sdcc-sup-voltages = <1800 1800>;
121 qcom,sdcc-bus-width = <4>;
Sujit Reddy Thumma7285c2e2011-11-04 10:18:15 +0530122 };
Yan He1466daa2011-11-30 17:25:38 -0800123
David Brown225abee2012-02-09 22:28:50 -0800124 qcom,sps@f9980000 {
Yan He1466daa2011-11-30 17:25:38 -0800125 compatible = "qcom,msm_sps";
David Brown225abee2012-02-09 22:28:50 -0800126 reg = <0xf9984000 0x15000>,
127 <0xf9999000 0xb000>;
Michael Bohanc7224532012-01-06 16:02:52 -0800128 interrupts = <0 94 0>;
Yan He1466daa2011-11-30 17:25:38 -0800129
130 qcom,bam-dma-res-pipes = <6>;
131 };
132
Harini Jayaraman5f98dbb2011-12-20 13:38:19 -0700133 spi@f9924000 {
134 compatible = "qcom,spi-qup-v2";
135 reg = <0xf9924000 0x1000>;
Michael Bohan857c8ac2012-01-23 16:57:34 -0800136 interrupts = <0 96 0>;
Vikram Mulukutla703e5722012-05-24 21:53:40 -0700137 spi-max-frequency = <25000000>;
Harini Jayaraman5f98dbb2011-12-20 13:38:19 -0700138 };
Kenneth Heitkef3c829c2012-01-13 17:02:43 -0700139
Sagar Dhariaa316a962012-03-21 16:13:22 -0600140 slim@fe12f000 {
141 cell-index = <1>;
142 compatible = "qcom,slim-msm";
143 reg = <0xfe12f000 0x35000>,
144 <0xfe104000 0x20000>;
145 reg-names = "slimbus_physical", "slimbus_bam_physical";
146 interrupts = <0 163 0 0 164 0>;
147 interrupt-names = "slimbus_irq", "slimbus_bam_irq";
148 qcom,min-clk-gear = <10>;
149 };
150
Kenneth Heitkef3c829c2012-01-13 17:02:43 -0700151 qcom,spmi@fc4c0000 {
152 cell-index = <0>;
153 compatible = "qcom,spmi-pmic-arb";
154 reg = <0xfc4cf000 0x1000>,
155 <0Xfc4cb000 0x1000>;
156 /* 190,ee0_krait_hlos_spmi_periph_irq */
157 /* 187,channel_0_krait_hlos_trans_done_irq */
158 interrupts = <0 190 0 0 187 0>;
159 qcom,pmic-arb-ee = <0>;
160 qcom,pmic-arb-channel = <0>;
Gilad Avidova11c0b52012-02-15 15:30:49 -0700161 qcom,pmic-arb-ppid-map = <0x13000000>, /* PM8941_LDO1 */
162 <0x13100001>, /* PM8941_LDO2 */
163 <0x13200002>, /* PM8941_LDO3 */
164 <0x13300003>, /* PM8941_LDO4 */
165 <0x13400004>, /* PM8941_LDO5 */
166 <0x13500005>, /* PM8941_LDO6 */
167 <0x13600006>, /* PM8941_LDO7 */
168 <0x13700007>, /* PM8941_LDO8 */
169 <0x13800008>, /* PM8941_LDO9 */
170 <0x13900009>, /* PM8941_LDO10 */
171 <0x13a0000a>, /* PM8941_LDO11 */
172 <0x13b0000b>, /* PM8941_LDO12 */
173 <0x13c0000c>, /* PM8941_LDO13 */
174 <0x13d0000d>, /* PM8941_LDO14 */
175 <0x13e0000e>, /* PM8941_LDO15 */
176 <0x13f0000f>, /* PM8941_LDO16 */
177 <0x14000010>, /* PM8941_LDO17 */
178 <0x14100011>, /* PM8941_LDO18 */
179 <0x14200012>, /* PM8941_LDO19 */
180 <0x14300013>, /* PM8941_LDO20 */
181 <0x14400014>, /* PM8941_LDO21 */
182 <0x14500015>, /* PM8941_LDO22 */
183 <0x14600016>, /* PM8941_LDO23 */
184 <0x14700017>, /* PM8941_LDO24 */
185 <0x14800018>, /* PM8941_LDO25 */
186 <0x14900019>, /* PM8941_LDO26 */
187 <0x0c00001a>, /* PM8941_GPIO1 */
188 <0x0c10001b>, /* PM8941_GPIO2 */
189 <0x0c20001c>, /* PM8941_GPIO3 */
190 <0x0c30001d>, /* PM8941_GPIO4 */
191 <0x0c40001e>, /* PM8941_GPIO5 */
192 <0x0c50001f>, /* PM8941_GPIO6 */
193 <0x0c600020>, /* PM8941_GPIO7 */
194 <0x0c700021>, /* PM8941_GPIO8 */
195 <0x0c800022>, /* PM8941_GPIO9 */
196 <0x0c900023>, /* PM8941_GPIO10 */
197 <0x0ca00024>, /* PM8941_GPIO11 */
198 <0x0cb00025>, /* PM8941_GPIO12 */
199 <0x0cc00026>, /* PM8941_GPIO13 */
200 <0x0cd00027>, /* PM8941_GPIO14 */
201 <0x0ce00028>, /* PM8941_GPIO15 */
202 <0x0cf00029>, /* PM8941_GPIO16 */
203 <0x0d00002a>, /* PM8941_GPIO17 */
204 <0x0d10002b>, /* PM8941_GPIO18 */
205 <0x0d20002c>, /* PM8941_GPIO19 */
206 <0x0d30002d>, /* PM8941_GPIO20 */
207 <0x0d40002e>, /* PM8941_GPIO21 */
208 <0x0d50002f>, /* PM8941_GPIO22 */
209 <0x0d600030>, /* PM8941_GPIO23 */
210 <0x0d700031>, /* PM8941_GPIO24 */
211 <0x0d800032>, /* PM8941_GPIO25 */
212 <0x0d900033>, /* PM8941_GPIO26 */
213 <0x0da00034>, /* PM8941_GPIO27 */
214 <0x0db00035>, /* PM8941_GPIO28 */
215 <0x0dc00036>, /* PM8941_GPIO29 */
216 <0x0dd00037>, /* PM8941_GPIO30 */
217 <0x0de00038>, /* PM8941_GPIO31 */
218 <0x0df00039>, /* PM8941_GPIO32 */
219 <0x0e00003a>, /* PM8941_GPIO33 */
220 <0x0e10003b>, /* PM8941_GPIO34 */
221 <0x0e20003c>, /* PM8941_GPIO35 */
222 <0x0e30003d>, /* PM8941_GPIO36 */
223 <0x0280003e>, /* COINCELL */
224 <0x0100003f>, /* SMBC_OVP */
225 <0x01100040>, /* SMBC_CHG */
226 <0x01200041>, /* SMBC_BIF */
227 <0x00500042>, /* INTERRUPT */
228 <0x00100043>, /* PM8941_0 */
229 <0x20100044>, /* PM8841_0 */
230 <0x10100045>, /* PM8941_1 */
231 <0x30100046>, /* PM8841_1 */
232 <0x00800047>, /* PON0 */
233 <0x20800048>, /* PON1 */
234 <0x11000049>, /* PM8941_SMPS1 */
235 <0x1110004a>, /* PM8941_SMPS2 */
236 <0x1120004b>, /* PM8941_SMPS3 */
237 <0x3100004c>, /* PM8841_SMPS1 */
238 <0x3110004d>, /* PM8841_SMPS2 */
239 <0x3120004e>, /* PM8841_SMPS3 */
240 <0x3130004f>, /* PM8841_SMPS4 */
241 <0x31400050>, /* PM8841_SMPS5 */
242 <0x31500051>, /* PM8841_SMPS6 */
243 <0x31600052>, /* PM8841_SMPS7 */
244 <0x31700053>, /* PM8841_SMPS8 */
245 <0x05000054>, /* SHARED_XO */
246 <0x05100055>, /* BB_CLK1 */
247 <0x05200056>, /* BB_CLK2 */
248 <0x05900057>, /* SLEEP_CLK */
249 <0x07000058>, /* PBS_CORE */
250 <0x07100059>, /* PBS_CLIENT1 */
251 <0x0720005a>; /* PBS_CLIENT2 */
Kenneth Heitkef3c829c2012-01-13 17:02:43 -0700252 };
Sagar Dharia218edb92012-01-15 18:03:01 -0700253
254 i2c@f9966000 {
255 cell-index = <0>;
256 compatible = "qcom,i2c-qup";
257 reg = <0Xf9966000 0x1000>;
258 reg-names = "qup_phys_addr";
259 interrupts = <0 104 0>;
260 interrupt-names = "qup_err_intr";
261 qcom,i2c-bus-freq = <100000>;
262 qcom,i2c-src-freq = <24000000>;
263 };
Matt Wagantalle9b715a2012-01-04 18:16:14 -0800264
Matt Wagantall48523022012-04-23 13:28:42 -0700265 qcom,acpuclk@f9000000 {
Matt Wagantalle9b715a2012-01-04 18:16:14 -0800266 compatible = "qcom,acpuclk-copper";
267 };
Ido Shayevitzef72ddd2012-03-28 18:55:55 +0200268
269 qcom,ssusb@F9200000 {
270 compatible = "qcom,dwc-usb3-msm";
271 reg = <0xF9200000 0xCCFF>;
272 interrupts = <0 131 0>;
273 qcom,dwc-usb3-msm-dbm-eps = <4>;
274 };
Matt Wagantallc2bbdc32012-03-21 19:44:50 -0700275
276 qcom,lpass@fe200000 {
277 compatible = "qcom,pil-q6v5-lpass";
278 reg = <0xfe200000 0x00100>,
Matt Wagantallc2bbdc32012-03-21 19:44:50 -0700279 <0xfd485100 0x00010>;
280
Matt Wagantall6e6b8cd2012-05-24 12:42:24 -0700281 qcom,firmware-name = "adsp";
Matt Wagantallc2bbdc32012-03-21 19:44:50 -0700282 };
Tianyi Gouc1e049f82011-11-23 14:20:16 -0800283
284 qcom,pronto@fb21b000 {
285 compatible = "qcom,pil-pronto";
286 reg = <0xfb21b000 0x3000>,
287 <0xfc401700 0x4>,
288 <0xfd485300 0xc>;
289 vdd_pronto_pll-supply = <&pm8941_l12>;
290
291 qcom,firmware-name = "wcnss";
292 };
Naveen Ramaraj51f5e8b2012-04-09 15:58:40 -0700293
294 qcom,ocmem@fdd00000 {
295 compatible = "qcom,msm_ocmem";
296 };
Sathish Ambley4df614c2011-10-07 16:30:46 -0700297};