blob: caed9ae48b04e2e1706a559ae79f6fb5ecffeff7 [file] [log] [blame]
Michael Bohana05f4552012-05-24 15:58:11 -07001* msm-qpnp-pin
2
3msm-qpnp-pin is a GPIO chip driver for the MSM SPMI implementation.
4It creates a spmi_device for every spmi-dev-container block of device_nodes.
5These device_nodes contained within specify the PMIC pin number associated
6with each gpio chip. The driver will map these to Linux GPIO numbers.
7
8[PMIC GPIO Device Declarations]
9
10-Root Node-
11
12Required properties :
13 - spmi-dev-container : Used to specify the following child nodes as part of the
14 same SPMI device.
15 - gpio-controller : Specify as gpio-contoller. All child nodes will belong to
16 this gpio_chip.
17 - #gpio-cells: We encode a PMIC pin number and a 32-bit flag field to
18 specify the gpio configuration. This must be set to '2'.
19 - #address-cells: Specify one address field. This must be set to '1'.
20 - #size-cells: Specify one size-cell. This must be set to '1'.
21 - compatible = "qcom,qpnp-pin" : Specify driver matching for this driver.
Michael Bohan6ea2cd22012-05-29 15:40:18 -070022 - label: String giving the name for the gpio_chip device. This name
23 should be unique on the system and portray the specifics of the device.
Michael Bohana05f4552012-05-24 15:58:11 -070024
25-Child Nodes-
26
27Required properties :
28 - reg : Specify the spmi offset and size for this pin device.
29 - qcom,pin-num : Specify the PMIC pin number for this device.
30
31Optional configuration properties :
32 - qcom,direction: indicates whether the gpio should be input, output, or
33 both.
34 QPNP_PIN_DIR_IN = 0,
35 QPNP_PIN_DIR_OUT = 1,
36 QPNP_PIN_DIR_BOTH = 2
37
38 - qcom,output-type: indicates gpio should be configured as CMOS or open
39 drain.
40 QPNP_PIN_OUT_BUF_CMOS = 0
41 QPNP_PIN_OUT_BUF_OPEN_DRAIN_NMOS = 1,
42 QPNP_PIN_OUT_BUF_OPEN_DRAIN_PMOS = 2,
43
44 - qcom,invert: Invert the signal of the gpio line -
45 QPNP_PIN_INVERT_DISABLE = 0
46 QPNP_PIN_INVERT_ENABLE = 1
47
48 - qcom,pull: Indicates whether a pull up or pull down should be
49 applied. If a pullup is required the current strength
50 needs to be specified. Current values of 30uA, 1.5uA,
51 31.5uA, 1.5uA with 30uA boost are supported.
52 QPNP_PIN_PULL_UP_30 = 0,
53 QPNP_PIN_PULL_UP_1P5 = 1,
54 QPNP_PIN_PULL_UP_31P5 = 2,
55 QPNP_PIN_PULL_UP_1P5_30 = 3,
56 QPNP_PIN_PULL_DN = 4,
57 QPNP_PIN_PULL_NO = 5
58
59 - qcom,vin-sel: specifies the voltage level when the output is set to 1.
60 For an input gpio specifies the voltage level at which
61 the input is interpreted as a logical 1.
62 QPNP_PIN_VIN0 = 0,
63 QPNP_PIN_VIN1 = 1,
64 QPNP_PIN_VIN2 = 2,
65 QPNP_PIN_VIN3 = 3,
66 QPNP_PIN_VIN4 = 4,
67 QPNP_PIN_VIN5 = 5,
68 QPNP_PIN_VIN6 = 6,
69 QPNP_PIN_VIN7 = 7
70
71 - qcom,out-strength: the amount of current supplied for an output gpio.
72 QPNP_PIN_OUT_STRENGTH_LOW = 1
73 QPNP_PIN_OUT_STRENGTH_MED = 2,
74 QPNP_PIN_OUT_STRENGTH_HIGH = 3,
75
76 - qcom,source-sel: choose alternate function for the gpio. Certain gpios
77 can be paired (shorted) with each other. Some gpio pin
78 can act as alternate functions.
79 QPNP_PIN_FUNC_NORMAL = 0,
80 QPNP_PIN_FUNC_PAIRED = 1
81 QPNP_PIN_FUNC_1 = 2,
82 QPNP_PIN_FUNC_2 = 3,
83 QPNP_PIN_DTEST1 = 4,
84 QPNP_PIN_DTEST2 = 5,
85 QPNP_PIN_DTEST3 = 6,
86 QPNP_PIN_DTEST4 = 7
87
88 - qcom,master-en: 1 = Enable features within the
89 pin block based on configurations.
90 0 = Completely disable the block and
91 let the pin float with high impedance
92 regardless of other settings.
93
94*Note: If any of the configuration properties are not specified, then the
95 qpnp-pin driver will not modify that respective configuration in
96 hardware.
97
98[PMIC GPIO clients]
99
100Required properties :
101 - gpios : Contains 3 fields of the form <&gpio_controller pmic_pin_num flags>
102
103[Example]
104
105qpnp: qcom,spmi@fc4c0000 {
106 #address-cells = <1>;
107 #size-cells = <0>;
108 interrupt-controller;
109 #interrupt-cells = <3>;
110
111 qcom,pm8941@0 {
112 spmi-slave-container;
113 reg = <0x0>;
114 #address-cells = <1>;
115 #size-cells = <1>;
116
117 pm8941_gpios: gpios {
118 spmi-dev-container;
119 compatible = "qcom,qpnp-pin";
120 gpio-controller;
121 #gpio-cells = <2>;
122 #address-cells = <1>;
123 #size-cells = <1>;
124
125 gpio@c000 {
126 reg = <0xc000 0x100>;
127 qcom,pin-num = <62>;
128 };
129
130 gpio@c100 {
131 reg = <0xc100 0x100>;
132 qcom,pin-num = <20>;
133 qcom,source_sel = <2>;
134 qcom,pull = <5>;
135 };
136 };
137
138 qcom,testgpio@1000 {
139 compatible = "qcom,qpnp-testgpio";
140 reg = <0x1000 0x1000>;
141 gpios = <&pm8941_gpios 62 0x0 &pm8941_gpios 20 0x1>;
142 };
143 };
144 };
145};