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review.evervolv.com / android_kernel_htc_msm8960 / 6f973b001a9b511900fb73d816adf77d8755838c / . / drivers / serial / sh-sci.h
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Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]1/* $Id: sh-sci.h,v 1.4 2004/02/19 16:43:56 lethal Exp $
2 *
3 * linux/drivers/serial/sh-sci.h
4 *
5 * SuperH on-chip serial module support. (SCI with no FIFO / with FIFO)
6 * Copyright (C) 1999, 2000 Niibe Yutaka
7 * Copyright (C) 2000 Greg Banks
8 * Copyright (C) 2002, 2003 Paul Mundt
9 * Modified to support multiple serial ports. Stuart Menefy (May 2000).
10 * Modified to support SH7300(SH-Mobile) SCIF. Takashi Kusuda (Jun 2003).
11 * Modified to support H8/300 Series Yoshinori Sato (Feb 2004).
12 */
13#include <linux/config.h>
14#include <linux/serial_core.h>
15
16#if defined(__H8300H__) || defined(__H8300S__)
17#include <asm/gpio.h>
18#if defined(CONFIG_H83007) || defined(CONFIG_H83068)
19#include <asm/regs306x.h>
20#endif
21#if defined(CONFIG_H8S2678)
22#include <asm/regs267x.h>
23#endif
24#endif
25
26/* Offsets into the sci_port->irqs array */
27#define SCIx_ERI_IRQ 0
28#define SCIx_RXI_IRQ 1
29#define SCIx_TXI_IRQ 2
30
31/* ERI, RXI, TXI, BRI */
32#define SCI_IRQS { 23, 24, 25, 0 }
33#define SH3_SCIF_IRQS { 56, 57, 59, 58 }
34#define SH3_IRDA_IRQS { 52, 53, 55, 54 }
35#define SH4_SCIF_IRQS { 40, 41, 43, 42 }
36#define STB1_SCIF1_IRQS {23, 24, 26, 25 }
37#define SH7760_SCIF0_IRQS { 52, 53, 55, 54 }
38#define SH7760_SCIF1_IRQS { 72, 73, 75, 74 }
39#define SH7760_SCIF2_IRQS { 76, 77, 79, 78 }
40#define SH7300_SCIF0_IRQS {80, 80, 80, 80 }
41#define SH73180_SCIF_IRQS {80, 81, 83, 82 }
42#define H8300H_SCI_IRQS0 {52, 53, 54, 0 }
43#define H8300H_SCI_IRQS1 {56, 57, 58, 0 }
44#define H8300H_SCI_IRQS2 {60, 61, 62, 0 }
45#define H8S_SCI_IRQS0 {88, 89, 90, 0 }
46#define H8S_SCI_IRQS1 {92, 93, 94, 0 }
47#define H8S_SCI_IRQS2 {96, 97, 98, 0 }
48#define SH5_SCIF_IRQS {39, 40, 42, 0 }
49
50#if defined(CONFIG_CPU_SUBTYPE_SH7708)
51# define SCI_NPORTS 1
52# define SCSPTR 0xffffff7c /* 8 bit */
53# define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */
54# define SCI_ONLY
55#elif defined(CONFIG_CPU_SUBTYPE_SH7707) || defined(CONFIG_CPU_SUBTYPE_SH7709)
56# define SCI_NPORTS 3
57# define SCPCR 0xA4000116 /* 16 bit SCI and SCIF */
58# define SCPDR 0xA4000136 /* 8 bit SCI and SCIF */
59# define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */
60# define SCI_AND_SCIF
61#elif defined(CONFIG_CPU_SUBTYPE_SH7705)
62# define SCIF0 0xA4400000
63# define SCIF2 0xA4410000
64# define SCSMR_Ir 0xA44A0000
65# define IRDA_SCIF SCIF0
66# define SCI_NPORTS 2
67# define SCPCR 0xA4000116
68# define SCPDR 0xA4000136
69
70/* Set the clock source,
71 * SCIF2 (0xA4410000) -> External clock, SCK pin used as clock input
72 * SCIF0 (0xA4400000) -> Internal clock, SCK pin as serial clock output
73 */
74# define SCSCR_INIT(port) (port->mapbase == SCIF2) ? 0xF3 : 0xF0
75# define SCIF_ONLY
76#elif defined(CONFIG_SH_RTS7751R2D)
77# define SCI_NPORTS 1
78# define SCSPTR1 0xffe0001c /* 8 bit SCI */
79# define SCSPTR2 0xFFE80020 /* 16 bit SCIF */
80# define SCIF_ORER 0x0001 /* overrun error bit */
81# define SCSCR_INIT(port) 0x3a /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
82# define SCIF_ONLY
83#elif defined(CONFIG_CPU_SUBTYPE_SH7750) || defined(CONFIG_CPU_SUBTYPE_SH7751)
84# define SCI_NPORTS 2
85# define SCSPTR1 0xffe0001c /* 8 bit SCI */
86# define SCSPTR2 0xFFE80020 /* 16 bit SCIF */
87# define SCIF_ORER 0x0001 /* overrun error bit */
88# define SCSCR_INIT(port) (((port)->type == PORT_SCI) ? \
89 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */ : \
90 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ )
91# define SCI_AND_SCIF
92#elif defined(CONFIG_CPU_SUBTYPE_SH7760)
93# define SCI_NPORTS 3
94# define SCSPTR0 0xfe600000 /* 16 bit SCIF */
95# define SCSPTR1 0xfe610000 /* 16 bit SCIF */
96# define SCSPTR2 0xfe620000 /* 16 bit SCIF */
97# define SCIF_ORER 0x0001 /* overrun error bit */
98# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
99# define SCIF_ONLY
100#elif defined(CONFIG_CPU_SUBTYPE_SH7300)
101# define SCI_NPORTS 1
102# define SCPCR 0xA4050116 /* 16 bit SCIF */
103# define SCPDR 0xA4050136 /* 16 bit SCIF */
104# define SCSCR_INIT(port) 0x0030 /* TIE=0,RIE=0,TE=1,RE=1 */
105# define SCIF_ONLY
106#elif defined(CONFIG_CPU_SUBTYPE_SH73180)
107# define SCI_NPORTS 1
108# define SCPDR 0xA4050138 /* 16 bit SCIF */
109# define SCSPTR2 SCPDR
110# define SCIF_ORER 0x0001 /* overrun error bit */
111# define SCSCR_INIT(port) 0x0038 /* TIE=0,RIE=0,TE=1,RE=1 */
112# define SCIF_ONLY
113#elif defined(CONFIG_CPU_SUBTYPE_SH4_202)
114# define SCI_NPORTS 1
115# define SCSPTR2 0xffe80020 /* 16 bit SCIF */
116# define SCIF_ORER 0x0001 /* overrun error bit */
117# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
118# define SCIF_ONLY
119#elif defined(CONFIG_CPU_SUBTYPE_ST40STB1)
120# define SCI_NPORTS 2
121# define SCSPTR1 0xffe00020 /* 16 bit SCIF */
122# define SCSPTR2 0xffe80020 /* 16 bit SCIF */
123# define SCIF_ORER 0x0001 /* overrun error bit */
124# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
125# define SCIF_ONLY
126#elif defined(CONFIG_CPU_SUBTYPE_SH5_101) || defined(CONFIG_CPU_SUBTYPE_SH5_103)
127# include <asm/hardware.h>
128# define SCIF_BASE_ADDR 0x01030000
129# define SCIF_ADDR_SH5 PHYS_PERIPHERAL_BLOCK+SCIF_BASE_ADDR
130# define SCIF_PTR2_OFFS 0x0000020
131# define SCIF_LSR2_OFFS 0x0000024
132# define SCI_NPORTS 1
133# define SCI_INIT { \
134 { {}, PORT_SCIF, 0, \
135 SH5_SCIF_IRQS, sci_init_pins_scif } \
136}
137# define SCSPTR2 ((port->mapbase)+SCIF_PTR2_OFFS) /* 16 bit SCIF */
138# define SCLSR2 ((port->mapbase)+SCIF_LSR2_OFFS) /* 16 bit SCIF */
139# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,
140 TE=1,RE=1,REIE=1 */
141# define SCIF_ONLY
142#elif defined(CONFIG_H83007) || defined(CONFIG_H83068)
143# define SCI_NPORTS 3
144# define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */
145# define SCI_ONLY
146# define H8300_SCI_DR(ch) *(volatile char *)(P1DR + h8300_sci_pins[ch].port)
147#elif defined(CONFIG_H8S2678)
148# define SCI_NPORTS 3
149# define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */
150# define SCI_ONLY
151# define H8300_SCI_DR(ch) *(volatile char *)(P1DR + h8300_sci_pins[ch].port)
152#else
153# error CPU subtype not defined
154#endif
155
156/* SCSCR */
157#define SCI_CTRL_FLAGS_TIE 0x80 /* all */
158#define SCI_CTRL_FLAGS_RIE 0x40 /* all */
159#define SCI_CTRL_FLAGS_TE 0x20 /* all */
160#define SCI_CTRL_FLAGS_RE 0x10 /* all */
161#if defined(CONFIG_CPU_SUBTYPE_SH7750) || defined(CONFIG_CPU_SUBTYPE_SH7751)
162#define SCI_CTRL_FLAGS_REIE 0x08 /* 7750 SCIF */
163#else
164#define SCI_CTRL_FLAGS_REIE 0
165#endif
166/* SCI_CTRL_FLAGS_MPIE 0x08 * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
167/* SCI_CTRL_FLAGS_TEIE 0x04 * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
168/* SCI_CTRL_FLAGS_CKE1 0x02 * all */
169/* SCI_CTRL_FLAGS_CKE0 0x01 * 7707 SCI/SCIF, 7708 SCI, 7709 SCI/SCIF, 7750 SCI */
170
171/* SCxSR SCI */
172#define SCI_TDRE 0x80 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
173#define SCI_RDRF 0x40 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
174#define SCI_ORER 0x20 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
175#define SCI_FER 0x10 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
176#define SCI_PER 0x08 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
177#define SCI_TEND 0x04 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
178/* SCI_MPB 0x02 * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
179/* SCI_MPBT 0x01 * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
180
181#define SCI_ERRORS ( SCI_PER | SCI_FER | SCI_ORER)
182
183/* SCxSR SCIF */
184#define SCIF_ER 0x0080 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
185#define SCIF_TEND 0x0040 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
186#define SCIF_TDFE 0x0020 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
187#define SCIF_BRK 0x0010 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
188#define SCIF_FER 0x0008 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
189#define SCIF_PER 0x0004 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
190#define SCIF_RDF 0x0002 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
191#define SCIF_DR 0x0001 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
192
193#if defined(CONFIG_CPU_SUBTYPE_SH7300) || defined(CONFIG_CPU_SUBTYPE_SH7705)
194#define SCIF_ORER 0x0200
195#define SCIF_ERRORS ( SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK | SCIF_ORER)
196#define SCIF_RFDC_MASK 0x007f
197#define SCIF_TXROOM_MAX 64
198#else
199#define SCIF_ERRORS ( SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK)
200#define SCIF_RFDC_MASK 0x001f
201#define SCIF_TXROOM_MAX 16
202#endif
203
204#if defined(SCI_ONLY)
205# define SCxSR_TEND(port) SCI_TEND
206# define SCxSR_ERRORS(port) SCI_ERRORS
207# define SCxSR_RDxF(port) SCI_RDRF
208# define SCxSR_TDxE(port) SCI_TDRE
209# define SCxSR_ORER(port) SCI_ORER
210# define SCxSR_FER(port) SCI_FER
211# define SCxSR_PER(port) SCI_PER
212# define SCxSR_BRK(port) 0x00
213# define SCxSR_RDxF_CLEAR(port) 0xbc
214# define SCxSR_ERROR_CLEAR(port) 0xc4
215# define SCxSR_TDxE_CLEAR(port) 0x78
216# define SCxSR_BREAK_CLEAR(port) 0xc4
217#elif defined(SCIF_ONLY)
218# define SCxSR_TEND(port) SCIF_TEND
219# define SCxSR_ERRORS(port) SCIF_ERRORS
220# define SCxSR_RDxF(port) SCIF_RDF
221# define SCxSR_TDxE(port) SCIF_TDFE
222#if defined(CONFIG_CPU_SUBTYPE_SH7300) || defined(CONFIG_CPU_SUBTYPE_SH7705)
223# define SCxSR_ORER(port) SCIF_ORER
224#else
225# define SCxSR_ORER(port) 0x0000
226#endif
227# define SCxSR_FER(port) SCIF_FER
228# define SCxSR_PER(port) SCIF_PER
229# define SCxSR_BRK(port) SCIF_BRK
230#if defined(CONFIG_CPU_SUBTYPE_SH7300) || defined(CONFIG_CPU_SUBTYPE_SH7705)
231# define SCxSR_RDxF_CLEAR(port) (sci_in(port,SCxSR)&0xfffc)
232# define SCxSR_ERROR_CLEAR(port) (sci_in(port,SCxSR)&0xfd73)
233# define SCxSR_TDxE_CLEAR(port) (sci_in(port,SCxSR)&0xffdf)
234# define SCxSR_BREAK_CLEAR(port) (sci_in(port,SCxSR)&0xffe3)
235#else
236/* SH7705 can also use this, clearing is same between 7705 and 7709 and 7300 */
237# define SCxSR_RDxF_CLEAR(port) 0x00fc
238# define SCxSR_ERROR_CLEAR(port) 0x0073
239# define SCxSR_TDxE_CLEAR(port) 0x00df
240# define SCxSR_BREAK_CLEAR(port) 0x00e3
241#endif
242#else
243# define SCxSR_TEND(port) (((port)->type == PORT_SCI) ? SCI_TEND : SCIF_TEND)
244# define SCxSR_ERRORS(port) (((port)->type == PORT_SCI) ? SCI_ERRORS : SCIF_ERRORS)
245# define SCxSR_RDxF(port) (((port)->type == PORT_SCI) ? SCI_RDRF : SCIF_RDF)
246# define SCxSR_TDxE(port) (((port)->type == PORT_SCI) ? SCI_TDRE : SCIF_TDFE)
247# define SCxSR_ORER(port) (((port)->type == PORT_SCI) ? SCI_ORER : 0x0000)
248# define SCxSR_FER(port) (((port)->type == PORT_SCI) ? SCI_FER : SCIF_FER)
249# define SCxSR_PER(port) (((port)->type == PORT_SCI) ? SCI_PER : SCIF_PER)
250# define SCxSR_BRK(port) (((port)->type == PORT_SCI) ? 0x00 : SCIF_BRK)
251# define SCxSR_RDxF_CLEAR(port) (((port)->type == PORT_SCI) ? 0xbc : 0x00fc)
252# define SCxSR_ERROR_CLEAR(port) (((port)->type == PORT_SCI) ? 0xc4 : 0x0073)
253# define SCxSR_TDxE_CLEAR(port) (((port)->type == PORT_SCI) ? 0x78 : 0x00df)
254# define SCxSR_BREAK_CLEAR(port) (((port)->type == PORT_SCI) ? 0xc4 : 0x00e3)
255#endif
256
257/* SCFCR */
258#define SCFCR_RFRST 0x0002
259#define SCFCR_TFRST 0x0004
260#define SCFCR_TCRST 0x4000
261#define SCFCR_MCE 0x0008
262
263#define SCI_MAJOR 204
264#define SCI_MINOR_START 8
265
266/* Generic serial flags */
267#define SCI_RX_THROTTLE 0x0000001
268
269#define SCI_MAGIC 0xbabeface
270
271/*
272 * Events are used to schedule things to happen at timer-interrupt
273 * time, instead of at rs interrupt time.
274 */
275#define SCI_EVENT_WRITE_WAKEUP 0
276
277struct sci_port {
278 struct uart_port port;
279 int type;
280 unsigned char irqs[4]; /* ERI, RXI, TXI, BRI */
281 void (*init_pins)(struct uart_port *port, unsigned int cflag);
282 int break_flag;
283 struct timer_list break_timer;
284};
285
286#define SCI_IN(size, offset) \
287 unsigned int addr = port->mapbase + (offset); \
288 if ((size) == 8) { \
289 return ctrl_inb(addr); \
290 } else { \
291 return ctrl_inw(addr); \
292 }
293#define SCI_OUT(size, offset, value) \
294 unsigned int addr = port->mapbase + (offset); \
295 if ((size) == 8) { \
296 ctrl_outb(value, addr); \
297 } else { \
298 ctrl_outw(value, addr); \
299 }
300
301#define CPU_SCIx_FNS(name, sci_offset, sci_size, scif_offset, scif_size)\
302 static inline unsigned int sci_##name##_in(struct uart_port *port) \
303 { \
304 if (port->type == PORT_SCI) { \
305 SCI_IN(sci_size, sci_offset) \
306 } else { \
307 SCI_IN(scif_size, scif_offset); \
308 } \
309 } \
310 static inline void sci_##name##_out(struct uart_port *port, unsigned int value) \
311 { \
312 if (port->type == PORT_SCI) { \
313 SCI_OUT(sci_size, sci_offset, value) \
314 } else { \
315 SCI_OUT(scif_size, scif_offset, value); \
316 } \
317 }
318
319#define CPU_SCIF_FNS(name, scif_offset, scif_size) \
320 static inline unsigned int sci_##name##_in(struct uart_port *port) \
321 { \
322 SCI_IN(scif_size, scif_offset); \
323 } \
324 static inline void sci_##name##_out(struct uart_port *port, unsigned int value) \
325 { \
326 SCI_OUT(scif_size, scif_offset, value); \
327 }
328
329#define CPU_SCI_FNS(name, sci_offset, sci_size) \
330 static inline unsigned int sci_##name##_in(struct uart_port* port) \
331 { \
332 SCI_IN(sci_size, sci_offset); \
333 } \
334 static inline void sci_##name##_out(struct uart_port* port, unsigned int value) \
335 { \
336 SCI_OUT(sci_size, sci_offset, value); \
337 }
338
339#ifdef CONFIG_CPU_SH3
340#if defined(CONFIG_CPU_SUBTYPE_SH7300) || defined(CONFIG_CPU_SUBTYPE_SH7705)
341#define SCIF_FNS(name, scif_offset, scif_size) \
342 CPU_SCIF_FNS(name, scif_offset, scif_size)
343#else
344#define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh4_sci_offset, sh4_sci_size, \
345 sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size, \
346 h8_sci_offset, h8_sci_size) \
347 CPU_SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh3_scif_offset, sh3_scif_size)
348#define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size) \
349 CPU_SCIF_FNS(name, sh3_scif_offset, sh3_scif_size)
350#endif
351#elif defined(__H8300H__) || defined(__H8300S__)
352#define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh4_sci_offset, sh4_sci_size, \
353 sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size, \
354 h8_sci_offset, h8_sci_size) \
355 CPU_SCI_FNS(name, h8_sci_offset, h8_sci_size)
356#define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size)
357#else
358#define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh4_sci_offset, sh4_sci_size, \
359 sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size, \
360 h8_sci_offset, h8_sci_size) \
361 CPU_SCIx_FNS(name, sh4_sci_offset, sh4_sci_size, sh4_scif_offset, sh4_scif_size)
362#define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size) \
363 CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size)
364#endif
365
366#if defined(CONFIG_CPU_SUBTYPE_SH7300) || defined(CONFIG_CPU_SUBTYPE_SH7705)
367SCIF_FNS(SCSMR, 0x00, 16)
368SCIF_FNS(SCBRR, 0x04, 8)
369SCIF_FNS(SCSCR, 0x08, 16)
370SCIF_FNS(SCTDSR, 0x0c, 8)
371SCIF_FNS(SCFER, 0x10, 16)
372SCIF_FNS(SCxSR, 0x14, 16)
373SCIF_FNS(SCFCR, 0x18, 16)
374SCIF_FNS(SCFDR, 0x1c, 16)
375SCIF_FNS(SCxTDR, 0x20, 8)
376SCIF_FNS(SCxRDR, 0x24, 8)
377SCIF_FNS(SCLSR, 0x24, 16)
378#else
379/* reg SCI/SH3 SCI/SH4 SCIF/SH3 SCIF/SH4 SCI/H8*/
380/* name off sz off sz off sz off sz off sz*/
381SCIx_FNS(SCSMR, 0x00, 8, 0x00, 8, 0x00, 8, 0x00, 16, 0x00, 8)
382SCIx_FNS(SCBRR, 0x02, 8, 0x04, 8, 0x02, 8, 0x04, 8, 0x01, 8)
383SCIx_FNS(SCSCR, 0x04, 8, 0x08, 8, 0x04, 8, 0x08, 16, 0x02, 8)
384SCIx_FNS(SCxTDR, 0x06, 8, 0x0c, 8, 0x06, 8, 0x0C, 8, 0x03, 8)
385SCIx_FNS(SCxSR, 0x08, 8, 0x10, 8, 0x08, 16, 0x10, 16, 0x04, 8)
386SCIx_FNS(SCxRDR, 0x0a, 8, 0x14, 8, 0x0A, 8, 0x14, 8, 0x05, 8)
387SCIF_FNS(SCFCR, 0x0c, 8, 0x18, 16)
388SCIF_FNS(SCFDR, 0x0e, 16, 0x1C, 16)
389SCIF_FNS(SCSPTR, 0, 0, 0x20, 16)
390SCIF_FNS(SCLSR, 0, 0, 0x24, 16)
391#endif
392#define sci_in(port, reg) sci_##reg##_in(port)
393#define sci_out(port, reg, value) sci_##reg##_out(port, value)
394
395/* H8/300 series SCI pins assignment */
396#if defined(__H8300H__) || defined(__H8300S__)
397static const struct __attribute__((packed)) {
398 int port; /* GPIO port no */
399 unsigned short rx,tx; /* GPIO bit no */
400} h8300_sci_pins[] = {
401#if defined(CONFIG_H83007) || defined(CONFIG_H83068)
402 { /* SCI0 */
403 .port = H8300_GPIO_P9,
404 .rx = H8300_GPIO_B2,
405 .tx = H8300_GPIO_B0,
406 },
407 { /* SCI1 */
408 .port = H8300_GPIO_P9,
409 .rx = H8300_GPIO_B3,
410 .tx = H8300_GPIO_B1,
411 },
412 { /* SCI2 */
413 .port = H8300_GPIO_PB,
414 .rx = H8300_GPIO_B7,
415 .tx = H8300_GPIO_B6,
416 }
417#elif defined(CONFIG_H8S2678)
418 { /* SCI0 */
419 .port = H8300_GPIO_P3,
420 .rx = H8300_GPIO_B2,
421 .tx = H8300_GPIO_B0,
422 },
423 { /* SCI1 */
424 .port = H8300_GPIO_P3,
425 .rx = H8300_GPIO_B3,
426 .tx = H8300_GPIO_B1,
427 },
428 { /* SCI2 */
429 .port = H8300_GPIO_P5,
430 .rx = H8300_GPIO_B1,
431 .tx = H8300_GPIO_B0,
432 }
433#endif
434};
435#endif
436
437#if defined(CONFIG_CPU_SUBTYPE_SH7708)
438static inline int sci_rxd_in(struct uart_port *port)
439{
440 if (port->mapbase == 0xfffffe80)
441 return ctrl_inb(SCSPTR)&0x01 ? 1 : 0; /* SCI */
442 return 1;
443}
444#elif defined(CONFIG_CPU_SUBTYPE_SH7707) || defined(CONFIG_CPU_SUBTYPE_SH7709)
445static inline int sci_rxd_in(struct uart_port *port)
446{
447 if (port->mapbase == 0xfffffe80)
448 return ctrl_inb(SCPDR)&0x01 ? 1 : 0; /* SCI */
449 if (port->mapbase == 0xa4000150)
450 return ctrl_inb(SCPDR)&0x10 ? 1 : 0; /* SCIF */
451 if (port->mapbase == 0xa4000140)
452 return ctrl_inb(SCPDR)&0x04 ? 1 : 0; /* IRDA */
453 return 1;
454}
455#elif defined(CONFIG_CPU_SUBTYPE_SH7705)
456static inline int sci_rxd_in(struct uart_port *port)
457{
458 if (port->mapbase == SCIF0)
459 return ctrl_inb(SCPDR)&0x04 ? 1 : 0; /* IRDA */
460 if (port->mapbase == SCIF2)
461 return ctrl_inb(SCPDR)&0x10 ? 1 : 0; /* SCIF */
462 return 1;
463}
464#elif defined(CONFIG_CPU_SUBTYPE_SH7750) || \
465 defined(CONFIG_CPU_SUBTYPE_SH7751) || \
466 defined(CONFIG_CPU_SUBTYPE_SH4_202)
467static inline int sci_rxd_in(struct uart_port *port)
468{
469#ifndef SCIF_ONLY
470 if (port->mapbase == 0xffe00000)
471 return ctrl_inb(SCSPTR1)&0x01 ? 1 : 0; /* SCI */
472#endif
473#ifndef SCI_ONLY
474 if (port->mapbase == 0xffe80000)
475 return ctrl_inw(SCSPTR2)&0x0001 ? 1 : 0; /* SCIF */
476#endif
477 return 1;
478}
479#elif defined(CONFIG_CPU_SUBTYPE_SH7760)
480static inline int sci_rxd_in(struct uart_port *port)
481{
482 if (port->mapbase == 0xfe600000)
483 return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
484 if (port->mapbase == 0xfe610000)
485 return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
486 if (port->mapbase == 0xfe620000)
487 return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */
488}
489#elif defined(CONFIG_CPU_SUBTYPE_SH7300)
490static inline int sci_rxd_in(struct uart_port *port)
491{
492 if (port->mapbase == 0xa4430000)
493 return ctrl_inb(SCPDR)&0x01 ? 1 : 0; /* SCIF0 */
494 return 1;
495}
496#elif defined(CONFIG_CPU_SUBTYPE_SH73180)
497static inline int sci_rxd_in(struct uart_port *port)
498{
499 return ctrl_inb(SCPDR)&0x01 ? 1 : 0; /* SCIF0 */
500}
501#elif defined(CONFIG_CPU_SUBTYPE_ST40STB1)
502static inline int sci_rxd_in(struct uart_port *port)
503{
504 if (port->mapbase == 0xffe00000)
505 return ctrl_inw(SCSPTR1)&0x0001 ? 1 : 0; /* SCIF */
506 else
507 return ctrl_inw(SCSPTR2)&0x0001 ? 1 : 0; /* SCIF */
508
509}
510#elif defined(CONFIG_CPU_SUBTYPE_SH5_101) || defined(CONFIG_CPU_SUBTYPE_SH5_103)
511static inline int sci_rxd_in(struct uart_port *port)
512{
513 return sci_in(port, SCSPTR)&0x0001 ? 1 : 0; /* SCIF */
514}
515#elif defined(__H8300H__) || defined(__H8300S__)
516static inline int sci_rxd_in(struct uart_port *port)
517{
518 int ch = (port->mapbase - SMR0) >> 3;
519 return (H8300_SCI_DR(ch) & h8300_sci_pins[ch].rx) ? 1 : 0;
520}
521#endif
522
523/*
524 * Values for the BitRate Register (SCBRR)
525 *
526 * The values are actually divisors for a frequency which can
527 * be internal to the SH3 (14.7456MHz) or derived from an external
528 * clock source. This driver assumes the internal clock is used;
529 * to support using an external clock source, config options or
530 * possibly command-line options would need to be added.
531 *
532 * Also, to support speeds below 2400 (why?) the lower 2 bits of
533 * the SCSMR register would also need to be set to non-zero values.
534 *
535 * -- Greg Banks 27Feb2000
536 *
537 * Answer: The SCBRR register is only eight bits, and the value in
538 * it gets larger with lower baud rates. At around 2400 (depending on
539 * the peripherial module clock) you run out of bits. However the
540 * lower two bits of SCSMR allow the module clock to be divided down,
541 * scaling the value which is needed in SCBRR.
542 *
543 * -- Stuart Menefy - 23 May 2000
544 *
545 * I meant, why would anyone bother with bitrates below 2400.
546 *
547 * -- Greg Banks - 7Jul2000
548 *
549 * You "speedist"! How will I use my 110bps ASR-33 teletype with paper
550 * tape reader as a console!
551 *
552 * -- Mitch Davis - 15 Jul 2000
553 */
554
555#define PCLK (current_cpu_data.module_clock)
556
557#if defined(CONFIG_CPU_SUBTYPE_SH7300)
558#define SCBRR_VALUE(bps) ((PCLK+16*bps)/(16*bps)-1)
559#elif defined(CONFIG_CPU_SUBTYPE_SH7705)
560#define SCBRR_VALUE(bps) (((PCLK*2)+16*bps)/(32*bps)-1)
561#elif !defined(__H8300H__) && !defined(__H8300S__)
562#define SCBRR_VALUE(bps) ((PCLK+16*bps)/(32*bps)-1)
563#else
564#define SCBRR_VALUE(bps) (((CONFIG_CPU_CLOCK*1000/32)/bps)-1)
565#endif
566#define BPS_2400 SCBRR_VALUE(2400)
567#define BPS_4800 SCBRR_VALUE(4800)
568#define BPS_9600 SCBRR_VALUE(9600)
569#define BPS_19200 SCBRR_VALUE(19200)
570#define BPS_38400 SCBRR_VALUE(38400)
571#define BPS_57600 SCBRR_VALUE(57600)
572#define BPS_115200 SCBRR_VALUE(115200)
573