| Benoit Cousson | 189892f | 2011-08-16 21:02:01 +0530 | [diff] [blame] | 1 | /* | 
|  | 2 | * Device Tree Source for OMAP3 SoC | 
|  | 3 | * | 
|  | 4 | * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ | 
|  | 5 | * | 
|  | 6 | * This file is licensed under the terms of the GNU General Public License | 
|  | 7 | * version 2.  This program is licensed "as is" without any warranty of any | 
|  | 8 | * kind, whether express or implied. | 
|  | 9 | */ | 
|  | 10 |  | 
|  | 11 | /include/ "skeleton.dtsi" | 
|  | 12 |  | 
|  | 13 | / { | 
|  | 14 | compatible = "ti,omap3430", "ti,omap3"; | 
|  | 15 |  | 
| Benoit Cousson | 476b679 | 2011-08-16 11:49:08 +0200 | [diff] [blame] | 16 | cpus { | 
|  | 17 | cpu@0 { | 
|  | 18 | compatible = "arm,cortex-a8"; | 
|  | 19 | }; | 
|  | 20 | }; | 
|  | 21 |  | 
| Benoit Cousson | 189892f | 2011-08-16 21:02:01 +0530 | [diff] [blame] | 22 | /* | 
|  | 23 | * The soc node represents the soc top level view. It is uses for IPs | 
|  | 24 | * that are not memory mapped in the MPU view or for the MPU itself. | 
|  | 25 | */ | 
|  | 26 | soc { | 
|  | 27 | compatible = "ti,omap-infra"; | 
| Benoit Cousson | 476b679 | 2011-08-16 11:49:08 +0200 | [diff] [blame] | 28 | mpu { | 
|  | 29 | compatible = "ti,omap3-mpu"; | 
|  | 30 | ti,hwmods = "mpu"; | 
|  | 31 | }; | 
|  | 32 |  | 
|  | 33 | iva { | 
|  | 34 | compatible = "ti,iva2.2"; | 
|  | 35 | ti,hwmods = "iva"; | 
|  | 36 |  | 
|  | 37 | dsp { | 
|  | 38 | compatible = "ti,omap3-c64"; | 
|  | 39 | }; | 
|  | 40 | }; | 
| Benoit Cousson | 189892f | 2011-08-16 21:02:01 +0530 | [diff] [blame] | 41 | }; | 
|  | 42 |  | 
|  | 43 | /* | 
|  | 44 | * XXX: Use a flat representation of the OMAP3 interconnect. | 
|  | 45 | * The real OMAP interconnect network is quite complex. | 
|  | 46 | * Since that will not bring real advantage to represent that in DT for | 
|  | 47 | * the moment, just use a fake OCP bus entry to represent the whole bus | 
|  | 48 | * hierarchy. | 
|  | 49 | */ | 
|  | 50 | ocp { | 
|  | 51 | compatible = "simple-bus"; | 
|  | 52 | #address-cells = <1>; | 
|  | 53 | #size-cells = <1>; | 
|  | 54 | ranges; | 
|  | 55 | ti,hwmods = "l3_main"; | 
|  | 56 |  | 
|  | 57 | intc: interrupt-controller@1 { | 
|  | 58 | compatible = "ti,omap3-intc"; | 
|  | 59 | interrupt-controller; | 
|  | 60 | #interrupt-cells = <1>; | 
|  | 61 | }; | 
|  | 62 | }; | 
|  | 63 | }; |