blob: 680dd743e88539da8aa36bf098075ee4d67445a5 [file] [log] [blame]
Deepak Verma587c98e2013-02-01 22:47:49 +05301/* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved.
Praveen Chidambaram78499012011-11-01 17:15:17 -06002 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 *
12 */
13
14#include <linux/kernel.h>
15#include <linux/platform_device.h>
Steve Mucklef132c6c2012-06-06 18:30:57 -070016#include <asm/io.h>
Mitchel Humpherysfb52d112012-09-06 11:35:55 -070017#include <linux/msm_ion.h>
Praveen Chidambaram78499012011-11-01 17:15:17 -060018#include <mach/msm_iomap.h>
19#include <mach/irqs-8930.h>
20#include <mach/rpm.h>
Arun Menonaabf2632012-02-24 15:30:47 -080021#include <mach/msm_bus.h>
Gagan Maccd5b3272012-02-09 18:13:10 -070022#include <mach/msm_bus_board.h>
Arun Menonaabf2632012-02-24 15:30:47 -080023#include <mach/board.h>
24#include <mach/socinfo.h>
Laura Abbott0577d7b2012-04-17 11:14:30 -070025#include <mach/iommu_domains.h>
Laura Abbott532b2df2012-04-12 10:53:48 -070026#include <mach/msm_rtb.h>
Laura Abbottf3173042012-05-29 15:23:18 -070027#include <mach/msm_cache_dump.h>
Praveen Chidambaram78499012011-11-01 17:15:17 -060028
29#include "devices.h"
30#include "rpm_log.h"
31#include "rpm_stats.h"
Girish Mahadevan898c56d2012-06-05 16:09:19 -060032#include "rpm_rbcpr_stats.h"
Matt Wagantall1f65d9d2012-04-25 14:24:20 -070033#include "footswitch.h"
Patrick Dalya3b73c42012-08-28 13:39:17 -070034#include "acpuclock-krait.h"
Anji Jonnala4bf6c0c2013-04-16 17:07:52 +053035#include "pm.h"
Praveen Chidambaram78499012011-11-01 17:15:17 -060036
37#ifdef CONFIG_MSM_MPM
Subhash Jadavani909e04f2012-04-12 10:52:50 +053038#include <mach/mpm.h>
Praveen Chidambaram78499012011-11-01 17:15:17 -060039#endif
Anji Jonnala2a8bd312012-11-01 13:11:42 +053040#define MSM8930_RPM_MASTER_STATS_BASE 0x10B100
Anji Jonnalae84292b2012-09-21 13:34:44 +053041#define MSM8930_PC_CNTR_PHYS (MSM8930_IMEM_PHYS + 0x664)
42#define MSM8930_PC_CNTR_SIZE 0x40
43
Anji Jonnala4bf6c0c2013-04-16 17:07:52 +053044static struct msm_pm_sleep_status_data msm_pm_slp_sts_data = {
45 .base_addr = MSM_ACC0_BASE + 0x08,
46 .cpu_offset = MSM_ACC1_BASE - MSM_ACC0_BASE,
47 .mask = 1UL << 13,
48};
49
50struct platform_device msm8930_cpu_slp_status = {
51 .name = "cpu_slp_status",
52 .id = -1,
53 .dev = {
54 .platform_data = &msm_pm_slp_sts_data,
55 },
56};
57
Anji Jonnalae84292b2012-09-21 13:34:44 +053058static struct resource msm8930_resources_pccntr[] = {
59 {
60 .start = MSM8930_PC_CNTR_PHYS,
61 .end = MSM8930_PC_CNTR_PHYS + MSM8930_PC_CNTR_SIZE,
62 .flags = IORESOURCE_MEM,
63 },
64};
65
66struct platform_device msm8930_pc_cntr = {
67 .name = "pc-cntr",
68 .id = -1,
69 .num_resources = ARRAY_SIZE(msm8930_resources_pccntr),
70 .resource = msm8930_resources_pccntr,
71};
Praveen Chidambaram78499012011-11-01 17:15:17 -060072
73struct msm_rpm_platform_data msm8930_rpm_data __initdata = {
74 .reg_base_addrs = {
75 [MSM_RPM_PAGE_STATUS] = MSM_RPM_BASE,
76 [MSM_RPM_PAGE_CTRL] = MSM_RPM_BASE + 0x400,
77 [MSM_RPM_PAGE_REQ] = MSM_RPM_BASE + 0x600,
78 [MSM_RPM_PAGE_ACK] = MSM_RPM_BASE + 0xa00,
79 },
80 .irq_ack = RPM_APCC_CPU0_GP_HIGH_IRQ,
Stephen Boydf61255e2012-02-24 14:31:09 -080081 .irq_err = RPM_APCC_CPU0_GP_LOW_IRQ,
Praveen Chidambarame396ce62012-03-30 11:15:57 -060082 .irq_wakeup = RPM_APCC_CPU0_WAKE_UP_IRQ,
Praveen Chidambaram78499012011-11-01 17:15:17 -060083 .ipc_rpm_reg = MSM_APCS_GCC_BASE + 0x008,
84 .ipc_rpm_val = 4,
85 .target_id = {
86 MSM_RPM_MAP(8930, NOTIFICATION_CONFIGURED_0, NOTIFICATION, 4),
87 MSM_RPM_MAP(8930, NOTIFICATION_REGISTERED_0, NOTIFICATION, 4),
88 MSM_RPM_MAP(8930, INVALIDATE_0, INVALIDATE, 8),
Mahesh Sivasubramanianef2a0fa2012-01-24 15:57:01 -070089 MSM_RPM_MAP(8960, TRIGGER_TIMED_TO, TRIGGER_TIMED, 1),
90 MSM_RPM_MAP(8960, TRIGGER_TIMED_SCLK_COUNT, TRIGGER_TIMED, 1),
Praveen Chidambaram78499012011-11-01 17:15:17 -060091 MSM_RPM_MAP(8930, RPM_CTL, RPM_CTL, 1),
92 MSM_RPM_MAP(8930, CXO_CLK, CXO_CLK, 1),
93 MSM_RPM_MAP(8930, PXO_CLK, PXO_CLK, 1),
94 MSM_RPM_MAP(8930, APPS_FABRIC_CLK, APPS_FABRIC_CLK, 1),
95 MSM_RPM_MAP(8930, SYSTEM_FABRIC_CLK, SYSTEM_FABRIC_CLK, 1),
96 MSM_RPM_MAP(8930, MM_FABRIC_CLK, MM_FABRIC_CLK, 1),
97 MSM_RPM_MAP(8930, DAYTONA_FABRIC_CLK, DAYTONA_FABRIC_CLK, 1),
98 MSM_RPM_MAP(8930, SFPB_CLK, SFPB_CLK, 1),
99 MSM_RPM_MAP(8930, CFPB_CLK, CFPB_CLK, 1),
100 MSM_RPM_MAP(8930, MMFPB_CLK, MMFPB_CLK, 1),
101 MSM_RPM_MAP(8930, EBI1_CLK, EBI1_CLK, 1),
102 MSM_RPM_MAP(8930, APPS_FABRIC_CFG_HALT_0,
103 APPS_FABRIC_CFG_HALT, 2),
104 MSM_RPM_MAP(8930, APPS_FABRIC_CFG_CLKMOD_0,
105 APPS_FABRIC_CFG_CLKMOD, 3),
106 MSM_RPM_MAP(8930, APPS_FABRIC_CFG_IOCTL,
107 APPS_FABRIC_CFG_IOCTL, 1),
Mahesh Sivasubramanian2d2c70592012-03-20 17:07:24 -0600108 MSM_RPM_MAP(8930, APPS_FABRIC_ARB_0, APPS_FABRIC_ARB, 6),
Praveen Chidambaram78499012011-11-01 17:15:17 -0600109 MSM_RPM_MAP(8930, SYS_FABRIC_CFG_HALT_0,
110 SYS_FABRIC_CFG_HALT, 2),
111 MSM_RPM_MAP(8930, SYS_FABRIC_CFG_CLKMOD_0,
112 SYS_FABRIC_CFG_CLKMOD, 3),
113 MSM_RPM_MAP(8930, SYS_FABRIC_CFG_IOCTL,
114 SYS_FABRIC_CFG_IOCTL, 1),
115 MSM_RPM_MAP(8930, SYSTEM_FABRIC_ARB_0,
Mahesh Sivasubramanian2d2c70592012-03-20 17:07:24 -0600116 SYSTEM_FABRIC_ARB, 20),
Praveen Chidambaram78499012011-11-01 17:15:17 -0600117 MSM_RPM_MAP(8930, MMSS_FABRIC_CFG_HALT_0,
118 MMSS_FABRIC_CFG_HALT, 2),
119 MSM_RPM_MAP(8930, MMSS_FABRIC_CFG_CLKMOD_0,
120 MMSS_FABRIC_CFG_CLKMOD, 3),
121 MSM_RPM_MAP(8930, MMSS_FABRIC_CFG_IOCTL,
122 MMSS_FABRIC_CFG_IOCTL, 1),
Mahesh Sivasubramanian2d2c70592012-03-20 17:07:24 -0600123 MSM_RPM_MAP(8930, MM_FABRIC_ARB_0, MM_FABRIC_ARB, 11),
Praveen Chidambaram78499012011-11-01 17:15:17 -0600124 MSM_RPM_MAP(8930, PM8038_S1_0, PM8038_S1, 2),
125 MSM_RPM_MAP(8930, PM8038_S2_0, PM8038_S2, 2),
126 MSM_RPM_MAP(8930, PM8038_S3_0, PM8038_S3, 2),
127 MSM_RPM_MAP(8930, PM8038_S4_0, PM8038_S4, 2),
128 MSM_RPM_MAP(8930, PM8038_S5_0, PM8038_S5, 2),
129 MSM_RPM_MAP(8930, PM8038_S6_0, PM8038_S6, 2),
130 MSM_RPM_MAP(8930, PM8038_L1_0, PM8038_L1, 2),
131 MSM_RPM_MAP(8930, PM8038_L2_0, PM8038_L2, 2),
132 MSM_RPM_MAP(8930, PM8038_L3_0, PM8038_L3, 2),
133 MSM_RPM_MAP(8930, PM8038_L4_0, PM8038_L4, 2),
134 MSM_RPM_MAP(8930, PM8038_L5_0, PM8038_L5, 2),
135 MSM_RPM_MAP(8930, PM8038_L6_0, PM8038_L6, 2),
136 MSM_RPM_MAP(8930, PM8038_L7_0, PM8038_L7, 2),
137 MSM_RPM_MAP(8930, PM8038_L8_0, PM8038_L8, 2),
138 MSM_RPM_MAP(8930, PM8038_L9_0, PM8038_L9, 2),
139 MSM_RPM_MAP(8930, PM8038_L10_0, PM8038_L10, 2),
140 MSM_RPM_MAP(8930, PM8038_L11_0, PM8038_L11, 2),
141 MSM_RPM_MAP(8930, PM8038_L12_0, PM8038_L12, 2),
142 MSM_RPM_MAP(8930, PM8038_L13_0, PM8038_L13, 2),
143 MSM_RPM_MAP(8930, PM8038_L14_0, PM8038_L14, 2),
144 MSM_RPM_MAP(8930, PM8038_L15_0, PM8038_L15, 2),
145 MSM_RPM_MAP(8930, PM8038_L16_0, PM8038_L16, 2),
146 MSM_RPM_MAP(8930, PM8038_L17_0, PM8038_L17, 2),
147 MSM_RPM_MAP(8930, PM8038_L18_0, PM8038_L18, 2),
148 MSM_RPM_MAP(8930, PM8038_L19_0, PM8038_L19, 2),
149 MSM_RPM_MAP(8930, PM8038_L20_0, PM8038_L20, 2),
150 MSM_RPM_MAP(8930, PM8038_L21_0, PM8038_L21, 2),
151 MSM_RPM_MAP(8930, PM8038_L22_0, PM8038_L22, 2),
152 MSM_RPM_MAP(8930, PM8038_L23_0, PM8038_L23, 2),
153 MSM_RPM_MAP(8930, PM8038_L24_0, PM8038_L24, 2),
154 MSM_RPM_MAP(8930, PM8038_L25_0, PM8038_L25, 2),
155 MSM_RPM_MAP(8930, PM8038_L26_0, PM8038_L26, 2),
156 MSM_RPM_MAP(8930, PM8038_L27_0, PM8038_L27, 2),
157 MSM_RPM_MAP(8930, PM8038_CLK1_0, PM8038_CLK1, 2),
158 MSM_RPM_MAP(8930, PM8038_CLK2_0, PM8038_CLK2, 2),
159 MSM_RPM_MAP(8930, PM8038_LVS1, PM8038_LVS1, 1),
160 MSM_RPM_MAP(8930, PM8038_LVS2, PM8038_LVS2, 1),
David Collins5ab4ddb2012-11-29 17:31:39 -0800161 MSM_RPM_MAP_PMIC(8930, 8038, NCP_0, NCP, 2),
162 MSM_RPM_MAP_PMIC(8930, 8038, CXO_BUFFERS, CXO_BUFFERS, 1),
163 MSM_RPM_MAP_PMIC(8930, 8038, USB_OTG_SWITCH, USB_OTG_SWITCH, 1),
164 MSM_RPM_MAP_PMIC(8930, 8038, HDMI_SWITCH, HDMI_SWITCH, 1),
165 MSM_RPM_MAP_PMIC(8930, 8038, QDSS_CLK, QDSS_CLK, 1),
166 MSM_RPM_MAP_PMIC(8930, 8038, VOLTAGE_CORNER, VOLTAGE_CORNER, 1),
Praveen Chidambaram78499012011-11-01 17:15:17 -0600167 },
168 .target_status = {
169 MSM_RPM_STATUS_ID_MAP(8930, VERSION_MAJOR),
170 MSM_RPM_STATUS_ID_MAP(8930, VERSION_MINOR),
171 MSM_RPM_STATUS_ID_MAP(8930, VERSION_BUILD),
172 MSM_RPM_STATUS_ID_MAP(8930, SUPPORTED_RESOURCES_0),
173 MSM_RPM_STATUS_ID_MAP(8930, SUPPORTED_RESOURCES_1),
174 MSM_RPM_STATUS_ID_MAP(8930, SUPPORTED_RESOURCES_2),
175 MSM_RPM_STATUS_ID_MAP(8930, RESERVED_SUPPORTED_RESOURCES_0),
176 MSM_RPM_STATUS_ID_MAP(8930, SEQUENCE),
177 MSM_RPM_STATUS_ID_MAP(8930, RPM_CTL),
178 MSM_RPM_STATUS_ID_MAP(8930, CXO_CLK),
179 MSM_RPM_STATUS_ID_MAP(8930, PXO_CLK),
180 MSM_RPM_STATUS_ID_MAP(8930, APPS_FABRIC_CLK),
181 MSM_RPM_STATUS_ID_MAP(8930, SYSTEM_FABRIC_CLK),
182 MSM_RPM_STATUS_ID_MAP(8930, MM_FABRIC_CLK),
183 MSM_RPM_STATUS_ID_MAP(8930, DAYTONA_FABRIC_CLK),
184 MSM_RPM_STATUS_ID_MAP(8930, SFPB_CLK),
185 MSM_RPM_STATUS_ID_MAP(8930, CFPB_CLK),
186 MSM_RPM_STATUS_ID_MAP(8930, MMFPB_CLK),
187 MSM_RPM_STATUS_ID_MAP(8930, EBI1_CLK),
188 MSM_RPM_STATUS_ID_MAP(8930, APPS_FABRIC_CFG_HALT),
189 MSM_RPM_STATUS_ID_MAP(8930, APPS_FABRIC_CFG_CLKMOD),
190 MSM_RPM_STATUS_ID_MAP(8930, APPS_FABRIC_CFG_IOCTL),
191 MSM_RPM_STATUS_ID_MAP(8930, APPS_FABRIC_ARB),
192 MSM_RPM_STATUS_ID_MAP(8930, SYS_FABRIC_CFG_HALT),
193 MSM_RPM_STATUS_ID_MAP(8930, SYS_FABRIC_CFG_CLKMOD),
194 MSM_RPM_STATUS_ID_MAP(8930, SYS_FABRIC_CFG_IOCTL),
195 MSM_RPM_STATUS_ID_MAP(8930, SYSTEM_FABRIC_ARB),
196 MSM_RPM_STATUS_ID_MAP(8930, MMSS_FABRIC_CFG_HALT),
197 MSM_RPM_STATUS_ID_MAP(8930, MMSS_FABRIC_CFG_CLKMOD),
198 MSM_RPM_STATUS_ID_MAP(8930, MMSS_FABRIC_CFG_IOCTL),
199 MSM_RPM_STATUS_ID_MAP(8930, MM_FABRIC_ARB),
200 MSM_RPM_STATUS_ID_MAP(8930, PM8038_S1_0),
201 MSM_RPM_STATUS_ID_MAP(8930, PM8038_S1_1),
202 MSM_RPM_STATUS_ID_MAP(8930, PM8038_S2_0),
203 MSM_RPM_STATUS_ID_MAP(8930, PM8038_S2_1),
204 MSM_RPM_STATUS_ID_MAP(8930, PM8038_S3_0),
205 MSM_RPM_STATUS_ID_MAP(8930, PM8038_S3_1),
206 MSM_RPM_STATUS_ID_MAP(8930, PM8038_S4_0),
207 MSM_RPM_STATUS_ID_MAP(8930, PM8038_S4_1),
208 MSM_RPM_STATUS_ID_MAP(8930, PM8038_L1_0),
209 MSM_RPM_STATUS_ID_MAP(8930, PM8038_L1_1),
210 MSM_RPM_STATUS_ID_MAP(8930, PM8038_L2_0),
211 MSM_RPM_STATUS_ID_MAP(8930, PM8038_L2_1),
212 MSM_RPM_STATUS_ID_MAP(8930, PM8038_L3_0),
213 MSM_RPM_STATUS_ID_MAP(8930, PM8038_L3_1),
214 MSM_RPM_STATUS_ID_MAP(8930, PM8038_L4_0),
215 MSM_RPM_STATUS_ID_MAP(8930, PM8038_L4_1),
216 MSM_RPM_STATUS_ID_MAP(8930, PM8038_L5_0),
217 MSM_RPM_STATUS_ID_MAP(8930, PM8038_L5_1),
218 MSM_RPM_STATUS_ID_MAP(8930, PM8038_L6_0),
219 MSM_RPM_STATUS_ID_MAP(8930, PM8038_L6_1),
220 MSM_RPM_STATUS_ID_MAP(8930, PM8038_L7_0),
221 MSM_RPM_STATUS_ID_MAP(8930, PM8038_L7_1),
222 MSM_RPM_STATUS_ID_MAP(8930, PM8038_L8_0),
223 MSM_RPM_STATUS_ID_MAP(8930, PM8038_L8_1),
224 MSM_RPM_STATUS_ID_MAP(8930, PM8038_L9_0),
225 MSM_RPM_STATUS_ID_MAP(8930, PM8038_L9_1),
226 MSM_RPM_STATUS_ID_MAP(8930, PM8038_L10_0),
227 MSM_RPM_STATUS_ID_MAP(8930, PM8038_L10_1),
228 MSM_RPM_STATUS_ID_MAP(8930, PM8038_L11_0),
229 MSM_RPM_STATUS_ID_MAP(8930, PM8038_L11_1),
230 MSM_RPM_STATUS_ID_MAP(8930, PM8038_L12_0),
231 MSM_RPM_STATUS_ID_MAP(8930, PM8038_L12_1),
232 MSM_RPM_STATUS_ID_MAP(8930, PM8038_L13_0),
233 MSM_RPM_STATUS_ID_MAP(8930, PM8038_L13_1),
234 MSM_RPM_STATUS_ID_MAP(8930, PM8038_L14_0),
235 MSM_RPM_STATUS_ID_MAP(8930, PM8038_L14_1),
236 MSM_RPM_STATUS_ID_MAP(8930, PM8038_L15_0),
237 MSM_RPM_STATUS_ID_MAP(8930, PM8038_L15_1),
238 MSM_RPM_STATUS_ID_MAP(8930, PM8038_L16_0),
239 MSM_RPM_STATUS_ID_MAP(8930, PM8038_L16_1),
240 MSM_RPM_STATUS_ID_MAP(8930, PM8038_L17_0),
241 MSM_RPM_STATUS_ID_MAP(8930, PM8038_L17_1),
242 MSM_RPM_STATUS_ID_MAP(8930, PM8038_L18_0),
243 MSM_RPM_STATUS_ID_MAP(8930, PM8038_L18_1),
244 MSM_RPM_STATUS_ID_MAP(8930, PM8038_L19_0),
245 MSM_RPM_STATUS_ID_MAP(8930, PM8038_L19_1),
246 MSM_RPM_STATUS_ID_MAP(8930, PM8038_L20_0),
247 MSM_RPM_STATUS_ID_MAP(8930, PM8038_L20_1),
248 MSM_RPM_STATUS_ID_MAP(8930, PM8038_L21_0),
249 MSM_RPM_STATUS_ID_MAP(8930, PM8038_L21_1),
250 MSM_RPM_STATUS_ID_MAP(8930, PM8038_L22_0),
251 MSM_RPM_STATUS_ID_MAP(8930, PM8038_L22_1),
252 MSM_RPM_STATUS_ID_MAP(8930, PM8038_L23_0),
253 MSM_RPM_STATUS_ID_MAP(8930, PM8038_L23_1),
254 MSM_RPM_STATUS_ID_MAP(8930, PM8038_L24_0),
255 MSM_RPM_STATUS_ID_MAP(8930, PM8038_L24_1),
256 MSM_RPM_STATUS_ID_MAP(8930, PM8038_L25_0),
257 MSM_RPM_STATUS_ID_MAP(8930, PM8038_L25_1),
258 MSM_RPM_STATUS_ID_MAP(8930, PM8038_CLK1_0),
259 MSM_RPM_STATUS_ID_MAP(8930, PM8038_CLK1_1),
260 MSM_RPM_STATUS_ID_MAP(8930, PM8038_CLK2_0),
261 MSM_RPM_STATUS_ID_MAP(8930, PM8038_CLK2_1),
262 MSM_RPM_STATUS_ID_MAP(8930, PM8038_LVS1),
263 MSM_RPM_STATUS_ID_MAP(8930, PM8038_LVS2),
Praveen Chidambaramc6e04692012-08-10 16:26:37 -0600264 MSM_RPM_STATUS_ID_MAP(8930, PM8038_NCP_0),
265 MSM_RPM_STATUS_ID_MAP(8930, PM8038_NCP_1),
266 MSM_RPM_STATUS_ID_MAP(8930, PM8038_CXO_BUFFERS),
267 MSM_RPM_STATUS_ID_MAP(8930, PM8038_USB_OTG_SWITCH),
268 MSM_RPM_STATUS_ID_MAP(8930, PM8038_HDMI_SWITCH),
269 MSM_RPM_STATUS_ID_MAP(8930, PM8038_QDSS_CLK),
270 MSM_RPM_STATUS_ID_MAP(8930, PM8038_VOLTAGE_CORNER),
Praveen Chidambaram78499012011-11-01 17:15:17 -0600271 },
272 .target_ctrl_id = {
273 MSM_RPM_CTRL_MAP(8930, VERSION_MAJOR),
274 MSM_RPM_CTRL_MAP(8930, VERSION_MINOR),
275 MSM_RPM_CTRL_MAP(8930, VERSION_BUILD),
276 MSM_RPM_CTRL_MAP(8930, REQ_CTX_0),
277 MSM_RPM_CTRL_MAP(8930, REQ_SEL_0),
278 MSM_RPM_CTRL_MAP(8930, ACK_CTX_0),
279 MSM_RPM_CTRL_MAP(8930, ACK_SEL_0),
280 },
281 .sel_invalidate = MSM_RPM_8930_SEL_INVALIDATE,
282 .sel_notification = MSM_RPM_8930_SEL_NOTIFICATION,
283 .sel_last = MSM_RPM_8930_SEL_LAST,
284 .ver = {3, 0, 0},
285};
286
Praveen Chidambaramc6e04692012-08-10 16:26:37 -0600287struct msm_rpm_platform_data msm8930_rpm_data_pm8917 __initdata = {
288 .reg_base_addrs = {
289 [MSM_RPM_PAGE_STATUS] = MSM_RPM_BASE,
290 [MSM_RPM_PAGE_CTRL] = MSM_RPM_BASE + 0x400,
291 [MSM_RPM_PAGE_REQ] = MSM_RPM_BASE + 0x600,
292 [MSM_RPM_PAGE_ACK] = MSM_RPM_BASE + 0xa00,
293 },
294 .irq_ack = RPM_APCC_CPU0_GP_HIGH_IRQ,
295 .irq_err = RPM_APCC_CPU0_GP_LOW_IRQ,
296 .irq_wakeup = RPM_APCC_CPU0_WAKE_UP_IRQ,
297 .ipc_rpm_reg = MSM_APCS_GCC_BASE + 0x008,
298 .ipc_rpm_val = 4,
299 .target_id = {
300 MSM_RPM_MAP(8930, NOTIFICATION_CONFIGURED_0, NOTIFICATION, 4),
301 MSM_RPM_MAP(8930, NOTIFICATION_REGISTERED_0, NOTIFICATION, 4),
302 MSM_RPM_MAP(8930, INVALIDATE_0, INVALIDATE, 8),
303 MSM_RPM_MAP(8960, TRIGGER_TIMED_TO, TRIGGER_TIMED, 1),
304 MSM_RPM_MAP(8960, TRIGGER_TIMED_SCLK_COUNT, TRIGGER_TIMED, 1),
305 MSM_RPM_MAP(8930, RPM_CTL, RPM_CTL, 1),
306 MSM_RPM_MAP(8930, CXO_CLK, CXO_CLK, 1),
307 MSM_RPM_MAP(8930, PXO_CLK, PXO_CLK, 1),
308 MSM_RPM_MAP(8930, APPS_FABRIC_CLK, APPS_FABRIC_CLK, 1),
309 MSM_RPM_MAP(8930, SYSTEM_FABRIC_CLK, SYSTEM_FABRIC_CLK, 1),
310 MSM_RPM_MAP(8930, MM_FABRIC_CLK, MM_FABRIC_CLK, 1),
311 MSM_RPM_MAP(8930, DAYTONA_FABRIC_CLK, DAYTONA_FABRIC_CLK, 1),
312 MSM_RPM_MAP(8930, SFPB_CLK, SFPB_CLK, 1),
313 MSM_RPM_MAP(8930, CFPB_CLK, CFPB_CLK, 1),
314 MSM_RPM_MAP(8930, MMFPB_CLK, MMFPB_CLK, 1),
315 MSM_RPM_MAP(8930, EBI1_CLK, EBI1_CLK, 1),
316 MSM_RPM_MAP(8930, APPS_FABRIC_CFG_HALT_0,
317 APPS_FABRIC_CFG_HALT, 2),
318 MSM_RPM_MAP(8930, APPS_FABRIC_CFG_CLKMOD_0,
319 APPS_FABRIC_CFG_CLKMOD, 3),
320 MSM_RPM_MAP(8930, APPS_FABRIC_CFG_IOCTL,
321 APPS_FABRIC_CFG_IOCTL, 1),
322 MSM_RPM_MAP(8930, APPS_FABRIC_ARB_0, APPS_FABRIC_ARB, 6),
323 MSM_RPM_MAP(8930, SYS_FABRIC_CFG_HALT_0,
324 SYS_FABRIC_CFG_HALT, 2),
325 MSM_RPM_MAP(8930, SYS_FABRIC_CFG_CLKMOD_0,
326 SYS_FABRIC_CFG_CLKMOD, 3),
327 MSM_RPM_MAP(8930, SYS_FABRIC_CFG_IOCTL,
328 SYS_FABRIC_CFG_IOCTL, 1),
329 MSM_RPM_MAP(8930, SYSTEM_FABRIC_ARB_0,
330 SYSTEM_FABRIC_ARB, 20),
331 MSM_RPM_MAP(8930, MMSS_FABRIC_CFG_HALT_0,
332 MMSS_FABRIC_CFG_HALT, 2),
333 MSM_RPM_MAP(8930, MMSS_FABRIC_CFG_CLKMOD_0,
334 MMSS_FABRIC_CFG_CLKMOD, 3),
335 MSM_RPM_MAP(8930, MMSS_FABRIC_CFG_IOCTL,
336 MMSS_FABRIC_CFG_IOCTL, 1),
337 MSM_RPM_MAP(8930, MM_FABRIC_ARB_0, MM_FABRIC_ARB, 11),
338 MSM_RPM_MAP(8930, PM8917_S1_0, PM8917_S1, 2),
339 MSM_RPM_MAP(8930, PM8917_S2_0, PM8917_S2, 2),
340 MSM_RPM_MAP(8930, PM8917_S3_0, PM8917_S3, 2),
341 MSM_RPM_MAP(8930, PM8917_S4_0, PM8917_S4, 2),
342 MSM_RPM_MAP(8930, PM8917_S5_0, PM8917_S5, 2),
343 MSM_RPM_MAP(8930, PM8917_S6_0, PM8917_S6, 2),
344 MSM_RPM_MAP(8930, PM8917_S7_0, PM8917_S7, 2),
345 MSM_RPM_MAP(8930, PM8917_S8_0, PM8917_S8, 2),
346 MSM_RPM_MAP(8930, PM8917_L1_0, PM8917_L1, 2),
347 MSM_RPM_MAP(8930, PM8917_L2_0, PM8917_L2, 2),
348 MSM_RPM_MAP(8930, PM8917_L3_0, PM8917_L3, 2),
349 MSM_RPM_MAP(8930, PM8917_L4_0, PM8917_L4, 2),
350 MSM_RPM_MAP(8930, PM8917_L5_0, PM8917_L5, 2),
351 MSM_RPM_MAP(8930, PM8917_L6_0, PM8917_L6, 2),
352 MSM_RPM_MAP(8930, PM8917_L7_0, PM8917_L7, 2),
353 MSM_RPM_MAP(8930, PM8917_L8_0, PM8917_L8, 2),
354 MSM_RPM_MAP(8930, PM8917_L9_0, PM8917_L9, 2),
355 MSM_RPM_MAP(8930, PM8917_L10_0, PM8917_L10, 2),
356 MSM_RPM_MAP(8930, PM8917_L11_0, PM8917_L11, 2),
357 MSM_RPM_MAP(8930, PM8917_L12_0, PM8917_L12, 2),
358 MSM_RPM_MAP(8930, PM8917_L14_0, PM8917_L14, 2),
359 MSM_RPM_MAP(8930, PM8917_L15_0, PM8917_L15, 2),
360 MSM_RPM_MAP(8930, PM8917_L16_0, PM8917_L16, 2),
361 MSM_RPM_MAP(8930, PM8917_L17_0, PM8917_L17, 2),
362 MSM_RPM_MAP(8930, PM8917_L18_0, PM8917_L18, 2),
363 MSM_RPM_MAP(8930, PM8917_L21_0, PM8917_L21, 2),
364 MSM_RPM_MAP(8930, PM8917_L22_0, PM8917_L22, 2),
365 MSM_RPM_MAP(8930, PM8917_L23_0, PM8917_L23, 2),
366 MSM_RPM_MAP(8930, PM8917_L24_0, PM8917_L24, 2),
367 MSM_RPM_MAP(8930, PM8917_L25_0, PM8917_L25, 2),
368 MSM_RPM_MAP(8930, PM8917_L26_0, PM8917_L26, 2),
369 MSM_RPM_MAP(8930, PM8917_L27_0, PM8917_L27, 2),
370 MSM_RPM_MAP(8930, PM8917_L28_0, PM8917_L28, 2),
371 MSM_RPM_MAP(8930, PM8917_L29_0, PM8917_L29, 2),
372 MSM_RPM_MAP(8930, PM8917_L30_0, PM8917_L30, 2),
373 MSM_RPM_MAP(8930, PM8917_L31_0, PM8917_L31, 2),
374 MSM_RPM_MAP(8930, PM8917_L32_0, PM8917_L32, 2),
375 MSM_RPM_MAP(8930, PM8917_L33_0, PM8917_L33, 2),
376 MSM_RPM_MAP(8930, PM8917_L34_0, PM8917_L34, 2),
377 MSM_RPM_MAP(8930, PM8917_L35_0, PM8917_L35, 2),
378 MSM_RPM_MAP(8930, PM8917_L36_0, PM8917_L36, 2),
379 MSM_RPM_MAP(8930, PM8917_CLK1_0, PM8917_CLK1, 2),
380 MSM_RPM_MAP(8930, PM8917_CLK2_0, PM8917_CLK2, 2),
381 MSM_RPM_MAP(8930, PM8917_LVS1, PM8917_LVS1, 1),
382 MSM_RPM_MAP(8930, PM8917_LVS3, PM8917_LVS3, 1),
383 MSM_RPM_MAP(8930, PM8917_LVS4, PM8917_LVS4, 1),
384 MSM_RPM_MAP(8930, PM8917_LVS5, PM8917_LVS5, 1),
385 MSM_RPM_MAP(8930, PM8917_LVS6, PM8917_LVS6, 1),
386 MSM_RPM_MAP(8930, PM8917_LVS7, PM8917_LVS7, 1),
David Collins5ab4ddb2012-11-29 17:31:39 -0800387 MSM_RPM_MAP_PMIC(8930, 8917, NCP_0, NCP, 2),
388 MSM_RPM_MAP_PMIC(8930, 8917, CXO_BUFFERS, CXO_BUFFERS, 1),
389 MSM_RPM_MAP_PMIC(8930, 8917, USB_OTG_SWITCH, USB_OTG_SWITCH, 1),
390 MSM_RPM_MAP_PMIC(8930, 8917, HDMI_SWITCH, HDMI_SWITCH, 1),
391 MSM_RPM_MAP_PMIC(8930, 8917, QDSS_CLK, QDSS_CLK, 1),
392 MSM_RPM_MAP_PMIC(8930, 8917, VOLTAGE_CORNER, VOLTAGE_CORNER, 1),
Praveen Chidambaramc6e04692012-08-10 16:26:37 -0600393 },
394 .target_status = {
395 MSM_RPM_STATUS_ID_MAP(8930, VERSION_MAJOR),
396 MSM_RPM_STATUS_ID_MAP(8930, VERSION_MINOR),
397 MSM_RPM_STATUS_ID_MAP(8930, VERSION_BUILD),
398 MSM_RPM_STATUS_ID_MAP(8930, SUPPORTED_RESOURCES_0),
399 MSM_RPM_STATUS_ID_MAP(8930, SUPPORTED_RESOURCES_1),
400 MSM_RPM_STATUS_ID_MAP(8930, SUPPORTED_RESOURCES_2),
401 MSM_RPM_STATUS_ID_MAP(8930, RESERVED_SUPPORTED_RESOURCES_0),
402 MSM_RPM_STATUS_ID_MAP(8930, SEQUENCE),
403 MSM_RPM_STATUS_ID_MAP(8930, RPM_CTL),
404 MSM_RPM_STATUS_ID_MAP(8930, CXO_CLK),
405 MSM_RPM_STATUS_ID_MAP(8930, PXO_CLK),
406 MSM_RPM_STATUS_ID_MAP(8930, APPS_FABRIC_CLK),
407 MSM_RPM_STATUS_ID_MAP(8930, SYSTEM_FABRIC_CLK),
408 MSM_RPM_STATUS_ID_MAP(8930, MM_FABRIC_CLK),
409 MSM_RPM_STATUS_ID_MAP(8930, DAYTONA_FABRIC_CLK),
410 MSM_RPM_STATUS_ID_MAP(8930, SFPB_CLK),
411 MSM_RPM_STATUS_ID_MAP(8930, CFPB_CLK),
412 MSM_RPM_STATUS_ID_MAP(8930, MMFPB_CLK),
413 MSM_RPM_STATUS_ID_MAP(8930, EBI1_CLK),
414 MSM_RPM_STATUS_ID_MAP(8930, APPS_FABRIC_CFG_HALT),
415 MSM_RPM_STATUS_ID_MAP(8930, APPS_FABRIC_CFG_CLKMOD),
416 MSM_RPM_STATUS_ID_MAP(8930, APPS_FABRIC_CFG_IOCTL),
417 MSM_RPM_STATUS_ID_MAP(8930, APPS_FABRIC_ARB),
418 MSM_RPM_STATUS_ID_MAP(8930, SYS_FABRIC_CFG_HALT),
419 MSM_RPM_STATUS_ID_MAP(8930, SYS_FABRIC_CFG_CLKMOD),
420 MSM_RPM_STATUS_ID_MAP(8930, SYS_FABRIC_CFG_IOCTL),
421 MSM_RPM_STATUS_ID_MAP(8930, SYSTEM_FABRIC_ARB),
422 MSM_RPM_STATUS_ID_MAP(8930, MMSS_FABRIC_CFG_HALT),
423 MSM_RPM_STATUS_ID_MAP(8930, MMSS_FABRIC_CFG_CLKMOD),
424 MSM_RPM_STATUS_ID_MAP(8930, MMSS_FABRIC_CFG_IOCTL),
425 MSM_RPM_STATUS_ID_MAP(8930, MM_FABRIC_ARB),
426 MSM_RPM_STATUS_ID_MAP(8930, PM8917_S1_0),
427 MSM_RPM_STATUS_ID_MAP(8930, PM8917_S1_1),
428 MSM_RPM_STATUS_ID_MAP(8930, PM8917_S2_0),
429 MSM_RPM_STATUS_ID_MAP(8930, PM8917_S2_1),
430 MSM_RPM_STATUS_ID_MAP(8930, PM8917_S3_0),
431 MSM_RPM_STATUS_ID_MAP(8930, PM8917_S3_1),
432 MSM_RPM_STATUS_ID_MAP(8930, PM8917_S4_0),
433 MSM_RPM_STATUS_ID_MAP(8930, PM8917_S4_1),
434 MSM_RPM_STATUS_ID_MAP(8930, PM8917_S5_0),
435 MSM_RPM_STATUS_ID_MAP(8930, PM8917_S5_1),
436 MSM_RPM_STATUS_ID_MAP(8930, PM8917_S6_0),
437 MSM_RPM_STATUS_ID_MAP(8930, PM8917_S6_1),
438 MSM_RPM_STATUS_ID_MAP(8930, PM8917_S7_0),
439 MSM_RPM_STATUS_ID_MAP(8930, PM8917_S7_1),
440 MSM_RPM_STATUS_ID_MAP(8930, PM8917_S8_0),
441 MSM_RPM_STATUS_ID_MAP(8930, PM8917_S8_1),
442 MSM_RPM_STATUS_ID_MAP(8930, PM8917_L1_0),
443 MSM_RPM_STATUS_ID_MAP(8930, PM8917_L1_1),
444 MSM_RPM_STATUS_ID_MAP(8930, PM8917_L2_0),
445 MSM_RPM_STATUS_ID_MAP(8930, PM8917_L2_1),
446 MSM_RPM_STATUS_ID_MAP(8930, PM8917_L3_0),
447 MSM_RPM_STATUS_ID_MAP(8930, PM8917_L3_1),
448 MSM_RPM_STATUS_ID_MAP(8930, PM8917_L4_0),
449 MSM_RPM_STATUS_ID_MAP(8930, PM8917_L4_1),
450 MSM_RPM_STATUS_ID_MAP(8930, PM8917_L5_0),
451 MSM_RPM_STATUS_ID_MAP(8930, PM8917_L5_1),
452 MSM_RPM_STATUS_ID_MAP(8930, PM8917_L6_0),
453 MSM_RPM_STATUS_ID_MAP(8930, PM8917_L6_1),
454 MSM_RPM_STATUS_ID_MAP(8930, PM8917_L7_0),
455 MSM_RPM_STATUS_ID_MAP(8930, PM8917_L7_1),
456 MSM_RPM_STATUS_ID_MAP(8930, PM8917_L8_0),
457 MSM_RPM_STATUS_ID_MAP(8930, PM8917_L8_1),
458 MSM_RPM_STATUS_ID_MAP(8930, PM8917_L9_0),
459 MSM_RPM_STATUS_ID_MAP(8930, PM8917_L9_1),
460 MSM_RPM_STATUS_ID_MAP(8930, PM8917_L10_0),
461 MSM_RPM_STATUS_ID_MAP(8930, PM8917_L10_1),
462 MSM_RPM_STATUS_ID_MAP(8930, PM8917_L11_0),
463 MSM_RPM_STATUS_ID_MAP(8930, PM8917_L11_1),
464 MSM_RPM_STATUS_ID_MAP(8930, PM8917_L12_0),
465 MSM_RPM_STATUS_ID_MAP(8930, PM8917_L12_1),
466 MSM_RPM_STATUS_ID_MAP(8930, PM8917_L14_0),
467 MSM_RPM_STATUS_ID_MAP(8930, PM8917_L14_1),
468 MSM_RPM_STATUS_ID_MAP(8930, PM8917_L15_0),
469 MSM_RPM_STATUS_ID_MAP(8930, PM8917_L15_1),
470 MSM_RPM_STATUS_ID_MAP(8930, PM8917_L16_0),
471 MSM_RPM_STATUS_ID_MAP(8930, PM8917_L16_1),
472 MSM_RPM_STATUS_ID_MAP(8930, PM8917_L17_0),
473 MSM_RPM_STATUS_ID_MAP(8930, PM8917_L17_1),
474 MSM_RPM_STATUS_ID_MAP(8930, PM8917_L18_0),
475 MSM_RPM_STATUS_ID_MAP(8930, PM8917_L18_1),
476 MSM_RPM_STATUS_ID_MAP(8930, PM8917_L21_0),
477 MSM_RPM_STATUS_ID_MAP(8930, PM8917_L21_1),
478 MSM_RPM_STATUS_ID_MAP(8930, PM8917_L22_0),
479 MSM_RPM_STATUS_ID_MAP(8930, PM8917_L22_1),
480 MSM_RPM_STATUS_ID_MAP(8930, PM8917_L23_0),
481 MSM_RPM_STATUS_ID_MAP(8930, PM8917_L23_1),
482 MSM_RPM_STATUS_ID_MAP(8930, PM8917_L24_0),
483 MSM_RPM_STATUS_ID_MAP(8930, PM8917_L24_1),
484 MSM_RPM_STATUS_ID_MAP(8930, PM8917_L25_0),
485 MSM_RPM_STATUS_ID_MAP(8930, PM8917_L25_1),
486 MSM_RPM_STATUS_ID_MAP(8930, PM8917_L26_0),
487 MSM_RPM_STATUS_ID_MAP(8930, PM8917_L26_1),
488 MSM_RPM_STATUS_ID_MAP(8930, PM8917_L27_0),
489 MSM_RPM_STATUS_ID_MAP(8930, PM8917_L27_1),
490 MSM_RPM_STATUS_ID_MAP(8930, PM8917_L28_0),
491 MSM_RPM_STATUS_ID_MAP(8930, PM8917_L28_1),
492 MSM_RPM_STATUS_ID_MAP(8930, PM8917_L29_0),
493 MSM_RPM_STATUS_ID_MAP(8930, PM8917_L29_1),
494 MSM_RPM_STATUS_ID_MAP(8930, PM8917_L30_0),
495 MSM_RPM_STATUS_ID_MAP(8930, PM8917_L30_1),
496 MSM_RPM_STATUS_ID_MAP(8930, PM8917_L31_0),
497 MSM_RPM_STATUS_ID_MAP(8930, PM8917_L31_1),
498 MSM_RPM_STATUS_ID_MAP(8930, PM8917_L32_0),
499 MSM_RPM_STATUS_ID_MAP(8930, PM8917_L32_1),
500 MSM_RPM_STATUS_ID_MAP(8930, PM8917_L33_0),
501 MSM_RPM_STATUS_ID_MAP(8930, PM8917_L33_1),
502 MSM_RPM_STATUS_ID_MAP(8930, PM8917_L34_0),
503 MSM_RPM_STATUS_ID_MAP(8930, PM8917_L34_1),
504 MSM_RPM_STATUS_ID_MAP(8930, PM8917_L35_0),
505 MSM_RPM_STATUS_ID_MAP(8930, PM8917_L35_1),
506 MSM_RPM_STATUS_ID_MAP(8930, PM8917_L36_0),
507 MSM_RPM_STATUS_ID_MAP(8930, PM8917_L36_1),
508 MSM_RPM_STATUS_ID_MAP(8930, PM8917_CLK1_0),
509 MSM_RPM_STATUS_ID_MAP(8930, PM8917_CLK1_1),
510 MSM_RPM_STATUS_ID_MAP(8930, PM8917_CLK2_0),
511 MSM_RPM_STATUS_ID_MAP(8930, PM8917_CLK2_1),
512 MSM_RPM_STATUS_ID_MAP(8930, PM8917_LVS1),
513 MSM_RPM_STATUS_ID_MAP(8930, PM8917_LVS3),
514 MSM_RPM_STATUS_ID_MAP(8930, PM8917_LVS4),
515 MSM_RPM_STATUS_ID_MAP(8930, PM8917_LVS5),
516 MSM_RPM_STATUS_ID_MAP(8930, PM8917_LVS6),
517 MSM_RPM_STATUS_ID_MAP(8930, PM8917_LVS7),
518 MSM_RPM_STATUS_ID_MAP(8930, PM8917_NCP_0),
519 MSM_RPM_STATUS_ID_MAP(8930, PM8917_NCP_1),
520 MSM_RPM_STATUS_ID_MAP(8930, PM8917_CXO_BUFFERS),
521 MSM_RPM_STATUS_ID_MAP(8930, PM8917_USB_OTG_SWITCH),
522 MSM_RPM_STATUS_ID_MAP(8930, PM8917_HDMI_SWITCH),
523 MSM_RPM_STATUS_ID_MAP(8930, PM8917_QDSS_CLK),
524 MSM_RPM_STATUS_ID_MAP(8930, PM8917_VOLTAGE_CORNER),
525 },
526 .target_ctrl_id = {
527 MSM_RPM_CTRL_MAP(8930, VERSION_MAJOR),
528 MSM_RPM_CTRL_MAP(8930, VERSION_MINOR),
529 MSM_RPM_CTRL_MAP(8930, VERSION_BUILD),
530 MSM_RPM_CTRL_MAP(8930, REQ_CTX_0),
531 MSM_RPM_CTRL_MAP(8930, REQ_SEL_0),
532 MSM_RPM_CTRL_MAP(8930, ACK_CTX_0),
533 MSM_RPM_CTRL_MAP(8930, ACK_SEL_0),
534 },
535 .sel_invalidate = MSM_RPM_8930_SEL_INVALIDATE,
536 .sel_notification = MSM_RPM_8930_SEL_NOTIFICATION,
537 .sel_last = MSM_RPM_8930_SEL_LAST,
538 .ver = {3, 0, 0},
539};
Praveen Chidambaram78499012011-11-01 17:15:17 -0600540struct platform_device msm8930_rpm_device = {
541 .name = "msm_rpm",
542 .id = -1,
543};
544
545static struct msm_rpm_log_platform_data msm_rpm_log_pdata = {
Anji Jonnalaa5777ce2013-03-28 13:45:58 +0530546 .phys_addr_base = 0x10B6A0,
Praveen Chidambaram78499012011-11-01 17:15:17 -0600547 .reg_offsets = {
548 [MSM_RPM_LOG_PAGE_INDICES] = 0x00000080,
549 [MSM_RPM_LOG_PAGE_BUFFER] = 0x000000A0,
550 },
551 .phys_size = SZ_8K,
Anji Jonnalaa5777ce2013-03-28 13:45:58 +0530552 .log_len = 8192, /* log's buffer length in bytes */
553 .log_len_mask = (8192 >> 2) - 1, /* length mask in units of u32 */
Praveen Chidambaram78499012011-11-01 17:15:17 -0600554};
555
556struct platform_device msm8930_rpm_log_device = {
557 .name = "msm_rpm_log",
558 .id = -1,
559 .dev = {
560 .platform_data = &msm_rpm_log_pdata,
561 },
562};
563
564static struct msm_rpmstats_platform_data msm_rpm_stat_pdata = {
Anji Jonnalaa1a1c3b2012-09-18 19:20:21 +0530565 .phys_addr_base = 0x0010DD04,
566 .phys_size = SZ_256,
Praveen Chidambaram78499012011-11-01 17:15:17 -0600567};
568
569struct platform_device msm8930_rpm_stat_device = {
570 .name = "msm_rpm_stat",
571 .id = -1,
572 .dev = {
573 .platform_data = &msm_rpm_stat_pdata,
574 },
575};
576
Anji Jonnala2a8bd312012-11-01 13:11:42 +0530577static struct resource resources_rpm_master_stats[] = {
578 {
579 .start = MSM8930_RPM_MASTER_STATS_BASE,
580 .end = MSM8930_RPM_MASTER_STATS_BASE + SZ_256,
581 .flags = IORESOURCE_MEM,
582 },
583};
584
585static char *master_names[] = {
586 "KPSS",
587 "MPSS",
588 "LPASS",
589 "RIVA",
590};
591
592static struct msm_rpm_master_stats_platform_data msm_rpm_master_stat_pdata = {
593 .masters = master_names,
594 .nomasters = ARRAY_SIZE(master_names),
595};
596
597struct platform_device msm8930_rpm_master_stat_device = {
598 .name = "msm_rpm_master_stat",
599 .id = -1,
600 .num_resources = ARRAY_SIZE(resources_rpm_master_stats),
601 .resource = resources_rpm_master_stats,
602 .dev = {
603 .platform_data = &msm_rpm_master_stat_pdata,
604 },
605};
606
Girish Mahadevan898c56d2012-06-05 16:09:19 -0600607static struct resource msm_rpm_rbcpr_resource = {
Girish Mahadevan2f08a582012-09-10 12:43:26 -0600608 .start = 0x0010DB00,
609 .end = 0x0010DB00 + SZ_8K - 1,
Girish Mahadevan898c56d2012-06-05 16:09:19 -0600610 .flags = IORESOURCE_MEM,
611};
612
613static struct msm_rpmrbcpr_platform_data msm_rpm_rbcpr_pdata = {
614 .rbcpr_data = {
615 .upside_steps = 1,
616 .downside_steps = 2,
617 .svs_voltage = 1050000,
618 .nominal_voltage = 1162500,
619 .turbo_voltage = 1287500,
620 },
621};
622
623struct platform_device msm8930_rpm_rbcpr_device = {
624 .name = "msm_rpm_rbcpr",
625 .id = -1,
626 .dev = {
627 .platform_data = &msm_rpm_rbcpr_pdata,
628 },
629 .resource = &msm_rpm_rbcpr_resource,
630};
631
Gagan Maccd5b3272012-02-09 18:13:10 -0700632struct platform_device msm_bus_8930_sys_fabric = {
633 .name = "msm_bus_fabric",
634 .id = MSM_BUS_FAB_SYSTEM,
635};
636struct platform_device msm_bus_8930_apps_fabric = {
637 .name = "msm_bus_fabric",
638 .id = MSM_BUS_FAB_APPSS,
639};
640struct platform_device msm_bus_8930_mm_fabric = {
641 .name = "msm_bus_fabric",
642 .id = MSM_BUS_FAB_MMSS,
643};
644struct platform_device msm_bus_8930_sys_fpb = {
645 .name = "msm_bus_fabric",
646 .id = MSM_BUS_FAB_SYSTEM_FPB,
647};
648struct platform_device msm_bus_8930_cpss_fpb = {
649 .name = "msm_bus_fabric",
650 .id = MSM_BUS_FAB_CPSS_FPB,
651};
652
Matt Wagantallab730bd2012-06-07 20:13:51 -0700653struct platform_device msm8627_device_acpuclk = {
654 .name = "acpuclk-8627",
655 .id = -1,
656};
657
Patrick Dalya3b73c42012-08-28 13:39:17 -0700658static struct acpuclk_platform_data acpuclk_8930_pdata = {
659 .uses_pm8917 = false,
660};
661
Matt Wagantall6dcfa922012-06-07 20:13:51 -0700662struct platform_device msm8930_device_acpuclk = {
663 .name = "acpuclk-8930",
664 .id = -1,
Patrick Dalya3b73c42012-08-28 13:39:17 -0700665 .dev = {
666 .platform_data = &acpuclk_8930_pdata,
667 },
Matt Wagantall6dcfa922012-06-07 20:13:51 -0700668};
669
Tianyi Gou12370f12012-07-23 19:13:57 -0700670struct platform_device msm8930aa_device_acpuclk = {
671 .name = "acpuclk-8930aa",
672 .id = -1,
673};
674
Tianyi Gou01c27a32012-10-29 19:13:53 -0700675static struct acpuclk_platform_data acpuclk_8930ab_pdata = {
676 .uses_pm8917 = false,
677};
678
679struct platform_device msm8930ab_device_acpuclk = {
680 .name = "acpuclk-8930ab",
681 .id = -1,
682 .dev = {
683 .platform_data = &acpuclk_8930ab_pdata,
684 },
685};
686
Matt Wagantall1f65d9d2012-04-25 14:24:20 -0700687static struct fs_driver_data gfx3d_fs_data = {
688 .clks = (struct fs_clk_data[]){
689 { .name = "core_clk", .reset_rate = 27000000 },
690 { .name = "iface_clk" },
691 { .name = "bus_clk" },
692 { 0 }
693 },
694 .bus_port0 = MSM_BUS_MASTER_GRAPHICS_3D,
695};
696
697static struct fs_driver_data ijpeg_fs_data = {
698 .clks = (struct fs_clk_data[]){
699 { .name = "core_clk" },
700 { .name = "iface_clk" },
701 { .name = "bus_clk" },
702 { 0 }
703 },
704 .bus_port0 = MSM_BUS_MASTER_JPEG_ENC,
705};
706
Tianyi Gou723843b2012-06-13 15:24:56 -0700707static struct fs_driver_data mdp_fs_data_8930 = {
Matt Wagantall1f65d9d2012-04-25 14:24:20 -0700708 .clks = (struct fs_clk_data[]){
709 { .name = "core_clk" },
710 { .name = "iface_clk" },
711 { .name = "bus_clk" },
712 { .name = "vsync_clk" },
713 { .name = "lut_clk" },
714 { .name = "tv_src_clk" },
715 { .name = "tv_clk" },
Matt Wagantallc33c1ed2012-07-23 17:19:08 -0700716 { .name = "reset1_clk" },
Matt Wagantall1f65d9d2012-04-25 14:24:20 -0700717 { 0 }
718 },
719 .bus_port0 = MSM_BUS_MASTER_MDP_PORT0,
720 .bus_port1 = MSM_BUS_MASTER_MDP_PORT1,
721};
722
Aravind Venkateswaranc5f91ca2012-10-29 17:54:55 -0700723static struct fs_driver_data mdp_fs_data_8930_pm8917 = {
724 .clks = (struct fs_clk_data[]){
725 { .name = "core_clk" },
726 { .name = "iface_clk" },
727 { .name = "bus_clk" },
728 { .name = "vsync_clk" },
729 { .name = "lut_clk" },
730 { .name = "reset1_clk" },
731 { 0 }
732 },
733 .bus_port0 = MSM_BUS_MASTER_MDP_PORT0,
734 .bus_port1 = MSM_BUS_MASTER_MDP_PORT1,
735};
736
Tianyi Gou723843b2012-06-13 15:24:56 -0700737static struct fs_driver_data mdp_fs_data_8627 = {
738 .clks = (struct fs_clk_data[]){
739 { .name = "core_clk" },
740 { .name = "iface_clk" },
741 { .name = "bus_clk" },
742 { .name = "vsync_clk" },
743 { .name = "lut_clk" },
744 { .name = "reset1_clk" },
745 { 0 }
746 },
747 .bus_port0 = MSM_BUS_MASTER_MDP_PORT0,
748 .bus_port1 = MSM_BUS_MASTER_MDP_PORT1,
749};
750
Matt Wagantall1f65d9d2012-04-25 14:24:20 -0700751static struct fs_driver_data rot_fs_data = {
752 .clks = (struct fs_clk_data[]){
753 { .name = "core_clk" },
754 { .name = "iface_clk" },
755 { .name = "bus_clk" },
756 { 0 }
757 },
758 .bus_port0 = MSM_BUS_MASTER_ROTATOR,
759};
760
761static struct fs_driver_data ved_fs_data = {
762 .clks = (struct fs_clk_data[]){
763 { .name = "core_clk" },
764 { .name = "iface_clk" },
765 { .name = "bus_clk" },
766 { 0 }
767 },
768 .bus_port0 = MSM_BUS_MASTER_HD_CODEC_PORT0,
769 .bus_port1 = MSM_BUS_MASTER_HD_CODEC_PORT1,
770};
771
772static struct fs_driver_data vfe_fs_data = {
773 .clks = (struct fs_clk_data[]){
774 { .name = "core_clk" },
775 { .name = "iface_clk" },
776 { .name = "bus_clk" },
777 { 0 }
778 },
779 .bus_port0 = MSM_BUS_MASTER_VFE,
780};
781
782static struct fs_driver_data vpe_fs_data = {
783 .clks = (struct fs_clk_data[]){
784 { .name = "core_clk" },
785 { .name = "iface_clk" },
786 { .name = "bus_clk" },
787 { 0 }
788 },
789 .bus_port0 = MSM_BUS_MASTER_VPE,
790};
791
792struct platform_device *msm8930_footswitch[] __initdata = {
Tianyi Gou723843b2012-06-13 15:24:56 -0700793 FS_8X60(FS_MDP, "vdd", "mdp.0", &mdp_fs_data_8930),
Matt Wagantall316f2fc2012-05-03 20:41:42 -0700794 FS_8X60(FS_ROT, "vdd", "msm_rotator.0", &rot_fs_data),
Matt Wagantalle4454b82012-05-03 20:48:01 -0700795 FS_8X60(FS_IJPEG, "vdd", "msm_gemini.0", &ijpeg_fs_data),
Kiran Kumar H Nfa18a032012-06-25 14:34:18 -0700796 FS_8X60(FS_VFE, "vdd", "msm_vfe.0", &vfe_fs_data),
797 FS_8X60(FS_VPE, "vdd", "msm_vpe.0", &vpe_fs_data),
Matt Wagantalld6fbf232012-05-03 20:09:28 -0700798 FS_8X60(FS_GFX3D, "vdd", "kgsl-3d0.0", &gfx3d_fs_data),
Matt Wagantall5e46aac2012-05-03 20:20:18 -0700799 FS_8X60(FS_VED, "vdd", "msm_vidc.0", &ved_fs_data),
Matt Wagantall1f65d9d2012-04-25 14:24:20 -0700800};
801unsigned msm8930_num_footswitch __initdata = ARRAY_SIZE(msm8930_footswitch);
802
Aravind Venkateswaranc5f91ca2012-10-29 17:54:55 -0700803struct platform_device *msm8930_pm8917_footswitch[] __initdata = {
804 FS_8X60(FS_MDP, "vdd", "mdp.0", &mdp_fs_data_8930_pm8917),
805 FS_8X60(FS_ROT, "vdd", "msm_rotator.0", &rot_fs_data),
806 FS_8X60(FS_IJPEG, "vdd", "msm_gemini.0", &ijpeg_fs_data),
807 FS_8X60(FS_VFE, "vdd", "msm_vfe.0", &vfe_fs_data),
808 FS_8X60(FS_VPE, "vdd", "msm_vpe.0", &vpe_fs_data),
809 FS_8X60(FS_GFX3D, "vdd", "kgsl-3d0.0", &gfx3d_fs_data),
810 FS_8X60(FS_VED, "vdd", "msm_vidc.0", &ved_fs_data),
811};
812unsigned msm8930_pm8917_num_footswitch __initdata =
813 ARRAY_SIZE(msm8930_pm8917_footswitch);
814
Tianyi Gou723843b2012-06-13 15:24:56 -0700815struct platform_device *msm8627_footswitch[] __initdata = {
816 FS_8X60(FS_MDP, "vdd", "mdp.0", &mdp_fs_data_8627),
817 FS_8X60(FS_ROT, "vdd", "msm_rotator.0", &rot_fs_data),
818 FS_8X60(FS_IJPEG, "vdd", "msm_gemini.0", &ijpeg_fs_data),
819 FS_8X60(FS_VFE, "vdd", "msm_vfe.0", &vfe_fs_data),
820 FS_8X60(FS_VPE, "vdd", "msm_vpe.0", &vpe_fs_data),
821 FS_8X60(FS_GFX3D, "vdd", "kgsl-3d0.0", &gfx3d_fs_data),
822 FS_8X60(FS_VED, "vdd", "msm_vidc.0", &ved_fs_data),
823};
824unsigned msm8627_num_footswitch __initdata = ARRAY_SIZE(msm8627_footswitch);
825
Arun Menonaabf2632012-02-24 15:30:47 -0800826/* MSM Video core device */
827#ifdef CONFIG_MSM_BUS_SCALING
828static struct msm_bus_vectors vidc_init_vectors[] = {
829 {
830 .src = MSM_BUS_MASTER_HD_CODEC_PORT0,
831 .dst = MSM_BUS_SLAVE_EBI_CH0,
832 .ab = 0,
833 .ib = 0,
834 },
835 {
836 .src = MSM_BUS_MASTER_HD_CODEC_PORT1,
837 .dst = MSM_BUS_SLAVE_EBI_CH0,
838 .ab = 0,
839 .ib = 0,
840 },
841 {
842 .src = MSM_BUS_MASTER_AMPSS_M0,
843 .dst = MSM_BUS_SLAVE_EBI_CH0,
844 .ab = 0,
845 .ib = 0,
846 },
847 {
848 .src = MSM_BUS_MASTER_AMPSS_M0,
849 .dst = MSM_BUS_SLAVE_EBI_CH0,
850 .ab = 0,
851 .ib = 0,
852 },
853};
854static struct msm_bus_vectors vidc_venc_vga_vectors[] = {
855 {
856 .src = MSM_BUS_MASTER_HD_CODEC_PORT0,
857 .dst = MSM_BUS_SLAVE_EBI_CH0,
858 .ab = 54525952,
859 .ib = 436207616,
860 },
861 {
862 .src = MSM_BUS_MASTER_HD_CODEC_PORT1,
863 .dst = MSM_BUS_SLAVE_EBI_CH0,
864 .ab = 72351744,
865 .ib = 289406976,
866 },
867 {
868 .src = MSM_BUS_MASTER_AMPSS_M0,
869 .dst = MSM_BUS_SLAVE_EBI_CH0,
870 .ab = 500000,
871 .ib = 1000000,
872 },
873 {
874 .src = MSM_BUS_MASTER_AMPSS_M0,
875 .dst = MSM_BUS_SLAVE_EBI_CH0,
876 .ab = 500000,
877 .ib = 1000000,
878 },
879};
880static struct msm_bus_vectors vidc_vdec_vga_vectors[] = {
881 {
882 .src = MSM_BUS_MASTER_HD_CODEC_PORT0,
883 .dst = MSM_BUS_SLAVE_EBI_CH0,
884 .ab = 40894464,
885 .ib = 327155712,
886 },
887 {
888 .src = MSM_BUS_MASTER_HD_CODEC_PORT1,
889 .dst = MSM_BUS_SLAVE_EBI_CH0,
890 .ab = 48234496,
891 .ib = 192937984,
892 },
893 {
894 .src = MSM_BUS_MASTER_AMPSS_M0,
895 .dst = MSM_BUS_SLAVE_EBI_CH0,
896 .ab = 500000,
897 .ib = 2000000,
898 },
899 {
900 .src = MSM_BUS_MASTER_AMPSS_M0,
901 .dst = MSM_BUS_SLAVE_EBI_CH0,
902 .ab = 500000,
903 .ib = 2000000,
904 },
905};
906static struct msm_bus_vectors vidc_venc_720p_vectors[] = {
907 {
908 .src = MSM_BUS_MASTER_HD_CODEC_PORT0,
909 .dst = MSM_BUS_SLAVE_EBI_CH0,
910 .ab = 163577856,
911 .ib = 1308622848,
912 },
913 {
914 .src = MSM_BUS_MASTER_HD_CODEC_PORT1,
915 .dst = MSM_BUS_SLAVE_EBI_CH0,
916 .ab = 219152384,
917 .ib = 876609536,
918 },
919 {
920 .src = MSM_BUS_MASTER_AMPSS_M0,
921 .dst = MSM_BUS_SLAVE_EBI_CH0,
922 .ab = 1750000,
923 .ib = 3500000,
924 },
925 {
926 .src = MSM_BUS_MASTER_AMPSS_M0,
927 .dst = MSM_BUS_SLAVE_EBI_CH0,
928 .ab = 1750000,
929 .ib = 3500000,
930 },
931};
932static struct msm_bus_vectors vidc_vdec_720p_vectors[] = {
933 {
934 .src = MSM_BUS_MASTER_HD_CODEC_PORT0,
935 .dst = MSM_BUS_SLAVE_EBI_CH0,
936 .ab = 121634816,
937 .ib = 973078528,
938 },
939 {
940 .src = MSM_BUS_MASTER_HD_CODEC_PORT1,
941 .dst = MSM_BUS_SLAVE_EBI_CH0,
942 .ab = 155189248,
943 .ib = 620756992,
944 },
945 {
946 .src = MSM_BUS_MASTER_AMPSS_M0,
947 .dst = MSM_BUS_SLAVE_EBI_CH0,
948 .ab = 1750000,
949 .ib = 7000000,
950 },
951 {
952 .src = MSM_BUS_MASTER_AMPSS_M0,
953 .dst = MSM_BUS_SLAVE_EBI_CH0,
954 .ab = 1750000,
955 .ib = 7000000,
956 },
957};
Nishant Pandit7331bd92013-04-16 05:59:22 +0530958/*This value is modified because internally we use
959 * lower value. But OEM has increased it. This is correct value
960 * for oem*/
Arun Menonaabf2632012-02-24 15:30:47 -0800961static struct msm_bus_vectors vidc_venc_1080p_vectors[] = {
962 {
963 .src = MSM_BUS_MASTER_HD_CODEC_PORT0,
964 .dst = MSM_BUS_SLAVE_EBI_CH0,
Nishant Pandit7331bd92013-04-16 05:59:22 +0530965 .ab = 400000000,
Arun Menonaabf2632012-02-24 15:30:47 -0800966 .ib = 2560000000U,
967 },
968 {
969 .src = MSM_BUS_MASTER_HD_CODEC_PORT1,
970 .dst = MSM_BUS_SLAVE_EBI_CH0,
Nishant Pandit7331bd92013-04-16 05:59:22 +0530971 .ab = 550000000,
Arun Menonaabf2632012-02-24 15:30:47 -0800972 .ib = 2560000000U,
973 },
974 {
975 .src = MSM_BUS_MASTER_AMPSS_M0,
976 .dst = MSM_BUS_SLAVE_EBI_CH0,
977 .ab = 2500000,
978 .ib = 5000000,
979 },
980 {
981 .src = MSM_BUS_MASTER_AMPSS_M0,
982 .dst = MSM_BUS_SLAVE_EBI_CH0,
983 .ab = 2500000,
984 .ib = 5000000,
985 },
986};
987static struct msm_bus_vectors vidc_vdec_1080p_vectors[] = {
988 {
989 .src = MSM_BUS_MASTER_HD_CODEC_PORT0,
990 .dst = MSM_BUS_SLAVE_EBI_CH0,
991 .ab = 222298112,
992 .ib = 2560000000U,
993 },
994 {
995 .src = MSM_BUS_MASTER_HD_CODEC_PORT1,
996 .dst = MSM_BUS_SLAVE_EBI_CH0,
997 .ab = 330301440,
998 .ib = 2560000000U,
999 },
1000 {
1001 .src = MSM_BUS_MASTER_AMPSS_M0,
1002 .dst = MSM_BUS_SLAVE_EBI_CH0,
1003 .ab = 2500000,
1004 .ib = 700000000,
1005 },
1006 {
1007 .src = MSM_BUS_MASTER_AMPSS_M0,
1008 .dst = MSM_BUS_SLAVE_EBI_CH0,
1009 .ab = 2500000,
1010 .ib = 10000000,
1011 },
1012};
Arun Menonb31fefd2012-07-19 14:02:13 -07001013static struct msm_bus_vectors vidc_venc_1080p_turbo_vectors[] = {
1014 {
1015 .src = MSM_BUS_MASTER_HD_CODEC_PORT0,
1016 .dst = MSM_BUS_SLAVE_EBI_CH0,
1017 .ab = 222298112,
1018 .ib = 3522000000U,
1019 },
1020 {
1021 .src = MSM_BUS_MASTER_HD_CODEC_PORT1,
1022 .dst = MSM_BUS_SLAVE_EBI_CH0,
1023 .ab = 330301440,
1024 .ib = 3522000000U,
1025 },
1026 {
1027 .src = MSM_BUS_MASTER_AMPSS_M0,
1028 .dst = MSM_BUS_SLAVE_EBI_CH0,
1029 .ab = 2500000,
1030 .ib = 700000000,
1031 },
1032 {
1033 .src = MSM_BUS_MASTER_AMPSS_M0,
1034 .dst = MSM_BUS_SLAVE_EBI_CH0,
1035 .ab = 2500000,
1036 .ib = 10000000,
1037 },
1038};
1039static struct msm_bus_vectors vidc_vdec_1080p_turbo_vectors[] = {
1040 {
1041 .src = MSM_BUS_MASTER_HD_CODEC_PORT0,
1042 .dst = MSM_BUS_SLAVE_EBI_CH0,
1043 .ab = 222298112,
1044 .ib = 3522000000U,
1045 },
1046 {
1047 .src = MSM_BUS_MASTER_HD_CODEC_PORT1,
1048 .dst = MSM_BUS_SLAVE_EBI_CH0,
1049 .ab = 330301440,
1050 .ib = 3522000000U,
1051 },
1052 {
1053 .src = MSM_BUS_MASTER_AMPSS_M0,
1054 .dst = MSM_BUS_SLAVE_EBI_CH0,
1055 .ab = 2500000,
1056 .ib = 700000000,
1057 },
1058 {
1059 .src = MSM_BUS_MASTER_AMPSS_M0,
1060 .dst = MSM_BUS_SLAVE_EBI_CH0,
1061 .ab = 2500000,
1062 .ib = 10000000,
1063 },
1064};
Arun Menonaabf2632012-02-24 15:30:47 -08001065
1066static struct msm_bus_paths vidc_bus_client_config[] = {
1067 {
1068 ARRAY_SIZE(vidc_init_vectors),
1069 vidc_init_vectors,
1070 },
1071 {
1072 ARRAY_SIZE(vidc_venc_vga_vectors),
1073 vidc_venc_vga_vectors,
1074 },
1075 {
1076 ARRAY_SIZE(vidc_vdec_vga_vectors),
1077 vidc_vdec_vga_vectors,
1078 },
1079 {
1080 ARRAY_SIZE(vidc_venc_720p_vectors),
1081 vidc_venc_720p_vectors,
1082 },
1083 {
1084 ARRAY_SIZE(vidc_vdec_720p_vectors),
1085 vidc_vdec_720p_vectors,
1086 },
1087 {
1088 ARRAY_SIZE(vidc_venc_1080p_vectors),
1089 vidc_venc_1080p_vectors,
1090 },
1091 {
1092 ARRAY_SIZE(vidc_vdec_1080p_vectors),
1093 vidc_vdec_1080p_vectors,
1094 },
Arun Menonb31fefd2012-07-19 14:02:13 -07001095 {
1096 ARRAY_SIZE(vidc_venc_1080p_turbo_vectors),
1097 vidc_vdec_1080p_turbo_vectors,
1098 },
1099 {
1100 ARRAY_SIZE(vidc_vdec_1080p_turbo_vectors),
1101 vidc_vdec_1080p_turbo_vectors,
1102 },
Arun Menonaabf2632012-02-24 15:30:47 -08001103};
1104
1105static struct msm_bus_scale_pdata vidc_bus_client_data = {
1106 vidc_bus_client_config,
1107 ARRAY_SIZE(vidc_bus_client_config),
1108 .name = "vidc",
1109};
1110#endif
1111
1112#define MSM_VIDC_BASE_PHYS 0x04400000
1113#define MSM_VIDC_BASE_SIZE 0x00100000
1114
1115static struct resource apq8930_device_vidc_resources[] = {
1116 {
1117 .start = MSM_VIDC_BASE_PHYS,
1118 .end = MSM_VIDC_BASE_PHYS + MSM_VIDC_BASE_SIZE - 1,
1119 .flags = IORESOURCE_MEM,
1120 },
1121 {
1122 .start = VCODEC_IRQ,
1123 .end = VCODEC_IRQ,
1124 .flags = IORESOURCE_IRQ,
1125 },
1126};
1127
1128struct msm_vidc_platform_data apq8930_vidc_platform_data = {
1129#ifdef CONFIG_MSM_BUS_SCALING
1130 .vidc_bus_client_pdata = &vidc_bus_client_data,
1131#endif
1132#ifdef CONFIG_MSM_MULTIMEDIA_USE_ION
1133 .memtype = ION_CP_MM_HEAP_ID,
1134 .enable_ion = 1,
Deepak Kotur8097f782012-05-14 14:13:06 -07001135 .cp_enabled = 1,
Arun Menonaabf2632012-02-24 15:30:47 -08001136#else
1137 .memtype = MEMTYPE_EBI1,
1138 .enable_ion = 0,
1139#endif
Anil Gahlotd0ce26d2012-05-08 17:58:46 -07001140 .disable_dmx = 1,
Arun Menonaabf2632012-02-24 15:30:47 -08001141 .disable_fullhd = 0,
Mohan Kumar Gubbihalli Lachma Naik42de2412012-10-26 17:55:27 -07001142 .cont_mode_dpb_count = 18,
Riaz Rahaman84f8c682012-05-30 13:32:10 +05301143 .fw_addr = 0x9fe00000,
Deepak Verma587c98e2013-02-01 22:47:49 +05301144 .enable_sec_metadata = 0,
Arun Menonaabf2632012-02-24 15:30:47 -08001145};
1146
1147struct platform_device apq8930_msm_device_vidc = {
1148 .name = "msm_vidc",
1149 .id = 0,
1150 .num_resources = ARRAY_SIZE(apq8930_device_vidc_resources),
1151 .resource = apq8930_device_vidc_resources,
1152 .dev = {
1153 .platform_data = &apq8930_vidc_platform_data,
1154 },
1155};
1156
1157struct platform_device *vidc_device[] __initdata = {
1158 &apq8930_msm_device_vidc
1159};
1160
1161void __init msm8930_add_vidc_device(void)
1162{
1163 if (cpu_is_msm8627()) {
1164 struct msm_vidc_platform_data *pdata;
1165 pdata = (struct msm_vidc_platform_data *)
1166 apq8930_msm_device_vidc.dev.platform_data;
1167 pdata->disable_fullhd = 1;
1168 }
1169 platform_add_devices(vidc_device, ARRAY_SIZE(vidc_device));
1170}
Laura Abbott0577d7b2012-04-17 11:14:30 -07001171
1172struct msm_iommu_domain_name msm8930_iommu_ctx_names[] = {
1173 /* Camera */
1174 {
Laura Abbott0577d7b2012-04-17 11:14:30 -07001175 .name = "ijpeg_src",
1176 .domain = CAMERA_DOMAIN,
1177 },
1178 /* Camera */
1179 {
1180 .name = "ijpeg_dst",
1181 .domain = CAMERA_DOMAIN,
1182 },
1183 /* Camera */
1184 {
1185 .name = "jpegd_src",
1186 .domain = CAMERA_DOMAIN,
1187 },
1188 /* Camera */
1189 {
1190 .name = "jpegd_dst",
1191 .domain = CAMERA_DOMAIN,
1192 },
1193 /* Rotator */
1194 {
1195 .name = "rot_src",
Olav Hauganef95ae32012-05-15 09:50:30 -07001196 .domain = ROTATOR_SRC_DOMAIN,
Laura Abbott0577d7b2012-04-17 11:14:30 -07001197 },
1198 /* Rotator */
1199 {
1200 .name = "rot_dst",
Olav Hauganef95ae32012-05-15 09:50:30 -07001201 .domain = ROTATOR_SRC_DOMAIN,
Laura Abbott0577d7b2012-04-17 11:14:30 -07001202 },
1203 /* Video */
1204 {
1205 .name = "vcodec_a_mm1",
1206 .domain = VIDEO_DOMAIN,
1207 },
1208 /* Video */
1209 {
1210 .name = "vcodec_b_mm2",
1211 .domain = VIDEO_DOMAIN,
1212 },
1213 /* Video */
1214 {
1215 .name = "vcodec_a_stream",
1216 .domain = VIDEO_DOMAIN,
1217 },
1218};
1219
1220static struct mem_pool msm8930_video_pools[] = {
1221 /*
1222 * Video hardware has the following requirements:
1223 * 1. All video addresses used by the video hardware must be at a higher
1224 * address than video firmware address.
1225 * 2. Video hardware can only access a range of 256MB from the base of
1226 * the video firmware.
1227 */
1228 [VIDEO_FIRMWARE_POOL] =
1229 /* Low addresses, intended for video firmware */
1230 {
1231 .paddr = SZ_128K,
1232 .size = SZ_16M - SZ_128K,
1233 },
1234 [VIDEO_MAIN_POOL] =
1235 /* Main video pool */
1236 {
1237 .paddr = SZ_16M,
1238 .size = SZ_256M - SZ_16M,
1239 },
1240 [GEN_POOL] =
1241 /* Remaining address space up to 2G */
1242 {
1243 .paddr = SZ_256M,
1244 .size = SZ_2G - SZ_256M,
1245 },
1246};
1247
1248static struct mem_pool msm8930_camera_pools[] = {
1249 [GEN_POOL] =
1250 /* One address space for camera */
1251 {
1252 .paddr = SZ_128K,
1253 .size = SZ_2G - SZ_128K,
1254 },
1255};
1256
Olav Hauganef95ae32012-05-15 09:50:30 -07001257static struct mem_pool msm8930_display_read_pools[] = {
Laura Abbott0577d7b2012-04-17 11:14:30 -07001258 [GEN_POOL] =
Olav Hauganef95ae32012-05-15 09:50:30 -07001259 /* One address space for display reads */
Laura Abbott0577d7b2012-04-17 11:14:30 -07001260 {
1261 .paddr = SZ_128K,
1262 .size = SZ_2G - SZ_128K,
1263 },
1264};
1265
Olav Hauganef95ae32012-05-15 09:50:30 -07001266static struct mem_pool msm8930_rotator_src_pools[] = {
Laura Abbott0577d7b2012-04-17 11:14:30 -07001267 [GEN_POOL] =
Olav Hauganef95ae32012-05-15 09:50:30 -07001268 /* One address space for rotator src */
Laura Abbott0577d7b2012-04-17 11:14:30 -07001269 {
1270 .paddr = SZ_128K,
1271 .size = SZ_2G - SZ_128K,
1272 },
1273};
1274
1275static struct msm_iommu_domain msm8930_iommu_domains[] = {
1276 [VIDEO_DOMAIN] = {
1277 .iova_pools = msm8930_video_pools,
1278 .npools = ARRAY_SIZE(msm8930_video_pools),
1279 },
1280 [CAMERA_DOMAIN] = {
1281 .iova_pools = msm8930_camera_pools,
1282 .npools = ARRAY_SIZE(msm8930_camera_pools),
1283 },
Olav Hauganef95ae32012-05-15 09:50:30 -07001284 [DISPLAY_READ_DOMAIN] = {
1285 .iova_pools = msm8930_display_read_pools,
1286 .npools = ARRAY_SIZE(msm8930_display_read_pools),
Laura Abbott0577d7b2012-04-17 11:14:30 -07001287 },
Olav Hauganef95ae32012-05-15 09:50:30 -07001288 [ROTATOR_SRC_DOMAIN] = {
1289 .iova_pools = msm8930_rotator_src_pools,
1290 .npools = ARRAY_SIZE(msm8930_rotator_src_pools),
Laura Abbott0577d7b2012-04-17 11:14:30 -07001291 },
1292};
1293
1294struct iommu_domains_pdata msm8930_iommu_domain_pdata = {
1295 .domains = msm8930_iommu_domains,
1296 .ndomains = ARRAY_SIZE(msm8930_iommu_domains),
1297 .domain_names = msm8930_iommu_ctx_names,
1298 .nnames = ARRAY_SIZE(msm8930_iommu_ctx_names),
1299 .domain_alloc_flags = 0,
1300};
1301
1302struct platform_device msm8930_iommu_domain_device = {
1303 .name = "iommu_domains",
1304 .id = -1,
1305 .dev = {
1306 .platform_data = &msm8930_iommu_domain_pdata,
Laura Abbott532b2df2012-04-12 10:53:48 -07001307 }
1308};
1309
1310struct msm_rtb_platform_data msm8930_rtb_pdata = {
1311 .size = SZ_1M,
1312};
1313
1314static int __init msm_rtb_set_buffer_size(char *p)
1315{
1316 int s;
1317
1318 s = memparse(p, NULL);
1319 msm8930_rtb_pdata.size = ALIGN(s, SZ_4K);
1320 return 0;
1321}
1322early_param("msm_rtb_size", msm_rtb_set_buffer_size);
1323
1324
1325struct platform_device msm8930_rtb_device = {
1326 .name = "msm_rtb",
1327 .id = -1,
1328 .dev = {
1329 .platform_data = &msm8930_rtb_pdata,
Laura Abbott0577d7b2012-04-17 11:14:30 -07001330 },
1331};
Laura Abbottf3173042012-05-29 15:23:18 -07001332
1333#define MSM8930_L1_SIZE SZ_1M
1334/*
1335 * The actual L2 size is smaller but we need a larger buffer
1336 * size to store other dump information
1337 */
1338#define MSM8930_L2_SIZE SZ_4M
1339
1340struct msm_cache_dump_platform_data msm8930_cache_dump_pdata = {
1341 .l2_size = MSM8930_L2_SIZE,
1342 .l1_size = MSM8930_L1_SIZE,
1343};
1344
1345struct platform_device msm8930_cache_dump_device = {
1346 .name = "msm_cache_dump",
1347 .id = -1,
1348 .dev = {
1349 .platform_data = &msm8930_cache_dump_pdata,
1350 },
1351};