| Paul Walmsley | 69d88a0 | 2008-03-18 10:02:50 +0200 | [diff] [blame] | 1 | #ifndef ____ASM_ARCH_SDRC_H |
| 2 | #define ____ASM_ARCH_SDRC_H |
| 3 | |
| 4 | /* |
| 5 | * OMAP2/3 SDRC/SMS register definitions |
| 6 | * |
| 7 | * Copyright (C) 2007 Texas Instruments, Inc. |
| 8 | * Copyright (C) 2007 Nokia Corporation |
| 9 | * |
| 10 | * Written by Paul Walmsley |
| 11 | * |
| 12 | * This program is free software; you can redistribute it and/or modify |
| 13 | * it under the terms of the GNU General Public License version 2 as |
| 14 | * published by the Free Software Foundation. |
| 15 | */ |
| 16 | |
| 17 | #include <asm/arch/io.h> |
| 18 | |
| 19 | /* SDRC register offsets - read/write with sdrc_{read,write}_reg() */ |
| 20 | |
| 21 | #define SDRC_SYSCONFIG 0x010 |
| 22 | #define SDRC_DLLA_CTRL 0x060 |
| 23 | #define SDRC_DLLA_STATUS 0x064 |
| 24 | #define SDRC_DLLB_CTRL 0x068 |
| 25 | #define SDRC_DLLB_STATUS 0x06C |
| 26 | #define SDRC_POWER 0x070 |
| 27 | #define SDRC_MR_0 0x084 |
| 28 | #define SDRC_RFR_CTRL_0 0x0a4 |
| 29 | |
| 30 | /* |
| 31 | * These values represent the number of memory clock cycles between |
| 32 | * autorefresh initiation. They assume 1 refresh per 64 ms (JEDEC), 8192 |
| 33 | * rows per device, and include a subtraction of a 50 cycle window in the |
| 34 | * event that the autorefresh command is delayed due to other SDRC activity. |
| 35 | * The '| 1' sets the ARE field to send one autorefresh when the autorefresh |
| 36 | * counter reaches 0. |
| 37 | * |
| 38 | * These represent optimal values for common parts, it won't work for all. |
| 39 | * As long as you scale down, most parameters are still work, they just |
| 40 | * become sub-optimal. The RFR value goes in the opposite direction. If you |
| 41 | * don't adjust it down as your clock period increases the refresh interval |
| 42 | * will not be met. Setting all parameters for complete worst case may work, |
| 43 | * but may cut memory performance by 2x. Due to errata the DLLs need to be |
| 44 | * unlocked and their value needs run time calibration. A dynamic call is |
| 45 | * need for that as no single right value exists acorss production samples. |
| 46 | * |
| 47 | * Only the FULL speed values are given. Current code is such that rate |
| 48 | * changes must be made at DPLLoutx2. The actual value adjustment for low |
| 49 | * frequency operation will be handled by omap_set_performance() |
| 50 | * |
| 51 | * By having the boot loader boot up in the fastest L4 speed available likely |
| 52 | * will result in something which you can switch between. |
| 53 | */ |
| 54 | #define SDRC_RFR_CTRL_165MHz (0x00044c00 | 1) |
| 55 | #define SDRC_RFR_CTRL_133MHz (0x0003de00 | 1) |
| 56 | #define SDRC_RFR_CTRL_100MHz (0x0002da01 | 1) |
| 57 | #define SDRC_RFR_CTRL_110MHz (0x0002da01 | 1) /* Need to calc */ |
| 58 | #define SDRC_RFR_CTRL_BYPASS (0x00005000 | 1) /* Need to calc */ |
| 59 | |
| 60 | |
| 61 | /* |
| 62 | * SMS register access |
| 63 | */ |
| 64 | |
| 65 | |
| 66 | #define OMAP242X_SMS_REGADDR(reg) (void __iomem *)IO_ADDRESS(OMAP2420_SMS_BASE + reg) |
| 67 | #define OMAP243X_SMS_REGADDR(reg) (void __iomem *)IO_ADDRESS(OMAP243X_SMS_BASE + reg) |
| 68 | #define OMAP343X_SMS_REGADDR(reg) (void __iomem *)IO_ADDRESS(OMAP343X_SMS_BASE + reg) |
| 69 | |
| 70 | /* SMS register offsets - read/write with sms_{read,write}_reg() */ |
| 71 | |
| 72 | #define SMS_SYSCONFIG 0x010 |
| 73 | /* REVISIT: fill in other SMS registers here */ |
| 74 | |
| 75 | #endif |