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Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001/* Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved.
Steve Mucklea55df6e2010-01-07 12:43:24 -08002 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 *
Steve Mucklea55df6e2010-01-07 12:43:24 -080012 */
13
14#include <linux/kernel.h>
15#include <linux/platform_device.h>
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070016#include <linux/gpio.h>
Steve Muckle9161d302010-02-11 11:50:40 -080017#include <linux/irq.h>
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070018#include <linux/io.h>
19#include <linux/mfd/pmic8058.h>
Steve Mucklea55df6e2010-01-07 12:43:24 -080020
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070021#include <linux/input/pmic8058-keypad.h>
22#include <linux/pmic8058-batt-alarm.h>
23#include <linux/pmic8058-pwrkey.h>
Ashay Jaiswal4d1ab552011-07-15 11:30:49 +053024#include <linux/rtc/rtc-pm8058.h>
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070025#include <linux/pmic8058-vibrator.h>
26#include <linux/leds.h>
27#include <linux/pmic8058-othc.h>
28#include <linux/mfd/pmic8901.h>
29#include <linux/regulator/pmic8058-regulator.h>
30#include <linux/regulator/pmic8901-regulator.h>
31#include <linux/bootmem.h>
32#include <linux/pwm.h>
33#include <linux/pmic8058-pwm.h>
34#include <linux/leds-pmic8058.h>
35#include <linux/pmic8058-xoadc.h>
36#include <linux/msm_adc.h>
37#include <linux/m_adcproc.h>
38#include <linux/mfd/marimba.h>
39#include <linux/msm-charger.h>
40#include <linux/i2c.h>
41#include <linux/i2c/sx150x.h>
42#include <linux/smsc911x.h>
43#include <linux/spi/spi.h>
44#include <linux/input/tdisc_shinetsu.h>
45#include <linux/input/cy8c_ts.h>
46#include <linux/cyttsp.h>
47#include <linux/i2c/isa1200.h>
48#include <linux/dma-mapping.h>
49#include <linux/i2c/bq27520.h>
50
51#ifdef CONFIG_ANDROID_PMEM
52#include <linux/android_pmem.h>
53#endif
54
55#if defined(CONFIG_SMB137B_CHARGER) || defined(CONFIG_SMB137B_CHARGER_MODULE)
56#include <linux/i2c/smb137b.h>
57#endif
Lei Zhou338cab82011-08-19 13:38:17 -040058#ifdef CONFIG_SND_SOC_WM8903
59#include <sound/wm8903.h>
60#endif
Steve Mucklea55df6e2010-01-07 12:43:24 -080061#include <asm/mach-types.h>
62#include <asm/mach/arch.h>
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070063#include <asm/setup.h>
Steve Mucklea55df6e2010-01-07 12:43:24 -080064
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070065#include <mach/dma.h>
66#include <mach/mpp.h>
Steve Mucklea55df6e2010-01-07 12:43:24 -080067#include <mach/board.h>
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070068#include <mach/irqs.h>
69#include <mach/msm_spi.h>
70#include <mach/msm_serial_hs.h>
71#include <mach/msm_serial_hs_lite.h>
Steve Mucklea55df6e2010-01-07 12:43:24 -080072#include <mach/msm_iomap.h>
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070073#include <mach/msm_memtypes.h>
74#include <asm/mach/mmc.h>
75#include <mach/msm_battery.h>
76#include <mach/msm_hsusb.h>
Rohit Vaswania513aa8d2011-07-18 15:14:28 -070077#include <mach/gpiomux.h>
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070078#ifdef CONFIG_MSM_DSPS
79#include <mach/msm_dsps.h>
80#endif
81#include <mach/msm_xo.h>
82#include <mach/msm_bus_board.h>
83#include <mach/socinfo.h>
84#include <linux/i2c/isl9519.h>
85#ifdef CONFIG_USB_G_ANDROID
86#include <linux/usb/android.h>
87#include <mach/usbdiag.h>
88#endif
89#include <linux/regulator/consumer.h>
90#include <linux/regulator/machine.h>
91#include <mach/sdio_al.h>
92#include <mach/rpm.h>
93#include <mach/rpm-regulator.h>
Abhijeet Dharmapurikar6d565fd2011-09-15 18:49:56 -070094#include <mach/restart.h>
Steve Mucklea55df6e2010-01-07 12:43:24 -080095
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070096#include "devices.h"
97#include "devices-msm8x60.h"
98#include "cpuidle.h"
99#include "pm.h"
100#include "mpm.h"
101#include "spm.h"
102#include "rpm_log.h"
103#include "timer.h"
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700104#include "gpiomux-8x60.h"
105#include "rpm_stats.h"
106#include "peripheral-loader.h"
107#include <linux/platform_data/qcom_crypto_device.h>
108#include "rpm_resources.h"
Matt Wagantall6d9ebee2011-08-26 12:15:24 -0700109#include "acpuclock.h"
Steve Mucklea55df6e2010-01-07 12:43:24 -0800110
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700111#define MSM_SHARED_RAM_PHYS 0x40000000
112
113/* Macros assume PMIC GPIOs start at 0 */
114#define PM8058_GPIO_BASE NR_MSM_GPIOS
115#define PM8058_GPIO_PM_TO_SYS(pm_gpio) (pm_gpio + PM8058_GPIO_BASE)
116#define PM8058_GPIO_SYS_TO_PM(sys_gpio) (sys_gpio - PM8058_GPIO_BASE)
117#define PM8058_MPP_BASE (PM8058_GPIO_BASE + PM8058_GPIOS)
118#define PM8058_MPP_PM_TO_SYS(pm_gpio) (pm_gpio + PM8058_MPP_BASE)
119#define PM8058_MPP_SYS_TO_PM(sys_gpio) (sys_gpio - PM8058_MPP_BASE)
120#define PM8058_IRQ_BASE (NR_MSM_IRQS + NR_GPIO_IRQS)
121
122#define PM8901_GPIO_BASE (PM8058_GPIO_BASE + \
123 PM8058_GPIOS + PM8058_MPPS)
124#define PM8901_GPIO_PM_TO_SYS(pm_gpio) (pm_gpio + PM8901_GPIO_BASE)
125#define PM8901_GPIO_SYS_TO_PM(sys_gpio) (sys_gpio - PM901_GPIO_BASE)
126#define PM8901_IRQ_BASE (PM8058_IRQ_BASE + \
127 NR_PMIC8058_IRQS)
128
129#define MDM2AP_SYNC 129
130
Terence Hampson1c73fef2011-07-19 17:10:49 -0400131#define GPIO_ETHERNET_RESET_N_DRAGON 30
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700132#define LCDC_SPI_GPIO_CLK 73
133#define LCDC_SPI_GPIO_CS 72
134#define LCDC_SPI_GPIO_MOSI 70
135#define LCDC_AUO_PANEL_NAME "lcdc_auo_wvga"
136#define LCDC_SAMSUNG_OLED_PANEL_NAME "lcdc_samsung_oled"
137#define LCDC_SAMSUNG_WSVGA_PANEL_NAME "lcdc_samsung_wsvga"
138#define LCDC_SAMSUNG_SPI_DEVICE_NAME "lcdc_samsung_ams367pe02"
139#define LCDC_AUO_SPI_DEVICE_NAME "lcdc_auo_nt35582"
Zhang Chang Ken3a8b8512011-08-04 18:41:39 -0400140#define LCDC_NT35582_PANEL_NAME "lcdc_nt35582_wvga"
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700141
Ravishangar Kalyanam61a7bd12011-07-28 16:48:36 -0700142#define PANEL_NAME_MAX_LEN 30
143#define MIPI_CMD_NOVATEK_QHD_PANEL_NAME "mipi_cmd_novatek_qhd"
144#define MIPI_VIDEO_NOVATEK_QHD_PANEL_NAME "mipi_video_novatek_qhd"
145#define MIPI_VIDEO_TOSHIBA_WVGA_PANEL_NAME "mipi_video_toshiba_wvga"
146#define HDMI_PANEL_NAME "hdmi_msm"
147#define TVOUT_PANEL_NAME "tvout_msm"
148
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700149#define DSPS_PIL_GENERIC_NAME "dsps"
150#define DSPS_PIL_FLUID_NAME "dsps_fluid"
151
152enum {
153 GPIO_EXPANDER_IRQ_BASE = PM8901_IRQ_BASE + NR_PMIC8901_IRQS,
154 GPIO_EXPANDER_GPIO_BASE = PM8901_GPIO_BASE + PM8901_MPPS,
155 /* CORE expander */
156 GPIO_CORE_EXPANDER_BASE = GPIO_EXPANDER_GPIO_BASE,
157 GPIO_CLASS_D1_EN = GPIO_CORE_EXPANDER_BASE,
158 GPIO_WLAN_DEEP_SLEEP_N,
159 GPIO_LVDS_SHUTDOWN_N,
160 GPIO_DISP_RESX_N = GPIO_LVDS_SHUTDOWN_N,
161 GPIO_MS_SYS_RESET_N,
162 GPIO_CAP_TS_RESOUT_N,
163 GPIO_CAP_GAUGE_BI_TOUT,
164 GPIO_ETHERNET_PME,
165 GPIO_EXT_GPS_LNA_EN,
166 GPIO_MSM_WAKES_BT,
167 GPIO_ETHERNET_RESET_N,
168 GPIO_HEADSET_DET_N,
169 GPIO_USB_UICC_EN,
170 GPIO_BACKLIGHT_EN,
171 GPIO_EXT_CAMIF_PWR_EN,
172 GPIO_BATT_GAUGE_INT_N,
173 GPIO_BATT_GAUGE_EN,
174 /* DOCKING expander */
175 GPIO_DOCKING_EXPANDER_BASE = GPIO_EXPANDER_GPIO_BASE + 16,
176 GPIO_MIPI_DSI_RST_N = GPIO_DOCKING_EXPANDER_BASE,
177 GPIO_AUX_JTAG_DET_N,
178 GPIO_DONGLE_DET_N,
179 GPIO_SVIDEO_LOAD_DET,
180 GPIO_SVID_AMP_SHUTDOWN1_N,
181 GPIO_SVID_AMP_SHUTDOWN0_N,
182 GPIO_SDC_WP,
183 GPIO_IRDA_PWDN,
184 GPIO_IRDA_RESET_N,
185 GPIO_DONGLE_GPIO0,
186 GPIO_DONGLE_GPIO1,
187 GPIO_DONGLE_GPIO2,
188 GPIO_DONGLE_GPIO3,
189 GPIO_DONGLE_PWR_EN,
190 GPIO_EMMC_RESET_N,
191 GPIO_TP_EXP2_IO15,
192 /* SURF expander */
193 GPIO_SURF_EXPANDER_BASE = GPIO_EXPANDER_GPIO_BASE + (16 * 2),
194 GPIO_SD_CARD_DET_1 = GPIO_SURF_EXPANDER_BASE,
195 GPIO_SD_CARD_DET_2,
196 GPIO_SD_CARD_DET_4,
197 GPIO_SD_CARD_DET_5,
198 GPIO_UIM3_RST,
199 GPIO_SURF_EXPANDER_IO5,
200 GPIO_SURF_EXPANDER_IO6,
201 GPIO_ADC_I2C_EN,
202 GPIO_SURF_EXPANDER_IO8,
203 GPIO_SURF_EXPANDER_IO9,
204 GPIO_SURF_EXPANDER_IO10,
205 GPIO_SURF_EXPANDER_IO11,
206 GPIO_SURF_EXPANDER_IO12,
207 GPIO_SURF_EXPANDER_IO13,
208 GPIO_SURF_EXPANDER_IO14,
209 GPIO_SURF_EXPANDER_IO15,
210 /* LEFT KB IO expander */
211 GPIO_LEFT_KB_EXPANDER_BASE = GPIO_EXPANDER_GPIO_BASE + (16 * 3),
212 GPIO_LEFT_LED_1 = GPIO_LEFT_KB_EXPANDER_BASE,
213 GPIO_LEFT_LED_2,
214 GPIO_LEFT_LED_3,
215 GPIO_LEFT_LED_WLAN,
216 GPIO_JOYSTICK_EN,
217 GPIO_CAP_TS_SLEEP,
218 GPIO_LEFT_KB_IO6,
219 GPIO_LEFT_LED_5,
220 /* RIGHT KB IO expander */
221 GPIO_RIGHT_KB_EXPANDER_BASE = GPIO_EXPANDER_GPIO_BASE + (16 * 3) + 8,
222 GPIO_RIGHT_LED_1 = GPIO_RIGHT_KB_EXPANDER_BASE,
223 GPIO_RIGHT_LED_2,
224 GPIO_RIGHT_LED_3,
225 GPIO_RIGHT_LED_BT,
226 GPIO_WEB_CAMIF_STANDBY,
227 GPIO_COMPASS_RST_N,
228 GPIO_WEB_CAMIF_RESET_N,
229 GPIO_RIGHT_LED_5,
230 GPIO_R_ALTIMETER_RESET_N,
231 /* FLUID S IO expander */
232 GPIO_SOUTH_EXPANDER_BASE,
233 GPIO_MIC2_ANCR_SEL = GPIO_SOUTH_EXPANDER_BASE,
234 GPIO_MIC1_ANCL_SEL,
235 GPIO_HS_MIC4_SEL,
236 GPIO_FML_MIC3_SEL,
237 GPIO_FMR_MIC5_SEL,
238 GPIO_TS_SLEEP,
239 GPIO_HAP_SHIFT_LVL_OE,
240 GPIO_HS_SW_DIR,
241 /* FLUID N IO expander */
242 GPIO_NORTH_EXPANDER_BASE,
243 GPIO_EPM_3_3V_EN = GPIO_NORTH_EXPANDER_BASE,
244 GPIO_EPM_5V_BOOST_EN,
245 GPIO_AUX_CAM_2P7_EN,
246 GPIO_LED_FLASH_EN,
247 GPIO_LED1_GREEN_N,
248 GPIO_LED2_RED_N,
249 GPIO_FRONT_CAM_RESET_N,
250 GPIO_EPM_LVLSFT_EN,
251 GPIO_N_ALTIMETER_RESET_N,
252 /* EPM expander */
253 GPIO_EPM_EXPANDER_BASE,
254 GPIO_PWR_MON_START = GPIO_EPM_EXPANDER_BASE,
255 GPIO_PWR_MON_RESET_N,
256 GPIO_ADC1_PWDN_N,
257 GPIO_ADC2_PWDN_N,
258 GPIO_EPM_EXPANDER_IO4,
259 GPIO_ADC1_MUX_SPI_INT_N_3_3V,
260 GPIO_ADC2_MUX_SPI_INT_N,
261 GPIO_EPM_EXPANDER_IO7,
262 GPIO_PWR_MON_ENABLE,
263 GPIO_EPM_SPI_ADC1_CS_N,
264 GPIO_EPM_SPI_ADC2_CS_N,
265 GPIO_EPM_EXPANDER_IO11,
266 GPIO_EPM_EXPANDER_IO12,
267 GPIO_EPM_EXPANDER_IO13,
268 GPIO_EPM_EXPANDER_IO14,
269 GPIO_EPM_EXPANDER_IO15,
270};
271
272/*
273 * The UI_INTx_N lines are pmic gpio lines which connect i2c
274 * gpio expanders to the pm8058.
275 */
276#define UI_INT1_N 25
277#define UI_INT2_N 34
278#define UI_INT3_N 14
279/*
280FM GPIO is GPIO 18 on PMIC 8058.
281As the index starts from 0 in the PMIC driver, and hence 17
282corresponds to GPIO 18 on PMIC 8058.
283*/
284#define FM_GPIO 17
285
286#ifdef CONFIG_MMC_MSM_SDC2_SUPPORT
287static void (*sdc2_status_notify_cb)(int card_present, void *dev_id);
288static void *sdc2_status_notify_cb_devid;
289#endif
290
291#ifdef CONFIG_MMC_MSM_SDC5_SUPPORT
292static void (*sdc5_status_notify_cb)(int card_present, void *dev_id);
293static void *sdc5_status_notify_cb_devid;
294#endif
295
296static struct msm_spm_platform_data msm_spm_data_v1[] __initdata = {
297 [0] = {
298 .reg_base_addr = MSM_SAW0_BASE,
299
300#ifdef CONFIG_MSM_AVS_HW
301 .reg_init_values[MSM_SPM_REG_SAW_AVS_CTL] = 0x586020FF,
302#endif
303 .reg_init_values[MSM_SPM_REG_SAW_CFG] = 0x0F,
304 .reg_init_values[MSM_SPM_REG_SAW_SPM_CTL] = 0x68,
305 .reg_init_values[MSM_SPM_REG_SAW_SPM_SLP_TMR_DLY] = 0xFFFFFFFF,
306 .reg_init_values[MSM_SPM_REG_SAW_SPM_WAKE_TMR_DLY] = 0xFFFFFFFF,
307
308 .reg_init_values[MSM_SPM_REG_SAW_SLP_CLK_EN] = 0x01,
309 .reg_init_values[MSM_SPM_REG_SAW_SLP_HSFS_PRECLMP_EN] = 0x07,
310 .reg_init_values[MSM_SPM_REG_SAW_SLP_HSFS_POSTCLMP_EN] = 0x00,
311
312 .reg_init_values[MSM_SPM_REG_SAW_SLP_CLMP_EN] = 0x01,
313 .reg_init_values[MSM_SPM_REG_SAW_SLP_RST_EN] = 0x00,
314 .reg_init_values[MSM_SPM_REG_SAW_SPM_MPM_CFG] = 0x00,
315
316 .awake_vlevel = 0x94,
317 .retention_vlevel = 0x81,
318 .collapse_vlevel = 0x20,
319 .retention_mid_vlevel = 0x94,
320 .collapse_mid_vlevel = 0x8C,
321
322 .vctl_timeout_us = 50,
323 },
324
325 [1] = {
326 .reg_base_addr = MSM_SAW1_BASE,
327
328#ifdef CONFIG_MSM_AVS_HW
329 .reg_init_values[MSM_SPM_REG_SAW_AVS_CTL] = 0x586020FF,
330#endif
331 .reg_init_values[MSM_SPM_REG_SAW_CFG] = 0x0F,
332 .reg_init_values[MSM_SPM_REG_SAW_SPM_CTL] = 0x68,
333 .reg_init_values[MSM_SPM_REG_SAW_SPM_SLP_TMR_DLY] = 0xFFFFFFFF,
334 .reg_init_values[MSM_SPM_REG_SAW_SPM_WAKE_TMR_DLY] = 0xFFFFFFFF,
335
336 .reg_init_values[MSM_SPM_REG_SAW_SLP_CLK_EN] = 0x13,
337 .reg_init_values[MSM_SPM_REG_SAW_SLP_HSFS_PRECLMP_EN] = 0x07,
338 .reg_init_values[MSM_SPM_REG_SAW_SLP_HSFS_POSTCLMP_EN] = 0x00,
339
340 .reg_init_values[MSM_SPM_REG_SAW_SLP_CLMP_EN] = 0x01,
341 .reg_init_values[MSM_SPM_REG_SAW_SLP_RST_EN] = 0x00,
342 .reg_init_values[MSM_SPM_REG_SAW_SPM_MPM_CFG] = 0x00,
343
344 .awake_vlevel = 0x94,
345 .retention_vlevel = 0x81,
346 .collapse_vlevel = 0x20,
347 .retention_mid_vlevel = 0x94,
348 .collapse_mid_vlevel = 0x8C,
349
350 .vctl_timeout_us = 50,
351 },
352};
353
354static struct msm_spm_platform_data msm_spm_data[] __initdata = {
355 [0] = {
356 .reg_base_addr = MSM_SAW0_BASE,
357
358#ifdef CONFIG_MSM_AVS_HW
359 .reg_init_values[MSM_SPM_REG_SAW_AVS_CTL] = 0x586020FF,
360#endif
361 .reg_init_values[MSM_SPM_REG_SAW_CFG] = 0x1C,
362 .reg_init_values[MSM_SPM_REG_SAW_SPM_CTL] = 0x68,
363 .reg_init_values[MSM_SPM_REG_SAW_SPM_SLP_TMR_DLY] = 0x0C0CFFFF,
364 .reg_init_values[MSM_SPM_REG_SAW_SPM_WAKE_TMR_DLY] = 0x78780FFF,
365
366 .reg_init_values[MSM_SPM_REG_SAW_SLP_CLK_EN] = 0x01,
367 .reg_init_values[MSM_SPM_REG_SAW_SLP_HSFS_PRECLMP_EN] = 0x07,
368 .reg_init_values[MSM_SPM_REG_SAW_SLP_HSFS_POSTCLMP_EN] = 0x00,
369
370 .reg_init_values[MSM_SPM_REG_SAW_SLP_CLMP_EN] = 0x01,
371 .reg_init_values[MSM_SPM_REG_SAW_SLP_RST_EN] = 0x00,
372 .reg_init_values[MSM_SPM_REG_SAW_SPM_MPM_CFG] = 0x00,
373
374 .awake_vlevel = 0xA0,
375 .retention_vlevel = 0x89,
376 .collapse_vlevel = 0x20,
377 .retention_mid_vlevel = 0x89,
378 .collapse_mid_vlevel = 0x89,
379
380 .vctl_timeout_us = 50,
381 },
382
383 [1] = {
384 .reg_base_addr = MSM_SAW1_BASE,
385
386#ifdef CONFIG_MSM_AVS_HW
387 .reg_init_values[MSM_SPM_REG_SAW_AVS_CTL] = 0x586020FF,
388#endif
389 .reg_init_values[MSM_SPM_REG_SAW_CFG] = 0x1C,
390 .reg_init_values[MSM_SPM_REG_SAW_SPM_CTL] = 0x68,
391 .reg_init_values[MSM_SPM_REG_SAW_SPM_SLP_TMR_DLY] = 0x0C0CFFFF,
392 .reg_init_values[MSM_SPM_REG_SAW_SPM_WAKE_TMR_DLY] = 0x78780FFF,
393
394 .reg_init_values[MSM_SPM_REG_SAW_SLP_CLK_EN] = 0x13,
395 .reg_init_values[MSM_SPM_REG_SAW_SLP_HSFS_PRECLMP_EN] = 0x07,
396 .reg_init_values[MSM_SPM_REG_SAW_SLP_HSFS_POSTCLMP_EN] = 0x00,
397
398 .reg_init_values[MSM_SPM_REG_SAW_SLP_CLMP_EN] = 0x01,
399 .reg_init_values[MSM_SPM_REG_SAW_SLP_RST_EN] = 0x00,
400 .reg_init_values[MSM_SPM_REG_SAW_SPM_MPM_CFG] = 0x00,
401
402 .awake_vlevel = 0xA0,
403 .retention_vlevel = 0x89,
404 .collapse_vlevel = 0x20,
405 .retention_mid_vlevel = 0x89,
406 .collapse_mid_vlevel = 0x89,
407
408 .vctl_timeout_us = 50,
409 },
410};
411
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700412/*
413 * Consumer specific regulator names:
414 * regulator name consumer dev_name
415 */
416static struct regulator_consumer_supply vreg_consumers_8901_S0[] = {
417 REGULATOR_SUPPLY("8901_s0", NULL),
418};
419static struct regulator_consumer_supply vreg_consumers_8901_S1[] = {
420 REGULATOR_SUPPLY("8901_s1", NULL),
421};
422
423static struct regulator_init_data saw_s0_init_data = {
424 .constraints = {
425 .name = "8901_s0",
426 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
Tianyi Gou7c81dfa2011-07-27 12:15:24 -0700427 .min_uV = 800000,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700428 .max_uV = 1250000,
429 },
430 .consumer_supplies = vreg_consumers_8901_S0,
431 .num_consumer_supplies = ARRAY_SIZE(vreg_consumers_8901_S0),
432};
433
434static struct regulator_init_data saw_s1_init_data = {
435 .constraints = {
436 .name = "8901_s1",
437 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
Tianyi Gou7c81dfa2011-07-27 12:15:24 -0700438 .min_uV = 800000,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700439 .max_uV = 1250000,
440 },
441 .consumer_supplies = vreg_consumers_8901_S1,
442 .num_consumer_supplies = ARRAY_SIZE(vreg_consumers_8901_S1),
443};
444
445static struct platform_device msm_device_saw_s0 = {
446 .name = "saw-regulator",
447 .id = 0,
448 .dev = {
449 .platform_data = &saw_s0_init_data,
450 },
451};
452
453static struct platform_device msm_device_saw_s1 = {
454 .name = "saw-regulator",
455 .id = 1,
456 .dev = {
457 .platform_data = &saw_s1_init_data,
458 },
459};
460
461/*
462 * The smc91x configuration varies depending on platform.
463 * The resources data structure is filled in at runtime.
464 */
465static struct resource smc91x_resources[] = {
466 [0] = {
467 .flags = IORESOURCE_MEM,
468 },
469 [1] = {
470 .flags = IORESOURCE_IRQ,
471 },
472};
473
474static struct platform_device smc91x_device = {
475 .name = "smc91x",
476 .id = 0,
477 .num_resources = ARRAY_SIZE(smc91x_resources),
478 .resource = smc91x_resources,
479};
480
481static struct resource smsc911x_resources[] = {
482 [0] = {
483 .flags = IORESOURCE_MEM,
484 .start = 0x1b800000,
485 .end = 0x1b8000ff
486 },
487 [1] = {
488 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
489 },
490};
491
492static struct smsc911x_platform_config smsc911x_config = {
493 .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
494 .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL,
495 .flags = SMSC911X_USE_16BIT,
496 .has_reset_gpio = 1,
497 .reset_gpio = GPIO_ETHERNET_RESET_N
498};
499
500static struct platform_device smsc911x_device = {
501 .name = "smsc911x",
502 .id = 0,
503 .num_resources = ARRAY_SIZE(smsc911x_resources),
504 .resource = smsc911x_resources,
505 .dev = {
506 .platform_data = &smsc911x_config
507 }
508};
509
510#if defined(CONFIG_CRYPTO_DEV_QCRYPTO) || \
511 defined(CONFIG_CRYPTO_DEV_QCRYPTO_MODULE) || \
512 defined(CONFIG_CRYPTO_DEV_QCEDEV) || \
513 defined(CONFIG_CRYPTO_DEV_QCEDEV_MODULE)
514
515#define QCE_SIZE 0x10000
516#define QCE_0_BASE 0x18500000
517
518#define QCE_HW_KEY_SUPPORT 0
519#define QCE_SHA_HMAC_SUPPORT 0
520#define QCE_SHARE_CE_RESOURCE 2
521#define QCE_CE_SHARED 1
522
523static struct resource qcrypto_resources[] = {
524 [0] = {
525 .start = QCE_0_BASE,
526 .end = QCE_0_BASE + QCE_SIZE - 1,
527 .flags = IORESOURCE_MEM,
528 },
529 [1] = {
530 .name = "crypto_channels",
531 .start = DMOV_CE_IN_CHAN,
532 .end = DMOV_CE_OUT_CHAN,
533 .flags = IORESOURCE_DMA,
534 },
535 [2] = {
536 .name = "crypto_crci_in",
537 .start = DMOV_CE_IN_CRCI,
538 .end = DMOV_CE_IN_CRCI,
539 .flags = IORESOURCE_DMA,
540 },
541 [3] = {
542 .name = "crypto_crci_out",
543 .start = DMOV_CE_OUT_CRCI,
544 .end = DMOV_CE_OUT_CRCI,
545 .flags = IORESOURCE_DMA,
546 },
547 [4] = {
548 .name = "crypto_crci_hash",
549 .start = DMOV_CE_HASH_CRCI,
550 .end = DMOV_CE_HASH_CRCI,
551 .flags = IORESOURCE_DMA,
552 },
553};
554
555static struct resource qcedev_resources[] = {
556 [0] = {
557 .start = QCE_0_BASE,
558 .end = QCE_0_BASE + QCE_SIZE - 1,
559 .flags = IORESOURCE_MEM,
560 },
561 [1] = {
562 .name = "crypto_channels",
563 .start = DMOV_CE_IN_CHAN,
564 .end = DMOV_CE_OUT_CHAN,
565 .flags = IORESOURCE_DMA,
566 },
567 [2] = {
568 .name = "crypto_crci_in",
569 .start = DMOV_CE_IN_CRCI,
570 .end = DMOV_CE_IN_CRCI,
571 .flags = IORESOURCE_DMA,
572 },
573 [3] = {
574 .name = "crypto_crci_out",
575 .start = DMOV_CE_OUT_CRCI,
576 .end = DMOV_CE_OUT_CRCI,
577 .flags = IORESOURCE_DMA,
578 },
579 [4] = {
580 .name = "crypto_crci_hash",
581 .start = DMOV_CE_HASH_CRCI,
582 .end = DMOV_CE_HASH_CRCI,
583 .flags = IORESOURCE_DMA,
584 },
585};
586
587#endif
588
589#if defined(CONFIG_CRYPTO_DEV_QCRYPTO) || \
590 defined(CONFIG_CRYPTO_DEV_QCRYPTO_MODULE)
591
592static struct msm_ce_hw_support qcrypto_ce_hw_suppport = {
593 .ce_shared = QCE_CE_SHARED,
594 .shared_ce_resource = QCE_SHARE_CE_RESOURCE,
595 .hw_key_support = QCE_HW_KEY_SUPPORT,
596 .sha_hmac = QCE_SHA_HMAC_SUPPORT,
597};
598
599static struct platform_device qcrypto_device = {
600 .name = "qcrypto",
601 .id = 0,
602 .num_resources = ARRAY_SIZE(qcrypto_resources),
603 .resource = qcrypto_resources,
604 .dev = {
605 .coherent_dma_mask = DMA_BIT_MASK(32),
606 .platform_data = &qcrypto_ce_hw_suppport,
607 },
608};
609#endif
610
611#if defined(CONFIG_CRYPTO_DEV_QCEDEV) || \
612 defined(CONFIG_CRYPTO_DEV_QCEDEV_MODULE)
613
614static struct msm_ce_hw_support qcedev_ce_hw_suppport = {
615 .ce_shared = QCE_CE_SHARED,
616 .shared_ce_resource = QCE_SHARE_CE_RESOURCE,
617 .hw_key_support = QCE_HW_KEY_SUPPORT,
618 .sha_hmac = QCE_SHA_HMAC_SUPPORT,
619};
620
621static struct platform_device qcedev_device = {
622 .name = "qce",
623 .id = 0,
624 .num_resources = ARRAY_SIZE(qcedev_resources),
625 .resource = qcedev_resources,
626 .dev = {
627 .coherent_dma_mask = DMA_BIT_MASK(32),
628 .platform_data = &qcedev_ce_hw_suppport,
629 },
630};
631#endif
632
633#if defined(CONFIG_HAPTIC_ISA1200) || \
634 defined(CONFIG_HAPTIC_ISA1200_MODULE)
635
636static const char *vregs_isa1200_name[] = {
637 "8058_s3",
638 "8901_l4",
639};
640
641static const int vregs_isa1200_val[] = {
642 1800000,/* uV */
643 2600000,
644};
645static struct regulator *vregs_isa1200[ARRAY_SIZE(vregs_isa1200_name)];
646static struct msm_xo_voter *xo_handle_a1;
647
648static int isa1200_power(int vreg_on)
Steve Mucklea55df6e2010-01-07 12:43:24 -0800649{
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700650 int i, rc = 0;
651
652 for (i = 0; i < ARRAY_SIZE(vregs_isa1200_name); i++) {
653 rc = vreg_on ? regulator_enable(vregs_isa1200[i]) :
654 regulator_disable(vregs_isa1200[i]);
655 if (rc < 0) {
656 pr_err("%s: vreg %s %s failed (%d)\n",
657 __func__, vregs_isa1200_name[i],
658 vreg_on ? "enable" : "disable", rc);
659 goto vreg_fail;
660 }
661 }
662
663 rc = vreg_on ? msm_xo_mode_vote(xo_handle_a1, MSM_XO_MODE_ON) :
664 msm_xo_mode_vote(xo_handle_a1, MSM_XO_MODE_OFF);
665 if (rc < 0) {
666 pr_err("%s: failed to %svote for TCXO A1 buffer%d\n",
667 __func__, vreg_on ? "" : "de-", rc);
668 goto vreg_fail;
669 }
670 return 0;
671
672vreg_fail:
673 while (i--)
674 !vreg_on ? regulator_enable(vregs_isa1200[i]) :
675 regulator_disable(vregs_isa1200[i]);
676 return rc;
Steve Mucklea55df6e2010-01-07 12:43:24 -0800677}
678
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700679static int isa1200_dev_setup(bool enable)
Steve Mucklea55df6e2010-01-07 12:43:24 -0800680{
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700681 int i, rc;
Steve Muckle9161d302010-02-11 11:50:40 -0800682
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700683 if (enable == true) {
684 for (i = 0; i < ARRAY_SIZE(vregs_isa1200_name); i++) {
685 vregs_isa1200[i] = regulator_get(NULL,
686 vregs_isa1200_name[i]);
687 if (IS_ERR(vregs_isa1200[i])) {
688 pr_err("%s: regulator get of %s failed (%ld)\n",
689 __func__, vregs_isa1200_name[i],
690 PTR_ERR(vregs_isa1200[i]));
691 rc = PTR_ERR(vregs_isa1200[i]);
692 goto vreg_get_fail;
693 }
694 rc = regulator_set_voltage(vregs_isa1200[i],
695 vregs_isa1200_val[i], vregs_isa1200_val[i]);
696 if (rc) {
697 pr_err("%s: regulator_set_voltage(%s) failed\n",
698 __func__, vregs_isa1200_name[i]);
699 goto vreg_get_fail;
700 }
701 }
Steve Muckle9161d302010-02-11 11:50:40 -0800702
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700703 rc = gpio_request(GPIO_HAP_SHIFT_LVL_OE, "haptics_shft_lvl_oe");
704 if (rc) {
705 pr_err("%s: unable to request gpio %d (%d)\n",
706 __func__, GPIO_HAP_SHIFT_LVL_OE, rc);
707 goto vreg_get_fail;
708 }
Steve Muckle9161d302010-02-11 11:50:40 -0800709
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700710 rc = gpio_direction_output(GPIO_HAP_SHIFT_LVL_OE, 1);
711 if (rc) {
712 pr_err("%s: Unable to set direction\n", __func__);;
713 goto free_gpio;
714 }
715
716 xo_handle_a1 = msm_xo_get(MSM_XO_TCXO_A1, "isa1200");
717 if (IS_ERR(xo_handle_a1)) {
718 rc = PTR_ERR(xo_handle_a1);
719 pr_err("%s: failed to get the handle for A1(%d)\n",
720 __func__, rc);
721 goto gpio_set_dir;
722 }
723 } else {
724 gpio_set_value(GPIO_HAP_SHIFT_LVL_OE, 0);
725 gpio_free(GPIO_HAP_SHIFT_LVL_OE);
726
727 for (i = 0; i < ARRAY_SIZE(vregs_isa1200_name); i++)
728 regulator_put(vregs_isa1200[i]);
729
730 msm_xo_put(xo_handle_a1);
731 }
732
733 return 0;
734gpio_set_dir:
735 gpio_set_value(GPIO_HAP_SHIFT_LVL_OE, 0);
736free_gpio:
737 gpio_free(GPIO_HAP_SHIFT_LVL_OE);
738vreg_get_fail:
739 while (i)
740 regulator_put(vregs_isa1200[--i]);
741 return rc;
742}
743
744#define PMIC_GPIO_HAP_ENABLE 18 /* PMIC GPIO Number 19 */
745static struct isa1200_platform_data isa1200_1_pdata = {
746 .name = "vibrator",
747 .power_on = isa1200_power,
748 .dev_setup = isa1200_dev_setup,
749 /*gpio to enable haptic*/
750 .hap_en_gpio = PM8058_GPIO_PM_TO_SYS(PMIC_GPIO_HAP_ENABLE),
751 .max_timeout = 15000,
752 .mode_ctrl = PWM_GEN_MODE,
753 .pwm_fd = {
754 .pwm_div = 256,
755 },
756 .is_erm = false,
757 .smart_en = true,
758 .ext_clk_en = true,
759 .chip_en = 1,
760};
761
762static struct i2c_board_info msm_isa1200_board_info[] = {
763 {
764 I2C_BOARD_INFO("isa1200_1", 0x90>>1),
765 .platform_data = &isa1200_1_pdata,
766 },
767};
768#endif
769
770#if defined(CONFIG_BATTERY_BQ27520) || \
771 defined(CONFIG_BATTERY_BQ27520_MODULE)
772static struct bq27520_platform_data bq27520_pdata = {
773 .name = "fuel-gauge",
774 .vreg_name = "8058_s3",
775 .vreg_value = 1800000,
776 .soc_int = GPIO_BATT_GAUGE_INT_N,
777 .bi_tout = GPIO_CAP_GAUGE_BI_TOUT,
778 .chip_en = GPIO_BATT_GAUGE_EN,
779 .enable_dlog = 0, /* if enable coulomb counter logger */
780};
781
782static struct i2c_board_info msm_bq27520_board_info[] = {
783 {
784 I2C_BOARD_INFO("bq27520", 0xaa>>1),
785 .platform_data = &bq27520_pdata,
786 },
787};
788#endif
789
790static struct msm_pm_platform_data msm_pm_data[MSM_PM_SLEEP_MODE_NR * 2] = {
791 [MSM_PM_MODE(0, MSM_PM_SLEEP_MODE_POWER_COLLAPSE)] = {
792 .idle_supported = 1,
793 .suspend_supported = 1,
794 .idle_enabled = 0,
795 .suspend_enabled = 0,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700796 },
797
798 [MSM_PM_MODE(0, MSM_PM_SLEEP_MODE_POWER_COLLAPSE_STANDALONE)] = {
799 .idle_supported = 1,
800 .suspend_supported = 1,
801 .idle_enabled = 0,
802 .suspend_enabled = 0,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700803 },
804
805 [MSM_PM_MODE(0, MSM_PM_SLEEP_MODE_WAIT_FOR_INTERRUPT)] = {
806 .idle_supported = 1,
807 .suspend_supported = 1,
808 .idle_enabled = 1,
809 .suspend_enabled = 1,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700810 },
811
812 [MSM_PM_MODE(1, MSM_PM_SLEEP_MODE_POWER_COLLAPSE)] = {
813 .idle_supported = 1,
814 .suspend_supported = 1,
815 .idle_enabled = 0,
816 .suspend_enabled = 0,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700817 },
818
819 [MSM_PM_MODE(1, MSM_PM_SLEEP_MODE_POWER_COLLAPSE_STANDALONE)] = {
820 .idle_supported = 1,
821 .suspend_supported = 1,
822 .idle_enabled = 0,
823 .suspend_enabled = 0,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700824 },
825
826 [MSM_PM_MODE(1, MSM_PM_SLEEP_MODE_WAIT_FOR_INTERRUPT)] = {
827 .idle_supported = 1,
828 .suspend_supported = 1,
829 .idle_enabled = 1,
830 .suspend_enabled = 1,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700831 },
832};
833
834static struct msm_cpuidle_state msm_cstates[] __initdata = {
835 {0, 0, "C0", "WFI",
836 MSM_PM_SLEEP_MODE_WAIT_FOR_INTERRUPT},
837
838 {0, 1, "C1", "STANDALONE_POWER_COLLAPSE",
839 MSM_PM_SLEEP_MODE_POWER_COLLAPSE_STANDALONE},
840
841 {0, 2, "C2", "POWER_COLLAPSE",
842 MSM_PM_SLEEP_MODE_POWER_COLLAPSE},
843
844 {1, 0, "C0", "WFI",
845 MSM_PM_SLEEP_MODE_WAIT_FOR_INTERRUPT},
846
847 {1, 1, "C1", "STANDALONE_POWER_COLLAPSE",
848 MSM_PM_SLEEP_MODE_POWER_COLLAPSE_STANDALONE},
849};
850
851static struct msm_rpmrs_level msm_rpmrs_levels[] __initdata = {
852 {
853 MSM_PM_SLEEP_MODE_WAIT_FOR_INTERRUPT,
854 MSM_RPMRS_LIMITS(ON, ACTIVE, MAX, ACTIVE),
855 true,
856 1, 8000, 100000, 1,
857 },
858
859 {
860 MSM_PM_SLEEP_MODE_POWER_COLLAPSE_STANDALONE,
861 MSM_RPMRS_LIMITS(ON, ACTIVE, MAX, ACTIVE),
862 true,
863 1500, 5000, 60100000, 3000,
864 },
865
866 {
867 MSM_PM_SLEEP_MODE_POWER_COLLAPSE,
868 MSM_RPMRS_LIMITS(ON, ACTIVE, MAX, ACTIVE),
869 false,
870 1800, 5000, 60350000, 3500,
871 },
872 {
873 MSM_PM_SLEEP_MODE_POWER_COLLAPSE,
874 MSM_RPMRS_LIMITS(OFF, ACTIVE, MAX, ACTIVE),
875 false,
876 3800, 4500, 65350000, 5500,
877 },
878
879 {
880 MSM_PM_SLEEP_MODE_POWER_COLLAPSE,
881 MSM_RPMRS_LIMITS(ON, HSFS_OPEN, MAX, ACTIVE),
882 false,
883 2800, 2500, 66850000, 4800,
884 },
885
886 {
887 MSM_PM_SLEEP_MODE_POWER_COLLAPSE,
888 MSM_RPMRS_LIMITS(OFF, HSFS_OPEN, MAX, ACTIVE),
889 false,
890 4800, 2000, 71850000, 6800,
891 },
892
893 {
894 MSM_PM_SLEEP_MODE_POWER_COLLAPSE,
895 MSM_RPMRS_LIMITS(OFF, HSFS_OPEN, ACTIVE, RET_HIGH),
896 false,
897 6800, 500, 75850000, 8800,
898 },
899
900 {
901 MSM_PM_SLEEP_MODE_POWER_COLLAPSE,
902 MSM_RPMRS_LIMITS(OFF, HSFS_OPEN, RET_HIGH, RET_LOW),
903 false,
904 7800, 0, 76350000, 9800,
905 },
906};
907
908#if defined(CONFIG_USB_PEHCI_HCD) || defined(CONFIG_USB_PEHCI_HCD_MODULE)
909
910#define ISP1763_INT_GPIO 117
911#define ISP1763_RST_GPIO 152
912static struct resource isp1763_resources[] = {
913 [0] = {
914 .flags = IORESOURCE_MEM,
915 .start = 0x1D000000,
916 .end = 0x1D005FFF, /* 24KB */
917 },
918 [1] = {
919 .flags = IORESOURCE_IRQ,
920 },
921};
922static void __init msm8x60_cfg_isp1763(void)
923{
924 isp1763_resources[1].start = gpio_to_irq(ISP1763_INT_GPIO);
925 isp1763_resources[1].end = gpio_to_irq(ISP1763_INT_GPIO);
926}
927
928static int isp1763_setup_gpio(int enable)
929{
930 int status = 0;
931
932 if (enable) {
933 status = gpio_request(ISP1763_INT_GPIO, "isp1763_usb");
934 if (status) {
935 pr_err("%s:Failed to request GPIO %d\n",
936 __func__, ISP1763_INT_GPIO);
937 return status;
938 }
939 status = gpio_direction_input(ISP1763_INT_GPIO);
940 if (status) {
941 pr_err("%s:Failed to configure GPIO %d\n",
942 __func__, ISP1763_INT_GPIO);
943 goto gpio_free_int;
944 }
945 status = gpio_request(ISP1763_RST_GPIO, "isp1763_usb");
946 if (status) {
947 pr_err("%s:Failed to request GPIO %d\n",
948 __func__, ISP1763_RST_GPIO);
949 goto gpio_free_int;
950 }
951 status = gpio_direction_output(ISP1763_RST_GPIO, 1);
952 if (status) {
953 pr_err("%s:Failed to configure GPIO %d\n",
954 __func__, ISP1763_RST_GPIO);
955 goto gpio_free_rst;
956 }
957 pr_debug("\nISP GPIO configuration done\n");
958 return status;
959 }
960
961gpio_free_rst:
962 gpio_free(ISP1763_RST_GPIO);
963gpio_free_int:
964 gpio_free(ISP1763_INT_GPIO);
965
966 return status;
967}
968static struct isp1763_platform_data isp1763_pdata = {
969 .reset_gpio = ISP1763_RST_GPIO,
970 .setup_gpio = isp1763_setup_gpio
971};
972
973static struct platform_device isp1763_device = {
974 .name = "isp1763_usb",
975 .num_resources = ARRAY_SIZE(isp1763_resources),
976 .resource = isp1763_resources,
977 .dev = {
978 .platform_data = &isp1763_pdata
979 }
980};
981#endif
982
983#if defined(CONFIG_USB_GADGET_MSM_72K) || defined(CONFIG_USB_EHCI_MSM_72K)
Anji jonnalaeb9e60d2011-10-05 12:19:46 +0530984static struct msm_otg_platform_data msm_otg_pdata;
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700985static struct regulator *ldo6_3p3;
986static struct regulator *ldo7_1p8;
987static struct regulator *vdd_cx;
988#define PMICID_INT PM8058_GPIO_IRQ(PM8058_IRQ_BASE, 36)
989notify_vbus_state notify_vbus_state_func_ptr;
990static int usb_phy_susp_dig_vol = 750000;
991static int pmic_id_notif_supported;
992
993#ifdef CONFIG_USB_EHCI_MSM_72K
994#define USB_PMIC_ID_DET_DELAY msecs_to_jiffies(100)
995struct delayed_work pmic_id_det;
996
997static int __init usb_id_pin_rework_setup(char *support)
998{
999 if (strncmp(support, "true", 4) == 0)
1000 pmic_id_notif_supported = 1;
1001
1002 return 1;
1003}
1004__setup("usb_id_pin_rework=", usb_id_pin_rework_setup);
1005
1006static void pmic_id_detect(struct work_struct *w)
1007{
1008 int val = gpio_get_value_cansleep(PM8058_GPIO_PM_TO_SYS(36));
1009 pr_debug("%s(): gpio_read_value = %d\n", __func__, val);
1010
1011 if (notify_vbus_state_func_ptr)
1012 (*notify_vbus_state_func_ptr) (val);
1013}
1014
1015static irqreturn_t pmic_id_on_irq(int irq, void *data)
1016{
1017 /*
1018 * Spurious interrupts are observed on pmic gpio line
1019 * even though there is no state change on USB ID. Schedule the
1020 * work to to allow debounce on gpio
Steve Muckle9161d302010-02-11 11:50:40 -08001021 */
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001022 schedule_delayed_work(&pmic_id_det, USB_PMIC_ID_DET_DELAY);
Steve Muckle9161d302010-02-11 11:50:40 -08001023
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001024 return IRQ_HANDLED;
1025}
1026
1027static int msm_hsusb_pmic_id_notif_init(void (*callback)(int online), int init)
1028{
1029 unsigned ret = -ENODEV;
1030
1031 if (!callback)
1032 return -EINVAL;
1033
1034 if (machine_is_msm8x60_fluid())
1035 return -ENOTSUPP;
1036
1037 if (SOCINFO_VERSION_MAJOR(socinfo_get_version()) != 2) {
1038 pr_debug("%s: USB_ID pin is not routed to PMIC"
1039 "on V1 surf/ffa\n", __func__);
1040 return -ENOTSUPP;
1041 }
1042
1043 if ((machine_is_msm8x60_fusion() || machine_is_msm8x60_fusn_ffa()) &&
1044 !pmic_id_notif_supported) {
1045 pr_debug("%s: USB_ID is not routed to PMIC"
1046 "on V2 ffa\n", __func__);
1047 return -ENOTSUPP;
1048 }
1049
1050 usb_phy_susp_dig_vol = 500000;
1051
1052 if (init) {
1053 notify_vbus_state_func_ptr = callback;
1054 ret = pm8901_mpp_config_digital_out(1,
1055 PM8901_MPP_DIG_LEVEL_L5, 1);
1056 if (ret) {
1057 pr_err("%s: MPP2 configuration failed\n", __func__);
1058 return -ENODEV;
1059 }
1060 INIT_DELAYED_WORK(&pmic_id_det, pmic_id_detect);
1061 ret = request_threaded_irq(PMICID_INT, NULL, pmic_id_on_irq,
1062 (IRQF_TRIGGER_RISING|IRQF_TRIGGER_FALLING),
1063 "msm_otg_id", NULL);
1064 if (ret) {
1065 pm8901_mpp_config_digital_out(1,
1066 PM8901_MPP_DIG_LEVEL_L5, 0);
1067 pr_err("%s:pmic_usb_id interrupt registration failed",
1068 __func__);
1069 return ret;
1070 }
1071 /* Notify the initial Id status */
1072 pmic_id_detect(&pmic_id_det.work);
Anji jonnalaeb9e60d2011-10-05 12:19:46 +05301073 msm_otg_pdata.pmic_id_irq = PMICID_INT;
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001074 } else {
1075 free_irq(PMICID_INT, 0);
Anji jonnalaeb9e60d2011-10-05 12:19:46 +05301076 msm_otg_pdata.pmic_id_irq = 0;
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001077 cancel_delayed_work_sync(&pmic_id_det);
1078 notify_vbus_state_func_ptr = NULL;
1079 ret = pm8901_mpp_config_digital_out(1,
1080 PM8901_MPP_DIG_LEVEL_L5, 0);
1081 if (ret) {
1082 pr_err("%s:MPP2 configuration failed\n", __func__);
1083 return -ENODEV;
1084 }
1085 }
1086 return 0;
1087}
1088#endif
1089
1090#define USB_PHY_OPERATIONAL_MIN_VDD_DIG_VOL 1000000
1091#define USB_PHY_MAX_VDD_DIG_VOL 1320000
1092static int msm_hsusb_init_vddcx(int init)
1093{
1094 int ret = 0;
1095
1096 if (init) {
1097 vdd_cx = regulator_get(NULL, "8058_s1");
1098 if (IS_ERR(vdd_cx)) {
1099 return PTR_ERR(vdd_cx);
1100 }
1101
1102 ret = regulator_set_voltage(vdd_cx,
1103 USB_PHY_OPERATIONAL_MIN_VDD_DIG_VOL,
1104 USB_PHY_MAX_VDD_DIG_VOL);
1105 if (ret) {
1106 pr_err("%s: unable to set the voltage for regulator"
1107 "vdd_cx\n", __func__);
1108 regulator_put(vdd_cx);
1109 return ret;
1110 }
1111
1112 ret = regulator_enable(vdd_cx);
1113 if (ret) {
1114 pr_err("%s: unable to enable regulator"
1115 "vdd_cx\n", __func__);
1116 regulator_put(vdd_cx);
1117 }
1118 } else {
1119 ret = regulator_disable(vdd_cx);
1120 if (ret) {
1121 pr_err("%s: Unable to disable the regulator:"
1122 "vdd_cx\n", __func__);
1123 return ret;
1124 }
1125
1126 regulator_put(vdd_cx);
1127 }
1128
1129 return ret;
1130}
1131
1132static int msm_hsusb_config_vddcx(int high)
1133{
1134 int max_vol = USB_PHY_MAX_VDD_DIG_VOL;
1135 int min_vol;
1136 int ret;
1137
1138 if (high)
1139 min_vol = USB_PHY_OPERATIONAL_MIN_VDD_DIG_VOL;
1140 else
1141 min_vol = usb_phy_susp_dig_vol;
1142
1143 ret = regulator_set_voltage(vdd_cx, min_vol, max_vol);
1144 if (ret) {
1145 pr_err("%s: unable to set the voltage for regulator"
1146 "vdd_cx\n", __func__);
1147 return ret;
1148 }
1149
1150 pr_debug("%s: min_vol:%d max_vol:%d\n", __func__, min_vol, max_vol);
1151
1152 return ret;
1153}
1154
1155#define USB_PHY_3P3_VOL_MIN 3050000 /* uV */
1156#define USB_PHY_3P3_VOL_MAX 3050000 /* uV */
1157#define USB_PHY_3P3_HPM_LOAD 50000 /* uA */
1158#define USB_PHY_3P3_LPM_LOAD 4000 /* uA */
1159
1160#define USB_PHY_1P8_VOL_MIN 1800000 /* uV */
1161#define USB_PHY_1P8_VOL_MAX 1800000 /* uV */
1162#define USB_PHY_1P8_HPM_LOAD 50000 /* uA */
1163#define USB_PHY_1P8_LPM_LOAD 4000 /* uA */
1164static int msm_hsusb_ldo_init(int init)
1165{
1166 int rc = 0;
1167
1168 if (init) {
1169 ldo6_3p3 = regulator_get(NULL, "8058_l6");
1170 if (IS_ERR(ldo6_3p3))
1171 return PTR_ERR(ldo6_3p3);
1172
1173 ldo7_1p8 = regulator_get(NULL, "8058_l7");
1174 if (IS_ERR(ldo7_1p8)) {
1175 rc = PTR_ERR(ldo7_1p8);
1176 goto put_3p3;
1177 }
1178
1179 rc = regulator_set_voltage(ldo6_3p3, USB_PHY_3P3_VOL_MIN,
1180 USB_PHY_3P3_VOL_MAX);
1181 if (rc) {
1182 pr_err("%s: Unable to set voltage level for"
1183 "ldo6_3p3 regulator\n", __func__);
1184 goto put_1p8;
1185 }
1186 rc = regulator_enable(ldo6_3p3);
1187 if (rc) {
1188 pr_err("%s: Unable to enable the regulator:"
1189 "ldo6_3p3\n", __func__);
1190 goto put_1p8;
1191 }
1192 rc = regulator_set_voltage(ldo7_1p8, USB_PHY_1P8_VOL_MIN,
1193 USB_PHY_1P8_VOL_MAX);
1194 if (rc) {
1195 pr_err("%s: Unable to set voltage level for"
1196 "ldo7_1p8 regulator\n", __func__);
1197 goto disable_3p3;
1198 }
1199 rc = regulator_enable(ldo7_1p8);
1200 if (rc) {
1201 pr_err("%s: Unable to enable the regulator:"
1202 "ldo7_1p8\n", __func__);
1203 goto disable_3p3;
1204 }
1205
1206 return 0;
1207 }
1208
1209 regulator_disable(ldo7_1p8);
1210disable_3p3:
1211 regulator_disable(ldo6_3p3);
1212put_1p8:
1213 regulator_put(ldo7_1p8);
1214put_3p3:
1215 regulator_put(ldo6_3p3);
1216 return rc;
1217}
1218
1219static int msm_hsusb_ldo_enable(int on)
1220{
1221 int ret = 0;
1222
1223 if (!ldo7_1p8 || IS_ERR(ldo7_1p8)) {
1224 pr_err("%s: ldo7_1p8 is not initialized\n", __func__);
1225 return -ENODEV;
1226 }
1227
1228 if (!ldo6_3p3 || IS_ERR(ldo6_3p3)) {
1229 pr_err("%s: ldo6_3p3 is not initialized\n", __func__);
1230 return -ENODEV;
1231 }
1232
1233 if (on) {
1234 ret = regulator_set_optimum_mode(ldo7_1p8,
1235 USB_PHY_1P8_HPM_LOAD);
1236 if (ret < 0) {
1237 pr_err("%s: Unable to set HPM of the regulator:"
1238 "ldo7_1p8\n", __func__);
1239 return ret;
1240 }
1241 ret = regulator_set_optimum_mode(ldo6_3p3,
1242 USB_PHY_3P3_HPM_LOAD);
1243 if (ret < 0) {
1244 pr_err("%s: Unable to set HPM of the regulator:"
1245 "ldo6_3p3\n", __func__);
1246 regulator_set_optimum_mode(ldo7_1p8,
1247 USB_PHY_1P8_LPM_LOAD);
1248 return ret;
1249 }
1250 } else {
1251 ret = regulator_set_optimum_mode(ldo7_1p8,
1252 USB_PHY_1P8_LPM_LOAD);
1253 if (ret < 0)
1254 pr_err("%s: Unable to set LPM of the regulator:"
1255 "ldo7_1p8\n", __func__);
1256 ret = regulator_set_optimum_mode(ldo6_3p3,
1257 USB_PHY_3P3_LPM_LOAD);
1258 if (ret < 0)
1259 pr_err("%s: Unable to set LPM of the regulator:"
1260 "ldo6_3p3\n", __func__);
1261 }
1262
1263 pr_debug("reg (%s)\n", on ? "HPM" : "LPM");
1264 return ret < 0 ? ret : 0;
1265 }
1266#endif
1267#ifdef CONFIG_USB_EHCI_MSM_72K
1268#if defined(CONFIG_SMB137B_CHARGER) || defined(CONFIG_SMB137B_CHARGER_MODULE)
1269static void msm_hsusb_smb137b_vbus_power(unsigned phy_info, int on)
1270{
1271 static int vbus_is_on;
1272
1273 /* If VBUS is already on (or off), do nothing. */
1274 if (on == vbus_is_on)
1275 return;
1276 smb137b_otg_power(on);
1277 vbus_is_on = on;
1278}
1279#endif
1280static void msm_hsusb_vbus_power(unsigned phy_info, int on)
1281{
1282 static struct regulator *votg_5v_switch;
1283 static struct regulator *ext_5v_reg;
1284 static int vbus_is_on;
1285
1286 /* If VBUS is already on (or off), do nothing. */
1287 if (on == vbus_is_on)
1288 return;
1289
1290 if (!votg_5v_switch) {
1291 votg_5v_switch = regulator_get(NULL, "8901_usb_otg");
1292 if (IS_ERR(votg_5v_switch)) {
1293 pr_err("%s: unable to get votg_5v_switch\n", __func__);
1294 return;
1295 }
1296 }
1297 if (!ext_5v_reg) {
1298 ext_5v_reg = regulator_get(NULL, "8901_mpp0");
1299 if (IS_ERR(ext_5v_reg)) {
1300 pr_err("%s: unable to get ext_5v_reg\n", __func__);
1301 return;
1302 }
1303 }
1304 if (on) {
1305 if (regulator_enable(ext_5v_reg)) {
1306 pr_err("%s: Unable to enable the regulator:"
1307 " ext_5v_reg\n", __func__);
1308 return;
1309 }
1310 if (regulator_enable(votg_5v_switch)) {
1311 pr_err("%s: Unable to enable the regulator:"
1312 " votg_5v_switch\n", __func__);
1313 return;
1314 }
1315 } else {
1316 if (regulator_disable(votg_5v_switch))
1317 pr_err("%s: Unable to enable the regulator:"
1318 " votg_5v_switch\n", __func__);
1319 if (regulator_disable(ext_5v_reg))
1320 pr_err("%s: Unable to enable the regulator:"
1321 " ext_5v_reg\n", __func__);
1322 }
1323
1324 vbus_is_on = on;
1325}
1326
1327static struct msm_usb_host_platform_data msm_usb_host_pdata = {
1328 .phy_info = (USB_PHY_INTEGRATED | USB_PHY_MODEL_45NM),
1329 .power_budget = 390,
1330};
1331#endif
1332
1333#ifdef CONFIG_BATTERY_MSM8X60
1334static int msm_hsusb_pmic_vbus_notif_init(void (*callback)(int online),
1335 int init)
1336{
1337 int ret = -ENOTSUPP;
1338
1339#if defined(CONFIG_SMB137B_CHARGER) || defined(CONFIG_SMB137B_CHARGER_MODULE)
1340 if (machine_is_msm8x60_fluid()) {
1341 if (init)
1342 msm_charger_register_vbus_sn(callback);
1343 else
1344 msm_charger_unregister_vbus_sn(callback);
1345 return 0;
1346 }
1347#endif
1348 /* ID and VBUS lines are connected to pmic on 8660.V2.SURF,
1349 * hence, irrespective of either peripheral only mode or
1350 * OTG (host and peripheral) modes, can depend on pmic for
1351 * vbus notifications
Steve Muckle9161d302010-02-11 11:50:40 -08001352 */
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001353 if ((SOCINFO_VERSION_MAJOR(socinfo_get_version()) == 2)
1354 && (machine_is_msm8x60_surf() ||
1355 pmic_id_notif_supported)) {
1356 if (init)
1357 ret = msm_charger_register_vbus_sn(callback);
1358 else {
1359 msm_charger_unregister_vbus_sn(callback);
1360 ret = 0;
1361 }
1362 } else {
1363#if !defined(CONFIG_USB_EHCI_MSM_72K)
1364 if (init)
1365 ret = msm_charger_register_vbus_sn(callback);
1366 else {
1367 msm_charger_unregister_vbus_sn(callback);
1368 ret = 0;
1369 }
1370#endif
1371 }
1372 return ret;
1373}
1374#endif
1375
1376#if defined(CONFIG_USB_GADGET_MSM_72K) || defined(CONFIG_USB_EHCI_MSM_72K)
1377static struct msm_otg_platform_data msm_otg_pdata = {
1378 /* if usb link is in sps there is no need for
1379 * usb pclk as dayatona fabric clock will be
1380 * used instead
1381 */
1382 .pclk_src_name = "dfab_usb_hs_clk",
1383 .pemp_level = PRE_EMPHASIS_WITH_20_PERCENT,
1384 .cdr_autoreset = CDR_AUTO_RESET_DISABLE,
1385 .se1_gating = SE1_GATING_DISABLE,
Chandra Devireddyb3fc78c2011-08-30 17:25:55 +05301386 .bam_disable = 1,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001387#ifdef CONFIG_USB_EHCI_MSM_72K
1388 .pmic_id_notif_init = msm_hsusb_pmic_id_notif_init,
1389#endif
1390#ifdef CONFIG_USB_EHCI_MSM_72K
1391 .vbus_power = msm_hsusb_vbus_power,
1392#endif
1393#ifdef CONFIG_BATTERY_MSM8X60
1394 .pmic_vbus_notif_init = msm_hsusb_pmic_vbus_notif_init,
1395#endif
1396 .ldo_init = msm_hsusb_ldo_init,
1397 .ldo_enable = msm_hsusb_ldo_enable,
1398 .config_vddcx = msm_hsusb_config_vddcx,
1399 .init_vddcx = msm_hsusb_init_vddcx,
1400#ifdef CONFIG_BATTERY_MSM8X60
1401 .chg_vbus_draw = msm_charger_vbus_draw,
1402#endif
1403};
1404#endif
1405
1406#ifdef CONFIG_USB_GADGET_MSM_72K
1407static struct msm_hsusb_gadget_platform_data msm_gadget_pdata = {
1408 .is_phy_status_timer_on = 1,
1409};
1410#endif
1411
1412#ifdef CONFIG_USB_G_ANDROID
1413
1414#define PID_MAGIC_ID 0x71432909
1415#define SERIAL_NUM_MAGIC_ID 0x61945374
1416#define SERIAL_NUMBER_LENGTH 127
1417#define DLOAD_USB_BASE_ADD 0x2A05F0C8
1418
1419struct magic_num_struct {
1420 uint32_t pid;
1421 uint32_t serial_num;
1422};
1423
1424struct dload_struct {
1425 uint32_t reserved1;
1426 uint32_t reserved2;
1427 uint32_t reserved3;
1428 uint16_t reserved4;
1429 uint16_t pid;
1430 char serial_number[SERIAL_NUMBER_LENGTH];
1431 uint16_t reserved5;
1432 struct magic_num_struct
1433 magic_struct;
1434};
1435
1436static int usb_diag_update_pid_and_serial_num(uint32_t pid, const char *snum)
1437{
1438 struct dload_struct __iomem *dload = 0;
1439
1440 dload = ioremap(DLOAD_USB_BASE_ADD, sizeof(*dload));
1441 if (!dload) {
1442 pr_err("%s: cannot remap I/O memory region: %08x\n",
1443 __func__, DLOAD_USB_BASE_ADD);
1444 return -ENXIO;
1445 }
1446
1447 pr_debug("%s: dload:%p pid:%x serial_num:%s\n",
1448 __func__, dload, pid, snum);
1449 /* update pid */
1450 dload->magic_struct.pid = PID_MAGIC_ID;
1451 dload->pid = pid;
1452
1453 /* update serial number */
1454 dload->magic_struct.serial_num = 0;
1455 if (!snum)
1456 return 0;
1457
1458 dload->magic_struct.serial_num = SERIAL_NUM_MAGIC_ID;
1459 strncpy(dload->serial_number, snum, SERIAL_NUMBER_LENGTH);
1460 dload->serial_number[SERIAL_NUMBER_LENGTH - 1] = '\0';
1461
1462 iounmap(dload);
1463
1464 return 0;
1465}
1466
1467static struct android_usb_platform_data android_usb_pdata = {
1468 .update_pid_and_serial_num = usb_diag_update_pid_and_serial_num,
1469};
1470
1471static struct platform_device android_usb_device = {
1472 .name = "android_usb",
1473 .id = -1,
1474 .dev = {
1475 .platform_data = &android_usb_pdata,
1476 },
1477};
1478
1479
1480#endif
1481
1482#ifdef CONFIG_MSM_VPE
1483static struct resource msm_vpe_resources[] = {
1484 {
1485 .start = 0x05300000,
1486 .end = 0x05300000 + SZ_1M - 1,
1487 .flags = IORESOURCE_MEM,
1488 },
1489 {
1490 .start = INT_VPE,
1491 .end = INT_VPE,
1492 .flags = IORESOURCE_IRQ,
1493 },
1494};
1495
1496static struct platform_device msm_vpe_device = {
1497 .name = "msm_vpe",
1498 .id = 0,
1499 .num_resources = ARRAY_SIZE(msm_vpe_resources),
1500 .resource = msm_vpe_resources,
1501};
1502#endif
1503
1504#ifdef CONFIG_MSM_CAMERA
1505#ifdef CONFIG_MSM_CAMERA_FLASH
1506#define VFE_CAMIF_TIMER1_GPIO 29
1507#define VFE_CAMIF_TIMER2_GPIO 30
1508#define VFE_CAMIF_TIMER3_GPIO_INT 31
1509#define FUSION_VFE_CAMIF_TIMER1_GPIO 42
1510static struct msm_camera_sensor_flash_src msm_flash_src = {
1511 .flash_sr_type = MSM_CAMERA_FLASH_SRC_PMIC,
1512 ._fsrc.pmic_src.num_of_src = 2,
1513 ._fsrc.pmic_src.low_current = 100,
1514 ._fsrc.pmic_src.high_current = 300,
1515 ._fsrc.pmic_src.led_src_1 = PMIC8058_ID_FLASH_LED_0,
1516 ._fsrc.pmic_src.led_src_2 = PMIC8058_ID_FLASH_LED_1,
1517 ._fsrc.pmic_src.pmic_set_current = pm8058_set_flash_led_current,
1518};
1519#ifdef CONFIG_IMX074
1520static struct msm_camera_sensor_strobe_flash_data strobe_flash_xenon = {
1521 .flash_trigger = VFE_CAMIF_TIMER2_GPIO,
1522 .flash_charge = VFE_CAMIF_TIMER1_GPIO,
1523 .flash_charge_done = VFE_CAMIF_TIMER3_GPIO_INT,
1524 .flash_recharge_duration = 50000,
1525 .irq = MSM_GPIO_TO_INT(VFE_CAMIF_TIMER3_GPIO_INT),
1526};
1527#endif
1528#endif
1529
1530int msm_cam_gpio_tbl[] = {
1531 32,/*CAMIF_MCLK*/
1532 47,/*CAMIF_I2C_DATA*/
1533 48,/*CAMIF_I2C_CLK*/
1534 105,/*STANDBY*/
1535};
1536
1537enum msm_cam_stat{
1538 MSM_CAM_OFF,
1539 MSM_CAM_ON,
1540};
1541
1542static int config_gpio_table(enum msm_cam_stat stat)
1543{
1544 int rc = 0, i = 0;
1545 if (stat == MSM_CAM_ON) {
1546 for (i = 0; i < ARRAY_SIZE(msm_cam_gpio_tbl); i++) {
1547 rc = gpio_request(msm_cam_gpio_tbl[i], "CAM_GPIO");
1548 if (unlikely(rc < 0)) {
1549 pr_err("%s not able to get gpio\n", __func__);
1550 for (i--; i >= 0; i--)
1551 gpio_free(msm_cam_gpio_tbl[i]);
1552 break;
1553 }
1554 }
1555 } else {
1556 for (i = 0; i < ARRAY_SIZE(msm_cam_gpio_tbl); i++)
1557 gpio_free(msm_cam_gpio_tbl[i]);
1558 }
1559 return rc;
1560}
1561
1562static struct msm_camera_sensor_platform_info sensor_board_info = {
1563 .mount_angle = 0
1564};
1565
1566/*external regulator VREG_5V*/
1567static struct regulator *reg_flash_5V;
1568
1569static int config_camera_on_gpios_fluid(void)
1570{
1571 int rc = 0;
1572
1573 reg_flash_5V = regulator_get(NULL, "8901_mpp0");
1574 if (IS_ERR(reg_flash_5V)) {
1575 pr_err("'%s' regulator not found, rc=%ld\n",
1576 "8901_mpp0", IS_ERR(reg_flash_5V));
1577 return -ENODEV;
1578 }
1579
1580 rc = regulator_enable(reg_flash_5V);
1581 if (rc) {
1582 pr_err("'%s' regulator enable failed, rc=%d\n",
1583 "8901_mpp0", rc);
1584 regulator_put(reg_flash_5V);
1585 return rc;
1586 }
1587
1588#ifdef CONFIG_IMX074
1589 sensor_board_info.mount_angle = 90;
1590#endif
1591 rc = config_gpio_table(MSM_CAM_ON);
1592 if (rc < 0) {
1593 printk(KERN_ERR "%s: CAMSENSOR gpio table request"
1594 "failed\n", __func__);
1595 return rc;
1596 }
1597
1598 rc = gpio_request(GPIO_EXT_CAMIF_PWR_EN, "CAM_EN");
1599 if (rc < 0) {
1600 printk(KERN_ERR "%s: CAMSENSOR gpio %d request"
1601 "failed\n", __func__, GPIO_EXT_CAMIF_PWR_EN);
1602 regulator_disable(reg_flash_5V);
1603 regulator_put(reg_flash_5V);
1604 return rc;
1605 }
1606 gpio_direction_output(GPIO_EXT_CAMIF_PWR_EN, 0);
1607 msleep(20);
1608 gpio_set_value_cansleep(GPIO_EXT_CAMIF_PWR_EN, 1);
1609
1610
1611 /*Enable LED_FLASH_EN*/
1612 rc = gpio_request(GPIO_LED_FLASH_EN, "LED_FLASH_EN");
1613 if (rc < 0) {
1614 printk(KERN_ERR "%s: CAMSENSOR gpio %d request"
1615 "failed\n", __func__, GPIO_LED_FLASH_EN);
1616
1617 regulator_disable(reg_flash_5V);
1618 regulator_put(reg_flash_5V);
1619 config_gpio_table(MSM_CAM_OFF);
1620 gpio_set_value_cansleep(GPIO_EXT_CAMIF_PWR_EN, 0);
1621 gpio_free(GPIO_EXT_CAMIF_PWR_EN);
1622 return rc;
1623 }
1624 gpio_direction_output(GPIO_LED_FLASH_EN, 1);
1625 msleep(20);
1626 return rc;
1627}
1628
1629
1630static void config_camera_off_gpios_fluid(void)
1631{
1632 regulator_disable(reg_flash_5V);
1633 regulator_put(reg_flash_5V);
1634
1635 gpio_direction_output(GPIO_LED_FLASH_EN, 0);
1636 gpio_free(GPIO_LED_FLASH_EN);
1637
1638 config_gpio_table(MSM_CAM_OFF);
1639
1640 gpio_set_value_cansleep(GPIO_EXT_CAMIF_PWR_EN, 0);
1641 gpio_free(GPIO_EXT_CAMIF_PWR_EN);
1642}
1643static int config_camera_on_gpios(void)
1644{
1645 int rc = 0;
1646
1647 if (machine_is_msm8x60_fluid())
1648 return config_camera_on_gpios_fluid();
1649
1650 rc = config_gpio_table(MSM_CAM_ON);
1651 if (rc < 0) {
1652 printk(KERN_ERR "%s: CAMSENSOR gpio table request"
1653 "failed\n", __func__);
1654 return rc;
1655 }
1656
Jilai Wang971f97f2011-07-13 14:25:25 -04001657 if (!machine_is_msm8x60_dragon()) {
1658 rc = gpio_request(GPIO_EXT_CAMIF_PWR_EN, "CAM_EN");
1659 if (rc < 0) {
1660 config_gpio_table(MSM_CAM_OFF);
1661 pr_err("%s: CAMSENSOR gpio %d request"
1662 "failed\n", __func__, GPIO_EXT_CAMIF_PWR_EN);
1663 return rc;
1664 }
1665 gpio_direction_output(GPIO_EXT_CAMIF_PWR_EN, 0);
1666 msleep(20);
1667 gpio_set_value_cansleep(GPIO_EXT_CAMIF_PWR_EN, 1);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001668 }
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001669
1670#ifdef CONFIG_MSM_CAMERA_FLASH
1671#ifdef CONFIG_IMX074
1672 if (machine_is_msm8x60_fusion() || machine_is_msm8x60_fusn_ffa())
1673 strobe_flash_xenon.flash_charge = FUSION_VFE_CAMIF_TIMER1_GPIO;
1674#endif
1675#endif
1676 return rc;
1677}
1678
1679static void config_camera_off_gpios(void)
1680{
1681 if (machine_is_msm8x60_fluid())
1682 return config_camera_off_gpios_fluid();
1683
1684
1685 config_gpio_table(MSM_CAM_OFF);
1686
Jilai Wang971f97f2011-07-13 14:25:25 -04001687 if (!machine_is_msm8x60_dragon()) {
1688 gpio_set_value_cansleep(GPIO_EXT_CAMIF_PWR_EN, 0);
1689 gpio_free(GPIO_EXT_CAMIF_PWR_EN);
1690 }
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001691}
1692
1693#ifdef CONFIG_QS_S5K4E1
1694
1695#define QS_CAM_HC37_CAM_PD PM8058_GPIO_PM_TO_SYS(26)
1696
1697static int config_camera_on_gpios_qs_cam_fluid(void)
1698{
1699 int rc = 0;
1700
1701 /* request QS_CAM_HC37_CAM_PD as an output to HC37 ASIC pin CAM_PD */
1702 rc = gpio_request(QS_CAM_HC37_CAM_PD, "QS_CAM_HC37_CAM_PD");
1703 if (rc < 0) {
1704 printk(KERN_ERR "%s: QS_CAM_HC37_CAM_PD gpio %d request"
1705 " failed\n", __func__, QS_CAM_HC37_CAM_PD);
1706 return rc;
1707 }
1708 gpio_direction_output(QS_CAM_HC37_CAM_PD, 0);
1709 msleep(20);
1710 gpio_set_value_cansleep(QS_CAM_HC37_CAM_PD, 1);
1711 msleep(20);
1712
1713 /*
1714 * Set GPIO_AUX_CAM_2P7_EN to 1 on North Expander IO2
1715 * to enable 2.7V power to Camera
1716 */
1717 rc = gpio_request(GPIO_AUX_CAM_2P7_EN, "CAM_2P7_EN");
1718 if (rc < 0) {
1719 printk(KERN_ERR "%s: CAMSENSOR gpio %d request"
1720 " failed\n", __func__, GPIO_AUX_CAM_2P7_EN);
1721 gpio_set_value_cansleep(QS_CAM_HC37_CAM_PD, 0);
1722 gpio_free(QS_CAM_HC37_CAM_PD);
1723 return rc;
1724 }
1725 gpio_direction_output(GPIO_AUX_CAM_2P7_EN, 0);
1726 msleep(20);
1727 gpio_set_value_cansleep(GPIO_AUX_CAM_2P7_EN, 1);
1728 msleep(20);
1729
1730 rc = config_camera_on_gpios_fluid();
1731 if (rc < 0) {
1732 printk(KERN_ERR "%s: config_camera_on_gpios_fluid"
1733 " failed\n", __func__);
1734 gpio_set_value_cansleep(QS_CAM_HC37_CAM_PD, 0);
1735 gpio_free(QS_CAM_HC37_CAM_PD);
1736 gpio_set_value_cansleep(GPIO_AUX_CAM_2P7_EN, 0);
1737 gpio_free(GPIO_AUX_CAM_2P7_EN);
1738 return rc;
1739 }
1740 return rc;
1741}
1742
1743static void config_camera_off_gpios_qs_cam_fluid(void)
1744{
1745 /*
1746 * Set GPIO_AUX_CAM_2P7_EN to 0 on North Expander IO2
1747 * to disable 2.7V power to Camera
1748 */
1749 gpio_set_value_cansleep(GPIO_AUX_CAM_2P7_EN, 0);
1750 gpio_free(GPIO_AUX_CAM_2P7_EN);
1751
1752 /* set QS_CAM_HC37_CAM_PD to 0 to power off HC37 ASIC*/
1753 gpio_set_value_cansleep(QS_CAM_HC37_CAM_PD, 0);
1754 gpio_free(QS_CAM_HC37_CAM_PD);
1755
1756 config_camera_off_gpios_fluid();
1757 return;
1758}
1759
1760static int config_camera_on_gpios_qs_cam(void)
1761{
1762 int rc = 0;
1763
1764 if (machine_is_msm8x60_fluid())
1765 return config_camera_on_gpios_qs_cam_fluid();
1766
1767 rc = config_camera_on_gpios();
1768 return rc;
1769}
1770
1771static void config_camera_off_gpios_qs_cam(void)
1772{
1773 if (machine_is_msm8x60_fluid())
1774 return config_camera_off_gpios_qs_cam_fluid();
1775
1776 config_camera_off_gpios();
1777 return;
1778}
1779#endif
1780
1781static int config_camera_on_gpios_web_cam(void)
1782{
1783 int rc = 0;
1784 rc = config_gpio_table(MSM_CAM_ON);
1785 if (rc < 0) {
1786 printk(KERN_ERR "%s: CAMSENSOR gpio table request"
1787 "failed\n", __func__);
1788 return rc;
1789 }
1790
Jilai Wang53d27a82011-07-13 14:32:58 -04001791 if (!(machine_is_msm8x60_fluid() || machine_is_msm8x60_dragon())) {
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001792 rc = gpio_request(GPIO_WEB_CAMIF_STANDBY, "CAM_EN");
1793 if (rc < 0) {
1794 config_gpio_table(MSM_CAM_OFF);
1795 pr_err(KERN_ERR "%s: CAMSENSOR gpio %d request"
1796 "failed\n", __func__, GPIO_WEB_CAMIF_STANDBY);
1797 return rc;
1798 }
1799 gpio_direction_output(GPIO_WEB_CAMIF_STANDBY, 0);
1800 }
1801 return rc;
1802}
1803
1804static void config_camera_off_gpios_web_cam(void)
1805{
1806 config_gpio_table(MSM_CAM_OFF);
Jilai Wang53d27a82011-07-13 14:32:58 -04001807 if (!(machine_is_msm8x60_fluid() || machine_is_msm8x60_dragon())) {
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001808 gpio_set_value_cansleep(GPIO_WEB_CAMIF_STANDBY, 1);
1809 gpio_free(GPIO_WEB_CAMIF_STANDBY);
1810 }
1811 return;
1812}
1813
1814#ifdef CONFIG_MSM_BUS_SCALING
1815static struct msm_bus_vectors cam_init_vectors[] = {
1816 {
1817 .src = MSM_BUS_MASTER_VFE,
1818 .dst = MSM_BUS_SLAVE_SMI,
1819 .ab = 0,
1820 .ib = 0,
1821 },
1822 {
1823 .src = MSM_BUS_MASTER_VFE,
1824 .dst = MSM_BUS_SLAVE_EBI_CH0,
1825 .ab = 0,
1826 .ib = 0,
1827 },
1828 {
1829 .src = MSM_BUS_MASTER_VPE,
1830 .dst = MSM_BUS_SLAVE_SMI,
1831 .ab = 0,
1832 .ib = 0,
1833 },
1834 {
1835 .src = MSM_BUS_MASTER_VPE,
1836 .dst = MSM_BUS_SLAVE_EBI_CH0,
1837 .ab = 0,
1838 .ib = 0,
1839 },
1840 {
1841 .src = MSM_BUS_MASTER_JPEG_ENC,
1842 .dst = MSM_BUS_SLAVE_SMI,
1843 .ab = 0,
1844 .ib = 0,
1845 },
1846 {
1847 .src = MSM_BUS_MASTER_JPEG_ENC,
1848 .dst = MSM_BUS_SLAVE_EBI_CH0,
1849 .ab = 0,
1850 .ib = 0,
1851 },
1852};
1853
1854static struct msm_bus_vectors cam_preview_vectors[] = {
1855 {
1856 .src = MSM_BUS_MASTER_VFE,
1857 .dst = MSM_BUS_SLAVE_SMI,
1858 .ab = 0,
1859 .ib = 0,
1860 },
1861 {
1862 .src = MSM_BUS_MASTER_VFE,
1863 .dst = MSM_BUS_SLAVE_EBI_CH0,
1864 .ab = 283115520,
1865 .ib = 452984832,
1866 },
1867 {
1868 .src = MSM_BUS_MASTER_VPE,
1869 .dst = MSM_BUS_SLAVE_SMI,
1870 .ab = 0,
1871 .ib = 0,
1872 },
1873 {
1874 .src = MSM_BUS_MASTER_VPE,
1875 .dst = MSM_BUS_SLAVE_EBI_CH0,
1876 .ab = 0,
1877 .ib = 0,
1878 },
1879 {
1880 .src = MSM_BUS_MASTER_JPEG_ENC,
1881 .dst = MSM_BUS_SLAVE_SMI,
1882 .ab = 0,
1883 .ib = 0,
1884 },
1885 {
1886 .src = MSM_BUS_MASTER_JPEG_ENC,
1887 .dst = MSM_BUS_SLAVE_EBI_CH0,
1888 .ab = 0,
1889 .ib = 0,
1890 },
1891};
1892
1893static struct msm_bus_vectors cam_video_vectors[] = {
1894 {
1895 .src = MSM_BUS_MASTER_VFE,
1896 .dst = MSM_BUS_SLAVE_SMI,
1897 .ab = 283115520,
1898 .ib = 452984832,
1899 },
1900 {
1901 .src = MSM_BUS_MASTER_VFE,
1902 .dst = MSM_BUS_SLAVE_EBI_CH0,
1903 .ab = 283115520,
1904 .ib = 452984832,
1905 },
1906 {
1907 .src = MSM_BUS_MASTER_VPE,
1908 .dst = MSM_BUS_SLAVE_SMI,
1909 .ab = 319610880,
1910 .ib = 511377408,
1911 },
1912 {
1913 .src = MSM_BUS_MASTER_VPE,
1914 .dst = MSM_BUS_SLAVE_EBI_CH0,
1915 .ab = 0,
1916 .ib = 0,
1917 },
1918 {
1919 .src = MSM_BUS_MASTER_JPEG_ENC,
1920 .dst = MSM_BUS_SLAVE_SMI,
1921 .ab = 0,
1922 .ib = 0,
1923 },
1924 {
1925 .src = MSM_BUS_MASTER_JPEG_ENC,
1926 .dst = MSM_BUS_SLAVE_EBI_CH0,
1927 .ab = 0,
1928 .ib = 0,
1929 },
1930};
1931
1932static struct msm_bus_vectors cam_snapshot_vectors[] = {
1933 {
1934 .src = MSM_BUS_MASTER_VFE,
1935 .dst = MSM_BUS_SLAVE_SMI,
1936 .ab = 566231040,
1937 .ib = 905969664,
1938 },
1939 {
1940 .src = MSM_BUS_MASTER_VFE,
1941 .dst = MSM_BUS_SLAVE_EBI_CH0,
1942 .ab = 69984000,
1943 .ib = 111974400,
1944 },
1945 {
1946 .src = MSM_BUS_MASTER_VPE,
1947 .dst = MSM_BUS_SLAVE_SMI,
1948 .ab = 0,
1949 .ib = 0,
1950 },
1951 {
1952 .src = MSM_BUS_MASTER_VPE,
1953 .dst = MSM_BUS_SLAVE_EBI_CH0,
1954 .ab = 0,
1955 .ib = 0,
1956 },
1957 {
1958 .src = MSM_BUS_MASTER_JPEG_ENC,
1959 .dst = MSM_BUS_SLAVE_SMI,
1960 .ab = 320864256,
1961 .ib = 513382810,
1962 },
1963 {
1964 .src = MSM_BUS_MASTER_JPEG_ENC,
1965 .dst = MSM_BUS_SLAVE_EBI_CH0,
1966 .ab = 320864256,
1967 .ib = 513382810,
1968 },
1969};
1970
1971static struct msm_bus_vectors cam_zsl_vectors[] = {
1972 {
1973 .src = MSM_BUS_MASTER_VFE,
1974 .dst = MSM_BUS_SLAVE_SMI,
1975 .ab = 566231040,
1976 .ib = 905969664,
1977 },
1978 {
1979 .src = MSM_BUS_MASTER_VFE,
1980 .dst = MSM_BUS_SLAVE_EBI_CH0,
1981 .ab = 706199040,
1982 .ib = 1129918464,
1983 },
1984 {
1985 .src = MSM_BUS_MASTER_VPE,
1986 .dst = MSM_BUS_SLAVE_SMI,
1987 .ab = 0,
1988 .ib = 0,
1989 },
1990 {
1991 .src = MSM_BUS_MASTER_VPE,
1992 .dst = MSM_BUS_SLAVE_EBI_CH0,
1993 .ab = 0,
1994 .ib = 0,
1995 },
1996 {
1997 .src = MSM_BUS_MASTER_JPEG_ENC,
1998 .dst = MSM_BUS_SLAVE_SMI,
1999 .ab = 320864256,
2000 .ib = 513382810,
2001 },
2002 {
2003 .src = MSM_BUS_MASTER_JPEG_ENC,
2004 .dst = MSM_BUS_SLAVE_EBI_CH0,
2005 .ab = 320864256,
2006 .ib = 513382810,
2007 },
2008};
2009
2010static struct msm_bus_vectors cam_stereo_video_vectors[] = {
2011 {
2012 .src = MSM_BUS_MASTER_VFE,
2013 .dst = MSM_BUS_SLAVE_SMI,
2014 .ab = 212336640,
2015 .ib = 339738624,
2016 },
2017 {
2018 .src = MSM_BUS_MASTER_VFE,
2019 .dst = MSM_BUS_SLAVE_EBI_CH0,
2020 .ab = 25090560,
2021 .ib = 40144896,
2022 },
2023 {
2024 .src = MSM_BUS_MASTER_VPE,
2025 .dst = MSM_BUS_SLAVE_SMI,
2026 .ab = 239708160,
2027 .ib = 383533056,
2028 },
2029 {
2030 .src = MSM_BUS_MASTER_VPE,
2031 .dst = MSM_BUS_SLAVE_EBI_CH0,
2032 .ab = 79902720,
2033 .ib = 127844352,
2034 },
2035 {
2036 .src = MSM_BUS_MASTER_JPEG_ENC,
2037 .dst = MSM_BUS_SLAVE_SMI,
2038 .ab = 0,
2039 .ib = 0,
2040 },
2041 {
2042 .src = MSM_BUS_MASTER_JPEG_ENC,
2043 .dst = MSM_BUS_SLAVE_EBI_CH0,
2044 .ab = 0,
2045 .ib = 0,
2046 },
2047};
2048
2049static struct msm_bus_vectors cam_stereo_snapshot_vectors[] = {
2050 {
2051 .src = MSM_BUS_MASTER_VFE,
2052 .dst = MSM_BUS_SLAVE_SMI,
2053 .ab = 0,
2054 .ib = 0,
2055 },
2056 {
2057 .src = MSM_BUS_MASTER_VFE,
2058 .dst = MSM_BUS_SLAVE_EBI_CH0,
2059 .ab = 300902400,
2060 .ib = 481443840,
2061 },
2062 {
2063 .src = MSM_BUS_MASTER_VPE,
2064 .dst = MSM_BUS_SLAVE_SMI,
2065 .ab = 230307840,
2066 .ib = 368492544,
2067 },
2068 {
2069 .src = MSM_BUS_MASTER_VPE,
2070 .dst = MSM_BUS_SLAVE_EBI_CH0,
2071 .ab = 245113344,
2072 .ib = 392181351,
2073 },
2074 {
2075 .src = MSM_BUS_MASTER_JPEG_ENC,
2076 .dst = MSM_BUS_SLAVE_SMI,
2077 .ab = 106536960,
2078 .ib = 170459136,
2079 },
2080 {
2081 .src = MSM_BUS_MASTER_JPEG_ENC,
2082 .dst = MSM_BUS_SLAVE_EBI_CH0,
2083 .ab = 106536960,
2084 .ib = 170459136,
2085 },
2086};
2087
2088static struct msm_bus_paths cam_bus_client_config[] = {
2089 {
2090 ARRAY_SIZE(cam_init_vectors),
2091 cam_init_vectors,
2092 },
2093 {
2094 ARRAY_SIZE(cam_preview_vectors),
2095 cam_preview_vectors,
2096 },
2097 {
2098 ARRAY_SIZE(cam_video_vectors),
2099 cam_video_vectors,
2100 },
2101 {
2102 ARRAY_SIZE(cam_snapshot_vectors),
2103 cam_snapshot_vectors,
2104 },
2105 {
2106 ARRAY_SIZE(cam_zsl_vectors),
2107 cam_zsl_vectors,
2108 },
2109 {
2110 ARRAY_SIZE(cam_stereo_video_vectors),
2111 cam_stereo_video_vectors,
2112 },
2113 {
2114 ARRAY_SIZE(cam_stereo_snapshot_vectors),
2115 cam_stereo_snapshot_vectors,
2116 },
2117};
2118
2119static struct msm_bus_scale_pdata cam_bus_client_pdata = {
2120 cam_bus_client_config,
2121 ARRAY_SIZE(cam_bus_client_config),
2122 .name = "msm_camera",
2123};
2124#endif
2125
2126struct msm_camera_device_platform_data msm_camera_device_data = {
2127 .camera_gpio_on = config_camera_on_gpios,
2128 .camera_gpio_off = config_camera_off_gpios,
2129 .ioext.csiphy = 0x04800000,
2130 .ioext.csisz = 0x00000400,
2131 .ioext.csiirq = CSI_0_IRQ,
2132 .ioclk.mclk_clk_rate = 24000000,
2133 .ioclk.vfe_clk_rate = 228570000,
2134#ifdef CONFIG_MSM_BUS_SCALING
2135 .cam_bus_scale_table = &cam_bus_client_pdata,
2136#endif
2137};
2138
2139#ifdef CONFIG_QS_S5K4E1
2140struct msm_camera_device_platform_data msm_camera_device_data_qs_cam = {
2141 .camera_gpio_on = config_camera_on_gpios_qs_cam,
2142 .camera_gpio_off = config_camera_off_gpios_qs_cam,
2143 .ioext.csiphy = 0x04800000,
2144 .ioext.csisz = 0x00000400,
2145 .ioext.csiirq = CSI_0_IRQ,
2146 .ioclk.mclk_clk_rate = 24000000,
2147 .ioclk.vfe_clk_rate = 228570000,
2148#ifdef CONFIG_MSM_BUS_SCALING
2149 .cam_bus_scale_table = &cam_bus_client_pdata,
2150#endif
2151};
2152#endif
2153
2154struct msm_camera_device_platform_data msm_camera_device_data_web_cam = {
2155 .camera_gpio_on = config_camera_on_gpios_web_cam,
2156 .camera_gpio_off = config_camera_off_gpios_web_cam,
2157 .ioext.csiphy = 0x04900000,
2158 .ioext.csisz = 0x00000400,
2159 .ioext.csiirq = CSI_1_IRQ,
2160 .ioclk.mclk_clk_rate = 24000000,
2161 .ioclk.vfe_clk_rate = 228570000,
2162#ifdef CONFIG_MSM_BUS_SCALING
2163 .cam_bus_scale_table = &cam_bus_client_pdata,
2164#endif
2165};
2166
2167struct resource msm_camera_resources[] = {
2168 {
2169 .start = 0x04500000,
2170 .end = 0x04500000 + SZ_1M - 1,
2171 .flags = IORESOURCE_MEM,
2172 },
2173 {
2174 .start = VFE_IRQ,
2175 .end = VFE_IRQ,
2176 .flags = IORESOURCE_IRQ,
2177 },
2178};
2179#ifdef CONFIG_MT9E013
2180static struct msm_camera_sensor_platform_info mt9e013_sensor_8660_info = {
2181 .mount_angle = 0
2182};
2183
2184static struct msm_camera_sensor_flash_data flash_mt9e013 = {
2185 .flash_type = MSM_CAMERA_FLASH_LED,
2186 .flash_src = &msm_flash_src
2187};
2188
2189static struct msm_camera_sensor_info msm_camera_sensor_mt9e013_data = {
2190 .sensor_name = "mt9e013",
2191 .sensor_reset = 106,
2192 .sensor_pwd = 85,
2193 .vcm_pwd = 1,
2194 .vcm_enable = 0,
2195 .pdata = &msm_camera_device_data,
2196 .resource = msm_camera_resources,
2197 .num_resources = ARRAY_SIZE(msm_camera_resources),
2198 .flash_data = &flash_mt9e013,
2199 .strobe_flash_data = &strobe_flash_xenon,
2200 .sensor_platform_info = &mt9e013_sensor_8660_info,
2201 .csi_if = 1
2202};
2203struct platform_device msm_camera_sensor_mt9e013 = {
2204 .name = "msm_camera_mt9e013",
2205 .dev = {
2206 .platform_data = &msm_camera_sensor_mt9e013_data,
2207 },
2208};
2209#endif
2210
2211#ifdef CONFIG_IMX074
2212static struct msm_camera_sensor_flash_data flash_imx074 = {
2213 .flash_type = MSM_CAMERA_FLASH_LED,
2214 .flash_src = &msm_flash_src
2215};
2216
2217static struct msm_camera_sensor_info msm_camera_sensor_imx074_data = {
2218 .sensor_name = "imx074",
2219 .sensor_reset = 106,
2220 .sensor_pwd = 85,
2221 .vcm_pwd = GPIO_AUX_CAM_2P7_EN,
2222 .vcm_enable = 1,
2223 .pdata = &msm_camera_device_data,
2224 .resource = msm_camera_resources,
2225 .num_resources = ARRAY_SIZE(msm_camera_resources),
2226 .flash_data = &flash_imx074,
2227 .strobe_flash_data = &strobe_flash_xenon,
2228 .sensor_platform_info = &sensor_board_info,
2229 .csi_if = 1
2230};
2231struct platform_device msm_camera_sensor_imx074 = {
2232 .name = "msm_camera_imx074",
2233 .dev = {
2234 .platform_data = &msm_camera_sensor_imx074_data,
2235 },
2236};
2237#endif
2238#ifdef CONFIG_WEBCAM_OV9726
2239
2240static struct msm_camera_sensor_platform_info ov9726_sensor_8660_info = {
2241 .mount_angle = 0
2242};
2243
2244static struct msm_camera_sensor_flash_data flash_ov9726 = {
2245 .flash_type = MSM_CAMERA_FLASH_LED,
2246 .flash_src = &msm_flash_src
2247};
2248static struct msm_camera_sensor_info msm_camera_sensor_ov9726_data = {
2249 .sensor_name = "ov9726",
Kevin Chan3382c512011-07-19 21:00:45 -07002250 .sensor_reset_enable = 1,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002251 .sensor_reset = GPIO_FRONT_CAM_RESET_N,
2252 .sensor_pwd = 85,
2253 .vcm_pwd = 1,
2254 .vcm_enable = 0,
2255 .pdata = &msm_camera_device_data_web_cam,
2256 .resource = msm_camera_resources,
2257 .num_resources = ARRAY_SIZE(msm_camera_resources),
2258 .flash_data = &flash_ov9726,
2259 .sensor_platform_info = &ov9726_sensor_8660_info,
2260 .csi_if = 1
2261};
2262struct platform_device msm_camera_sensor_webcam_ov9726 = {
2263 .name = "msm_camera_ov9726",
2264 .dev = {
2265 .platform_data = &msm_camera_sensor_ov9726_data,
2266 },
2267};
2268#endif
2269#ifdef CONFIG_WEBCAM_OV7692
2270static struct msm_camera_sensor_flash_data flash_ov7692 = {
2271 .flash_type = MSM_CAMERA_FLASH_LED,
2272 .flash_src = &msm_flash_src
2273};
2274static struct msm_camera_sensor_info msm_camera_sensor_ov7692_data = {
2275 .sensor_name = "ov7692",
2276 .sensor_reset = GPIO_WEB_CAMIF_RESET_N,
2277 .sensor_pwd = 85,
2278 .vcm_pwd = 1,
2279 .vcm_enable = 0,
2280 .pdata = &msm_camera_device_data_web_cam,
2281 .resource = msm_camera_resources,
2282 .num_resources = ARRAY_SIZE(msm_camera_resources),
2283 .flash_data = &flash_ov7692,
2284 .csi_if = 1
2285};
2286
2287static struct platform_device msm_camera_sensor_webcam_ov7692 = {
2288 .name = "msm_camera_ov7692",
2289 .dev = {
2290 .platform_data = &msm_camera_sensor_ov7692_data,
2291 },
2292};
2293#endif
Jilai Wang971f97f2011-07-13 14:25:25 -04002294#ifdef CONFIG_VX6953
2295static struct msm_camera_sensor_platform_info vx6953_sensor_8660_info = {
2296 .mount_angle = 270
2297};
2298
2299static struct msm_camera_sensor_flash_data flash_vx6953 = {
2300 .flash_type = MSM_CAMERA_FLASH_NONE,
2301 .flash_src = &msm_flash_src
2302};
2303
2304static struct msm_camera_sensor_info msm_camera_sensor_vx6953_data = {
2305 .sensor_name = "vx6953",
2306 .sensor_reset = 63,
2307 .sensor_pwd = 63,
2308 .vcm_pwd = GPIO_AUX_CAM_2P7_EN,
2309 .vcm_enable = 1,
2310 .pdata = &msm_camera_device_data,
2311 .resource = msm_camera_resources,
2312 .num_resources = ARRAY_SIZE(msm_camera_resources),
2313 .flash_data = &flash_vx6953,
2314 .sensor_platform_info = &vx6953_sensor_8660_info,
2315 .csi_if = 1
2316};
2317struct platform_device msm_camera_sensor_vx6953 = {
2318 .name = "msm_camera_vx6953",
2319 .dev = {
2320 .platform_data = &msm_camera_sensor_vx6953_data,
2321 },
2322};
2323#endif
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002324#ifdef CONFIG_QS_S5K4E1
2325
Nishant Pandit613ab7a2011-09-02 03:36:01 +05302326static struct msm_camera_sensor_platform_info qs_s5k4e1_sensor_8660_info = {
2327#ifdef CONFIG_FB_MSM_MIPI_NOVATEK_CMD_QHD_PT
2328 .mount_angle = 90
2329#else
2330 .mount_angle = 0
2331#endif
2332};
2333
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002334static char eeprom_data[864];
2335static struct msm_camera_sensor_flash_data flash_qs_s5k4e1 = {
2336 .flash_type = MSM_CAMERA_FLASH_LED,
2337 .flash_src = &msm_flash_src
2338};
2339
2340static struct msm_camera_sensor_info msm_camera_sensor_qs_s5k4e1_data = {
2341 .sensor_name = "qs_s5k4e1",
2342 .sensor_reset = 106,
2343 .sensor_pwd = 85,
2344 .vcm_pwd = 1,
2345 .vcm_enable = 0,
2346 .pdata = &msm_camera_device_data_qs_cam,
2347 .resource = msm_camera_resources,
2348 .num_resources = ARRAY_SIZE(msm_camera_resources),
2349 .flash_data = &flash_qs_s5k4e1,
2350 .strobe_flash_data = &strobe_flash_xenon,
Nishant Pandit613ab7a2011-09-02 03:36:01 +05302351 .sensor_platform_info = &qs_s5k4e1_sensor_8660_info,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002352 .csi_if = 1,
2353 .eeprom_data = eeprom_data,
2354};
2355struct platform_device msm_camera_sensor_qs_s5k4e1 = {
2356 .name = "msm_camera_qs_s5k4e1",
2357 .dev = {
2358 .platform_data = &msm_camera_sensor_qs_s5k4e1_data,
2359 },
2360};
2361#endif
2362static struct i2c_board_info msm_camera_boardinfo[] __initdata = {
2363 #ifdef CONFIG_MT9E013
2364 {
2365 I2C_BOARD_INFO("mt9e013", 0x6C >> 2),
2366 },
2367 #endif
2368 #ifdef CONFIG_IMX074
2369 {
2370 I2C_BOARD_INFO("imx074", 0x1A),
2371 },
2372 #endif
2373 #ifdef CONFIG_WEBCAM_OV7692
2374 {
2375 I2C_BOARD_INFO("ov7692", 0x78),
2376 },
2377 #endif
2378 #ifdef CONFIG_WEBCAM_OV9726
2379 {
2380 I2C_BOARD_INFO("ov9726", 0x10),
2381 },
2382 #endif
2383 #ifdef CONFIG_QS_S5K4E1
2384 {
2385 I2C_BOARD_INFO("qs_s5k4e1", 0x20),
2386 },
2387 #endif
2388};
Jilai Wang971f97f2011-07-13 14:25:25 -04002389
2390static struct i2c_board_info msm_camera_dragon_boardinfo[] __initdata = {
Jilai Wang53d27a82011-07-13 14:32:58 -04002391 #ifdef CONFIG_WEBCAM_OV9726
2392 {
2393 I2C_BOARD_INFO("ov9726", 0x10),
2394 },
2395 #endif
Jilai Wang971f97f2011-07-13 14:25:25 -04002396 #ifdef CONFIG_VX6953
2397 {
2398 I2C_BOARD_INFO("vx6953", 0x20),
2399 },
2400 #endif
2401};
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002402#endif
2403
2404#ifdef CONFIG_MSM_GEMINI
2405static struct resource msm_gemini_resources[] = {
2406 {
2407 .start = 0x04600000,
2408 .end = 0x04600000 + SZ_1M - 1,
2409 .flags = IORESOURCE_MEM,
2410 },
2411 {
2412 .start = INT_JPEG,
2413 .end = INT_JPEG,
2414 .flags = IORESOURCE_IRQ,
2415 },
2416};
2417
2418static struct platform_device msm_gemini_device = {
2419 .name = "msm_gemini",
2420 .resource = msm_gemini_resources,
2421 .num_resources = ARRAY_SIZE(msm_gemini_resources),
2422};
2423#endif
2424
2425#ifdef CONFIG_I2C_QUP
2426static void gsbi_qup_i2c_gpio_config(int adap_id, int config_type)
2427{
2428}
2429
2430static struct msm_i2c_platform_data msm_gsbi3_qup_i2c_pdata = {
2431 .clk_freq = 384000,
2432 .src_clk_rate = 24000000,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002433 .msm_i2c_config_gpio = gsbi_qup_i2c_gpio_config,
2434};
2435
2436static struct msm_i2c_platform_data msm_gsbi4_qup_i2c_pdata = {
2437 .clk_freq = 100000,
2438 .src_clk_rate = 24000000,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002439 .msm_i2c_config_gpio = gsbi_qup_i2c_gpio_config,
2440};
2441
2442static struct msm_i2c_platform_data msm_gsbi7_qup_i2c_pdata = {
2443 .clk_freq = 100000,
2444 .src_clk_rate = 24000000,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002445 .msm_i2c_config_gpio = gsbi_qup_i2c_gpio_config,
2446};
2447
2448static struct msm_i2c_platform_data msm_gsbi8_qup_i2c_pdata = {
2449 .clk_freq = 100000,
2450 .src_clk_rate = 24000000,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002451 .msm_i2c_config_gpio = gsbi_qup_i2c_gpio_config,
2452};
2453
2454static struct msm_i2c_platform_data msm_gsbi9_qup_i2c_pdata = {
2455 .clk_freq = 100000,
2456 .src_clk_rate = 24000000,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002457 .msm_i2c_config_gpio = gsbi_qup_i2c_gpio_config,
2458};
2459
2460static struct msm_i2c_platform_data msm_gsbi12_qup_i2c_pdata = {
2461 .clk_freq = 100000,
2462 .src_clk_rate = 24000000,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002463 .use_gsbi_shared_mode = 1,
2464 .msm_i2c_config_gpio = gsbi_qup_i2c_gpio_config,
2465};
2466#endif
2467
2468#if defined(CONFIG_SPI_QUP) || defined(CONFIG_SPI_QUP_MODULE)
2469static struct msm_spi_platform_data msm_gsbi1_qup_spi_pdata = {
2470 .max_clock_speed = 24000000,
2471};
2472
2473static struct msm_spi_platform_data msm_gsbi10_qup_spi_pdata = {
2474 .max_clock_speed = 24000000,
2475};
2476#endif
2477
2478#ifdef CONFIG_I2C_SSBI
2479/* PMIC SSBI */
2480static struct msm_i2c_ssbi_platform_data msm_ssbi1_pdata = {
2481 .controller_type = MSM_SBI_CTRL_PMIC_ARBITER,
2482};
2483
2484/* PMIC SSBI */
2485static struct msm_i2c_ssbi_platform_data msm_ssbi2_pdata = {
2486 .controller_type = MSM_SBI_CTRL_PMIC_ARBITER,
2487};
2488
2489/* CODEC/TSSC SSBI */
2490static struct msm_i2c_ssbi_platform_data msm_ssbi3_pdata = {
2491 .controller_type = MSM_SBI_CTRL_SSBI,
2492};
2493#endif
2494
2495#ifdef CONFIG_BATTERY_MSM
2496/* Use basic value for fake MSM battery */
2497static struct msm_psy_batt_pdata msm_psy_batt_data = {
2498 .avail_chg_sources = AC_CHG,
2499};
2500
2501static struct platform_device msm_batt_device = {
2502 .name = "msm-battery",
2503 .id = -1,
2504 .dev.platform_data = &msm_psy_batt_data,
2505};
2506#endif
2507
2508#ifdef CONFIG_FB_MSM_LCDC_DSUB
2509/* VGA = 1440 x 900 x 4(bpp) x 2(pages)
2510 prim = 1024 x 600 x 4(bpp) x 2(pages)
2511 This is the difference. */
2512#define MSM_FB_DSUB_PMEM_ADDER (0xA32000-0x4B0000)
2513#else
2514#define MSM_FB_DSUB_PMEM_ADDER (0)
2515#endif
2516
2517/* Sensors DSPS platform data */
2518#ifdef CONFIG_MSM_DSPS
2519
2520static struct dsps_gpio_info dsps_surf_gpios[] = {
2521 {
2522 .name = "compass_rst_n",
2523 .num = GPIO_COMPASS_RST_N,
2524 .on_val = 1, /* device not in reset */
2525 .off_val = 0, /* device in reset */
2526 },
2527 {
2528 .name = "gpio_r_altimeter_reset_n",
2529 .num = GPIO_R_ALTIMETER_RESET_N,
2530 .on_val = 1, /* device not in reset */
2531 .off_val = 0, /* device in reset */
2532 }
2533};
2534
2535static struct dsps_gpio_info dsps_fluid_gpios[] = {
2536 {
2537 .name = "gpio_n_altimeter_reset_n",
2538 .num = GPIO_N_ALTIMETER_RESET_N,
2539 .on_val = 1, /* device not in reset */
2540 .off_val = 0, /* device in reset */
2541 }
2542};
2543
2544static void __init msm8x60_init_dsps(void)
2545{
2546 struct msm_dsps_platform_data *pdata =
2547 msm_dsps_device.dev.platform_data;
2548 /*
2549 * On Fluid the Compass sensor Chip-Select (CS) is directly connected
2550 * to the power supply and not controled via GPIOs. Fluid uses a
2551 * different IO-Expender (north) than used on surf/ffa.
2552 */
2553 if (machine_is_msm8x60_fluid()) {
2554 /* fluid has different firmware, gpios */
2555 peripheral_dsps.name = DSPS_PIL_FLUID_NAME;
2556 pdata->pil_name = DSPS_PIL_FLUID_NAME;
2557 pdata->gpios = dsps_fluid_gpios;
2558 pdata->gpios_num = ARRAY_SIZE(dsps_fluid_gpios);
2559 } else {
2560 peripheral_dsps.name = DSPS_PIL_GENERIC_NAME;
2561 pdata->pil_name = DSPS_PIL_GENERIC_NAME;
2562 pdata->gpios = dsps_surf_gpios;
2563 pdata->gpios_num = ARRAY_SIZE(dsps_surf_gpios);
2564 }
2565
2566 msm_pil_add_device(&peripheral_dsps);
2567
2568 platform_device_register(&msm_dsps_device);
2569}
2570#endif /* CONFIG_MSM_DSPS */
2571
2572#ifdef CONFIG_FB_MSM_TRIPLE_BUFFER
kuogee hsiehc9a2e6d2011-09-12 15:27:01 -07002573#define MSM_FB_PRIM_BUF_SIZE (1024 * 600 * 4 * 3) /* 4 bpp x 3 pages */
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002574#else
kuogee hsiehc9a2e6d2011-09-12 15:27:01 -07002575#define MSM_FB_PRIM_BUF_SIZE (1024 * 600 * 4 * 2) /* 4 bpp x 2 pages */
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002576#endif
2577
kuogee hsiehc9a2e6d2011-09-12 15:27:01 -07002578#ifdef CONFIG_FB_MSM_HDMI_MSM_PANEL
2579#define MSM_FB_EXT_BUF_SIZE (1920 * 1080 * 2 * 1) /* 2 bpp x 1 page */
2580#elif defined(CONFIG_FB_MSM_TVOUT)
2581#define MSM_FB_EXT_BUF_SIZE (720 * 576 * 2 * 2) /* 2 bpp x 2 pages */
2582#else
2583#define MSM_FB_EXT_BUFT_SIZE 0
2584#endif
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002585
2586#ifdef CONFIG_FB_MSM_OVERLAY_WRITEBACK
kuogee hsieha39040b2011-08-11 15:40:45 -07002587/* width x height x 3 bpp x 2 frame buffer */
2588#define MSM_FB_WRITEBACK_SIZE (1024 * 600 * 3 * 2)
kuogee hsiehc9a2e6d2011-09-12 15:27:01 -07002589#define MSM_FB_WRITEBACK_OFFSET \
2590 (MSM_FB_PRIM_BUF_SIZE + MSM_FB_EXT_BUF_SIZE)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002591#else
kuogee hsiehc9a2e6d2011-09-12 15:27:01 -07002592#define MSM_FB_WRITEBACK_SIZE 0
2593#define MSM_FB_WRITEBACK_OFFSET 0
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002594#endif
2595
Ravishangar Kalyanam75f37322011-10-14 12:15:40 -07002596#ifdef CONFIG_FB_MSM_HDMI_AS_PRIMARY
2597/* 4 bpp x 2 page HDMI case */
2598#define MSM_FB_SIZE roundup((1920 * 1088 * 4 * 2), 4096)
2599#else
kuogee hsiehc9a2e6d2011-09-12 15:27:01 -07002600/* Note: must be multiple of 4096 */
2601#define MSM_FB_SIZE roundup(MSM_FB_PRIM_BUF_SIZE + MSM_FB_EXT_BUF_SIZE + \
2602 MSM_FB_WRITEBACK_SIZE + \
2603 MSM_FB_DSUB_PMEM_ADDER, 4096)
Ravishangar Kalyanam75f37322011-10-14 12:15:40 -07002604#endif
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002605
Ravishangar Kalyanam75f37322011-10-14 12:15:40 -07002606#ifdef CONFIG_FB_MSM_HDMI_AS_PRIMARY
2607#define MSM_PMEM_SF_SIZE 0x8000000 /* 128 Mbytes */
2608#else
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002609#define MSM_PMEM_SF_SIZE 0x4000000 /* 64 Mbytes */
Ravishangar Kalyanam75f37322011-10-14 12:15:40 -07002610#endif
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002611
kuogee hsiehc9a2e6d2011-09-12 15:27:01 -07002612static int writeback_offset(void)
2613{
2614 return MSM_FB_WRITEBACK_OFFSET;
2615}
2616
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002617#define MSM_PMEM_KERNEL_EBI1_SIZE 0x600000
2618#define MSM_PMEM_ADSP_SIZE 0x2000000
Ben Romberger09e462d2011-08-09 15:24:37 -07002619#define MSM_PMEM_AUDIO_SIZE 0x28B000
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002620
2621#define MSM_SMI_BASE 0x38000000
2622#define MSM_SMI_SIZE 0x4000000
2623
2624#define KERNEL_SMI_BASE (MSM_SMI_BASE)
2625#define KERNEL_SMI_SIZE 0x300000
2626
2627#define USER_SMI_BASE (KERNEL_SMI_BASE + KERNEL_SMI_SIZE)
2628#define USER_SMI_SIZE (MSM_SMI_SIZE - KERNEL_SMI_SIZE)
2629#define MSM_PMEM_SMIPOOL_SIZE USER_SMI_SIZE
2630
2631static unsigned fb_size;
2632static int __init fb_size_setup(char *p)
2633{
2634 fb_size = memparse(p, NULL);
2635 return 0;
2636}
2637early_param("fb_size", fb_size_setup);
2638
2639static unsigned pmem_kernel_ebi1_size = MSM_PMEM_KERNEL_EBI1_SIZE;
2640static int __init pmem_kernel_ebi1_size_setup(char *p)
2641{
2642 pmem_kernel_ebi1_size = memparse(p, NULL);
2643 return 0;
2644}
2645early_param("pmem_kernel_ebi1_size", pmem_kernel_ebi1_size_setup);
2646
2647#ifdef CONFIG_ANDROID_PMEM
2648static unsigned pmem_sf_size = MSM_PMEM_SF_SIZE;
2649static int __init pmem_sf_size_setup(char *p)
2650{
2651 pmem_sf_size = memparse(p, NULL);
2652 return 0;
2653}
2654early_param("pmem_sf_size", pmem_sf_size_setup);
2655
2656static unsigned pmem_adsp_size = MSM_PMEM_ADSP_SIZE;
2657
2658static int __init pmem_adsp_size_setup(char *p)
2659{
2660 pmem_adsp_size = memparse(p, NULL);
2661 return 0;
2662}
2663early_param("pmem_adsp_size", pmem_adsp_size_setup);
2664
2665static unsigned pmem_audio_size = MSM_PMEM_AUDIO_SIZE;
2666
2667static int __init pmem_audio_size_setup(char *p)
2668{
2669 pmem_audio_size = memparse(p, NULL);
2670 return 0;
2671}
2672early_param("pmem_audio_size", pmem_audio_size_setup);
2673#endif
2674
2675static struct resource msm_fb_resources[] = {
2676 {
2677 .flags = IORESOURCE_DMA,
2678 }
2679};
2680
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002681static int msm_fb_detect_panel(const char *name)
2682{
2683 if (machine_is_msm8x60_fluid()) {
2684 uint32_t soc_platform_version = socinfo_get_platform_version();
2685 if (SOCINFO_VERSION_MAJOR(soc_platform_version) < 3) {
2686#ifdef CONFIG_FB_MSM_LCDC_SAMSUNG_OLED_PT
2687 if (!strncmp(name, LCDC_SAMSUNG_OLED_PANEL_NAME,
Ravishangar Kalyanam61a7bd12011-07-28 16:48:36 -07002688 strnlen(LCDC_SAMSUNG_OLED_PANEL_NAME,
2689 PANEL_NAME_MAX_LEN)))
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002690 return 0;
2691#endif
2692 } else { /*P3 and up use AUO panel */
2693#ifdef CONFIG_FB_MSM_LCDC_AUO_WVGA
2694 if (!strncmp(name, LCDC_AUO_PANEL_NAME,
Ravishangar Kalyanam61a7bd12011-07-28 16:48:36 -07002695 strnlen(LCDC_AUO_PANEL_NAME,
2696 PANEL_NAME_MAX_LEN)))
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002697 return 0;
2698#endif
2699 }
Zhang Chang Ken3a8b8512011-08-04 18:41:39 -04002700#ifdef CONFIG_FB_MSM_LCDC_NT35582_WVGA
2701 } else if machine_is_msm8x60_dragon() {
2702 if (!strncmp(name, LCDC_NT35582_PANEL_NAME,
Ravishangar Kalyanam61a7bd12011-07-28 16:48:36 -07002703 strnlen(LCDC_NT35582_PANEL_NAME,
2704 PANEL_NAME_MAX_LEN)))
Zhang Chang Ken3a8b8512011-08-04 18:41:39 -04002705 return 0;
2706#endif
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002707 } else {
2708 if (!strncmp(name, LCDC_SAMSUNG_WSVGA_PANEL_NAME,
Ravishangar Kalyanam61a7bd12011-07-28 16:48:36 -07002709 strnlen(LCDC_SAMSUNG_WSVGA_PANEL_NAME,
2710 PANEL_NAME_MAX_LEN)))
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002711 return 0;
Ravishangar Kalyanam61a7bd12011-07-28 16:48:36 -07002712
2713#if !defined(CONFIG_FB_MSM_LCDC_AUTO_DETECT) && \
2714 !defined(CONFIG_FB_MSM_MIPI_PANEL_AUTO_DETECT) && \
2715 !defined(CONFIG_FB_MSM_LCDC_MIPI_PANEL_AUTO_DETECT)
2716 if (!strncmp(name, MIPI_VIDEO_TOSHIBA_WVGA_PANEL_NAME,
2717 strnlen(MIPI_VIDEO_TOSHIBA_WVGA_PANEL_NAME,
2718 PANEL_NAME_MAX_LEN)))
2719 return 0;
2720
2721 if (!strncmp(name, MIPI_VIDEO_NOVATEK_QHD_PANEL_NAME,
2722 strnlen(MIPI_VIDEO_NOVATEK_QHD_PANEL_NAME,
2723 PANEL_NAME_MAX_LEN)))
2724 return 0;
2725
2726 if (!strncmp(name, MIPI_CMD_NOVATEK_QHD_PANEL_NAME,
2727 strnlen(MIPI_CMD_NOVATEK_QHD_PANEL_NAME,
2728 PANEL_NAME_MAX_LEN)))
2729 return 0;
2730#endif
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002731 }
Ravishangar Kalyanam61a7bd12011-07-28 16:48:36 -07002732
2733 if (!strncmp(name, HDMI_PANEL_NAME,
2734 strnlen(HDMI_PANEL_NAME,
2735 PANEL_NAME_MAX_LEN)))
2736 return 0;
2737
2738 if (!strncmp(name, TVOUT_PANEL_NAME,
2739 strnlen(TVOUT_PANEL_NAME,
2740 PANEL_NAME_MAX_LEN)))
2741 return 0;
2742
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002743 pr_warning("%s: not supported '%s'", __func__, name);
2744 return -ENODEV;
2745}
2746
2747static struct msm_fb_platform_data msm_fb_pdata = {
2748 .detect_client = msm_fb_detect_panel,
2749};
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002750
2751static struct platform_device msm_fb_device = {
2752 .name = "msm_fb",
2753 .id = 0,
2754 .num_resources = ARRAY_SIZE(msm_fb_resources),
2755 .resource = msm_fb_resources,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002756 .dev.platform_data = &msm_fb_pdata,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002757};
2758
2759#ifdef CONFIG_ANDROID_PMEM
2760static struct android_pmem_platform_data android_pmem_pdata = {
2761 .name = "pmem",
2762 .allocator_type = PMEM_ALLOCATORTYPE_ALLORNOTHING,
2763 .cached = 1,
2764 .memory_type = MEMTYPE_EBI1,
2765};
2766
2767static struct platform_device android_pmem_device = {
2768 .name = "android_pmem",
2769 .id = 0,
2770 .dev = {.platform_data = &android_pmem_pdata},
2771};
2772
2773static struct android_pmem_platform_data android_pmem_adsp_pdata = {
2774 .name = "pmem_adsp",
2775 .allocator_type = PMEM_ALLOCATORTYPE_BITMAP,
2776 .cached = 0,
2777 .memory_type = MEMTYPE_EBI1,
2778};
2779
2780static struct platform_device android_pmem_adsp_device = {
2781 .name = "android_pmem",
2782 .id = 2,
2783 .dev = { .platform_data = &android_pmem_adsp_pdata },
2784};
2785
2786static struct android_pmem_platform_data android_pmem_audio_pdata = {
2787 .name = "pmem_audio",
2788 .allocator_type = PMEM_ALLOCATORTYPE_BITMAP,
2789 .cached = 0,
2790 .memory_type = MEMTYPE_EBI1,
2791};
2792
2793static struct platform_device android_pmem_audio_device = {
2794 .name = "android_pmem",
2795 .id = 4,
2796 .dev = { .platform_data = &android_pmem_audio_pdata },
2797};
2798
Laura Abbott1e36a022011-06-22 17:08:13 -07002799#define PMEM_BUS_WIDTH(_bw) \
2800 { \
2801 .vectors = &(struct msm_bus_vectors){ \
2802 .src = MSM_BUS_MASTER_AMPSS_M0, \
2803 .dst = MSM_BUS_SLAVE_SMI, \
2804 .ib = (_bw), \
2805 .ab = 0, \
2806 }, \
2807 .num_paths = 1, \
2808 }
2809static struct msm_bus_paths pmem_smi_table[] = {
2810 [0] = PMEM_BUS_WIDTH(0), /* Off */
2811 [1] = PMEM_BUS_WIDTH(1), /* On */
2812};
2813
2814static struct msm_bus_scale_pdata smi_client_pdata = {
2815 .usecase = pmem_smi_table,
2816 .num_usecases = ARRAY_SIZE(pmem_smi_table),
2817 .name = "pmem_smi",
2818};
2819
2820void pmem_request_smi_region(void *data)
2821{
2822 int bus_id = (int) data;
2823
2824 msm_bus_scale_client_update_request(bus_id, 1);
2825}
2826
2827void pmem_release_smi_region(void *data)
2828{
2829 int bus_id = (int) data;
2830
2831 msm_bus_scale_client_update_request(bus_id, 0);
2832}
2833
2834void *pmem_setup_smi_region(void)
2835{
2836 return (void *)msm_bus_scale_register_client(&smi_client_pdata);
2837}
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002838static struct android_pmem_platform_data android_pmem_smipool_pdata = {
2839 .name = "pmem_smipool",
2840 .allocator_type = PMEM_ALLOCATORTYPE_BITMAP,
2841 .cached = 0,
2842 .memory_type = MEMTYPE_SMI,
Laura Abbott1e36a022011-06-22 17:08:13 -07002843 .request_region = pmem_request_smi_region,
2844 .release_region = pmem_release_smi_region,
2845 .setup_region = pmem_setup_smi_region,
2846 .map_on_demand = 1,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002847};
2848static struct platform_device android_pmem_smipool_device = {
2849 .name = "android_pmem",
2850 .id = 7,
2851 .dev = { .platform_data = &android_pmem_smipool_pdata },
2852};
2853
2854#endif
2855
2856#define GPIO_DONGLE_PWR_EN 258
2857static void setup_display_power(void);
2858static int lcdc_vga_enabled;
2859static int vga_enable_request(int enable)
2860{
2861 if (enable)
2862 lcdc_vga_enabled = 1;
2863 else
2864 lcdc_vga_enabled = 0;
2865 setup_display_power();
2866
2867 return 0;
2868}
2869
2870#define GPIO_BACKLIGHT_PWM0 0
2871#define GPIO_BACKLIGHT_PWM1 1
2872
2873static int pmic_backlight_gpio[2]
2874 = { GPIO_BACKLIGHT_PWM0, GPIO_BACKLIGHT_PWM1 };
2875static struct msm_panel_common_pdata lcdc_samsung_panel_data = {
2876 .gpio_num = pmic_backlight_gpio, /* two LPG CHANNELS for backlight */
2877 .vga_switch = vga_enable_request,
2878};
2879
2880static struct platform_device lcdc_samsung_panel_device = {
2881 .name = LCDC_SAMSUNG_WSVGA_PANEL_NAME,
2882 .id = 0,
2883 .dev = {
2884 .platform_data = &lcdc_samsung_panel_data,
2885 }
2886};
2887#if (!defined(CONFIG_SPI_QUP)) && \
2888 (defined(CONFIG_FB_MSM_LCDC_SAMSUNG_OLED_PT) || \
2889 defined(CONFIG_FB_MSM_LCDC_AUO_WVGA))
2890
2891static int lcdc_spi_gpio_array_num[] = {
2892 LCDC_SPI_GPIO_CLK,
2893 LCDC_SPI_GPIO_CS,
2894 LCDC_SPI_GPIO_MOSI,
2895};
2896
2897static uint32_t lcdc_spi_gpio_config_data[] = {
2898 GPIO_CFG(LCDC_SPI_GPIO_CLK, 0,
2899 GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA),
2900 GPIO_CFG(LCDC_SPI_GPIO_CS, 0,
2901 GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA),
2902 GPIO_CFG(LCDC_SPI_GPIO_MOSI, 0,
2903 GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA),
2904};
2905
2906static void lcdc_config_spi_gpios(int enable)
2907{
2908 int n;
2909 for (n = 0; n < ARRAY_SIZE(lcdc_spi_gpio_config_data); ++n)
2910 gpio_tlmm_config(lcdc_spi_gpio_config_data[n], 0);
2911}
2912#endif
2913
2914#ifdef CONFIG_FB_MSM_LCDC_SAMSUNG_OLED_PT
2915#ifdef CONFIG_SPI_QUP
2916static struct spi_board_info lcdc_samsung_spi_board_info[] __initdata = {
2917 {
2918 .modalias = LCDC_SAMSUNG_SPI_DEVICE_NAME,
2919 .mode = SPI_MODE_3,
2920 .bus_num = 1,
2921 .chip_select = 0,
2922 .max_speed_hz = 10800000,
2923 }
2924};
2925#endif /* CONFIG_SPI_QUP */
2926
2927static struct msm_panel_common_pdata lcdc_samsung_oled_panel_data = {
2928#ifndef CONFIG_SPI_QUP
2929 .panel_config_gpio = lcdc_config_spi_gpios,
2930 .gpio_num = lcdc_spi_gpio_array_num,
2931#endif
2932};
2933
2934static struct platform_device lcdc_samsung_oled_panel_device = {
2935 .name = LCDC_SAMSUNG_OLED_PANEL_NAME,
2936 .id = 0,
2937 .dev.platform_data = &lcdc_samsung_oled_panel_data,
2938};
2939#endif /*CONFIG_FB_MSM_LCDC_SAMSUNG_OLED_PT */
2940
2941#ifdef CONFIG_FB_MSM_LCDC_AUO_WVGA
2942#ifdef CONFIG_SPI_QUP
2943static struct spi_board_info lcdc_auo_spi_board_info[] __initdata = {
2944 {
2945 .modalias = LCDC_AUO_SPI_DEVICE_NAME,
2946 .mode = SPI_MODE_3,
2947 .bus_num = 1,
2948 .chip_select = 0,
2949 .max_speed_hz = 10800000,
2950 }
2951};
2952#endif
2953
2954static struct msm_panel_common_pdata lcdc_auo_wvga_panel_data = {
2955#ifndef CONFIG_SPI_QUP
2956 .panel_config_gpio = lcdc_config_spi_gpios,
2957 .gpio_num = lcdc_spi_gpio_array_num,
2958#endif
2959};
2960
2961static struct platform_device lcdc_auo_wvga_panel_device = {
2962 .name = LCDC_AUO_PANEL_NAME,
2963 .id = 0,
2964 .dev.platform_data = &lcdc_auo_wvga_panel_data,
2965};
2966#endif /*CONFIG_FB_MSM_LCDC_AUO_WVGA*/
2967
Zhang Chang Ken3a8b8512011-08-04 18:41:39 -04002968#ifdef CONFIG_FB_MSM_LCDC_NT35582_WVGA
2969
2970#define GPIO_NT35582_RESET 94
2971#define GPIO_NT35582_BL_EN_HW_PIN 24
2972#define GPIO_NT35582_BL_EN \
2973 PM8058_GPIO_PM_TO_SYS(GPIO_NT35582_BL_EN_HW_PIN - 1)
2974
2975static int lcdc_nt35582_pmic_gpio[] = {GPIO_NT35582_BL_EN };
2976
2977static struct msm_panel_common_pdata lcdc_nt35582_panel_data = {
2978 .gpio_num = lcdc_nt35582_pmic_gpio,
2979};
2980
2981static struct platform_device lcdc_nt35582_panel_device = {
2982 .name = LCDC_NT35582_PANEL_NAME,
2983 .id = 0,
2984 .dev = {
2985 .platform_data = &lcdc_nt35582_panel_data,
2986 }
2987};
2988
2989static struct spi_board_info lcdc_nt35582_spi_board_info[] __initdata = {
2990 {
2991 .modalias = "lcdc_nt35582_spi",
2992 .mode = SPI_MODE_0,
2993 .bus_num = 0,
2994 .chip_select = 0,
2995 .max_speed_hz = 1100000,
2996 }
2997};
2998#endif
2999
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003000#ifdef CONFIG_FB_MSM_HDMI_MSM_PANEL
3001static struct resource hdmi_msm_resources[] = {
3002 {
3003 .name = "hdmi_msm_qfprom_addr",
3004 .start = 0x00700000,
3005 .end = 0x007060FF,
3006 .flags = IORESOURCE_MEM,
3007 },
3008 {
3009 .name = "hdmi_msm_hdmi_addr",
3010 .start = 0x04A00000,
3011 .end = 0x04A00FFF,
3012 .flags = IORESOURCE_MEM,
3013 },
3014 {
3015 .name = "hdmi_msm_irq",
3016 .start = HDMI_IRQ,
3017 .end = HDMI_IRQ,
3018 .flags = IORESOURCE_IRQ,
3019 },
3020};
3021
3022static int hdmi_enable_5v(int on);
3023static int hdmi_core_power(int on, int show);
3024static int hdmi_cec_power(int on);
3025
3026static struct msm_hdmi_platform_data hdmi_msm_data = {
3027 .irq = HDMI_IRQ,
3028 .enable_5v = hdmi_enable_5v,
3029 .core_power = hdmi_core_power,
3030 .cec_power = hdmi_cec_power,
3031};
3032
3033static struct platform_device hdmi_msm_device = {
3034 .name = "hdmi_msm",
3035 .id = 0,
3036 .num_resources = ARRAY_SIZE(hdmi_msm_resources),
3037 .resource = hdmi_msm_resources,
3038 .dev.platform_data = &hdmi_msm_data,
3039};
3040#endif /* CONFIG_FB_MSM_HDMI_MSM_PANEL */
3041
3042#ifdef CONFIG_FB_MSM_MIPI_DSI
3043static struct platform_device mipi_dsi_toshiba_panel_device = {
3044 .name = "mipi_toshiba",
3045 .id = 0,
3046};
3047
3048#define FPGA_3D_GPIO_CONFIG_ADDR 0x1D00017A
3049
Nagamalleswararao Ganjieac5dfa2011-07-23 17:31:16 -07003050static struct mipi_dsi_panel_platform_data novatek_pdata = {
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003051 .fpga_3d_config_addr = FPGA_3D_GPIO_CONFIG_ADDR,
Chandan Uddaraju83eac3c2011-09-11 18:32:23 -07003052 .fpga_ctrl_mode = FPGA_EBI2_INTF,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003053};
3054
3055static struct platform_device mipi_dsi_novatek_panel_device = {
3056 .name = "mipi_novatek",
3057 .id = 0,
3058 .dev = {
3059 .platform_data = &novatek_pdata,
3060 }
3061};
3062#endif
3063
3064static void __init msm8x60_allocate_memory_regions(void)
3065{
3066 void *addr;
3067 unsigned long size;
3068
3069 size = MSM_FB_SIZE;
3070 addr = alloc_bootmem_align(size, 0x1000);
3071 msm_fb_resources[0].start = __pa(addr);
3072 msm_fb_resources[0].end = msm_fb_resources[0].start + size - 1;
3073 pr_info("allocating %lu bytes at %p (%lx physical) for fb\n",
3074 size, addr, __pa(addr));
3075
3076}
3077
3078#if defined(CONFIG_TOUCHSCREEN_CYTTSP_I2C) || \
3079 defined(CONFIG_TOUCHSCREEN_CYTTSP_I2C_MODULE)
3080/*virtual key support */
3081static ssize_t tma300_vkeys_show(struct kobject *kobj,
3082 struct kobj_attribute *attr, char *buf)
3083{
3084 return sprintf(buf,
3085 __stringify(EV_KEY) ":" __stringify(KEY_BACK) ":60:900:90:120"
3086 ":" __stringify(EV_KEY) ":" __stringify(KEY_MENU) ":180:900:90:120"
3087 ":" __stringify(EV_KEY) ":" __stringify(KEY_HOME) ":300:900:90:120"
3088 ":" __stringify(EV_KEY) ":" __stringify(KEY_SEARCH) ":420:900:90:120"
3089 "\n");
3090}
3091
3092static struct kobj_attribute tma300_vkeys_attr = {
3093 .attr = {
3094 .mode = S_IRUGO,
3095 },
3096 .show = &tma300_vkeys_show,
3097};
3098
3099static struct attribute *tma300_properties_attrs[] = {
3100 &tma300_vkeys_attr.attr,
3101 NULL
3102};
3103
3104static struct attribute_group tma300_properties_attr_group = {
3105 .attrs = tma300_properties_attrs,
3106};
3107
3108static struct kobject *properties_kobj;
3109
3110
3111
3112#define CYTTSP_TS_GPIO_IRQ 61
3113static int cyttsp_platform_init(struct i2c_client *client)
3114{
3115 int rc = -EINVAL;
3116 struct regulator *pm8058_l5 = NULL, *pm8058_s3;
3117
3118 if (machine_is_msm8x60_fluid()) {
3119 pm8058_l5 = regulator_get(NULL, "8058_l5");
3120 if (IS_ERR(pm8058_l5)) {
3121 pr_err("%s: regulator get of 8058_l5 failed (%ld)\n",
3122 __func__, PTR_ERR(pm8058_l5));
3123 rc = PTR_ERR(pm8058_l5);
3124 return rc;
3125 }
3126 rc = regulator_set_voltage(pm8058_l5, 2850000, 2850000);
3127 if (rc) {
3128 pr_err("%s: regulator_set_voltage of 8058_l5 failed(%d)\n",
3129 __func__, rc);
3130 goto reg_l5_put;
3131 }
3132
3133 rc = regulator_enable(pm8058_l5);
3134 if (rc) {
3135 pr_err("%s: regulator_enable of 8058_l5 failed(%d)\n",
3136 __func__, rc);
3137 goto reg_l5_put;
3138 }
3139 }
3140 /* vote for s3 to enable i2c communication lines */
3141 pm8058_s3 = regulator_get(NULL, "8058_s3");
3142 if (IS_ERR(pm8058_s3)) {
3143 pr_err("%s: regulator get of 8058_s3 failed (%ld)\n",
3144 __func__, PTR_ERR(pm8058_s3));
3145 rc = PTR_ERR(pm8058_s3);
3146 goto reg_l5_disable;
3147 }
3148
3149 rc = regulator_set_voltage(pm8058_s3, 1800000, 1800000);
3150 if (rc) {
3151 pr_err("%s: regulator_set_voltage() = %d\n",
3152 __func__, rc);
3153 goto reg_s3_put;
3154 }
3155
3156 rc = regulator_enable(pm8058_s3);
3157 if (rc) {
3158 pr_err("%s: regulator_enable of 8058_l5 failed(%d)\n",
3159 __func__, rc);
3160 goto reg_s3_put;
3161 }
3162
3163 /* wait for vregs to stabilize */
3164 usleep_range(10000, 10000);
3165
3166 /* check this device active by reading first byte/register */
3167 rc = i2c_smbus_read_byte_data(client, 0x01);
3168 if (rc < 0) {
3169 pr_err("%s: i2c sanity check failed\n", __func__);
3170 goto reg_s3_disable;
3171 }
3172
3173 /* virtual keys */
3174 if (machine_is_msm8x60_fluid()) {
3175 tma300_vkeys_attr.attr.name = "virtualkeys.cyttsp-i2c";
3176 properties_kobj = kobject_create_and_add("board_properties",
3177 NULL);
3178 if (properties_kobj)
3179 rc = sysfs_create_group(properties_kobj,
3180 &tma300_properties_attr_group);
3181 if (!properties_kobj || rc)
3182 pr_err("%s: failed to create board_properties\n",
3183 __func__);
3184 }
3185 return CY_OK;
3186
3187reg_s3_disable:
3188 regulator_disable(pm8058_s3);
3189reg_s3_put:
3190 regulator_put(pm8058_s3);
3191reg_l5_disable:
3192 if (machine_is_msm8x60_fluid())
3193 regulator_disable(pm8058_l5);
3194reg_l5_put:
3195 if (machine_is_msm8x60_fluid())
3196 regulator_put(pm8058_l5);
3197 return rc;
3198}
3199
3200static int cyttsp_platform_resume(struct i2c_client *client)
3201{
3202 /* add any special code to strobe a wakeup pin or chip reset */
3203 msleep(10);
3204
3205 return CY_OK;
3206}
3207
3208static struct cyttsp_platform_data cyttsp_fluid_pdata = {
3209 .flags = 0x04,
3210 .gen = CY_GEN3, /* or */
3211 .use_st = CY_USE_ST,
3212 .use_mt = CY_USE_MT,
3213 .use_hndshk = CY_SEND_HNDSHK,
3214 .use_trk_id = CY_USE_TRACKING_ID,
Anirudh Ghayal15187772011-06-22 17:39:41 +05303215 .use_sleep = CY_USE_DEEP_SLEEP_SEL | CY_USE_LOW_POWER_SEL,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003216 .use_gestures = CY_USE_GESTURES,
3217 /* activate up to 4 groups
3218 * and set active distance
3219 */
3220 .gest_set = CY_GEST_GRP1 | CY_GEST_GRP2 |
3221 CY_GEST_GRP3 | CY_GEST_GRP4 |
3222 CY_ACT_DIST,
3223 /* change act_intrvl to customize the Active power state
3224 * scanning/processing refresh interval for Operating mode
3225 */
3226 .act_intrvl = CY_ACT_INTRVL_DFLT,
3227 /* change tch_tmout to customize the touch timeout for the
3228 * Active power state for Operating mode
3229 */
3230 .tch_tmout = CY_TCH_TMOUT_DFLT,
3231 /* change lp_intrvl to customize the Low Power power state
3232 * scanning/processing refresh interval for Operating mode
3233 */
3234 .lp_intrvl = CY_LP_INTRVL_DFLT,
3235 .sleep_gpio = -1,
3236 .resout_gpio = -1,
3237 .irq_gpio = CYTTSP_TS_GPIO_IRQ,
3238 .resume = cyttsp_platform_resume,
3239 .init = cyttsp_platform_init,
3240};
3241
3242static struct cyttsp_platform_data cyttsp_tmg240_pdata = {
3243 .panel_maxx = 1083,
3244 .panel_maxy = 659,
3245 .disp_minx = 30,
3246 .disp_maxx = 1053,
3247 .disp_miny = 30,
3248 .disp_maxy = 629,
3249 .correct_fw_ver = 8,
3250 .fw_fname = "cyttsp_8660_ffa.hex",
3251 .flags = 0x00,
3252 .gen = CY_GEN2, /* or */
3253 .use_st = CY_USE_ST,
3254 .use_mt = CY_USE_MT,
3255 .use_hndshk = CY_SEND_HNDSHK,
3256 .use_trk_id = CY_USE_TRACKING_ID,
Anirudh Ghayal15187772011-06-22 17:39:41 +05303257 .use_sleep = CY_USE_DEEP_SLEEP_SEL | CY_USE_LOW_POWER_SEL,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003258 .use_gestures = CY_USE_GESTURES,
3259 /* activate up to 4 groups
3260 * and set active distance
3261 */
3262 .gest_set = CY_GEST_GRP1 | CY_GEST_GRP2 |
3263 CY_GEST_GRP3 | CY_GEST_GRP4 |
3264 CY_ACT_DIST,
3265 /* change act_intrvl to customize the Active power state
3266 * scanning/processing refresh interval for Operating mode
3267 */
3268 .act_intrvl = CY_ACT_INTRVL_DFLT,
3269 /* change tch_tmout to customize the touch timeout for the
3270 * Active power state for Operating mode
3271 */
3272 .tch_tmout = CY_TCH_TMOUT_DFLT,
3273 /* change lp_intrvl to customize the Low Power power state
3274 * scanning/processing refresh interval for Operating mode
3275 */
3276 .lp_intrvl = CY_LP_INTRVL_DFLT,
3277 .sleep_gpio = -1,
3278 .resout_gpio = -1,
3279 .irq_gpio = CYTTSP_TS_GPIO_IRQ,
3280 .resume = cyttsp_platform_resume,
3281 .init = cyttsp_platform_init,
Mohan Pallaka1ea7d8a2011-08-18 15:06:00 +05303282 .disable_ghost_det = true,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003283};
3284static void cyttsp_set_params(void)
3285{
3286 if (SOCINFO_VERSION_MAJOR(socinfo_get_platform_version()) < 3) {
3287 cyttsp_fluid_pdata.fw_fname = "cyttsp_8660_fluid_p2.hex";
3288 cyttsp_fluid_pdata.panel_maxx = 539;
3289 cyttsp_fluid_pdata.panel_maxy = 994;
3290 cyttsp_fluid_pdata.disp_minx = 30;
3291 cyttsp_fluid_pdata.disp_maxx = 509;
3292 cyttsp_fluid_pdata.disp_miny = 60;
3293 cyttsp_fluid_pdata.disp_maxy = 859;
3294 cyttsp_fluid_pdata.correct_fw_ver = 4;
3295 } else {
3296 cyttsp_fluid_pdata.fw_fname = "cyttsp_8660_fluid_p3.hex";
3297 cyttsp_fluid_pdata.panel_maxx = 550;
3298 cyttsp_fluid_pdata.panel_maxy = 1013;
3299 cyttsp_fluid_pdata.disp_minx = 35;
3300 cyttsp_fluid_pdata.disp_maxx = 515;
3301 cyttsp_fluid_pdata.disp_miny = 69;
3302 cyttsp_fluid_pdata.disp_maxy = 869;
3303 cyttsp_fluid_pdata.correct_fw_ver = 5;
3304 }
3305
3306}
3307
3308static struct i2c_board_info cyttsp_fluid_info[] __initdata = {
3309 {
3310 I2C_BOARD_INFO(CY_I2C_NAME, 0x24),
3311 .platform_data = &cyttsp_fluid_pdata,
3312#ifndef CY_USE_TIMER
3313 .irq = MSM_GPIO_TO_INT(CYTTSP_TS_GPIO_IRQ),
3314#endif /* CY_USE_TIMER */
3315 },
3316};
3317
3318static struct i2c_board_info cyttsp_ffa_info[] __initdata = {
3319 {
3320 I2C_BOARD_INFO(CY_I2C_NAME, 0x3b),
3321 .platform_data = &cyttsp_tmg240_pdata,
3322#ifndef CY_USE_TIMER
3323 .irq = MSM_GPIO_TO_INT(CYTTSP_TS_GPIO_IRQ),
3324#endif /* CY_USE_TIMER */
3325 },
3326};
3327#endif
3328
3329static struct regulator *vreg_tmg200;
3330
3331#define TS_PEN_IRQ_GPIO 61
3332static int tmg200_power(int vreg_on)
3333{
3334 int rc = -EINVAL;
3335
3336 if (!vreg_tmg200) {
3337 printk(KERN_ERR "%s: regulator 8058_s3 not found (%d)\n",
3338 __func__, rc);
3339 return rc;
3340 }
3341
3342 rc = vreg_on ? regulator_enable(vreg_tmg200) :
3343 regulator_disable(vreg_tmg200);
3344 if (rc < 0)
3345 printk(KERN_ERR "%s: vreg 8058_s3 %s failed (%d)\n",
3346 __func__, vreg_on ? "enable" : "disable", rc);
3347
3348 /* wait for vregs to stabilize */
Amy Maloche12b5d4e2011-08-03 15:42:28 -07003349 msleep(20);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003350
3351 return rc;
3352}
3353
3354static int tmg200_dev_setup(bool enable)
3355{
3356 int rc;
3357
3358 if (enable) {
3359 vreg_tmg200 = regulator_get(NULL, "8058_s3");
3360 if (IS_ERR(vreg_tmg200)) {
3361 pr_err("%s: regulator get of 8058_s3 failed (%ld)\n",
3362 __func__, PTR_ERR(vreg_tmg200));
3363 rc = PTR_ERR(vreg_tmg200);
3364 return rc;
3365 }
3366
3367 rc = regulator_set_voltage(vreg_tmg200, 1800000, 1800000);
3368 if (rc) {
3369 pr_err("%s: regulator_set_voltage() = %d\n",
3370 __func__, rc);
3371 goto reg_put;
3372 }
3373 } else {
3374 /* put voltage sources */
3375 regulator_put(vreg_tmg200);
3376 }
3377 return 0;
3378reg_put:
3379 regulator_put(vreg_tmg200);
3380 return rc;
3381}
3382
3383static struct cy8c_ts_platform_data cy8ctmg200_pdata = {
3384 .ts_name = "msm_tmg200_ts",
3385 .dis_min_x = 0,
3386 .dis_max_x = 1023,
3387 .dis_min_y = 0,
3388 .dis_max_y = 599,
3389 .min_tid = 0,
3390 .max_tid = 255,
3391 .min_touch = 0,
3392 .max_touch = 255,
3393 .min_width = 0,
3394 .max_width = 255,
3395 .power_on = tmg200_power,
3396 .dev_setup = tmg200_dev_setup,
3397 .nfingers = 2,
3398 .irq_gpio = TS_PEN_IRQ_GPIO,
3399 .resout_gpio = GPIO_CAP_TS_RESOUT_N,
3400};
3401
3402static struct i2c_board_info cy8ctmg200_board_info[] = {
3403 {
3404 I2C_BOARD_INFO("cy8ctmg200", 0x2),
3405 .platform_data = &cy8ctmg200_pdata,
3406 }
3407};
3408
Zhang Chang Ken211df572011-07-05 19:16:39 -04003409static struct regulator *vreg_tma340;
3410
3411static int tma340_power(int vreg_on)
3412{
3413 int rc = -EINVAL;
3414
3415 if (!vreg_tma340) {
3416 pr_err("%s: regulator 8901_l2 not found (%d)\n",
3417 __func__, rc);
3418 return rc;
3419 }
3420
3421 rc = vreg_on ? regulator_enable(vreg_tma340) :
3422 regulator_disable(vreg_tma340);
3423 if (rc < 0)
3424 pr_err("%s: vreg 8901_l2 %s failed (%d)\n",
3425 __func__, vreg_on ? "enable" : "disable", rc);
3426
3427 /* wait for vregs to stabilize */
Amy Malocheb5c67e8d2011-08-18 16:39:35 -07003428 msleep(100);
Zhang Chang Ken211df572011-07-05 19:16:39 -04003429
3430 return rc;
3431}
3432
3433static struct kobject *tma340_prop_kobj;
3434
3435static int tma340_dragon_dev_setup(bool enable)
3436{
3437 int rc;
3438
3439 if (enable) {
3440 vreg_tma340 = regulator_get(NULL, "8901_l2");
3441 if (IS_ERR(vreg_tma340)) {
3442 pr_err("%s: regulator get of 8901_l2 failed (%ld)\n",
3443 __func__, PTR_ERR(vreg_tma340));
3444 rc = PTR_ERR(vreg_tma340);
3445 return rc;
3446 }
3447
3448 rc = regulator_set_voltage(vreg_tma340, 3300000, 3300000);
3449 if (rc) {
3450 pr_err("%s: regulator_set_voltage() = %d\n",
3451 __func__, rc);
3452 goto reg_put;
3453 }
3454 tma300_vkeys_attr.attr.name = "virtualkeys.cy8ctma340";
3455 tma340_prop_kobj = kobject_create_and_add("board_properties",
3456 NULL);
3457 if (tma340_prop_kobj) {
3458 rc = sysfs_create_group(tma340_prop_kobj,
3459 &tma300_properties_attr_group);
3460 if (rc) {
3461 kobject_put(tma340_prop_kobj);
3462 pr_err("%s: failed to create board_properties\n",
3463 __func__);
3464 goto reg_put;
3465 }
3466 }
3467
3468 } else {
3469 /* put voltage sources */
3470 regulator_put(vreg_tma340);
3471 /* destroy virtual keys */
3472 if (tma340_prop_kobj) {
3473 sysfs_remove_group(tma340_prop_kobj,
3474 &tma300_properties_attr_group);
3475 kobject_put(tma340_prop_kobj);
3476 }
3477 }
3478 return 0;
3479reg_put:
3480 regulator_put(vreg_tma340);
3481 return rc;
3482}
3483
3484
3485static struct cy8c_ts_platform_data cy8ctma340_dragon_pdata = {
3486 .ts_name = "cy8ctma340",
3487 .dis_min_x = 0,
3488 .dis_max_x = 479,
3489 .dis_min_y = 0,
3490 .dis_max_y = 799,
3491 .min_tid = 0,
3492 .max_tid = 255,
3493 .min_touch = 0,
3494 .max_touch = 255,
3495 .min_width = 0,
3496 .max_width = 255,
3497 .power_on = tma340_power,
3498 .dev_setup = tma340_dragon_dev_setup,
3499 .nfingers = 2,
3500 .irq_gpio = TS_PEN_IRQ_GPIO,
3501 .resout_gpio = -1,
3502};
3503
3504static struct i2c_board_info cy8ctma340_dragon_board_info[] = {
3505 {
3506 I2C_BOARD_INFO("cy8ctma340", 0x24),
3507 .platform_data = &cy8ctma340_dragon_pdata,
3508 }
3509};
3510
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003511#ifdef CONFIG_SERIAL_MSM_HS
3512static int configure_uart_gpios(int on)
3513{
3514 int ret = 0, i;
3515 int uart_gpios[] = {53, 54, 55, 56};
3516 for (i = 0; i < ARRAY_SIZE(uart_gpios); i++) {
3517 if (on) {
3518 ret = msm_gpiomux_get(uart_gpios[i]);
3519 if (unlikely(ret))
3520 break;
3521 } else {
3522 ret = msm_gpiomux_put(uart_gpios[i]);
3523 if (unlikely(ret))
3524 return ret;
3525 }
3526 }
3527 if (ret)
3528 for (; i >= 0; i--)
3529 msm_gpiomux_put(uart_gpios[i]);
3530 return ret;
3531}
3532static struct msm_serial_hs_platform_data msm_uart_dm1_pdata = {
3533 .inject_rx_on_wakeup = 1,
3534 .rx_to_inject = 0xFD,
3535 .gpio_config = configure_uart_gpios,
3536};
3537#endif
3538
3539
3540#if defined(CONFIG_GPIO_SX150X) || defined(CONFIG_GPIO_SX150X_MODULE)
3541
3542static struct gpio_led gpio_exp_leds_config[] = {
3543 {
3544 .name = "left_led1:green",
3545 .gpio = GPIO_LEFT_LED_1,
3546 .active_low = 1,
3547 .retain_state_suspended = 0,
3548 .default_state = LEDS_GPIO_DEFSTATE_OFF,
3549 },
3550 {
3551 .name = "left_led2:red",
3552 .gpio = GPIO_LEFT_LED_2,
3553 .active_low = 1,
3554 .retain_state_suspended = 0,
3555 .default_state = LEDS_GPIO_DEFSTATE_OFF,
3556 },
3557 {
3558 .name = "left_led3:green",
3559 .gpio = GPIO_LEFT_LED_3,
3560 .active_low = 1,
3561 .retain_state_suspended = 0,
3562 .default_state = LEDS_GPIO_DEFSTATE_OFF,
3563 },
3564 {
3565 .name = "wlan_led:orange",
3566 .gpio = GPIO_LEFT_LED_WLAN,
3567 .active_low = 1,
3568 .retain_state_suspended = 0,
3569 .default_state = LEDS_GPIO_DEFSTATE_OFF,
3570 },
3571 {
3572 .name = "left_led5:green",
3573 .gpio = GPIO_LEFT_LED_5,
3574 .active_low = 1,
3575 .retain_state_suspended = 0,
3576 .default_state = LEDS_GPIO_DEFSTATE_OFF,
3577 },
3578 {
3579 .name = "right_led1:green",
3580 .gpio = GPIO_RIGHT_LED_1,
3581 .active_low = 1,
3582 .retain_state_suspended = 0,
3583 .default_state = LEDS_GPIO_DEFSTATE_OFF,
3584 },
3585 {
3586 .name = "right_led2:red",
3587 .gpio = GPIO_RIGHT_LED_2,
3588 .active_low = 1,
3589 .retain_state_suspended = 0,
3590 .default_state = LEDS_GPIO_DEFSTATE_OFF,
3591 },
3592 {
3593 .name = "right_led3:green",
3594 .gpio = GPIO_RIGHT_LED_3,
3595 .active_low = 1,
3596 .retain_state_suspended = 0,
3597 .default_state = LEDS_GPIO_DEFSTATE_OFF,
3598 },
3599 {
3600 .name = "bt_led:blue",
3601 .gpio = GPIO_RIGHT_LED_BT,
3602 .active_low = 1,
3603 .retain_state_suspended = 0,
3604 .default_state = LEDS_GPIO_DEFSTATE_OFF,
3605 },
3606 {
3607 .name = "right_led5:green",
3608 .gpio = GPIO_RIGHT_LED_5,
3609 .active_low = 1,
3610 .retain_state_suspended = 0,
3611 .default_state = LEDS_GPIO_DEFSTATE_OFF,
3612 },
3613};
3614
3615static struct gpio_led_platform_data gpio_leds_pdata = {
3616 .num_leds = ARRAY_SIZE(gpio_exp_leds_config),
3617 .leds = gpio_exp_leds_config,
3618};
3619
3620static struct platform_device gpio_leds = {
3621 .name = "leds-gpio",
3622 .id = -1,
3623 .dev = {
3624 .platform_data = &gpio_leds_pdata,
3625 },
3626};
3627
3628static struct gpio_led fluid_gpio_leds[] = {
3629 {
3630 .name = "dual_led:green",
3631 .gpio = GPIO_LED1_GREEN_N,
3632 .default_state = LEDS_GPIO_DEFSTATE_OFF,
3633 .active_low = 1,
3634 .retain_state_suspended = 0,
3635 },
3636 {
3637 .name = "dual_led:red",
3638 .gpio = GPIO_LED2_RED_N,
3639 .default_state = LEDS_GPIO_DEFSTATE_OFF,
3640 .active_low = 1,
3641 .retain_state_suspended = 0,
3642 },
3643};
3644
3645static struct gpio_led_platform_data gpio_led_pdata = {
3646 .leds = fluid_gpio_leds,
3647 .num_leds = ARRAY_SIZE(fluid_gpio_leds),
3648};
3649
3650static struct platform_device fluid_leds_gpio = {
3651 .name = "leds-gpio",
3652 .id = -1,
3653 .dev = {
3654 .platform_data = &gpio_led_pdata,
3655 },
3656};
3657
3658#endif
3659
3660#if defined(CONFIG_MSM_RPM_LOG) || defined(CONFIG_MSM_RPM_LOG_MODULE)
3661
3662static struct msm_rpm_log_platform_data msm_rpm_log_pdata = {
3663 .phys_addr_base = 0x00106000,
3664 .reg_offsets = {
3665 [MSM_RPM_LOG_PAGE_INDICES] = 0x00000C80,
3666 [MSM_RPM_LOG_PAGE_BUFFER] = 0x00000CA0,
3667 },
3668 .phys_size = SZ_8K,
3669 .log_len = 4096, /* log's buffer length in bytes */
3670 .log_len_mask = (4096 >> 2) - 1, /* length mask in units of u32 */
3671};
3672
3673static struct platform_device msm_rpm_log_device = {
3674 .name = "msm_rpm_log",
3675 .id = -1,
3676 .dev = {
3677 .platform_data = &msm_rpm_log_pdata,
3678 },
3679};
3680#endif
3681
3682#ifdef CONFIG_BATTERY_MSM8X60
3683static struct msm_charger_platform_data msm_charger_data = {
3684 .safety_time = 180,
3685 .update_time = 1,
3686 .max_voltage = 4200,
3687 .min_voltage = 3200,
3688};
3689
3690static struct platform_device msm_charger_device = {
3691 .name = "msm-charger",
3692 .id = -1,
3693 .dev = {
3694 .platform_data = &msm_charger_data,
3695 }
3696};
3697#endif
3698
3699/*
3700 * Consumer specific regulator names:
3701 * regulator name consumer dev_name
3702 */
3703static struct regulator_consumer_supply vreg_consumers_PM8058_L0[] = {
3704 REGULATOR_SUPPLY("8058_l0", NULL),
3705};
3706static struct regulator_consumer_supply vreg_consumers_PM8058_L1[] = {
3707 REGULATOR_SUPPLY("8058_l1", NULL),
3708};
3709static struct regulator_consumer_supply vreg_consumers_PM8058_L2[] = {
3710 REGULATOR_SUPPLY("8058_l2", NULL),
3711};
3712static struct regulator_consumer_supply vreg_consumers_PM8058_L3[] = {
3713 REGULATOR_SUPPLY("8058_l3", NULL),
3714};
3715static struct regulator_consumer_supply vreg_consumers_PM8058_L4[] = {
3716 REGULATOR_SUPPLY("8058_l4", NULL),
3717};
3718static struct regulator_consumer_supply vreg_consumers_PM8058_L5[] = {
3719 REGULATOR_SUPPLY("8058_l5", NULL),
3720};
3721static struct regulator_consumer_supply vreg_consumers_PM8058_L6[] = {
3722 REGULATOR_SUPPLY("8058_l6", NULL),
3723};
3724static struct regulator_consumer_supply vreg_consumers_PM8058_L7[] = {
3725 REGULATOR_SUPPLY("8058_l7", NULL),
3726};
3727static struct regulator_consumer_supply vreg_consumers_PM8058_L8[] = {
3728 REGULATOR_SUPPLY("8058_l8", NULL),
3729};
3730static struct regulator_consumer_supply vreg_consumers_PM8058_L9[] = {
3731 REGULATOR_SUPPLY("8058_l9", NULL),
3732};
3733static struct regulator_consumer_supply vreg_consumers_PM8058_L10[] = {
3734 REGULATOR_SUPPLY("8058_l10", NULL),
3735};
3736static struct regulator_consumer_supply vreg_consumers_PM8058_L11[] = {
3737 REGULATOR_SUPPLY("8058_l11", NULL),
3738};
3739static struct regulator_consumer_supply vreg_consumers_PM8058_L12[] = {
3740 REGULATOR_SUPPLY("8058_l12", NULL),
3741};
3742static struct regulator_consumer_supply vreg_consumers_PM8058_L13[] = {
3743 REGULATOR_SUPPLY("8058_l13", NULL),
3744};
3745static struct regulator_consumer_supply vreg_consumers_PM8058_L14[] = {
3746 REGULATOR_SUPPLY("8058_l14", NULL),
3747};
3748static struct regulator_consumer_supply vreg_consumers_PM8058_L15[] = {
3749 REGULATOR_SUPPLY("8058_l15", NULL),
3750};
3751static struct regulator_consumer_supply vreg_consumers_PM8058_L16[] = {
3752 REGULATOR_SUPPLY("8058_l16", NULL),
3753};
3754static struct regulator_consumer_supply vreg_consumers_PM8058_L17[] = {
3755 REGULATOR_SUPPLY("8058_l17", NULL),
3756};
3757static struct regulator_consumer_supply vreg_consumers_PM8058_L18[] = {
3758 REGULATOR_SUPPLY("8058_l18", NULL),
3759};
3760static struct regulator_consumer_supply vreg_consumers_PM8058_L19[] = {
3761 REGULATOR_SUPPLY("8058_l19", NULL),
3762};
3763static struct regulator_consumer_supply vreg_consumers_PM8058_L20[] = {
3764 REGULATOR_SUPPLY("8058_l20", NULL),
3765};
3766static struct regulator_consumer_supply vreg_consumers_PM8058_L21[] = {
3767 REGULATOR_SUPPLY("8058_l21", NULL),
3768};
3769static struct regulator_consumer_supply vreg_consumers_PM8058_L22[] = {
3770 REGULATOR_SUPPLY("8058_l22", NULL),
3771};
3772static struct regulator_consumer_supply vreg_consumers_PM8058_L23[] = {
3773 REGULATOR_SUPPLY("8058_l23", NULL),
3774};
3775static struct regulator_consumer_supply vreg_consumers_PM8058_L24[] = {
3776 REGULATOR_SUPPLY("8058_l24", NULL),
3777};
3778static struct regulator_consumer_supply vreg_consumers_PM8058_L25[] = {
3779 REGULATOR_SUPPLY("8058_l25", NULL),
3780};
3781static struct regulator_consumer_supply vreg_consumers_PM8058_S0[] = {
3782 REGULATOR_SUPPLY("8058_s0", NULL),
3783};
3784static struct regulator_consumer_supply vreg_consumers_PM8058_S1[] = {
3785 REGULATOR_SUPPLY("8058_s1", NULL),
3786};
3787static struct regulator_consumer_supply vreg_consumers_PM8058_S2[] = {
3788 REGULATOR_SUPPLY("8058_s2", NULL),
3789};
3790static struct regulator_consumer_supply vreg_consumers_PM8058_S3[] = {
3791 REGULATOR_SUPPLY("8058_s3", NULL),
3792};
3793static struct regulator_consumer_supply vreg_consumers_PM8058_S4[] = {
3794 REGULATOR_SUPPLY("8058_s4", NULL),
3795};
3796static struct regulator_consumer_supply vreg_consumers_PM8058_LVS0[] = {
3797 REGULATOR_SUPPLY("8058_lvs0", NULL),
3798};
3799static struct regulator_consumer_supply vreg_consumers_PM8058_LVS1[] = {
3800 REGULATOR_SUPPLY("8058_lvs1", NULL),
3801};
3802static struct regulator_consumer_supply vreg_consumers_PM8058_NCP[] = {
3803 REGULATOR_SUPPLY("8058_ncp", NULL),
3804};
3805
3806static struct regulator_consumer_supply vreg_consumers_PM8901_L0[] = {
3807 REGULATOR_SUPPLY("8901_l0", NULL),
3808};
3809static struct regulator_consumer_supply vreg_consumers_PM8901_L1[] = {
3810 REGULATOR_SUPPLY("8901_l1", NULL),
3811};
3812static struct regulator_consumer_supply vreg_consumers_PM8901_L2[] = {
3813 REGULATOR_SUPPLY("8901_l2", NULL),
3814};
3815static struct regulator_consumer_supply vreg_consumers_PM8901_L3[] = {
3816 REGULATOR_SUPPLY("8901_l3", NULL),
3817};
3818static struct regulator_consumer_supply vreg_consumers_PM8901_L4[] = {
3819 REGULATOR_SUPPLY("8901_l4", NULL),
3820};
3821static struct regulator_consumer_supply vreg_consumers_PM8901_L5[] = {
3822 REGULATOR_SUPPLY("8901_l5", NULL),
3823};
3824static struct regulator_consumer_supply vreg_consumers_PM8901_L6[] = {
3825 REGULATOR_SUPPLY("8901_l6", NULL),
3826};
3827static struct regulator_consumer_supply vreg_consumers_PM8901_S2[] = {
3828 REGULATOR_SUPPLY("8901_s2", NULL),
3829};
3830static struct regulator_consumer_supply vreg_consumers_PM8901_S3[] = {
3831 REGULATOR_SUPPLY("8901_s3", NULL),
3832};
3833static struct regulator_consumer_supply vreg_consumers_PM8901_S4[] = {
3834 REGULATOR_SUPPLY("8901_s4", NULL),
3835};
3836static struct regulator_consumer_supply vreg_consumers_PM8901_LVS0[] = {
3837 REGULATOR_SUPPLY("8901_lvs0", NULL),
3838};
3839static struct regulator_consumer_supply vreg_consumers_PM8901_LVS1[] = {
3840 REGULATOR_SUPPLY("8901_lvs1", NULL),
3841};
3842static struct regulator_consumer_supply vreg_consumers_PM8901_LVS2[] = {
3843 REGULATOR_SUPPLY("8901_lvs2", NULL),
3844};
3845static struct regulator_consumer_supply vreg_consumers_PM8901_LVS3[] = {
3846 REGULATOR_SUPPLY("8901_lvs3", NULL),
3847};
3848static struct regulator_consumer_supply vreg_consumers_PM8901_MVS0[] = {
3849 REGULATOR_SUPPLY("8901_mvs0", NULL),
3850};
3851
David Collins6f032ba2011-08-31 14:08:15 -07003852/* Pin control regulators */
3853static struct regulator_consumer_supply vreg_consumers_PM8058_L8_PC[] = {
3854 REGULATOR_SUPPLY("8058_l8_pc", NULL),
3855};
3856static struct regulator_consumer_supply vreg_consumers_PM8058_L20_PC[] = {
3857 REGULATOR_SUPPLY("8058_l20_pc", NULL),
3858};
3859static struct regulator_consumer_supply vreg_consumers_PM8058_L21_PC[] = {
3860 REGULATOR_SUPPLY("8058_l21_pc", NULL),
3861};
3862static struct regulator_consumer_supply vreg_consumers_PM8058_S2_PC[] = {
3863 REGULATOR_SUPPLY("8058_s2_pc", NULL),
3864};
3865static struct regulator_consumer_supply vreg_consumers_PM8901_L0_PC[] = {
3866 REGULATOR_SUPPLY("8901_l0_pc", NULL),
3867};
3868static struct regulator_consumer_supply vreg_consumers_PM8901_S4_PC[] = {
3869 REGULATOR_SUPPLY("8901_s4_pc", NULL),
3870};
3871
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003872#define RPM_VREG_INIT(_id, _min_uV, _max_uV, _modes, _ops, _apply_uV, \
3873 _default_uV, _peak_uA, _avg_uA, _pull_down, _pin_ctrl, \
David Collins6f032ba2011-08-31 14:08:15 -07003874 _freq, _pin_fn, _force_mode, _state, _sleep_selectable, \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003875 _always_on) \
David Collins6f032ba2011-08-31 14:08:15 -07003876 { \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003877 .init_data = { \
3878 .constraints = { \
David Collins6f032ba2011-08-31 14:08:15 -07003879 .valid_modes_mask = _modes, \
3880 .valid_ops_mask = _ops, \
3881 .min_uV = _min_uV, \
3882 .max_uV = _max_uV, \
3883 .input_uV = _min_uV, \
3884 .apply_uV = _apply_uV, \
3885 .always_on = _always_on, \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003886 }, \
David Collins6f032ba2011-08-31 14:08:15 -07003887 .consumer_supplies = vreg_consumers_##_id, \
3888 .num_consumer_supplies = \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003889 ARRAY_SIZE(vreg_consumers_##_id), \
3890 }, \
David Collins6f032ba2011-08-31 14:08:15 -07003891 .id = RPM_VREG_ID_##_id, \
3892 .default_uV = _default_uV, \
3893 .peak_uA = _peak_uA, \
3894 .avg_uA = _avg_uA, \
3895 .pull_down_enable = _pull_down, \
3896 .pin_ctrl = _pin_ctrl, \
3897 .freq = RPM_VREG_FREQ_##_freq, \
3898 .pin_fn = _pin_fn, \
3899 .force_mode = _force_mode, \
3900 .state = _state, \
3901 .sleep_selectable = _sleep_selectable, \
3902 }
3903
3904/* Pin control initialization */
3905#define RPM_PC(_id, _always_on, _pin_fn, _pin_ctrl) \
3906 { \
3907 .init_data = { \
3908 .constraints = { \
3909 .valid_ops_mask = REGULATOR_CHANGE_STATUS, \
3910 .always_on = _always_on, \
3911 }, \
3912 .num_consumer_supplies = \
3913 ARRAY_SIZE(vreg_consumers_##_id##_PC), \
3914 .consumer_supplies = vreg_consumers_##_id##_PC, \
3915 }, \
3916 .id = RPM_VREG_ID_##_id##_PC, \
3917 .pin_fn = RPM_VREG_PIN_FN_8660_##_pin_fn, \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003918 .pin_ctrl = _pin_ctrl, \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003919 }
3920
3921/*
3922 * The default LPM/HPM state of an RPM controlled regulator can be controlled
3923 * via the peak_uA value specified in the table below. If the value is less
3924 * than the high power min threshold for the regulator, then the regulator will
3925 * be set to LPM. Otherwise, it will be set to HPM.
3926 *
3927 * This value can be further overridden by specifying an initial mode via
3928 * .init_data.constraints.initial_mode.
3929 */
3930
David Collins6f032ba2011-08-31 14:08:15 -07003931#define RPM_LDO(_id, _always_on, _pd, _sleep_selectable, _min_uV, _max_uV, \
3932 _init_peak_uA) \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003933 RPM_VREG_INIT(_id, _min_uV, _max_uV, REGULATOR_MODE_FAST | \
3934 REGULATOR_MODE_NORMAL | REGULATOR_MODE_IDLE | \
3935 REGULATOR_MODE_STANDBY, REGULATOR_CHANGE_VOLTAGE | \
3936 REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_MODE | \
3937 REGULATOR_CHANGE_DRMS, 0, _min_uV, _init_peak_uA, \
David Collins6f032ba2011-08-31 14:08:15 -07003938 _init_peak_uA, _pd, RPM_VREG_PIN_CTRL_NONE, NONE, \
3939 RPM_VREG_PIN_FN_8660_ENABLE, \
3940 RPM_VREG_FORCE_MODE_8660_NONE, RPM_VREG_STATE_OFF, \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003941 _sleep_selectable, _always_on)
3942
David Collins6f032ba2011-08-31 14:08:15 -07003943#define RPM_SMPS(_id, _always_on, _pd, _sleep_selectable, _min_uV, _max_uV, \
3944 _init_peak_uA, _freq) \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003945 RPM_VREG_INIT(_id, _min_uV, _max_uV, REGULATOR_MODE_FAST | \
3946 REGULATOR_MODE_NORMAL | REGULATOR_MODE_IDLE | \
3947 REGULATOR_MODE_STANDBY, REGULATOR_CHANGE_VOLTAGE | \
3948 REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_MODE | \
3949 REGULATOR_CHANGE_DRMS, 0, _min_uV, _init_peak_uA, \
David Collins6f032ba2011-08-31 14:08:15 -07003950 _init_peak_uA, _pd, RPM_VREG_PIN_CTRL_NONE, _freq, \
3951 RPM_VREG_PIN_FN_8660_ENABLE, \
3952 RPM_VREG_FORCE_MODE_8660_NONE, RPM_VREG_STATE_OFF, \
3953 _sleep_selectable, _always_on)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003954
David Collins6f032ba2011-08-31 14:08:15 -07003955#define RPM_VS(_id, _always_on, _pd, _sleep_selectable) \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003956 RPM_VREG_INIT(_id, 0, 0, REGULATOR_MODE_NORMAL | REGULATOR_MODE_IDLE, \
3957 REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_MODE, 0, 0, \
David Collins6f032ba2011-08-31 14:08:15 -07003958 1000, 1000, _pd, RPM_VREG_PIN_CTRL_NONE, NONE, \
3959 RPM_VREG_PIN_FN_8660_ENABLE, \
3960 RPM_VREG_FORCE_MODE_8660_NONE, RPM_VREG_STATE_OFF, \
3961 _sleep_selectable, _always_on)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003962
David Collins6f032ba2011-08-31 14:08:15 -07003963#define RPM_NCP(_id, _always_on, _pd, _sleep_selectable, _min_uV, _max_uV) \
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003964 RPM_VREG_INIT(_id, _min_uV, _max_uV, REGULATOR_MODE_NORMAL, \
3965 REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS, 0, \
David Collins6f032ba2011-08-31 14:08:15 -07003966 _min_uV, 1000, 1000, _pd, RPM_VREG_PIN_CTRL_NONE, NONE, \
3967 RPM_VREG_PIN_FN_8660_ENABLE, \
3968 RPM_VREG_FORCE_MODE_8660_NONE, RPM_VREG_STATE_OFF, \
3969 _sleep_selectable, _always_on)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003970
David Collins6f032ba2011-08-31 14:08:15 -07003971#define LDO50HMIN RPM_VREG_8660_LDO_50_HPM_MIN_LOAD
3972#define LDO150HMIN RPM_VREG_8660_LDO_150_HPM_MIN_LOAD
3973#define LDO300HMIN RPM_VREG_8660_LDO_300_HPM_MIN_LOAD
3974#define SMPS_HMIN RPM_VREG_8660_SMPS_HPM_MIN_LOAD
3975#define FTS_HMIN RPM_VREG_8660_FTSMPS_HPM_MIN_LOAD
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003976
David Collins6f032ba2011-08-31 14:08:15 -07003977/* RPM early regulator constraints */
3978static struct rpm_regulator_init_data rpm_regulator_early_init_data[] = {
3979 /* ID a_on pd ss min_uV max_uV init_ip freq */
3980 RPM_SMPS(PM8058_S0, 0, 1, 1, 500000, 1250000, SMPS_HMIN, 1p60),
3981 RPM_SMPS(PM8058_S1, 0, 1, 1, 500000, 1250000, SMPS_HMIN, 1p60),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07003982};
3983
David Collins6f032ba2011-08-31 14:08:15 -07003984/* RPM regulator constraints */
3985static struct rpm_regulator_init_data rpm_regulator_init_data[] = {
3986 /* ID a_on pd ss min_uV max_uV init_ip */
3987 RPM_LDO(PM8058_L0, 0, 1, 0, 1200000, 1200000, LDO150HMIN),
3988 RPM_LDO(PM8058_L1, 0, 1, 0, 1200000, 1200000, LDO300HMIN),
3989 RPM_LDO(PM8058_L2, 0, 1, 0, 1800000, 2600000, LDO300HMIN),
3990 RPM_LDO(PM8058_L3, 0, 1, 0, 1800000, 1800000, LDO150HMIN),
3991 RPM_LDO(PM8058_L4, 0, 1, 0, 2850000, 2850000, LDO50HMIN),
3992 RPM_LDO(PM8058_L5, 0, 1, 0, 2850000, 2850000, LDO300HMIN),
3993 RPM_LDO(PM8058_L6, 0, 1, 0, 3000000, 3600000, LDO50HMIN),
3994 RPM_LDO(PM8058_L7, 0, 1, 0, 1800000, 1800000, LDO50HMIN),
3995 RPM_LDO(PM8058_L8, 0, 1, 0, 2900000, 3050000, LDO300HMIN),
3996 RPM_LDO(PM8058_L9, 0, 1, 0, 1800000, 1800000, LDO300HMIN),
3997 RPM_LDO(PM8058_L10, 0, 1, 0, 2600000, 2600000, LDO300HMIN),
3998 RPM_LDO(PM8058_L11, 0, 1, 0, 1500000, 1500000, LDO150HMIN),
3999 RPM_LDO(PM8058_L12, 0, 1, 0, 2900000, 2900000, LDO150HMIN),
4000 RPM_LDO(PM8058_L13, 0, 1, 0, 2050000, 2050000, LDO300HMIN),
4001 RPM_LDO(PM8058_L14, 0, 0, 0, 2850000, 2850000, LDO300HMIN),
4002 RPM_LDO(PM8058_L15, 0, 1, 0, 2850000, 2850000, LDO300HMIN),
4003 RPM_LDO(PM8058_L16, 1, 1, 0, 1800000, 1800000, LDO300HMIN),
4004 RPM_LDO(PM8058_L17, 0, 1, 0, 2600000, 2600000, LDO150HMIN),
4005 RPM_LDO(PM8058_L18, 0, 1, 0, 2200000, 2200000, LDO150HMIN),
4006 RPM_LDO(PM8058_L19, 0, 1, 0, 2500000, 2500000, LDO150HMIN),
4007 RPM_LDO(PM8058_L20, 0, 1, 0, 1800000, 1800000, LDO150HMIN),
4008 RPM_LDO(PM8058_L21, 1, 1, 0, 1200000, 1200000, LDO150HMIN),
4009 RPM_LDO(PM8058_L22, 0, 1, 0, 1150000, 1150000, LDO300HMIN),
4010 RPM_LDO(PM8058_L23, 0, 1, 0, 1200000, 1200000, LDO300HMIN),
4011 RPM_LDO(PM8058_L24, 0, 1, 0, 1200000, 1200000, LDO150HMIN),
4012 RPM_LDO(PM8058_L25, 0, 1, 0, 1200000, 1200000, LDO150HMIN),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004013
David Collins6f032ba2011-08-31 14:08:15 -07004014 /* ID a_on pd ss min_uV max_uV init_ip freq */
4015 RPM_SMPS(PM8058_S2, 0, 1, 1, 1200000, 1400000, SMPS_HMIN, 1p60),
4016 RPM_SMPS(PM8058_S3, 1, 1, 0, 1800000, 1800000, SMPS_HMIN, 1p60),
4017 RPM_SMPS(PM8058_S4, 1, 1, 0, 2200000, 2200000, SMPS_HMIN, 1p60),
4018
4019 /* ID a_on pd ss */
4020 RPM_VS(PM8058_LVS0, 0, 1, 0),
4021 RPM_VS(PM8058_LVS1, 0, 1, 0),
4022
4023 /* ID a_on pd ss min_uV max_uV */
4024 RPM_NCP(PM8058_NCP, 0, 1, 0, 1800000, 1800000),
4025
4026 /* ID a_on pd ss min_uV max_uV init_ip */
4027 RPM_LDO(PM8901_L0, 0, 1, 0, 1200000, 1200000, LDO300HMIN),
4028 RPM_LDO(PM8901_L1, 0, 1, 0, 3300000, 3300000, LDO300HMIN),
4029 RPM_LDO(PM8901_L2, 0, 1, 0, 2850000, 3300000, LDO300HMIN),
4030 RPM_LDO(PM8901_L3, 0, 1, 0, 3300000, 3300000, LDO300HMIN),
4031 RPM_LDO(PM8901_L4, 0, 1, 0, 2600000, 2600000, LDO300HMIN),
4032 RPM_LDO(PM8901_L5, 0, 1, 0, 2850000, 2850000, LDO300HMIN),
4033 RPM_LDO(PM8901_L6, 0, 1, 0, 2200000, 2200000, LDO300HMIN),
4034
4035 /* ID a_on pd ss min_uV max_uV init_ip freq */
4036 RPM_SMPS(PM8901_S2, 0, 1, 0, 1300000, 1300000, FTS_HMIN, 1p60),
4037 RPM_SMPS(PM8901_S3, 0, 1, 0, 1100000, 1100000, FTS_HMIN, 1p60),
4038 RPM_SMPS(PM8901_S4, 0, 1, 0, 1225000, 1225000, FTS_HMIN, 1p60),
4039
4040 /* ID a_on pd ss */
4041 RPM_VS(PM8901_LVS0, 1, 1, 0),
4042 RPM_VS(PM8901_LVS1, 0, 1, 0),
4043 RPM_VS(PM8901_LVS2, 0, 1, 0),
4044 RPM_VS(PM8901_LVS3, 0, 1, 0),
4045 RPM_VS(PM8901_MVS0, 0, 1, 0),
4046
4047 /* ID a_on pin_func pin_ctrl */
4048 RPM_PC(PM8058_L8, 0, SLEEP_B, RPM_VREG_PIN_CTRL_NONE),
4049 RPM_PC(PM8058_L20, 0, SLEEP_B, RPM_VREG_PIN_CTRL_NONE),
4050 RPM_PC(PM8058_L21, 1, SLEEP_B, RPM_VREG_PIN_CTRL_NONE),
4051 RPM_PC(PM8058_S2, 0, ENABLE, RPM_VREG_PIN_CTRL_PM8058_A0),
4052 RPM_PC(PM8901_L0, 0, ENABLE, RPM_VREG_PIN_CTRL_PM8901_A0),
4053 RPM_PC(PM8901_S4, 0, ENABLE, RPM_VREG_PIN_CTRL_PM8901_A0),
4054};
4055
4056static struct rpm_regulator_platform_data rpm_regulator_early_pdata = {
4057 .init_data = rpm_regulator_early_init_data,
4058 .num_regulators = ARRAY_SIZE(rpm_regulator_early_init_data),
4059 .version = RPM_VREG_VERSION_8660,
4060 .vreg_id_vdd_mem = RPM_VREG_ID_PM8058_S0,
4061 .vreg_id_vdd_dig = RPM_VREG_ID_PM8058_S1,
4062};
4063
4064static struct rpm_regulator_platform_data rpm_regulator_pdata = {
4065 .init_data = rpm_regulator_init_data,
4066 .num_regulators = ARRAY_SIZE(rpm_regulator_init_data),
4067 .version = RPM_VREG_VERSION_8660,
4068};
4069
4070static struct platform_device rpm_regulator_early_device = {
4071 .name = "rpm-regulator",
4072 .id = 0,
4073 .dev = {
4074 .platform_data = &rpm_regulator_early_pdata,
4075 },
4076};
4077
4078static struct platform_device rpm_regulator_device = {
4079 .name = "rpm-regulator",
4080 .id = 1,
4081 .dev = {
4082 .platform_data = &rpm_regulator_pdata,
4083 },
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004084};
4085
4086static struct platform_device *early_regulators[] __initdata = {
4087 &msm_device_saw_s0,
4088 &msm_device_saw_s1,
David Collins6f032ba2011-08-31 14:08:15 -07004089 &rpm_regulator_early_device,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004090};
4091
4092static struct platform_device *early_devices[] __initdata = {
4093#ifdef CONFIG_MSM_BUS_SCALING
4094 &msm_bus_apps_fabric,
4095 &msm_bus_sys_fabric,
4096 &msm_bus_mm_fabric,
4097 &msm_bus_sys_fpb,
4098 &msm_bus_cpss_fpb,
4099#endif
4100 &msm_device_dmov_adm0,
4101 &msm_device_dmov_adm1,
4102};
4103
4104#if (defined(CONFIG_MARIMBA_CORE)) && \
4105 (defined(CONFIG_MSM_BT_POWER) || defined(CONFIG_MSM_BT_POWER_MODULE))
4106
4107static int bluetooth_power(int);
4108static struct platform_device msm_bt_power_device = {
4109 .name = "bt_power",
4110 .id = -1,
4111 .dev = {
4112 .platform_data = &bluetooth_power,
4113 },
4114};
4115#endif
4116
4117static struct platform_device msm_tsens_device = {
4118 .name = "tsens-tm",
4119 .id = -1,
4120};
4121
4122static struct platform_device *rumi_sim_devices[] __initdata = {
4123 &smc91x_device,
4124 &msm_device_uart_dm12,
4125#ifdef CONFIG_I2C_QUP
4126 &msm_gsbi3_qup_i2c_device,
4127 &msm_gsbi4_qup_i2c_device,
4128 &msm_gsbi7_qup_i2c_device,
4129 &msm_gsbi8_qup_i2c_device,
4130 &msm_gsbi9_qup_i2c_device,
4131 &msm_gsbi12_qup_i2c_device,
4132#endif
4133#ifdef CONFIG_I2C_SSBI
4134 &msm_device_ssbi1,
4135 &msm_device_ssbi2,
4136 &msm_device_ssbi3,
4137#endif
4138#ifdef CONFIG_ANDROID_PMEM
4139 &android_pmem_device,
4140 &android_pmem_adsp_device,
4141 &android_pmem_audio_device,
4142 &android_pmem_smipool_device,
4143#endif
4144#ifdef CONFIG_MSM_ROTATOR
4145 &msm_rotator_device,
4146#endif
4147 &msm_fb_device,
4148 &msm_kgsl_3d0,
4149 &msm_kgsl_2d0,
4150 &msm_kgsl_2d1,
4151 &lcdc_samsung_panel_device,
4152#ifdef CONFIG_FB_MSM_HDMI_MSM_PANEL
4153 &hdmi_msm_device,
4154#endif /* CONFIG_FB_MSM_HDMI_MSM_PANEL */
4155#ifdef CONFIG_MSM_CAMERA
4156#ifdef CONFIG_MT9E013
4157 &msm_camera_sensor_mt9e013,
4158#endif
4159#ifdef CONFIG_IMX074
4160 &msm_camera_sensor_imx074,
4161#endif
Jilai Wang971f97f2011-07-13 14:25:25 -04004162#ifdef CONFIG_VX6953
4163 &msm_camera_sensor_vx6953,
4164#endif
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004165#ifdef CONFIG_WEBCAM_OV7692
4166 &msm_camera_sensor_webcam_ov7692,
4167#endif
4168#ifdef CONFIG_WEBCAM_OV9726
4169 &msm_camera_sensor_webcam_ov9726,
4170#endif
4171#ifdef CONFIG_QS_S5K4E1
4172 &msm_camera_sensor_qs_s5k4e1,
4173#endif
4174#endif
4175#ifdef CONFIG_MSM_GEMINI
4176 &msm_gemini_device,
4177#endif
4178#ifdef CONFIG_MSM_VPE
4179 &msm_vpe_device,
4180#endif
4181 &msm_device_vidc,
4182};
4183
4184#if defined(CONFIG_GPIO_SX150X) || defined(CONFIG_GPIO_SX150X_MODULE)
4185enum {
4186 SX150X_CORE,
4187 SX150X_DOCKING,
4188 SX150X_SURF,
4189 SX150X_LEFT_FHA,
4190 SX150X_RIGHT_FHA,
4191 SX150X_SOUTH,
4192 SX150X_NORTH,
4193 SX150X_CORE_FLUID,
4194};
4195
4196static struct sx150x_platform_data sx150x_data[] __initdata = {
4197 [SX150X_CORE] = {
4198 .gpio_base = GPIO_CORE_EXPANDER_BASE,
4199 .oscio_is_gpo = false,
4200 .io_pullup_ena = 0x0c08,
4201 .io_pulldn_ena = 0x4060,
4202 .io_open_drain_ena = 0x000c,
4203 .io_polarity = 0,
4204 .irq_summary = -1, /* see fixup_i2c_configs() */
4205 .irq_base = GPIO_EXPANDER_IRQ_BASE,
4206 },
4207 [SX150X_DOCKING] = {
4208 .gpio_base = GPIO_DOCKING_EXPANDER_BASE,
4209 .oscio_is_gpo = false,
4210 .io_pullup_ena = 0x5e06,
4211 .io_pulldn_ena = 0x81b8,
4212 .io_open_drain_ena = 0,
4213 .io_polarity = 0,
4214 .irq_summary = PM8058_GPIO_IRQ(PM8058_IRQ_BASE,
4215 UI_INT2_N),
4216 .irq_base = GPIO_EXPANDER_IRQ_BASE +
4217 GPIO_DOCKING_EXPANDER_BASE -
4218 GPIO_EXPANDER_GPIO_BASE,
4219 },
4220 [SX150X_SURF] = {
4221 .gpio_base = GPIO_SURF_EXPANDER_BASE,
4222 .oscio_is_gpo = false,
4223 .io_pullup_ena = 0,
4224 .io_pulldn_ena = 0,
4225 .io_open_drain_ena = 0,
4226 .io_polarity = 0,
4227 .irq_summary = PM8058_GPIO_IRQ(PM8058_IRQ_BASE,
4228 UI_INT1_N),
4229 .irq_base = GPIO_EXPANDER_IRQ_BASE +
4230 GPIO_SURF_EXPANDER_BASE -
4231 GPIO_EXPANDER_GPIO_BASE,
4232 },
4233 [SX150X_LEFT_FHA] = {
4234 .gpio_base = GPIO_LEFT_KB_EXPANDER_BASE,
4235 .oscio_is_gpo = false,
4236 .io_pullup_ena = 0,
4237 .io_pulldn_ena = 0x40,
4238 .io_open_drain_ena = 0,
4239 .io_polarity = 0,
4240 .irq_summary = PM8058_GPIO_IRQ(PM8058_IRQ_BASE,
4241 UI_INT3_N),
4242 .irq_base = GPIO_EXPANDER_IRQ_BASE +
4243 GPIO_LEFT_KB_EXPANDER_BASE -
4244 GPIO_EXPANDER_GPIO_BASE,
4245 },
4246 [SX150X_RIGHT_FHA] = {
4247 .gpio_base = GPIO_RIGHT_KB_EXPANDER_BASE,
4248 .oscio_is_gpo = true,
4249 .io_pullup_ena = 0,
4250 .io_pulldn_ena = 0,
4251 .io_open_drain_ena = 0,
4252 .io_polarity = 0,
4253 .irq_summary = PM8058_GPIO_IRQ(PM8058_IRQ_BASE,
4254 UI_INT3_N),
4255 .irq_base = GPIO_EXPANDER_IRQ_BASE +
4256 GPIO_RIGHT_KB_EXPANDER_BASE -
4257 GPIO_EXPANDER_GPIO_BASE,
4258 },
4259 [SX150X_SOUTH] = {
4260 .gpio_base = GPIO_SOUTH_EXPANDER_BASE,
4261 .irq_base = GPIO_EXPANDER_IRQ_BASE +
4262 GPIO_SOUTH_EXPANDER_BASE -
4263 GPIO_EXPANDER_GPIO_BASE,
4264 .irq_summary = PM8058_GPIO_IRQ(PM8058_IRQ_BASE, UI_INT3_N),
4265 },
4266 [SX150X_NORTH] = {
4267 .gpio_base = GPIO_NORTH_EXPANDER_BASE,
4268 .irq_base = GPIO_EXPANDER_IRQ_BASE +
4269 GPIO_NORTH_EXPANDER_BASE -
4270 GPIO_EXPANDER_GPIO_BASE,
4271 .irq_summary = PM8058_GPIO_IRQ(PM8058_IRQ_BASE, UI_INT3_N),
4272 .oscio_is_gpo = true,
4273 .io_open_drain_ena = 0x30,
4274 },
4275 [SX150X_CORE_FLUID] = {
4276 .gpio_base = GPIO_CORE_EXPANDER_BASE,
4277 .oscio_is_gpo = false,
4278 .io_pullup_ena = 0x0408,
4279 .io_pulldn_ena = 0x4060,
4280 .io_open_drain_ena = 0x0008,
4281 .io_polarity = 0,
4282 .irq_summary = -1, /* see fixup_i2c_configs() */
4283 .irq_base = GPIO_EXPANDER_IRQ_BASE,
4284 },
4285};
4286
4287#ifdef CONFIG_SENSORS_MSM_ADC
4288/* Configuration of EPM expander is done when client
4289 * request an adc read
4290 */
4291static struct sx150x_platform_data sx150x_epmdata = {
4292 .gpio_base = GPIO_EPM_EXPANDER_BASE,
4293 .irq_base = GPIO_EXPANDER_IRQ_BASE +
4294 GPIO_EPM_EXPANDER_BASE -
4295 GPIO_EXPANDER_GPIO_BASE,
4296 .irq_summary = -1,
4297};
4298#endif
4299
4300/* sx150x_low_power_cfg
4301 *
4302 * This data and init function are used to put unused gpio-expander output
4303 * lines into their low-power states at boot. The init
4304 * function must be deferred until a later init stage because the i2c
4305 * gpio expander drivers do not probe until after they are registered
4306 * (see register_i2c_devices) and the work-queues for those registrations
4307 * are processed. Because these lines are unused, there is no risk of
4308 * competing with a device driver for the gpio.
4309 *
4310 * gpio lines whose low-power states are input are naturally in their low-
4311 * power configurations once probed, see the platform data structures above.
4312 */
4313struct sx150x_low_power_cfg {
4314 unsigned gpio;
4315 unsigned val;
4316};
4317
4318static struct sx150x_low_power_cfg
4319common_sx150x_lp_cfgs[] __initdata = {
4320 {GPIO_WLAN_DEEP_SLEEP_N, 0},
4321 {GPIO_EXT_GPS_LNA_EN, 0},
4322 {GPIO_MSM_WAKES_BT, 0},
4323 {GPIO_USB_UICC_EN, 0},
4324 {GPIO_BATT_GAUGE_EN, 0},
4325};
4326
4327static struct sx150x_low_power_cfg
4328surf_ffa_sx150x_lp_cfgs[] __initdata = {
4329 {GPIO_MIPI_DSI_RST_N, 0},
4330 {GPIO_DONGLE_PWR_EN, 0},
4331 {GPIO_CAP_TS_SLEEP, 1},
4332 {GPIO_WEB_CAMIF_RESET_N, 0},
4333};
4334
4335static void __init
4336cfg_gpio_low_power(struct sx150x_low_power_cfg *cfgs, unsigned nelems)
4337{
4338 unsigned n;
4339 int rc;
4340
4341 for (n = 0; n < nelems; ++n) {
4342 rc = gpio_request(cfgs[n].gpio, NULL);
4343 if (!rc) {
4344 rc = gpio_direction_output(cfgs[n].gpio, cfgs[n].val);
4345 gpio_free(cfgs[n].gpio);
4346 }
4347
4348 if (rc) {
4349 printk(KERN_NOTICE "%s: failed to sleep gpio %d: %d\n",
4350 __func__, cfgs[n].gpio, rc);
4351 }
Steve Muckle9161d302010-02-11 11:50:40 -08004352 }
Steve Mucklea55df6e2010-01-07 12:43:24 -08004353}
4354
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004355static int __init cfg_sx150xs_low_power(void)
Steve Mucklea55df6e2010-01-07 12:43:24 -08004356{
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004357 cfg_gpio_low_power(common_sx150x_lp_cfgs,
4358 ARRAY_SIZE(common_sx150x_lp_cfgs));
4359 if (!machine_is_msm8x60_fluid())
4360 cfg_gpio_low_power(surf_ffa_sx150x_lp_cfgs,
4361 ARRAY_SIZE(surf_ffa_sx150x_lp_cfgs));
4362 return 0;
4363}
4364module_init(cfg_sx150xs_low_power);
4365
4366#ifdef CONFIG_I2C
4367static struct i2c_board_info core_expander_i2c_info[] __initdata = {
4368 {
4369 I2C_BOARD_INFO("sx1509q", 0x3e),
4370 .platform_data = &sx150x_data[SX150X_CORE]
4371 },
4372};
4373
4374static struct i2c_board_info docking_expander_i2c_info[] __initdata = {
4375 {
4376 I2C_BOARD_INFO("sx1509q", 0x3f),
4377 .platform_data = &sx150x_data[SX150X_DOCKING]
4378 },
4379};
4380
4381static struct i2c_board_info surf_expanders_i2c_info[] __initdata = {
4382 {
4383 I2C_BOARD_INFO("sx1509q", 0x70),
4384 .platform_data = &sx150x_data[SX150X_SURF]
4385 }
4386};
4387
4388static struct i2c_board_info fha_expanders_i2c_info[] __initdata = {
4389 {
4390 I2C_BOARD_INFO("sx1508q", 0x21),
4391 .platform_data = &sx150x_data[SX150X_LEFT_FHA]
4392 },
4393 {
4394 I2C_BOARD_INFO("sx1508q", 0x22),
4395 .platform_data = &sx150x_data[SX150X_RIGHT_FHA]
4396 }
4397};
4398
4399static struct i2c_board_info fluid_expanders_i2c_info[] __initdata = {
4400 {
4401 I2C_BOARD_INFO("sx1508q", 0x23),
4402 .platform_data = &sx150x_data[SX150X_SOUTH]
4403 },
4404 {
4405 I2C_BOARD_INFO("sx1508q", 0x20),
4406 .platform_data = &sx150x_data[SX150X_NORTH]
4407 }
4408};
4409
4410static struct i2c_board_info fluid_core_expander_i2c_info[] __initdata = {
4411 {
4412 I2C_BOARD_INFO("sx1509q", 0x3e),
4413 .platform_data = &sx150x_data[SX150X_CORE_FLUID]
4414 },
4415};
4416
4417#ifdef CONFIG_SENSORS_MSM_ADC
4418static struct i2c_board_info fluid_expanders_i2c_epm_info[] = {
4419 {
4420 I2C_BOARD_INFO("sx1509q", 0x3e),
4421 .platform_data = &sx150x_epmdata
4422 },
4423};
4424#endif
4425#endif
4426#endif
4427
4428#ifdef CONFIG_SENSORS_MSM_ADC
4429static struct resource resources_adc[] = {
4430 {
4431 .start = PM8058_ADC_IRQ(PM8058_IRQ_BASE),
4432 .end = PM8058_ADC_IRQ(PM8058_IRQ_BASE),
4433 .flags = IORESOURCE_IRQ,
4434 },
4435};
4436
4437static struct adc_access_fn xoadc_fn = {
4438 pm8058_xoadc_select_chan_and_start_conv,
4439 pm8058_xoadc_read_adc_code,
4440 pm8058_xoadc_get_properties,
4441 pm8058_xoadc_slot_request,
4442 pm8058_xoadc_restore_slot,
4443 pm8058_xoadc_calibrate,
4444};
4445
4446#if defined(CONFIG_I2C) && \
4447 (defined(CONFIG_GPIO_SX150X) || defined(CONFIG_GPIO_SX150X_MODULE))
4448static struct regulator *vreg_adc_epm1;
4449
4450static struct i2c_client *epm_expander_i2c_register_board(void)
4451
4452{
4453 struct i2c_adapter *i2c_adap;
4454 struct i2c_client *client = NULL;
4455 i2c_adap = i2c_get_adapter(0x0);
4456
4457 if (i2c_adap == NULL)
4458 printk(KERN_ERR "\nepm_expander_i2c_adapter is NULL\n");
4459
4460 if (i2c_adap != NULL)
4461 client = i2c_new_device(i2c_adap,
4462 &fluid_expanders_i2c_epm_info[0]);
4463 return client;
4464
4465}
4466
4467static unsigned int msm_adc_gpio_configure_expander_enable(void)
4468{
4469 int rc = 0;
4470 static struct i2c_client *epm_i2c_client;
4471
4472 printk(KERN_DEBUG "Enter msm_adc_gpio_configure_expander_enable\n");
4473
4474 vreg_adc_epm1 = regulator_get(NULL, "8058_s3");
4475
4476 if (IS_ERR(vreg_adc_epm1)) {
4477 printk(KERN_ERR "%s: Unable to get 8058_s3\n", __func__);
4478 return 0;
4479 }
4480
4481 rc = regulator_set_voltage(vreg_adc_epm1, 1800000, 1800000);
4482 if (rc)
4483 printk(KERN_ERR "msm_adc_gpio_configure_expander_enable: "
4484 "regulator set voltage failed\n");
4485
4486 rc = regulator_enable(vreg_adc_epm1);
4487 if (rc) {
4488 printk(KERN_ERR "msm_adc_gpio_configure_expander_enable: "
4489 "Error while enabling regulator for epm s3 %d\n", rc);
4490 return rc;
4491 }
4492
4493 printk(KERN_DEBUG "msm_adc_gpio_configure_expander_enable: Start"
4494 " setting the value of the EPM 3.3, 5v and lvlsft\n");
4495
4496 msleep(1000);
4497
4498 rc = gpio_request(GPIO_EPM_5V_BOOST_EN, "boost_epm_5v");
4499 if (!rc) {
4500 printk(KERN_DEBUG "msm_adc_gpio_configure_expander_enable: "
4501 "Configure 5v boost\n");
4502 gpio_direction_output(GPIO_EPM_5V_BOOST_EN, 1);
4503 } else {
4504 printk(KERN_ERR "msm_adc_gpio_configure_expander_enable: "
4505 "Error for epm 5v boost en\n");
4506 goto exit_vreg_epm;
4507 }
4508
4509 msleep(500);
4510
4511 rc = gpio_request(GPIO_EPM_3_3V_EN, "epm_3_3v");
4512 if (!rc) {
4513 gpio_direction_output(GPIO_EPM_3_3V_EN, 1);
4514 printk(KERN_DEBUG "msm_adc_gpio_configure_expander_enable: "
4515 "Configure epm 3.3v\n");
4516 } else {
4517 printk(KERN_ERR "msm_adc_gpio_configure_expander_enable: "
4518 "Error for gpio 3.3ven\n");
4519 goto exit_vreg_epm;
4520 }
4521 msleep(500);
4522
4523 printk(KERN_DEBUG "msm_adc_gpio_configure_expander_enable: "
4524 "Trying to request EPM LVLSFT_EN\n");
4525 rc = gpio_request(GPIO_EPM_LVLSFT_EN, "lvsft_en");
4526 if (!rc) {
4527 gpio_direction_output(GPIO_EPM_LVLSFT_EN, 1);
4528 printk(KERN_DEBUG "msm_adc_gpio_configure_expander_enable: "
4529 "Configure the lvlsft\n");
4530 } else {
4531 printk(KERN_ERR "msm_adc_gpio_configure_expander_enable: "
4532 "Error for epm lvlsft_en\n");
4533 goto exit_vreg_epm;
4534 }
4535
4536 msleep(500);
4537
4538 if (!epm_i2c_client)
4539 epm_i2c_client = epm_expander_i2c_register_board();
4540
4541 rc = gpio_request(GPIO_PWR_MON_ENABLE, "pwr_mon_enable");
4542 if (!rc)
4543 rc = gpio_direction_output(GPIO_PWR_MON_ENABLE, 1);
4544 if (rc) {
4545 printk(KERN_ERR "msm_adc_gpio_configure_expander_enable"
4546 ": GPIO PWR MON Enable issue\n");
4547 goto exit_vreg_epm;
4548 }
4549
4550 msleep(1000);
4551
4552 rc = gpio_request(GPIO_ADC1_PWDN_N, "adc1_pwdn");
4553 if (!rc) {
4554 rc = gpio_direction_output(GPIO_ADC1_PWDN_N, 1);
4555 if (rc) {
4556 printk(KERN_ERR "msm_adc_gpio_configure_expander_enable"
4557 ": ADC1_PWDN error direction out\n");
4558 goto exit_vreg_epm;
4559 }
4560 }
4561
4562 msleep(100);
4563
4564 rc = gpio_request(GPIO_ADC2_PWDN_N, "adc2_pwdn");
4565 if (!rc) {
4566 rc = gpio_direction_output(GPIO_ADC2_PWDN_N, 1);
4567 if (rc) {
4568 printk(KERN_ERR "msm_adc_gpio_configure_expander_enable"
4569 ": ADC2_PWD error direction out\n");
4570 goto exit_vreg_epm;
4571 }
4572 }
4573
4574 msleep(1000);
4575
4576 rc = gpio_request(GPIO_PWR_MON_START, "pwr_mon_start");
4577 if (!rc) {
4578 rc = gpio_direction_output(GPIO_PWR_MON_START, 0);
4579 if (rc) {
4580 printk(KERN_ERR "msm_adc_gpio_configure_expander_enable"
4581 "Gpio request problem %d\n", rc);
4582 goto exit_vreg_epm;
4583 }
4584 }
4585
4586 rc = gpio_request(GPIO_EPM_SPI_ADC1_CS_N, "spi_adc1_cs");
4587 if (!rc) {
4588 rc = gpio_direction_output(GPIO_EPM_SPI_ADC1_CS_N, 0);
4589 if (rc) {
4590 printk(KERN_ERR "msm_adc_gpio_configure_expander_enable"
4591 ": EPM_SPI_ADC1_CS_N error\n");
4592 goto exit_vreg_epm;
4593 }
4594 }
4595
4596 rc = gpio_request(GPIO_EPM_SPI_ADC2_CS_N, "spi_adc2_cs");
4597 if (!rc) {
4598 rc = gpio_direction_output(GPIO_EPM_SPI_ADC2_CS_N, 0);
4599 if (rc) {
4600 printk(KERN_ERR "msm_adc_gpio_configure_expander_enable"
4601 ": EPM_SPI_ADC2_Cs_N error\n");
4602 goto exit_vreg_epm;
4603 }
4604 }
4605
4606 printk(KERN_DEBUG "msm_adc_gpio_configure_expander_enable: Set "
4607 "the power monitor reset for epm\n");
4608
4609 rc = gpio_request(GPIO_PWR_MON_RESET_N, "pwr_mon_reset_n");
4610 if (!rc) {
4611 gpio_direction_output(GPIO_PWR_MON_RESET_N, 0);
4612 if (rc) {
4613 printk(KERN_ERR "msm_adc_gpio_configure_expander_enable"
4614 ": Error in the power mon reset\n");
4615 goto exit_vreg_epm;
4616 }
4617 }
4618
4619 msleep(1000);
4620
4621 gpio_set_value_cansleep(GPIO_PWR_MON_RESET_N, 1);
4622
4623 msleep(500);
4624
4625 gpio_set_value_cansleep(GPIO_EPM_SPI_ADC1_CS_N, 1);
4626
4627 gpio_set_value_cansleep(GPIO_EPM_SPI_ADC2_CS_N, 1);
4628
4629 return rc;
4630
4631exit_vreg_epm:
4632 regulator_disable(vreg_adc_epm1);
4633
4634 printk(KERN_ERR "msm_adc_gpio_configure_expander_enable: Exit."
4635 " rc = %d.\n", rc);
4636 return rc;
4637};
4638
4639static unsigned int msm_adc_gpio_configure_expander_disable(void)
4640{
4641 int rc = 0;
4642
4643 gpio_set_value_cansleep(GPIO_PWR_MON_RESET_N, 0);
4644 gpio_free(GPIO_PWR_MON_RESET_N);
4645
4646 gpio_set_value_cansleep(GPIO_EPM_SPI_ADC1_CS_N, 0);
4647 gpio_free(GPIO_EPM_SPI_ADC1_CS_N);
4648
4649 gpio_set_value_cansleep(GPIO_EPM_SPI_ADC2_CS_N, 0);
4650 gpio_free(GPIO_EPM_SPI_ADC2_CS_N);
4651
4652 gpio_set_value_cansleep(GPIO_PWR_MON_START, 0);
4653 gpio_free(GPIO_PWR_MON_START);
4654
4655 gpio_direction_output(GPIO_ADC1_PWDN_N, 0);
4656 gpio_free(GPIO_ADC1_PWDN_N);
4657
4658 gpio_direction_output(GPIO_ADC2_PWDN_N, 0);
4659 gpio_free(GPIO_ADC2_PWDN_N);
4660
4661 gpio_set_value_cansleep(GPIO_PWR_MON_ENABLE, 0);
4662 gpio_free(GPIO_PWR_MON_ENABLE);
4663
4664 gpio_set_value_cansleep(GPIO_EPM_LVLSFT_EN, 0);
4665 gpio_free(GPIO_EPM_LVLSFT_EN);
4666
4667 gpio_set_value_cansleep(GPIO_EPM_5V_BOOST_EN, 0);
4668 gpio_free(GPIO_EPM_5V_BOOST_EN);
4669
4670 gpio_set_value_cansleep(GPIO_EPM_3_3V_EN, 0);
4671 gpio_free(GPIO_EPM_3_3V_EN);
4672
4673 rc = regulator_disable(vreg_adc_epm1);
4674 if (rc)
4675 printk(KERN_DEBUG "msm_adc_gpio_configure_expander_disable: "
4676 "Error while enabling regulator for epm s3 %d\n", rc);
4677 regulator_put(vreg_adc_epm1);
4678
4679 printk(KERN_DEBUG "Exi msm_adc_gpio_configure_expander_disable\n");
4680 return rc;
4681};
4682
4683unsigned int msm_adc_gpio_expander_enable(int cs_enable)
4684{
4685 int rc = 0;
4686
4687 printk(KERN_DEBUG "msm_adc_gpio_expander_enable: cs_enable = %d",
4688 cs_enable);
4689
4690 if (cs_enable < 16) {
4691 gpio_set_value_cansleep(GPIO_EPM_SPI_ADC1_CS_N, 0);
4692 gpio_set_value_cansleep(GPIO_EPM_SPI_ADC2_CS_N, 1);
4693 } else {
4694 gpio_set_value_cansleep(GPIO_EPM_SPI_ADC2_CS_N, 0);
4695 gpio_set_value_cansleep(GPIO_EPM_SPI_ADC1_CS_N, 1);
4696 }
4697 return rc;
4698};
4699
4700unsigned int msm_adc_gpio_expander_disable(int cs_disable)
4701{
4702 int rc = 0;
4703
4704 printk(KERN_DEBUG "Enter msm_adc_gpio_expander_disable.\n");
4705
4706 gpio_set_value_cansleep(GPIO_EPM_SPI_ADC1_CS_N, 1);
4707
4708 gpio_set_value_cansleep(GPIO_EPM_SPI_ADC2_CS_N, 1);
4709
4710 return rc;
4711};
4712#endif
4713
4714static struct msm_adc_channels msm_adc_channels_data[] = {
4715 {"vbatt", CHANNEL_ADC_VBATT, 0, &xoadc_fn, CHAN_PATH_TYPE2,
4716 ADC_CONFIG_TYPE2, ADC_CALIB_CONFIG_TYPE3, scale_default},
4717 {"vcoin", CHANNEL_ADC_VCOIN, 0, &xoadc_fn, CHAN_PATH_TYPE1,
4718 ADC_CONFIG_TYPE2, ADC_CALIB_CONFIG_TYPE2, scale_default},
4719 {"vcharger_channel", CHANNEL_ADC_VCHG, 0, &xoadc_fn, CHAN_PATH_TYPE3,
4720 ADC_CONFIG_TYPE2, ADC_CALIB_CONFIG_TYPE4, scale_default},
4721 {"charger_current_monitor", CHANNEL_ADC_CHG_MONITOR, 0, &xoadc_fn,
4722 CHAN_PATH_TYPE4,
4723 ADC_CONFIG_TYPE2, ADC_CALIB_CONFIG_TYPE1, scale_default},
4724 {"vph_pwr", CHANNEL_ADC_VPH_PWR, 0, &xoadc_fn, CHAN_PATH_TYPE5,
4725 ADC_CONFIG_TYPE2, ADC_CALIB_CONFIG_TYPE3, scale_default},
4726 {"usb_vbus", CHANNEL_ADC_USB_VBUS, 0, &xoadc_fn, CHAN_PATH_TYPE11,
4727 ADC_CONFIG_TYPE2, ADC_CALIB_CONFIG_TYPE3, scale_default},
4728 {"pmic_therm", CHANNEL_ADC_DIE_TEMP, 0, &xoadc_fn, CHAN_PATH_TYPE12,
4729 ADC_CONFIG_TYPE2, ADC_CALIB_CONFIG_TYPE1, scale_pmic_therm},
4730 {"pmic_therm_4K", CHANNEL_ADC_DIE_TEMP_4K, 0, &xoadc_fn,
4731 CHAN_PATH_TYPE12,
4732 ADC_CONFIG_TYPE1, ADC_CALIB_CONFIG_TYPE7, scale_pmic_therm},
4733 {"xo_therm", CHANNEL_ADC_XOTHERM, 0, &xoadc_fn, CHAN_PATH_TYPE_NONE,
4734 ADC_CONFIG_TYPE2, ADC_CALIB_CONFIG_TYPE5, tdkntcgtherm},
4735 {"xo_therm_4K", CHANNEL_ADC_XOTHERM_4K, 0, &xoadc_fn,
4736 CHAN_PATH_TYPE_NONE,
4737 ADC_CONFIG_TYPE1, ADC_CALIB_CONFIG_TYPE6, tdkntcgtherm},
4738 {"hdset_detect", CHANNEL_ADC_HDSET, 0, &xoadc_fn, CHAN_PATH_TYPE6,
4739 ADC_CONFIG_TYPE2, ADC_CALIB_CONFIG_TYPE1, scale_default},
4740 {"chg_batt_amon", CHANNEL_ADC_BATT_AMON, 0, &xoadc_fn, CHAN_PATH_TYPE10,
4741 ADC_CONFIG_TYPE2, ADC_CALIB_CONFIG_TYPE1,
4742 scale_xtern_chgr_cur},
4743 {"msm_therm", CHANNEL_ADC_MSM_THERM, 0, &xoadc_fn, CHAN_PATH_TYPE8,
4744 ADC_CONFIG_TYPE2, ADC_CALIB_CONFIG_TYPE2, scale_msm_therm},
4745 {"batt_therm", CHANNEL_ADC_BATT_THERM, 0, &xoadc_fn, CHAN_PATH_TYPE7,
4746 ADC_CONFIG_TYPE2, ADC_CALIB_CONFIG_TYPE2, scale_batt_therm},
4747 {"batt_id", CHANNEL_ADC_BATT_ID, 0, &xoadc_fn, CHAN_PATH_TYPE9,
4748 ADC_CONFIG_TYPE2, ADC_CALIB_CONFIG_TYPE2, scale_default},
4749 {"ref_625mv", CHANNEL_ADC_625_REF, 0, &xoadc_fn, CHAN_PATH_TYPE15,
4750 ADC_CONFIG_TYPE2, ADC_CALIB_CONFIG_TYPE2, scale_default},
4751 {"ref_1250mv", CHANNEL_ADC_1250_REF, 0, &xoadc_fn, CHAN_PATH_TYPE13,
4752 ADC_CONFIG_TYPE2, ADC_CALIB_CONFIG_TYPE2, scale_default},
4753 {"ref_325mv", CHANNEL_ADC_325_REF, 0, &xoadc_fn, CHAN_PATH_TYPE14,
4754 ADC_CONFIG_TYPE2, ADC_CALIB_CONFIG_TYPE2, scale_default},
4755};
4756
4757static char *msm_adc_fluid_device_names[] = {
4758 "ADS_ADC1",
4759 "ADS_ADC2",
4760};
4761
4762static struct msm_adc_platform_data msm_adc_pdata = {
4763 .channel = msm_adc_channels_data,
4764 .num_chan_supported = ARRAY_SIZE(msm_adc_channels_data),
4765#if defined(CONFIG_I2C) && \
4766 (defined(CONFIG_GPIO_SX150X) || defined(CONFIG_GPIO_SX150X_MODULE))
4767 .adc_gpio_enable = msm_adc_gpio_expander_enable,
4768 .adc_gpio_disable = msm_adc_gpio_expander_disable,
4769 .adc_fluid_enable = msm_adc_gpio_configure_expander_enable,
4770 .adc_fluid_disable = msm_adc_gpio_configure_expander_disable,
4771#endif
4772};
4773
4774static struct platform_device msm_adc_device = {
4775 .name = "msm_adc",
4776 .id = -1,
4777 .dev = {
4778 .platform_data = &msm_adc_pdata,
4779 },
4780};
4781
4782static void pmic8058_xoadc_mpp_config(void)
4783{
4784 int rc;
4785
4786 rc = pm8901_mpp_config_digital_out(XOADC_MPP_4,
4787 PM8901_MPP_DIG_LEVEL_S4, PM_MPP_DOUT_CTL_LOW);
4788 if (rc)
4789 pr_err("%s: Config mpp4 on pmic 8901 failed\n", __func__);
4790
4791 rc = pm8058_mpp_config_analog_input(XOADC_MPP_3,
4792 PM_MPP_AIN_AMUX_CH5, PM_MPP_AOUT_CTL_DISABLE);
4793 if (rc)
4794 pr_err("%s: Config mpp3 on pmic 8058 failed\n", __func__);
4795
4796 rc = pm8058_mpp_config_analog_input(XOADC_MPP_5,
4797 PM_MPP_AIN_AMUX_CH9, PM_MPP_AOUT_CTL_DISABLE);
4798 if (rc)
4799 pr_err("%s: Config mpp5 on pmic 8058 failed\n", __func__);
4800
4801 rc = pm8058_mpp_config_analog_input(XOADC_MPP_7,
4802 PM_MPP_AIN_AMUX_CH6, PM_MPP_AOUT_CTL_DISABLE);
4803 if (rc)
4804 pr_err("%s: Config mpp7 on pmic 8058 failed\n", __func__);
4805
4806 rc = pm8058_mpp_config_analog_input(XOADC_MPP_8,
4807 PM_MPP_AIN_AMUX_CH8, PM_MPP_AOUT_CTL_DISABLE);
4808 if (rc)
4809 pr_err("%s: Config mpp8 on pmic 8058 failed\n", __func__);
4810
4811 rc = pm8058_mpp_config_analog_input(XOADC_MPP_10,
4812 PM_MPP_AIN_AMUX_CH7, PM_MPP_AOUT_CTL_DISABLE);
4813 if (rc)
4814 pr_err("%s: Config mpp10 on pmic 8058 failed\n", __func__);
4815}
4816
4817static struct regulator *vreg_ldo18_adc;
4818
4819static int pmic8058_xoadc_vreg_config(int on)
4820{
4821 int rc;
4822
4823 if (on) {
4824 rc = regulator_enable(vreg_ldo18_adc);
4825 if (rc)
4826 pr_err("%s: Enable of regulator ldo18_adc "
4827 "failed\n", __func__);
4828 } else {
4829 rc = regulator_disable(vreg_ldo18_adc);
4830 if (rc)
4831 pr_err("%s: Disable of regulator ldo18_adc "
4832 "failed\n", __func__);
4833 }
4834
4835 return rc;
4836}
4837
4838static int pmic8058_xoadc_vreg_setup(void)
4839{
4840 int rc;
4841
4842 vreg_ldo18_adc = regulator_get(NULL, "8058_l18");
4843 if (IS_ERR(vreg_ldo18_adc)) {
4844 printk(KERN_ERR "%s: vreg get failed (%ld)\n",
4845 __func__, PTR_ERR(vreg_ldo18_adc));
4846 rc = PTR_ERR(vreg_ldo18_adc);
4847 goto fail;
4848 }
4849
4850 rc = regulator_set_voltage(vreg_ldo18_adc, 2200000, 2200000);
4851 if (rc) {
4852 pr_err("%s: unable to set ldo18 voltage to 2.2V\n", __func__);
4853 goto fail;
4854 }
4855
4856 return rc;
4857fail:
4858 regulator_put(vreg_ldo18_adc);
4859 return rc;
4860}
4861
4862static void pmic8058_xoadc_vreg_shutdown(void)
4863{
4864 regulator_put(vreg_ldo18_adc);
4865}
4866
4867/* usec. For this ADC,
4868 * this time represents clk rate @ txco w/ 1024 decimation ratio.
4869 * Each channel has different configuration, thus at the time of starting
4870 * the conversion, xoadc will return actual conversion time
4871 * */
4872static struct adc_properties pm8058_xoadc_data = {
4873 .adc_reference = 2200, /* milli-voltage for this adc */
4874 .bitresolution = 15,
4875 .bipolar = 0,
4876 .conversiontime = 54,
4877};
4878
4879static struct xoadc_platform_data xoadc_pdata = {
4880 .xoadc_prop = &pm8058_xoadc_data,
4881 .xoadc_mpp_config = pmic8058_xoadc_mpp_config,
4882 .xoadc_vreg_set = pmic8058_xoadc_vreg_config,
4883 .xoadc_num = XOADC_PMIC_0,
4884 .xoadc_vreg_setup = pmic8058_xoadc_vreg_setup,
4885 .xoadc_vreg_shutdown = pmic8058_xoadc_vreg_shutdown,
4886};
4887#endif
4888
4889#ifdef CONFIG_MSM_SDIO_AL
4890
4891static unsigned mdm2ap_status = 140;
4892
4893static int configure_mdm2ap_status(int on)
4894{
4895 int ret = 0;
4896 if (on)
4897 ret = msm_gpiomux_get(mdm2ap_status);
4898 else
4899 ret = msm_gpiomux_put(mdm2ap_status);
4900
4901 if (ret)
4902 pr_err("%s: mdm2ap_status config failed, on = %d\n", __func__,
4903 on);
4904
4905 return ret;
4906}
4907
4908
4909static int get_mdm2ap_status(void)
4910{
4911 return gpio_get_value(mdm2ap_status);
4912}
4913
4914static struct sdio_al_platform_data sdio_al_pdata = {
4915 .config_mdm2ap_status = configure_mdm2ap_status,
4916 .get_mdm2ap_status = get_mdm2ap_status,
4917 .allow_sdioc_version_major_2 = 0,
Konstantin Dorfmanee2e3082011-08-16 15:12:01 +03004918 .peer_sdioc_version_minor = 0x0202,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004919 .peer_sdioc_version_major = 0x0004,
4920 .peer_sdioc_boot_version_minor = 0x0001,
4921 .peer_sdioc_boot_version_major = 0x0003
4922};
4923
4924struct platform_device msm_device_sdio_al = {
4925 .name = "msm_sdio_al",
4926 .id = -1,
4927 .dev = {
Maya Erez6862b142011-08-22 09:07:07 +03004928 .parent = &msm_charm_modem.dev,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004929 .platform_data = &sdio_al_pdata,
4930 },
4931};
4932
4933#endif /* CONFIG_MSM_SDIO_AL */
4934
4935static struct platform_device *charm_devices[] __initdata = {
4936 &msm_charm_modem,
4937#ifdef CONFIG_MSM_SDIO_AL
4938 &msm_device_sdio_al,
4939#endif
4940};
4941
Lei Zhou338cab82011-08-19 13:38:17 -04004942#ifdef CONFIG_SND_SOC_MSM8660_APQ
4943static struct platform_device *dragon_alsa_devices[] __initdata = {
4944 &msm_pcm,
4945 &msm_pcm_routing,
4946 &msm_cpudai0,
4947 &msm_cpudai1,
4948 &msm_cpudai_hdmi_rx,
4949 &msm_cpudai_bt_rx,
4950 &msm_cpudai_bt_tx,
4951 &msm_cpudai_fm_rx,
4952 &msm_cpudai_fm_tx,
4953 &msm_cpu_fe,
4954 &msm_stub_codec,
4955 &msm_lpa_pcm,
4956};
4957#endif
4958
4959static struct platform_device *asoc_devices[] __initdata = {
4960 &asoc_msm_pcm,
4961 &asoc_msm_dai0,
4962 &asoc_msm_dai1,
4963};
4964
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004965static struct platform_device *surf_devices[] __initdata = {
4966 &msm_device_smd,
4967 &msm_device_uart_dm12,
4968#ifdef CONFIG_I2C_QUP
4969 &msm_gsbi3_qup_i2c_device,
4970 &msm_gsbi4_qup_i2c_device,
4971 &msm_gsbi7_qup_i2c_device,
4972 &msm_gsbi8_qup_i2c_device,
4973 &msm_gsbi9_qup_i2c_device,
4974 &msm_gsbi12_qup_i2c_device,
4975#endif
4976#ifdef CONFIG_SERIAL_MSM_HS
4977 &msm_device_uart_dm1,
4978#endif
4979#ifdef CONFIG_I2C_SSBI
4980 &msm_device_ssbi1,
4981 &msm_device_ssbi2,
4982 &msm_device_ssbi3,
4983#endif
4984#if defined(CONFIG_USB_PEHCI_HCD) || defined(CONFIG_USB_PEHCI_HCD_MODULE)
4985 &isp1763_device,
4986#endif
4987
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004988#if defined (CONFIG_MSM_8x60_VOIP)
4989 &asoc_msm_mvs,
4990 &asoc_mvs_dai0,
4991 &asoc_mvs_dai1,
4992#endif
Lei Zhou338cab82011-08-19 13:38:17 -04004993
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004994#if defined(CONFIG_USB_GADGET_MSM_72K) || defined(CONFIG_USB_EHCI_HCD)
4995 &msm_device_otg,
4996#endif
4997#ifdef CONFIG_USB_GADGET_MSM_72K
4998 &msm_device_gadget_peripheral,
4999#endif
5000#ifdef CONFIG_USB_G_ANDROID
5001 &android_usb_device,
5002#endif
5003#ifdef CONFIG_BATTERY_MSM
5004 &msm_batt_device,
5005#endif
5006#ifdef CONFIG_ANDROID_PMEM
5007 &android_pmem_device,
5008 &android_pmem_adsp_device,
5009 &android_pmem_audio_device,
5010 &android_pmem_smipool_device,
5011#endif
5012#ifdef CONFIG_MSM_ROTATOR
5013 &msm_rotator_device,
5014#endif
5015 &msm_fb_device,
5016 &msm_kgsl_3d0,
5017 &msm_kgsl_2d0,
5018 &msm_kgsl_2d1,
5019 &lcdc_samsung_panel_device,
Zhang Chang Ken3a8b8512011-08-04 18:41:39 -04005020#ifdef CONFIG_FB_MSM_LCDC_NT35582_WVGA
5021 &lcdc_nt35582_panel_device,
5022#endif
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005023#ifdef CONFIG_FB_MSM_LCDC_SAMSUNG_OLED_PT
5024 &lcdc_samsung_oled_panel_device,
5025#endif
5026#ifdef CONFIG_FB_MSM_LCDC_AUO_WVGA
5027 &lcdc_auo_wvga_panel_device,
5028#endif
5029#ifdef CONFIG_FB_MSM_HDMI_MSM_PANEL
5030 &hdmi_msm_device,
5031#endif /* CONFIG_FB_MSM_HDMI_MSM_PANEL */
5032#ifdef CONFIG_FB_MSM_MIPI_DSI
5033 &mipi_dsi_toshiba_panel_device,
5034 &mipi_dsi_novatek_panel_device,
5035#endif
5036#ifdef CONFIG_MSM_CAMERA
5037#ifdef CONFIG_MT9E013
5038 &msm_camera_sensor_mt9e013,
5039#endif
5040#ifdef CONFIG_IMX074
5041 &msm_camera_sensor_imx074,
5042#endif
5043#ifdef CONFIG_WEBCAM_OV7692
5044 &msm_camera_sensor_webcam_ov7692,
5045#endif
5046#ifdef CONFIG_WEBCAM_OV9726
5047 &msm_camera_sensor_webcam_ov9726,
5048#endif
5049#ifdef CONFIG_QS_S5K4E1
5050 &msm_camera_sensor_qs_s5k4e1,
5051#endif
Jilai Wang971f97f2011-07-13 14:25:25 -04005052#ifdef CONFIG_VX6953
5053 &msm_camera_sensor_vx6953,
5054#endif
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005055#endif
5056#ifdef CONFIG_MSM_GEMINI
5057 &msm_gemini_device,
5058#endif
5059#ifdef CONFIG_MSM_VPE
5060 &msm_vpe_device,
5061#endif
5062
5063#if defined(CONFIG_MSM_RPM_LOG) || defined(CONFIG_MSM_RPM_LOG_MODULE)
5064 &msm_rpm_log_device,
5065#endif
5066#if defined(CONFIG_MSM_RPM_STATS_LOG)
5067 &msm_rpm_stat_device,
5068#endif
5069 &msm_device_vidc,
5070#if (defined(CONFIG_MARIMBA_CORE)) && \
5071 (defined(CONFIG_MSM_BT_POWER) || defined(CONFIG_MSM_BT_POWER_MODULE))
5072 &msm_bt_power_device,
5073#endif
5074#ifdef CONFIG_SENSORS_MSM_ADC
5075 &msm_adc_device,
5076#endif
David Collins6f032ba2011-08-31 14:08:15 -07005077 &rpm_regulator_device,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005078
5079#if defined(CONFIG_CRYPTO_DEV_QCRYPTO) || \
5080 defined(CONFIG_CRYPTO_DEV_QCRYPTO_MODULE)
5081 &qcrypto_device,
5082#endif
5083
5084#if defined(CONFIG_CRYPTO_DEV_QCEDEV) || \
5085 defined(CONFIG_CRYPTO_DEV_QCEDEV_MODULE)
5086 &qcedev_device,
5087#endif
5088
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005089
5090#if defined(CONFIG_TSIF) || defined(CONFIG_TSIF_MODULE)
5091#ifdef CONFIG_MSM_USE_TSIF1
5092 &msm_device_tsif[1],
5093#else
5094 &msm_device_tsif[0],
5095#endif /* CONFIG_MSM_USE_TSIF1 */
5096#endif /* CONFIG_TSIF */
5097
5098#ifdef CONFIG_HW_RANDOM_MSM
5099 &msm_device_rng,
5100#endif
5101
5102 &msm_tsens_device,
Praveen Chidambaram043f4ce2011-08-02 09:37:59 -06005103 &msm_rpm_device,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005104
5105};
5106
5107static struct memtype_reserve msm8x60_reserve_table[] __initdata = {
5108 /* Kernel SMI memory pool for video core, used for firmware */
5109 /* and encoder, decoder scratch buffers */
5110 /* Kernel SMI memory pool should always precede the user space */
5111 /* SMI memory pool, as the video core will use offset address */
5112 /* from the Firmware base */
5113 [MEMTYPE_SMI_KERNEL] = {
5114 .start = KERNEL_SMI_BASE,
5115 .limit = KERNEL_SMI_SIZE,
5116 .size = KERNEL_SMI_SIZE,
5117 .flags = MEMTYPE_FLAGS_FIXED,
5118 },
5119 /* User space SMI memory pool for video core */
5120 /* used for encoder, decoder input & output buffers */
5121 [MEMTYPE_SMI] = {
5122 .start = USER_SMI_BASE,
5123 .limit = USER_SMI_SIZE,
5124 .flags = MEMTYPE_FLAGS_FIXED,
5125 },
5126 [MEMTYPE_EBI0] = {
5127 .flags = MEMTYPE_FLAGS_1M_ALIGN,
5128 },
5129 [MEMTYPE_EBI1] = {
5130 .flags = MEMTYPE_FLAGS_1M_ALIGN,
5131 },
5132};
5133
5134static void __init size_pmem_devices(void)
5135{
5136#ifdef CONFIG_ANDROID_PMEM
5137 android_pmem_adsp_pdata.size = pmem_adsp_size;
5138 android_pmem_smipool_pdata.size = MSM_PMEM_SMIPOOL_SIZE;
5139 android_pmem_audio_pdata.size = MSM_PMEM_AUDIO_SIZE;
5140 android_pmem_pdata.size = pmem_sf_size;
5141#endif
5142}
5143
5144static void __init reserve_memory_for(struct android_pmem_platform_data *p)
5145{
5146 msm8x60_reserve_table[p->memory_type].size += p->size;
5147}
5148
5149static void __init reserve_pmem_memory(void)
5150{
5151#ifdef CONFIG_ANDROID_PMEM
5152 reserve_memory_for(&android_pmem_adsp_pdata);
5153 reserve_memory_for(&android_pmem_smipool_pdata);
5154 reserve_memory_for(&android_pmem_audio_pdata);
5155 reserve_memory_for(&android_pmem_pdata);
5156 msm8x60_reserve_table[MEMTYPE_EBI1].size += pmem_kernel_ebi1_size;
5157#endif
5158}
5159
5160static void __init msm8x60_calculate_reserve_sizes(void)
5161{
5162 size_pmem_devices();
5163 reserve_pmem_memory();
5164}
5165
5166static int msm8x60_paddr_to_memtype(unsigned int paddr)
5167{
5168 if (paddr >= 0x40000000 && paddr < 0x60000000)
5169 return MEMTYPE_EBI1;
5170 if (paddr >= 0x38000000 && paddr < 0x40000000)
5171 return MEMTYPE_SMI;
5172 return MEMTYPE_NONE;
5173}
5174
5175static struct reserve_info msm8x60_reserve_info __initdata = {
5176 .memtype_reserve_table = msm8x60_reserve_table,
5177 .calculate_reserve_sizes = msm8x60_calculate_reserve_sizes,
5178 .paddr_to_memtype = msm8x60_paddr_to_memtype,
5179};
5180
5181static void __init msm8x60_reserve(void)
5182{
5183 reserve_info = &msm8x60_reserve_info;
5184 msm_reserve();
5185}
5186
5187#define EXT_CHG_VALID_MPP 10
5188#define EXT_CHG_VALID_MPP_2 11
5189
5190#ifdef CONFIG_ISL9519_CHARGER
5191static int isl_detection_setup(void)
5192{
5193 int ret = 0;
5194
5195 ret = pm8058_mpp_config_digital_in(EXT_CHG_VALID_MPP,
5196 PM8058_MPP_DIG_LEVEL_S3,
5197 PM_MPP_DIN_TO_INT);
5198 ret |= pm8058_mpp_config_bi_dir(EXT_CHG_VALID_MPP_2,
5199 PM8058_MPP_DIG_LEVEL_S3,
5200 PM_MPP_BI_PULLUP_10KOHM
5201 );
5202 return ret;
5203}
5204
5205static struct isl_platform_data isl_data __initdata = {
5206 .chgcurrent = 700,
5207 .valid_n_gpio = PM8058_MPP_PM_TO_SYS(10),
5208 .chg_detection_config = isl_detection_setup,
5209 .max_system_voltage = 4200,
5210 .min_system_voltage = 3200,
5211 .term_current = 120,
5212 .input_current = 2048,
5213};
5214
5215static struct i2c_board_info isl_charger_i2c_info[] __initdata = {
5216 {
5217 I2C_BOARD_INFO("isl9519q", 0x9),
5218 .irq = PM8058_CBLPWR_IRQ(PM8058_IRQ_BASE),
5219 .platform_data = &isl_data,
5220 },
5221};
5222#endif
5223
5224#if defined(CONFIG_SMB137B_CHARGER) || defined(CONFIG_SMB137B_CHARGER_MODULE)
5225static int smb137b_detection_setup(void)
5226{
5227 int ret = 0;
5228
5229 ret = pm8058_mpp_config_digital_in(EXT_CHG_VALID_MPP,
5230 PM8058_MPP_DIG_LEVEL_S3,
5231 PM_MPP_DIN_TO_INT);
5232 ret |= pm8058_mpp_config_bi_dir(EXT_CHG_VALID_MPP_2,
5233 PM8058_MPP_DIG_LEVEL_S3,
5234 PM_MPP_BI_PULLUP_10KOHM);
5235 return ret;
5236}
5237
5238static struct smb137b_platform_data smb137b_data __initdata = {
5239 .chg_detection_config = smb137b_detection_setup,
5240 .valid_n_gpio = PM8058_MPP_PM_TO_SYS(10),
5241 .batt_mah_rating = 950,
5242};
5243
5244static struct i2c_board_info smb137b_charger_i2c_info[] __initdata = {
5245 {
5246 I2C_BOARD_INFO("smb137b", 0x08),
5247 .irq = PM8058_CBLPWR_IRQ(PM8058_IRQ_BASE),
5248 .platform_data = &smb137b_data,
5249 },
5250};
5251#endif
5252
5253#ifdef CONFIG_PMIC8058
5254#define PMIC_GPIO_SDC3_DET 22
5255
5256static int pm8058_gpios_init(void)
5257{
5258 int i;
5259 int rc;
5260 struct pm8058_gpio_cfg {
5261 int gpio;
5262 struct pm8058_gpio cfg;
5263 };
5264
5265 struct pm8058_gpio_cfg gpio_cfgs[] = {
5266 { /* FFA ethernet */
5267 6,
5268 {
5269 .direction = PM_GPIO_DIR_IN,
5270 .pull = PM_GPIO_PULL_DN,
5271 .vin_sel = 2,
5272 .function = PM_GPIO_FUNC_NORMAL,
5273 .inv_int_pol = 0,
5274 },
5275 },
5276#ifdef CONFIG_MMC_MSM_CARD_HW_DETECTION
5277 {
5278 PMIC_GPIO_SDC3_DET - 1,
5279 {
5280 .direction = PM_GPIO_DIR_IN,
5281 .pull = PM_GPIO_PULL_UP_30,
5282 .vin_sel = 2,
5283 .function = PM_GPIO_FUNC_NORMAL,
5284 .inv_int_pol = 0,
5285 },
5286 },
5287#endif
5288 { /* core&surf gpio expander */
5289 UI_INT1_N,
5290 {
5291 .direction = PM_GPIO_DIR_IN,
5292 .pull = PM_GPIO_PULL_NO,
5293 .vin_sel = PM_GPIO_VIN_S3,
5294 .function = PM_GPIO_FUNC_NORMAL,
5295 .inv_int_pol = 0,
5296 },
5297 },
5298 { /* docking gpio expander */
5299 UI_INT2_N,
5300 {
5301 .direction = PM_GPIO_DIR_IN,
5302 .pull = PM_GPIO_PULL_NO,
5303 .vin_sel = PM_GPIO_VIN_S3,
5304 .function = PM_GPIO_FUNC_NORMAL,
5305 .inv_int_pol = 0,
5306 },
5307 },
5308 { /* FHA/keypad gpio expanders */
5309 UI_INT3_N,
5310 {
5311 .direction = PM_GPIO_DIR_IN,
5312 .pull = PM_GPIO_PULL_NO,
5313 .vin_sel = PM_GPIO_VIN_S3,
5314 .function = PM_GPIO_FUNC_NORMAL,
5315 .inv_int_pol = 0,
5316 },
5317 },
5318 { /* TouchDisc Interrupt */
5319 5,
5320 {
5321 .direction = PM_GPIO_DIR_IN,
5322 .pull = PM_GPIO_PULL_UP_1P5,
5323 .vin_sel = 2,
5324 .function = PM_GPIO_FUNC_NORMAL,
5325 .inv_int_pol = 0,
5326 }
5327 },
5328 { /* Timpani Reset */
5329 20,
5330 {
5331 .direction = PM_GPIO_DIR_OUT,
5332 .output_value = 1,
5333 .output_buffer = PM_GPIO_OUT_BUF_CMOS,
5334 .pull = PM_GPIO_PULL_DN,
5335 .out_strength = PM_GPIO_STRENGTH_HIGH,
5336 .function = PM_GPIO_FUNC_NORMAL,
5337 .vin_sel = 2,
5338 .inv_int_pol = 0,
5339 }
5340 },
5341 { /* PMIC ID interrupt */
5342 36,
5343 {
5344 .direction = PM_GPIO_DIR_IN,
5345 .pull = PM_GPIO_PULL_UP_1P5,
5346 .function = PM_GPIO_FUNC_NORMAL,
5347 .vin_sel = 2,
5348 .inv_int_pol = 0,
5349 }
5350 },
5351 };
5352
5353#if defined(CONFIG_HAPTIC_ISA1200) || \
5354 defined(CONFIG_HAPTIC_ISA1200_MODULE)
5355
5356 struct pm8058_gpio_cfg en_hap_gpio_cfg = {
5357 PMIC_GPIO_HAP_ENABLE,
5358 {
5359 .direction = PM_GPIO_DIR_OUT,
5360 .pull = PM_GPIO_PULL_NO,
5361 .out_strength = PM_GPIO_STRENGTH_HIGH,
5362 .function = PM_GPIO_FUNC_NORMAL,
5363 .inv_int_pol = 0,
5364 .vin_sel = 2,
5365 .output_buffer = PM_GPIO_OUT_BUF_CMOS,
5366 .output_value = 0,
5367 }
5368
5369 };
5370#endif
5371
5372#if defined(CONFIG_PMIC8058_OTHC) || defined(CONFIG_PMIC8058_OTHC_MODULE)
5373 struct pm8058_gpio_cfg line_in_gpio_cfg = {
5374 18,
5375 {
5376 .direction = PM_GPIO_DIR_IN,
5377 .pull = PM_GPIO_PULL_UP_1P5,
5378 .vin_sel = 2,
5379 .function = PM_GPIO_FUNC_NORMAL,
5380 .inv_int_pol = 0,
5381 }
5382 };
5383#endif
5384
5385#if defined(CONFIG_QS_S5K4E1)
5386 {
5387 struct pm8058_gpio_cfg qs_hc37_cam_pd_gpio_cfg = {
5388 26,
5389 {
5390 .direction = PM_GPIO_DIR_OUT,
5391 .output_value = 0,
5392 .output_buffer = PM_GPIO_OUT_BUF_CMOS,
5393 .pull = PM_GPIO_PULL_DN,
5394 .out_strength = PM_GPIO_STRENGTH_HIGH,
5395 .function = PM_GPIO_FUNC_NORMAL,
5396 .vin_sel = 2,
5397 .inv_int_pol = 0,
5398 }
5399 };
5400#endif
Zhang Chang Ken3a8b8512011-08-04 18:41:39 -04005401#ifdef CONFIG_FB_MSM_LCDC_NT35582_WVGA
5402 struct pm8058_gpio_cfg pmic_lcdc_nt35582_gpio_cfg = {
5403 GPIO_NT35582_BL_EN_HW_PIN - 1,
5404 {
5405 .direction = PM_GPIO_DIR_OUT,
5406 .output_buffer = PM_GPIO_OUT_BUF_CMOS,
5407 .output_value = 1,
5408 .pull = PM_GPIO_PULL_UP_30,
5409 /* 2.9V PM_GPIO_VIN_L2, which gives 2.6V */
5410 .vin_sel = PM_GPIO_VIN_L5,
5411 .out_strength = PM_GPIO_STRENGTH_HIGH,
5412 .function = PM_GPIO_FUNC_NORMAL,
5413 .inv_int_pol = 0,
5414 }
5415 };
5416#endif
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005417#if defined(CONFIG_HAPTIC_ISA1200) || \
5418 defined(CONFIG_HAPTIC_ISA1200_MODULE)
5419 if (machine_is_msm8x60_fluid()) {
5420 rc = pm8058_gpio_config(en_hap_gpio_cfg.gpio,
5421 &en_hap_gpio_cfg.cfg);
5422 if (rc < 0) {
5423 pr_err("%s pmic haptics gpio config failed\n",
5424 __func__);
5425 return rc;
5426 }
5427 }
5428#endif
5429
5430#if defined(CONFIG_PMIC8058_OTHC) || defined(CONFIG_PMIC8058_OTHC_MODULE)
5431 /* Line_in only for 8660 ffa & surf */
5432 if (machine_is_msm8x60_ffa() || machine_is_msm8x60_surf() ||
Zhang Chang Ken6baadf02011-08-05 09:48:15 -04005433 machine_is_msm8x60_fusion() || machine_is_msm8x60_dragon() ||
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005434 machine_is_msm8x60_fusn_ffa()) {
5435 rc = pm8058_gpio_config(line_in_gpio_cfg.gpio,
5436 &line_in_gpio_cfg.cfg);
5437 if (rc < 0) {
5438 pr_err("%s pmic line_in gpio config failed\n",
5439 __func__);
5440 return rc;
5441 }
5442 }
5443#endif
5444
Zhang Chang Ken3a8b8512011-08-04 18:41:39 -04005445#ifdef CONFIG_FB_MSM_LCDC_NT35582_WVGA
5446 if (machine_is_msm8x60_dragon()) {
5447 rc = pm8058_gpio_config(pmic_lcdc_nt35582_gpio_cfg.gpio,
5448 &pmic_lcdc_nt35582_gpio_cfg.cfg);
5449 if (rc < 0) {
5450 pr_err("%s pmic gpio config failed\n", __func__);
5451 return rc;
5452 }
5453 }
5454#endif
5455
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005456#if defined(CONFIG_QS_S5K4E1)
5457 /* qs_cam_hc37_cam_pd only for 8660 fluid qs camera*/
5458 if (machine_is_msm8x60_fluid()) {
5459 rc = pm8058_gpio_config(qs_hc37_cam_pd_gpio_cfg.gpio,
5460 &qs_hc37_cam_pd_gpio_cfg.cfg);
5461 if (rc < 0) {
5462 pr_err("%s pmic qs_hc37_cam_pd gpio config failed\n",
5463 __func__);
5464 return rc;
5465 }
5466 }
5467 }
5468#endif
5469
5470 for (i = 0; i < ARRAY_SIZE(gpio_cfgs); ++i) {
5471 rc = pm8058_gpio_config(gpio_cfgs[i].gpio,
5472 &gpio_cfgs[i].cfg);
5473 if (rc < 0) {
5474 pr_err("%s pmic gpio config failed\n",
5475 __func__);
5476 return rc;
5477 }
5478 }
5479
5480 return 0;
5481}
5482
5483static const unsigned int ffa_keymap[] = {
5484 KEY(0, 0, KEY_FN_F1), /* LS - PUSH1 */
5485 KEY(0, 1, KEY_UP), /* NAV - UP */
5486 KEY(0, 2, KEY_LEFT), /* NAV - LEFT */
5487 KEY(0, 3, KEY_VOLUMEUP), /* Shuttle SW_UP */
5488
5489 KEY(1, 0, KEY_FN_F2), /* LS - PUSH2 */
5490 KEY(1, 1, KEY_RIGHT), /* NAV - RIGHT */
5491 KEY(1, 2, KEY_DOWN), /* NAV - DOWN */
5492 KEY(1, 3, KEY_VOLUMEDOWN),
5493
5494 KEY(2, 3, KEY_ENTER), /* SW_PUSH key */
5495
5496 KEY(4, 0, KEY_CAMERA_FOCUS), /* RS - PUSH1 */
5497 KEY(4, 1, KEY_UP), /* USER_UP */
5498 KEY(4, 2, KEY_LEFT), /* USER_LEFT */
5499 KEY(4, 3, KEY_HOME), /* Right switch: MIC Bd */
5500 KEY(4, 4, KEY_FN_F3), /* Reserved MIC */
5501
5502 KEY(5, 0, KEY_CAMERA), /* RS - PUSH2 */
5503 KEY(5, 1, KEY_RIGHT), /* USER_RIGHT */
5504 KEY(5, 2, KEY_DOWN), /* USER_DOWN */
5505 KEY(5, 3, KEY_BACK), /* Left switch: MIC */
5506 KEY(5, 4, KEY_MENU), /* Center switch: MIC */
5507};
5508
Zhang Chang Ken683be172011-08-10 17:45:34 -04005509static const unsigned int dragon_keymap[] = {
5510 KEY(0, 0, KEY_MENU),
5511 KEY(0, 2, KEY_1),
5512 KEY(0, 3, KEY_4),
5513 KEY(0, 4, KEY_7),
5514
5515 KEY(1, 0, KEY_UP),
5516 KEY(1, 1, KEY_LEFT),
5517 KEY(1, 2, KEY_DOWN),
5518 KEY(1, 3, KEY_5),
5519 KEY(1, 4, KEY_8),
5520
5521 KEY(2, 0, KEY_HOME),
5522 KEY(2, 1, KEY_REPLY),
5523 KEY(2, 2, KEY_2),
5524 KEY(2, 3, KEY_6),
5525 KEY(2, 4, KEY_0),
5526
5527 KEY(3, 0, KEY_VOLUMEUP),
5528 KEY(3, 1, KEY_RIGHT),
5529 KEY(3, 2, KEY_3),
5530 KEY(3, 3, KEY_9),
5531 KEY(3, 4, KEY_SWITCHVIDEOMODE),
5532
5533 KEY(4, 0, KEY_VOLUMEDOWN),
5534 KEY(4, 1, KEY_BACK),
5535 KEY(4, 2, KEY_CAMERA),
5536 KEY(4, 3, KEY_KBDILLUMTOGGLE),
5537};
5538
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005539static struct resource resources_keypad[] = {
5540 {
5541 .start = PM8058_KEYPAD_IRQ(PM8058_IRQ_BASE),
5542 .end = PM8058_KEYPAD_IRQ(PM8058_IRQ_BASE),
5543 .flags = IORESOURCE_IRQ,
5544 },
5545 {
5546 .start = PM8058_KEYSTUCK_IRQ(PM8058_IRQ_BASE),
5547 .end = PM8058_KEYSTUCK_IRQ(PM8058_IRQ_BASE),
5548 .flags = IORESOURCE_IRQ,
5549 },
5550};
5551
5552static struct matrix_keymap_data ffa_keymap_data = {
5553 .keymap_size = ARRAY_SIZE(ffa_keymap),
5554 .keymap = ffa_keymap,
5555};
5556
5557static struct pmic8058_keypad_data ffa_keypad_data = {
5558 .input_name = "ffa-keypad",
5559 .input_phys_device = "ffa-keypad/input0",
5560 .num_rows = 6,
5561 .num_cols = 5,
5562 .rows_gpio_start = 8,
5563 .cols_gpio_start = 0,
5564 .debounce_ms = {8, 10},
5565 .scan_delay_ms = 32,
5566 .row_hold_ns = 91500,
5567 .wakeup = 1,
5568 .keymap_data = &ffa_keymap_data,
5569};
5570
Zhang Chang Ken683be172011-08-10 17:45:34 -04005571static struct matrix_keymap_data dragon_keymap_data = {
5572 .keymap_size = ARRAY_SIZE(dragon_keymap),
5573 .keymap = dragon_keymap,
5574};
5575
5576static struct pmic8058_keypad_data dragon_keypad_data = {
5577 .input_name = "dragon-keypad",
5578 .input_phys_device = "dragon-keypad/input0",
5579 .num_rows = 6,
5580 .num_cols = 5,
5581 .rows_gpio_start = 8,
5582 .cols_gpio_start = 0,
5583 .debounce_ms = {8, 10},
5584 .scan_delay_ms = 32,
5585 .row_hold_ns = 91500,
5586 .wakeup = 1,
5587 .keymap_data = &dragon_keymap_data,
5588};
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005589static const unsigned int fluid_keymap[] = {
5590 KEY(0, 0, KEY_FN_F1), /* LS - PUSH1 */
5591 KEY(0, 1, KEY_UP), /* NAV - UP */
5592 KEY(0, 2, KEY_LEFT), /* NAV - LEFT */
5593 KEY(0, 3, KEY_VOLUMEDOWN), /* Shuttle SW_UP */
5594
5595 KEY(1, 0, KEY_FN_F2), /* LS - PUSH2 */
5596 KEY(1, 1, KEY_RIGHT), /* NAV - RIGHT */
5597 KEY(1, 2, KEY_DOWN), /* NAV - DOWN */
5598 KEY(1, 3, KEY_VOLUMEUP),
5599
5600 KEY(2, 3, KEY_ENTER), /* SW_PUSH key */
5601
5602 KEY(4, 0, KEY_CAMERA_FOCUS), /* RS - PUSH1 */
5603 KEY(4, 1, KEY_UP), /* USER_UP */
5604 KEY(4, 2, KEY_LEFT), /* USER_LEFT */
5605 KEY(4, 3, KEY_HOME), /* Right switch: MIC Bd */
5606 KEY(4, 4, KEY_FN_F3), /* Reserved MIC */
5607
Jilai Wang9a895102011-07-12 14:00:35 -04005608 KEY(5, 0, KEY_CAMERA), /* RS - PUSH2 */
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005609 KEY(5, 1, KEY_RIGHT), /* USER_RIGHT */
5610 KEY(5, 2, KEY_DOWN), /* USER_DOWN */
5611 KEY(5, 3, KEY_BACK), /* Left switch: MIC */
5612 KEY(5, 4, KEY_MENU), /* Center switch: MIC */
5613};
5614
5615static struct matrix_keymap_data fluid_keymap_data = {
5616 .keymap_size = ARRAY_SIZE(fluid_keymap),
5617 .keymap = fluid_keymap,
5618};
5619
5620static struct pmic8058_keypad_data fluid_keypad_data = {
5621 .input_name = "fluid-keypad",
5622 .input_phys_device = "fluid-keypad/input0",
5623 .num_rows = 6,
5624 .num_cols = 5,
5625 .rows_gpio_start = 8,
5626 .cols_gpio_start = 0,
5627 .debounce_ms = {8, 10},
5628 .scan_delay_ms = 32,
5629 .row_hold_ns = 91500,
5630 .wakeup = 1,
5631 .keymap_data = &fluid_keymap_data,
5632};
5633
5634static struct resource resources_pwrkey[] = {
5635 {
5636 .start = PM8058_PWRKEY_REL_IRQ(PM8058_IRQ_BASE),
5637 .end = PM8058_PWRKEY_REL_IRQ(PM8058_IRQ_BASE),
5638 .flags = IORESOURCE_IRQ,
5639 },
5640 {
5641 .start = PM8058_PWRKEY_PRESS_IRQ(PM8058_IRQ_BASE),
5642 .end = PM8058_PWRKEY_PRESS_IRQ(PM8058_IRQ_BASE),
5643 .flags = IORESOURCE_IRQ,
5644 },
5645};
5646
5647static struct pmic8058_pwrkey_pdata pwrkey_pdata = {
5648 .pull_up = 1,
5649 .kpd_trigger_delay_us = 970,
5650 .wakeup = 1,
5651 .pwrkey_time_ms = 500,
5652};
5653
5654static struct pmic8058_vibrator_pdata pmic_vib_pdata = {
5655 .initial_vibrate_ms = 500,
5656 .level_mV = 3000,
5657 .max_timeout_ms = 15000,
5658};
5659
5660#if defined(CONFIG_PMIC8058_OTHC) || defined(CONFIG_PMIC8058_OTHC_MODULE)
5661#define PM8058_OTHC_CNTR_BASE0 0xA0
5662#define PM8058_OTHC_CNTR_BASE1 0x134
5663#define PM8058_OTHC_CNTR_BASE2 0x137
5664#define PM8058_LINE_IN_DET_GPIO PM8058_GPIO_PM_TO_SYS(18)
5665
5666static struct othc_accessory_info othc_accessories[] = {
5667 {
5668 .accessory = OTHC_SVIDEO_OUT,
5669 .detect_flags = OTHC_MICBIAS_DETECT | OTHC_SWITCH_DETECT
5670 | OTHC_ADC_DETECT,
5671 .key_code = SW_VIDEOOUT_INSERT,
5672 .enabled = false,
5673 .adc_thres = {
5674 .min_threshold = 20,
5675 .max_threshold = 40,
5676 },
5677 },
5678 {
5679 .accessory = OTHC_ANC_HEADPHONE,
5680 .detect_flags = OTHC_MICBIAS_DETECT | OTHC_GPIO_DETECT |
5681 OTHC_SWITCH_DETECT,
5682 .gpio = PM8058_LINE_IN_DET_GPIO,
5683 .active_low = 1,
5684 .key_code = SW_HEADPHONE_INSERT,
5685 .enabled = true,
5686 },
5687 {
5688 .accessory = OTHC_ANC_HEADSET,
5689 .detect_flags = OTHC_MICBIAS_DETECT | OTHC_GPIO_DETECT,
5690 .gpio = PM8058_LINE_IN_DET_GPIO,
5691 .active_low = 1,
5692 .key_code = SW_HEADPHONE_INSERT,
5693 .enabled = true,
5694 },
5695 {
5696 .accessory = OTHC_HEADPHONE,
5697 .detect_flags = OTHC_MICBIAS_DETECT | OTHC_SWITCH_DETECT,
5698 .key_code = SW_HEADPHONE_INSERT,
5699 .enabled = true,
5700 },
5701 {
5702 .accessory = OTHC_MICROPHONE,
5703 .detect_flags = OTHC_GPIO_DETECT,
5704 .gpio = PM8058_LINE_IN_DET_GPIO,
5705 .active_low = 1,
5706 .key_code = SW_MICROPHONE_INSERT,
5707 .enabled = true,
5708 },
5709 {
5710 .accessory = OTHC_HEADSET,
5711 .detect_flags = OTHC_MICBIAS_DETECT,
5712 .key_code = SW_HEADPHONE_INSERT,
5713 .enabled = true,
5714 },
5715};
5716
5717static struct othc_switch_info switch_info[] = {
5718 {
5719 .min_adc_threshold = 0,
5720 .max_adc_threshold = 100,
5721 .key_code = KEY_PLAYPAUSE,
5722 },
5723 {
5724 .min_adc_threshold = 100,
5725 .max_adc_threshold = 200,
5726 .key_code = KEY_REWIND,
5727 },
5728 {
5729 .min_adc_threshold = 200,
5730 .max_adc_threshold = 500,
5731 .key_code = KEY_FASTFORWARD,
5732 },
5733};
5734
5735static struct othc_n_switch_config switch_config = {
5736 .voltage_settling_time_ms = 0,
5737 .num_adc_samples = 3,
5738 .adc_channel = CHANNEL_ADC_HDSET,
5739 .switch_info = switch_info,
5740 .num_keys = ARRAY_SIZE(switch_info),
5741 .default_sw_en = true,
5742 .default_sw_idx = 0,
5743};
5744
5745static struct hsed_bias_config hsed_bias_config = {
5746 /* HSED mic bias config info */
5747 .othc_headset = OTHC_HEADSET_NO,
5748 .othc_lowcurr_thresh_uA = 100,
5749 .othc_highcurr_thresh_uA = 600,
5750 .othc_hyst_prediv_us = 7800,
5751 .othc_period_clkdiv_us = 62500,
5752 .othc_hyst_clk_us = 121000,
5753 .othc_period_clk_us = 312500,
5754 .othc_wakeup = 1,
5755};
5756
5757static struct othc_hsed_config hsed_config_1 = {
5758 .hsed_bias_config = &hsed_bias_config,
5759 /*
5760 * The detection delay and switch reporting delay are
5761 * required to encounter a hardware bug (spurious switch
5762 * interrupts on slow insertion/removal of the headset).
5763 * This will introduce a delay in reporting the accessory
5764 * insertion and removal to the userspace.
5765 */
5766 .detection_delay_ms = 1500,
5767 /* Switch info */
5768 .switch_debounce_ms = 1500,
5769 .othc_support_n_switch = false,
5770 .switch_config = &switch_config,
5771 .ir_gpio = -1,
5772 /* Accessory info */
5773 .accessories_support = true,
5774 .accessories = othc_accessories,
5775 .othc_num_accessories = ARRAY_SIZE(othc_accessories),
5776};
5777
5778static struct othc_regulator_config othc_reg = {
5779 .regulator = "8058_l5",
5780 .max_uV = 2850000,
5781 .min_uV = 2850000,
5782};
5783
5784/* MIC_BIAS0 is configured as normal MIC BIAS */
5785static struct pmic8058_othc_config_pdata othc_config_pdata_0 = {
5786 .micbias_select = OTHC_MICBIAS_0,
5787 .micbias_capability = OTHC_MICBIAS,
5788 .micbias_enable = OTHC_SIGNAL_OFF,
5789 .micbias_regulator = &othc_reg,
5790};
5791
5792/* MIC_BIAS1 is configured as HSED_BIAS for OTHC */
5793static struct pmic8058_othc_config_pdata othc_config_pdata_1 = {
5794 .micbias_select = OTHC_MICBIAS_1,
5795 .micbias_capability = OTHC_MICBIAS_HSED,
5796 .micbias_enable = OTHC_SIGNAL_PWM_TCXO,
5797 .micbias_regulator = &othc_reg,
5798 .hsed_config = &hsed_config_1,
5799 .hsed_name = "8660_handset",
5800};
5801
5802/* MIC_BIAS2 is configured as normal MIC BIAS */
5803static struct pmic8058_othc_config_pdata othc_config_pdata_2 = {
5804 .micbias_select = OTHC_MICBIAS_2,
5805 .micbias_capability = OTHC_MICBIAS,
5806 .micbias_enable = OTHC_SIGNAL_OFF,
5807 .micbias_regulator = &othc_reg,
5808};
5809
5810static struct resource resources_othc_0[] = {
5811 {
5812 .name = "othc_base",
5813 .start = PM8058_OTHC_CNTR_BASE0,
5814 .end = PM8058_OTHC_CNTR_BASE0,
5815 .flags = IORESOURCE_IO,
5816 },
5817};
5818
5819static struct resource resources_othc_1[] = {
5820 {
5821 .start = PM8058_SW_1_IRQ(PM8058_IRQ_BASE),
5822 .end = PM8058_SW_1_IRQ(PM8058_IRQ_BASE),
5823 .flags = IORESOURCE_IRQ,
5824 },
5825 {
5826 .start = PM8058_IR_1_IRQ(PM8058_IRQ_BASE),
5827 .end = PM8058_IR_1_IRQ(PM8058_IRQ_BASE),
5828 .flags = IORESOURCE_IRQ,
5829 },
5830 {
5831 .name = "othc_base",
5832 .start = PM8058_OTHC_CNTR_BASE1,
5833 .end = PM8058_OTHC_CNTR_BASE1,
5834 .flags = IORESOURCE_IO,
5835 },
5836};
5837
5838static struct resource resources_othc_2[] = {
5839 {
5840 .name = "othc_base",
5841 .start = PM8058_OTHC_CNTR_BASE2,
5842 .end = PM8058_OTHC_CNTR_BASE2,
5843 .flags = IORESOURCE_IO,
5844 },
5845};
5846
5847static void __init msm8x60_init_pm8058_othc(void)
5848{
5849 int i;
5850
5851 if (SOCINFO_VERSION_MAJOR(socinfo_get_version()) == 2 ||
5852 machine_is_msm8x60_fluid() || machine_is_msm8x60_fusion() ||
5853 machine_is_msm8x60_fusn_ffa()) {
5854 /* 3-switch headset supported only by V2 FFA and FLUID */
5855 hsed_config_1.accessories_adc_support = true,
5856 /* ADC based accessory detection works only on V2 and FLUID */
5857 hsed_config_1.accessories_adc_channel = CHANNEL_ADC_HDSET,
5858 hsed_config_1.othc_support_n_switch = true;
5859 }
5860
5861 /* IR GPIO is absent on FLUID */
5862 if (machine_is_msm8x60_fluid())
5863 hsed_config_1.ir_gpio = -1;
5864
5865 for (i = 0; i < ARRAY_SIZE(othc_accessories); i++) {
5866 if (machine_is_msm8x60_fluid()) {
5867 switch (othc_accessories[i].accessory) {
5868 case OTHC_ANC_HEADPHONE:
5869 case OTHC_ANC_HEADSET:
5870 othc_accessories[i].gpio = GPIO_HEADSET_DET_N;
5871 break;
5872 case OTHC_MICROPHONE:
5873 othc_accessories[i].enabled = false;
5874 break;
5875 case OTHC_SVIDEO_OUT:
5876 othc_accessories[i].enabled = true;
5877 hsed_config_1.video_out_gpio = GPIO_HS_SW_DIR;
5878 break;
5879 }
5880 }
5881 }
5882}
5883#endif
5884
5885static struct resource resources_pm8058_charger[] = {
5886 { .name = "CHGVAL",
5887 .start = PM8058_CHGVAL_IRQ(PM8058_IRQ_BASE),
5888 .end = PM8058_CHGVAL_IRQ(PM8058_IRQ_BASE),
5889 .flags = IORESOURCE_IRQ,
5890 },
5891 { .name = "CHGINVAL",
5892 .start = PM8058_CHGINVAL_IRQ(PM8058_IRQ_BASE),
5893 .end = PM8058_CHGINVAL_IRQ(PM8058_IRQ_BASE),
5894 .flags = IORESOURCE_IRQ,
5895 },
5896 {
5897 .name = "CHGILIM",
5898 .start = PM8058_CHGILIM_IRQ(PM8058_IRQ_BASE),
5899 .end = PM8058_CHGILIM_IRQ(PM8058_IRQ_BASE),
5900 .flags = IORESOURCE_IRQ,
5901 },
5902 {
5903 .name = "VCP",
5904 .start = PM8058_VCP_IRQ(PM8058_IRQ_BASE),
5905 .end = PM8058_VCP_IRQ(PM8058_IRQ_BASE),
5906 .flags = IORESOURCE_IRQ,
5907 },
5908 {
5909 .name = "ATC_DONE",
5910 .start = PM8058_ATC_DONE_IRQ(PM8058_IRQ_BASE),
5911 .end = PM8058_ATC_DONE_IRQ(PM8058_IRQ_BASE),
5912 .flags = IORESOURCE_IRQ,
5913 },
5914 {
5915 .name = "ATCFAIL",
5916 .start = PM8058_ATCFAIL_IRQ(PM8058_IRQ_BASE),
5917 .end = PM8058_ATCFAIL_IRQ(PM8058_IRQ_BASE),
5918 .flags = IORESOURCE_IRQ,
5919 },
5920 {
5921 .name = "AUTO_CHGDONE",
5922 .start = PM8058_AUTO_CHGDONE_IRQ(PM8058_IRQ_BASE),
5923 .end = PM8058_AUTO_CHGDONE_IRQ(PM8058_IRQ_BASE),
5924 .flags = IORESOURCE_IRQ,
5925 },
5926 {
5927 .name = "AUTO_CHGFAIL",
5928 .start = PM8058_AUTO_CHGFAIL_IRQ(PM8058_IRQ_BASE),
5929 .end = PM8058_AUTO_CHGFAIL_IRQ(PM8058_IRQ_BASE),
5930 .flags = IORESOURCE_IRQ,
5931 },
5932 {
5933 .name = "CHGSTATE",
5934 .start = PM8058_CHGSTATE_IRQ(PM8058_IRQ_BASE),
5935 .end = PM8058_CHGSTATE_IRQ(PM8058_IRQ_BASE),
5936 .flags = IORESOURCE_IRQ,
5937 },
5938 {
5939 .name = "FASTCHG",
5940 .start = PM8058_FASTCHG_IRQ(PM8058_IRQ_BASE),
5941 .end = PM8058_FASTCHG_IRQ(PM8058_IRQ_BASE),
5942 .flags = IORESOURCE_IRQ,
5943 },
5944 {
5945 .name = "CHG_END",
5946 .start = PM8058_CHG_END_IRQ(PM8058_IRQ_BASE),
5947 .end = PM8058_CHG_END_IRQ(PM8058_IRQ_BASE),
5948 .flags = IORESOURCE_IRQ,
5949 },
5950 {
5951 .name = "BATTTEMP",
5952 .start = PM8058_BATTTEMP_IRQ(PM8058_IRQ_BASE),
5953 .end = PM8058_BATTTEMP_IRQ(PM8058_IRQ_BASE),
5954 .flags = IORESOURCE_IRQ,
5955 },
5956 {
5957 .name = "CHGHOT",
5958 .start = PM8058_CHGHOT_IRQ(PM8058_IRQ_BASE),
5959 .end = PM8058_CHGHOT_IRQ(PM8058_IRQ_BASE),
5960 .flags = IORESOURCE_IRQ,
5961 },
5962 {
5963 .name = "CHGTLIMIT",
5964 .start = PM8058_CHGTLIMIT_IRQ(PM8058_IRQ_BASE),
5965 .end = PM8058_CHGTLIMIT_IRQ(PM8058_IRQ_BASE),
5966 .flags = IORESOURCE_IRQ,
5967 },
5968 {
5969 .name = "CHG_GONE",
5970 .start = PM8058_CHG_GONE_IRQ(PM8058_IRQ_BASE),
5971 .end = PM8058_CHG_GONE_IRQ(PM8058_IRQ_BASE),
5972 .flags = IORESOURCE_IRQ,
5973 },
5974 {
5975 .name = "VCPMAJOR",
5976 .start = PM8058_VCPMAJOR_IRQ(PM8058_IRQ_BASE),
5977 .end = PM8058_VCPMAJOR_IRQ(PM8058_IRQ_BASE),
5978 .flags = IORESOURCE_IRQ,
5979 },
5980 {
5981 .name = "VBATDET",
5982 .start = PM8058_VBATDET_IRQ(PM8058_IRQ_BASE),
5983 .end = PM8058_VBATDET_IRQ(PM8058_IRQ_BASE),
5984 .flags = IORESOURCE_IRQ,
5985 },
5986 {
5987 .name = "BATFET",
5988 .start = PM8058_BATFET_IRQ(PM8058_IRQ_BASE),
5989 .end = PM8058_BATFET_IRQ(PM8058_IRQ_BASE),
5990 .flags = IORESOURCE_IRQ,
5991 },
5992 {
5993 .name = "BATT_REPLACE",
5994 .start = PM8058_BATT_REPLACE_IRQ(PM8058_IRQ_BASE),
5995 .end = PM8058_BATT_REPLACE_IRQ(PM8058_IRQ_BASE),
5996 .flags = IORESOURCE_IRQ,
5997 },
5998 {
5999 .name = "BATTCONNECT",
6000 .start = PM8058_BATTCONNECT_IRQ(PM8058_IRQ_BASE),
6001 .end = PM8058_BATTCONNECT_IRQ(PM8058_IRQ_BASE),
6002 .flags = IORESOURCE_IRQ,
6003 },
6004 {
6005 .name = "VBATDET_LOW",
6006 .start = PM8058_VBATDET_LOW_IRQ(PM8058_IRQ_BASE),
6007 .end = PM8058_VBATDET_LOW_IRQ(PM8058_IRQ_BASE),
6008 .flags = IORESOURCE_IRQ,
6009 },
6010};
6011
6012static int pm8058_pwm_config(struct pwm_device *pwm, int ch, int on)
6013{
6014 struct pm8058_gpio pwm_gpio_config = {
6015 .direction = PM_GPIO_DIR_OUT,
6016 .output_buffer = PM_GPIO_OUT_BUF_CMOS,
6017 .output_value = 0,
6018 .pull = PM_GPIO_PULL_NO,
6019 .vin_sel = PM_GPIO_VIN_VPH,
6020 .out_strength = PM_GPIO_STRENGTH_HIGH,
6021 .function = PM_GPIO_FUNC_2,
6022 };
6023
6024 int rc = -EINVAL;
6025 int id, mode, max_mA;
6026
6027 id = mode = max_mA = 0;
6028 switch (ch) {
6029 case 0:
6030 case 1:
6031 case 2:
6032 if (on) {
6033 id = 24 + ch;
6034 rc = pm8058_gpio_config(id - 1, &pwm_gpio_config);
6035 if (rc)
6036 pr_err("%s: pm8058_gpio_config(%d): rc=%d\n",
6037 __func__, id, rc);
6038 }
6039 break;
6040
6041 case 6:
6042 id = PM_PWM_LED_FLASH;
6043 mode = PM_PWM_CONF_PWM1;
6044 max_mA = 300;
6045 break;
6046
6047 case 7:
6048 id = PM_PWM_LED_FLASH1;
6049 mode = PM_PWM_CONF_PWM1;
6050 max_mA = 300;
6051 break;
6052
6053 default:
6054 break;
6055 }
6056
6057 if (ch >= 6 && ch <= 7) {
6058 if (!on) {
6059 mode = PM_PWM_CONF_NONE;
6060 max_mA = 0;
6061 }
6062 rc = pm8058_pwm_config_led(pwm, id, mode, max_mA);
6063 if (rc)
6064 pr_err("%s: pm8058_pwm_config_led(ch=%d): rc=%d\n",
6065 __func__, ch, rc);
6066 }
6067 return rc;
6068
6069}
6070
6071static struct pm8058_pwm_pdata pm8058_pwm_data = {
6072 .config = pm8058_pwm_config,
6073};
6074
6075#define PM8058_GPIO_INT 88
6076
6077static struct pm8058_gpio_platform_data pm8058_gpio_data = {
6078 .gpio_base = PM8058_GPIO_PM_TO_SYS(0),
6079 .irq_base = PM8058_GPIO_IRQ(PM8058_IRQ_BASE, 0),
6080 .init = pm8058_gpios_init,
6081};
6082
6083static struct pm8058_gpio_platform_data pm8058_mpp_data = {
6084 .gpio_base = PM8058_GPIO_PM_TO_SYS(PM8058_GPIOS),
6085 .irq_base = PM8058_MPP_IRQ(PM8058_IRQ_BASE, 0),
6086};
6087
6088static struct resource resources_rtc[] = {
6089 {
6090 .start = PM8058_RTC_IRQ(PM8058_IRQ_BASE),
6091 .end = PM8058_RTC_IRQ(PM8058_IRQ_BASE),
6092 .flags = IORESOURCE_IRQ,
6093 },
6094 {
6095 .start = PM8058_RTC_ALARM_IRQ(PM8058_IRQ_BASE),
6096 .end = PM8058_RTC_ALARM_IRQ(PM8058_IRQ_BASE),
6097 .flags = IORESOURCE_IRQ,
6098 },
6099};
6100
Ashay Jaiswal4d1ab552011-07-15 11:30:49 +05306101static struct pm8058_rtc_platform_data pm8058_rtc_pdata = {
6102 .rtc_alarm_powerup = false,
6103};
6104
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07006105static struct pmic8058_led pmic8058_flash_leds[] = {
6106 [0] = {
6107 .name = "camera:flash0",
6108 .max_brightness = 15,
6109 .id = PMIC8058_ID_FLASH_LED_0,
6110 },
6111 [1] = {
6112 .name = "camera:flash1",
6113 .max_brightness = 15,
6114 .id = PMIC8058_ID_FLASH_LED_1,
6115 },
6116};
6117
6118static struct pmic8058_leds_platform_data pm8058_flash_leds_data = {
6119 .num_leds = ARRAY_SIZE(pmic8058_flash_leds),
6120 .leds = pmic8058_flash_leds,
6121};
6122
Terence Hampsonc0b6dfb2011-07-15 11:07:17 -04006123static struct pmic8058_led pmic8058_dragon_leds[] = {
6124 [0] = {
6125 /* RED */
6126 .name = "led_drv0",
6127 .max_brightness = 15,
6128 .id = PMIC8058_ID_LED_0,
6129 },/* 300 mA flash led0 drv sink */
6130 [1] = {
6131 /* Yellow */
6132 .name = "led_drv1",
6133 .max_brightness = 15,
6134 .id = PMIC8058_ID_LED_1,
6135 },/* 300 mA flash led0 drv sink */
6136 [2] = {
6137 /* Green */
6138 .name = "led_drv2",
6139 .max_brightness = 15,
6140 .id = PMIC8058_ID_LED_2,
6141 },/* 300 mA flash led0 drv sink */
6142 [3] = {
6143 .name = "led_psensor",
6144 .max_brightness = 15,
6145 .id = PMIC8058_ID_LED_KB_LIGHT,
6146 },/* 300 mA flash led0 drv sink */
6147};
6148
6149static struct pmic8058_leds_platform_data pm8058_dragon_leds_data = {
6150 .num_leds = ARRAY_SIZE(pmic8058_dragon_leds),
6151 .leds = pmic8058_dragon_leds,
6152};
6153
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07006154static struct pmic8058_led pmic8058_fluid_flash_leds[] = {
6155 [0] = {
6156 .name = "led:drv0",
6157 .max_brightness = 15,
6158 .id = PMIC8058_ID_FLASH_LED_0,
6159 },/* 300 mA flash led0 drv sink */
6160 [1] = {
6161 .name = "led:drv1",
6162 .max_brightness = 15,
6163 .id = PMIC8058_ID_FLASH_LED_1,
6164 },/* 300 mA flash led1 sink */
6165 [2] = {
6166 .name = "led:drv2",
6167 .max_brightness = 20,
6168 .id = PMIC8058_ID_LED_0,
6169 },/* 40 mA led0 sink */
6170 [3] = {
6171 .name = "keypad:drv",
6172 .max_brightness = 15,
6173 .id = PMIC8058_ID_LED_KB_LIGHT,
6174 },/* 300 mA keypad drv sink */
6175};
6176
6177static struct pmic8058_leds_platform_data pm8058_fluid_flash_leds_data = {
6178 .num_leds = ARRAY_SIZE(pmic8058_fluid_flash_leds),
6179 .leds = pmic8058_fluid_flash_leds,
6180};
6181
6182static struct resource resources_temp_alarm[] = {
6183 {
6184 .start = PM8058_TEMP_ALARM_IRQ(PM8058_IRQ_BASE),
6185 .end = PM8058_TEMP_ALARM_IRQ(PM8058_IRQ_BASE),
6186 .flags = IORESOURCE_IRQ,
6187 },
6188};
6189
6190static struct resource resources_pm8058_misc[] = {
6191 {
6192 .start = PM8058_OSCHALT_IRQ(PM8058_IRQ_BASE),
6193 .end = PM8058_OSCHALT_IRQ(PM8058_IRQ_BASE),
6194 .flags = IORESOURCE_IRQ,
6195 },
6196};
6197
6198static struct resource resources_pm8058_batt_alarm[] = {
6199 {
6200 .start = PM8058_BATT_ALARM_IRQ(PM8058_IRQ_BASE),
6201 .end = PM8058_BATT_ALARM_IRQ(PM8058_IRQ_BASE),
6202 .flags = IORESOURCE_IRQ,
6203 },
6204};
6205
6206#define PM8058_SUBDEV_KPD 0
6207#define PM8058_SUBDEV_LED 1
6208#define PM8058_SUBDEV_VIB 2
6209
6210static struct mfd_cell pm8058_subdevs[] = {
6211 {
6212 .name = "pm8058-keypad",
6213 .id = -1,
6214 .num_resources = ARRAY_SIZE(resources_keypad),
6215 .resources = resources_keypad,
6216 },
6217 { .name = "pm8058-led",
6218 .id = -1,
6219 },
6220 {
6221 .name = "pm8058-vib",
6222 .id = -1,
6223 },
6224 { .name = "pm8058-gpio",
6225 .id = -1,
6226 .platform_data = &pm8058_gpio_data,
6227 .pdata_size = sizeof(pm8058_gpio_data),
6228 },
6229 { .name = "pm8058-mpp",
6230 .id = -1,
6231 .platform_data = &pm8058_mpp_data,
6232 .pdata_size = sizeof(pm8058_mpp_data),
6233 },
6234 { .name = "pm8058-pwrkey",
6235 .id = -1,
6236 .resources = resources_pwrkey,
6237 .num_resources = ARRAY_SIZE(resources_pwrkey),
6238 .platform_data = &pwrkey_pdata,
6239 .pdata_size = sizeof(pwrkey_pdata),
6240 },
6241 {
6242 .name = "pm8058-pwm",
6243 .id = -1,
6244 .platform_data = &pm8058_pwm_data,
6245 .pdata_size = sizeof(pm8058_pwm_data),
6246 },
6247#ifdef CONFIG_SENSORS_MSM_ADC
6248 {
6249 .name = "pm8058-xoadc",
6250 .id = -1,
6251 .num_resources = ARRAY_SIZE(resources_adc),
6252 .resources = resources_adc,
6253 .platform_data = &xoadc_pdata,
6254 .pdata_size = sizeof(xoadc_pdata),
6255 },
6256#endif
6257#if defined(CONFIG_PMIC8058_OTHC) || defined(CONFIG_PMIC8058_OTHC_MODULE)
6258 {
6259 .name = "pm8058-othc",
6260 .id = 0,
6261 .platform_data = &othc_config_pdata_0,
6262 .pdata_size = sizeof(othc_config_pdata_0),
6263 .num_resources = ARRAY_SIZE(resources_othc_0),
6264 .resources = resources_othc_0,
6265 },
6266 {
6267 /* OTHC1 module has headset/switch dection */
6268 .name = "pm8058-othc",
6269 .id = 1,
6270 .num_resources = ARRAY_SIZE(resources_othc_1),
6271 .resources = resources_othc_1,
6272 .platform_data = &othc_config_pdata_1,
6273 .pdata_size = sizeof(othc_config_pdata_1),
6274 },
6275 {
6276 .name = "pm8058-othc",
6277 .id = 2,
6278 .platform_data = &othc_config_pdata_2,
6279 .pdata_size = sizeof(othc_config_pdata_2),
6280 .num_resources = ARRAY_SIZE(resources_othc_2),
6281 .resources = resources_othc_2,
6282 },
6283#endif
6284 {
6285 .name = "pm8058-rtc",
6286 .id = -1,
6287 .num_resources = ARRAY_SIZE(resources_rtc),
6288 .resources = resources_rtc,
Ashay Jaiswal4d1ab552011-07-15 11:30:49 +05306289 .platform_data = &pm8058_rtc_pdata,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07006290 },
6291 {
6292 .name = "pm8058-tm",
6293 .id = -1,
6294 .num_resources = ARRAY_SIZE(resources_temp_alarm),
6295 .resources = resources_temp_alarm,
6296 },
6297 { .name = "pm8058-upl",
6298 .id = -1,
6299 },
6300 {
6301 .name = "pm8058-misc",
6302 .id = -1,
6303 .num_resources = ARRAY_SIZE(resources_pm8058_misc),
6304 .resources = resources_pm8058_misc,
6305 },
6306 { .name = "pm8058-batt-alarm",
6307 .id = -1,
6308 .num_resources = ARRAY_SIZE(resources_pm8058_batt_alarm),
6309 .resources = resources_pm8058_batt_alarm,
6310 },
6311};
6312
Terence Hampson90508a92011-08-09 10:40:08 -04006313static struct pmic8058_charger_data pmic8058_charger_dragon = {
6314 .max_source_current = 1800,
6315 .charger_type = CHG_TYPE_AC,
6316};
6317
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07006318static struct mfd_cell pm8058_charger_sub_dev = {
6319 .name = "pm8058-charger",
6320 .id = -1,
6321 .num_resources = ARRAY_SIZE(resources_pm8058_charger),
6322 .resources = resources_pm8058_charger,
6323};
6324
6325static struct pm8058_platform_data pm8058_platform_data = {
6326 .irq_base = PM8058_IRQ_BASE,
6327
6328 .num_subdevs = ARRAY_SIZE(pm8058_subdevs),
6329 .sub_devices = pm8058_subdevs,
6330 .irq_trigger_flags = IRQF_TRIGGER_LOW,
6331};
6332
6333static struct i2c_board_info pm8058_boardinfo[] __initdata = {
6334 {
6335 I2C_BOARD_INFO("pm8058-core", 0x55),
6336 .irq = MSM_GPIO_TO_INT(PM8058_GPIO_INT),
6337 .platform_data = &pm8058_platform_data,
6338 },
6339};
6340#endif /* CONFIG_PMIC8058 */
6341
6342#if defined(CONFIG_TOUCHDISC_VTD518_SHINETSU) || \
6343 defined(CONFIG_TOUCHDISC_VTD518_SHINETSU_MODULE)
6344#define TDISC_I2C_SLAVE_ADDR 0x67
6345#define PMIC_GPIO_TDISC PM8058_GPIO_PM_TO_SYS(5)
6346#define TDISC_INT PM8058_GPIO_IRQ(PM8058_IRQ_BASE, 5)
6347
6348static const char *vregs_tdisc_name[] = {
6349 "8058_l5",
6350 "8058_s3",
6351};
6352
6353static const int vregs_tdisc_val[] = {
6354 2850000,/* uV */
6355 1800000,
6356};
6357static struct regulator *vregs_tdisc[ARRAY_SIZE(vregs_tdisc_name)];
6358
6359static int tdisc_shinetsu_setup(void)
6360{
6361 int rc, i;
6362
6363 rc = gpio_request(PMIC_GPIO_TDISC, "tdisc_interrupt");
6364 if (rc) {
6365 pr_err("%s: gpio_request failed for PMIC_GPIO_TDISC\n",
6366 __func__);
6367 return rc;
6368 }
6369
6370 rc = gpio_request(GPIO_JOYSTICK_EN, "tdisc_oe");
6371 if (rc) {
6372 pr_err("%s: gpio_request failed for GPIO_JOYSTICK_EN\n",
6373 __func__);
6374 goto fail_gpio_oe;
6375 }
6376
6377 rc = gpio_direction_output(GPIO_JOYSTICK_EN, 1);
6378 if (rc) {
6379 pr_err("%s: gpio_direction_output failed for GPIO_JOYSTICK_EN\n",
6380 __func__);
6381 gpio_free(GPIO_JOYSTICK_EN);
6382 goto fail_gpio_oe;
6383 }
6384
6385 for (i = 0; i < ARRAY_SIZE(vregs_tdisc_name); i++) {
6386 vregs_tdisc[i] = regulator_get(NULL, vregs_tdisc_name[i]);
6387 if (IS_ERR(vregs_tdisc[i])) {
6388 printk(KERN_ERR "%s: regulator get %s failed (%ld)\n",
6389 __func__, vregs_tdisc_name[i],
6390 PTR_ERR(vregs_tdisc[i]));
6391 rc = PTR_ERR(vregs_tdisc[i]);
6392 goto vreg_get_fail;
6393 }
6394
6395 rc = regulator_set_voltage(vregs_tdisc[i],
6396 vregs_tdisc_val[i], vregs_tdisc_val[i]);
6397 if (rc) {
6398 printk(KERN_ERR "%s: regulator_set_voltage() = %d\n",
6399 __func__, rc);
6400 goto vreg_set_voltage_fail;
6401 }
6402 }
6403
6404 return rc;
6405vreg_set_voltage_fail:
6406 i++;
6407vreg_get_fail:
6408 while (i)
6409 regulator_put(vregs_tdisc[--i]);
6410fail_gpio_oe:
6411 gpio_free(PMIC_GPIO_TDISC);
6412 return rc;
6413}
6414
6415static void tdisc_shinetsu_release(void)
6416{
6417 int i;
6418
6419 for (i = 0; i < ARRAY_SIZE(vregs_tdisc_name); i++)
6420 regulator_put(vregs_tdisc[i]);
6421
6422 gpio_free(PMIC_GPIO_TDISC);
6423 gpio_free(GPIO_JOYSTICK_EN);
6424}
6425
6426static int tdisc_shinetsu_enable(void)
6427{
6428 int i, rc = -EINVAL;
6429
6430 for (i = 0; i < ARRAY_SIZE(vregs_tdisc_name); i++) {
6431 rc = regulator_enable(vregs_tdisc[i]);
6432 if (rc < 0) {
6433 printk(KERN_ERR "%s: vreg %s enable failed (%d)\n",
6434 __func__, vregs_tdisc_name[i], rc);
6435 goto vreg_fail;
6436 }
6437 }
6438
6439 /* Enable the OE (output enable) gpio */
6440 gpio_set_value_cansleep(GPIO_JOYSTICK_EN, 1);
6441 /* voltage and gpio stabilization delay */
6442 msleep(50);
6443
6444 return 0;
6445vreg_fail:
6446 while (i)
6447 regulator_disable(vregs_tdisc[--i]);
6448 return rc;
6449}
6450
6451static int tdisc_shinetsu_disable(void)
6452{
6453 int i, rc;
6454
6455 for (i = 0; i < ARRAY_SIZE(vregs_tdisc_name); i++) {
6456 rc = regulator_disable(vregs_tdisc[i]);
6457 if (rc < 0) {
6458 printk(KERN_ERR "%s: vreg %s disable failed (%d)\n",
6459 __func__, vregs_tdisc_name[i], rc);
6460 goto tdisc_reg_fail;
6461 }
6462 }
6463
6464 /* Disable the OE (output enable) gpio */
6465 gpio_set_value_cansleep(GPIO_JOYSTICK_EN, 0);
6466
6467 return 0;
6468
6469tdisc_reg_fail:
6470 while (i)
6471 regulator_enable(vregs_tdisc[--i]);
6472 return rc;
6473}
6474
6475static struct tdisc_abs_values tdisc_abs = {
6476 .x_max = 32,
6477 .y_max = 32,
6478 .x_min = -32,
6479 .y_min = -32,
6480 .pressure_max = 32,
6481 .pressure_min = 0,
6482};
6483
6484static struct tdisc_platform_data tdisc_data = {
6485 .tdisc_setup = tdisc_shinetsu_setup,
6486 .tdisc_release = tdisc_shinetsu_release,
6487 .tdisc_enable = tdisc_shinetsu_enable,
6488 .tdisc_disable = tdisc_shinetsu_disable,
6489 .tdisc_wakeup = 0,
6490 .tdisc_gpio = PMIC_GPIO_TDISC,
6491 .tdisc_report_keys = true,
6492 .tdisc_report_relative = true,
6493 .tdisc_report_absolute = false,
6494 .tdisc_report_wheel = false,
6495 .tdisc_reverse_x = false,
6496 .tdisc_reverse_y = true,
6497 .tdisc_abs = &tdisc_abs,
6498};
6499
6500static struct i2c_board_info msm_i2c_gsbi3_tdisc_info[] = {
6501 {
6502 I2C_BOARD_INFO("vtd518", TDISC_I2C_SLAVE_ADDR),
6503 .irq = TDISC_INT,
6504 .platform_data = &tdisc_data,
6505 },
6506};
6507#endif
6508
6509#define PM_GPIO_CDC_RST_N 20
6510#define GPIO_CDC_RST_N PM8058_GPIO_PM_TO_SYS(PM_GPIO_CDC_RST_N)
6511
6512static struct regulator *vreg_timpani_1;
6513static struct regulator *vreg_timpani_2;
6514
6515static unsigned int msm_timpani_setup_power(void)
6516{
6517 int rc;
6518
6519 vreg_timpani_1 = regulator_get(NULL, "8058_l0");
6520 if (IS_ERR(vreg_timpani_1)) {
6521 pr_err("%s: Unable to get 8058_l0\n", __func__);
6522 return -ENODEV;
6523 }
6524
6525 vreg_timpani_2 = regulator_get(NULL, "8058_s3");
6526 if (IS_ERR(vreg_timpani_2)) {
6527 pr_err("%s: Unable to get 8058_s3\n", __func__);
6528 regulator_put(vreg_timpani_1);
6529 return -ENODEV;
6530 }
6531
6532 rc = regulator_set_voltage(vreg_timpani_1, 1200000, 1200000);
6533 if (rc) {
6534 pr_err("%s: unable to set L0 voltage to 1.2V\n", __func__);
6535 goto fail;
6536 }
6537
6538 rc = regulator_set_voltage(vreg_timpani_2, 1800000, 1800000);
6539 if (rc) {
6540 pr_err("%s: unable to set S3 voltage to 1.8V\n", __func__);
6541 goto fail;
6542 }
6543
6544 rc = regulator_enable(vreg_timpani_1);
6545 if (rc) {
6546 pr_err("%s: Enable regulator 8058_l0 failed\n", __func__);
6547 goto fail;
6548 }
6549
6550 /* The settings for LDO0 should be set such that
6551 * it doesn't require to reset the timpani. */
6552 rc = regulator_set_optimum_mode(vreg_timpani_1, 5000);
6553 if (rc < 0) {
6554 pr_err("Timpani regulator optimum mode setting failed\n");
6555 goto fail;
6556 }
6557
6558 rc = regulator_enable(vreg_timpani_2);
6559 if (rc) {
6560 pr_err("%s: Enable regulator 8058_s3 failed\n", __func__);
6561 regulator_disable(vreg_timpani_1);
6562 goto fail;
6563 }
6564
6565 rc = gpio_request(GPIO_CDC_RST_N, "CDC_RST_N");
6566 if (rc) {
6567 pr_err("%s: GPIO Request %d failed\n", __func__,
6568 GPIO_CDC_RST_N);
6569 regulator_disable(vreg_timpani_1);
6570 regulator_disable(vreg_timpani_2);
6571 goto fail;
6572 } else {
6573 gpio_direction_output(GPIO_CDC_RST_N, 1);
6574 usleep_range(1000, 1050);
6575 gpio_direction_output(GPIO_CDC_RST_N, 0);
6576 usleep_range(1000, 1050);
6577 gpio_direction_output(GPIO_CDC_RST_N, 1);
6578 gpio_free(GPIO_CDC_RST_N);
6579 }
6580 return rc;
6581
6582fail:
6583 regulator_put(vreg_timpani_1);
6584 regulator_put(vreg_timpani_2);
6585 return rc;
6586}
6587
6588static void msm_timpani_shutdown_power(void)
6589{
6590 int rc;
6591
6592 rc = regulator_disable(vreg_timpani_1);
6593 if (rc)
6594 pr_err("%s: Disable regulator 8058_l0 failed\n", __func__);
6595
6596 regulator_put(vreg_timpani_1);
6597
6598 rc = regulator_disable(vreg_timpani_2);
6599 if (rc)
6600 pr_err("%s: Disable regulator 8058_s3 failed\n", __func__);
6601
6602 regulator_put(vreg_timpani_2);
6603}
6604
6605/* Power analog function of codec */
6606static struct regulator *vreg_timpani_cdc_apwr;
6607static int msm_timpani_codec_power(int vreg_on)
6608{
6609 int rc = 0;
6610
6611 if (!vreg_timpani_cdc_apwr) {
6612
6613 vreg_timpani_cdc_apwr = regulator_get(NULL, "8058_s4");
6614
6615 if (IS_ERR(vreg_timpani_cdc_apwr)) {
6616 pr_err("%s: vreg_get failed (%ld)\n",
6617 __func__, PTR_ERR(vreg_timpani_cdc_apwr));
6618 rc = PTR_ERR(vreg_timpani_cdc_apwr);
6619 return rc;
6620 }
6621 }
6622
6623 if (vreg_on) {
6624
6625 rc = regulator_set_voltage(vreg_timpani_cdc_apwr,
6626 2200000, 2200000);
6627 if (rc) {
6628 pr_err("%s: unable to set 8058_s4 voltage to 2.2 V\n",
6629 __func__);
6630 goto vreg_fail;
6631 }
6632
6633 rc = regulator_enable(vreg_timpani_cdc_apwr);
6634 if (rc) {
6635 pr_err("%s: vreg_enable failed %d\n", __func__, rc);
6636 goto vreg_fail;
6637 }
6638 } else {
6639 rc = regulator_disable(vreg_timpani_cdc_apwr);
6640 if (rc) {
6641 pr_err("%s: vreg_disable failed %d\n",
6642 __func__, rc);
6643 goto vreg_fail;
6644 }
6645 }
6646
6647 return 0;
6648
6649vreg_fail:
6650 regulator_put(vreg_timpani_cdc_apwr);
6651 vreg_timpani_cdc_apwr = NULL;
6652 return rc;
6653}
6654
6655static struct marimba_codec_platform_data timpani_codec_pdata = {
6656 .marimba_codec_power = msm_timpani_codec_power,
6657};
6658
6659#define TIMPANI_SLAVE_ID_CDC_ADDR 0X77
6660#define TIMPANI_SLAVE_ID_QMEMBIST_ADDR 0X66
6661
6662static struct marimba_platform_data timpani_pdata = {
6663 .slave_id[MARIMBA_SLAVE_ID_CDC] = TIMPANI_SLAVE_ID_CDC_ADDR,
6664 .slave_id[MARIMBA_SLAVE_ID_QMEMBIST] = TIMPANI_SLAVE_ID_QMEMBIST_ADDR,
6665 .marimba_setup = msm_timpani_setup_power,
6666 .marimba_shutdown = msm_timpani_shutdown_power,
6667 .codec = &timpani_codec_pdata,
6668 .tsadc_ssbi_adap = MARIMBA_SSBI_ADAP,
6669};
6670
6671#define TIMPANI_I2C_SLAVE_ADDR 0xD
6672
6673static struct i2c_board_info msm_i2c_gsbi7_timpani_info[] = {
6674 {
6675 I2C_BOARD_INFO("timpani", TIMPANI_I2C_SLAVE_ADDR),
6676 .platform_data = &timpani_pdata,
6677 },
6678};
6679
Lei Zhou338cab82011-08-19 13:38:17 -04006680#ifdef CONFIG_SND_SOC_WM8903
6681static struct wm8903_platform_data wm8903_pdata = {
6682 .gpio_cfg[2] = 0x3A8,
6683};
6684
6685#define WM8903_I2C_SLAVE_ADDR 0x34
6686static struct i2c_board_info wm8903_codec_i2c_info[] = {
6687 {
6688 I2C_BOARD_INFO("wm8903", WM8903_I2C_SLAVE_ADDR >> 1),
6689 .platform_data = &wm8903_pdata,
6690 },
6691};
6692#endif
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07006693#ifdef CONFIG_PMIC8901
6694
6695#define PM8901_GPIO_INT 91
6696
6697static struct pm8901_gpio_platform_data pm8901_mpp_data = {
6698 .gpio_base = PM8901_GPIO_PM_TO_SYS(0),
6699 .irq_base = PM8901_MPP_IRQ(PM8901_IRQ_BASE, 0),
6700};
6701
6702static struct resource pm8901_temp_alarm[] = {
6703 {
6704 .start = PM8901_TEMP_ALARM_IRQ(PM8901_IRQ_BASE),
6705 .end = PM8901_TEMP_ALARM_IRQ(PM8901_IRQ_BASE),
6706 .flags = IORESOURCE_IRQ,
6707 },
6708 {
6709 .start = PM8901_TEMP_HI_ALARM_IRQ(PM8901_IRQ_BASE),
6710 .end = PM8901_TEMP_HI_ALARM_IRQ(PM8901_IRQ_BASE),
6711 .flags = IORESOURCE_IRQ,
6712 },
6713};
6714
6715/*
6716 * Consumer specific regulator names:
6717 * regulator name consumer dev_name
6718 */
6719static struct regulator_consumer_supply vreg_consumers_8901_MPP0[] = {
6720 REGULATOR_SUPPLY("8901_mpp0", NULL),
6721};
6722static struct regulator_consumer_supply vreg_consumers_8901_USB_OTG[] = {
6723 REGULATOR_SUPPLY("8901_usb_otg", NULL),
6724};
6725static struct regulator_consumer_supply vreg_consumers_8901_HDMI_MVS[] = {
6726 REGULATOR_SUPPLY("8901_hdmi_mvs", NULL),
6727};
6728
6729#define PM8901_VREG_INIT(_id, _min_uV, _max_uV, _modes, _ops, _apply_uV, \
6730 _always_on, _active_high) \
6731 [PM8901_VREG_ID_##_id] = { \
6732 .init_data = { \
6733 .constraints = { \
6734 .valid_modes_mask = _modes, \
6735 .valid_ops_mask = _ops, \
6736 .min_uV = _min_uV, \
6737 .max_uV = _max_uV, \
6738 .input_uV = _min_uV, \
6739 .apply_uV = _apply_uV, \
6740 .always_on = _always_on, \
6741 }, \
6742 .consumer_supplies = vreg_consumers_8901_##_id, \
6743 .num_consumer_supplies = \
6744 ARRAY_SIZE(vreg_consumers_8901_##_id), \
6745 }, \
6746 .active_high = _active_high, \
6747 }
6748
6749#define PM8901_VREG_INIT_MPP(_id, _active_high) \
6750 PM8901_VREG_INIT(_id, 0, 0, REGULATOR_MODE_NORMAL, \
6751 REGULATOR_CHANGE_STATUS, 0, 0, _active_high)
6752
6753#define PM8901_VREG_INIT_VS(_id) \
6754 PM8901_VREG_INIT(_id, 0, 0, REGULATOR_MODE_NORMAL, \
6755 REGULATOR_CHANGE_STATUS, 0, 0, 0)
6756
6757static struct pm8901_vreg_pdata pm8901_vreg_init_pdata[PM8901_VREG_MAX] = {
6758 PM8901_VREG_INIT_MPP(MPP0, 1),
6759
6760 PM8901_VREG_INIT_VS(USB_OTG),
6761 PM8901_VREG_INIT_VS(HDMI_MVS),
6762};
6763
6764#define PM8901_VREG(_id) { \
6765 .name = "pm8901-regulator", \
6766 .id = _id, \
6767 .platform_data = &pm8901_vreg_init_pdata[_id], \
6768 .pdata_size = sizeof(pm8901_vreg_init_pdata[_id]), \
6769}
6770
6771static struct mfd_cell pm8901_subdevs[] = {
6772 { .name = "pm8901-mpp",
6773 .id = -1,
6774 .platform_data = &pm8901_mpp_data,
6775 .pdata_size = sizeof(pm8901_mpp_data),
6776 },
6777 { .name = "pm8901-tm",
6778 .id = -1,
6779 .num_resources = ARRAY_SIZE(pm8901_temp_alarm),
6780 .resources = pm8901_temp_alarm,
6781 },
6782 PM8901_VREG(PM8901_VREG_ID_MPP0),
6783 PM8901_VREG(PM8901_VREG_ID_USB_OTG),
6784 PM8901_VREG(PM8901_VREG_ID_HDMI_MVS),
6785};
6786
6787static struct pm8901_platform_data pm8901_platform_data = {
6788 .irq_base = PM8901_IRQ_BASE,
6789 .num_subdevs = ARRAY_SIZE(pm8901_subdevs),
6790 .sub_devices = pm8901_subdevs,
6791 .irq_trigger_flags = IRQF_TRIGGER_LOW,
6792};
6793
6794static struct i2c_board_info pm8901_boardinfo[] __initdata = {
6795 {
6796 I2C_BOARD_INFO("pm8901-core", 0x55),
6797 .irq = MSM_GPIO_TO_INT(PM8901_GPIO_INT),
6798 .platform_data = &pm8901_platform_data,
6799 },
6800};
6801
6802#endif /* CONFIG_PMIC8901 */
6803
6804#if defined(CONFIG_MARIMBA_CORE) && (defined(CONFIG_GPIO_SX150X) \
6805 || defined(CONFIG_GPIO_SX150X_MODULE))
6806
6807static struct regulator *vreg_bahama;
Zhang Chang Kene1fd3da2011-08-10 08:25:57 -04006808static int msm_bahama_sys_rst = GPIO_MS_SYS_RESET_N;
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07006809
6810struct bahama_config_register{
6811 u8 reg;
6812 u8 value;
6813 u8 mask;
6814};
6815
6816enum version{
6817 VER_1_0,
6818 VER_2_0,
6819 VER_UNSUPPORTED = 0xFF
6820};
6821
6822static u8 read_bahama_ver(void)
6823{
6824 int rc;
6825 struct marimba config = { .mod_id = SLAVE_ID_BAHAMA };
6826 u8 bahama_version;
6827
6828 rc = marimba_read_bit_mask(&config, 0x00, &bahama_version, 1, 0x1F);
6829 if (rc < 0) {
6830 printk(KERN_ERR
6831 "%s: version read failed: %d\n",
6832 __func__, rc);
6833 return VER_UNSUPPORTED;
6834 } else {
6835 printk(KERN_INFO
6836 "%s: version read got: 0x%x\n",
6837 __func__, bahama_version);
6838 }
6839
6840 switch (bahama_version) {
6841 case 0x08: /* varient of bahama v1 */
6842 case 0x10:
6843 case 0x00:
6844 return VER_1_0;
6845 case 0x09: /* variant of bahama v2 */
6846 return VER_2_0;
6847 default:
6848 return VER_UNSUPPORTED;
6849 }
6850}
6851
6852static unsigned int msm_bahama_setup_power(void)
6853{
6854 int rc = 0;
6855 const char *msm_bahama_regulator = "8058_s3";
Zhang Chang Kene1fd3da2011-08-10 08:25:57 -04006856
6857 if (machine_is_msm8x60_dragon())
6858 msm_bahama_sys_rst = GPIO_CDC_RST_N;
6859
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07006860 vreg_bahama = regulator_get(NULL, msm_bahama_regulator);
6861
6862 if (IS_ERR(vreg_bahama)) {
6863 rc = PTR_ERR(vreg_bahama);
6864 pr_err("%s: regulator_get %s = %d\n", __func__,
6865 msm_bahama_regulator, rc);
6866 }
6867
6868 if (!rc)
6869 rc = regulator_set_voltage(vreg_bahama, 1800000, 1800000);
6870 else {
6871 pr_err("%s: regulator_set_voltage %s = %d\n", __func__,
6872 msm_bahama_regulator, rc);
6873 goto unget;
6874 }
6875
6876 if (!rc)
6877 rc = regulator_enable(vreg_bahama);
6878 else {
6879 pr_err("%s: regulator_enable %s = %d\n", __func__,
6880 msm_bahama_regulator, rc);
6881 goto unget;
6882 }
6883
Zhang Chang Kene1fd3da2011-08-10 08:25:57 -04006884 if (!rc) {
6885 rc = gpio_request(msm_bahama_sys_rst, "bahama sys_rst_n");
6886 } else {
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07006887 pr_err("%s: gpio_request %d = %d\n", __func__,
Zhang Chang Kene1fd3da2011-08-10 08:25:57 -04006888 msm_bahama_sys_rst, rc);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07006889 goto unenable;
6890 }
6891
Siddartha Mohanadoss72d796e2011-07-20 22:08:34 -07006892 if (!rc) {
Zhang Chang Kene1fd3da2011-08-10 08:25:57 -04006893 gpio_direction_output(msm_bahama_sys_rst, 0);
Siddartha Mohanadoss72d796e2011-07-20 22:08:34 -07006894 usleep_range(1000, 1050);
Zhang Chang Kene1fd3da2011-08-10 08:25:57 -04006895 gpio_set_value_cansleep(msm_bahama_sys_rst, 1);
Siddartha Mohanadoss72d796e2011-07-20 22:08:34 -07006896 usleep_range(1000, 1050);
6897 } else {
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07006898 pr_err("%s: gpio_direction_output %d = %d\n", __func__,
Zhang Chang Kene1fd3da2011-08-10 08:25:57 -04006899 msm_bahama_sys_rst, rc);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07006900 goto unrequest;
6901 }
6902
6903 return rc;
6904
6905unrequest:
Zhang Chang Kene1fd3da2011-08-10 08:25:57 -04006906 gpio_free(msm_bahama_sys_rst);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07006907unenable:
6908 regulator_disable(vreg_bahama);
6909unget:
6910 regulator_put(vreg_bahama);
6911 return rc;
6912};
6913static unsigned int msm_bahama_shutdown_power(int value)
6914
6915
6916{
Zhang Chang Kene1fd3da2011-08-10 08:25:57 -04006917 gpio_set_value_cansleep(msm_bahama_sys_rst, 0);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07006918
Zhang Chang Kene1fd3da2011-08-10 08:25:57 -04006919 gpio_free(msm_bahama_sys_rst);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07006920
6921 regulator_disable(vreg_bahama);
6922
6923 regulator_put(vreg_bahama);
6924
6925 return 0;
6926};
6927
6928static unsigned int msm_bahama_core_config(int type)
6929{
6930 int rc = 0;
6931
6932 if (type == BAHAMA_ID) {
6933
6934 int i;
6935 struct marimba config = { .mod_id = SLAVE_ID_BAHAMA };
6936
6937 const struct bahama_config_register v20_init[] = {
6938 /* reg, value, mask */
6939 { 0xF4, 0x84, 0xFF }, /* AREG */
6940 { 0xF0, 0x04, 0xFF } /* DREG */
6941 };
6942
6943 if (read_bahama_ver() == VER_2_0) {
6944 for (i = 0; i < ARRAY_SIZE(v20_init); i++) {
6945 u8 value = v20_init[i].value;
6946 rc = marimba_write_bit_mask(&config,
6947 v20_init[i].reg,
6948 &value,
6949 sizeof(v20_init[i].value),
6950 v20_init[i].mask);
6951 if (rc < 0) {
6952 printk(KERN_ERR
6953 "%s: reg %d write failed: %d\n",
6954 __func__, v20_init[i].reg, rc);
6955 return rc;
6956 }
6957 printk(KERN_INFO "%s: reg 0x%02x value 0x%02x"
6958 " mask 0x%02x\n",
6959 __func__, v20_init[i].reg,
6960 v20_init[i].value, v20_init[i].mask);
6961 }
6962 }
6963 }
6964 printk(KERN_INFO "core type: %d\n", type);
6965
6966 return rc;
6967}
6968
6969static struct regulator *fm_regulator_s3;
6970static struct msm_xo_voter *fm_clock;
6971
6972static int fm_radio_setup(struct marimba_fm_platform_data *pdata)
6973{
6974 int rc = 0;
6975 struct pm8058_gpio cfg = {
6976 .direction = PM_GPIO_DIR_IN,
6977 .pull = PM_GPIO_PULL_NO,
6978 .vin_sel = PM_GPIO_VIN_S3,
6979 .function = PM_GPIO_FUNC_NORMAL,
6980 .inv_int_pol = 0,
6981 };
6982
6983 if (!fm_regulator_s3) {
6984 fm_regulator_s3 = regulator_get(NULL, "8058_s3");
6985 if (IS_ERR(fm_regulator_s3)) {
6986 rc = PTR_ERR(fm_regulator_s3);
6987 printk(KERN_ERR "%s: regulator get s3 (%d)\n",
6988 __func__, rc);
6989 goto out;
6990 }
6991 }
6992
6993
6994 rc = regulator_set_voltage(fm_regulator_s3, 1800000, 1800000);
6995 if (rc < 0) {
6996 printk(KERN_ERR "%s: regulator set voltage failed (%d)\n",
6997 __func__, rc);
6998 goto fm_fail_put;
6999 }
7000
7001 rc = regulator_enable(fm_regulator_s3);
7002 if (rc < 0) {
7003 printk(KERN_ERR "%s: regulator s3 enable failed (%d)\n",
7004 __func__, rc);
7005 goto fm_fail_put;
7006 }
7007
7008 /*Vote for XO clock*/
7009 fm_clock = msm_xo_get(MSM_XO_TCXO_D0, "fm_power");
7010
7011 if (IS_ERR(fm_clock)) {
7012 rc = PTR_ERR(fm_clock);
7013 printk(KERN_ERR "%s: Couldn't get TCXO_D0 vote for FM (%d)\n",
7014 __func__, rc);
7015 goto fm_fail_switch;
7016 }
7017
7018 rc = msm_xo_mode_vote(fm_clock, MSM_XO_MODE_ON);
7019 if (rc < 0) {
7020 printk(KERN_ERR "%s: Failed to vote for TCX0_D0 ON (%d)\n",
7021 __func__, rc);
7022 goto fm_fail_vote;
7023 }
7024
7025 /*GPIO 18 on PMIC is FM_IRQ*/
7026 rc = pm8058_gpio_config(FM_GPIO, &cfg);
7027 if (rc) {
7028 printk(KERN_ERR "%s: return val of pm8058_gpio_config: %d\n",
7029 __func__, rc);
7030 goto fm_fail_clock;
7031 }
7032 goto out;
7033
7034fm_fail_clock:
7035 msm_xo_mode_vote(fm_clock, MSM_XO_MODE_OFF);
7036fm_fail_vote:
7037 msm_xo_put(fm_clock);
7038fm_fail_switch:
7039 regulator_disable(fm_regulator_s3);
7040fm_fail_put:
7041 regulator_put(fm_regulator_s3);
7042out:
7043 return rc;
7044};
7045
7046static void fm_radio_shutdown(struct marimba_fm_platform_data *pdata)
7047{
7048 int rc = 0;
7049 if (fm_regulator_s3 != NULL) {
7050 rc = regulator_disable(fm_regulator_s3);
7051 if (rc < 0) {
7052 printk(KERN_ERR "%s: regulator s3 disable (%d)\n",
7053 __func__, rc);
7054 }
7055 regulator_put(fm_regulator_s3);
7056 fm_regulator_s3 = NULL;
7057 }
7058 printk(KERN_ERR "%s: Voting off for XO", __func__);
7059
7060 if (fm_clock != NULL) {
7061 rc = msm_xo_mode_vote(fm_clock, MSM_XO_MODE_OFF);
7062 if (rc < 0) {
7063 printk(KERN_ERR "%s: Voting off XO clock (%d)\n",
7064 __func__, rc);
7065 }
7066 msm_xo_put(fm_clock);
7067 }
7068 printk(KERN_ERR "%s: coming out of fm_radio_shutdown", __func__);
7069}
7070
7071/* Slave id address for FM/CDC/QMEMBIST
7072 * Values can be programmed using Marimba slave id 0
7073 * should there be a conflict with other I2C devices
7074 * */
7075#define BAHAMA_SLAVE_ID_FM_ADDR 0x2A
7076#define BAHAMA_SLAVE_ID_QMEMBIST_ADDR 0x7B
7077
7078static struct marimba_fm_platform_data marimba_fm_pdata = {
7079 .fm_setup = fm_radio_setup,
7080 .fm_shutdown = fm_radio_shutdown,
7081 .irq = PM8058_GPIO_IRQ(PM8058_IRQ_BASE, FM_GPIO),
7082 .is_fm_soc_i2s_master = false,
7083 .config_i2s_gpio = NULL,
7084};
7085
7086/*
7087Just initializing the BAHAMA related slave
7088*/
7089static struct marimba_platform_data marimba_pdata = {
7090 .slave_id[SLAVE_ID_BAHAMA_FM] = BAHAMA_SLAVE_ID_FM_ADDR,
7091 .slave_id[SLAVE_ID_BAHAMA_QMEMBIST] = BAHAMA_SLAVE_ID_QMEMBIST_ADDR,
7092 .bahama_setup = msm_bahama_setup_power,
7093 .bahama_shutdown = msm_bahama_shutdown_power,
7094 .bahama_core_config = msm_bahama_core_config,
7095 .fm = &marimba_fm_pdata,
7096 .tsadc_ssbi_adap = MARIMBA_SSBI_ADAP,
7097};
7098
7099
7100static struct i2c_board_info msm_marimba_board_info[] = {
7101 {
7102 I2C_BOARD_INFO("marimba", 0xc),
7103 .platform_data = &marimba_pdata,
7104 }
7105};
7106#endif /* CONFIG_MAIMBA_CORE */
7107
7108#ifdef CONFIG_I2C
7109#define I2C_SURF 1
7110#define I2C_FFA (1 << 1)
7111#define I2C_RUMI (1 << 2)
7112#define I2C_SIM (1 << 3)
7113#define I2C_FLUID (1 << 4)
Zhang Chang Ken6baadf02011-08-05 09:48:15 -04007114#define I2C_DRAGON (1 << 5)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07007115
7116struct i2c_registry {
7117 u8 machs;
7118 int bus;
7119 struct i2c_board_info *info;
7120 int len;
7121};
7122
7123static struct i2c_registry msm8x60_i2c_devices[] __initdata = {
7124#ifdef CONFIG_PMIC8058
7125 {
Zhang Chang Ken6baadf02011-08-05 09:48:15 -04007126 I2C_SURF | I2C_FFA | I2C_FLUID | I2C_DRAGON,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07007127 MSM_SSBI1_I2C_BUS_ID,
7128 pm8058_boardinfo,
7129 ARRAY_SIZE(pm8058_boardinfo),
7130 },
7131#endif
7132#ifdef CONFIG_PMIC8901
7133 {
Zhang Chang Ken6baadf02011-08-05 09:48:15 -04007134 I2C_SURF | I2C_FFA | I2C_FLUID | I2C_DRAGON,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07007135 MSM_SSBI2_I2C_BUS_ID,
7136 pm8901_boardinfo,
7137 ARRAY_SIZE(pm8901_boardinfo),
7138 },
7139#endif
7140#if defined(CONFIG_GPIO_SX150X) || defined(CONFIG_GPIO_SX150X_MODULE)
7141 {
Zhang Chang Ken6baadf02011-08-05 09:48:15 -04007142 I2C_SURF | I2C_FFA | I2C_DRAGON,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07007143 MSM_GSBI8_QUP_I2C_BUS_ID,
7144 core_expander_i2c_info,
7145 ARRAY_SIZE(core_expander_i2c_info),
7146 },
7147 {
Zhang Chang Ken6baadf02011-08-05 09:48:15 -04007148 I2C_SURF | I2C_FFA | I2C_DRAGON,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07007149 MSM_GSBI8_QUP_I2C_BUS_ID,
7150 docking_expander_i2c_info,
7151 ARRAY_SIZE(docking_expander_i2c_info),
7152 },
7153 {
7154 I2C_SURF,
7155 MSM_GSBI8_QUP_I2C_BUS_ID,
7156 surf_expanders_i2c_info,
7157 ARRAY_SIZE(surf_expanders_i2c_info),
7158 },
7159 {
Zhang Chang Ken6baadf02011-08-05 09:48:15 -04007160 I2C_SURF | I2C_FFA | I2C_DRAGON,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07007161 MSM_GSBI3_QUP_I2C_BUS_ID,
7162 fha_expanders_i2c_info,
7163 ARRAY_SIZE(fha_expanders_i2c_info),
7164 },
7165 {
7166 I2C_FLUID,
7167 MSM_GSBI3_QUP_I2C_BUS_ID,
7168 fluid_expanders_i2c_info,
7169 ARRAY_SIZE(fluid_expanders_i2c_info),
7170 },
7171 {
7172 I2C_FLUID,
7173 MSM_GSBI8_QUP_I2C_BUS_ID,
7174 fluid_core_expander_i2c_info,
7175 ARRAY_SIZE(fluid_core_expander_i2c_info),
7176 },
7177#endif
7178#if defined(CONFIG_TOUCHDISC_VTD518_SHINETSU) || \
7179 defined(CONFIG_TOUCHDISC_VTD518_SHINETSU_MODULE)
7180 {
Zhang Chang Ken6baadf02011-08-05 09:48:15 -04007181 I2C_SURF | I2C_FFA | I2C_FLUID | I2C_DRAGON,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07007182 MSM_GSBI3_QUP_I2C_BUS_ID,
7183 msm_i2c_gsbi3_tdisc_info,
7184 ARRAY_SIZE(msm_i2c_gsbi3_tdisc_info),
7185 },
7186#endif
7187 {
Zhang Chang Ken211df572011-07-05 19:16:39 -04007188 I2C_SURF | I2C_FFA | I2C_FLUID,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07007189 MSM_GSBI3_QUP_I2C_BUS_ID,
7190 cy8ctmg200_board_info,
7191 ARRAY_SIZE(cy8ctmg200_board_info),
7192 },
Zhang Chang Ken211df572011-07-05 19:16:39 -04007193 {
7194 I2C_DRAGON,
7195 MSM_GSBI3_QUP_I2C_BUS_ID,
7196 cy8ctma340_dragon_board_info,
7197 ARRAY_SIZE(cy8ctma340_dragon_board_info),
7198 },
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07007199#if defined(CONFIG_TOUCHSCREEN_CYTTSP_I2C) || \
7200 defined(CONFIG_TOUCHSCREEN_CYTTSP_I2C_MODULE)
7201 {
7202 I2C_FLUID,
7203 MSM_GSBI3_QUP_I2C_BUS_ID,
7204 cyttsp_fluid_info,
7205 ARRAY_SIZE(cyttsp_fluid_info),
7206 },
7207 {
7208 I2C_FFA | I2C_SURF,
7209 MSM_GSBI3_QUP_I2C_BUS_ID,
7210 cyttsp_ffa_info,
7211 ARRAY_SIZE(cyttsp_ffa_info),
7212 },
7213#endif
7214#ifdef CONFIG_MSM_CAMERA
Jilai Wang971f97f2011-07-13 14:25:25 -04007215 {
7216 I2C_SURF | I2C_FFA | I2C_FLUID ,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07007217 MSM_GSBI4_QUP_I2C_BUS_ID,
7218 msm_camera_boardinfo,
7219 ARRAY_SIZE(msm_camera_boardinfo),
7220 },
Jilai Wang971f97f2011-07-13 14:25:25 -04007221 {
7222 I2C_DRAGON,
7223 MSM_GSBI4_QUP_I2C_BUS_ID,
7224 msm_camera_dragon_boardinfo,
7225 ARRAY_SIZE(msm_camera_dragon_boardinfo),
7226 },
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07007227#endif
7228 {
7229 I2C_SURF | I2C_FFA | I2C_FLUID,
7230 MSM_GSBI7_QUP_I2C_BUS_ID,
7231 msm_i2c_gsbi7_timpani_info,
7232 ARRAY_SIZE(msm_i2c_gsbi7_timpani_info),
7233 },
7234#if defined(CONFIG_MARIMBA_CORE)
7235 {
Zhang Chang Kene1fd3da2011-08-10 08:25:57 -04007236 I2C_SURF | I2C_FFA | I2C_FLUID | I2C_DRAGON,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07007237 MSM_GSBI7_QUP_I2C_BUS_ID,
7238 msm_marimba_board_info,
7239 ARRAY_SIZE(msm_marimba_board_info),
7240 },
7241#endif /* CONFIG_MARIMBA_CORE */
7242#ifdef CONFIG_ISL9519_CHARGER
7243 {
7244 I2C_SURF | I2C_FFA,
7245 MSM_GSBI8_QUP_I2C_BUS_ID,
7246 isl_charger_i2c_info,
7247 ARRAY_SIZE(isl_charger_i2c_info),
7248 },
7249#endif
7250#if defined(CONFIG_HAPTIC_ISA1200) || \
7251 defined(CONFIG_HAPTIC_ISA1200_MODULE)
7252 {
7253 I2C_FLUID,
7254 MSM_GSBI8_QUP_I2C_BUS_ID,
7255 msm_isa1200_board_info,
7256 ARRAY_SIZE(msm_isa1200_board_info),
7257 },
7258#endif
7259#if defined(CONFIG_SMB137B_CHARGER) || defined(CONFIG_SMB137B_CHARGER_MODULE)
7260 {
7261 I2C_FLUID,
7262 MSM_GSBI8_QUP_I2C_BUS_ID,
7263 smb137b_charger_i2c_info,
7264 ARRAY_SIZE(smb137b_charger_i2c_info),
7265 },
7266#endif
7267#if defined(CONFIG_BATTERY_BQ27520) || \
7268 defined(CONFIG_BATTERY_BQ27520_MODULE)
7269 {
7270 I2C_FLUID,
7271 MSM_GSBI8_QUP_I2C_BUS_ID,
7272 msm_bq27520_board_info,
7273 ARRAY_SIZE(msm_bq27520_board_info),
7274 },
7275#endif
Lei Zhou338cab82011-08-19 13:38:17 -04007276#if defined(CONFIG_SND_SOC_WM8903) || defined(CONFIG_SND_SOC_WM8903_MODULE)
7277 {
7278 I2C_DRAGON,
7279 MSM_GSBI8_QUP_I2C_BUS_ID,
7280 wm8903_codec_i2c_info,
7281 ARRAY_SIZE(wm8903_codec_i2c_info),
7282 },
7283#endif
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07007284};
7285#endif /* CONFIG_I2C */
7286
7287static void fixup_i2c_configs(void)
7288{
7289#ifdef CONFIG_I2C
7290#if defined(CONFIG_GPIO_SX150X) || defined(CONFIG_GPIO_SX150X_MODULE)
7291 if (machine_is_msm8x60_surf() || machine_is_msm8x60_fusion())
7292 sx150x_data[SX150X_CORE].irq_summary =
7293 PM8058_GPIO_IRQ(PM8058_IRQ_BASE, UI_INT2_N);
Zhang Chang Ken6baadf02011-08-05 09:48:15 -04007294 else if (machine_is_msm8x60_ffa() || machine_is_msm8x60_fusn_ffa() ||
7295 machine_is_msm8x60_dragon())
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07007296 sx150x_data[SX150X_CORE].irq_summary =
7297 PM8058_GPIO_IRQ(PM8058_IRQ_BASE, UI_INT1_N);
7298 else if (machine_is_msm8x60_fluid())
7299 sx150x_data[SX150X_CORE_FLUID].irq_summary =
7300 PM8058_GPIO_IRQ(PM8058_IRQ_BASE, UI_INT1_N);
7301#endif
7302 /*
7303 * Set PMIC 8901 MPP0 active_high to 0 for surf and charm_surf. This
7304 * implies that the regulator connected to MPP0 is enabled when
7305 * MPP0 is low.
7306 */
7307 if (machine_is_msm8x60_surf() || machine_is_msm8x60_fusion())
7308 pm8901_vreg_init_pdata[PM8901_VREG_ID_MPP0].active_high = 0;
7309 else
7310 pm8901_vreg_init_pdata[PM8901_VREG_ID_MPP0].active_high = 1;
7311#endif
7312}
7313
7314static void register_i2c_devices(void)
7315{
7316#ifdef CONFIG_I2C
7317 u8 mach_mask = 0;
7318 int i;
7319
7320 /* Build the matching 'supported_machs' bitmask */
7321 if (machine_is_msm8x60_surf() || machine_is_msm8x60_fusion())
7322 mach_mask = I2C_SURF;
7323 else if (machine_is_msm8x60_ffa() || machine_is_msm8x60_fusn_ffa())
7324 mach_mask = I2C_FFA;
7325 else if (machine_is_msm8x60_rumi3())
7326 mach_mask = I2C_RUMI;
7327 else if (machine_is_msm8x60_sim())
7328 mach_mask = I2C_SIM;
7329 else if (machine_is_msm8x60_fluid())
7330 mach_mask = I2C_FLUID;
Zhang Chang Ken6baadf02011-08-05 09:48:15 -04007331 else if (machine_is_msm8x60_dragon())
7332 mach_mask = I2C_DRAGON;
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07007333 else
7334 pr_err("unmatched machine ID in register_i2c_devices\n");
7335
7336 /* Run the array and install devices as appropriate */
7337 for (i = 0; i < ARRAY_SIZE(msm8x60_i2c_devices); ++i) {
7338 if (msm8x60_i2c_devices[i].machs & mach_mask)
7339 i2c_register_board_info(msm8x60_i2c_devices[i].bus,
7340 msm8x60_i2c_devices[i].info,
7341 msm8x60_i2c_devices[i].len);
7342 }
7343#endif
7344}
7345
7346static void __init msm8x60_init_uart12dm(void)
7347{
7348#if !defined(CONFIG_USB_PEHCI_HCD) && !defined(CONFIG_USB_PEHCI_HCD_MODULE)
7349 /* 0x1D000000 now belongs to EBI2:CS3 i.e. USB ISP Controller */
7350 void *fpga_mem = ioremap_nocache(0x1D000000, SZ_4K);
7351
7352 if (!fpga_mem)
7353 pr_err("%s(): Error getting memory\n", __func__);
7354
7355 /* Advanced mode */
7356 writew(0xFFFF, fpga_mem + 0x15C);
7357 /* FPGA_UART_SEL */
7358 writew(0, fpga_mem + 0x172);
7359 /* FPGA_GPIO_CONFIG_117 */
7360 writew(1, fpga_mem + 0xEA);
7361 /* FPGA_GPIO_CONFIG_118 */
7362 writew(1, fpga_mem + 0xEC);
7363 mb();
7364 iounmap(fpga_mem);
7365#endif
7366}
7367
7368#define MSM_GSBI9_PHYS 0x19900000
7369#define GSBI_DUAL_MODE_CODE 0x60
7370
7371static void __init msm8x60_init_buses(void)
7372{
7373#ifdef CONFIG_I2C_QUP
7374 void *gsbi_mem = ioremap_nocache(0x19C00000, 4);
7375 /* Setting protocol code to 0x60 for dual UART/I2C in GSBI12 */
7376 writel_relaxed(0x6 << 4, gsbi_mem);
7377 /* Ensure protocol code is written before proceeding further */
7378 mb();
7379 iounmap(gsbi_mem);
7380
7381 msm_gsbi3_qup_i2c_device.dev.platform_data = &msm_gsbi3_qup_i2c_pdata;
7382 msm_gsbi4_qup_i2c_device.dev.platform_data = &msm_gsbi4_qup_i2c_pdata;
7383 msm_gsbi7_qup_i2c_device.dev.platform_data = &msm_gsbi7_qup_i2c_pdata;
7384 msm_gsbi8_qup_i2c_device.dev.platform_data = &msm_gsbi8_qup_i2c_pdata;
7385
7386#ifdef CONFIG_MSM_GSBI9_UART
7387 if (machine_is_msm8x60_fusion() || machine_is_msm8x60_fusn_ffa()) {
7388 /* Setting protocol code to 0x60 for dual UART/I2C in GSBI9 */
7389 gsbi_mem = ioremap_nocache(MSM_GSBI9_PHYS, 4);
7390 writel_relaxed(GSBI_DUAL_MODE_CODE, gsbi_mem);
7391 iounmap(gsbi_mem);
7392 msm_gsbi9_qup_i2c_pdata.use_gsbi_shared_mode = 1;
7393 }
7394#endif
7395 msm_gsbi9_qup_i2c_device.dev.platform_data = &msm_gsbi9_qup_i2c_pdata;
7396 msm_gsbi12_qup_i2c_device.dev.platform_data = &msm_gsbi12_qup_i2c_pdata;
7397#endif
7398#if defined(CONFIG_SPI_QUP) || defined(CONFIG_SPI_QUP_MODULE)
7399 msm_gsbi1_qup_spi_device.dev.platform_data = &msm_gsbi1_qup_spi_pdata;
7400#endif
7401#ifdef CONFIG_I2C_SSBI
7402 msm_device_ssbi1.dev.platform_data = &msm_ssbi1_pdata;
7403 msm_device_ssbi2.dev.platform_data = &msm_ssbi2_pdata;
7404 msm_device_ssbi3.dev.platform_data = &msm_ssbi3_pdata;
7405#endif
7406
7407 if (machine_is_msm8x60_fluid()) {
7408#if (defined(CONFIG_USB_EHCI_MSM_72K) && \
7409 (defined(CONFIG_SMB137B_CHARGER) || \
7410 defined(CONFIG_SMB137B_CHARGER_MODULE)))
7411 msm_otg_pdata.vbus_power = msm_hsusb_smb137b_vbus_power;
7412#endif
7413#if defined(CONFIG_SPI_QUP) || defined(CONFIG_SPI_QUP_MODULE)
7414 msm_gsbi10_qup_spi_device.dev.platform_data =
7415 &msm_gsbi10_qup_spi_pdata;
7416#endif
7417 }
7418
7419#if defined(CONFIG_USB_GADGET_MSM_72K) || defined(CONFIG_USB_EHCI_HCD)
7420 /*
7421 * We can not put USB regulators (8058_l6 and 8058_l7) in LPM
7422 * when we depend on USB PHY for VBUS/ID notifications. VBUS
7423 * and ID notifications are available only on V2 surf and FFA
7424 * with a hardware workaround.
7425 */
7426 if (SOCINFO_VERSION_MAJOR(socinfo_get_version()) == 2 &&
7427 (machine_is_msm8x60_surf() ||
7428 (machine_is_msm8x60_ffa() &&
7429 pmic_id_notif_supported)))
7430 msm_otg_pdata.phy_can_powercollapse = 1;
7431 msm_device_otg.dev.platform_data = &msm_otg_pdata;
7432#endif
7433
7434#ifdef CONFIG_USB_GADGET_MSM_72K
7435 msm_device_gadget_peripheral.dev.platform_data = &msm_gadget_pdata;
7436#endif
7437
7438#ifdef CONFIG_SERIAL_MSM_HS
7439 msm_uart_dm1_pdata.wakeup_irq = gpio_to_irq(54); /* GSBI6(2) */
7440 msm_device_uart_dm1.dev.platform_data = &msm_uart_dm1_pdata;
7441#endif
7442#ifdef CONFIG_MSM_GSBI9_UART
7443 if (machine_is_msm8x60_fusion() || machine_is_msm8x60_fusn_ffa()) {
7444 msm_device_uart_gsbi9 = msm_add_gsbi9_uart();
7445 if (IS_ERR(msm_device_uart_gsbi9))
7446 pr_err("%s(): Failed to create uart gsbi9 device\n",
7447 __func__);
7448 }
7449#endif
7450
7451#ifdef CONFIG_MSM_BUS_SCALING
7452
7453 /* RPM calls are only enabled on V2 */
7454 if (SOCINFO_VERSION_MAJOR(socinfo_get_version()) == 2) {
7455 msm_bus_apps_fabric_pdata.rpm_enabled = 1;
7456 msm_bus_sys_fabric_pdata.rpm_enabled = 1;
7457 msm_bus_mm_fabric_pdata.rpm_enabled = 1;
7458 msm_bus_sys_fpb_pdata.rpm_enabled = 1;
7459 msm_bus_cpss_fpb_pdata.rpm_enabled = 1;
7460 }
7461
7462 msm_bus_apps_fabric.dev.platform_data = &msm_bus_apps_fabric_pdata;
7463 msm_bus_sys_fabric.dev.platform_data = &msm_bus_sys_fabric_pdata;
7464 msm_bus_mm_fabric.dev.platform_data = &msm_bus_mm_fabric_pdata;
7465 msm_bus_sys_fpb.dev.platform_data = &msm_bus_sys_fpb_pdata;
7466 msm_bus_cpss_fpb.dev.platform_data = &msm_bus_cpss_fpb_pdata;
7467#endif
7468}
7469
7470static void __init msm8x60_map_io(void)
7471{
7472 msm_shared_ram_phys = MSM_SHARED_RAM_PHYS;
7473 msm_map_msm8x60_io();
Jeff Ohlstein3a77f9f2011-09-06 14:50:20 -07007474
7475 if (socinfo_init() < 0)
7476 pr_err("socinfo_init() failed!\n");
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07007477}
7478
7479/*
7480 * Most segments of the EBI2 bus are disabled by default.
7481 */
7482static void __init msm8x60_init_ebi2(void)
7483{
7484 uint32_t ebi2_cfg;
7485 void *ebi2_cfg_ptr;
Terence Hampsonb36a38c2011-09-19 19:10:40 -04007486 struct clk *mem_clk = clk_get_sys("msm_ebi2", "mem_clk");
7487
7488 if (IS_ERR(mem_clk)) {
7489 pr_err("%s: clk_get_sys(%s,%s), failed", __func__,
7490 "msm_ebi2", "mem_clk");
7491 return;
7492 }
7493 clk_enable(mem_clk);
7494 clk_put(mem_clk);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07007495
7496 ebi2_cfg_ptr = ioremap_nocache(0x1a100000, sizeof(uint32_t));
7497 if (ebi2_cfg_ptr != 0) {
7498 ebi2_cfg = readl_relaxed(ebi2_cfg_ptr);
7499
7500 if (machine_is_msm8x60_surf() || machine_is_msm8x60_ffa() ||
Zhang Chang Ken6baadf02011-08-05 09:48:15 -04007501 machine_is_msm8x60_fluid() ||
7502 machine_is_msm8x60_dragon())
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07007503 ebi2_cfg |= (1 << 4) | (1 << 5); /* CS2, CS3 */
7504 else if (machine_is_msm8x60_sim())
7505 ebi2_cfg |= (1 << 4); /* CS2 */
7506 else if (machine_is_msm8x60_rumi3())
7507 ebi2_cfg |= (1 << 5); /* CS3 */
7508
7509 writel_relaxed(ebi2_cfg, ebi2_cfg_ptr);
7510 iounmap(ebi2_cfg_ptr);
7511 }
7512
7513 if (machine_is_msm8x60_surf() || machine_is_msm8x60_ffa() ||
Zhang Chang Ken6baadf02011-08-05 09:48:15 -04007514 machine_is_msm8x60_fluid() || machine_is_msm8x60_dragon()) {
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07007515 ebi2_cfg_ptr = ioremap_nocache(0x1a110000, SZ_4K);
7516 if (ebi2_cfg_ptr != 0) {
7517 /* EBI2_XMEM_CFG:PWRSAVE_MODE off */
7518 writel_relaxed(0UL, ebi2_cfg_ptr);
7519
7520 /* CS2: Delay 9 cycles (140ns@64MHz) between SMSC
7521 * LAN9221 Ethernet controller reads and writes.
7522 * The lowest 4 bits are the read delay, the next
7523 * 4 are the write delay. */
7524 writel_relaxed(0x031F1C99, ebi2_cfg_ptr + 0x10);
7525#if defined(CONFIG_USB_PEHCI_HCD) || defined(CONFIG_USB_PEHCI_HCD_MODULE)
7526 /*
7527 * RECOVERY=5, HOLD_WR=1
7528 * INIT_LATENCY_WR=1, INIT_LATENCY_RD=1
7529 * WAIT_WR=1, WAIT_RD=2
7530 */
7531 writel_relaxed(0x51010112, ebi2_cfg_ptr + 0x14);
7532 /*
7533 * HOLD_RD=1
7534 * ADV_OE_RECOVERY=0, ADDR_HOLD_ENA=1
7535 */
7536 writel_relaxed(0x01000020, ebi2_cfg_ptr + 0x34);
7537#else
7538 /* EBI2 CS3 muxed address/data,
7539 * two cyc addr enable */
7540 writel_relaxed(0xA3030020, ebi2_cfg_ptr + 0x34);
7541
7542#endif
7543 iounmap(ebi2_cfg_ptr);
7544 }
7545 }
7546}
7547
7548static void __init msm8x60_configure_smc91x(void)
7549{
7550 if (machine_is_msm8x60_sim()) {
7551
7552 smc91x_resources[0].start = 0x1b800300;
7553 smc91x_resources[0].end = 0x1b8003ff;
7554
7555 smc91x_resources[1].start = (NR_MSM_IRQS + 40);
7556 smc91x_resources[1].end = (NR_MSM_IRQS + 40);
7557
7558 } else if (machine_is_msm8x60_rumi3()) {
7559
7560 smc91x_resources[0].start = 0x1d000300;
7561 smc91x_resources[0].end = 0x1d0003ff;
7562
7563 smc91x_resources[1].start = TLMM_MSM_DIR_CONN_IRQ_0;
7564 smc91x_resources[1].end = TLMM_MSM_DIR_CONN_IRQ_0;
7565 }
7566}
7567
7568static void __init msm8x60_init_tlmm(void)
7569{
7570 if (machine_is_msm8x60_rumi3())
7571 msm_gpio_install_direct_irq(0, 0, 1);
7572}
7573
7574#if (defined(CONFIG_MMC_MSM_SDC1_SUPPORT)\
7575 || defined(CONFIG_MMC_MSM_SDC2_SUPPORT)\
7576 || defined(CONFIG_MMC_MSM_SDC3_SUPPORT)\
7577 || defined(CONFIG_MMC_MSM_SDC4_SUPPORT)\
7578 || defined(CONFIG_MMC_MSM_SDC5_SUPPORT))
7579
7580/* 8x60 is having 5 SDCC controllers */
7581#define MAX_SDCC_CONTROLLER 5
7582
7583struct msm_sdcc_gpio {
7584 /* maximum 10 GPIOs per SDCC controller */
7585 s16 no;
7586 /* name of this GPIO */
7587 const char *name;
7588 bool always_on;
7589 bool is_enabled;
7590};
7591
7592#ifdef CONFIG_MMC_MSM_SDC1_SUPPORT
7593static struct msm_sdcc_gpio sdc1_gpio_cfg[] = {
7594 {159, "sdc1_dat_0"},
7595 {160, "sdc1_dat_1"},
7596 {161, "sdc1_dat_2"},
7597 {162, "sdc1_dat_3"},
7598#ifdef CONFIG_MMC_MSM_SDC1_8_BIT_SUPPORT
7599 {163, "sdc1_dat_4"},
7600 {164, "sdc1_dat_5"},
7601 {165, "sdc1_dat_6"},
7602 {166, "sdc1_dat_7"},
7603#endif
7604 {167, "sdc1_clk"},
7605 {168, "sdc1_cmd"}
7606};
7607#endif
7608
7609#ifdef CONFIG_MMC_MSM_SDC2_SUPPORT
7610static struct msm_sdcc_gpio sdc2_gpio_cfg[] = {
7611 {143, "sdc2_dat_0"},
7612 {144, "sdc2_dat_1", 1},
7613 {145, "sdc2_dat_2"},
7614 {146, "sdc2_dat_3"},
7615#ifdef CONFIG_MMC_MSM_SDC2_8_BIT_SUPPORT
7616 {147, "sdc2_dat_4"},
7617 {148, "sdc2_dat_5"},
7618 {149, "sdc2_dat_6"},
7619 {150, "sdc2_dat_7"},
7620#endif
7621 {151, "sdc2_cmd"},
7622 {152, "sdc2_clk", 1}
7623};
7624#endif
7625
7626#ifdef CONFIG_MMC_MSM_SDC5_SUPPORT
7627static struct msm_sdcc_gpio sdc5_gpio_cfg[] = {
7628 {95, "sdc5_cmd"},
7629 {96, "sdc5_dat_3"},
7630 {97, "sdc5_clk", 1},
7631 {98, "sdc5_dat_2"},
7632 {99, "sdc5_dat_1", 1},
7633 {100, "sdc5_dat_0"}
7634};
7635#endif
7636
7637struct msm_sdcc_pad_pull_cfg {
7638 enum msm_tlmm_pull_tgt pull;
7639 u32 pull_val;
7640};
7641
7642struct msm_sdcc_pad_drv_cfg {
7643 enum msm_tlmm_hdrive_tgt drv;
7644 u32 drv_val;
7645};
7646
7647#ifdef CONFIG_MMC_MSM_SDC3_SUPPORT
7648static struct msm_sdcc_pad_drv_cfg sdc3_pad_on_drv_cfg[] = {
7649 {TLMM_HDRV_SDC3_CLK, GPIO_CFG_8MA},
7650 {TLMM_HDRV_SDC3_CMD, GPIO_CFG_8MA},
7651 {TLMM_HDRV_SDC3_DATA, GPIO_CFG_8MA}
7652};
7653
7654static struct msm_sdcc_pad_pull_cfg sdc3_pad_on_pull_cfg[] = {
7655 {TLMM_PULL_SDC3_CMD, GPIO_CFG_PULL_UP},
7656 {TLMM_PULL_SDC3_DATA, GPIO_CFG_PULL_UP}
7657};
7658
7659static struct msm_sdcc_pad_drv_cfg sdc3_pad_off_drv_cfg[] = {
7660 {TLMM_HDRV_SDC3_CLK, GPIO_CFG_2MA},
7661 {TLMM_HDRV_SDC3_CMD, GPIO_CFG_2MA},
7662 {TLMM_HDRV_SDC3_DATA, GPIO_CFG_2MA}
7663};
7664
7665static struct msm_sdcc_pad_pull_cfg sdc3_pad_off_pull_cfg[] = {
7666 {TLMM_PULL_SDC3_CMD, GPIO_CFG_PULL_DOWN},
7667 {TLMM_PULL_SDC3_DATA, GPIO_CFG_PULL_DOWN}
7668};
7669#endif
7670
7671#ifdef CONFIG_MMC_MSM_SDC4_SUPPORT
7672static struct msm_sdcc_pad_drv_cfg sdc4_pad_on_drv_cfg[] = {
7673 {TLMM_HDRV_SDC4_CLK, GPIO_CFG_8MA},
7674 {TLMM_HDRV_SDC4_CMD, GPIO_CFG_8MA},
7675 {TLMM_HDRV_SDC4_DATA, GPIO_CFG_8MA}
7676};
7677
7678static struct msm_sdcc_pad_pull_cfg sdc4_pad_on_pull_cfg[] = {
7679 {TLMM_PULL_SDC4_CMD, GPIO_CFG_PULL_UP},
7680 {TLMM_PULL_SDC4_DATA, GPIO_CFG_PULL_UP}
7681};
7682
7683static struct msm_sdcc_pad_drv_cfg sdc4_pad_off_drv_cfg[] = {
7684 {TLMM_HDRV_SDC4_CLK, GPIO_CFG_2MA},
7685 {TLMM_HDRV_SDC4_CMD, GPIO_CFG_2MA},
7686 {TLMM_HDRV_SDC4_DATA, GPIO_CFG_2MA}
7687};
7688
7689static struct msm_sdcc_pad_pull_cfg sdc4_pad_off_pull_cfg[] = {
7690 {TLMM_PULL_SDC4_CMD, GPIO_CFG_PULL_DOWN},
7691 {TLMM_PULL_SDC4_DATA, GPIO_CFG_PULL_DOWN}
7692};
7693#endif
7694
7695struct msm_sdcc_pin_cfg {
7696 /*
7697 * = 1 if controller pins are using gpios
7698 * = 0 if controller has dedicated MSM pins
7699 */
7700 u8 is_gpio;
7701 u8 cfg_sts;
7702 u8 gpio_data_size;
7703 struct msm_sdcc_gpio *gpio_data;
7704 struct msm_sdcc_pad_drv_cfg *pad_drv_on_data;
7705 struct msm_sdcc_pad_drv_cfg *pad_drv_off_data;
7706 struct msm_sdcc_pad_pull_cfg *pad_pull_on_data;
7707 struct msm_sdcc_pad_pull_cfg *pad_pull_off_data;
7708 u8 pad_drv_data_size;
7709 u8 pad_pull_data_size;
7710 u8 sdio_lpm_gpio_cfg;
7711};
7712
7713
7714static struct msm_sdcc_pin_cfg sdcc_pin_cfg_data[MAX_SDCC_CONTROLLER] = {
7715#ifdef CONFIG_MMC_MSM_SDC1_SUPPORT
7716 [0] = {
7717 .is_gpio = 1,
7718 .gpio_data_size = ARRAY_SIZE(sdc1_gpio_cfg),
7719 .gpio_data = sdc1_gpio_cfg
7720 },
7721#endif
7722#ifdef CONFIG_MMC_MSM_SDC2_SUPPORT
7723 [1] = {
7724 .is_gpio = 1,
7725 .gpio_data_size = ARRAY_SIZE(sdc2_gpio_cfg),
7726 .gpio_data = sdc2_gpio_cfg
7727 },
7728#endif
7729#ifdef CONFIG_MMC_MSM_SDC3_SUPPORT
7730 [2] = {
7731 .is_gpio = 0,
7732 .pad_drv_on_data = sdc3_pad_on_drv_cfg,
7733 .pad_drv_off_data = sdc3_pad_off_drv_cfg,
7734 .pad_pull_on_data = sdc3_pad_on_pull_cfg,
7735 .pad_pull_off_data = sdc3_pad_off_pull_cfg,
7736 .pad_drv_data_size = ARRAY_SIZE(sdc3_pad_on_drv_cfg),
7737 .pad_pull_data_size = ARRAY_SIZE(sdc3_pad_on_pull_cfg)
7738 },
7739#endif
7740#ifdef CONFIG_MMC_MSM_SDC4_SUPPORT
7741 [3] = {
7742 .is_gpio = 0,
7743 .pad_drv_on_data = sdc4_pad_on_drv_cfg,
7744 .pad_drv_off_data = sdc4_pad_off_drv_cfg,
7745 .pad_pull_on_data = sdc4_pad_on_pull_cfg,
7746 .pad_pull_off_data = sdc4_pad_off_pull_cfg,
7747 .pad_drv_data_size = ARRAY_SIZE(sdc4_pad_on_drv_cfg),
7748 .pad_pull_data_size = ARRAY_SIZE(sdc4_pad_on_pull_cfg)
7749 },
7750#endif
7751#ifdef CONFIG_MMC_MSM_SDC5_SUPPORT
7752 [4] = {
7753 .is_gpio = 1,
7754 .gpio_data_size = ARRAY_SIZE(sdc5_gpio_cfg),
7755 .gpio_data = sdc5_gpio_cfg
7756 }
7757#endif
7758};
7759
7760static int msm_sdcc_setup_gpio(int dev_id, unsigned int enable)
7761{
7762 int rc = 0;
7763 struct msm_sdcc_pin_cfg *curr;
7764 int n;
7765
7766 curr = &sdcc_pin_cfg_data[dev_id - 1];
7767 if (!curr->gpio_data)
7768 goto out;
7769
7770 for (n = 0; n < curr->gpio_data_size; n++) {
7771 if (enable) {
7772
7773 if (curr->gpio_data[n].always_on &&
7774 curr->gpio_data[n].is_enabled)
7775 continue;
7776 pr_debug("%s: enable: %s\n", __func__,
7777 curr->gpio_data[n].name);
7778 rc = gpio_request(curr->gpio_data[n].no,
7779 curr->gpio_data[n].name);
7780 if (rc) {
7781 pr_err("%s: gpio_request(%d, %s)"
7782 "failed", __func__,
7783 curr->gpio_data[n].no,
7784 curr->gpio_data[n].name);
7785 goto free_gpios;
7786 }
7787 /* set direction as output for all GPIOs */
7788 rc = gpio_direction_output(
7789 curr->gpio_data[n].no, 1);
7790 if (rc) {
7791 pr_err("%s: gpio_direction_output"
7792 "(%d, 1) failed\n", __func__,
7793 curr->gpio_data[n].no);
7794 goto free_gpios;
7795 }
7796 curr->gpio_data[n].is_enabled = 1;
7797 } else {
7798 /*
7799 * now free this GPIO which will put GPIO
7800 * in low power mode and will also put GPIO
7801 * in input mode
7802 */
7803 if (curr->gpio_data[n].always_on)
7804 continue;
7805 pr_debug("%s: disable: %s\n", __func__,
7806 curr->gpio_data[n].name);
7807 gpio_free(curr->gpio_data[n].no);
7808 curr->gpio_data[n].is_enabled = 0;
7809 }
7810 }
7811 curr->cfg_sts = enable;
7812 goto out;
7813
7814free_gpios:
7815 for (; n >= 0; n--)
7816 gpio_free(curr->gpio_data[n].no);
7817out:
7818 return rc;
7819}
7820
7821static int msm_sdcc_setup_pad(int dev_id, unsigned int enable)
7822{
7823 int rc = 0;
7824 struct msm_sdcc_pin_cfg *curr;
7825 int n;
7826
7827 curr = &sdcc_pin_cfg_data[dev_id - 1];
7828 if (!curr->pad_drv_on_data || !curr->pad_pull_on_data)
7829 goto out;
7830
7831 if (enable) {
7832 /*
7833 * set up the normal driver strength and
7834 * pull config for pads
7835 */
7836 for (n = 0; n < curr->pad_drv_data_size; n++) {
7837 if (curr->sdio_lpm_gpio_cfg) {
7838 if (curr->pad_drv_on_data[n].drv ==
7839 TLMM_HDRV_SDC4_DATA)
7840 continue;
7841 }
7842 msm_tlmm_set_hdrive(curr->pad_drv_on_data[n].drv,
7843 curr->pad_drv_on_data[n].drv_val);
7844 }
7845 for (n = 0; n < curr->pad_pull_data_size; n++) {
7846 if (curr->sdio_lpm_gpio_cfg) {
7847 if (curr->pad_pull_on_data[n].pull ==
7848 TLMM_PULL_SDC4_DATA)
7849 continue;
7850 }
7851 msm_tlmm_set_pull(curr->pad_pull_on_data[n].pull,
7852 curr->pad_pull_on_data[n].pull_val);
7853 }
7854 } else {
7855 /* set the low power config for pads */
7856 for (n = 0; n < curr->pad_drv_data_size; n++) {
7857 if (curr->sdio_lpm_gpio_cfg) {
7858 if (curr->pad_drv_off_data[n].drv ==
7859 TLMM_HDRV_SDC4_DATA)
7860 continue;
7861 }
7862 msm_tlmm_set_hdrive(
7863 curr->pad_drv_off_data[n].drv,
7864 curr->pad_drv_off_data[n].drv_val);
7865 }
7866 for (n = 0; n < curr->pad_pull_data_size; n++) {
7867 if (curr->sdio_lpm_gpio_cfg) {
7868 if (curr->pad_pull_off_data[n].pull ==
7869 TLMM_PULL_SDC4_DATA)
7870 continue;
7871 }
7872 msm_tlmm_set_pull(
7873 curr->pad_pull_off_data[n].pull,
7874 curr->pad_pull_off_data[n].pull_val);
7875 }
7876 }
7877 curr->cfg_sts = enable;
7878out:
7879 return rc;
7880}
7881
7882struct sdcc_reg {
7883 /* VDD/VCC/VCCQ regulator name on PMIC8058/PMIC8089*/
7884 const char *reg_name;
7885 /*
7886 * is set voltage supported for this regulator?
7887 * 0 = not supported, 1 = supported
7888 */
7889 unsigned char set_voltage_sup;
7890 /* voltage level to be set */
7891 unsigned int level;
7892 /* VDD/VCC/VCCQ voltage regulator handle */
7893 struct regulator *reg;
7894 /* is this regulator enabled? */
7895 bool enabled;
7896 /* is this regulator needs to be always on? */
7897 bool always_on;
7898 /* is operating power mode setting required for this regulator? */
7899 bool op_pwr_mode_sup;
7900 /* Load values for low power and high power mode */
7901 unsigned int lpm_uA;
7902 unsigned int hpm_uA;
7903};
7904/* all SDCC controllers requires VDD/VCC voltage */
7905static struct sdcc_reg sdcc_vdd_reg_data[MAX_SDCC_CONTROLLER];
7906/* only SDCC1 requires VCCQ voltage */
7907static struct sdcc_reg sdcc_vccq_reg_data[1];
7908/* all SDCC controllers may require voting for VDD PAD voltage */
7909static struct sdcc_reg sdcc_vddp_reg_data[MAX_SDCC_CONTROLLER];
7910
7911struct sdcc_reg_data {
7912 struct sdcc_reg *vdd_data; /* keeps VDD/VCC regulator info */
7913 struct sdcc_reg *vccq_data; /* keeps VCCQ regulator info */
7914 struct sdcc_reg *vddp_data; /* keeps VDD Pad regulator info */
7915 unsigned char sts; /* regulator enable/disable status */
7916};
7917/* msm8x60 have 5 SDCC controllers */
7918static struct sdcc_reg_data sdcc_vreg_data[MAX_SDCC_CONTROLLER];
7919
7920static int msm_sdcc_vreg_init_reg(struct sdcc_reg *vreg)
7921{
7922 int rc = 0;
7923
7924 /* Get the regulator handle */
7925 vreg->reg = regulator_get(NULL, vreg->reg_name);
7926 if (IS_ERR(vreg->reg)) {
7927 rc = PTR_ERR(vreg->reg);
7928 pr_err("%s: regulator_get(%s) failed. rc=%d\n",
7929 __func__, vreg->reg_name, rc);
7930 goto out;
7931 }
7932
7933 /* Set the voltage level if required */
7934 if (vreg->set_voltage_sup) {
7935 rc = regulator_set_voltage(vreg->reg, vreg->level,
7936 vreg->level);
7937 if (rc) {
7938 pr_err("%s: regulator_set_voltage(%s) failed rc=%d\n",
7939 __func__, vreg->reg_name, rc);
7940 goto vreg_put;
7941 }
7942 }
7943 goto out;
7944
7945vreg_put:
7946 regulator_put(vreg->reg);
7947out:
7948 return rc;
7949}
7950
7951static inline void msm_sdcc_vreg_deinit_reg(struct sdcc_reg *vreg)
7952{
7953 regulator_put(vreg->reg);
7954}
7955
7956/* this init function should be called only once for each SDCC */
7957static int msm_sdcc_vreg_init(int dev_id, unsigned char init)
7958{
7959 int rc = 0;
7960 struct sdcc_reg *curr_vdd_reg, *curr_vccq_reg, *curr_vddp_reg;
7961 struct sdcc_reg_data *curr;
7962
7963 curr = &sdcc_vreg_data[dev_id - 1];
7964 curr_vdd_reg = curr->vdd_data;
7965 curr_vccq_reg = curr->vccq_data;
7966 curr_vddp_reg = curr->vddp_data;
7967
7968 if (init) {
7969 /*
7970 * get the regulator handle from voltage regulator framework
7971 * and then try to set the voltage level for the regulator
7972 */
7973 if (curr_vdd_reg) {
7974 rc = msm_sdcc_vreg_init_reg(curr_vdd_reg);
7975 if (rc)
7976 goto out;
7977 }
7978 if (curr_vccq_reg) {
7979 rc = msm_sdcc_vreg_init_reg(curr_vccq_reg);
7980 if (rc)
7981 goto vdd_reg_deinit;
7982 }
7983 if (curr_vddp_reg) {
7984 rc = msm_sdcc_vreg_init_reg(curr_vddp_reg);
7985 if (rc)
7986 goto vccq_reg_deinit;
7987 }
7988 goto out;
7989 } else
7990 /* deregister with all regulators from regulator framework */
7991 goto vddp_reg_deinit;
7992
7993vddp_reg_deinit:
7994 if (curr_vddp_reg)
7995 msm_sdcc_vreg_deinit_reg(curr_vddp_reg);
7996vccq_reg_deinit:
7997 if (curr_vccq_reg)
7998 msm_sdcc_vreg_deinit_reg(curr_vccq_reg);
7999vdd_reg_deinit:
8000 if (curr_vdd_reg)
8001 msm_sdcc_vreg_deinit_reg(curr_vdd_reg);
8002out:
8003 return rc;
8004}
8005
8006static int msm_sdcc_vreg_enable(struct sdcc_reg *vreg)
8007{
8008 int rc;
8009
8010 if (!vreg->enabled) {
8011 rc = regulator_enable(vreg->reg);
8012 if (rc) {
8013 pr_err("%s: regulator_enable(%s) failed. rc=%d\n",
8014 __func__, vreg->reg_name, rc);
8015 goto out;
8016 }
8017 vreg->enabled = 1;
8018 }
8019
8020 /* Put always_on regulator in HPM (high power mode) */
8021 if (vreg->always_on && vreg->op_pwr_mode_sup) {
8022 rc = regulator_set_optimum_mode(vreg->reg, vreg->hpm_uA);
8023 if (rc < 0) {
8024 pr_err("%s: reg=%s: HPM setting failed"
8025 " hpm_uA=%d, rc=%d\n",
8026 __func__, vreg->reg_name,
8027 vreg->hpm_uA, rc);
8028 goto vreg_disable;
8029 }
8030 rc = 0;
8031 }
8032 goto out;
8033
8034vreg_disable:
8035 regulator_disable(vreg->reg);
8036 vreg->enabled = 0;
8037out:
8038 return rc;
8039}
8040
8041static int msm_sdcc_vreg_disable(struct sdcc_reg *vreg)
8042{
8043 int rc;
8044
8045 /* Never disable always_on regulator */
8046 if (!vreg->always_on) {
8047 rc = regulator_disable(vreg->reg);
8048 if (rc) {
8049 pr_err("%s: regulator_disable(%s) failed. rc=%d\n",
8050 __func__, vreg->reg_name, rc);
8051 goto out;
8052 }
8053 vreg->enabled = 0;
8054 }
8055
8056 /* Put always_on regulator in LPM (low power mode) */
8057 if (vreg->always_on && vreg->op_pwr_mode_sup) {
8058 rc = regulator_set_optimum_mode(vreg->reg, vreg->lpm_uA);
8059 if (rc < 0) {
8060 pr_err("%s: reg=%s: LPM setting failed"
8061 " lpm_uA=%d, rc=%d\n",
8062 __func__,
8063 vreg->reg_name,
8064 vreg->lpm_uA, rc);
8065 goto out;
8066 }
8067 rc = 0;
8068 }
8069
8070out:
8071 return rc;
8072}
8073
8074static int msm_sdcc_setup_vreg(int dev_id, unsigned char enable)
8075{
8076 int rc = 0;
8077 struct sdcc_reg *curr_vdd_reg, *curr_vccq_reg, *curr_vddp_reg;
8078 struct sdcc_reg_data *curr;
8079
8080 curr = &sdcc_vreg_data[dev_id - 1];
8081 curr_vdd_reg = curr->vdd_data;
8082 curr_vccq_reg = curr->vccq_data;
8083 curr_vddp_reg = curr->vddp_data;
8084
8085 /* check if regulators are initialized or not? */
8086 if ((curr_vdd_reg && !curr_vdd_reg->reg) ||
8087 (curr_vccq_reg && !curr_vccq_reg->reg) ||
8088 (curr_vddp_reg && !curr_vddp_reg->reg)) {
8089 /* initialize voltage regulators required for this SDCC */
8090 rc = msm_sdcc_vreg_init(dev_id, 1);
8091 if (rc) {
8092 pr_err("%s: regulator init failed = %d\n",
8093 __func__, rc);
8094 goto out;
8095 }
8096 }
8097
8098 if (curr->sts == enable)
8099 goto out;
8100
8101 if (curr_vdd_reg) {
8102 if (enable)
8103 rc = msm_sdcc_vreg_enable(curr_vdd_reg);
8104 else
8105 rc = msm_sdcc_vreg_disable(curr_vdd_reg);
8106 if (rc)
8107 goto out;
8108 }
8109
8110 if (curr_vccq_reg) {
8111 if (enable)
8112 rc = msm_sdcc_vreg_enable(curr_vccq_reg);
8113 else
8114 rc = msm_sdcc_vreg_disable(curr_vccq_reg);
8115 if (rc)
8116 goto out;
8117 }
8118
8119 if (curr_vddp_reg) {
8120 if (enable)
8121 rc = msm_sdcc_vreg_enable(curr_vddp_reg);
8122 else
8123 rc = msm_sdcc_vreg_disable(curr_vddp_reg);
8124 if (rc)
8125 goto out;
8126 }
8127 curr->sts = enable;
8128
8129out:
8130 return rc;
8131}
8132
8133static u32 msm_sdcc_setup_power(struct device *dv, unsigned int vdd)
8134{
8135 u32 rc_pin_cfg = 0;
8136 u32 rc_vreg_cfg = 0;
8137 u32 rc = 0;
8138 struct platform_device *pdev;
8139 struct msm_sdcc_pin_cfg *curr_pin_cfg;
8140
8141 pdev = container_of(dv, struct platform_device, dev);
8142
8143 /* setup gpio/pad */
8144 curr_pin_cfg = &sdcc_pin_cfg_data[pdev->id - 1];
8145 if (curr_pin_cfg->cfg_sts == !!vdd)
8146 goto setup_vreg;
8147
8148 if (curr_pin_cfg->is_gpio)
8149 rc_pin_cfg = msm_sdcc_setup_gpio(pdev->id, !!vdd);
8150 else
8151 rc_pin_cfg = msm_sdcc_setup_pad(pdev->id, !!vdd);
8152
8153setup_vreg:
8154 /* setup voltage regulators */
8155 rc_vreg_cfg = msm_sdcc_setup_vreg(pdev->id, !!vdd);
8156
8157 if (rc_pin_cfg || rc_vreg_cfg)
8158 rc = rc_pin_cfg ? rc_pin_cfg : rc_vreg_cfg;
8159
8160 return rc;
8161}
8162
8163static void msm_sdcc_sdio_lpm_gpio(struct device *dv, unsigned int active)
8164{
8165 struct msm_sdcc_pin_cfg *curr_pin_cfg;
8166 struct platform_device *pdev;
8167
8168 pdev = container_of(dv, struct platform_device, dev);
8169 /* setup gpio/pad */
8170 curr_pin_cfg = &sdcc_pin_cfg_data[pdev->id - 1];
8171
8172 if (curr_pin_cfg->cfg_sts == active)
8173 return;
8174
8175 curr_pin_cfg->sdio_lpm_gpio_cfg = 1;
8176 if (curr_pin_cfg->is_gpio)
8177 msm_sdcc_setup_gpio(pdev->id, active);
8178 else
8179 msm_sdcc_setup_pad(pdev->id, active);
8180 curr_pin_cfg->sdio_lpm_gpio_cfg = 0;
8181}
8182
8183static int msm_sdc3_get_wpswitch(struct device *dev)
8184{
8185 struct platform_device *pdev;
8186 int status;
8187 pdev = container_of(dev, struct platform_device, dev);
8188
8189 status = gpio_request(GPIO_SDC_WP, "SD_WP_Switch");
8190 if (status) {
8191 pr_err("%s:Failed to request GPIO %d\n",
8192 __func__, GPIO_SDC_WP);
8193 } else {
8194 status = gpio_direction_input(GPIO_SDC_WP);
8195 if (!status) {
8196 status = gpio_get_value_cansleep(GPIO_SDC_WP);
8197 pr_info("%s: WP Status for Slot %d = %d\n",
8198 __func__, pdev->id, status);
8199 }
8200 gpio_free(GPIO_SDC_WP);
8201 }
8202 return status;
8203}
8204
8205#ifdef CONFIG_MMC_MSM_SDC5_SUPPORT
8206int sdc5_register_status_notify(void (*callback)(int, void *),
8207 void *dev_id)
8208{
8209 sdc5_status_notify_cb = callback;
8210 sdc5_status_notify_cb_devid = dev_id;
8211 return 0;
8212}
8213#endif
8214
8215#ifdef CONFIG_MMC_MSM_SDC2_SUPPORT
8216int sdc2_register_status_notify(void (*callback)(int, void *),
8217 void *dev_id)
8218{
8219 sdc2_status_notify_cb = callback;
8220 sdc2_status_notify_cb_devid = dev_id;
8221 return 0;
8222}
8223#endif
8224
8225/* Interrupt handler for SDC2 and SDC5 detection
8226 * This function uses dual-edge interrputs settings in order
8227 * to get SDIO detection when the GPIO is rising and SDIO removal
8228 * when the GPIO is falling */
8229static irqreturn_t msm8x60_multi_sdio_slot_status_irq(int irq, void *dev_id)
8230{
8231 int status;
8232
8233 if (!machine_is_msm8x60_fusion() &&
8234 !machine_is_msm8x60_fusn_ffa())
8235 return IRQ_NONE;
8236
8237 status = gpio_get_value(MDM2AP_SYNC);
8238 pr_info("%s: MDM2AP_SYNC Status = %d\n",
8239 __func__, status);
8240
8241#ifdef CONFIG_MMC_MSM_SDC2_SUPPORT
8242 if (sdc2_status_notify_cb) {
8243 pr_info("%s: calling sdc2_status_notify_cb\n", __func__);
8244 sdc2_status_notify_cb(status,
8245 sdc2_status_notify_cb_devid);
8246 }
8247#endif
8248
8249#ifdef CONFIG_MMC_MSM_SDC5_SUPPORT
8250 if (sdc5_status_notify_cb) {
8251 pr_info("%s: calling sdc5_status_notify_cb\n", __func__);
8252 sdc5_status_notify_cb(status,
8253 sdc5_status_notify_cb_devid);
8254 }
8255#endif
8256 return IRQ_HANDLED;
8257}
8258
8259static int msm8x60_multi_sdio_init(void)
8260{
8261 int ret, irq_num;
8262
8263 if (!machine_is_msm8x60_fusion() &&
8264 !machine_is_msm8x60_fusn_ffa())
8265 return 0;
8266
8267 ret = msm_gpiomux_get(MDM2AP_SYNC);
8268 if (ret) {
8269 pr_err("%s:Failed to request GPIO %d, ret=%d\n",
8270 __func__, MDM2AP_SYNC, ret);
8271 return ret;
8272 }
8273
8274 irq_num = gpio_to_irq(MDM2AP_SYNC);
8275
8276 ret = request_irq(irq_num,
8277 msm8x60_multi_sdio_slot_status_irq,
8278 IRQ_TYPE_EDGE_BOTH,
8279 "sdio_multidetection", NULL);
8280
8281 if (ret) {
8282 pr_err("%s:Failed to request irq, ret=%d\n",
8283 __func__, ret);
8284 return ret;
8285 }
8286
8287 return ret;
8288}
8289
8290#ifdef CONFIG_MMC_MSM_SDC3_SUPPORT
8291#ifdef CONFIG_MMC_MSM_CARD_HW_DETECTION
8292static unsigned int msm8x60_sdcc_slot_status(struct device *dev)
8293{
8294 int status;
8295
8296 status = gpio_request(PM8058_GPIO_PM_TO_SYS(PMIC_GPIO_SDC3_DET - 1)
8297 , "SD_HW_Detect");
8298 if (status) {
8299 pr_err("%s:Failed to request GPIO %d\n", __func__,
8300 PM8058_GPIO_PM_TO_SYS(PMIC_GPIO_SDC3_DET - 1));
8301 } else {
8302 status = gpio_direction_input(
8303 PM8058_GPIO_PM_TO_SYS(PMIC_GPIO_SDC3_DET - 1));
8304 if (!status)
8305 status = !(gpio_get_value_cansleep(
8306 PM8058_GPIO_PM_TO_SYS(PMIC_GPIO_SDC3_DET - 1)));
8307 gpio_free(PM8058_GPIO_PM_TO_SYS(PMIC_GPIO_SDC3_DET - 1));
8308 }
8309 return (unsigned int) status;
8310}
8311#endif
8312#endif
8313
8314#ifdef CONFIG_MMC_MSM_SDC4_SUPPORT
8315static int msm_sdcc_cfg_mpm_sdiowakeup(struct device *dev, unsigned mode)
8316{
8317 struct platform_device *pdev;
8318 enum msm_mpm_pin pin;
8319 int ret = 0;
8320
8321 pdev = container_of(dev, struct platform_device, dev);
8322
8323 /* Only SDCC4 slot connected to WLAN chip has wakeup capability */
8324 if (pdev->id == 4)
8325 pin = MSM_MPM_PIN_SDC4_DAT1;
8326 else
8327 return -EINVAL;
8328
8329 switch (mode) {
8330 case SDC_DAT1_DISABLE:
8331 ret = msm_mpm_enable_pin(pin, 0);
8332 break;
8333 case SDC_DAT1_ENABLE:
8334 ret = msm_mpm_set_pin_type(pin, IRQ_TYPE_LEVEL_LOW);
8335 ret = msm_mpm_enable_pin(pin, 1);
8336 break;
8337 case SDC_DAT1_ENWAKE:
8338 ret = msm_mpm_set_pin_wake(pin, 1);
8339 break;
8340 case SDC_DAT1_DISWAKE:
8341 ret = msm_mpm_set_pin_wake(pin, 0);
8342 break;
8343 default:
8344 ret = -EINVAL;
8345 break;
8346 }
8347 return ret;
8348}
8349#endif
8350#endif
8351
8352#ifdef CONFIG_MMC_MSM_SDC1_SUPPORT
8353static struct mmc_platform_data msm8x60_sdc1_data = {
8354 .ocr_mask = MMC_VDD_27_28 | MMC_VDD_28_29,
8355 .translate_vdd = msm_sdcc_setup_power,
8356#ifdef CONFIG_MMC_MSM_SDC1_8_BIT_SUPPORT
8357 .mmc_bus_width = MMC_CAP_8_BIT_DATA,
8358#else
8359 .mmc_bus_width = MMC_CAP_4_BIT_DATA,
8360#endif
8361 .msmsdcc_fmin = 400000,
8362 .msmsdcc_fmid = 24000000,
8363 .msmsdcc_fmax = 48000000,
8364 .nonremovable = 1,
8365 .pclk_src_dfab = 1,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07008366};
8367#endif
8368
8369#ifdef CONFIG_MMC_MSM_SDC2_SUPPORT
8370static struct mmc_platform_data msm8x60_sdc2_data = {
8371 .ocr_mask = MMC_VDD_27_28 | MMC_VDD_28_29 | MMC_VDD_165_195,
8372 .translate_vdd = msm_sdcc_setup_power,
8373 .sdio_lpm_gpio_setup = msm_sdcc_sdio_lpm_gpio,
8374 .mmc_bus_width = MMC_CAP_8_BIT_DATA,
8375 .msmsdcc_fmin = 400000,
8376 .msmsdcc_fmid = 24000000,
8377 .msmsdcc_fmax = 48000000,
8378 .nonremovable = 0,
8379 .pclk_src_dfab = 1,
8380 .register_status_notify = sdc2_register_status_notify,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07008381#ifdef CONFIG_MSM_SDIO_AL
8382 .is_sdio_al_client = 1,
8383#endif
8384};
8385#endif
8386
8387#ifdef CONFIG_MMC_MSM_SDC3_SUPPORT
8388static struct mmc_platform_data msm8x60_sdc3_data = {
8389 .ocr_mask = MMC_VDD_27_28 | MMC_VDD_28_29,
8390 .translate_vdd = msm_sdcc_setup_power,
8391 .mmc_bus_width = MMC_CAP_4_BIT_DATA,
8392 .wpswitch = msm_sdc3_get_wpswitch,
8393#ifdef CONFIG_MMC_MSM_CARD_HW_DETECTION
8394 .status = msm8x60_sdcc_slot_status,
8395 .status_irq = PM8058_GPIO_IRQ(PM8058_IRQ_BASE,
8396 PMIC_GPIO_SDC3_DET - 1),
8397 .irq_flags = IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING,
8398#endif
8399 .msmsdcc_fmin = 400000,
8400 .msmsdcc_fmid = 24000000,
8401 .msmsdcc_fmax = 48000000,
8402 .nonremovable = 0,
8403 .pclk_src_dfab = 1,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07008404};
8405#endif
8406
8407#ifdef CONFIG_MMC_MSM_SDC4_SUPPORT
8408static struct mmc_platform_data msm8x60_sdc4_data = {
8409 .ocr_mask = MMC_VDD_27_28 | MMC_VDD_28_29,
8410 .translate_vdd = msm_sdcc_setup_power,
8411 .mmc_bus_width = MMC_CAP_4_BIT_DATA,
8412 .msmsdcc_fmin = 400000,
8413 .msmsdcc_fmid = 24000000,
8414 .msmsdcc_fmax = 48000000,
8415 .nonremovable = 0,
8416 .pclk_src_dfab = 1,
8417 .cfg_mpm_sdiowakeup = msm_sdcc_cfg_mpm_sdiowakeup,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07008418};
8419#endif
8420
8421#ifdef CONFIG_MMC_MSM_SDC5_SUPPORT
8422static struct mmc_platform_data msm8x60_sdc5_data = {
8423 .ocr_mask = MMC_VDD_27_28 | MMC_VDD_28_29 | MMC_VDD_165_195,
8424 .translate_vdd = msm_sdcc_setup_power,
8425 .sdio_lpm_gpio_setup = msm_sdcc_sdio_lpm_gpio,
8426 .mmc_bus_width = MMC_CAP_4_BIT_DATA,
8427 .msmsdcc_fmin = 400000,
8428 .msmsdcc_fmid = 24000000,
8429 .msmsdcc_fmax = 48000000,
8430 .nonremovable = 0,
8431 .pclk_src_dfab = 1,
8432 .register_status_notify = sdc5_register_status_notify,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07008433#ifdef CONFIG_MSM_SDIO_AL
8434 .is_sdio_al_client = 1,
8435#endif
8436};
8437#endif
8438
8439static void __init msm8x60_init_mmc(void)
8440{
8441#ifdef CONFIG_MMC_MSM_SDC1_SUPPORT
8442 /* SDCC1 : eMMC card connected */
8443 sdcc_vreg_data[0].vdd_data = &sdcc_vdd_reg_data[0];
8444 sdcc_vreg_data[0].vdd_data->reg_name = "8901_l5";
8445 sdcc_vreg_data[0].vdd_data->set_voltage_sup = 1;
8446 sdcc_vreg_data[0].vdd_data->level = 2850000;
Subhash Jadavania8482a32011-08-08 11:01:44 +05308447 sdcc_vreg_data[0].vdd_data->always_on = 1;
8448 sdcc_vreg_data[0].vdd_data->op_pwr_mode_sup = 1;
8449 sdcc_vreg_data[0].vdd_data->lpm_uA = 9000;
8450 sdcc_vreg_data[0].vdd_data->hpm_uA = 200000;
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07008451
8452 sdcc_vreg_data[0].vccq_data = &sdcc_vccq_reg_data[0];
8453 sdcc_vreg_data[0].vccq_data->reg_name = "8901_lvs0";
8454 sdcc_vreg_data[0].vccq_data->set_voltage_sup = 0;
8455 sdcc_vreg_data[0].vccq_data->always_on = 1;
8456
8457 msm_add_sdcc(1, &msm8x60_sdc1_data);
8458#endif
8459#ifdef CONFIG_MMC_MSM_SDC2_SUPPORT
8460 /*
8461 * MDM SDIO client is connected to SDC2 on charm SURF/FFA
8462 * and no card is connected on 8660 SURF/FFA/FLUID.
8463 */
8464 sdcc_vreg_data[1].vdd_data = &sdcc_vdd_reg_data[1];
8465 sdcc_vreg_data[1].vdd_data->reg_name = "8058_s3";
8466 sdcc_vreg_data[1].vdd_data->set_voltage_sup = 1;
8467 sdcc_vreg_data[1].vdd_data->level = 1800000;
8468
8469 sdcc_vreg_data[1].vccq_data = NULL;
8470
8471 if (machine_is_msm8x60_fusion())
8472 msm8x60_sdc2_data.msmsdcc_fmax = 24000000;
8473 if (machine_is_msm8x60_fusion() || machine_is_msm8x60_fusn_ffa()) {
8474#ifdef CONFIG_MMC_MSM_SDIO_SUPPORT
8475 msm8x60_sdc2_data.sdiowakeup_irq = gpio_to_irq(144);
8476 msm_sdcc_setup_gpio(2, 1);
8477#endif
8478 msm_add_sdcc(2, &msm8x60_sdc2_data);
8479 }
8480#endif
8481#ifdef CONFIG_MMC_MSM_SDC3_SUPPORT
8482 /* SDCC3 : External card slot connected */
8483 sdcc_vreg_data[2].vdd_data = &sdcc_vdd_reg_data[2];
8484 sdcc_vreg_data[2].vdd_data->reg_name = "8058_l14";
8485 sdcc_vreg_data[2].vdd_data->set_voltage_sup = 1;
8486 sdcc_vreg_data[2].vdd_data->level = 2850000;
8487 sdcc_vreg_data[2].vdd_data->always_on = 1;
8488 sdcc_vreg_data[2].vdd_data->op_pwr_mode_sup = 1;
8489 sdcc_vreg_data[2].vdd_data->lpm_uA = 9000;
8490 sdcc_vreg_data[2].vdd_data->hpm_uA = 200000;
8491
8492 sdcc_vreg_data[2].vccq_data = NULL;
8493
8494 sdcc_vreg_data[2].vddp_data = &sdcc_vddp_reg_data[2];
8495 sdcc_vreg_data[2].vddp_data->reg_name = "8058_l5";
8496 sdcc_vreg_data[2].vddp_data->set_voltage_sup = 1;
8497 sdcc_vreg_data[2].vddp_data->level = 2850000;
8498 sdcc_vreg_data[2].vddp_data->always_on = 1;
8499 sdcc_vreg_data[2].vddp_data->op_pwr_mode_sup = 1;
8500 /* Sleep current required is ~300 uA. But min. RPM
8501 * vote can be in terms of mA (min. 1 mA).
8502 * So let's vote for 2 mA during sleep.
8503 */
8504 sdcc_vreg_data[2].vddp_data->lpm_uA = 2000;
8505 /* Max. Active current required is 16 mA */
8506 sdcc_vreg_data[2].vddp_data->hpm_uA = 16000;
8507
8508 if (machine_is_msm8x60_fluid())
8509 msm8x60_sdc3_data.wpswitch = NULL;
8510 msm_add_sdcc(3, &msm8x60_sdc3_data);
8511#endif
8512#ifdef CONFIG_MMC_MSM_SDC4_SUPPORT
8513 /* SDCC4 : WLAN WCN1314 chip is connected */
8514 sdcc_vreg_data[3].vdd_data = &sdcc_vdd_reg_data[3];
8515 sdcc_vreg_data[3].vdd_data->reg_name = "8058_s3";
8516 sdcc_vreg_data[3].vdd_data->set_voltage_sup = 1;
8517 sdcc_vreg_data[3].vdd_data->level = 1800000;
8518
8519 sdcc_vreg_data[3].vccq_data = NULL;
8520
8521 msm_add_sdcc(4, &msm8x60_sdc4_data);
8522#endif
8523#ifdef CONFIG_MMC_MSM_SDC5_SUPPORT
8524 /*
8525 * MDM SDIO client is connected to SDC5 on charm SURF/FFA
8526 * and no card is connected on 8660 SURF/FFA/FLUID.
8527 */
8528 sdcc_vreg_data[4].vdd_data = &sdcc_vdd_reg_data[4];
8529 sdcc_vreg_data[4].vdd_data->reg_name = "8058_s3";
8530 sdcc_vreg_data[4].vdd_data->set_voltage_sup = 1;
8531 sdcc_vreg_data[4].vdd_data->level = 1800000;
8532
8533 sdcc_vreg_data[4].vccq_data = NULL;
8534
8535 if (machine_is_msm8x60_fusion())
8536 msm8x60_sdc5_data.msmsdcc_fmax = 24000000;
8537 if (machine_is_msm8x60_fusion() || machine_is_msm8x60_fusn_ffa()) {
8538#ifdef CONFIG_MMC_MSM_SDIO_SUPPORT
8539 msm8x60_sdc5_data.sdiowakeup_irq = gpio_to_irq(99);
8540 msm_sdcc_setup_gpio(5, 1);
8541#endif
8542 msm_add_sdcc(5, &msm8x60_sdc5_data);
8543 }
8544#endif
8545}
8546
8547#if !defined(CONFIG_GPIO_SX150X) && !defined(CONFIG_GPIO_SX150X_MODULE)
8548static inline void display_common_power(int on) {}
8549#else
8550
8551#define _GET_REGULATOR(var, name) do { \
8552 if (var == NULL) { \
8553 var = regulator_get(NULL, name); \
8554 if (IS_ERR(var)) { \
8555 pr_err("'%s' regulator not found, rc=%ld\n", \
8556 name, PTR_ERR(var)); \
8557 var = NULL; \
8558 } \
8559 } \
8560} while (0)
8561
8562static int dsub_regulator(int on)
8563{
8564 static struct regulator *dsub_reg;
8565 static struct regulator *mpp0_reg;
8566 static int dsub_reg_enabled;
8567 int rc = 0;
8568
8569 _GET_REGULATOR(dsub_reg, "8901_l3");
8570 if (IS_ERR(dsub_reg)) {
8571 printk(KERN_ERR "%s: failed to get reg 8901_l3 err=%ld",
8572 __func__, PTR_ERR(dsub_reg));
8573 return PTR_ERR(dsub_reg);
8574 }
8575
8576 _GET_REGULATOR(mpp0_reg, "8901_mpp0");
8577 if (IS_ERR(mpp0_reg)) {
8578 printk(KERN_ERR "%s: failed to get reg 8901_mpp0 err=%ld",
8579 __func__, PTR_ERR(mpp0_reg));
8580 return PTR_ERR(mpp0_reg);
8581 }
8582
8583 if (on && !dsub_reg_enabled) {
8584 rc = regulator_set_voltage(dsub_reg, 3300000, 3300000);
8585 if (rc) {
8586 printk(KERN_ERR "%s: failed to set reg 8901_l3 voltage"
8587 " err=%d", __func__, rc);
8588 goto dsub_regulator_err;
8589 }
8590 rc = regulator_enable(dsub_reg);
8591 if (rc) {
8592 printk(KERN_ERR "%s: failed to enable reg 8901_l3"
8593 " err=%d", __func__, rc);
8594 goto dsub_regulator_err;
8595 }
8596 rc = regulator_enable(mpp0_reg);
8597 if (rc) {
8598 printk(KERN_ERR "%s: failed to enable reg 8901_mpp0"
8599 " err=%d", __func__, rc);
8600 goto dsub_regulator_err;
8601 }
8602 dsub_reg_enabled = 1;
8603 } else if (!on && dsub_reg_enabled) {
8604 rc = regulator_disable(dsub_reg);
8605 if (rc)
8606 printk(KERN_WARNING "%s: failed to disable reg 8901_l3"
8607 " err=%d", __func__, rc);
8608 rc = regulator_disable(mpp0_reg);
8609 if (rc)
8610 printk(KERN_WARNING "%s: failed to disable reg "
8611 "8901_mpp0 err=%d", __func__, rc);
8612 dsub_reg_enabled = 0;
8613 }
8614
8615 return rc;
8616
8617dsub_regulator_err:
8618 regulator_put(mpp0_reg);
8619 regulator_put(dsub_reg);
8620 return rc;
8621}
8622
8623static int display_power_on;
8624static void setup_display_power(void)
8625{
8626 if (display_power_on)
8627 if (lcdc_vga_enabled) {
8628 dsub_regulator(1);
8629 gpio_set_value_cansleep(GPIO_LVDS_SHUTDOWN_N, 0);
8630 gpio_set_value_cansleep(GPIO_BACKLIGHT_EN, 0);
8631 if (machine_is_msm8x60_ffa() ||
8632 machine_is_msm8x60_fusn_ffa())
8633 gpio_set_value_cansleep(GPIO_DONGLE_PWR_EN, 1);
8634 } else {
8635 dsub_regulator(0);
8636 gpio_set_value_cansleep(GPIO_LVDS_SHUTDOWN_N, 1);
8637 gpio_set_value_cansleep(GPIO_BACKLIGHT_EN, 1);
8638 if (machine_is_msm8x60_ffa() ||
8639 machine_is_msm8x60_fusn_ffa())
8640 gpio_set_value_cansleep(GPIO_DONGLE_PWR_EN, 0);
8641 }
8642 else {
8643 dsub_regulator(0);
8644 if (machine_is_msm8x60_ffa() || machine_is_msm8x60_fusn_ffa())
8645 gpio_set_value_cansleep(GPIO_DONGLE_PWR_EN, 0);
8646 /* BACKLIGHT */
8647 gpio_set_value_cansleep(GPIO_BACKLIGHT_EN, 0);
8648 /* LVDS */
8649 gpio_set_value_cansleep(GPIO_LVDS_SHUTDOWN_N, 0);
8650 }
8651}
8652
8653#define _GET_REGULATOR(var, name) do { \
8654 if (var == NULL) { \
8655 var = regulator_get(NULL, name); \
8656 if (IS_ERR(var)) { \
8657 pr_err("'%s' regulator not found, rc=%ld\n", \
8658 name, PTR_ERR(var)); \
8659 var = NULL; \
8660 } \
8661 } \
8662} while (0)
8663
8664#define GPIO_RESX_N (GPIO_EXPANDER_GPIO_BASE + 2)
8665
8666static void display_common_power(int on)
8667{
8668 int rc;
8669 static struct regulator *display_reg;
8670
8671 if (machine_is_msm8x60_surf() || machine_is_msm8x60_ffa() ||
8672 machine_is_msm8x60_fusion() || machine_is_msm8x60_fusn_ffa()) {
8673 if (on) {
8674 /* LVDS */
8675 _GET_REGULATOR(display_reg, "8901_l2");
8676 if (!display_reg)
8677 return;
8678 rc = regulator_set_voltage(display_reg,
8679 3300000, 3300000);
8680 if (rc)
8681 goto out;
8682 rc = regulator_enable(display_reg);
8683 if (rc)
8684 goto out;
8685 rc = gpio_request(GPIO_LVDS_SHUTDOWN_N,
8686 "LVDS_STDN_OUT_N");
8687 if (rc) {
8688 printk(KERN_ERR "%s: LVDS gpio %d request"
8689 "failed\n", __func__,
8690 GPIO_LVDS_SHUTDOWN_N);
8691 goto out2;
8692 }
8693
8694 /* BACKLIGHT */
8695 rc = gpio_request(GPIO_BACKLIGHT_EN, "BACKLIGHT_EN");
8696 if (rc) {
8697 printk(KERN_ERR "%s: BACKLIGHT gpio %d request"
8698 "failed\n", __func__,
8699 GPIO_BACKLIGHT_EN);
8700 goto out3;
8701 }
8702
8703 if (machine_is_msm8x60_ffa() ||
8704 machine_is_msm8x60_fusn_ffa()) {
8705 rc = gpio_request(GPIO_DONGLE_PWR_EN,
8706 "DONGLE_PWR_EN");
8707 if (rc) {
8708 printk(KERN_ERR "%s: DONGLE_PWR_EN gpio"
8709 " %d request failed\n", __func__,
8710 GPIO_DONGLE_PWR_EN);
8711 goto out4;
8712 }
8713 }
8714
8715 gpio_direction_output(GPIO_LVDS_SHUTDOWN_N, 0);
8716 gpio_direction_output(GPIO_BACKLIGHT_EN, 0);
8717 if (machine_is_msm8x60_ffa() ||
8718 machine_is_msm8x60_fusn_ffa())
8719 gpio_direction_output(GPIO_DONGLE_PWR_EN, 0);
8720 mdelay(20);
8721 display_power_on = 1;
8722 setup_display_power();
8723 } else {
8724 if (display_power_on) {
8725 display_power_on = 0;
8726 setup_display_power();
8727 mdelay(20);
8728 if (machine_is_msm8x60_ffa() ||
8729 machine_is_msm8x60_fusn_ffa())
8730 gpio_free(GPIO_DONGLE_PWR_EN);
8731 goto out4;
8732 }
8733 }
8734 }
8735#if defined(CONFIG_FB_MSM_LCDC_SAMSUNG_OLED_PT) || \
8736 defined(CONFIG_FB_MSM_LCDC_AUO_WVGA)
8737 else if (machine_is_msm8x60_fluid()) {
8738 static struct regulator *fluid_reg;
8739 static struct regulator *fluid_reg2;
8740
8741 if (on) {
8742 _GET_REGULATOR(fluid_reg, "8901_l2");
8743 if (!fluid_reg)
8744 return;
8745 _GET_REGULATOR(fluid_reg2, "8058_s3");
8746 if (!fluid_reg2) {
8747 regulator_put(fluid_reg);
8748 return;
8749 }
8750 rc = gpio_request(GPIO_RESX_N, "RESX_N");
8751 if (rc) {
8752 regulator_put(fluid_reg2);
8753 regulator_put(fluid_reg);
8754 return;
8755 }
8756 regulator_set_voltage(fluid_reg, 2850000, 2850000);
8757 regulator_set_voltage(fluid_reg2, 1800000, 1800000);
8758 regulator_enable(fluid_reg);
8759 regulator_enable(fluid_reg2);
8760 msleep(20);
8761 gpio_direction_output(GPIO_RESX_N, 0);
8762 udelay(10);
8763 gpio_set_value_cansleep(GPIO_RESX_N, 1);
8764 display_power_on = 1;
8765 setup_display_power();
8766 } else {
8767 gpio_set_value_cansleep(GPIO_RESX_N, 0);
8768 gpio_free(GPIO_RESX_N);
8769 msleep(20);
8770 regulator_disable(fluid_reg2);
8771 regulator_disable(fluid_reg);
8772 regulator_put(fluid_reg2);
8773 regulator_put(fluid_reg);
8774 display_power_on = 0;
8775 setup_display_power();
8776 fluid_reg = NULL;
8777 fluid_reg2 = NULL;
8778 }
8779 }
8780#endif
Zhang Chang Ken3a8b8512011-08-04 18:41:39 -04008781#if defined(CONFIG_FB_MSM_LCDC_NT35582_WVGA)
8782 else if (machine_is_msm8x60_dragon()) {
8783 static struct regulator *dragon_reg;
8784 static struct regulator *dragon_reg2;
8785
8786 if (on) {
8787 _GET_REGULATOR(dragon_reg, "8901_l2");
8788 if (!dragon_reg)
8789 return;
8790 _GET_REGULATOR(dragon_reg2, "8058_l16");
8791 if (!dragon_reg2) {
8792 regulator_put(dragon_reg);
8793 dragon_reg = NULL;
8794 return;
8795 }
8796
8797 rc = gpio_request(GPIO_NT35582_BL_EN, "lcdc_bl_en");
8798 if (rc) {
8799 pr_err("%s: gpio %d request failed with rc=%d\n",
8800 __func__, GPIO_NT35582_BL_EN, rc);
8801 regulator_put(dragon_reg);
8802 regulator_put(dragon_reg2);
8803 dragon_reg = NULL;
8804 dragon_reg2 = NULL;
8805 return;
8806 }
8807
8808 if (gpio_tlmm_config(GPIO_CFG(GPIO_NT35582_RESET, 0,
8809 GPIO_CFG_OUTPUT, GPIO_CFG_PULL_DOWN,
8810 GPIO_CFG_16MA), GPIO_CFG_ENABLE)) {
8811 pr_err("%s: config gpio '%d' failed!\n",
8812 __func__, GPIO_NT35582_RESET);
8813 gpio_free(GPIO_NT35582_BL_EN);
8814 regulator_put(dragon_reg);
8815 regulator_put(dragon_reg2);
8816 dragon_reg = NULL;
8817 dragon_reg2 = NULL;
8818 return;
8819 }
8820
8821 rc = gpio_request(GPIO_NT35582_RESET, "lcdc_reset");
8822 if (rc) {
8823 pr_err("%s: unable to request gpio %d (rc=%d)\n",
8824 __func__, GPIO_NT35582_RESET, rc);
8825 gpio_free(GPIO_NT35582_BL_EN);
8826 regulator_put(dragon_reg);
8827 regulator_put(dragon_reg2);
8828 dragon_reg = NULL;
8829 dragon_reg2 = NULL;
8830 return;
8831 }
8832
8833 regulator_set_voltage(dragon_reg, 3300000, 3300000);
8834 regulator_set_voltage(dragon_reg2, 1800000, 1800000);
8835 regulator_enable(dragon_reg);
8836 regulator_enable(dragon_reg2);
8837 msleep(20);
8838
8839 gpio_set_value_cansleep(GPIO_NT35582_RESET, 1);
8840 msleep(20);
8841 gpio_set_value_cansleep(GPIO_NT35582_RESET, 0);
8842 msleep(20);
8843 gpio_set_value_cansleep(GPIO_NT35582_RESET, 1);
8844 msleep(50);
8845
8846 gpio_set_value_cansleep(GPIO_NT35582_BL_EN, 1);
8847
8848 display_power_on = 1;
8849 } else if ((dragon_reg != NULL) && (dragon_reg2 != NULL)) {
8850 gpio_free(GPIO_NT35582_RESET);
8851 gpio_free(GPIO_NT35582_BL_EN);
8852 regulator_disable(dragon_reg2);
8853 regulator_disable(dragon_reg);
8854 regulator_put(dragon_reg2);
8855 regulator_put(dragon_reg);
8856 display_power_on = 0;
8857 dragon_reg = NULL;
8858 dragon_reg2 = NULL;
8859 }
8860 }
8861#endif
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07008862 return;
8863
8864out4:
8865 gpio_free(GPIO_BACKLIGHT_EN);
8866out3:
8867 gpio_free(GPIO_LVDS_SHUTDOWN_N);
8868out2:
8869 regulator_disable(display_reg);
8870out:
8871 regulator_put(display_reg);
8872 display_reg = NULL;
8873}
8874#undef _GET_REGULATOR
8875#endif
8876
8877static int mipi_dsi_panel_power(int on);
8878
8879#define LCDC_NUM_GPIO 28
8880#define LCDC_GPIO_START 0
8881
8882static void lcdc_samsung_panel_power(int on)
8883{
8884 int n, ret = 0;
8885
8886 display_common_power(on);
8887
8888 for (n = 0; n < LCDC_NUM_GPIO; n++) {
8889 if (on) {
8890 ret = gpio_request(LCDC_GPIO_START + n, "LCDC_GPIO");
8891 if (unlikely(ret)) {
8892 pr_err("%s not able to get gpio\n", __func__);
8893 break;
8894 }
8895 } else
8896 gpio_free(LCDC_GPIO_START + n);
8897 }
8898
8899 if (ret) {
8900 for (n--; n >= 0; n--)
8901 gpio_free(LCDC_GPIO_START + n);
8902 }
8903
8904 mipi_dsi_panel_power(0); /* set 8058_ldo0 to LPM */
8905}
8906
8907#ifdef CONFIG_FB_MSM_HDMI_MSM_PANEL
8908#define _GET_REGULATOR(var, name) do { \
8909 var = regulator_get(NULL, name); \
8910 if (IS_ERR(var)) { \
8911 pr_err("'%s' regulator not found, rc=%ld\n", \
8912 name, IS_ERR(var)); \
8913 var = NULL; \
8914 return -ENODEV; \
8915 } \
8916} while (0)
8917
8918static int hdmi_enable_5v(int on)
8919{
8920 static struct regulator *reg_8901_hdmi_mvs; /* HDMI_5V */
8921 static struct regulator *reg_8901_mpp0; /* External 5V */
8922 static int prev_on;
8923 int rc;
8924
8925 if (on == prev_on)
8926 return 0;
8927
8928 if (!reg_8901_hdmi_mvs)
8929 _GET_REGULATOR(reg_8901_hdmi_mvs, "8901_hdmi_mvs");
8930 if (!reg_8901_mpp0)
8931 _GET_REGULATOR(reg_8901_mpp0, "8901_mpp0");
8932
8933 if (on) {
8934 rc = regulator_enable(reg_8901_mpp0);
8935 if (rc) {
8936 pr_err("'%s' regulator enable failed, rc=%d\n",
8937 "reg_8901_mpp0", rc);
8938 return rc;
8939 }
8940 rc = regulator_enable(reg_8901_hdmi_mvs);
8941 if (rc) {
8942 pr_err("'%s' regulator enable failed, rc=%d\n",
8943 "8901_hdmi_mvs", rc);
8944 return rc;
8945 }
8946 pr_info("%s(on): success\n", __func__);
8947 } else {
8948 rc = regulator_disable(reg_8901_hdmi_mvs);
8949 if (rc)
8950 pr_warning("'%s' regulator disable failed, rc=%d\n",
8951 "8901_hdmi_mvs", rc);
8952 rc = regulator_disable(reg_8901_mpp0);
8953 if (rc)
8954 pr_warning("'%s' regulator disable failed, rc=%d\n",
8955 "reg_8901_mpp0", rc);
8956 pr_info("%s(off): success\n", __func__);
8957 }
8958
8959 prev_on = on;
8960
8961 return 0;
8962}
8963
8964static int hdmi_core_power(int on, int show)
8965{
8966 static struct regulator *reg_8058_l16; /* VDD_HDMI */
8967 static int prev_on;
8968 int rc;
8969
8970 if (on == prev_on)
8971 return 0;
8972
8973 if (!reg_8058_l16)
8974 _GET_REGULATOR(reg_8058_l16, "8058_l16");
8975
8976 if (on) {
8977 rc = regulator_set_voltage(reg_8058_l16, 1800000, 1800000);
8978 if (!rc)
8979 rc = regulator_enable(reg_8058_l16);
8980 if (rc) {
8981 pr_err("'%s' regulator enable failed, rc=%d\n",
8982 "8058_l16", rc);
8983 return rc;
8984 }
8985 rc = gpio_request(170, "HDMI_DDC_CLK");
8986 if (rc) {
8987 pr_err("'%s'(%d) gpio_request failed, rc=%d\n",
8988 "HDMI_DDC_CLK", 170, rc);
8989 goto error1;
8990 }
8991 rc = gpio_request(171, "HDMI_DDC_DATA");
8992 if (rc) {
8993 pr_err("'%s'(%d) gpio_request failed, rc=%d\n",
8994 "HDMI_DDC_DATA", 171, rc);
8995 goto error2;
8996 }
8997 rc = gpio_request(172, "HDMI_HPD");
8998 if (rc) {
8999 pr_err("'%s'(%d) gpio_request failed, rc=%d\n",
9000 "HDMI_HPD", 172, rc);
9001 goto error3;
9002 }
9003 pr_info("%s(on): success\n", __func__);
9004 } else {
9005 gpio_free(170);
9006 gpio_free(171);
9007 gpio_free(172);
9008 rc = regulator_disable(reg_8058_l16);
9009 if (rc)
9010 pr_warning("'%s' regulator disable failed, rc=%d\n",
9011 "8058_l16", rc);
9012 pr_info("%s(off): success\n", __func__);
9013 }
9014
9015 prev_on = on;
9016
9017 return 0;
9018
9019error3:
9020 gpio_free(171);
9021error2:
9022 gpio_free(170);
9023error1:
9024 regulator_disable(reg_8058_l16);
9025 return rc;
9026}
9027
9028static int hdmi_cec_power(int on)
9029{
9030 static struct regulator *reg_8901_l3; /* HDMI_CEC */
9031 static int prev_on;
9032 int rc;
9033
9034 if (on == prev_on)
9035 return 0;
9036
9037 if (!reg_8901_l3)
9038 _GET_REGULATOR(reg_8901_l3, "8901_l3");
9039
9040 if (on) {
9041 rc = regulator_set_voltage(reg_8901_l3, 3300000, 3300000);
9042 if (!rc)
9043 rc = regulator_enable(reg_8901_l3);
9044 if (rc) {
9045 pr_err("'%s' regulator enable failed, rc=%d\n",
9046 "8901_l3", rc);
9047 return rc;
9048 }
9049 rc = gpio_request(169, "HDMI_CEC_VAR");
9050 if (rc) {
9051 pr_err("'%s'(%d) gpio_request failed, rc=%d\n",
9052 "HDMI_CEC_VAR", 169, rc);
9053 goto error;
9054 }
9055 pr_info("%s(on): success\n", __func__);
9056 } else {
9057 gpio_free(169);
9058 rc = regulator_disable(reg_8901_l3);
9059 if (rc)
9060 pr_warning("'%s' regulator disable failed, rc=%d\n",
9061 "8901_l3", rc);
9062 pr_info("%s(off): success\n", __func__);
9063 }
9064
9065 prev_on = on;
9066
9067 return 0;
9068error:
9069 regulator_disable(reg_8901_l3);
9070 return rc;
9071}
9072
9073#undef _GET_REGULATOR
9074
9075#endif /* CONFIG_FB_MSM_HDMI_MSM_PANEL */
9076
9077static int lcdc_panel_power(int on)
9078{
9079 int flag_on = !!on;
9080 static int lcdc_power_save_on;
9081
9082 if (lcdc_power_save_on == flag_on)
9083 return 0;
9084
9085 lcdc_power_save_on = flag_on;
9086
9087 lcdc_samsung_panel_power(on);
9088
9089 return 0;
9090}
9091
9092#ifdef CONFIG_MSM_BUS_SCALING
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07009093static struct msm_bus_vectors mdp_init_vectors[] = {
9094 /* For now, 0th array entry is reserved.
9095 * Please leave 0 as is and don't use it
9096 */
9097 {
9098 .src = MSM_BUS_MASTER_MDP_PORT0,
9099 .dst = MSM_BUS_SLAVE_SMI,
9100 .ab = 0,
9101 .ib = 0,
9102 },
9103 /* Master and slaves can be from different fabrics */
9104 {
9105 .src = MSM_BUS_MASTER_MDP_PORT0,
9106 .dst = MSM_BUS_SLAVE_EBI_CH0,
9107 .ab = 0,
9108 .ib = 0,
9109 },
9110};
9111
Ravishangar Kalyanam75f37322011-10-14 12:15:40 -07009112#ifdef CONFIG_FB_MSM_HDMI_AS_PRIMARY
9113static struct msm_bus_vectors hdmi_as_primary_vectors[] = {
9114 /* If HDMI is used as primary */
9115 {
9116 .src = MSM_BUS_MASTER_MDP_PORT0,
9117 .dst = MSM_BUS_SLAVE_SMI,
9118 .ab = 2000000000,
9119 .ib = 2000000000,
9120 },
9121 /* Master and slaves can be from different fabrics */
9122 {
9123 .src = MSM_BUS_MASTER_MDP_PORT0,
9124 .dst = MSM_BUS_SLAVE_EBI_CH0,
9125 .ab = 2000000000,
9126 .ib = 2000000000,
9127 },
9128};
9129
9130static struct msm_bus_paths mdp_bus_scale_usecases[] = {
9131 {
9132 ARRAY_SIZE(mdp_init_vectors),
9133 mdp_init_vectors,
9134 },
9135 {
9136 ARRAY_SIZE(hdmi_as_primary_vectors),
9137 hdmi_as_primary_vectors,
9138 },
9139 {
9140 ARRAY_SIZE(hdmi_as_primary_vectors),
9141 hdmi_as_primary_vectors,
9142 },
9143 {
9144 ARRAY_SIZE(hdmi_as_primary_vectors),
9145 hdmi_as_primary_vectors,
9146 },
9147 {
9148 ARRAY_SIZE(hdmi_as_primary_vectors),
9149 hdmi_as_primary_vectors,
9150 },
9151 {
9152 ARRAY_SIZE(hdmi_as_primary_vectors),
9153 hdmi_as_primary_vectors,
9154 },
9155};
9156#else
9157#ifdef CONFIG_FB_MSM_LCDC_DSUB
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07009158static struct msm_bus_vectors mdp_sd_smi_vectors[] = {
9159 /* Default case static display/UI/2d/3d if FB SMI */
9160 {
9161 .src = MSM_BUS_MASTER_MDP_PORT0,
9162 .dst = MSM_BUS_SLAVE_SMI,
9163 .ab = 388800000,
9164 .ib = 486000000,
9165 },
9166 /* Master and slaves can be from different fabrics */
9167 {
9168 .src = MSM_BUS_MASTER_MDP_PORT0,
9169 .dst = MSM_BUS_SLAVE_EBI_CH0,
9170 .ab = 0,
9171 .ib = 0,
9172 },
9173};
9174
9175static struct msm_bus_vectors mdp_sd_ebi_vectors[] = {
9176 /* Default case static display/UI/2d/3d if FB SMI */
9177 {
9178 .src = MSM_BUS_MASTER_MDP_PORT0,
9179 .dst = MSM_BUS_SLAVE_SMI,
9180 .ab = 0,
9181 .ib = 0,
9182 },
9183 /* Master and slaves can be from different fabrics */
9184 {
9185 .src = MSM_BUS_MASTER_MDP_PORT0,
9186 .dst = MSM_BUS_SLAVE_EBI_CH0,
9187 .ab = 388800000,
9188 .ib = 486000000 * 2,
9189 },
9190};
9191static struct msm_bus_vectors mdp_vga_vectors[] = {
9192 /* VGA and less video */
9193 {
9194 .src = MSM_BUS_MASTER_MDP_PORT0,
9195 .dst = MSM_BUS_SLAVE_SMI,
9196 .ab = 458092800,
9197 .ib = 572616000,
9198 },
9199 {
9200 .src = MSM_BUS_MASTER_MDP_PORT0,
9201 .dst = MSM_BUS_SLAVE_EBI_CH0,
9202 .ab = 458092800,
9203 .ib = 572616000 * 2,
9204 },
9205};
9206static struct msm_bus_vectors mdp_720p_vectors[] = {
9207 /* 720p and less video */
9208 {
9209 .src = MSM_BUS_MASTER_MDP_PORT0,
9210 .dst = MSM_BUS_SLAVE_SMI,
9211 .ab = 471744000,
9212 .ib = 589680000,
9213 },
9214 /* Master and slaves can be from different fabrics */
9215 {
9216 .src = MSM_BUS_MASTER_MDP_PORT0,
9217 .dst = MSM_BUS_SLAVE_EBI_CH0,
9218 .ab = 471744000,
9219 .ib = 589680000 * 2,
9220 },
9221};
9222
9223static struct msm_bus_vectors mdp_1080p_vectors[] = {
9224 /* 1080p and less video */
9225 {
9226 .src = MSM_BUS_MASTER_MDP_PORT0,
9227 .dst = MSM_BUS_SLAVE_SMI,
9228 .ab = 575424000,
9229 .ib = 719280000,
9230 },
9231 /* Master and slaves can be from different fabrics */
9232 {
9233 .src = MSM_BUS_MASTER_MDP_PORT0,
9234 .dst = MSM_BUS_SLAVE_EBI_CH0,
9235 .ab = 575424000,
9236 .ib = 719280000 * 2,
9237 },
9238};
9239
9240#else
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07009241static struct msm_bus_vectors mdp_sd_smi_vectors[] = {
9242 /* Default case static display/UI/2d/3d if FB SMI */
9243 {
9244 .src = MSM_BUS_MASTER_MDP_PORT0,
9245 .dst = MSM_BUS_SLAVE_SMI,
9246 .ab = 175110000,
9247 .ib = 218887500,
9248 },
9249 /* Master and slaves can be from different fabrics */
9250 {
9251 .src = MSM_BUS_MASTER_MDP_PORT0,
9252 .dst = MSM_BUS_SLAVE_EBI_CH0,
9253 .ab = 0,
9254 .ib = 0,
9255 },
9256};
9257
9258static struct msm_bus_vectors mdp_sd_ebi_vectors[] = {
9259 /* Default case static display/UI/2d/3d if FB SMI */
9260 {
9261 .src = MSM_BUS_MASTER_MDP_PORT0,
9262 .dst = MSM_BUS_SLAVE_SMI,
9263 .ab = 0,
9264 .ib = 0,
9265 },
9266 /* Master and slaves can be from different fabrics */
9267 {
9268 .src = MSM_BUS_MASTER_MDP_PORT0,
9269 .dst = MSM_BUS_SLAVE_EBI_CH0,
9270 .ab = 216000000,
9271 .ib = 270000000 * 2,
9272 },
9273};
9274static struct msm_bus_vectors mdp_vga_vectors[] = {
9275 /* VGA and less video */
9276 {
9277 .src = MSM_BUS_MASTER_MDP_PORT0,
9278 .dst = MSM_BUS_SLAVE_SMI,
9279 .ab = 216000000,
9280 .ib = 270000000,
9281 },
9282 {
9283 .src = MSM_BUS_MASTER_MDP_PORT0,
9284 .dst = MSM_BUS_SLAVE_EBI_CH0,
9285 .ab = 216000000,
9286 .ib = 270000000 * 2,
9287 },
9288};
9289
9290static struct msm_bus_vectors mdp_720p_vectors[] = {
9291 /* 720p and less video */
9292 {
9293 .src = MSM_BUS_MASTER_MDP_PORT0,
9294 .dst = MSM_BUS_SLAVE_SMI,
9295 .ab = 230400000,
9296 .ib = 288000000,
9297 },
9298 /* Master and slaves can be from different fabrics */
9299 {
9300 .src = MSM_BUS_MASTER_MDP_PORT0,
9301 .dst = MSM_BUS_SLAVE_EBI_CH0,
9302 .ab = 230400000,
9303 .ib = 288000000 * 2,
9304 },
9305};
9306
9307static struct msm_bus_vectors mdp_1080p_vectors[] = {
9308 /* 1080p and less video */
9309 {
9310 .src = MSM_BUS_MASTER_MDP_PORT0,
9311 .dst = MSM_BUS_SLAVE_SMI,
9312 .ab = 334080000,
9313 .ib = 417600000,
9314 },
9315 /* Master and slaves can be from different fabrics */
9316 {
9317 .src = MSM_BUS_MASTER_MDP_PORT0,
9318 .dst = MSM_BUS_SLAVE_EBI_CH0,
9319 .ab = 334080000,
Ravishangar Kalyanam731beb92011-07-07 18:27:32 -07009320 .ib = 550000000 * 2,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07009321 },
9322};
9323
9324#endif
9325static struct msm_bus_paths mdp_bus_scale_usecases[] = {
9326 {
9327 ARRAY_SIZE(mdp_init_vectors),
9328 mdp_init_vectors,
9329 },
9330 {
9331 ARRAY_SIZE(mdp_sd_smi_vectors),
9332 mdp_sd_smi_vectors,
9333 },
9334 {
9335 ARRAY_SIZE(mdp_sd_ebi_vectors),
9336 mdp_sd_ebi_vectors,
9337 },
9338 {
9339 ARRAY_SIZE(mdp_vga_vectors),
9340 mdp_vga_vectors,
9341 },
9342 {
9343 ARRAY_SIZE(mdp_720p_vectors),
9344 mdp_720p_vectors,
9345 },
9346 {
9347 ARRAY_SIZE(mdp_1080p_vectors),
9348 mdp_1080p_vectors,
9349 },
9350};
Ravishangar Kalyanam75f37322011-10-14 12:15:40 -07009351#endif
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07009352static struct msm_bus_scale_pdata mdp_bus_scale_pdata = {
9353 mdp_bus_scale_usecases,
9354 ARRAY_SIZE(mdp_bus_scale_usecases),
9355 .name = "mdp",
9356};
9357
9358#endif
9359#ifdef CONFIG_MSM_BUS_SCALING
9360static struct msm_bus_vectors dtv_bus_init_vectors[] = {
9361 /* For now, 0th array entry is reserved.
9362 * Please leave 0 as is and don't use it
9363 */
9364 {
9365 .src = MSM_BUS_MASTER_MDP_PORT0,
9366 .dst = MSM_BUS_SLAVE_SMI,
9367 .ab = 0,
9368 .ib = 0,
9369 },
9370 /* Master and slaves can be from different fabrics */
9371 {
9372 .src = MSM_BUS_MASTER_MDP_PORT0,
9373 .dst = MSM_BUS_SLAVE_EBI_CH0,
9374 .ab = 0,
9375 .ib = 0,
9376 },
9377};
Ravishangar Kalyanam75f37322011-10-14 12:15:40 -07009378#ifdef CONFIG_FB_MSM_HDMI_AS_PRIMARY
9379static struct msm_bus_vectors dtv_bus_def_vectors[] = {
9380 /* For now, 0th array entry is reserved.
9381 * Please leave 0 as is and don't use it
9382 */
9383 {
9384 .src = MSM_BUS_MASTER_MDP_PORT0,
9385 .dst = MSM_BUS_SLAVE_SMI,
9386 .ab = 2000000000,
9387 .ib = 2000000000,
9388 },
9389 /* Master and slaves can be from different fabrics */
9390 {
9391 .src = MSM_BUS_MASTER_MDP_PORT0,
9392 .dst = MSM_BUS_SLAVE_EBI_CH0,
9393 .ab = 2000000000,
9394 .ib = 2000000000,
9395 },
9396};
9397#else
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07009398static struct msm_bus_vectors dtv_bus_def_vectors[] = {
9399 /* For now, 0th array entry is reserved.
9400 * Please leave 0 as is and don't use it
9401 */
9402 {
9403 .src = MSM_BUS_MASTER_MDP_PORT0,
9404 .dst = MSM_BUS_SLAVE_SMI,
9405 .ab = 566092800,
9406 .ib = 707616000,
9407 },
9408 /* Master and slaves can be from different fabrics */
9409 {
9410 .src = MSM_BUS_MASTER_MDP_PORT0,
9411 .dst = MSM_BUS_SLAVE_EBI_CH0,
9412 .ab = 566092800,
9413 .ib = 707616000,
9414 },
9415};
Ravishangar Kalyanam75f37322011-10-14 12:15:40 -07009416#endif
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07009417static struct msm_bus_paths dtv_bus_scale_usecases[] = {
9418 {
9419 ARRAY_SIZE(dtv_bus_init_vectors),
9420 dtv_bus_init_vectors,
9421 },
9422 {
9423 ARRAY_SIZE(dtv_bus_def_vectors),
9424 dtv_bus_def_vectors,
9425 },
9426};
9427static struct msm_bus_scale_pdata dtv_bus_scale_pdata = {
9428 dtv_bus_scale_usecases,
9429 ARRAY_SIZE(dtv_bus_scale_usecases),
9430 .name = "dtv",
9431};
9432
9433static struct lcdc_platform_data dtv_pdata = {
9434 .bus_scale_table = &dtv_bus_scale_pdata,
9435};
9436#endif
9437
9438
9439static struct lcdc_platform_data lcdc_pdata = {
9440 .lcdc_power_save = lcdc_panel_power,
9441};
9442
9443
9444#define MDP_VSYNC_GPIO 28
9445
9446/*
9447 * MIPI_DSI only use 8058_LDO0 which need always on
9448 * therefore it need to be put at low power mode if
9449 * it was not used instead of turn it off.
9450 */
9451static int mipi_dsi_panel_power(int on)
9452{
9453 int flag_on = !!on;
9454 static int mipi_dsi_power_save_on;
9455 static struct regulator *ldo0;
9456 int rc = 0;
9457
9458 if (mipi_dsi_power_save_on == flag_on)
9459 return 0;
9460
9461 mipi_dsi_power_save_on = flag_on;
9462
9463 if (ldo0 == NULL) { /* init */
9464 ldo0 = regulator_get(NULL, "8058_l0");
9465 if (IS_ERR(ldo0)) {
9466 pr_debug("%s: LDO0 failed\n", __func__);
9467 rc = PTR_ERR(ldo0);
9468 return rc;
9469 }
9470
9471 rc = regulator_set_voltage(ldo0, 1200000, 1200000);
9472 if (rc)
9473 goto out;
9474
9475 rc = regulator_enable(ldo0);
9476 if (rc)
9477 goto out;
9478 }
9479
9480 if (on) {
9481 /* set ldo0 to HPM */
9482 rc = regulator_set_optimum_mode(ldo0, 100000);
9483 if (rc < 0)
9484 goto out;
9485 } else {
9486 /* set ldo0 to LPM */
9487 rc = regulator_set_optimum_mode(ldo0, 9000);
9488 if (rc < 0)
9489 goto out;
9490 }
9491
9492 return 0;
9493out:
9494 regulator_disable(ldo0);
9495 regulator_put(ldo0);
9496 ldo0 = NULL;
9497 return rc;
9498}
9499
9500static struct mipi_dsi_platform_data mipi_dsi_pdata = {
9501 .vsync_gpio = MDP_VSYNC_GPIO,
9502 .dsi_power_save = mipi_dsi_panel_power,
9503};
9504
9505#ifdef CONFIG_FB_MSM_TVOUT
9506static struct regulator *reg_8058_l13;
9507
9508static int atv_dac_power(int on)
9509{
9510 int rc = 0;
9511 #define _GET_REGULATOR(var, name) do { \
9512 var = regulator_get(NULL, name); \
9513 if (IS_ERR(var)) { \
9514 pr_info("'%s' regulator not found, rc=%ld\n", \
9515 name, IS_ERR(var)); \
9516 var = NULL; \
9517 return -ENODEV; \
9518 } \
9519 } while (0)
9520
9521 if (!reg_8058_l13)
9522 _GET_REGULATOR(reg_8058_l13, "8058_l13");
9523 #undef _GET_REGULATOR
9524
9525 if (on) {
9526 rc = regulator_set_voltage(reg_8058_l13, 2050000, 2050000);
9527 if (rc) {
9528 pr_info("%s: '%s' regulator set voltage failed,\
9529 rc=%d\n", __func__, "8058_l13", rc);
9530 return rc;
9531 }
9532
9533 rc = regulator_enable(reg_8058_l13);
9534 if (rc) {
9535 pr_err("%s: '%s' regulator enable failed,\
9536 rc=%d\n", __func__, "8058_l13", rc);
9537 return rc;
9538 }
9539 } else {
9540 rc = regulator_force_disable(reg_8058_l13);
9541 if (rc)
9542 pr_warning("%s: '%s' regulator disable failed, rc=%d\n",
9543 __func__, "8058_l13", rc);
9544 }
9545 return rc;
9546
9547}
9548#endif
9549
9550#ifdef CONFIG_FB_MSM_MIPI_DSI
9551int mdp_core_clk_rate_table[] = {
9552 85330000,
9553 85330000,
9554 160000000,
9555 200000000,
9556};
Ravishangar Kalyanam75f37322011-10-14 12:15:40 -07009557#elif defined(CONFIG_FB_MSM_HDMI_AS_PRIMARY)
9558int mdp_core_clk_rate_table[] = {
9559 200000000,
9560 200000000,
9561 200000000,
9562 200000000,
9563};
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07009564#else
9565int mdp_core_clk_rate_table[] = {
9566 59080000,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07009567 85330000,
kuogee hsieh26791a92011-08-01 18:35:58 -07009568 128000000,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07009569 200000000,
9570};
9571#endif
9572
9573static struct msm_panel_common_pdata mdp_pdata = {
9574 .gpio = MDP_VSYNC_GPIO,
Ravishangar Kalyanam75f37322011-10-14 12:15:40 -07009575#ifdef CONFIG_FB_MSM_HDMI_AS_PRIMARY
9576 .mdp_core_clk_rate = 200000000,
9577#else
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07009578 .mdp_core_clk_rate = 59080000,
Ravishangar Kalyanam75f37322011-10-14 12:15:40 -07009579#endif
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07009580 .mdp_core_clk_table = mdp_core_clk_rate_table,
9581 .num_mdp_clk = ARRAY_SIZE(mdp_core_clk_rate_table),
9582#ifdef CONFIG_MSM_BUS_SCALING
9583 .mdp_bus_scale_table = &mdp_bus_scale_pdata,
9584#endif
9585 .mdp_rev = MDP_REV_41,
kuogee hsiehc9a2e6d2011-09-12 15:27:01 -07009586 .writeback_offset = writeback_offset,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07009587};
9588
9589#ifdef CONFIG_FB_MSM_TVOUT
9590
9591#ifdef CONFIG_MSM_BUS_SCALING
9592static struct msm_bus_vectors atv_bus_init_vectors[] = {
9593 /* For now, 0th array entry is reserved.
9594 * Please leave 0 as is and don't use it
9595 */
9596 {
9597 .src = MSM_BUS_MASTER_MDP_PORT0,
9598 .dst = MSM_BUS_SLAVE_SMI,
9599 .ab = 0,
9600 .ib = 0,
9601 },
9602 /* Master and slaves can be from different fabrics */
9603 {
9604 .src = MSM_BUS_MASTER_MDP_PORT0,
9605 .dst = MSM_BUS_SLAVE_EBI_CH0,
9606 .ab = 0,
9607 .ib = 0,
9608 },
9609};
9610static struct msm_bus_vectors atv_bus_def_vectors[] = {
9611 /* For now, 0th array entry is reserved.
9612 * Please leave 0 as is and don't use it
9613 */
9614 {
9615 .src = MSM_BUS_MASTER_MDP_PORT0,
9616 .dst = MSM_BUS_SLAVE_SMI,
9617 .ab = 236390400,
9618 .ib = 265939200,
9619 },
9620 /* Master and slaves can be from different fabrics */
9621 {
9622 .src = MSM_BUS_MASTER_MDP_PORT0,
9623 .dst = MSM_BUS_SLAVE_EBI_CH0,
9624 .ab = 236390400,
9625 .ib = 265939200,
9626 },
9627};
9628static struct msm_bus_paths atv_bus_scale_usecases[] = {
9629 {
9630 ARRAY_SIZE(atv_bus_init_vectors),
9631 atv_bus_init_vectors,
9632 },
9633 {
9634 ARRAY_SIZE(atv_bus_def_vectors),
9635 atv_bus_def_vectors,
9636 },
9637};
9638static struct msm_bus_scale_pdata atv_bus_scale_pdata = {
9639 atv_bus_scale_usecases,
9640 ARRAY_SIZE(atv_bus_scale_usecases),
9641 .name = "atv",
9642};
9643#endif
9644
9645static struct tvenc_platform_data atv_pdata = {
9646 .poll = 0,
9647 .pm_vid_en = atv_dac_power,
9648#ifdef CONFIG_MSM_BUS_SCALING
9649 .bus_scale_table = &atv_bus_scale_pdata,
9650#endif
9651};
9652#endif
9653
9654static void __init msm_fb_add_devices(void)
9655{
9656#ifdef CONFIG_FB_MSM_LCDC_DSUB
9657 mdp_pdata.mdp_core_clk_table = NULL;
9658 mdp_pdata.num_mdp_clk = 0;
9659 mdp_pdata.mdp_core_clk_rate = 200000000;
9660#endif
9661 if (machine_is_msm8x60_rumi3())
9662 msm_fb_register_device("mdp", NULL);
9663 else
9664 msm_fb_register_device("mdp", &mdp_pdata);
9665
9666 msm_fb_register_device("lcdc", &lcdc_pdata);
9667 msm_fb_register_device("mipi_dsi", &mipi_dsi_pdata);
9668#ifdef CONFIG_MSM_BUS_SCALING
9669 msm_fb_register_device("dtv", &dtv_pdata);
9670#endif
9671#ifdef CONFIG_FB_MSM_TVOUT
9672 msm_fb_register_device("tvenc", &atv_pdata);
9673 msm_fb_register_device("tvout_device", NULL);
9674#endif
9675}
9676
9677#if (defined(CONFIG_MARIMBA_CORE)) && \
9678 (defined(CONFIG_MSM_BT_POWER) || defined(CONFIG_MSM_BT_POWER_MODULE))
9679
9680static const struct {
9681 char *name;
9682 int vmin;
9683 int vmax;
9684} bt_regs_info[] = {
9685 { "8058_s3", 1800000, 1800000 },
9686 { "8058_s2", 1300000, 1300000 },
9687 { "8058_l8", 2900000, 3050000 },
9688};
9689
9690static struct {
9691 bool enabled;
9692} bt_regs_status[] = {
9693 { false },
9694 { false },
9695 { false },
9696};
9697static struct regulator *bt_regs[ARRAY_SIZE(bt_regs_info)];
9698
9699static int bahama_bt(int on)
9700{
9701 int rc;
9702 int i;
9703 struct marimba config = { .mod_id = SLAVE_ID_BAHAMA};
9704
9705 struct bahama_variant_register {
9706 const size_t size;
9707 const struct bahama_config_register *set;
9708 };
9709
9710 const struct bahama_config_register *p;
9711
9712 u8 version;
9713
9714 const struct bahama_config_register v10_bt_on[] = {
9715 { 0xE9, 0x00, 0xFF },
9716 { 0xF4, 0x80, 0xFF },
9717 { 0xE4, 0x00, 0xFF },
9718 { 0xE5, 0x00, 0x0F },
9719#ifdef CONFIG_WLAN
9720 { 0xE6, 0x38, 0x7F },
9721 { 0xE7, 0x06, 0xFF },
9722#endif
9723 { 0xE9, 0x21, 0xFF },
9724 { 0x01, 0x0C, 0x1F },
9725 { 0x01, 0x08, 0x1F },
9726 };
9727
9728 const struct bahama_config_register v20_bt_on_fm_off[] = {
9729 { 0x11, 0x0C, 0xFF },
9730 { 0x13, 0x01, 0xFF },
9731 { 0xF4, 0x80, 0xFF },
9732 { 0xF0, 0x00, 0xFF },
9733 { 0xE9, 0x00, 0xFF },
9734#ifdef CONFIG_WLAN
9735 { 0x81, 0x00, 0x7F },
9736 { 0x82, 0x00, 0xFF },
9737 { 0xE6, 0x38, 0x7F },
9738 { 0xE7, 0x06, 0xFF },
9739#endif
9740 { 0xE9, 0x21, 0xFF },
9741 };
9742
9743 const struct bahama_config_register v20_bt_on_fm_on[] = {
9744 { 0x11, 0x0C, 0xFF },
9745 { 0x13, 0x01, 0xFF },
9746 { 0xF4, 0x86, 0xFF },
9747 { 0xF0, 0x06, 0xFF },
9748 { 0xE9, 0x00, 0xFF },
9749#ifdef CONFIG_WLAN
9750 { 0x81, 0x00, 0x7F },
9751 { 0x82, 0x00, 0xFF },
9752 { 0xE6, 0x38, 0x7F },
9753 { 0xE7, 0x06, 0xFF },
9754#endif
9755 { 0xE9, 0x21, 0xFF },
9756 };
9757
9758 const struct bahama_config_register v10_bt_off[] = {
9759 { 0xE9, 0x00, 0xFF },
9760 };
9761
9762 const struct bahama_config_register v20_bt_off_fm_off[] = {
9763 { 0xF4, 0x84, 0xFF },
9764 { 0xF0, 0x04, 0xFF },
9765 { 0xE9, 0x00, 0xFF }
9766 };
9767
9768 const struct bahama_config_register v20_bt_off_fm_on[] = {
9769 { 0xF4, 0x86, 0xFF },
9770 { 0xF0, 0x06, 0xFF },
9771 { 0xE9, 0x00, 0xFF }
9772 };
9773 const struct bahama_variant_register bt_bahama[2][3] = {
9774 {
9775 { ARRAY_SIZE(v10_bt_off), v10_bt_off },
9776 { ARRAY_SIZE(v20_bt_off_fm_off), v20_bt_off_fm_off },
9777 { ARRAY_SIZE(v20_bt_off_fm_on), v20_bt_off_fm_on }
9778 },
9779 {
9780 { ARRAY_SIZE(v10_bt_on), v10_bt_on },
9781 { ARRAY_SIZE(v20_bt_on_fm_off), v20_bt_on_fm_off },
9782 { ARRAY_SIZE(v20_bt_on_fm_on), v20_bt_on_fm_on }
9783 }
9784 };
9785
9786 u8 offset = 0; /* index into bahama configs */
9787
9788 on = on ? 1 : 0;
9789 version = read_bahama_ver();
9790
9791 if (version == VER_UNSUPPORTED) {
9792 dev_err(&msm_bt_power_device.dev,
9793 "%s: unsupported version\n",
9794 __func__);
9795 return -EIO;
9796 }
9797
9798 if (version == VER_2_0) {
9799 if (marimba_get_fm_status(&config))
9800 offset = 0x01;
9801 }
9802
9803 /* Voting off 1.3V S2 Regulator,BahamaV2 used in Normal mode */
9804 if (on && (version == VER_2_0)) {
9805 for (i = 0; i < ARRAY_SIZE(bt_regs_info); i++) {
9806 if ((!strcmp(bt_regs_info[i].name, "8058_s2"))
9807 && (bt_regs_status[i].enabled == true)) {
9808 if (regulator_disable(bt_regs[i])) {
9809 dev_err(&msm_bt_power_device.dev,
9810 "%s: regulator disable failed",
9811 __func__);
9812 }
9813 bt_regs_status[i].enabled = false;
9814 break;
9815 }
9816 }
9817 }
9818
9819 p = bt_bahama[on][version + offset].set;
9820
9821 dev_info(&msm_bt_power_device.dev,
9822 "%s: found version %d\n", __func__, version);
9823
9824 for (i = 0; i < bt_bahama[on][version + offset].size; i++) {
9825 u8 value = (p+i)->value;
9826 rc = marimba_write_bit_mask(&config,
9827 (p+i)->reg,
9828 &value,
9829 sizeof((p+i)->value),
9830 (p+i)->mask);
9831 if (rc < 0) {
9832 dev_err(&msm_bt_power_device.dev,
9833 "%s: reg %d write failed: %d\n",
9834 __func__, (p+i)->reg, rc);
9835 return rc;
9836 }
9837 dev_dbg(&msm_bt_power_device.dev,
9838 "%s: reg 0x%02x write value 0x%02x mask 0x%02x\n",
9839 __func__, (p+i)->reg,
9840 value, (p+i)->mask);
9841 }
9842 /* Update BT Status */
9843 if (on)
9844 marimba_set_bt_status(&config, true);
9845 else
9846 marimba_set_bt_status(&config, false);
9847
9848 return 0;
9849}
9850
9851static int bluetooth_use_regulators(int on)
9852{
9853 int i, recover = -1, rc = 0;
9854
9855 for (i = 0; i < ARRAY_SIZE(bt_regs_info); i++) {
9856 bt_regs[i] = on ? regulator_get(&msm_bt_power_device.dev,
9857 bt_regs_info[i].name) :
9858 (regulator_put(bt_regs[i]), NULL);
9859 if (IS_ERR(bt_regs[i])) {
9860 rc = PTR_ERR(bt_regs[i]);
9861 dev_err(&msm_bt_power_device.dev,
9862 "regulator %s get failed (%d)\n",
9863 bt_regs_info[i].name, rc);
9864 recover = i - 1;
9865 bt_regs[i] = NULL;
9866 break;
9867 }
9868
9869 if (!on)
9870 continue;
9871
9872 rc = regulator_set_voltage(bt_regs[i],
9873 bt_regs_info[i].vmin,
9874 bt_regs_info[i].vmax);
9875 if (rc < 0) {
9876 dev_err(&msm_bt_power_device.dev,
9877 "regulator %s voltage set (%d)\n",
9878 bt_regs_info[i].name, rc);
9879 recover = i;
9880 break;
9881 }
9882 }
9883
9884 if (on && (recover > -1))
9885 for (i = recover; i >= 0; i--) {
9886 regulator_put(bt_regs[i]);
9887 bt_regs[i] = NULL;
9888 }
9889
9890 return rc;
9891}
9892
9893static int bluetooth_switch_regulators(int on)
9894{
9895 int i, rc = 0;
9896
9897 for (i = 0; i < ARRAY_SIZE(bt_regs_info); i++) {
9898 if (on && (bt_regs_status[i].enabled == false)) {
9899 rc = regulator_enable(bt_regs[i]);
9900 if (rc < 0) {
9901 dev_err(&msm_bt_power_device.dev,
9902 "regulator %s %s failed (%d)\n",
9903 bt_regs_info[i].name,
9904 "enable", rc);
9905 if (i > 0) {
9906 while (--i) {
9907 regulator_disable(bt_regs[i]);
9908 bt_regs_status[i].enabled
9909 = false;
9910 }
9911 break;
9912 }
9913 }
9914 bt_regs_status[i].enabled = true;
9915 } else if (!on && (bt_regs_status[i].enabled == true)) {
9916 rc = regulator_disable(bt_regs[i]);
9917 if (rc < 0) {
9918 dev_err(&msm_bt_power_device.dev,
9919 "regulator %s %s failed (%d)\n",
9920 bt_regs_info[i].name,
9921 "disable", rc);
9922 break;
9923 }
9924 bt_regs_status[i].enabled = false;
9925 }
9926 }
9927 return rc;
9928}
9929
9930static struct msm_xo_voter *bt_clock;
9931
9932static int bluetooth_power(int on)
9933{
9934 int rc = 0;
9935 int id;
9936
9937 /* In case probe function fails, cur_connv_type would be -1 */
9938 id = adie_get_detected_connectivity_type();
9939 if (id != BAHAMA_ID) {
9940 pr_err("%s: unexpected adie connectivity type: %d\n",
9941 __func__, id);
9942 return -ENODEV;
9943 }
9944
9945 if (on) {
9946
9947 rc = bluetooth_use_regulators(1);
9948 if (rc < 0)
9949 goto out;
9950
9951 rc = bluetooth_switch_regulators(1);
9952
9953 if (rc < 0)
9954 goto fail_put;
9955
9956 bt_clock = msm_xo_get(MSM_XO_TCXO_D0, "bt_power");
9957
9958 if (IS_ERR(bt_clock)) {
9959 pr_err("Couldn't get TCXO_D0 voter\n");
9960 goto fail_switch;
9961 }
9962
9963 rc = msm_xo_mode_vote(bt_clock, MSM_XO_MODE_ON);
9964
9965 if (rc < 0) {
9966 pr_err("Failed to vote for TCXO_DO ON\n");
9967 goto fail_vote;
9968 }
9969
9970 rc = bahama_bt(1);
9971
9972 if (rc < 0)
9973 goto fail_clock;
9974
9975 msleep(10);
9976
9977 rc = msm_xo_mode_vote(bt_clock, MSM_XO_MODE_PIN_CTRL);
9978
9979 if (rc < 0) {
9980 pr_err("Failed to vote for TCXO_DO pin control\n");
9981 goto fail_vote;
9982 }
9983 } else {
9984 /* check for initial RFKILL block (power off) */
9985 /* some RFKILL versions/configurations rfkill_register */
9986 /* calls here for an initial set_block */
9987 /* avoid calling i2c and regulator before unblock (on) */
9988 if (platform_get_drvdata(&msm_bt_power_device) == NULL) {
9989 dev_info(&msm_bt_power_device.dev,
9990 "%s: initialized OFF/blocked\n", __func__);
9991 goto out;
9992 }
9993
9994 bahama_bt(0);
9995
9996fail_clock:
9997 msm_xo_mode_vote(bt_clock, MSM_XO_MODE_OFF);
9998fail_vote:
9999 msm_xo_put(bt_clock);
10000fail_switch:
10001 bluetooth_switch_regulators(0);
10002fail_put:
10003 bluetooth_use_regulators(0);
10004 }
10005
10006out:
10007 if (rc < 0)
10008 on = 0;
10009 dev_info(&msm_bt_power_device.dev,
10010 "Bluetooth power switch: state %d result %d\n", on, rc);
10011
10012 return rc;
10013}
10014
10015#endif /*CONFIG_MARIMBA_CORE, CONFIG_MSM_BT_POWER, CONFIG_MSM_BT_POWER_MODULE*/
10016
10017static void __init msm8x60_cfg_smsc911x(void)
10018{
10019 smsc911x_resources[1].start =
10020 PM8058_GPIO_IRQ(PM8058_IRQ_BASE, 6);
10021 smsc911x_resources[1].end =
10022 PM8058_GPIO_IRQ(PM8058_IRQ_BASE, 6);
10023}
10024
10025#ifdef CONFIG_MSM_RPM
10026static struct msm_rpm_platform_data msm_rpm_data = {
10027 .reg_base_addrs = {
10028 [MSM_RPM_PAGE_STATUS] = MSM_RPM_BASE,
10029 [MSM_RPM_PAGE_CTRL] = MSM_RPM_BASE + 0x400,
10030 [MSM_RPM_PAGE_REQ] = MSM_RPM_BASE + 0x600,
10031 [MSM_RPM_PAGE_ACK] = MSM_RPM_BASE + 0xa00,
10032 },
10033
10034 .irq_ack = RPM_SCSS_CPU0_GP_HIGH_IRQ,
10035 .irq_err = RPM_SCSS_CPU0_GP_LOW_IRQ,
10036 .irq_vmpm = RPM_SCSS_CPU0_GP_MEDIUM_IRQ,
10037 .msm_apps_ipc_rpm_reg = MSM_GCC_BASE + 0x008,
10038 .msm_apps_ipc_rpm_val = 4,
10039};
10040#endif
10041
Laura Abbott5d2d1e62011-08-10 16:27:35 -070010042void msm_fusion_setup_pinctrl(void)
10043{
10044 struct msm_xo_voter *a1;
10045
10046 if (socinfo_get_platform_subtype() == 0x3) {
10047 /*
10048 * Vote for the A1 clock to be in pin control mode before
10049 * the external images are loaded.
10050 */
10051 a1 = msm_xo_get(MSM_XO_TCXO_A1, "mdm");
10052 BUG_ON(!a1);
10053 msm_xo_mode_vote(a1, MSM_XO_MODE_PIN_CTRL);
10054 }
10055}
10056
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070010057struct msm_board_data {
10058 struct msm_gpiomux_configs *gpiomux_cfgs;
10059};
10060
10061static struct msm_board_data msm8x60_rumi3_board_data __initdata = {
10062 .gpiomux_cfgs = msm8x60_surf_ffa_gpiomux_cfgs,
10063};
10064
10065static struct msm_board_data msm8x60_sim_board_data __initdata = {
10066 .gpiomux_cfgs = msm8x60_surf_ffa_gpiomux_cfgs,
10067};
10068
10069static struct msm_board_data msm8x60_surf_board_data __initdata = {
10070 .gpiomux_cfgs = msm8x60_surf_ffa_gpiomux_cfgs,
10071};
10072
10073static struct msm_board_data msm8x60_ffa_board_data __initdata = {
10074 .gpiomux_cfgs = msm8x60_surf_ffa_gpiomux_cfgs,
10075};
10076
10077static struct msm_board_data msm8x60_fluid_board_data __initdata = {
10078 .gpiomux_cfgs = msm8x60_fluid_gpiomux_cfgs,
10079};
10080
10081static struct msm_board_data msm8x60_charm_surf_board_data __initdata = {
10082 .gpiomux_cfgs = msm8x60_charm_gpiomux_cfgs,
10083};
10084
10085static struct msm_board_data msm8x60_charm_ffa_board_data __initdata = {
10086 .gpiomux_cfgs = msm8x60_charm_gpiomux_cfgs,
10087};
10088
Zhang Chang Kenef05b172011-07-27 15:28:13 -040010089static struct msm_board_data msm8x60_dragon_board_data __initdata = {
10090 .gpiomux_cfgs = msm8x60_dragon_gpiomux_cfgs,
10091};
10092
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070010093static void __init msm8x60_init(struct msm_board_data *board_data)
10094{
10095 uint32_t soc_platform_version;
10096
Abhijeet Dharmapurikar6d565fd2011-09-15 18:49:56 -070010097 pmic_reset_irq = PM8058_RESOUT_IRQ(PM8058_IRQ_BASE);
10098
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070010099 /*
10100 * Initialize RPM first as other drivers and devices may need
10101 * it for their initialization.
10102 */
10103#ifdef CONFIG_MSM_RPM
10104 BUG_ON(msm_rpm_init(&msm_rpm_data));
10105#endif
10106 BUG_ON(msm_rpmrs_levels_init(msm_rpmrs_levels,
10107 ARRAY_SIZE(msm_rpmrs_levels)));
10108 if (msm_xo_init())
10109 pr_err("Failed to initialize XO votes\n");
10110
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070010111 msm8x60_check_2d_hardware();
10112
10113 /* Change SPM handling of core 1 if PMM 8160 is present. */
10114 soc_platform_version = socinfo_get_platform_version();
10115 if (SOCINFO_VERSION_MAJOR(soc_platform_version) == 1 &&
10116 SOCINFO_VERSION_MINOR(soc_platform_version) >= 2) {
10117 struct msm_spm_platform_data *spm_data;
10118
10119 spm_data = &msm_spm_data_v1[1];
10120 spm_data->reg_init_values[MSM_SPM_REG_SAW_CFG] &= ~0x0F00UL;
10121 spm_data->reg_init_values[MSM_SPM_REG_SAW_CFG] |= 0x0100UL;
10122
10123 spm_data = &msm_spm_data[1];
10124 spm_data->reg_init_values[MSM_SPM_REG_SAW_CFG] &= ~0x0F00UL;
10125 spm_data->reg_init_values[MSM_SPM_REG_SAW_CFG] |= 0x0100UL;
10126 }
10127
10128 /*
10129 * Initialize SPM before acpuclock as the latter calls into SPM
10130 * driver to set ACPU voltages.
10131 */
10132 if (SOCINFO_VERSION_MAJOR(socinfo_get_version()) != 1)
10133 msm_spm_init(msm_spm_data, ARRAY_SIZE(msm_spm_data));
10134 else
10135 msm_spm_init(msm_spm_data_v1, ARRAY_SIZE(msm_spm_data_v1));
10136
10137 /*
10138 * Set regulators 8901_l4 and 8901_l6 to be always on in HPM for SURF
10139 * devices so that the RPM doesn't drop into a low power mode that an
10140 * un-reworked SURF cannot resume from.
10141 */
10142 if (machine_is_msm8x60_surf()) {
David Collins6f032ba2011-08-31 14:08:15 -070010143 int i;
10144
10145 for (i = 0; i < ARRAY_SIZE(rpm_regulator_init_data); i++)
10146 if (rpm_regulator_init_data[i].id
10147 == RPM_VREG_ID_PM8901_L4
10148 || rpm_regulator_init_data[i].id
10149 == RPM_VREG_ID_PM8901_L6)
10150 rpm_regulator_init_data[i]
10151 .init_data.constraints.always_on = 1;
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070010152 }
10153
10154 /*
10155 * Disable regulator info printing so that regulator registration
10156 * messages do not enter the kmsg log.
10157 */
10158 regulator_suppress_info_printing();
10159
10160 /* Initialize regulators needed for clock_init. */
10161 platform_add_devices(early_regulators, ARRAY_SIZE(early_regulators));
10162
Stephen Boydbb600ae2011-08-02 20:11:40 -070010163 msm_clock_init(&msm8x60_clock_init_data);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070010164
10165 /* Buses need to be initialized before early-device registration
10166 * to get the platform data for fabrics.
10167 */
10168 msm8x60_init_buses();
10169 platform_add_devices(early_devices, ARRAY_SIZE(early_devices));
10170 /* CPU frequency control is not supported on simulated targets. */
10171 if (!machine_is_msm8x60_rumi3() && !machine_is_msm8x60_sim())
Matt Wagantallec57f062011-08-16 23:54:46 -070010172 acpuclk_init(&acpuclk_8x60_soc_data);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070010173
Terence Hampsonb36a38c2011-09-19 19:10:40 -040010174 /*
10175 * Enable EBI2 only for boards which make use of it. Leave
10176 * it disabled for all others for additional power savings.
10177 */
10178 if (machine_is_msm8x60_surf() || machine_is_msm8x60_ffa() ||
10179 machine_is_msm8x60_rumi3() ||
10180 machine_is_msm8x60_sim() ||
10181 machine_is_msm8x60_fluid() ||
10182 machine_is_msm8x60_dragon())
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070010183 msm8x60_init_ebi2();
10184 msm8x60_init_tlmm();
10185 msm8x60_init_gpiomux(board_data->gpiomux_cfgs);
10186 msm8x60_init_uart12dm();
10187 msm8x60_init_mmc();
10188
10189#if defined(CONFIG_PMIC8058_OTHC) || defined(CONFIG_PMIC8058_OTHC_MODULE)
10190 msm8x60_init_pm8058_othc();
10191#endif
10192
10193 if (machine_is_msm8x60_fluid()) {
10194 pm8058_platform_data.sub_devices[PM8058_SUBDEV_KPD].
10195 platform_data = &fluid_keypad_data;
10196 pm8058_platform_data.sub_devices[PM8058_SUBDEV_KPD].pdata_size
10197 = sizeof(fluid_keypad_data);
Zhang Chang Ken683be172011-08-10 17:45:34 -040010198 } else if (machine_is_msm8x60_dragon()) {
10199 pm8058_platform_data.sub_devices[PM8058_SUBDEV_KPD].
10200 platform_data = &dragon_keypad_data;
10201 pm8058_platform_data.sub_devices[PM8058_SUBDEV_KPD].pdata_size
10202 = sizeof(dragon_keypad_data);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070010203 } else {
10204 pm8058_platform_data.sub_devices[PM8058_SUBDEV_KPD].
10205 platform_data = &ffa_keypad_data;
10206 pm8058_platform_data.sub_devices[PM8058_SUBDEV_KPD].pdata_size
10207 = sizeof(ffa_keypad_data);
10208
10209 }
10210
10211 /* Disable END_CALL simulation function of powerkey on fluid */
10212 if (machine_is_msm8x60_fluid()) {
10213 pwrkey_pdata.pwrkey_time_ms = 0;
10214 }
10215
Jilai Wang53d27a82011-07-13 14:32:58 -040010216 /* Specify reset pin for OV9726 */
10217 if (machine_is_msm8x60_dragon()) {
10218 msm_camera_sensor_ov9726_data.sensor_reset = 62;
10219 ov9726_sensor_8660_info.mount_angle = 270;
10220 }
10221
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070010222 if (machine_is_msm8x60_surf() || machine_is_msm8x60_ffa() ||
10223 machine_is_msm8x60_fluid() || machine_is_msm8x60_fusion() ||
Zhang Chang Ken6baadf02011-08-05 09:48:15 -040010224 machine_is_msm8x60_fusn_ffa() || machine_is_msm8x60_dragon()) {
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070010225 msm8x60_cfg_smsc911x();
10226 if (SOCINFO_VERSION_MAJOR(socinfo_get_version()) != 1)
10227 platform_add_devices(msm_footswitch_devices,
10228 msm_num_footswitch_devices);
10229 platform_add_devices(surf_devices,
10230 ARRAY_SIZE(surf_devices));
10231
10232#ifdef CONFIG_MSM_DSPS
10233 if (machine_is_msm8x60_fluid()) {
10234 platform_device_unregister(&msm_gsbi12_qup_i2c_device);
10235 msm8x60_init_dsps();
10236 }
10237#endif
10238
10239#ifdef CONFIG_USB_EHCI_MSM_72K
10240 /*
10241 * Drive MPP2 pin HIGH for PHY to generate ID interrupts on 8660
10242 * fluid
10243 */
10244 if (machine_is_msm8x60_fluid()) {
10245 pm8901_mpp_config_digital_out(1,
10246 PM8901_MPP_DIG_LEVEL_L5, 1);
10247 }
10248 msm_add_host(0, &msm_usb_host_pdata);
10249#endif
Lei Zhou338cab82011-08-19 13:38:17 -040010250
10251#ifdef CONFIG_SND_SOC_MSM8660_APQ
10252 if (machine_is_msm8x60_dragon())
10253 platform_add_devices(dragon_alsa_devices,
10254 ARRAY_SIZE(dragon_alsa_devices));
10255 else
10256#endif
10257 platform_add_devices(asoc_devices,
10258 ARRAY_SIZE(asoc_devices));
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070010259 } else {
10260 msm8x60_configure_smc91x();
10261 platform_add_devices(rumi_sim_devices,
10262 ARRAY_SIZE(rumi_sim_devices));
10263 }
10264#if defined(CONFIG_USB_PEHCI_HCD) || defined(CONFIG_USB_PEHCI_HCD_MODULE)
Zhang Chang Ken6baadf02011-08-05 09:48:15 -040010265 if (machine_is_msm8x60_surf() || machine_is_msm8x60_ffa() ||
10266 machine_is_msm8x60_dragon())
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070010267 msm8x60_cfg_isp1763();
10268#endif
10269#ifdef CONFIG_BATTERY_MSM8X60
10270 if (machine_is_msm8x60_surf() || machine_is_msm8x60_ffa() ||
Zhang Chang Ken6baadf02011-08-05 09:48:15 -040010271 machine_is_msm8x60_fusion() || machine_is_msm8x60_dragon() ||
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070010272 machine_is_msm8x60_fusn_ffa() || machine_is_msm8x60_fluid())
10273 platform_device_register(&msm_charger_device);
10274#endif
10275
10276 if (machine_is_msm8x60_fusion() || machine_is_msm8x60_fusn_ffa())
10277 platform_add_devices(charm_devices, ARRAY_SIZE(charm_devices));
10278
Terence Hampson90508a92011-08-09 10:40:08 -040010279 if (machine_is_msm8x60_dragon()) {
10280 pm8058_charger_sub_dev.platform_data
10281 = &pmic8058_charger_dragon;
10282 pm8058_charger_sub_dev.pdata_size
10283 = sizeof(pmic8058_charger_dragon);
10284 }
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070010285 if (!machine_is_msm8x60_fluid())
10286 pm8058_platform_data.charger_sub_device
10287 = &pm8058_charger_sub_dev;
10288
10289#if defined(CONFIG_SPI_QUP) || defined(CONFIG_SPI_QUP_MODULE)
10290 if (machine_is_msm8x60_fluid())
10291 platform_device_register(&msm_gsbi10_qup_spi_device);
10292 else
10293 platform_device_register(&msm_gsbi1_qup_spi_device);
10294#endif
10295
10296#if defined(CONFIG_TOUCHSCREEN_CYTTSP_I2C) || \
10297 defined(CONFIG_TOUCHSCREEN_CYTTSP_I2C_MODULE)
10298 if (machine_is_msm8x60_fluid())
10299 cyttsp_set_params();
10300#endif
10301 if (!machine_is_msm8x60_sim())
10302 msm_fb_add_devices();
10303 fixup_i2c_configs();
10304 register_i2c_devices();
10305
Terence Hampson1c73fef2011-07-19 17:10:49 -040010306 if (machine_is_msm8x60_dragon())
10307 smsc911x_config.reset_gpio
10308 = GPIO_ETHERNET_RESET_N_DRAGON;
10309
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070010310 platform_device_register(&smsc911x_device);
10311
10312#if (defined(CONFIG_SPI_QUP)) && \
10313 (defined(CONFIG_FB_MSM_LCDC_SAMSUNG_OLED_PT) || \
Zhang Chang Ken3a8b8512011-08-04 18:41:39 -040010314 defined(CONFIG_FB_MSM_LCDC_AUO_WVGA) || \
10315 defined(CONFIG_FB_MSM_LCDC_NT35582_WVGA))
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070010316
10317 if (machine_is_msm8x60_fluid()) {
10318#ifdef CONFIG_FB_MSM_LCDC_SAMSUNG_OLED_PT
10319 if (SOCINFO_VERSION_MAJOR(soc_platform_version) < 3) {
10320 spi_register_board_info(lcdc_samsung_spi_board_info,
10321 ARRAY_SIZE(lcdc_samsung_spi_board_info));
10322 } else
10323#endif
10324 {
10325#ifdef CONFIG_FB_MSM_LCDC_AUO_WVGA
10326 spi_register_board_info(lcdc_auo_spi_board_info,
10327 ARRAY_SIZE(lcdc_auo_spi_board_info));
10328#endif
10329 }
Zhang Chang Ken3a8b8512011-08-04 18:41:39 -040010330#ifdef CONFIG_FB_MSM_LCDC_NT35582_WVGA
10331 } else if (machine_is_msm8x60_dragon()) {
10332 spi_register_board_info(lcdc_nt35582_spi_board_info,
10333 ARRAY_SIZE(lcdc_nt35582_spi_board_info));
10334#endif
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070010335 }
10336#endif
10337
10338 msm_pm_set_platform_data(msm_pm_data, ARRAY_SIZE(msm_pm_data));
10339 msm_pm_set_rpm_wakeup_irq(RPM_SCSS_CPU0_WAKE_UP_IRQ);
10340 msm_cpuidle_set_states(msm_cstates, ARRAY_SIZE(msm_cstates),
10341 msm_pm_data);
10342
10343#ifdef CONFIG_SENSORS_MSM_ADC
10344 if (machine_is_msm8x60_fluid()) {
10345 msm_adc_pdata.dev_names = msm_adc_fluid_device_names;
10346 msm_adc_pdata.num_adc = ARRAY_SIZE(msm_adc_fluid_device_names);
10347 if (SOCINFO_VERSION_MAJOR(soc_platform_version) < 3)
10348 msm_adc_pdata.gpio_config = APROC_CONFIG;
10349 else
10350 msm_adc_pdata.gpio_config = MPROC_CONFIG;
10351 }
10352 msm_adc_pdata.target_hw = MSM_8x60;
10353#endif
10354#ifdef CONFIG_MSM8X60_AUDIO
10355 msm_snddev_init();
10356#endif
10357#if defined(CONFIG_GPIO_SX150X) || defined(CONFIG_GPIO_SX150X_MODULE)
10358 if (machine_is_msm8x60_fluid())
10359 platform_device_register(&fluid_leds_gpio);
10360 else
10361 platform_device_register(&gpio_leds);
10362#endif
10363
10364 /* configure pmic leds */
10365 if (machine_is_msm8x60_fluid()) {
10366 pm8058_platform_data.sub_devices[PM8058_SUBDEV_LED].
10367 platform_data = &pm8058_fluid_flash_leds_data;
10368 pm8058_platform_data.sub_devices[PM8058_SUBDEV_LED].pdata_size
10369 = sizeof(pm8058_fluid_flash_leds_data);
Terence Hampsonc0b6dfb2011-07-15 11:07:17 -040010370 } else if (machine_is_msm8x60_dragon()) {
10371 pm8058_platform_data.sub_devices[PM8058_SUBDEV_LED].
10372 platform_data = &pm8058_dragon_leds_data;
10373 pm8058_platform_data.sub_devices[PM8058_SUBDEV_LED].pdata_size
10374 = sizeof(pm8058_dragon_leds_data);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070010375 } else {
10376 pm8058_platform_data.sub_devices[PM8058_SUBDEV_LED].
10377 platform_data = &pm8058_flash_leds_data;
10378 pm8058_platform_data.sub_devices[PM8058_SUBDEV_LED].pdata_size
10379 = sizeof(pm8058_flash_leds_data);
10380 }
10381
Zhang Chang Ken6baadf02011-08-05 09:48:15 -040010382 if (machine_is_msm8x60_ffa() || machine_is_msm8x60_fusn_ffa() ||
10383 machine_is_msm8x60_dragon()) {
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070010384 pm8058_platform_data.sub_devices[PM8058_SUBDEV_VIB].
10385 platform_data = &pmic_vib_pdata;
10386 pm8058_platform_data.sub_devices[PM8058_SUBDEV_VIB].
10387 pdata_size = sizeof(pmic_vib_pdata);
10388 }
10389
10390 msm8x60_multi_sdio_init();
Laura Abbott5d2d1e62011-08-10 16:27:35 -070010391
10392 if (machine_is_msm8x60_fusion() || machine_is_msm8x60_fusn_ffa())
10393 msm_fusion_setup_pinctrl();
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070010394}
10395
10396static void __init msm8x60_rumi3_init(void)
10397{
10398 msm8x60_init(&msm8x60_rumi3_board_data);
10399}
10400
10401static void __init msm8x60_sim_init(void)
10402{
10403 msm8x60_init(&msm8x60_sim_board_data);
10404}
10405
10406static void __init msm8x60_surf_init(void)
10407{
10408 msm8x60_init(&msm8x60_surf_board_data);
10409}
10410
10411static void __init msm8x60_ffa_init(void)
10412{
10413 msm8x60_init(&msm8x60_ffa_board_data);
10414}
10415
10416static void __init msm8x60_fluid_init(void)
10417{
10418 msm8x60_init(&msm8x60_fluid_board_data);
10419}
10420
10421static void __init msm8x60_charm_surf_init(void)
10422{
10423 msm8x60_init(&msm8x60_charm_surf_board_data);
10424}
10425
10426static void __init msm8x60_charm_ffa_init(void)
10427{
10428 msm8x60_init(&msm8x60_charm_ffa_board_data);
10429}
10430
10431static void __init msm8x60_charm_init_early(void)
10432{
10433 msm8x60_allocate_memory_regions();
Steve Mucklea55df6e2010-01-07 12:43:24 -080010434}
10435
Zhang Chang Kenef05b172011-07-27 15:28:13 -040010436static void __init msm8x60_dragon_init(void)
10437{
10438 msm8x60_init(&msm8x60_dragon_board_data);
10439}
10440
Steve Mucklea55df6e2010-01-07 12:43:24 -080010441MACHINE_START(MSM8X60_RUMI3, "QCT MSM8X60 RUMI3")
10442 .map_io = msm8x60_map_io,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070010443 .reserve = msm8x60_reserve,
Steve Mucklea55df6e2010-01-07 12:43:24 -080010444 .init_irq = msm8x60_init_irq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070010445 .init_machine = msm8x60_rumi3_init,
Steve Mucklea55df6e2010-01-07 12:43:24 -080010446 .timer = &msm_timer,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070010447 .init_early = msm8x60_charm_init_early,
Steve Muckle49b76f72010-03-19 17:00:08 -070010448MACHINE_END
Steve Muckle57bbf1c2010-01-07 12:51:10 -080010449
10450MACHINE_START(MSM8X60_SIM, "QCT MSM8X60 SIMULATOR")
10451 .map_io = msm8x60_map_io,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070010452 .reserve = msm8x60_reserve,
Steve Muckle57bbf1c2010-01-07 12:51:10 -080010453 .init_irq = msm8x60_init_irq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070010454 .init_machine = msm8x60_sim_init,
Steve Muckle57bbf1c2010-01-07 12:51:10 -080010455 .timer = &msm_timer,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070010456 .init_early = msm8x60_charm_init_early,
10457MACHINE_END
10458
10459MACHINE_START(MSM8X60_SURF, "QCT MSM8X60 SURF")
10460 .map_io = msm8x60_map_io,
10461 .reserve = msm8x60_reserve,
10462 .init_irq = msm8x60_init_irq,
10463 .init_machine = msm8x60_surf_init,
10464 .timer = &msm_timer,
10465 .init_early = msm8x60_charm_init_early,
Steve Muckle57bbf1c2010-01-07 12:51:10 -080010466MACHINE_END
Gregory Bean69b7f6f2010-04-04 22:29:02 -070010467
10468MACHINE_START(MSM8X60_FFA, "QCT MSM8X60 FFA")
10469 .map_io = msm8x60_map_io,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070010470 .reserve = msm8x60_reserve,
Gregory Bean69b7f6f2010-04-04 22:29:02 -070010471 .init_irq = msm8x60_init_irq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070010472 .init_machine = msm8x60_ffa_init,
Gregory Bean69b7f6f2010-04-04 22:29:02 -070010473 .timer = &msm_timer,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070010474 .init_early = msm8x60_charm_init_early,
10475MACHINE_END
10476
10477MACHINE_START(MSM8X60_FLUID, "QCT MSM8X60 FLUID")
10478 .map_io = msm8x60_map_io,
10479 .reserve = msm8x60_reserve,
10480 .init_irq = msm8x60_init_irq,
10481 .init_machine = msm8x60_fluid_init,
10482 .timer = &msm_timer,
10483 .init_early = msm8x60_charm_init_early,
10484MACHINE_END
10485
10486MACHINE_START(MSM8X60_FUSION, "QCT MSM8X60 FUSION SURF")
10487 .map_io = msm8x60_map_io,
10488 .reserve = msm8x60_reserve,
10489 .init_irq = msm8x60_init_irq,
10490 .init_machine = msm8x60_charm_surf_init,
10491 .timer = &msm_timer,
10492 .init_early = msm8x60_charm_init_early,
10493MACHINE_END
10494
10495MACHINE_START(MSM8X60_FUSN_FFA, "QCT MSM8X60 FUSION FFA")
10496 .map_io = msm8x60_map_io,
10497 .reserve = msm8x60_reserve,
10498 .init_irq = msm8x60_init_irq,
10499 .init_machine = msm8x60_charm_ffa_init,
10500 .timer = &msm_timer,
10501 .init_early = msm8x60_charm_init_early,
Gregory Bean69b7f6f2010-04-04 22:29:02 -070010502MACHINE_END
Zhang Chang Kenef05b172011-07-27 15:28:13 -040010503
10504MACHINE_START(MSM8X60_DRAGON, "QCT MSM8X60 DRAGON")
10505 .map_io = msm8x60_map_io,
10506 .reserve = msm8x60_reserve,
10507 .init_irq = msm8x60_init_irq,
10508 .init_machine = msm8x60_dragon_init,
10509 .timer = &msm_timer,
10510 .init_early = msm8x60_charm_init_early,
10511MACHINE_END