blob: 066eaf9533fea76520eedf106ed90102e1582213 [file] [log] [blame]
Olof Johansson85940b42011-02-19 16:26:18 -08001/*
2 * Copyright (C) 2010,2011 Google, Inc.
3 *
4 * Author:
5 * Colin Cross <ccross@android.com>
6 * Erik Gilling <ccross@android.com>
7 *
8 * This software is licensed under the terms of the GNU General Public
9 * License version 2, as published by the Free Software Foundation, and
10 * may be copied, distributed, and modified under those terms.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 */
18
19
20#include <linux/resource.h>
21#include <linux/platform_device.h>
22#include <linux/dma-mapping.h>
23#include <linux/fsl_devices.h>
24#include <linux/serial_8250.h>
Colin Cross78702e42011-07-10 14:37:22 -070025#include <linux/i2c-tegra.h>
Olof Johansson85940b42011-02-19 16:26:18 -080026#include <asm/pmu.h>
27#include <mach/irqs.h>
28#include <mach/iomap.h>
29#include <mach/dma.h>
30
31static struct resource i2c_resource1[] = {
32 [0] = {
33 .start = INT_I2C,
34 .end = INT_I2C,
35 .flags = IORESOURCE_IRQ,
36 },
37 [1] = {
38 .start = TEGRA_I2C_BASE,
39 .end = TEGRA_I2C_BASE + TEGRA_I2C_SIZE-1,
40 .flags = IORESOURCE_MEM,
41 },
42};
43
44static struct resource i2c_resource2[] = {
45 [0] = {
46 .start = INT_I2C2,
47 .end = INT_I2C2,
48 .flags = IORESOURCE_IRQ,
49 },
50 [1] = {
51 .start = TEGRA_I2C2_BASE,
52 .end = TEGRA_I2C2_BASE + TEGRA_I2C2_SIZE-1,
53 .flags = IORESOURCE_MEM,
54 },
55};
56
57static struct resource i2c_resource3[] = {
58 [0] = {
59 .start = INT_I2C3,
60 .end = INT_I2C3,
61 .flags = IORESOURCE_IRQ,
62 },
63 [1] = {
64 .start = TEGRA_I2C3_BASE,
65 .end = TEGRA_I2C3_BASE + TEGRA_I2C3_SIZE-1,
66 .flags = IORESOURCE_MEM,
67 },
68};
69
70static struct resource i2c_resource4[] = {
71 [0] = {
72 .start = INT_DVC,
73 .end = INT_DVC,
74 .flags = IORESOURCE_IRQ,
75 },
76 [1] = {
77 .start = TEGRA_DVC_BASE,
78 .end = TEGRA_DVC_BASE + TEGRA_DVC_SIZE-1,
79 .flags = IORESOURCE_MEM,
80 },
81};
82
Colin Cross78702e42011-07-10 14:37:22 -070083static struct tegra_i2c_platform_data tegra_i2c1_platform_data = {
84 .bus_clk_rate = 400000,
85};
86
87static struct tegra_i2c_platform_data tegra_i2c2_platform_data = {
88 .bus_clk_rate = 400000,
89};
90
91static struct tegra_i2c_platform_data tegra_i2c3_platform_data = {
92 .bus_clk_rate = 400000,
93};
94
95static struct tegra_i2c_platform_data tegra_dvc_platform_data = {
96 .bus_clk_rate = 400000,
97};
98
Olof Johansson85940b42011-02-19 16:26:18 -080099struct platform_device tegra_i2c_device1 = {
100 .name = "tegra-i2c",
101 .id = 0,
102 .resource = i2c_resource1,
103 .num_resources = ARRAY_SIZE(i2c_resource1),
104 .dev = {
Colin Cross78702e42011-07-10 14:37:22 -0700105 .platform_data = &tegra_i2c1_platform_data,
Olof Johansson85940b42011-02-19 16:26:18 -0800106 },
107};
108
109struct platform_device tegra_i2c_device2 = {
110 .name = "tegra-i2c",
111 .id = 1,
112 .resource = i2c_resource2,
113 .num_resources = ARRAY_SIZE(i2c_resource2),
114 .dev = {
Colin Cross78702e42011-07-10 14:37:22 -0700115 .platform_data = &tegra_i2c2_platform_data,
Olof Johansson85940b42011-02-19 16:26:18 -0800116 },
117};
118
119struct platform_device tegra_i2c_device3 = {
120 .name = "tegra-i2c",
121 .id = 2,
122 .resource = i2c_resource3,
123 .num_resources = ARRAY_SIZE(i2c_resource3),
124 .dev = {
Colin Cross78702e42011-07-10 14:37:22 -0700125 .platform_data = &tegra_i2c3_platform_data,
Olof Johansson85940b42011-02-19 16:26:18 -0800126 },
127};
128
129struct platform_device tegra_i2c_device4 = {
130 .name = "tegra-i2c",
131 .id = 3,
132 .resource = i2c_resource4,
133 .num_resources = ARRAY_SIZE(i2c_resource4),
134 .dev = {
Colin Cross78702e42011-07-10 14:37:22 -0700135 .platform_data = &tegra_dvc_platform_data,
Olof Johansson85940b42011-02-19 16:26:18 -0800136 },
137};
138
139static struct resource spi_resource1[] = {
140 [0] = {
141 .start = INT_S_LINK1,
142 .end = INT_S_LINK1,
143 .flags = IORESOURCE_IRQ,
144 },
145 [1] = {
146 .start = TEGRA_SPI1_BASE,
147 .end = TEGRA_SPI1_BASE + TEGRA_SPI1_SIZE-1,
148 .flags = IORESOURCE_MEM,
149 },
150};
151
152static struct resource spi_resource2[] = {
153 [0] = {
154 .start = INT_SPI_2,
155 .end = INT_SPI_2,
156 .flags = IORESOURCE_IRQ,
157 },
158 [1] = {
159 .start = TEGRA_SPI2_BASE,
160 .end = TEGRA_SPI2_BASE + TEGRA_SPI2_SIZE-1,
161 .flags = IORESOURCE_MEM,
162 },
163};
164
165static struct resource spi_resource3[] = {
166 [0] = {
167 .start = INT_SPI_3,
168 .end = INT_SPI_3,
169 .flags = IORESOURCE_IRQ,
170 },
171 [1] = {
172 .start = TEGRA_SPI3_BASE,
173 .end = TEGRA_SPI3_BASE + TEGRA_SPI3_SIZE-1,
174 .flags = IORESOURCE_MEM,
175 },
176};
177
178static struct resource spi_resource4[] = {
179 [0] = {
180 .start = INT_SPI_4,
181 .end = INT_SPI_4,
182 .flags = IORESOURCE_IRQ,
183 },
184 [1] = {
185 .start = TEGRA_SPI4_BASE,
186 .end = TEGRA_SPI4_BASE + TEGRA_SPI4_SIZE-1,
187 .flags = IORESOURCE_MEM,
188 },
189};
190
191struct platform_device tegra_spi_device1 = {
192 .name = "spi_tegra",
193 .id = 0,
194 .resource = spi_resource1,
195 .num_resources = ARRAY_SIZE(spi_resource1),
196 .dev = {
197 .coherent_dma_mask = 0xffffffff,
198 },
199};
200
201struct platform_device tegra_spi_device2 = {
202 .name = "spi_tegra",
203 .id = 1,
204 .resource = spi_resource2,
205 .num_resources = ARRAY_SIZE(spi_resource2),
206 .dev = {
207 .coherent_dma_mask = 0xffffffff,
208 },
209};
210
211struct platform_device tegra_spi_device3 = {
212 .name = "spi_tegra",
213 .id = 2,
214 .resource = spi_resource3,
215 .num_resources = ARRAY_SIZE(spi_resource3),
216 .dev = {
217 .coherent_dma_mask = 0xffffffff,
218 },
219};
220
221struct platform_device tegra_spi_device4 = {
222 .name = "spi_tegra",
223 .id = 3,
224 .resource = spi_resource4,
225 .num_resources = ARRAY_SIZE(spi_resource4),
226 .dev = {
227 .coherent_dma_mask = 0xffffffff,
228 },
229};
230
231
232static struct resource sdhci_resource1[] = {
233 [0] = {
234 .start = INT_SDMMC1,
235 .end = INT_SDMMC1,
236 .flags = IORESOURCE_IRQ,
237 },
238 [1] = {
239 .start = TEGRA_SDMMC1_BASE,
240 .end = TEGRA_SDMMC1_BASE + TEGRA_SDMMC1_SIZE-1,
241 .flags = IORESOURCE_MEM,
242 },
243};
244
245static struct resource sdhci_resource2[] = {
246 [0] = {
247 .start = INT_SDMMC2,
248 .end = INT_SDMMC2,
249 .flags = IORESOURCE_IRQ,
250 },
251 [1] = {
252 .start = TEGRA_SDMMC2_BASE,
253 .end = TEGRA_SDMMC2_BASE + TEGRA_SDMMC2_SIZE-1,
254 .flags = IORESOURCE_MEM,
255 },
256};
257
258static struct resource sdhci_resource3[] = {
259 [0] = {
260 .start = INT_SDMMC3,
261 .end = INT_SDMMC3,
262 .flags = IORESOURCE_IRQ,
263 },
264 [1] = {
265 .start = TEGRA_SDMMC3_BASE,
266 .end = TEGRA_SDMMC3_BASE + TEGRA_SDMMC3_SIZE-1,
267 .flags = IORESOURCE_MEM,
268 },
269};
270
271static struct resource sdhci_resource4[] = {
272 [0] = {
273 .start = INT_SDMMC4,
274 .end = INT_SDMMC4,
275 .flags = IORESOURCE_IRQ,
276 },
277 [1] = {
278 .start = TEGRA_SDMMC4_BASE,
279 .end = TEGRA_SDMMC4_BASE + TEGRA_SDMMC4_SIZE-1,
280 .flags = IORESOURCE_MEM,
281 },
282};
283
284/* board files should fill in platform_data register the devices themselvs.
285 * See board-harmony.c for an example
286 */
287struct platform_device tegra_sdhci_device1 = {
288 .name = "sdhci-tegra",
289 .id = 0,
290 .resource = sdhci_resource1,
291 .num_resources = ARRAY_SIZE(sdhci_resource1),
292};
293
294struct platform_device tegra_sdhci_device2 = {
295 .name = "sdhci-tegra",
296 .id = 1,
297 .resource = sdhci_resource2,
298 .num_resources = ARRAY_SIZE(sdhci_resource2),
299};
300
301struct platform_device tegra_sdhci_device3 = {
302 .name = "sdhci-tegra",
303 .id = 2,
304 .resource = sdhci_resource3,
305 .num_resources = ARRAY_SIZE(sdhci_resource3),
306};
307
308struct platform_device tegra_sdhci_device4 = {
309 .name = "sdhci-tegra",
310 .id = 3,
311 .resource = sdhci_resource4,
312 .num_resources = ARRAY_SIZE(sdhci_resource4),
313};
314
315static struct resource tegra_usb1_resources[] = {
316 [0] = {
317 .start = TEGRA_USB_BASE,
318 .end = TEGRA_USB_BASE + TEGRA_USB_SIZE - 1,
319 .flags = IORESOURCE_MEM,
320 },
321 [1] = {
322 .start = INT_USB,
323 .end = INT_USB,
324 .flags = IORESOURCE_IRQ,
325 },
326};
327
328static struct resource tegra_usb2_resources[] = {
329 [0] = {
330 .start = TEGRA_USB2_BASE,
331 .end = TEGRA_USB2_BASE + TEGRA_USB2_SIZE - 1,
332 .flags = IORESOURCE_MEM,
333 },
334 [1] = {
335 .start = INT_USB2,
336 .end = INT_USB2,
337 .flags = IORESOURCE_IRQ,
338 },
339};
340
341static struct resource tegra_usb3_resources[] = {
342 [0] = {
343 .start = TEGRA_USB3_BASE,
344 .end = TEGRA_USB3_BASE + TEGRA_USB3_SIZE - 1,
345 .flags = IORESOURCE_MEM,
346 },
347 [1] = {
348 .start = INT_USB3,
349 .end = INT_USB3,
350 .flags = IORESOURCE_IRQ,
351 },
352};
353
354static u64 tegra_ehci_dmamask = DMA_BIT_MASK(32);
355
356struct platform_device tegra_ehci1_device = {
357 .name = "tegra-ehci",
358 .id = 0,
359 .dev = {
360 .dma_mask = &tegra_ehci_dmamask,
361 .coherent_dma_mask = DMA_BIT_MASK(32),
362 },
363 .resource = tegra_usb1_resources,
364 .num_resources = ARRAY_SIZE(tegra_usb1_resources),
365};
366
367struct platform_device tegra_ehci2_device = {
368 .name = "tegra-ehci",
369 .id = 1,
370 .dev = {
371 .dma_mask = &tegra_ehci_dmamask,
372 .coherent_dma_mask = DMA_BIT_MASK(32),
373 },
374 .resource = tegra_usb2_resources,
375 .num_resources = ARRAY_SIZE(tegra_usb2_resources),
376};
377
378struct platform_device tegra_ehci3_device = {
379 .name = "tegra-ehci",
380 .id = 2,
381 .dev = {
382 .dma_mask = &tegra_ehci_dmamask,
383 .coherent_dma_mask = DMA_BIT_MASK(32),
384 },
385 .resource = tegra_usb3_resources,
386 .num_resources = ARRAY_SIZE(tegra_usb3_resources),
387};
388
389static struct resource tegra_pmu_resources[] = {
390 [0] = {
391 .start = INT_CPU0_PMU_INTR,
392 .end = INT_CPU0_PMU_INTR,
393 .flags = IORESOURCE_IRQ,
394 },
395 [1] = {
396 .start = INT_CPU1_PMU_INTR,
397 .end = INT_CPU1_PMU_INTR,
398 .flags = IORESOURCE_IRQ,
399 },
400};
401
402struct platform_device tegra_pmu_device = {
403 .name = "arm-pmu",
404 .id = ARM_PMU_DEVICE_CPU,
405 .num_resources = ARRAY_SIZE(tegra_pmu_resources),
406 .resource = tegra_pmu_resources,
407};
408
409static struct resource tegra_uarta_resources[] = {
410 [0] = {
411 .start = TEGRA_UARTA_BASE,
412 .end = TEGRA_UARTA_BASE + TEGRA_UARTA_SIZE - 1,
413 .flags = IORESOURCE_MEM,
414 },
415 [1] = {
416 .start = INT_UARTA,
417 .end = INT_UARTA,
418 .flags = IORESOURCE_IRQ,
419 },
420};
421
422static struct resource tegra_uartb_resources[] = {
423 [0] = {
424 .start = TEGRA_UARTB_BASE,
425 .end = TEGRA_UARTB_BASE + TEGRA_UARTB_SIZE - 1,
426 .flags = IORESOURCE_MEM,
427 },
428 [1] = {
429 .start = INT_UARTB,
430 .end = INT_UARTB,
431 .flags = IORESOURCE_IRQ,
432 },
433};
434
435static struct resource tegra_uartc_resources[] = {
436 [0] = {
437 .start = TEGRA_UARTC_BASE,
438 .end = TEGRA_UARTC_BASE + TEGRA_UARTC_SIZE - 1,
439 .flags = IORESOURCE_MEM,
440 },
441 [1] = {
442 .start = INT_UARTC,
443 .end = INT_UARTC,
444 .flags = IORESOURCE_IRQ,
445 },
446};
447
448static struct resource tegra_uartd_resources[] = {
449 [0] = {
450 .start = TEGRA_UARTD_BASE,
451 .end = TEGRA_UARTD_BASE + TEGRA_UARTD_SIZE - 1,
452 .flags = IORESOURCE_MEM,
453 },
454 [1] = {
455 .start = INT_UARTD,
456 .end = INT_UARTD,
457 .flags = IORESOURCE_IRQ,
458 },
459};
460
461static struct resource tegra_uarte_resources[] = {
462 [0] = {
463 .start = TEGRA_UARTE_BASE,
464 .end = TEGRA_UARTE_BASE + TEGRA_UARTE_SIZE - 1,
465 .flags = IORESOURCE_MEM,
466 },
467 [1] = {
468 .start = INT_UARTE,
469 .end = INT_UARTE,
470 .flags = IORESOURCE_IRQ,
471 },
472};
473
474struct platform_device tegra_uarta_device = {
475 .name = "tegra_uart",
476 .id = 0,
477 .num_resources = ARRAY_SIZE(tegra_uarta_resources),
478 .resource = tegra_uarta_resources,
479 .dev = {
480 .coherent_dma_mask = DMA_BIT_MASK(32),
481 },
482};
483
484struct platform_device tegra_uartb_device = {
485 .name = "tegra_uart",
486 .id = 1,
487 .num_resources = ARRAY_SIZE(tegra_uartb_resources),
488 .resource = tegra_uartb_resources,
489 .dev = {
490 .coherent_dma_mask = DMA_BIT_MASK(32),
491 },
492};
493
494struct platform_device tegra_uartc_device = {
495 .name = "tegra_uart",
496 .id = 2,
497 .num_resources = ARRAY_SIZE(tegra_uartc_resources),
498 .resource = tegra_uartc_resources,
499 .dev = {
500 .coherent_dma_mask = DMA_BIT_MASK(32),
501 },
502};
503
504struct platform_device tegra_uartd_device = {
505 .name = "tegra_uart",
506 .id = 3,
507 .num_resources = ARRAY_SIZE(tegra_uartd_resources),
508 .resource = tegra_uartd_resources,
509 .dev = {
510 .coherent_dma_mask = DMA_BIT_MASK(32),
511 },
512};
513
514struct platform_device tegra_uarte_device = {
515 .name = "tegra_uart",
516 .id = 4,
517 .num_resources = ARRAY_SIZE(tegra_uarte_resources),
518 .resource = tegra_uarte_resources,
519 .dev = {
520 .coherent_dma_mask = DMA_BIT_MASK(32),
521 },
522};
Stephen Warrenb9652c22011-03-04 22:44:27 -0700523
524static struct resource i2s_resource1[] = {
525 [0] = {
526 .start = INT_I2S1,
527 .end = INT_I2S1,
528 .flags = IORESOURCE_IRQ
529 },
530 [1] = {
531 .start = TEGRA_DMA_REQ_SEL_I2S_1,
532 .end = TEGRA_DMA_REQ_SEL_I2S_1,
533 .flags = IORESOURCE_DMA
534 },
535 [2] = {
536 .start = TEGRA_I2S1_BASE,
537 .end = TEGRA_I2S1_BASE + TEGRA_I2S1_SIZE - 1,
538 .flags = IORESOURCE_MEM
539 }
540};
541
542static struct resource i2s_resource2[] = {
543 [0] = {
544 .start = INT_I2S2,
545 .end = INT_I2S2,
546 .flags = IORESOURCE_IRQ
547 },
548 [1] = {
549 .start = TEGRA_DMA_REQ_SEL_I2S2_1,
550 .end = TEGRA_DMA_REQ_SEL_I2S2_1,
551 .flags = IORESOURCE_DMA
552 },
553 [2] = {
554 .start = TEGRA_I2S2_BASE,
555 .end = TEGRA_I2S2_BASE + TEGRA_I2S2_SIZE - 1,
556 .flags = IORESOURCE_MEM
557 }
558};
559
560struct platform_device tegra_i2s_device1 = {
561 .name = "tegra-i2s",
562 .id = 0,
563 .resource = i2s_resource1,
564 .num_resources = ARRAY_SIZE(i2s_resource1),
565};
566
567struct platform_device tegra_i2s_device2 = {
568 .name = "tegra-i2s",
569 .id = 1,
570 .resource = i2s_resource2,
571 .num_resources = ARRAY_SIZE(i2s_resource2),
572};
573
574static struct resource tegra_das_resources[] = {
575 [0] = {
576 .start = TEGRA_APB_MISC_DAS_BASE,
577 .end = TEGRA_APB_MISC_DAS_BASE + TEGRA_APB_MISC_DAS_SIZE - 1,
578 .flags = IORESOURCE_MEM,
579 },
580};
581
582struct platform_device tegra_das_device = {
583 .name = "tegra-das",
584 .id = -1,
585 .num_resources = ARRAY_SIZE(tegra_das_resources),
586 .resource = tegra_das_resources,
587};
588
589struct platform_device tegra_pcm_device = {
590 .name = "tegra-pcm-audio",
591 .id = -1,
592};