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Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * ATI Frame Buffer Device Driver Core
3 *
4 * Copyright (C) 2004 Alex Kern <alex.kern@gmx.de>
5 * Copyright (C) 1997-2001 Geert Uytterhoeven
6 * Copyright (C) 1998 Bernd Harries
7 * Copyright (C) 1998 Eddie C. Dost (ecd@skynet.be)
8 *
9 * This driver supports the following ATI graphics chips:
10 * - ATI Mach64
11 *
12 * To do: add support for
13 * - ATI Rage128 (from aty128fb.c)
14 * - ATI Radeon (from radeonfb.c)
15 *
16 * This driver is partly based on the PowerMac console driver:
17 *
18 * Copyright (C) 1996 Paul Mackerras
19 *
20 * and on the PowerMac ATI/mach64 display driver:
21 *
22 * Copyright (C) 1997 Michael AK Tesch
23 *
24 * with work by Jon Howell
25 * Harry AC Eaton
26 * Anthony Tong <atong@uiuc.edu>
27 *
28 * Generic LCD support written by Daniel Mantione, ported from 2.4.20 by Alex Kern
29 * Many Thanks to Ville Syrjälä for patches and fixing nasting 16 bit color bug.
30 *
31 * This file is subject to the terms and conditions of the GNU General Public
32 * License. See the file COPYING in the main directory of this archive for
33 * more details.
34 *
35 * Many thanks to Nitya from ATI devrel for support and patience !
36 */
37
38/******************************************************************************
39
40 TODO:
41
42 - cursor support on all cards and all ramdacs.
43 - cursor parameters controlable via ioctl()s.
44 - guess PLL and MCLK based on the original PLL register values initialized
45 by Open Firmware (if they are initialized). BIOS is done
46
47 (Anyone with Mac to help with this?)
48
49******************************************************************************/
50
51
52#include <linux/config.h>
53#include <linux/module.h>
54#include <linux/moduleparam.h>
55#include <linux/kernel.h>
56#include <linux/errno.h>
57#include <linux/string.h>
58#include <linux/mm.h>
59#include <linux/slab.h>
60#include <linux/vmalloc.h>
61#include <linux/delay.h>
62#include <linux/console.h>
63#include <linux/fb.h>
64#include <linux/init.h>
65#include <linux/pci.h>
66#include <linux/interrupt.h>
67#include <linux/spinlock.h>
68#include <linux/wait.h>
Michael Hanselmann5474c122006-06-25 05:47:08 -070069#include <linux/backlight.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070070
71#include <asm/io.h>
72#include <asm/uaccess.h>
73
74#include <video/mach64.h>
75#include "atyfb.h"
76#include "ati_ids.h"
77
78#ifdef __powerpc__
Benjamin Herrenschmidte8222502006-03-28 23:15:54 +110079#include <asm/machdep.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070080#include <asm/prom.h>
81#include "../macmodes.h"
82#endif
83#ifdef __sparc__
84#include <asm/pbm.h>
85#include <asm/fbio.h>
86#endif
87
88#ifdef CONFIG_ADB_PMU
89#include <linux/adb.h>
90#include <linux/pmu.h>
91#endif
92#ifdef CONFIG_BOOTX_TEXT
93#include <asm/btext.h>
94#endif
95#ifdef CONFIG_PMAC_BACKLIGHT
96#include <asm/backlight.h>
97#endif
98#ifdef CONFIG_MTRR
99#include <asm/mtrr.h>
100#endif
101
102/*
103 * Debug flags.
104 */
105#undef DEBUG
106/*#define DEBUG*/
107
108/* Make sure n * PAGE_SIZE is protected at end of Aperture for GUI-regs */
109/* - must be large enough to catch all GUI-Regs */
110/* - must be aligned to a PAGE boundary */
111#define GUI_RESERVE (1 * PAGE_SIZE)
112
113/* FIXME: remove the FAIL definition */
Ville Syrjälä866d84c2006-01-09 20:53:22 -0800114#define FAIL(msg) do { \
115 if (!(var->activate & FB_ACTIVATE_TEST)) \
116 printk(KERN_CRIT "atyfb: " msg "\n"); \
117 return -EINVAL; \
118} while (0)
119#define FAIL_MAX(msg, x, _max_) do { \
120 if (x > _max_) { \
121 if (!(var->activate & FB_ACTIVATE_TEST)) \
122 printk(KERN_CRIT "atyfb: " msg " %x(%x)\n", x, _max_); \
123 return -EINVAL; \
124 } \
125} while (0)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700126#ifdef DEBUG
127#define DPRINTK(fmt, args...) printk(KERN_DEBUG "atyfb: " fmt, ## args)
128#else
129#define DPRINTK(fmt, args...)
130#endif
131
132#define PRINTKI(fmt, args...) printk(KERN_INFO "atyfb: " fmt, ## args)
133#define PRINTKE(fmt, args...) printk(KERN_ERR "atyfb: " fmt, ## args)
134
135#if defined(CONFIG_PM) || defined(CONFIG_PMAC_BACKLIGHT) || defined (CONFIG_FB_ATY_GENERIC_LCD)
136static const u32 lt_lcd_regs[] = {
137 CONFIG_PANEL_LG,
138 LCD_GEN_CNTL_LG,
139 DSTN_CONTROL_LG,
140 HFB_PITCH_ADDR_LG,
141 HORZ_STRETCHING_LG,
142 VERT_STRETCHING_LG,
143 0, /* EXT_VERT_STRETCH */
144 LT_GIO_LG,
145 POWER_MANAGEMENT_LG
146};
147
148void aty_st_lcd(int index, u32 val, const struct atyfb_par *par)
149{
150 if (M64_HAS(LT_LCD_REGS)) {
151 aty_st_le32(lt_lcd_regs[index], val, par);
152 } else {
153 unsigned long temp;
154
155 /* write addr byte */
156 temp = aty_ld_le32(LCD_INDEX, par);
157 aty_st_le32(LCD_INDEX, (temp & ~LCD_INDEX_MASK) | index, par);
158 /* write the register value */
159 aty_st_le32(LCD_DATA, val, par);
160 }
161}
162
163u32 aty_ld_lcd(int index, const struct atyfb_par *par)
164{
165 if (M64_HAS(LT_LCD_REGS)) {
166 return aty_ld_le32(lt_lcd_regs[index], par);
167 } else {
168 unsigned long temp;
169
170 /* write addr byte */
171 temp = aty_ld_le32(LCD_INDEX, par);
172 aty_st_le32(LCD_INDEX, (temp & ~LCD_INDEX_MASK) | index, par);
173 /* read the register value */
174 return aty_ld_le32(LCD_DATA, par);
175 }
176}
177#endif /* defined(CONFIG_PM) || defined(CONFIG_PMAC_BACKLIGHT) || defined (CONFIG_FB_ATY_GENERIC_LCD) */
178
179#ifdef CONFIG_FB_ATY_GENERIC_LCD
180/*
181 * ATIReduceRatio --
182 *
183 * Reduce a fraction by factoring out the largest common divider of the
184 * fraction's numerator and denominator.
185 */
186static void ATIReduceRatio(int *Numerator, int *Denominator)
187{
188 int Multiplier, Divider, Remainder;
189
190 Multiplier = *Numerator;
191 Divider = *Denominator;
192
193 while ((Remainder = Multiplier % Divider))
194 {
195 Multiplier = Divider;
196 Divider = Remainder;
197 }
198
199 *Numerator /= Divider;
200 *Denominator /= Divider;
201}
202#endif
203 /*
204 * The Hardware parameters for each card
205 */
206
207struct aty_cmap_regs {
208 u8 windex;
209 u8 lut;
210 u8 mask;
211 u8 rindex;
212 u8 cntl;
213};
214
215struct pci_mmap_map {
216 unsigned long voff;
217 unsigned long poff;
218 unsigned long size;
219 unsigned long prot_flag;
220 unsigned long prot_mask;
221};
222
223static struct fb_fix_screeninfo atyfb_fix __devinitdata = {
224 .id = "ATY Mach64",
225 .type = FB_TYPE_PACKED_PIXELS,
226 .visual = FB_VISUAL_PSEUDOCOLOR,
227 .xpanstep = 8,
228 .ypanstep = 1,
229};
230
231 /*
232 * Frame buffer device API
233 */
234
235static int atyfb_open(struct fb_info *info, int user);
236static int atyfb_release(struct fb_info *info, int user);
237static int atyfb_check_var(struct fb_var_screeninfo *var, struct fb_info *info);
238static int atyfb_set_par(struct fb_info *info);
239static int atyfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
240 u_int transp, struct fb_info *info);
241static int atyfb_pan_display(struct fb_var_screeninfo *var, struct fb_info *info);
242static int atyfb_blank(int blank, struct fb_info *info);
Christoph Hellwig67a66802006-01-14 13:21:25 -0800243static int atyfb_ioctl(struct fb_info *info, u_int cmd, u_long arg);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700244extern void atyfb_fillrect(struct fb_info *info, const struct fb_fillrect *rect);
245extern void atyfb_copyarea(struct fb_info *info, const struct fb_copyarea *area);
246extern void atyfb_imageblit(struct fb_info *info, const struct fb_image *image);
247#ifdef __sparc__
Christoph Hellwig216d5262006-01-14 13:21:25 -0800248static int atyfb_mmap(struct fb_info *info, struct vm_area_struct *vma);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700249#endif
250static int atyfb_sync(struct fb_info *info);
251
252 /*
253 * Internal routines
254 */
255
256static int aty_init(struct fb_info *info, const char *name);
257#ifdef CONFIG_ATARI
258static int store_video_par(char *videopar, unsigned char m64_num);
259#endif
260
261static struct crtc saved_crtc;
262static union aty_pll saved_pll;
263static void aty_get_crtc(const struct atyfb_par *par, struct crtc *crtc);
264
265static void aty_set_crtc(const struct atyfb_par *par, const struct crtc *crtc);
266static int aty_var_to_crtc(const struct fb_info *info, const struct fb_var_screeninfo *var, struct crtc *crtc);
267static int aty_crtc_to_var(const struct crtc *crtc, struct fb_var_screeninfo *var);
268static void set_off_pitch(struct atyfb_par *par, const struct fb_info *info);
269#ifdef CONFIG_PPC
270static int read_aty_sense(const struct atyfb_par *par);
271#endif
272
273
274 /*
275 * Interface used by the world
276 */
277
278static struct fb_var_screeninfo default_var = {
279 /* 640x480, 60 Hz, Non-Interlaced (25.175 MHz dotclock) */
280 640, 480, 640, 480, 0, 0, 8, 0,
281 {0, 8, 0}, {0, 8, 0}, {0, 8, 0}, {0, 0, 0},
282 0, 0, -1, -1, 0, 39722, 48, 16, 33, 10, 96, 2,
283 0, FB_VMODE_NONINTERLACED
284};
285
286static struct fb_videomode defmode = {
287 /* 640x480 @ 60 Hz, 31.5 kHz hsync */
288 NULL, 60, 640, 480, 39721, 40, 24, 32, 11, 96, 2,
289 0, FB_VMODE_NONINTERLACED
290};
291
292static struct fb_ops atyfb_ops = {
293 .owner = THIS_MODULE,
294 .fb_open = atyfb_open,
295 .fb_release = atyfb_release,
296 .fb_check_var = atyfb_check_var,
297 .fb_set_par = atyfb_set_par,
298 .fb_setcolreg = atyfb_setcolreg,
299 .fb_pan_display = atyfb_pan_display,
300 .fb_blank = atyfb_blank,
301 .fb_ioctl = atyfb_ioctl,
302 .fb_fillrect = atyfb_fillrect,
303 .fb_copyarea = atyfb_copyarea,
304 .fb_imageblit = atyfb_imageblit,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700305#ifdef __sparc__
306 .fb_mmap = atyfb_mmap,
307#endif
308 .fb_sync = atyfb_sync,
309};
310
311static int noaccel;
312#ifdef CONFIG_MTRR
313static int nomtrr;
314#endif
315static int vram;
316static int pll;
317static int mclk;
318static int xclk;
319static int comp_sync __initdata = -1;
320static char *mode;
321
322#ifdef CONFIG_PPC
323static int default_vmode __initdata = VMODE_CHOOSE;
324static int default_cmode __initdata = CMODE_CHOOSE;
325
326module_param_named(vmode, default_vmode, int, 0);
327MODULE_PARM_DESC(vmode, "int: video mode for mac");
328module_param_named(cmode, default_cmode, int, 0);
329MODULE_PARM_DESC(cmode, "int: color mode for mac");
330#endif
331
332#ifdef CONFIG_ATARI
333static unsigned int mach64_count __initdata = 0;
334static unsigned long phys_vmembase[FB_MAX] __initdata = { 0, };
335static unsigned long phys_size[FB_MAX] __initdata = { 0, };
336static unsigned long phys_guiregbase[FB_MAX] __initdata = { 0, };
337#endif
338
339/* top -> down is an evolution of mach64 chipset, any corrections? */
340#define ATI_CHIP_88800GX (M64F_GX)
341#define ATI_CHIP_88800CX (M64F_GX)
342
343#define ATI_CHIP_264CT (M64F_CT | M64F_INTEGRATED | M64F_CT_BUS | M64F_MAGIC_FIFO)
344#define ATI_CHIP_264ET (M64F_CT | M64F_INTEGRATED | M64F_CT_BUS | M64F_MAGIC_FIFO)
345
346#define ATI_CHIP_264VT (M64F_VT | M64F_INTEGRATED | M64F_VT_BUS | M64F_MAGIC_FIFO)
347#define ATI_CHIP_264GT (M64F_GT | M64F_INTEGRATED | M64F_MAGIC_FIFO | M64F_EXTRA_BRIGHT)
348
349#define ATI_CHIP_264VTB (M64F_VT | M64F_INTEGRATED | M64F_VT_BUS | M64F_GTB_DSP)
350#define ATI_CHIP_264VT3 (M64F_VT | M64F_INTEGRATED | M64F_VT_BUS | M64F_GTB_DSP | M64F_SDRAM_MAGIC_PLL)
351#define ATI_CHIP_264VT4 (M64F_VT | M64F_INTEGRATED | M64F_GTB_DSP)
352
Ville Syrjäläa14b2282006-01-09 20:53:32 -0800353/* FIXME what is this chip? */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700354#define ATI_CHIP_264LT (M64F_GT | M64F_INTEGRATED | M64F_GTB_DSP)
355
356/* make sets shorter */
357#define ATI_MODERN_SET (M64F_GT | M64F_INTEGRATED | M64F_GTB_DSP | M64F_EXTRA_BRIGHT)
358
359#define ATI_CHIP_264GTB (ATI_MODERN_SET | M64F_SDRAM_MAGIC_PLL)
360/*#define ATI_CHIP_264GTDVD ?*/
361#define ATI_CHIP_264LTG (ATI_MODERN_SET | M64F_SDRAM_MAGIC_PLL)
362
363#define ATI_CHIP_264GT2C (ATI_MODERN_SET | M64F_SDRAM_MAGIC_PLL | M64F_HW_TRIPLE)
364#define ATI_CHIP_264GTPRO (ATI_MODERN_SET | M64F_SDRAM_MAGIC_PLL | M64F_HW_TRIPLE | M64F_FIFO_32 | M64F_RESET_3D)
365#define ATI_CHIP_264LTPRO (ATI_MODERN_SET | M64F_HW_TRIPLE | M64F_FIFO_32 | M64F_RESET_3D)
366
367#define ATI_CHIP_264XL (ATI_MODERN_SET | M64F_HW_TRIPLE | M64F_FIFO_32 | M64F_RESET_3D | M64F_XL_DLL | M64F_MFB_FORCE_4)
368#define ATI_CHIP_MOBILITY (ATI_MODERN_SET | M64F_HW_TRIPLE | M64F_FIFO_32 | M64F_RESET_3D | M64F_XL_DLL | M64F_MFB_FORCE_4 | M64F_MOBIL_BUS)
369
370static struct {
371 u16 pci_id;
372 const char *name;
Ville Syrjälä25163c52006-01-09 20:53:27 -0800373 int pll, mclk, xclk, ecp_max;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700374 u32 features;
375} aty_chips[] __devinitdata = {
376#ifdef CONFIG_FB_ATY_GX
377 /* Mach64 GX */
Ville Syrjälä25163c52006-01-09 20:53:27 -0800378 { PCI_CHIP_MACH64GX, "ATI888GX00 (Mach64 GX)", 135, 50, 50, 0, ATI_CHIP_88800GX },
379 { PCI_CHIP_MACH64CX, "ATI888CX00 (Mach64 CX)", 135, 50, 50, 0, ATI_CHIP_88800CX },
Linus Torvalds1da177e2005-04-16 15:20:36 -0700380#endif /* CONFIG_FB_ATY_GX */
381
382#ifdef CONFIG_FB_ATY_CT
Ville Syrjälä25163c52006-01-09 20:53:27 -0800383 { PCI_CHIP_MACH64CT, "ATI264CT (Mach64 CT)", 135, 60, 60, 0, ATI_CHIP_264CT },
384 { PCI_CHIP_MACH64ET, "ATI264ET (Mach64 ET)", 135, 60, 60, 0, ATI_CHIP_264ET },
Ville Syrjälä0c23b672006-01-09 20:53:31 -0800385
Ville Syrjäläa14b2282006-01-09 20:53:32 -0800386 /* FIXME what is this chip? */
387 { PCI_CHIP_MACH64LT, "ATI264LT (Mach64 LT)", 135, 63, 63, 0, ATI_CHIP_264LT },
388
Ville Syrjälä0c23b672006-01-09 20:53:31 -0800389 { PCI_CHIP_MACH64VT, "ATI264VT (Mach64 VT)", 170, 67, 67, 80, ATI_CHIP_264VT },
Ville Syrjälä25163c52006-01-09 20:53:27 -0800390 { PCI_CHIP_MACH64GT, "3D RAGE (Mach64 GT)", 135, 63, 63, 80, ATI_CHIP_264GT },
Ville Syrjälä0c23b672006-01-09 20:53:31 -0800391
392 { PCI_CHIP_MACH64VU, "ATI264VT3 (Mach64 VU)", 200, 67, 67, 80, ATI_CHIP_264VT3 },
393 { PCI_CHIP_MACH64GU, "3D RAGE II+ (Mach64 GU)", 200, 67, 67, 100, ATI_CHIP_264GTB },
Linus Torvalds1da177e2005-04-16 15:20:36 -0700394
Ville Syrjäläa14b2282006-01-09 20:53:32 -0800395 { PCI_CHIP_MACH64LG, "3D RAGE LT (Mach64 LG)", 230, 63, 63, 100, ATI_CHIP_264LTG | M64F_LT_LCD_REGS | M64F_G3_PB_1024x768 },
Linus Torvalds1da177e2005-04-16 15:20:36 -0700396
Ville Syrjälä25163c52006-01-09 20:53:27 -0800397 { PCI_CHIP_MACH64VV, "ATI264VT4 (Mach64 VV)", 230, 83, 83, 100, ATI_CHIP_264VT4 },
Linus Torvalds1da177e2005-04-16 15:20:36 -0700398
Ville Syrjälä25163c52006-01-09 20:53:27 -0800399 { PCI_CHIP_MACH64GV, "3D RAGE IIC (Mach64 GV, PCI)", 230, 83, 83, 100, ATI_CHIP_264GT2C },
400 { PCI_CHIP_MACH64GW, "3D RAGE IIC (Mach64 GW, AGP)", 230, 83, 83, 100, ATI_CHIP_264GT2C },
401 { PCI_CHIP_MACH64GY, "3D RAGE IIC (Mach64 GY, PCI)", 230, 83, 83, 100, ATI_CHIP_264GT2C },
402 { PCI_CHIP_MACH64GZ, "3D RAGE IIC (Mach64 GZ, AGP)", 230, 83, 83, 100, ATI_CHIP_264GT2C },
Linus Torvalds1da177e2005-04-16 15:20:36 -0700403
Ville Syrjälä25163c52006-01-09 20:53:27 -0800404 { PCI_CHIP_MACH64GB, "3D RAGE PRO (Mach64 GB, BGA, AGP)", 230, 100, 100, 125, ATI_CHIP_264GTPRO },
405 { PCI_CHIP_MACH64GD, "3D RAGE PRO (Mach64 GD, BGA, AGP 1x)", 230, 100, 100, 125, ATI_CHIP_264GTPRO },
406 { PCI_CHIP_MACH64GI, "3D RAGE PRO (Mach64 GI, BGA, PCI)", 230, 100, 100, 125, ATI_CHIP_264GTPRO | M64F_MAGIC_VRAM_SIZE },
407 { PCI_CHIP_MACH64GP, "3D RAGE PRO (Mach64 GP, PQFP, PCI)", 230, 100, 100, 125, ATI_CHIP_264GTPRO },
408 { PCI_CHIP_MACH64GQ, "3D RAGE PRO (Mach64 GQ, PQFP, PCI, limited 3D)", 230, 100, 100, 125, ATI_CHIP_264GTPRO },
Linus Torvalds1da177e2005-04-16 15:20:36 -0700409
Ville Syrjälä25163c52006-01-09 20:53:27 -0800410 { PCI_CHIP_MACH64LB, "3D RAGE LT PRO (Mach64 LB, AGP)", 236, 75, 100, 135, ATI_CHIP_264LTPRO },
411 { PCI_CHIP_MACH64LD, "3D RAGE LT PRO (Mach64 LD, AGP)", 230, 100, 100, 135, ATI_CHIP_264LTPRO },
412 { PCI_CHIP_MACH64LI, "3D RAGE LT PRO (Mach64 LI, PCI)", 230, 100, 100, 135, ATI_CHIP_264LTPRO | M64F_G3_PB_1_1 | M64F_G3_PB_1024x768 },
413 { PCI_CHIP_MACH64LP, "3D RAGE LT PRO (Mach64 LP, PCI)", 230, 100, 100, 135, ATI_CHIP_264LTPRO },
414 { PCI_CHIP_MACH64LQ, "3D RAGE LT PRO (Mach64 LQ, PCI)", 230, 100, 100, 135, ATI_CHIP_264LTPRO },
Linus Torvalds1da177e2005-04-16 15:20:36 -0700415
Ville Syrjälä69b569f2006-01-09 20:53:30 -0800416 { PCI_CHIP_MACH64GM, "3D RAGE XL (Mach64 GM, AGP 2x)", 230, 83, 63, 135, ATI_CHIP_264XL },
417 { PCI_CHIP_MACH64GN, "3D RAGE XC (Mach64 GN, AGP 2x)", 230, 83, 63, 135, ATI_CHIP_264XL },
418 { PCI_CHIP_MACH64GO, "3D RAGE XL (Mach64 GO, PCI-66)", 230, 83, 63, 135, ATI_CHIP_264XL },
419 { PCI_CHIP_MACH64GL, "3D RAGE XC (Mach64 GL, PCI-66)", 230, 83, 63, 135, ATI_CHIP_264XL },
420 { PCI_CHIP_MACH64GR, "3D RAGE XL (Mach64 GR, PCI-33)", 230, 83, 63, 135, ATI_CHIP_264XL | M64F_SDRAM_MAGIC_PLL },
421 { PCI_CHIP_MACH64GS, "3D RAGE XC (Mach64 GS, PCI-33)", 230, 83, 63, 135, ATI_CHIP_264XL },
Linus Torvalds1da177e2005-04-16 15:20:36 -0700422
Ville Syrjälä25163c52006-01-09 20:53:27 -0800423 { PCI_CHIP_MACH64LM, "3D RAGE Mobility P/M (Mach64 LM, AGP 2x)", 230, 83, 125, 135, ATI_CHIP_MOBILITY },
424 { PCI_CHIP_MACH64LN, "3D RAGE Mobility L (Mach64 LN, AGP 2x)", 230, 83, 125, 135, ATI_CHIP_MOBILITY },
425 { PCI_CHIP_MACH64LR, "3D RAGE Mobility P/M (Mach64 LR, PCI)", 230, 83, 125, 135, ATI_CHIP_MOBILITY },
426 { PCI_CHIP_MACH64LS, "3D RAGE Mobility L (Mach64 LS, PCI)", 230, 83, 125, 135, ATI_CHIP_MOBILITY },
Linus Torvalds1da177e2005-04-16 15:20:36 -0700427#endif /* CONFIG_FB_ATY_CT */
428};
429
430/* can not fail */
431static int __devinit correct_chipset(struct atyfb_par *par)
432{
433 u8 rev;
434 u16 type;
435 u32 chip_id;
436 const char *name;
437 int i;
438
Tobias Klauserd1ae4182006-03-27 01:17:39 -0800439 for (i = ARRAY_SIZE(aty_chips) - 1; i >= 0; i--)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700440 if (par->pci_id == aty_chips[i].pci_id)
441 break;
442
443 name = aty_chips[i].name;
444 par->pll_limits.pll_max = aty_chips[i].pll;
445 par->pll_limits.mclk = aty_chips[i].mclk;
446 par->pll_limits.xclk = aty_chips[i].xclk;
Ville Syrjälä25163c52006-01-09 20:53:27 -0800447 par->pll_limits.ecp_max = aty_chips[i].ecp_max;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700448 par->features = aty_chips[i].features;
449
450 chip_id = aty_ld_le32(CONFIG_CHIP_ID, par);
451 type = chip_id & CFG_CHIP_TYPE;
452 rev = (chip_id & CFG_CHIP_REV) >> 24;
453
454 switch(par->pci_id) {
455#ifdef CONFIG_FB_ATY_GX
456 case PCI_CHIP_MACH64GX:
457 if(type != 0x00d7)
458 return -ENODEV;
459 break;
460 case PCI_CHIP_MACH64CX:
461 if(type != 0x0057)
462 return -ENODEV;
463 break;
464#endif
465#ifdef CONFIG_FB_ATY_CT
466 case PCI_CHIP_MACH64VT:
Ville Syrjälä0c23b672006-01-09 20:53:31 -0800467 switch (rev & 0x07) {
468 case 0x00:
469 switch (rev & 0xc0) {
470 case 0x00:
471 name = "ATI264VT (A3) (Mach64 VT)";
472 par->pll_limits.pll_max = 170;
473 par->pll_limits.mclk = 67;
474 par->pll_limits.xclk = 67;
475 par->pll_limits.ecp_max = 80;
476 par->features = ATI_CHIP_264VT;
477 break;
478 case 0x40:
479 name = "ATI264VT2 (A4) (Mach64 VT)";
480 par->pll_limits.pll_max = 200;
481 par->pll_limits.mclk = 67;
482 par->pll_limits.xclk = 67;
483 par->pll_limits.ecp_max = 80;
484 par->features = ATI_CHIP_264VT | M64F_MAGIC_POSTDIV;
485 break;
486 }
487 break;
488 case 0x01:
489 name = "ATI264VT3 (B1) (Mach64 VT)";
Linus Torvalds1da177e2005-04-16 15:20:36 -0700490 par->pll_limits.pll_max = 200;
491 par->pll_limits.mclk = 67;
492 par->pll_limits.xclk = 67;
Ville Syrjälä25163c52006-01-09 20:53:27 -0800493 par->pll_limits.ecp_max = 80;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700494 par->features = ATI_CHIP_264VTB;
Ville Syrjälä0c23b672006-01-09 20:53:31 -0800495 break;
496 case 0x02:
497 name = "ATI264VT3 (B2) (Mach64 VT)";
498 par->pll_limits.pll_max = 200;
499 par->pll_limits.mclk = 67;
500 par->pll_limits.xclk = 67;
501 par->pll_limits.ecp_max = 80;
502 par->features = ATI_CHIP_264VT3;
503 break;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700504 }
505 break;
506 case PCI_CHIP_MACH64GT:
Ville Syrjälä0c23b672006-01-09 20:53:31 -0800507 switch (rev & 0x07) {
508 case 0x01:
509 name = "3D RAGE II (Mach64 GT)";
Linus Torvalds1da177e2005-04-16 15:20:36 -0700510 par->pll_limits.pll_max = 170;
511 par->pll_limits.mclk = 67;
512 par->pll_limits.xclk = 67;
Ville Syrjälä25163c52006-01-09 20:53:27 -0800513 par->pll_limits.ecp_max = 80;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700514 par->features = ATI_CHIP_264GTB;
Ville Syrjälä0c23b672006-01-09 20:53:31 -0800515 break;
516 case 0x02:
517 name = "3D RAGE II+ (Mach64 GT)";
Linus Torvalds1da177e2005-04-16 15:20:36 -0700518 par->pll_limits.pll_max = 200;
519 par->pll_limits.mclk = 67;
520 par->pll_limits.xclk = 67;
Ville Syrjälä25163c52006-01-09 20:53:27 -0800521 par->pll_limits.ecp_max = 100;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700522 par->features = ATI_CHIP_264GTB;
Ville Syrjälä0c23b672006-01-09 20:53:31 -0800523 break;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700524 }
525 break;
526#endif
527 }
528
529 PRINTKI("%s [0x%04x rev 0x%02x]\n", name, type, rev);
530 return 0;
531}
532
533static char ram_dram[] __devinitdata = "DRAM";
534static char ram_resv[] __devinitdata = "RESV";
535#ifdef CONFIG_FB_ATY_GX
536static char ram_vram[] __devinitdata = "VRAM";
537#endif /* CONFIG_FB_ATY_GX */
538#ifdef CONFIG_FB_ATY_CT
539static char ram_edo[] __devinitdata = "EDO";
540static char ram_sdram[] __devinitdata = "SDRAM (1:1)";
541static char ram_sgram[] __devinitdata = "SGRAM (1:1)";
542static char ram_sdram32[] __devinitdata = "SDRAM (2:1) (32-bit)";
543static char ram_off[] __devinitdata = "OFF";
544#endif /* CONFIG_FB_ATY_CT */
545
546
547static u32 pseudo_palette[17];
548
549#ifdef CONFIG_FB_ATY_GX
550static char *aty_gx_ram[8] __devinitdata = {
551 ram_dram, ram_vram, ram_vram, ram_dram,
552 ram_dram, ram_vram, ram_vram, ram_resv
553};
554#endif /* CONFIG_FB_ATY_GX */
555
556#ifdef CONFIG_FB_ATY_CT
557static char *aty_ct_ram[8] __devinitdata = {
558 ram_off, ram_dram, ram_edo, ram_edo,
559 ram_sdram, ram_sgram, ram_sdram32, ram_resv
560};
561#endif /* CONFIG_FB_ATY_CT */
562
563static u32 atyfb_get_pixclock(struct fb_var_screeninfo *var, struct atyfb_par *par)
564{
565 u32 pixclock = var->pixclock;
566#ifdef CONFIG_FB_ATY_GENERIC_LCD
567 u32 lcd_on_off;
568 par->pll.ct.xres = 0;
569 if (par->lcd_table != 0) {
570 lcd_on_off = aty_ld_lcd(LCD_GEN_CNTL, par);
571 if(lcd_on_off & LCD_ON) {
572 par->pll.ct.xres = var->xres;
573 pixclock = par->lcd_pixclock;
574 }
575 }
576#endif
577 return pixclock;
578}
579
580#if defined(CONFIG_PPC)
581
582/*
583 * Apple monitor sense
584 */
585
586static int __init read_aty_sense(const struct atyfb_par *par)
587{
588 int sense, i;
589
590 aty_st_le32(GP_IO, 0x31003100, par); /* drive outputs high */
591 __delay(200);
592 aty_st_le32(GP_IO, 0, par); /* turn off outputs */
593 __delay(2000);
594 i = aty_ld_le32(GP_IO, par); /* get primary sense value */
595 sense = ((i & 0x3000) >> 3) | (i & 0x100);
596
597 /* drive each sense line low in turn and collect the other 2 */
598 aty_st_le32(GP_IO, 0x20000000, par); /* drive A low */
599 __delay(2000);
600 i = aty_ld_le32(GP_IO, par);
601 sense |= ((i & 0x1000) >> 7) | ((i & 0x100) >> 4);
602 aty_st_le32(GP_IO, 0x20002000, par); /* drive A high again */
603 __delay(200);
604
605 aty_st_le32(GP_IO, 0x10000000, par); /* drive B low */
606 __delay(2000);
607 i = aty_ld_le32(GP_IO, par);
608 sense |= ((i & 0x2000) >> 10) | ((i & 0x100) >> 6);
609 aty_st_le32(GP_IO, 0x10001000, par); /* drive B high again */
610 __delay(200);
611
612 aty_st_le32(GP_IO, 0x01000000, par); /* drive C low */
613 __delay(2000);
614 sense |= (aty_ld_le32(GP_IO, par) & 0x3000) >> 12;
615 aty_st_le32(GP_IO, 0, par); /* turn off outputs */
616 return sense;
617}
618
619#endif /* defined(CONFIG_PPC) */
620
621/* ------------------------------------------------------------------------- */
622
623/*
624 * CRTC programming
625 */
626
627static void aty_get_crtc(const struct atyfb_par *par, struct crtc *crtc)
628{
629#ifdef CONFIG_FB_ATY_GENERIC_LCD
630 if (par->lcd_table != 0) {
631 if(!M64_HAS(LT_LCD_REGS)) {
632 crtc->lcd_index = aty_ld_le32(LCD_INDEX, par);
633 aty_st_le32(LCD_INDEX, crtc->lcd_index, par);
634 }
635 crtc->lcd_config_panel = aty_ld_lcd(CONFIG_PANEL, par);
636 crtc->lcd_gen_cntl = aty_ld_lcd(LCD_GEN_CNTL, par);
637
638
639 /* switch to non shadow registers */
640 aty_st_lcd(LCD_GEN_CNTL, crtc->lcd_gen_cntl &
641 ~(CRTC_RW_SELECT | SHADOW_EN | SHADOW_RW_EN), par);
642
643 /* save stretching */
644 crtc->horz_stretching = aty_ld_lcd(HORZ_STRETCHING, par);
645 crtc->vert_stretching = aty_ld_lcd(VERT_STRETCHING, par);
646 if (!M64_HAS(LT_LCD_REGS))
647 crtc->ext_vert_stretch = aty_ld_lcd(EXT_VERT_STRETCH, par);
648 }
649#endif
650 crtc->h_tot_disp = aty_ld_le32(CRTC_H_TOTAL_DISP, par);
651 crtc->h_sync_strt_wid = aty_ld_le32(CRTC_H_SYNC_STRT_WID, par);
652 crtc->v_tot_disp = aty_ld_le32(CRTC_V_TOTAL_DISP, par);
653 crtc->v_sync_strt_wid = aty_ld_le32(CRTC_V_SYNC_STRT_WID, par);
654 crtc->vline_crnt_vline = aty_ld_le32(CRTC_VLINE_CRNT_VLINE, par);
655 crtc->off_pitch = aty_ld_le32(CRTC_OFF_PITCH, par);
656 crtc->gen_cntl = aty_ld_le32(CRTC_GEN_CNTL, par);
657
658#ifdef CONFIG_FB_ATY_GENERIC_LCD
659 if (par->lcd_table != 0) {
660 /* switch to shadow registers */
661 aty_st_lcd(LCD_GEN_CNTL, (crtc->lcd_gen_cntl & ~CRTC_RW_SELECT) |
662 SHADOW_EN | SHADOW_RW_EN, par);
663
664 crtc->shadow_h_tot_disp = aty_ld_le32(CRTC_H_TOTAL_DISP, par);
665 crtc->shadow_h_sync_strt_wid = aty_ld_le32(CRTC_H_SYNC_STRT_WID, par);
666 crtc->shadow_v_tot_disp = aty_ld_le32(CRTC_V_TOTAL_DISP, par);
667 crtc->shadow_v_sync_strt_wid = aty_ld_le32(CRTC_V_SYNC_STRT_WID, par);
668
669 aty_st_le32(LCD_GEN_CNTL, crtc->lcd_gen_cntl, par);
670 }
671#endif /* CONFIG_FB_ATY_GENERIC_LCD */
672}
673
674static void aty_set_crtc(const struct atyfb_par *par, const struct crtc *crtc)
675{
676#ifdef CONFIG_FB_ATY_GENERIC_LCD
677 if (par->lcd_table != 0) {
678 /* stop CRTC */
679 aty_st_le32(CRTC_GEN_CNTL, crtc->gen_cntl & ~(CRTC_EXT_DISP_EN | CRTC_EN), par);
680
681 /* update non-shadow registers first */
682 aty_st_lcd(CONFIG_PANEL, crtc->lcd_config_panel, par);
683 aty_st_lcd(LCD_GEN_CNTL, crtc->lcd_gen_cntl &
684 ~(CRTC_RW_SELECT | SHADOW_EN | SHADOW_RW_EN), par);
685
686 /* temporarily disable stretching */
687 aty_st_lcd(HORZ_STRETCHING,
688 crtc->horz_stretching &
689 ~(HORZ_STRETCH_MODE | HORZ_STRETCH_EN), par);
690 aty_st_lcd(VERT_STRETCHING,
691 crtc->vert_stretching &
692 ~(VERT_STRETCH_RATIO1 | VERT_STRETCH_RATIO2 |
693 VERT_STRETCH_USE0 | VERT_STRETCH_EN), par);
694 }
695#endif
696 /* turn off CRT */
697 aty_st_le32(CRTC_GEN_CNTL, crtc->gen_cntl & ~CRTC_EN, par);
698
699 DPRINTK("setting up CRTC\n");
700 DPRINTK("set primary CRT to %ix%i %c%c composite %c\n",
701 ((((crtc->h_tot_disp>>16) & 0xff) + 1)<<3), (((crtc->v_tot_disp>>16) & 0x7ff) + 1),
702 (crtc->h_sync_strt_wid & 0x200000)?'N':'P', (crtc->v_sync_strt_wid & 0x200000)?'N':'P',
703 (crtc->gen_cntl & CRTC_CSYNC_EN)?'P':'N');
704
705 DPRINTK("CRTC_H_TOTAL_DISP: %x\n",crtc->h_tot_disp);
706 DPRINTK("CRTC_H_SYNC_STRT_WID: %x\n",crtc->h_sync_strt_wid);
707 DPRINTK("CRTC_V_TOTAL_DISP: %x\n",crtc->v_tot_disp);
708 DPRINTK("CRTC_V_SYNC_STRT_WID: %x\n",crtc->v_sync_strt_wid);
709 DPRINTK("CRTC_OFF_PITCH: %x\n", crtc->off_pitch);
710 DPRINTK("CRTC_VLINE_CRNT_VLINE: %x\n", crtc->vline_crnt_vline);
711 DPRINTK("CRTC_GEN_CNTL: %x\n",crtc->gen_cntl);
712
713 aty_st_le32(CRTC_H_TOTAL_DISP, crtc->h_tot_disp, par);
714 aty_st_le32(CRTC_H_SYNC_STRT_WID, crtc->h_sync_strt_wid, par);
715 aty_st_le32(CRTC_V_TOTAL_DISP, crtc->v_tot_disp, par);
716 aty_st_le32(CRTC_V_SYNC_STRT_WID, crtc->v_sync_strt_wid, par);
717 aty_st_le32(CRTC_OFF_PITCH, crtc->off_pitch, par);
718 aty_st_le32(CRTC_VLINE_CRNT_VLINE, crtc->vline_crnt_vline, par);
719
720 aty_st_le32(CRTC_GEN_CNTL, crtc->gen_cntl, par);
721#if 0
722 FIXME
723 if (par->accel_flags & FB_ACCELF_TEXT)
724 aty_init_engine(par, info);
725#endif
726#ifdef CONFIG_FB_ATY_GENERIC_LCD
727 /* after setting the CRTC registers we should set the LCD registers. */
728 if (par->lcd_table != 0) {
729 /* switch to shadow registers */
730 aty_st_lcd(LCD_GEN_CNTL, (crtc->lcd_gen_cntl & ~CRTC_RW_SELECT) |
731 (SHADOW_EN | SHADOW_RW_EN), par);
732
Ville Syrjäläcd4617b2006-01-09 20:53:21 -0800733 DPRINTK("set shadow CRT to %ix%i %c%c\n",
Linus Torvalds1da177e2005-04-16 15:20:36 -0700734 ((((crtc->shadow_h_tot_disp>>16) & 0xff) + 1)<<3), (((crtc->shadow_v_tot_disp>>16) & 0x7ff) + 1),
735 (crtc->shadow_h_sync_strt_wid & 0x200000)?'N':'P', (crtc->shadow_v_sync_strt_wid & 0x200000)?'N':'P');
736
737 DPRINTK("SHADOW CRTC_H_TOTAL_DISP: %x\n", crtc->shadow_h_tot_disp);
738 DPRINTK("SHADOW CRTC_H_SYNC_STRT_WID: %x\n", crtc->shadow_h_sync_strt_wid);
739 DPRINTK("SHADOW CRTC_V_TOTAL_DISP: %x\n", crtc->shadow_v_tot_disp);
740 DPRINTK("SHADOW CRTC_V_SYNC_STRT_WID: %x\n", crtc->shadow_v_sync_strt_wid);
741
742 aty_st_le32(CRTC_H_TOTAL_DISP, crtc->shadow_h_tot_disp, par);
743 aty_st_le32(CRTC_H_SYNC_STRT_WID, crtc->shadow_h_sync_strt_wid, par);
744 aty_st_le32(CRTC_V_TOTAL_DISP, crtc->shadow_v_tot_disp, par);
745 aty_st_le32(CRTC_V_SYNC_STRT_WID, crtc->shadow_v_sync_strt_wid, par);
746
747 /* restore CRTC selection & shadow state and enable stretching */
748 DPRINTK("LCD_GEN_CNTL: %x\n", crtc->lcd_gen_cntl);
749 DPRINTK("HORZ_STRETCHING: %x\n", crtc->horz_stretching);
750 DPRINTK("VERT_STRETCHING: %x\n", crtc->vert_stretching);
751 if(!M64_HAS(LT_LCD_REGS))
752 DPRINTK("EXT_VERT_STRETCH: %x\n", crtc->ext_vert_stretch);
753
754 aty_st_lcd(LCD_GEN_CNTL, crtc->lcd_gen_cntl, par);
755 aty_st_lcd(HORZ_STRETCHING, crtc->horz_stretching, par);
756 aty_st_lcd(VERT_STRETCHING, crtc->vert_stretching, par);
757 if(!M64_HAS(LT_LCD_REGS)) {
758 aty_st_lcd(EXT_VERT_STRETCH, crtc->ext_vert_stretch, par);
759 aty_ld_le32(LCD_INDEX, par);
760 aty_st_le32(LCD_INDEX, crtc->lcd_index, par);
761 }
762 }
763#endif /* CONFIG_FB_ATY_GENERIC_LCD */
764}
765
766static int aty_var_to_crtc(const struct fb_info *info,
767 const struct fb_var_screeninfo *var, struct crtc *crtc)
768{
769 struct atyfb_par *par = (struct atyfb_par *) info->par;
770 u32 xres, yres, vxres, vyres, xoffset, yoffset, bpp;
771 u32 sync, vmode, vdisplay;
772 u32 h_total, h_disp, h_sync_strt, h_sync_end, h_sync_dly, h_sync_wid, h_sync_pol;
773 u32 v_total, v_disp, v_sync_strt, v_sync_end, v_sync_wid, v_sync_pol, c_sync;
774 u32 pix_width, dp_pix_width, dp_chain_mask;
775
776 /* input */
777 xres = var->xres;
778 yres = var->yres;
779 vxres = var->xres_virtual;
780 vyres = var->yres_virtual;
781 xoffset = var->xoffset;
782 yoffset = var->yoffset;
783 bpp = var->bits_per_pixel;
784 if (bpp == 16)
785 bpp = (var->green.length == 5) ? 15 : 16;
786 sync = var->sync;
787 vmode = var->vmode;
788
789 /* convert (and round up) and validate */
790 if (vxres < xres + xoffset)
791 vxres = xres + xoffset;
792 h_disp = xres;
793
794 if (vyres < yres + yoffset)
795 vyres = yres + yoffset;
796 v_disp = yres;
797
798 if (bpp <= 8) {
799 bpp = 8;
800 pix_width = CRTC_PIX_WIDTH_8BPP;
801 dp_pix_width =
802 HOST_8BPP | SRC_8BPP | DST_8BPP |
803 BYTE_ORDER_LSB_TO_MSB;
804 dp_chain_mask = DP_CHAIN_8BPP;
805 } else if (bpp <= 15) {
806 bpp = 16;
807 pix_width = CRTC_PIX_WIDTH_15BPP;
808 dp_pix_width = HOST_15BPP | SRC_15BPP | DST_15BPP |
809 BYTE_ORDER_LSB_TO_MSB;
810 dp_chain_mask = DP_CHAIN_15BPP;
811 } else if (bpp <= 16) {
812 bpp = 16;
813 pix_width = CRTC_PIX_WIDTH_16BPP;
814 dp_pix_width = HOST_16BPP | SRC_16BPP | DST_16BPP |
815 BYTE_ORDER_LSB_TO_MSB;
816 dp_chain_mask = DP_CHAIN_16BPP;
817 } else if (bpp <= 24 && M64_HAS(INTEGRATED)) {
818 bpp = 24;
819 pix_width = CRTC_PIX_WIDTH_24BPP;
820 dp_pix_width =
821 HOST_8BPP | SRC_8BPP | DST_8BPP |
822 BYTE_ORDER_LSB_TO_MSB;
823 dp_chain_mask = DP_CHAIN_24BPP;
824 } else if (bpp <= 32) {
825 bpp = 32;
826 pix_width = CRTC_PIX_WIDTH_32BPP;
827 dp_pix_width = HOST_32BPP | SRC_32BPP | DST_32BPP |
828 BYTE_ORDER_LSB_TO_MSB;
829 dp_chain_mask = DP_CHAIN_32BPP;
830 } else
831 FAIL("invalid bpp");
832
833 if (vxres * vyres * bpp / 8 > info->fix.smem_len)
834 FAIL("not enough video RAM");
835
836 h_sync_pol = sync & FB_SYNC_HOR_HIGH_ACT ? 0 : 1;
837 v_sync_pol = sync & FB_SYNC_VERT_HIGH_ACT ? 0 : 1;
838
839 if((xres > 1600) || (yres > 1200)) {
840 FAIL("MACH64 chips are designed for max 1600x1200\n"
841 "select anoter resolution.");
842 }
843 h_sync_strt = h_disp + var->right_margin;
844 h_sync_end = h_sync_strt + var->hsync_len;
845 h_sync_dly = var->right_margin & 7;
846 h_total = h_sync_end + h_sync_dly + var->left_margin;
847
848 v_sync_strt = v_disp + var->lower_margin;
849 v_sync_end = v_sync_strt + var->vsync_len;
850 v_total = v_sync_end + var->upper_margin;
851
852#ifdef CONFIG_FB_ATY_GENERIC_LCD
853 if (par->lcd_table != 0) {
854 if(!M64_HAS(LT_LCD_REGS)) {
855 u32 lcd_index = aty_ld_le32(LCD_INDEX, par);
856 crtc->lcd_index = lcd_index &
857 ~(LCD_INDEX_MASK | LCD_DISPLAY_DIS | LCD_SRC_SEL | CRTC2_DISPLAY_DIS);
858 aty_st_le32(LCD_INDEX, lcd_index, par);
859 }
860
861 if (!M64_HAS(MOBIL_BUS))
862 crtc->lcd_index |= CRTC2_DISPLAY_DIS;
863
864 crtc->lcd_config_panel = aty_ld_lcd(CONFIG_PANEL, par) | 0x4000;
865 crtc->lcd_gen_cntl = aty_ld_lcd(LCD_GEN_CNTL, par) & ~CRTC_RW_SELECT;
866
867 crtc->lcd_gen_cntl &=
868 ~(HORZ_DIVBY2_EN | DIS_HOR_CRT_DIVBY2 | TVCLK_PM_EN |
869 /*VCLK_DAC_PM_EN | USE_SHADOWED_VEND |*/
870 USE_SHADOWED_ROWCUR | SHADOW_EN | SHADOW_RW_EN);
871 crtc->lcd_gen_cntl |= DONT_SHADOW_VPAR | LOCK_8DOT;
872
873 if((crtc->lcd_gen_cntl & LCD_ON) &&
874 ((xres > par->lcd_width) || (yres > par->lcd_height))) {
875 /* We cannot display the mode on the LCD. If the CRT is enabled
876 we can turn off the LCD.
877 If the CRT is off, it isn't a good idea to switch it on; we don't
878 know if one is connected. So it's better to fail then.
879 */
880 if (crtc->lcd_gen_cntl & CRT_ON) {
Ville Syrjälä866d84c2006-01-09 20:53:22 -0800881 if (!(var->activate & FB_ACTIVATE_TEST))
882 PRINTKI("Disable LCD panel, because video mode does not fit.\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700883 crtc->lcd_gen_cntl &= ~LCD_ON;
884 /*aty_st_lcd(LCD_GEN_CNTL, crtc->lcd_gen_cntl, par);*/
885 } else {
Ville Syrjälä866d84c2006-01-09 20:53:22 -0800886 if (!(var->activate & FB_ACTIVATE_TEST))
887 PRINTKE("Video mode exceeds size of LCD panel.\nConnect this computer to a conventional monitor if you really need this mode.\n");
888 return -EINVAL;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700889 }
890 }
891 }
892
893 if ((par->lcd_table != 0) && (crtc->lcd_gen_cntl & LCD_ON)) {
894 int VScan = 1;
895 /* bpp -> bytespp, 1,4 -> 0; 8 -> 2; 15,16 -> 1; 24 -> 6; 32 -> 5
896 const u8 DFP_h_sync_dly_LT[] = { 0, 2, 1, 6, 5 };
897 const u8 ADD_to_strt_wid_and_dly_LT_DAC[] = { 0, 5, 6, 9, 9, 12, 12 }; */
898
899 vmode &= ~(FB_VMODE_DOUBLE | FB_VMODE_INTERLACED);
900
901 /* This is horror! When we simulate, say 640x480 on an 800x600
Ville Syrjäläcd4617b2006-01-09 20:53:21 -0800902 LCD monitor, the CRTC should be programmed 800x600 values for
Linus Torvalds1da177e2005-04-16 15:20:36 -0700903 the non visible part, but 640x480 for the visible part.
Ville Syrjäläcd4617b2006-01-09 20:53:21 -0800904 This code has been tested on a laptop with it's 1400x1050 LCD
Linus Torvalds1da177e2005-04-16 15:20:36 -0700905 monitor and a conventional monitor both switched on.
906 Tested modes: 1280x1024, 1152x864, 1024x768, 800x600,
907 works with little glitches also with DOUBLESCAN modes
908 */
909 if (yres < par->lcd_height) {
910 VScan = par->lcd_height / yres;
911 if(VScan > 1) {
912 VScan = 2;
913 vmode |= FB_VMODE_DOUBLE;
914 }
915 }
916
917 h_sync_strt = h_disp + par->lcd_right_margin;
918 h_sync_end = h_sync_strt + par->lcd_hsync_len;
919 h_sync_dly = /*DFP_h_sync_dly[ ( bpp + 1 ) / 3 ]; */par->lcd_hsync_dly;
920 h_total = h_disp + par->lcd_hblank_len;
921
922 v_sync_strt = v_disp + par->lcd_lower_margin / VScan;
923 v_sync_end = v_sync_strt + par->lcd_vsync_len / VScan;
924 v_total = v_disp + par->lcd_vblank_len / VScan;
925 }
926#endif /* CONFIG_FB_ATY_GENERIC_LCD */
927
928 h_disp = (h_disp >> 3) - 1;
929 h_sync_strt = (h_sync_strt >> 3) - 1;
930 h_sync_end = (h_sync_end >> 3) - 1;
931 h_total = (h_total >> 3) - 1;
932 h_sync_wid = h_sync_end - h_sync_strt;
933
934 FAIL_MAX("h_disp too large", h_disp, 0xff);
935 FAIL_MAX("h_sync_strt too large", h_sync_strt, 0x1ff);
936 /*FAIL_MAX("h_sync_wid too large", h_sync_wid, 0x1f);*/
937 if(h_sync_wid > 0x1f)
938 h_sync_wid = 0x1f;
939 FAIL_MAX("h_total too large", h_total, 0x1ff);
940
941 if (vmode & FB_VMODE_DOUBLE) {
942 v_disp <<= 1;
943 v_sync_strt <<= 1;
944 v_sync_end <<= 1;
945 v_total <<= 1;
946 }
947
948 vdisplay = yres;
949#ifdef CONFIG_FB_ATY_GENERIC_LCD
950 if ((par->lcd_table != 0) && (crtc->lcd_gen_cntl & LCD_ON))
951 vdisplay = par->lcd_height;
952#endif
953
Linus Torvalds1da177e2005-04-16 15:20:36 -0700954 v_disp--;
955 v_sync_strt--;
956 v_sync_end--;
957 v_total--;
958 v_sync_wid = v_sync_end - v_sync_strt;
959
960 FAIL_MAX("v_disp too large", v_disp, 0x7ff);
961 FAIL_MAX("v_sync_stsrt too large", v_sync_strt, 0x7ff);
962 /*FAIL_MAX("v_sync_wid too large", v_sync_wid, 0x1f);*/
963 if(v_sync_wid > 0x1f)
964 v_sync_wid = 0x1f;
965 FAIL_MAX("v_total too large", v_total, 0x7ff);
966
967 c_sync = sync & FB_SYNC_COMP_HIGH_ACT ? CRTC_CSYNC_EN : 0;
968
969 /* output */
970 crtc->vxres = vxres;
971 crtc->vyres = vyres;
972 crtc->xoffset = xoffset;
973 crtc->yoffset = yoffset;
974 crtc->bpp = bpp;
975 crtc->off_pitch = ((yoffset*vxres+xoffset)*bpp/64) | (vxres<<19);
976 crtc->vline_crnt_vline = 0;
977
978 crtc->h_tot_disp = h_total | (h_disp<<16);
979 crtc->h_sync_strt_wid = (h_sync_strt & 0xff) | (h_sync_dly<<8) |
980 ((h_sync_strt & 0x100)<<4) | (h_sync_wid<<16) | (h_sync_pol<<21);
981 crtc->v_tot_disp = v_total | (v_disp<<16);
982 crtc->v_sync_strt_wid = v_sync_strt | (v_sync_wid<<16) | (v_sync_pol<<21);
983
984 /* crtc->gen_cntl = aty_ld_le32(CRTC_GEN_CNTL, par) & CRTC_PRESERVED_MASK; */
985 crtc->gen_cntl = CRTC_EXT_DISP_EN | CRTC_EN | pix_width | c_sync;
986 crtc->gen_cntl |= CRTC_VGA_LINEAR;
987
988 /* Enable doublescan mode if requested */
989 if (vmode & FB_VMODE_DOUBLE)
990 crtc->gen_cntl |= CRTC_DBL_SCAN_EN;
991 /* Enable interlaced mode if requested */
992 if (vmode & FB_VMODE_INTERLACED)
993 crtc->gen_cntl |= CRTC_INTERLACE_EN;
994#ifdef CONFIG_FB_ATY_GENERIC_LCD
995 if (par->lcd_table != 0) {
996 vdisplay = yres;
997 if(vmode & FB_VMODE_DOUBLE)
998 vdisplay <<= 1;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700999 crtc->gen_cntl &= ~(CRTC2_EN | CRTC2_PIX_WIDTH);
1000 crtc->lcd_gen_cntl &= ~(HORZ_DIVBY2_EN | DIS_HOR_CRT_DIVBY2 |
1001 /*TVCLK_PM_EN | VCLK_DAC_PM_EN |*/
1002 USE_SHADOWED_VEND | USE_SHADOWED_ROWCUR | SHADOW_EN | SHADOW_RW_EN);
1003 crtc->lcd_gen_cntl |= (DONT_SHADOW_VPAR/* | LOCK_8DOT*/);
1004
1005 /* MOBILITY M1 tested, FIXME: LT */
1006 crtc->horz_stretching = aty_ld_lcd(HORZ_STRETCHING, par);
1007 if (!M64_HAS(LT_LCD_REGS))
1008 crtc->ext_vert_stretch = aty_ld_lcd(EXT_VERT_STRETCH, par) &
1009 ~(AUTO_VERT_RATIO | VERT_STRETCH_MODE | VERT_STRETCH_RATIO3);
1010
1011 crtc->horz_stretching &=
1012 ~(HORZ_STRETCH_RATIO | HORZ_STRETCH_LOOP | AUTO_HORZ_RATIO |
1013 HORZ_STRETCH_MODE | HORZ_STRETCH_EN);
Ville Syrjäläe98cef12006-01-09 20:53:26 -08001014 if (xres < par->lcd_width && crtc->lcd_gen_cntl & LCD_ON) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001015 do {
1016 /*
1017 * The horizontal blender misbehaves when HDisplay is less than a
1018 * a certain threshold (440 for a 1024-wide panel). It doesn't
1019 * stretch such modes enough. Use pixel replication instead of
1020 * blending to stretch modes that can be made to exactly fit the
1021 * panel width. The undocumented "NoLCDBlend" option allows the
1022 * pixel-replicated mode to be slightly wider or narrower than the
1023 * panel width. It also causes a mode that is exactly half as wide
1024 * as the panel to be pixel-replicated, rather than blended.
1025 */
1026 int HDisplay = xres & ~7;
1027 int nStretch = par->lcd_width / HDisplay;
1028 int Remainder = par->lcd_width % HDisplay;
1029
1030 if ((!Remainder && ((nStretch > 2))) ||
1031 (((HDisplay * 16) / par->lcd_width) < 7)) {
1032 static const char StretchLoops[] = {10, 12, 13, 15, 16};
1033 int horz_stretch_loop = -1, BestRemainder;
1034 int Numerator = HDisplay, Denominator = par->lcd_width;
1035 int Index = 5;
1036 ATIReduceRatio(&Numerator, &Denominator);
1037
1038 BestRemainder = (Numerator * 16) / Denominator;
1039 while (--Index >= 0) {
1040 Remainder = ((Denominator - Numerator) * StretchLoops[Index]) %
1041 Denominator;
1042 if (Remainder < BestRemainder) {
1043 horz_stretch_loop = Index;
1044 if (!(BestRemainder = Remainder))
1045 break;
1046 }
1047 }
1048
1049 if ((horz_stretch_loop >= 0) && !BestRemainder) {
1050 int horz_stretch_ratio = 0, Accumulator = 0;
1051 int reuse_previous = 1;
1052
1053 Index = StretchLoops[horz_stretch_loop];
1054
1055 while (--Index >= 0) {
1056 if (Accumulator > 0)
1057 horz_stretch_ratio |= reuse_previous;
1058 else
1059 Accumulator += Denominator;
1060 Accumulator -= Numerator;
1061 reuse_previous <<= 1;
1062 }
1063
1064 crtc->horz_stretching |= (HORZ_STRETCH_EN |
1065 ((horz_stretch_loop & HORZ_STRETCH_LOOP) << 16) |
1066 (horz_stretch_ratio & HORZ_STRETCH_RATIO));
1067 break; /* Out of the do { ... } while (0) */
1068 }
1069 }
1070
1071 crtc->horz_stretching |= (HORZ_STRETCH_MODE | HORZ_STRETCH_EN |
1072 (((HDisplay * (HORZ_STRETCH_BLEND + 1)) / par->lcd_width) & HORZ_STRETCH_BLEND));
1073 } while (0);
1074 }
1075
Ville Syrjäläe98cef12006-01-09 20:53:26 -08001076 if (vdisplay < par->lcd_height && crtc->lcd_gen_cntl & LCD_ON) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001077 crtc->vert_stretching = (VERT_STRETCH_USE0 | VERT_STRETCH_EN |
1078 (((vdisplay * (VERT_STRETCH_RATIO0 + 1)) / par->lcd_height) & VERT_STRETCH_RATIO0));
1079
1080 if (!M64_HAS(LT_LCD_REGS) &&
1081 xres <= (M64_HAS(MOBIL_BUS)?1024:800))
1082 crtc->ext_vert_stretch |= VERT_STRETCH_MODE;
1083 } else {
1084 /*
1085 * Don't use vertical blending if the mode is too wide or not
1086 * vertically stretched.
1087 */
1088 crtc->vert_stretching = 0;
1089 }
1090 /* copy to shadow crtc */
1091 crtc->shadow_h_tot_disp = crtc->h_tot_disp;
1092 crtc->shadow_h_sync_strt_wid = crtc->h_sync_strt_wid;
1093 crtc->shadow_v_tot_disp = crtc->v_tot_disp;
1094 crtc->shadow_v_sync_strt_wid = crtc->v_sync_strt_wid;
1095 }
1096#endif /* CONFIG_FB_ATY_GENERIC_LCD */
1097
1098 if (M64_HAS(MAGIC_FIFO)) {
Ville Syrjälä50c839c2006-01-09 20:53:23 -08001099 /* FIXME: display FIFO low watermark values */
1100 crtc->gen_cntl |= (aty_ld_le32(CRTC_GEN_CNTL, par) & CRTC_FIFO_LWM);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001101 }
1102 crtc->dp_pix_width = dp_pix_width;
1103 crtc->dp_chain_mask = dp_chain_mask;
1104
1105 return 0;
1106}
1107
1108static int aty_crtc_to_var(const struct crtc *crtc, struct fb_var_screeninfo *var)
1109{
1110 u32 xres, yres, bpp, left, right, upper, lower, hslen, vslen, sync;
1111 u32 h_total, h_disp, h_sync_strt, h_sync_dly, h_sync_wid,
1112 h_sync_pol;
1113 u32 v_total, v_disp, v_sync_strt, v_sync_wid, v_sync_pol, c_sync;
1114 u32 pix_width;
1115 u32 double_scan, interlace;
1116
1117 /* input */
1118 h_total = crtc->h_tot_disp & 0x1ff;
1119 h_disp = (crtc->h_tot_disp >> 16) & 0xff;
1120 h_sync_strt = (crtc->h_sync_strt_wid & 0xff) | ((crtc->h_sync_strt_wid >> 4) & 0x100);
1121 h_sync_dly = (crtc->h_sync_strt_wid >> 8) & 0x7;
1122 h_sync_wid = (crtc->h_sync_strt_wid >> 16) & 0x1f;
1123 h_sync_pol = (crtc->h_sync_strt_wid >> 21) & 0x1;
1124 v_total = crtc->v_tot_disp & 0x7ff;
1125 v_disp = (crtc->v_tot_disp >> 16) & 0x7ff;
1126 v_sync_strt = crtc->v_sync_strt_wid & 0x7ff;
1127 v_sync_wid = (crtc->v_sync_strt_wid >> 16) & 0x1f;
1128 v_sync_pol = (crtc->v_sync_strt_wid >> 21) & 0x1;
1129 c_sync = crtc->gen_cntl & CRTC_CSYNC_EN ? 1 : 0;
1130 pix_width = crtc->gen_cntl & CRTC_PIX_WIDTH_MASK;
1131 double_scan = crtc->gen_cntl & CRTC_DBL_SCAN_EN;
1132 interlace = crtc->gen_cntl & CRTC_INTERLACE_EN;
1133
1134 /* convert */
1135 xres = (h_disp + 1) * 8;
1136 yres = v_disp + 1;
1137 left = (h_total - h_sync_strt - h_sync_wid) * 8 - h_sync_dly;
1138 right = (h_sync_strt - h_disp) * 8 + h_sync_dly;
1139 hslen = h_sync_wid * 8;
1140 upper = v_total - v_sync_strt - v_sync_wid;
1141 lower = v_sync_strt - v_disp;
1142 vslen = v_sync_wid;
1143 sync = (h_sync_pol ? 0 : FB_SYNC_HOR_HIGH_ACT) |
1144 (v_sync_pol ? 0 : FB_SYNC_VERT_HIGH_ACT) |
1145 (c_sync ? FB_SYNC_COMP_HIGH_ACT : 0);
1146
1147 switch (pix_width) {
1148#if 0
1149 case CRTC_PIX_WIDTH_4BPP:
1150 bpp = 4;
1151 var->red.offset = 0;
1152 var->red.length = 8;
1153 var->green.offset = 0;
1154 var->green.length = 8;
1155 var->blue.offset = 0;
1156 var->blue.length = 8;
1157 var->transp.offset = 0;
1158 var->transp.length = 0;
1159 break;
1160#endif
1161 case CRTC_PIX_WIDTH_8BPP:
1162 bpp = 8;
1163 var->red.offset = 0;
1164 var->red.length = 8;
1165 var->green.offset = 0;
1166 var->green.length = 8;
1167 var->blue.offset = 0;
1168 var->blue.length = 8;
1169 var->transp.offset = 0;
1170 var->transp.length = 0;
1171 break;
1172 case CRTC_PIX_WIDTH_15BPP: /* RGB 555 */
1173 bpp = 16;
1174 var->red.offset = 10;
1175 var->red.length = 5;
1176 var->green.offset = 5;
1177 var->green.length = 5;
1178 var->blue.offset = 0;
1179 var->blue.length = 5;
1180 var->transp.offset = 0;
1181 var->transp.length = 0;
1182 break;
1183 case CRTC_PIX_WIDTH_16BPP: /* RGB 565 */
1184 bpp = 16;
1185 var->red.offset = 11;
1186 var->red.length = 5;
1187 var->green.offset = 5;
1188 var->green.length = 6;
1189 var->blue.offset = 0;
1190 var->blue.length = 5;
1191 var->transp.offset = 0;
1192 var->transp.length = 0;
1193 break;
1194 case CRTC_PIX_WIDTH_24BPP: /* RGB 888 */
1195 bpp = 24;
1196 var->red.offset = 16;
1197 var->red.length = 8;
1198 var->green.offset = 8;
1199 var->green.length = 8;
1200 var->blue.offset = 0;
1201 var->blue.length = 8;
1202 var->transp.offset = 0;
1203 var->transp.length = 0;
1204 break;
1205 case CRTC_PIX_WIDTH_32BPP: /* ARGB 8888 */
1206 bpp = 32;
1207 var->red.offset = 16;
1208 var->red.length = 8;
1209 var->green.offset = 8;
1210 var->green.length = 8;
1211 var->blue.offset = 0;
1212 var->blue.length = 8;
1213 var->transp.offset = 24;
1214 var->transp.length = 8;
1215 break;
1216 default:
Ville Syrjälä866d84c2006-01-09 20:53:22 -08001217 PRINTKE("Invalid pixel width\n");
1218 return -EINVAL;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001219 }
1220
1221 /* output */
1222 var->xres = xres;
1223 var->yres = yres;
1224 var->xres_virtual = crtc->vxres;
1225 var->yres_virtual = crtc->vyres;
1226 var->bits_per_pixel = bpp;
1227 var->left_margin = left;
1228 var->right_margin = right;
1229 var->upper_margin = upper;
1230 var->lower_margin = lower;
1231 var->hsync_len = hslen;
1232 var->vsync_len = vslen;
1233 var->sync = sync;
1234 var->vmode = FB_VMODE_NONINTERLACED;
1235 /* In double scan mode, the vertical parameters are doubled, so we need to
1236 half them to get the right values.
1237 In interlaced mode the values are already correct, so no correction is
1238 necessary.
1239 */
1240 if (interlace)
1241 var->vmode = FB_VMODE_INTERLACED;
1242
1243 if (double_scan) {
1244 var->vmode = FB_VMODE_DOUBLE;
1245 var->yres>>=1;
1246 var->upper_margin>>=1;
1247 var->lower_margin>>=1;
1248 var->vsync_len>>=1;
1249 }
1250
1251 return 0;
1252}
1253
1254/* ------------------------------------------------------------------------- */
1255
1256static int atyfb_set_par(struct fb_info *info)
1257{
1258 struct atyfb_par *par = (struct atyfb_par *) info->par;
1259 struct fb_var_screeninfo *var = &info->var;
1260 u32 tmp, pixclock;
1261 int err;
1262#ifdef DEBUG
1263 struct fb_var_screeninfo debug;
1264 u32 pixclock_in_ps;
1265#endif
1266 if (par->asleep)
1267 return 0;
1268
1269 if ((err = aty_var_to_crtc(info, var, &par->crtc)))
1270 return err;
1271
1272 pixclock = atyfb_get_pixclock(var, par);
1273
1274 if (pixclock == 0) {
Ville Syrjälä866d84c2006-01-09 20:53:22 -08001275 PRINTKE("Invalid pixclock\n");
1276 return -EINVAL;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001277 } else {
1278 if((err = par->pll_ops->var_to_pll(info, pixclock, var->bits_per_pixel, &par->pll)))
1279 return err;
1280 }
1281
1282 par->accel_flags = var->accel_flags; /* hack */
1283
Antonino A. Daplas7914cb22006-06-26 00:26:32 -07001284 if (var->accel_flags) {
1285 info->fbops->fb_sync = atyfb_sync;
1286 info->flags &= ~FBINFO_HWACCEL_DISABLED;
1287 } else {
1288 info->fbops->fb_sync = NULL;
1289 info->flags |= FBINFO_HWACCEL_DISABLED;
1290 }
1291
Linus Torvalds1da177e2005-04-16 15:20:36 -07001292 if (par->blitter_may_be_busy)
1293 wait_for_idle(par);
1294
1295 aty_set_crtc(par, &par->crtc);
1296 par->dac_ops->set_dac(info, &par->pll, var->bits_per_pixel, par->accel_flags);
1297 par->pll_ops->set_pll(info, &par->pll);
1298
1299#ifdef DEBUG
1300 if(par->pll_ops && par->pll_ops->pll_to_var)
1301 pixclock_in_ps = par->pll_ops->pll_to_var(info, &(par->pll));
1302 else
1303 pixclock_in_ps = 0;
1304
1305 if(0 == pixclock_in_ps) {
1306 PRINTKE("ALERT ops->pll_to_var get 0\n");
1307 pixclock_in_ps = pixclock;
1308 }
1309
1310 memset(&debug, 0, sizeof(debug));
1311 if(!aty_crtc_to_var(&(par->crtc), &debug)) {
1312 u32 hSync, vRefresh;
1313 u32 h_disp, h_sync_strt, h_sync_end, h_total;
1314 u32 v_disp, v_sync_strt, v_sync_end, v_total;
1315
1316 h_disp = debug.xres;
1317 h_sync_strt = h_disp + debug.right_margin;
1318 h_sync_end = h_sync_strt + debug.hsync_len;
1319 h_total = h_sync_end + debug.left_margin;
1320 v_disp = debug.yres;
1321 v_sync_strt = v_disp + debug.lower_margin;
1322 v_sync_end = v_sync_strt + debug.vsync_len;
1323 v_total = v_sync_end + debug.upper_margin;
1324
1325 hSync = 1000000000 / (pixclock_in_ps * h_total);
1326 vRefresh = (hSync * 1000) / v_total;
1327 if (par->crtc.gen_cntl & CRTC_INTERLACE_EN)
1328 vRefresh *= 2;
1329 if (par->crtc.gen_cntl & CRTC_DBL_SCAN_EN)
1330 vRefresh /= 2;
1331
1332 DPRINTK("atyfb_set_par\n");
1333 DPRINTK(" Set Visible Mode to %ix%i-%i\n", var->xres, var->yres, var->bits_per_pixel);
1334 DPRINTK(" Virtual resolution %ix%i, pixclock_in_ps %i (calculated %i)\n",
1335 var->xres_virtual, var->yres_virtual, pixclock, pixclock_in_ps);
1336 DPRINTK(" Dot clock: %i MHz\n", 1000000 / pixclock_in_ps);
1337 DPRINTK(" Horizontal sync: %i kHz\n", hSync);
1338 DPRINTK(" Vertical refresh: %i Hz\n", vRefresh);
1339 DPRINTK(" x style: %i.%03i %i %i %i %i %i %i %i %i\n",
1340 1000000 / pixclock_in_ps, 1000000 % pixclock_in_ps,
1341 h_disp, h_sync_strt, h_sync_end, h_total,
1342 v_disp, v_sync_strt, v_sync_end, v_total);
1343 DPRINTK(" fb style: %i %i %i %i %i %i %i %i %i\n",
1344 pixclock_in_ps,
1345 debug.left_margin, h_disp, debug.right_margin, debug.hsync_len,
1346 debug.upper_margin, v_disp, debug.lower_margin, debug.vsync_len);
1347 }
1348#endif /* DEBUG */
1349
1350 if (!M64_HAS(INTEGRATED)) {
1351 /* Don't forget MEM_CNTL */
1352 tmp = aty_ld_le32(MEM_CNTL, par) & 0xf0ffffff;
1353 switch (var->bits_per_pixel) {
1354 case 8:
1355 tmp |= 0x02000000;
1356 break;
1357 case 16:
1358 tmp |= 0x03000000;
1359 break;
1360 case 32:
1361 tmp |= 0x06000000;
1362 break;
1363 }
1364 aty_st_le32(MEM_CNTL, tmp, par);
1365 } else {
1366 tmp = aty_ld_le32(MEM_CNTL, par) & 0xf00fffff;
1367 if (!M64_HAS(MAGIC_POSTDIV))
1368 tmp |= par->mem_refresh_rate << 20;
1369 switch (var->bits_per_pixel) {
1370 case 8:
1371 case 24:
1372 tmp |= 0x00000000;
1373 break;
1374 case 16:
1375 tmp |= 0x04000000;
1376 break;
1377 case 32:
1378 tmp |= 0x08000000;
1379 break;
1380 }
1381 if (M64_HAS(CT_BUS)) {
1382 aty_st_le32(DAC_CNTL, 0x87010184, par);
1383 aty_st_le32(BUS_CNTL, 0x680000f9, par);
1384 } else if (M64_HAS(VT_BUS)) {
1385 aty_st_le32(DAC_CNTL, 0x87010184, par);
1386 aty_st_le32(BUS_CNTL, 0x680000f9, par);
1387 } else if (M64_HAS(MOBIL_BUS)) {
1388 aty_st_le32(DAC_CNTL, 0x80010102, par);
1389 aty_st_le32(BUS_CNTL, 0x7b33a040 | (par->aux_start ? BUS_APER_REG_DIS : 0), par);
1390 } else {
1391 /* GT */
1392 aty_st_le32(DAC_CNTL, 0x86010102, par);
1393 aty_st_le32(BUS_CNTL, 0x7b23a040 | (par->aux_start ? BUS_APER_REG_DIS : 0), par);
1394 aty_st_le32(EXT_MEM_CNTL, aty_ld_le32(EXT_MEM_CNTL, par) | 0x5000001, par);
1395 }
1396 aty_st_le32(MEM_CNTL, tmp, par);
1397 }
1398 aty_st_8(DAC_MASK, 0xff, par);
1399
1400 info->fix.line_length = var->xres_virtual * var->bits_per_pixel/8;
1401 info->fix.visual = var->bits_per_pixel <= 8 ?
1402 FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_DIRECTCOLOR;
1403
1404 /* Initialize the graphics engine */
1405 if (par->accel_flags & FB_ACCELF_TEXT)
1406 aty_init_engine(par, info);
1407
1408#ifdef CONFIG_BOOTX_TEXT
1409 btext_update_display(info->fix.smem_start,
1410 (((par->crtc.h_tot_disp >> 16) & 0xff) + 1) * 8,
1411 ((par->crtc.v_tot_disp >> 16) & 0x7ff) + 1,
1412 var->bits_per_pixel,
1413 par->crtc.vxres * var->bits_per_pixel / 8);
1414#endif /* CONFIG_BOOTX_TEXT */
1415#if 0
1416 /* switch to accelerator mode */
1417 if (!(par->crtc.gen_cntl & CRTC_EXT_DISP_EN))
1418 aty_st_le32(CRTC_GEN_CNTL, par->crtc.gen_cntl | CRTC_EXT_DISP_EN, par);
1419#endif
1420#ifdef DEBUG
1421{
1422 /* dump non shadow CRTC, pll, LCD registers */
1423 int i; u32 base;
1424
1425 /* CRTC registers */
1426 base = 0x2000;
1427 printk("debug atyfb: Mach64 non-shadow register values:");
1428 for (i = 0; i < 256; i = i+4) {
1429 if(i%16 == 0) printk("\ndebug atyfb: 0x%04X: ", base + i);
1430 printk(" %08X", aty_ld_le32(i, par));
1431 }
1432 printk("\n\n");
1433
1434#ifdef CONFIG_FB_ATY_CT
1435 /* PLL registers */
1436 base = 0x00;
1437 printk("debug atyfb: Mach64 PLL register values:");
1438 for (i = 0; i < 64; i++) {
1439 if(i%16 == 0) printk("\ndebug atyfb: 0x%02X: ", base + i);
1440 if(i%4 == 0) printk(" ");
1441 printk("%02X", aty_ld_pll_ct(i, par));
1442 }
1443 printk("\n\n");
1444#endif /* CONFIG_FB_ATY_CT */
1445
1446#ifdef CONFIG_FB_ATY_GENERIC_LCD
1447 if (par->lcd_table != 0) {
1448 /* LCD registers */
1449 base = 0x00;
1450 printk("debug atyfb: LCD register values:");
1451 if(M64_HAS(LT_LCD_REGS)) {
1452 for(i = 0; i <= POWER_MANAGEMENT; i++) {
1453 if(i == EXT_VERT_STRETCH)
1454 continue;
1455 printk("\ndebug atyfb: 0x%04X: ", lt_lcd_regs[i]);
1456 printk(" %08X", aty_ld_lcd(i, par));
1457 }
1458
1459 } else {
1460 for (i = 0; i < 64; i++) {
1461 if(i%4 == 0) printk("\ndebug atyfb: 0x%02X: ", base + i);
1462 printk(" %08X", aty_ld_lcd(i, par));
1463 }
1464 }
1465 printk("\n\n");
1466 }
1467#endif /* CONFIG_FB_ATY_GENERIC_LCD */
1468}
1469#endif /* DEBUG */
1470 return 0;
1471}
1472
1473static int atyfb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
1474{
1475 struct atyfb_par *par = (struct atyfb_par *) info->par;
1476 int err;
1477 struct crtc crtc;
1478 union aty_pll pll;
1479 u32 pixclock;
1480
1481 memcpy(&pll, &(par->pll), sizeof(pll));
1482
1483 if((err = aty_var_to_crtc(info, var, &crtc)))
1484 return err;
1485
1486 pixclock = atyfb_get_pixclock(var, par);
1487
1488 if (pixclock == 0) {
Ville Syrjälä866d84c2006-01-09 20:53:22 -08001489 if (!(var->activate & FB_ACTIVATE_TEST))
1490 PRINTKE("Invalid pixclock\n");
1491 return -EINVAL;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001492 } else {
1493 if((err = par->pll_ops->var_to_pll(info, pixclock, var->bits_per_pixel, &pll)))
1494 return err;
1495 }
1496
1497 if (var->accel_flags & FB_ACCELF_TEXT)
1498 info->var.accel_flags = FB_ACCELF_TEXT;
1499 else
1500 info->var.accel_flags = 0;
1501
1502#if 0 /* fbmon is not done. uncomment for 2.5.x -brad */
1503 if (!fbmon_valid_timings(pixclock, htotal, vtotal, info))
1504 return -EINVAL;
1505#endif
1506 aty_crtc_to_var(&crtc, var);
1507 var->pixclock = par->pll_ops->pll_to_var(info, &pll);
1508 return 0;
1509}
1510
1511static void set_off_pitch(struct atyfb_par *par, const struct fb_info *info)
1512{
1513 u32 xoffset = info->var.xoffset;
1514 u32 yoffset = info->var.yoffset;
1515 u32 vxres = par->crtc.vxres;
1516 u32 bpp = info->var.bits_per_pixel;
1517
1518 par->crtc.off_pitch = ((yoffset * vxres + xoffset) * bpp / 64) | (vxres << 19);
1519}
1520
1521
1522 /*
1523 * Open/Release the frame buffer device
1524 */
1525
1526static int atyfb_open(struct fb_info *info, int user)
1527{
1528 struct atyfb_par *par = (struct atyfb_par *) info->par;
1529
1530 if (user) {
1531 par->open++;
1532#ifdef __sparc__
1533 par->mmaped = 0;
1534#endif
1535 }
1536 return (0);
1537}
1538
1539static irqreturn_t aty_irq(int irq, void *dev_id, struct pt_regs *fp)
1540{
1541 struct atyfb_par *par = dev_id;
1542 int handled = 0;
1543 u32 int_cntl;
1544
1545 spin_lock(&par->int_lock);
1546
1547 int_cntl = aty_ld_le32(CRTC_INT_CNTL, par);
1548
1549 if (int_cntl & CRTC_VBLANK_INT) {
1550 /* clear interrupt */
1551 aty_st_le32(CRTC_INT_CNTL, (int_cntl & CRTC_INT_EN_MASK) | CRTC_VBLANK_INT_AK, par);
1552 par->vblank.count++;
1553 if (par->vblank.pan_display) {
1554 par->vblank.pan_display = 0;
1555 aty_st_le32(CRTC_OFF_PITCH, par->crtc.off_pitch, par);
1556 }
1557 wake_up_interruptible(&par->vblank.wait);
1558 handled = 1;
1559 }
1560
1561 spin_unlock(&par->int_lock);
1562
1563 return IRQ_RETVAL(handled);
1564}
1565
1566static int aty_enable_irq(struct atyfb_par *par, int reenable)
1567{
1568 u32 int_cntl;
1569
1570 if (!test_and_set_bit(0, &par->irq_flags)) {
1571 if (request_irq(par->irq, aty_irq, SA_SHIRQ, "atyfb", par)) {
1572 clear_bit(0, &par->irq_flags);
1573 return -EINVAL;
1574 }
1575 spin_lock_irq(&par->int_lock);
1576 int_cntl = aty_ld_le32(CRTC_INT_CNTL, par) & CRTC_INT_EN_MASK;
1577 /* clear interrupt */
1578 aty_st_le32(CRTC_INT_CNTL, int_cntl | CRTC_VBLANK_INT_AK, par);
1579 /* enable interrupt */
1580 aty_st_le32(CRTC_INT_CNTL, int_cntl | CRTC_VBLANK_INT_EN, par);
1581 spin_unlock_irq(&par->int_lock);
1582 } else if (reenable) {
1583 spin_lock_irq(&par->int_lock);
1584 int_cntl = aty_ld_le32(CRTC_INT_CNTL, par) & CRTC_INT_EN_MASK;
1585 if (!(int_cntl & CRTC_VBLANK_INT_EN)) {
1586 printk("atyfb: someone disabled IRQ [%08x]\n", int_cntl);
1587 /* re-enable interrupt */
1588 aty_st_le32(CRTC_INT_CNTL, int_cntl | CRTC_VBLANK_INT_EN, par );
1589 }
1590 spin_unlock_irq(&par->int_lock);
1591 }
1592
1593 return 0;
1594}
1595
1596static int aty_disable_irq(struct atyfb_par *par)
1597{
1598 u32 int_cntl;
1599
1600 if (test_and_clear_bit(0, &par->irq_flags)) {
1601 if (par->vblank.pan_display) {
1602 par->vblank.pan_display = 0;
1603 aty_st_le32(CRTC_OFF_PITCH, par->crtc.off_pitch, par);
1604 }
1605 spin_lock_irq(&par->int_lock);
1606 int_cntl = aty_ld_le32(CRTC_INT_CNTL, par) & CRTC_INT_EN_MASK;
1607 /* disable interrupt */
1608 aty_st_le32(CRTC_INT_CNTL, int_cntl & ~CRTC_VBLANK_INT_EN, par );
1609 spin_unlock_irq(&par->int_lock);
1610 free_irq(par->irq, par);
1611 }
1612
1613 return 0;
1614}
1615
1616static int atyfb_release(struct fb_info *info, int user)
1617{
1618 struct atyfb_par *par = (struct atyfb_par *) info->par;
1619 if (user) {
1620 par->open--;
1621 mdelay(1);
1622 wait_for_idle(par);
1623 if (!par->open) {
1624#ifdef __sparc__
1625 int was_mmaped = par->mmaped;
1626
1627 par->mmaped = 0;
1628
1629 if (was_mmaped) {
1630 struct fb_var_screeninfo var;
1631
1632 /* Now reset the default display config, we have no
1633 * idea what the program(s) which mmap'd the chip did
1634 * to the configuration, nor whether it restored it
1635 * correctly.
1636 */
1637 var = default_var;
1638 if (noaccel)
1639 var.accel_flags &= ~FB_ACCELF_TEXT;
1640 else
1641 var.accel_flags |= FB_ACCELF_TEXT;
1642 if (var.yres == var.yres_virtual) {
1643 u32 videoram = (info->fix.smem_len - (PAGE_SIZE << 2));
1644 var.yres_virtual = ((videoram * 8) / var.bits_per_pixel) / var.xres_virtual;
1645 if (var.yres_virtual < var.yres)
1646 var.yres_virtual = var.yres;
1647 }
1648 }
1649#endif
1650 aty_disable_irq(par);
1651 }
1652 }
1653 return (0);
1654}
1655
1656 /*
1657 * Pan or Wrap the Display
1658 *
1659 * This call looks only at xoffset, yoffset and the FB_VMODE_YWRAP flag
1660 */
1661
1662static int atyfb_pan_display(struct fb_var_screeninfo *var, struct fb_info *info)
1663{
1664 struct atyfb_par *par = (struct atyfb_par *) info->par;
1665 u32 xres, yres, xoffset, yoffset;
1666
1667 xres = (((par->crtc.h_tot_disp >> 16) & 0xff) + 1) * 8;
1668 yres = ((par->crtc.v_tot_disp >> 16) & 0x7ff) + 1;
1669 if (par->crtc.gen_cntl & CRTC_DBL_SCAN_EN)
1670 yres >>= 1;
1671 xoffset = (var->xoffset + 7) & ~7;
1672 yoffset = var->yoffset;
1673 if (xoffset + xres > par->crtc.vxres || yoffset + yres > par->crtc.vyres)
1674 return -EINVAL;
1675 info->var.xoffset = xoffset;
1676 info->var.yoffset = yoffset;
1677 if (par->asleep)
1678 return 0;
1679
1680 set_off_pitch(par, info);
1681 if ((var->activate & FB_ACTIVATE_VBL) && !aty_enable_irq(par, 0)) {
1682 par->vblank.pan_display = 1;
1683 } else {
1684 par->vblank.pan_display = 0;
1685 aty_st_le32(CRTC_OFF_PITCH, par->crtc.off_pitch, par);
1686 }
1687
1688 return 0;
1689}
1690
1691static int aty_waitforvblank(struct atyfb_par *par, u32 crtc)
1692{
1693 struct aty_interrupt *vbl;
1694 unsigned int count;
1695 int ret;
1696
1697 switch (crtc) {
1698 case 0:
1699 vbl = &par->vblank;
1700 break;
1701 default:
1702 return -ENODEV;
1703 }
1704
1705 ret = aty_enable_irq(par, 0);
1706 if (ret)
1707 return ret;
1708
1709 count = vbl->count;
1710 ret = wait_event_interruptible_timeout(vbl->wait, count != vbl->count, HZ/10);
1711 if (ret < 0) {
1712 return ret;
1713 }
1714 if (ret == 0) {
1715 aty_enable_irq(par, 1);
1716 return -ETIMEDOUT;
1717 }
1718
1719 return 0;
1720}
1721
1722
1723#ifdef DEBUG
1724#define ATYIO_CLKR 0x41545900 /* ATY\00 */
1725#define ATYIO_CLKW 0x41545901 /* ATY\01 */
1726
1727struct atyclk {
1728 u32 ref_clk_per;
1729 u8 pll_ref_div;
1730 u8 mclk_fb_div;
1731 u8 mclk_post_div; /* 1,2,3,4,8 */
1732 u8 mclk_fb_mult; /* 2 or 4 */
1733 u8 xclk_post_div; /* 1,2,3,4,8 */
1734 u8 vclk_fb_div;
1735 u8 vclk_post_div; /* 1,2,3,4,6,8,12 */
1736 u32 dsp_xclks_per_row; /* 0-16383 */
1737 u32 dsp_loop_latency; /* 0-15 */
1738 u32 dsp_precision; /* 0-7 */
1739 u32 dsp_on; /* 0-2047 */
1740 u32 dsp_off; /* 0-2047 */
1741};
1742
1743#define ATYIO_FEATR 0x41545902 /* ATY\02 */
1744#define ATYIO_FEATW 0x41545903 /* ATY\03 */
1745#endif
1746
1747#ifndef FBIO_WAITFORVSYNC
1748#define FBIO_WAITFORVSYNC _IOW('F', 0x20, __u32)
1749#endif
1750
Christoph Hellwig67a66802006-01-14 13:21:25 -08001751static int atyfb_ioctl(struct fb_info *info, u_int cmd, u_long arg)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001752{
1753 struct atyfb_par *par = (struct atyfb_par *) info->par;
1754#ifdef __sparc__
1755 struct fbtype fbtyp;
1756#endif
1757
1758 switch (cmd) {
1759#ifdef __sparc__
1760 case FBIOGTYPE:
1761 fbtyp.fb_type = FBTYPE_PCI_GENERIC;
1762 fbtyp.fb_width = par->crtc.vxres;
1763 fbtyp.fb_height = par->crtc.vyres;
1764 fbtyp.fb_depth = info->var.bits_per_pixel;
1765 fbtyp.fb_cmsize = info->cmap.len;
1766 fbtyp.fb_size = info->fix.smem_len;
1767 if (copy_to_user((struct fbtype __user *) arg, &fbtyp, sizeof(fbtyp)))
1768 return -EFAULT;
1769 break;
1770#endif /* __sparc__ */
1771
1772 case FBIO_WAITFORVSYNC:
1773 {
1774 u32 crtc;
1775
1776 if (get_user(crtc, (__u32 __user *) arg))
1777 return -EFAULT;
1778
1779 return aty_waitforvblank(par, crtc);
1780 }
1781 break;
1782
1783#if defined(DEBUG) && defined(CONFIG_FB_ATY_CT)
1784 case ATYIO_CLKR:
1785 if (M64_HAS(INTEGRATED)) {
1786 struct atyclk clk;
1787 union aty_pll *pll = &(par->pll);
1788 u32 dsp_config = pll->ct.dsp_config;
1789 u32 dsp_on_off = pll->ct.dsp_on_off;
1790 clk.ref_clk_per = par->ref_clk_per;
1791 clk.pll_ref_div = pll->ct.pll_ref_div;
1792 clk.mclk_fb_div = pll->ct.mclk_fb_div;
1793 clk.mclk_post_div = pll->ct.mclk_post_div_real;
1794 clk.mclk_fb_mult = pll->ct.mclk_fb_mult;
1795 clk.xclk_post_div = pll->ct.xclk_post_div_real;
1796 clk.vclk_fb_div = pll->ct.vclk_fb_div;
1797 clk.vclk_post_div = pll->ct.vclk_post_div_real;
1798 clk.dsp_xclks_per_row = dsp_config & 0x3fff;
1799 clk.dsp_loop_latency = (dsp_config >> 16) & 0xf;
1800 clk.dsp_precision = (dsp_config >> 20) & 7;
1801 clk.dsp_off = dsp_on_off & 0x7ff;
1802 clk.dsp_on = (dsp_on_off >> 16) & 0x7ff;
1803 if (copy_to_user((struct atyclk __user *) arg, &clk,
1804 sizeof(clk)))
1805 return -EFAULT;
1806 } else
1807 return -EINVAL;
1808 break;
1809 case ATYIO_CLKW:
1810 if (M64_HAS(INTEGRATED)) {
1811 struct atyclk clk;
1812 union aty_pll *pll = &(par->pll);
1813 if (copy_from_user(&clk, (struct atyclk __user *) arg, sizeof(clk)))
1814 return -EFAULT;
1815 par->ref_clk_per = clk.ref_clk_per;
1816 pll->ct.pll_ref_div = clk.pll_ref_div;
1817 pll->ct.mclk_fb_div = clk.mclk_fb_div;
1818 pll->ct.mclk_post_div_real = clk.mclk_post_div;
1819 pll->ct.mclk_fb_mult = clk.mclk_fb_mult;
1820 pll->ct.xclk_post_div_real = clk.xclk_post_div;
1821 pll->ct.vclk_fb_div = clk.vclk_fb_div;
1822 pll->ct.vclk_post_div_real = clk.vclk_post_div;
1823 pll->ct.dsp_config = (clk.dsp_xclks_per_row & 0x3fff) |
1824 ((clk.dsp_loop_latency & 0xf)<<16)| ((clk.dsp_precision & 7)<<20);
1825 pll->ct.dsp_on_off = (clk.dsp_off & 0x7ff) | ((clk.dsp_on & 0x7ff)<<16);
1826 /*aty_calc_pll_ct(info, &pll->ct);*/
1827 aty_set_pll_ct(info, pll);
1828 } else
1829 return -EINVAL;
1830 break;
1831 case ATYIO_FEATR:
1832 if (get_user(par->features, (u32 __user *) arg))
1833 return -EFAULT;
1834 break;
1835 case ATYIO_FEATW:
1836 if (put_user(par->features, (u32 __user *) arg))
1837 return -EFAULT;
1838 break;
1839#endif /* DEBUG && CONFIG_FB_ATY_CT */
1840 default:
1841 return -EINVAL;
1842 }
1843 return 0;
1844}
1845
1846static int atyfb_sync(struct fb_info *info)
1847{
1848 struct atyfb_par *par = (struct atyfb_par *) info->par;
1849
1850 if (par->blitter_may_be_busy)
1851 wait_for_idle(par);
1852 return 0;
1853}
1854
1855#ifdef __sparc__
Christoph Hellwig216d5262006-01-14 13:21:25 -08001856static int atyfb_mmap(struct fb_info *info, struct vm_area_struct *vma)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001857{
1858 struct atyfb_par *par = (struct atyfb_par *) info->par;
1859 unsigned int size, page, map_size = 0;
1860 unsigned long map_offset = 0;
1861 unsigned long off;
1862 int i;
1863
1864 if (!par->mmap_map)
1865 return -ENXIO;
1866
1867 if (vma->vm_pgoff > (~0UL >> PAGE_SHIFT))
1868 return -EINVAL;
1869
1870 off = vma->vm_pgoff << PAGE_SHIFT;
1871 size = vma->vm_end - vma->vm_start;
1872
1873 /* To stop the swapper from even considering these pages. */
1874 vma->vm_flags |= (VM_IO | VM_RESERVED);
1875
1876 if (((vma->vm_pgoff == 0) && (size == info->fix.smem_len)) ||
1877 ((off == info->fix.smem_len) && (size == PAGE_SIZE)))
1878 off += 0x8000000000000000UL;
1879
1880 vma->vm_pgoff = off >> PAGE_SHIFT; /* propagate off changes */
1881
1882 /* Each page, see which map applies */
1883 for (page = 0; page < size;) {
1884 map_size = 0;
1885 for (i = 0; par->mmap_map[i].size; i++) {
1886 unsigned long start = par->mmap_map[i].voff;
1887 unsigned long end = start + par->mmap_map[i].size;
1888 unsigned long offset = off + page;
1889
1890 if (start > offset)
1891 continue;
1892 if (offset >= end)
1893 continue;
1894
1895 map_size = par->mmap_map[i].size - (offset - start);
1896 map_offset =
1897 par->mmap_map[i].poff + (offset - start);
1898 break;
1899 }
1900 if (!map_size) {
1901 page += PAGE_SIZE;
1902 continue;
1903 }
1904 if (page + map_size > size)
1905 map_size = size - page;
1906
1907 pgprot_val(vma->vm_page_prot) &=
1908 ~(par->mmap_map[i].prot_mask);
1909 pgprot_val(vma->vm_page_prot) |= par->mmap_map[i].prot_flag;
1910
1911 if (remap_pfn_range(vma, vma->vm_start + page,
1912 map_offset >> PAGE_SHIFT, map_size, vma->vm_page_prot))
1913 return -EAGAIN;
1914
1915 page += map_size;
1916 }
1917
1918 if (!map_size)
1919 return -EINVAL;
1920
1921 if (!par->mmaped)
1922 par->mmaped = 1;
1923 return 0;
1924}
1925
1926static struct {
1927 u32 yoffset;
1928 u8 r[2][256];
1929 u8 g[2][256];
1930 u8 b[2][256];
1931} atyfb_save;
1932
1933static void atyfb_save_palette(struct atyfb_par *par, int enter)
1934{
1935 int i, tmp;
1936
1937 for (i = 0; i < 256; i++) {
1938 tmp = aty_ld_8(DAC_CNTL, par) & 0xfc;
1939 if (M64_HAS(EXTRA_BRIGHT))
1940 tmp |= 0x2;
1941 aty_st_8(DAC_CNTL, tmp, par);
1942 aty_st_8(DAC_MASK, 0xff, par);
1943
1944 writeb(i, &par->aty_cmap_regs->rindex);
1945 atyfb_save.r[enter][i] = readb(&par->aty_cmap_regs->lut);
1946 atyfb_save.g[enter][i] = readb(&par->aty_cmap_regs->lut);
1947 atyfb_save.b[enter][i] = readb(&par->aty_cmap_regs->lut);
1948 writeb(i, &par->aty_cmap_regs->windex);
1949 writeb(atyfb_save.r[1 - enter][i],
1950 &par->aty_cmap_regs->lut);
1951 writeb(atyfb_save.g[1 - enter][i],
1952 &par->aty_cmap_regs->lut);
1953 writeb(atyfb_save.b[1 - enter][i],
1954 &par->aty_cmap_regs->lut);
1955 }
1956}
1957
1958static void atyfb_palette(int enter)
1959{
1960 struct atyfb_par *par;
1961 struct fb_info *info;
1962 int i;
1963
1964 for (i = 0; i < FB_MAX; i++) {
1965 info = registered_fb[i];
1966 if (info && info->fbops == &atyfb_ops) {
1967 par = (struct atyfb_par *) info->par;
1968
1969 atyfb_save_palette(par, enter);
1970 if (enter) {
1971 atyfb_save.yoffset = info->var.yoffset;
1972 info->var.yoffset = 0;
1973 set_off_pitch(par, info);
1974 } else {
1975 info->var.yoffset = atyfb_save.yoffset;
1976 set_off_pitch(par, info);
1977 }
1978 aty_st_le32(CRTC_OFF_PITCH, par->crtc.off_pitch, par);
1979 break;
1980 }
1981 }
1982}
1983#endif /* __sparc__ */
1984
1985
1986
1987#if defined(CONFIG_PM) && defined(CONFIG_PCI)
1988
1989/* Power management routines. Those are used for PowerBook sleep.
1990 */
1991static int aty_power_mgmt(int sleep, struct atyfb_par *par)
1992{
1993 u32 pm;
1994 int timeout;
1995
1996 pm = aty_ld_lcd(POWER_MANAGEMENT, par);
1997 pm = (pm & ~PWR_MGT_MODE_MASK) | PWR_MGT_MODE_REG;
1998 aty_st_lcd(POWER_MANAGEMENT, pm, par);
1999 pm = aty_ld_lcd(POWER_MANAGEMENT, par);
2000
2001 timeout = 2000;
2002 if (sleep) {
2003 /* Sleep */
2004 pm &= ~PWR_MGT_ON;
2005 aty_st_lcd(POWER_MANAGEMENT, pm, par);
2006 pm = aty_ld_lcd(POWER_MANAGEMENT, par);
2007 udelay(10);
2008 pm &= ~(PWR_BLON | AUTO_PWR_UP);
2009 pm |= SUSPEND_NOW;
2010 aty_st_lcd(POWER_MANAGEMENT, pm, par);
2011 pm = aty_ld_lcd(POWER_MANAGEMENT, par);
2012 udelay(10);
2013 pm |= PWR_MGT_ON;
2014 aty_st_lcd(POWER_MANAGEMENT, pm, par);
2015 do {
2016 pm = aty_ld_lcd(POWER_MANAGEMENT, par);
2017 mdelay(1);
2018 if ((--timeout) == 0)
2019 break;
2020 } while ((pm & PWR_MGT_STATUS_MASK) != PWR_MGT_STATUS_SUSPEND);
2021 } else {
2022 /* Wakeup */
2023 pm &= ~PWR_MGT_ON;
2024 aty_st_lcd(POWER_MANAGEMENT, pm, par);
2025 pm = aty_ld_lcd(POWER_MANAGEMENT, par);
2026 udelay(10);
2027 pm &= ~SUSPEND_NOW;
2028 pm |= (PWR_BLON | AUTO_PWR_UP);
2029 aty_st_lcd(POWER_MANAGEMENT, pm, par);
2030 pm = aty_ld_lcd(POWER_MANAGEMENT, par);
2031 udelay(10);
2032 pm |= PWR_MGT_ON;
2033 aty_st_lcd(POWER_MANAGEMENT, pm, par);
2034 do {
2035 pm = aty_ld_lcd(POWER_MANAGEMENT, par);
2036 mdelay(1);
2037 if ((--timeout) == 0)
2038 break;
2039 } while ((pm & PWR_MGT_STATUS_MASK) != 0);
2040 }
2041 mdelay(500);
2042
2043 return timeout ? 0 : -EIO;
2044}
2045
2046static int atyfb_pci_suspend(struct pci_dev *pdev, pm_message_t state)
2047{
2048 struct fb_info *info = pci_get_drvdata(pdev);
2049 struct atyfb_par *par = (struct atyfb_par *) info->par;
2050
Pavel Machekca078ba2005-09-03 15:56:57 -07002051#ifndef CONFIG_PPC_PMAC
Linus Torvalds1da177e2005-04-16 15:20:36 -07002052 /* HACK ALERT ! Once I find a proper way to say to each driver
2053 * individually what will happen with it's PCI slot, I'll change
2054 * that. On laptops, the AGP slot is just unclocked, so D2 is
2055 * expected, while on desktops, the card is powered off
2056 */
Pavel Machekca078ba2005-09-03 15:56:57 -07002057 return 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002058#endif /* CONFIG_PPC_PMAC */
2059
Pavel Machekca078ba2005-09-03 15:56:57 -07002060 if (state.event == pdev->dev.power.power_state.event)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002061 return 0;
2062
2063 acquire_console_sem();
2064
2065 fb_set_suspend(info, 1);
2066
2067 /* Idle & reset engine */
2068 wait_for_idle(par);
2069 aty_reset_engine(par);
2070
2071 /* Blank display and LCD */
2072 atyfb_blank(FB_BLANK_POWERDOWN, info);
2073
2074 par->asleep = 1;
2075 par->lock_blank = 1;
2076
2077 /* Set chip to "suspend" mode */
2078 if (aty_power_mgmt(1, par)) {
2079 par->asleep = 0;
2080 par->lock_blank = 0;
2081 atyfb_blank(FB_BLANK_UNBLANK, info);
2082 fb_set_suspend(info, 0);
2083 release_console_sem();
2084 return -EIO;
2085 }
2086
2087 release_console_sem();
2088
2089 pdev->dev.power.power_state = state;
2090
2091 return 0;
2092}
2093
2094static int atyfb_pci_resume(struct pci_dev *pdev)
2095{
2096 struct fb_info *info = pci_get_drvdata(pdev);
2097 struct atyfb_par *par = (struct atyfb_par *) info->par;
2098
Pavel Machekca078ba2005-09-03 15:56:57 -07002099 if (pdev->dev.power.power_state.event == PM_EVENT_ON)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002100 return 0;
2101
2102 acquire_console_sem();
2103
Pavel Machekca078ba2005-09-03 15:56:57 -07002104 if (pdev->dev.power.power_state.event == 2)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002105 aty_power_mgmt(0, par);
2106 par->asleep = 0;
2107
2108 /* Restore display */
2109 atyfb_set_par(info);
2110
2111 /* Refresh */
2112 fb_set_suspend(info, 0);
2113
2114 /* Unblank */
2115 par->lock_blank = 0;
2116 atyfb_blank(FB_BLANK_UNBLANK, info);
2117
2118 release_console_sem();
2119
2120 pdev->dev.power.power_state = PMSG_ON;
2121
2122 return 0;
2123}
2124
2125#endif /* defined(CONFIG_PM) && defined(CONFIG_PCI) */
2126
Michael Hanselmann5474c122006-06-25 05:47:08 -07002127/* Backlight */
2128#ifdef CONFIG_FB_ATY_BACKLIGHT
2129#define MAX_LEVEL 0xFF
Linus Torvalds1da177e2005-04-16 15:20:36 -07002130
Michael Hanselmann5474c122006-06-25 05:47:08 -07002131static struct backlight_properties aty_bl_data;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002132
Michael Hanselmann5474c122006-06-25 05:47:08 -07002133static int aty_bl_get_level_brightness(struct atyfb_par *par, int level)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002134{
Michael Hanselmann5474c122006-06-25 05:47:08 -07002135 struct fb_info *info = pci_get_drvdata(par->pdev);
2136 int atylevel;
2137
2138 /* Get and convert the value */
2139 mutex_lock(&info->bl_mutex);
2140 atylevel = info->bl_curve[level] * FB_BACKLIGHT_MAX / MAX_LEVEL;
2141 mutex_unlock(&info->bl_mutex);
2142
2143 if (atylevel < 0)
2144 atylevel = 0;
2145 else if (atylevel > MAX_LEVEL)
2146 atylevel = MAX_LEVEL;
2147
2148 return atylevel;
2149}
2150
2151static int aty_bl_update_status(struct backlight_device *bd)
2152{
2153 struct atyfb_par *par = class_get_devdata(&bd->class_dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002154 unsigned int reg = aty_ld_lcd(LCD_MISC_CNTL, par);
Michael Hanselmann5474c122006-06-25 05:47:08 -07002155 int level;
2156
2157 if (bd->props->power != FB_BLANK_UNBLANK ||
2158 bd->props->fb_blank != FB_BLANK_UNBLANK)
2159 level = 0;
2160 else
2161 level = bd->props->brightness;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002162
2163 reg |= (BLMOD_EN | BIASMOD_EN);
Michael Hanselmann5474c122006-06-25 05:47:08 -07002164 if (level > 0) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07002165 reg &= ~BIAS_MOD_LEVEL_MASK;
Michael Hanselmann5474c122006-06-25 05:47:08 -07002166 reg |= (aty_bl_get_level_brightness(par, level) << BIAS_MOD_LEVEL_SHIFT);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002167 } else {
2168 reg &= ~BIAS_MOD_LEVEL_MASK;
Michael Hanselmann5474c122006-06-25 05:47:08 -07002169 reg |= (aty_bl_get_level_brightness(par, 0) << BIAS_MOD_LEVEL_SHIFT);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002170 }
2171 aty_st_lcd(LCD_MISC_CNTL, reg, par);
Michael Hanselmann5474c122006-06-25 05:47:08 -07002172
Linus Torvalds1da177e2005-04-16 15:20:36 -07002173 return 0;
2174}
2175
Michael Hanselmann5474c122006-06-25 05:47:08 -07002176static int aty_bl_get_brightness(struct backlight_device *bd)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002177{
Michael Hanselmann5474c122006-06-25 05:47:08 -07002178 return bd->props->brightness;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002179}
2180
Michael Hanselmann5474c122006-06-25 05:47:08 -07002181static struct backlight_properties aty_bl_data = {
2182 .owner = THIS_MODULE,
2183 .get_brightness = aty_bl_get_brightness,
2184 .update_status = aty_bl_update_status,
2185 .max_brightness = (FB_BACKLIGHT_LEVELS - 1),
Linus Torvalds1da177e2005-04-16 15:20:36 -07002186};
Michael Hanselmann5474c122006-06-25 05:47:08 -07002187
2188static void aty_bl_init(struct atyfb_par *par)
2189{
2190 struct fb_info *info = pci_get_drvdata(par->pdev);
2191 struct backlight_device *bd;
2192 char name[12];
2193
2194#ifdef CONFIG_PMAC_BACKLIGHT
2195 if (!pmac_has_backlight_type("ati"))
2196 return;
2197#endif
2198
2199 snprintf(name, sizeof(name), "atybl%d", info->node);
2200
2201 bd = backlight_device_register(name, par, &aty_bl_data);
2202 if (IS_ERR(bd)) {
2203 info->bl_dev = NULL;
2204 printk("aty: Backlight registration failed\n");
2205 goto error;
2206 }
2207
2208 mutex_lock(&info->bl_mutex);
2209 info->bl_dev = bd;
2210 fb_bl_default_curve(info, 0,
2211 0x3F * FB_BACKLIGHT_MAX / MAX_LEVEL,
2212 0xFF * FB_BACKLIGHT_MAX / MAX_LEVEL);
2213 mutex_unlock(&info->bl_mutex);
2214
2215 up(&bd->sem);
2216 bd->props->brightness = aty_bl_data.max_brightness;
2217 bd->props->power = FB_BLANK_UNBLANK;
2218 bd->props->update_status(bd);
2219 down(&bd->sem);
2220
2221#ifdef CONFIG_PMAC_BACKLIGHT
2222 mutex_lock(&pmac_backlight_mutex);
2223 if (!pmac_backlight)
2224 pmac_backlight = bd;
2225 mutex_unlock(&pmac_backlight_mutex);
2226#endif
2227
2228 printk("aty: Backlight initialized (%s)\n", name);
2229
2230 return;
2231
2232error:
2233 return;
2234}
2235
2236static void aty_bl_exit(struct atyfb_par *par)
2237{
2238 struct fb_info *info = pci_get_drvdata(par->pdev);
2239
2240#ifdef CONFIG_PMAC_BACKLIGHT
2241 mutex_lock(&pmac_backlight_mutex);
2242#endif
2243
2244 mutex_lock(&info->bl_mutex);
2245 if (info->bl_dev) {
2246#ifdef CONFIG_PMAC_BACKLIGHT
2247 if (pmac_backlight == info->bl_dev)
2248 pmac_backlight = NULL;
2249#endif
2250
2251 backlight_device_unregister(info->bl_dev);
2252
2253 printk("aty: Backlight unloaded\n");
2254 }
2255 mutex_unlock(&info->bl_mutex);
2256
2257#ifdef CONFIG_PMAC_BACKLIGHT
2258 mutex_unlock(&pmac_backlight_mutex);
2259#endif
2260}
2261
2262#endif /* CONFIG_FB_ATY_BACKLIGHT */
Linus Torvalds1da177e2005-04-16 15:20:36 -07002263
2264static void __init aty_calc_mem_refresh(struct atyfb_par *par, int xclk)
2265{
2266 const int ragepro_tbl[] = {
2267 44, 50, 55, 66, 75, 80, 100
2268 };
2269 const int ragexl_tbl[] = {
2270 50, 66, 75, 83, 90, 95, 100, 105,
2271 110, 115, 120, 125, 133, 143, 166
2272 };
2273 const int *refresh_tbl;
2274 int i, size;
2275
2276 if (IS_XL(par->pci_id) || IS_MOBILITY(par->pci_id)) {
2277 refresh_tbl = ragexl_tbl;
Tobias Klauserd1ae4182006-03-27 01:17:39 -08002278 size = ARRAY_SIZE(ragexl_tbl);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002279 } else {
2280 refresh_tbl = ragepro_tbl;
Tobias Klauserd1ae4182006-03-27 01:17:39 -08002281 size = ARRAY_SIZE(ragepro_tbl);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002282 }
2283
2284 for (i=0; i < size; i++) {
2285 if (xclk < refresh_tbl[i])
2286 break;
2287 }
2288 par->mem_refresh_rate = i;
2289}
2290
2291 /*
2292 * Initialisation
2293 */
2294
2295static struct fb_info *fb_list = NULL;
2296
Antonino A. Daplas1013d262005-11-07 01:00:41 -08002297#if defined(__i386__) && defined(CONFIG_FB_ATY_GENERIC_LCD)
2298static int __devinit atyfb_get_timings_from_lcd(struct atyfb_par *par,
2299 struct fb_var_screeninfo *var)
2300{
2301 int ret = -EINVAL;
2302
2303 if (par->lcd_table != 0 && (aty_ld_lcd(LCD_GEN_CNTL, par) & LCD_ON)) {
2304 *var = default_var;
2305 var->xres = var->xres_virtual = par->lcd_hdisp;
2306 var->right_margin = par->lcd_right_margin;
2307 var->left_margin = par->lcd_hblank_len -
2308 (par->lcd_right_margin + par->lcd_hsync_dly +
2309 par->lcd_hsync_len);
2310 var->hsync_len = par->lcd_hsync_len + par->lcd_hsync_dly;
2311 var->yres = var->yres_virtual = par->lcd_vdisp;
2312 var->lower_margin = par->lcd_lower_margin;
2313 var->upper_margin = par->lcd_vblank_len -
2314 (par->lcd_lower_margin + par->lcd_vsync_len);
2315 var->vsync_len = par->lcd_vsync_len;
2316 var->pixclock = par->lcd_pixclock;
2317 ret = 0;
2318 }
2319
2320 return ret;
2321}
2322#endif /* defined(__i386__) && defined(CONFIG_FB_ATY_GENERIC_LCD) */
2323
Linus Torvalds1da177e2005-04-16 15:20:36 -07002324static int __init aty_init(struct fb_info *info, const char *name)
2325{
2326 struct atyfb_par *par = (struct atyfb_par *) info->par;
2327 const char *ramname = NULL, *xtal;
Antonino A. Daplas1013d262005-11-07 01:00:41 -08002328 int gtb_memsize, has_var = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002329 struct fb_var_screeninfo var;
2330 u8 pll_ref_div;
2331 u32 i;
2332#if defined(CONFIG_PPC)
2333 int sense;
2334#endif
2335
2336 init_waitqueue_head(&par->vblank.wait);
2337 spin_lock_init(&par->int_lock);
2338
2339 par->aty_cmap_regs =
2340 (struct aty_cmap_regs __iomem *) (par->ati_regbase + 0xc0);
2341
2342#ifdef CONFIG_PPC_PMAC
2343 /* The Apple iBook1 uses non-standard memory frequencies. We detect it
2344 * and set the frequency manually. */
2345 if (machine_is_compatible("PowerBook2,1")) {
2346 par->pll_limits.mclk = 70;
2347 par->pll_limits.xclk = 53;
2348 }
2349#endif
2350 if (pll)
2351 par->pll_limits.pll_max = pll;
2352 if (mclk)
2353 par->pll_limits.mclk = mclk;
2354 if (xclk)
2355 par->pll_limits.xclk = xclk;
2356
2357 aty_calc_mem_refresh(par, par->pll_limits.xclk);
2358 par->pll_per = 1000000/par->pll_limits.pll_max;
2359 par->mclk_per = 1000000/par->pll_limits.mclk;
2360 par->xclk_per = 1000000/par->pll_limits.xclk;
2361
2362 par->ref_clk_per = 1000000000000ULL / 14318180;
2363 xtal = "14.31818";
2364
2365#ifdef CONFIG_FB_ATY_GX
2366 if (!M64_HAS(INTEGRATED)) {
2367 u32 stat0;
2368 u8 dac_type, dac_subtype, clk_type;
2369 stat0 = aty_ld_le32(CONFIG_STAT0, par);
2370 par->bus_type = (stat0 >> 0) & 0x07;
2371 par->ram_type = (stat0 >> 3) & 0x07;
2372 ramname = aty_gx_ram[par->ram_type];
2373 /* FIXME: clockchip/RAMDAC probing? */
2374 dac_type = (aty_ld_le32(DAC_CNTL, par) >> 16) & 0x07;
2375#ifdef CONFIG_ATARI
2376 clk_type = CLK_ATI18818_1;
2377 dac_type = (stat0 >> 9) & 0x07;
2378 if (dac_type == 0x07)
2379 dac_subtype = DAC_ATT20C408;
2380 else
2381 dac_subtype = (aty_ld_8(SCRATCH_REG1 + 1, par) & 0xF0) | dac_type;
2382#else
2383 dac_type = DAC_IBMRGB514;
2384 dac_subtype = DAC_IBMRGB514;
2385 clk_type = CLK_IBMRGB514;
2386#endif
2387 switch (dac_subtype) {
2388 case DAC_IBMRGB514:
2389 par->dac_ops = &aty_dac_ibm514;
2390 break;
2391 case DAC_ATI68860_B:
2392 case DAC_ATI68860_C:
2393 par->dac_ops = &aty_dac_ati68860b;
2394 break;
2395 case DAC_ATT20C408:
2396 case DAC_ATT21C498:
2397 par->dac_ops = &aty_dac_att21c498;
2398 break;
2399 default:
2400 PRINTKI("aty_init: DAC type not implemented yet!\n");
2401 par->dac_ops = &aty_dac_unsupported;
2402 break;
2403 }
2404 switch (clk_type) {
2405 case CLK_ATI18818_1:
2406 par->pll_ops = &aty_pll_ati18818_1;
2407 break;
Antonino A. Daplaseba87e82006-03-27 01:17:35 -08002408 case CLK_IBMRGB514:
2409 par->pll_ops = &aty_pll_ibm514;
2410 break;
2411#if 0 /* dead code */
Linus Torvalds1da177e2005-04-16 15:20:36 -07002412 case CLK_STG1703:
2413 par->pll_ops = &aty_pll_stg1703;
2414 break;
2415 case CLK_CH8398:
2416 par->pll_ops = &aty_pll_ch8398;
2417 break;
2418 case CLK_ATT20C408:
2419 par->pll_ops = &aty_pll_att20c408;
2420 break;
Antonino A. Daplaseba87e82006-03-27 01:17:35 -08002421#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -07002422 default:
2423 PRINTKI("aty_init: CLK type not implemented yet!");
2424 par->pll_ops = &aty_pll_unsupported;
2425 break;
2426 }
2427 }
2428#endif /* CONFIG_FB_ATY_GX */
2429#ifdef CONFIG_FB_ATY_CT
2430 if (M64_HAS(INTEGRATED)) {
2431 par->dac_ops = &aty_dac_ct;
2432 par->pll_ops = &aty_pll_ct;
2433 par->bus_type = PCI;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002434 par->ram_type = (aty_ld_le32(CONFIG_STAT0, par) & 0x07);
2435 ramname = aty_ct_ram[par->ram_type];
2436 /* for many chips, the mclk is 67 MHz for SDRAM, 63 MHz otherwise */
2437 if (par->pll_limits.mclk == 67 && par->ram_type < SDRAM)
2438 par->pll_limits.mclk = 63;
2439 }
2440
2441 if (M64_HAS(GTB_DSP)
2442 && (pll_ref_div = aty_ld_pll_ct(PLL_REF_DIV, par))) {
2443 int diff1, diff2;
2444 diff1 = 510 * 14 / pll_ref_div - par->pll_limits.pll_max;
2445 diff2 = 510 * 29 / pll_ref_div - par->pll_limits.pll_max;
2446 if (diff1 < 0)
2447 diff1 = -diff1;
2448 if (diff2 < 0)
2449 diff2 = -diff2;
2450 if (diff2 < diff1) {
2451 par->ref_clk_per = 1000000000000ULL / 29498928;
2452 xtal = "29.498928";
2453 }
2454 }
2455#endif /* CONFIG_FB_ATY_CT */
2456
2457 /* save previous video mode */
2458 aty_get_crtc(par, &saved_crtc);
2459 if(par->pll_ops->get_pll)
2460 par->pll_ops->get_pll(info, &saved_pll);
2461
2462 i = aty_ld_le32(MEM_CNTL, par);
2463 gtb_memsize = M64_HAS(GTB_DSP);
2464 if (gtb_memsize)
2465 switch (i & 0xF) { /* 0xF used instead of MEM_SIZE_ALIAS */
2466 case MEM_SIZE_512K:
2467 info->fix.smem_len = 0x80000;
2468 break;
2469 case MEM_SIZE_1M:
2470 info->fix.smem_len = 0x100000;
2471 break;
2472 case MEM_SIZE_2M_GTB:
2473 info->fix.smem_len = 0x200000;
2474 break;
2475 case MEM_SIZE_4M_GTB:
2476 info->fix.smem_len = 0x400000;
2477 break;
2478 case MEM_SIZE_6M_GTB:
2479 info->fix.smem_len = 0x600000;
2480 break;
2481 case MEM_SIZE_8M_GTB:
2482 info->fix.smem_len = 0x800000;
2483 break;
2484 default:
2485 info->fix.smem_len = 0x80000;
2486 } else
2487 switch (i & MEM_SIZE_ALIAS) {
2488 case MEM_SIZE_512K:
2489 info->fix.smem_len = 0x80000;
2490 break;
2491 case MEM_SIZE_1M:
2492 info->fix.smem_len = 0x100000;
2493 break;
2494 case MEM_SIZE_2M:
2495 info->fix.smem_len = 0x200000;
2496 break;
2497 case MEM_SIZE_4M:
2498 info->fix.smem_len = 0x400000;
2499 break;
2500 case MEM_SIZE_6M:
2501 info->fix.smem_len = 0x600000;
2502 break;
2503 case MEM_SIZE_8M:
2504 info->fix.smem_len = 0x800000;
2505 break;
2506 default:
2507 info->fix.smem_len = 0x80000;
2508 }
2509
2510 if (M64_HAS(MAGIC_VRAM_SIZE)) {
2511 if (aty_ld_le32(CONFIG_STAT1, par) & 0x40000000)
2512 info->fix.smem_len += 0x400000;
2513 }
2514
2515 if (vram) {
2516 info->fix.smem_len = vram * 1024;
2517 i = i & ~(gtb_memsize ? 0xF : MEM_SIZE_ALIAS);
2518 if (info->fix.smem_len <= 0x80000)
2519 i |= MEM_SIZE_512K;
2520 else if (info->fix.smem_len <= 0x100000)
2521 i |= MEM_SIZE_1M;
2522 else if (info->fix.smem_len <= 0x200000)
2523 i |= gtb_memsize ? MEM_SIZE_2M_GTB : MEM_SIZE_2M;
2524 else if (info->fix.smem_len <= 0x400000)
2525 i |= gtb_memsize ? MEM_SIZE_4M_GTB : MEM_SIZE_4M;
2526 else if (info->fix.smem_len <= 0x600000)
2527 i |= gtb_memsize ? MEM_SIZE_6M_GTB : MEM_SIZE_6M;
2528 else
2529 i |= gtb_memsize ? MEM_SIZE_8M_GTB : MEM_SIZE_8M;
2530 aty_st_le32(MEM_CNTL, i, par);
2531 }
2532
2533 /*
2534 * Reg Block 0 (CT-compatible block) is at mmio_start
2535 * Reg Block 1 (multimedia extensions) is at mmio_start - 0x400
2536 */
2537 if (M64_HAS(GX)) {
2538 info->fix.mmio_len = 0x400;
2539 info->fix.accel = FB_ACCEL_ATI_MACH64GX;
2540 } else if (M64_HAS(CT)) {
2541 info->fix.mmio_len = 0x400;
2542 info->fix.accel = FB_ACCEL_ATI_MACH64CT;
2543 } else if (M64_HAS(VT)) {
2544 info->fix.mmio_start -= 0x400;
2545 info->fix.mmio_len = 0x800;
2546 info->fix.accel = FB_ACCEL_ATI_MACH64VT;
2547 } else {/* GT */
2548 info->fix.mmio_start -= 0x400;
2549 info->fix.mmio_len = 0x800;
2550 info->fix.accel = FB_ACCEL_ATI_MACH64GT;
2551 }
2552
2553 PRINTKI("%d%c %s, %s MHz XTAL, %d MHz PLL, %d Mhz MCLK, %d MHz XCLK\n",
2554 info->fix.smem_len == 0x80000 ? 512 : (info->fix.smem_len >> 20),
2555 info->fix.smem_len == 0x80000 ? 'K' : 'M', ramname, xtal, par->pll_limits.pll_max,
2556 par->pll_limits.mclk, par->pll_limits.xclk);
2557
2558#if defined(DEBUG) && defined(CONFIG_ATY_CT)
2559 if (M64_HAS(INTEGRATED)) {
2560 int i;
2561 printk("debug atyfb: BUS_CNTL DAC_CNTL MEM_CNTL EXT_MEM_CNTL CRTC_GEN_CNTL "
2562 "DSP_CONFIG DSP_ON_OFF CLOCK_CNTL\n"
2563 "debug atyfb: %08x %08x %08x %08x %08x %08x %08x %08x\n"
2564 "debug atyfb: PLL",
2565 aty_ld_le32(BUS_CNTL, par), aty_ld_le32(DAC_CNTL, par),
2566 aty_ld_le32(MEM_CNTL, par), aty_ld_le32(EXT_MEM_CNTL, par),
2567 aty_ld_le32(CRTC_GEN_CNTL, par), aty_ld_le32(DSP_CONFIG, par),
2568 aty_ld_le32(DSP_ON_OFF, par), aty_ld_le32(CLOCK_CNTL, par));
2569 for (i = 0; i < 40; i++)
2570 printk(" %02x", aty_ld_pll_ct(i, par));
2571 printk("\n");
2572 }
2573#endif
2574 if(par->pll_ops->init_pll)
2575 par->pll_ops->init_pll(info, &par->pll);
2576
2577 /*
2578 * Last page of 8 MB (4 MB on ISA) aperture is MMIO
2579 * FIXME: we should use the auxiliary aperture instead so we can access
2580 * the full 8 MB of video RAM on 8 MB boards
2581 */
2582
2583 if (!par->aux_start &&
2584 (info->fix.smem_len == 0x800000 || (par->bus_type == ISA && info->fix.smem_len == 0x400000)))
2585 info->fix.smem_len -= GUI_RESERVE;
2586
2587 /*
2588 * Disable register access through the linear aperture
2589 * if the auxiliary aperture is used so we can access
2590 * the full 8 MB of video RAM on 8 MB boards.
2591 */
2592 if (par->aux_start)
2593 aty_st_le32(BUS_CNTL, aty_ld_le32(BUS_CNTL, par) | BUS_APER_REG_DIS, par);
2594
2595#ifdef CONFIG_MTRR
2596 par->mtrr_aper = -1;
2597 par->mtrr_reg = -1;
2598 if (!nomtrr) {
2599 /* Cover the whole resource. */
2600 par->mtrr_aper = mtrr_add(par->res_start, par->res_size, MTRR_TYPE_WRCOMB, 1);
2601 if (par->mtrr_aper >= 0 && !par->aux_start) {
2602 /* Make a hole for mmio. */
2603 par->mtrr_reg = mtrr_add(par->res_start + 0x800000 - GUI_RESERVE,
2604 GUI_RESERVE, MTRR_TYPE_UNCACHABLE, 1);
2605 if (par->mtrr_reg < 0) {
2606 mtrr_del(par->mtrr_aper, 0, 0);
2607 par->mtrr_aper = -1;
2608 }
2609 }
2610 }
2611#endif
2612
2613 info->fbops = &atyfb_ops;
2614 info->pseudo_palette = pseudo_palette;
Antonino A. Daplas7914cb22006-06-26 00:26:32 -07002615 info->flags = FBINFO_DEFAULT |
2616 FBINFO_HWACCEL_IMAGEBLIT |
2617 FBINFO_HWACCEL_FILLRECT |
2618 FBINFO_HWACCEL_COPYAREA |
2619 FBINFO_HWACCEL_YPAN;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002620
2621#ifdef CONFIG_PMAC_BACKLIGHT
2622 if (M64_HAS(G3_PB_1_1) && machine_is_compatible("PowerBook1,1")) {
2623 /* these bits let the 101 powerbook wake up from sleep -- paulus */
2624 aty_st_lcd(POWER_MANAGEMENT, aty_ld_lcd(POWER_MANAGEMENT, par)
2625 | (USE_F32KHZ | TRISTATE_MEM_EN), par);
Michael Hanselmann5474c122006-06-25 05:47:08 -07002626 } else
2627#endif
2628 if (M64_HAS(MOBIL_BUS)) {
2629#ifdef CONFIG_FB_ATY_BACKLIGHT
2630 aty_bl_init (par);
2631#endif
2632 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07002633
2634 memset(&var, 0, sizeof(var));
2635#ifdef CONFIG_PPC
Benjamin Herrenschmidte8222502006-03-28 23:15:54 +11002636 if (machine_is(powermac)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07002637 /*
2638 * FIXME: The NVRAM stuff should be put in a Mac-specific file, as it
2639 * applies to all Mac video cards
2640 */
2641 if (mode) {
Antonino A. Daplas1013d262005-11-07 01:00:41 -08002642 if (mac_find_mode(&var, info, mode, 8))
2643 has_var = 1;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002644 } else {
2645 if (default_vmode == VMODE_CHOOSE) {
2646 if (M64_HAS(G3_PB_1024x768))
2647 /* G3 PowerBook with 1024x768 LCD */
2648 default_vmode = VMODE_1024_768_60;
2649 else if (machine_is_compatible("iMac"))
2650 default_vmode = VMODE_1024_768_75;
2651 else if (machine_is_compatible
2652 ("PowerBook2,1"))
2653 /* iBook with 800x600 LCD */
2654 default_vmode = VMODE_800_600_60;
2655 else
2656 default_vmode = VMODE_640_480_67;
2657 sense = read_aty_sense(par);
2658 PRINTKI("monitor sense=%x, mode %d\n",
2659 sense, mac_map_monitor_sense(sense));
2660 }
2661 if (default_vmode <= 0 || default_vmode > VMODE_MAX)
2662 default_vmode = VMODE_640_480_60;
2663 if (default_cmode < CMODE_8 || default_cmode > CMODE_32)
2664 default_cmode = CMODE_8;
Antonino A. Daplas1013d262005-11-07 01:00:41 -08002665 if (!mac_vmode_to_var(default_vmode, default_cmode,
2666 &var))
2667 has_var = 1;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002668 }
Antonino A. Daplas1013d262005-11-07 01:00:41 -08002669 }
2670
Linus Torvalds1da177e2005-04-16 15:20:36 -07002671#endif /* !CONFIG_PPC */
Antonino A. Daplas1013d262005-11-07 01:00:41 -08002672
2673#if defined(__i386__) && defined(CONFIG_FB_ATY_GENERIC_LCD)
2674 if (!atyfb_get_timings_from_lcd(par, &var))
2675 has_var = 1;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002676#endif
Antonino A. Daplas1013d262005-11-07 01:00:41 -08002677
2678 if (mode && fb_find_mode(&var, info, mode, NULL, 0, &defmode, 8))
2679 has_var = 1;
2680
2681 if (!has_var)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002682 var = default_var;
2683
2684 if (noaccel)
2685 var.accel_flags &= ~FB_ACCELF_TEXT;
2686 else
2687 var.accel_flags |= FB_ACCELF_TEXT;
2688
2689 if (comp_sync != -1) {
2690 if (!comp_sync)
2691 var.sync &= ~FB_SYNC_COMP_HIGH_ACT;
2692 else
2693 var.sync |= FB_SYNC_COMP_HIGH_ACT;
2694 }
2695
2696 if (var.yres == var.yres_virtual) {
2697 u32 videoram = (info->fix.smem_len - (PAGE_SIZE << 2));
2698 var.yres_virtual = ((videoram * 8) / var.bits_per_pixel) / var.xres_virtual;
2699 if (var.yres_virtual < var.yres)
2700 var.yres_virtual = var.yres;
2701 }
2702
2703 if (atyfb_check_var(&var, info)) {
2704 PRINTKE("can't set default video mode\n");
2705 goto aty_init_exit;
2706 }
2707
2708#ifdef __sparc__
2709 atyfb_save_palette(par, 0);
2710#endif
2711
2712#ifdef CONFIG_FB_ATY_CT
2713 if (!noaccel && M64_HAS(INTEGRATED))
2714 aty_init_cursor(info);
2715#endif /* CONFIG_FB_ATY_CT */
2716 info->var = var;
2717
2718 fb_alloc_cmap(&info->cmap, 256, 0);
2719
2720 if (register_framebuffer(info) < 0)
2721 goto aty_init_exit;
2722
2723 fb_list = info;
2724
2725 PRINTKI("fb%d: %s frame buffer device on %s\n",
2726 info->node, info->fix.id, name);
2727 return 0;
2728
2729aty_init_exit:
2730 /* restore video mode */
2731 aty_set_crtc(par, &saved_crtc);
2732 par->pll_ops->set_pll(info, &saved_pll);
2733
2734#ifdef CONFIG_MTRR
2735 if (par->mtrr_reg >= 0) {
2736 mtrr_del(par->mtrr_reg, 0, 0);
2737 par->mtrr_reg = -1;
2738 }
2739 if (par->mtrr_aper >= 0) {
2740 mtrr_del(par->mtrr_aper, 0, 0);
2741 par->mtrr_aper = -1;
2742 }
2743#endif
2744 return -1;
2745}
2746
2747#ifdef CONFIG_ATARI
2748static int __init store_video_par(char *video_str, unsigned char m64_num)
2749{
2750 char *p;
2751 unsigned long vmembase, size, guiregbase;
2752
2753 PRINTKI("store_video_par() '%s' \n", video_str);
2754
2755 if (!(p = strsep(&video_str, ";")) || !*p)
2756 goto mach64_invalid;
2757 vmembase = simple_strtoul(p, NULL, 0);
2758 if (!(p = strsep(&video_str, ";")) || !*p)
2759 goto mach64_invalid;
2760 size = simple_strtoul(p, NULL, 0);
2761 if (!(p = strsep(&video_str, ";")) || !*p)
2762 goto mach64_invalid;
2763 guiregbase = simple_strtoul(p, NULL, 0);
2764
2765 phys_vmembase[m64_num] = vmembase;
2766 phys_size[m64_num] = size;
2767 phys_guiregbase[m64_num] = guiregbase;
2768 PRINTKI("stored them all: $%08lX $%08lX $%08lX \n", vmembase, size,
2769 guiregbase);
2770 return 0;
2771
2772 mach64_invalid:
2773 phys_vmembase[m64_num] = 0;
2774 return -1;
2775}
2776#endif /* CONFIG_ATARI */
2777
2778 /*
2779 * Blank the display.
2780 */
2781
2782static int atyfb_blank(int blank, struct fb_info *info)
2783{
2784 struct atyfb_par *par = (struct atyfb_par *) info->par;
Ville Syrjälä480913f2006-01-09 20:53:28 -08002785 u32 gen_cntl;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002786
2787 if (par->lock_blank || par->asleep)
2788 return 0;
2789
2790#ifdef CONFIG_PMAC_BACKLIGHT
Michael Hanselmann5474c122006-06-25 05:47:08 -07002791 if (machine_is(powermac) && blank > FB_BLANK_NORMAL) {
2792 mutex_lock(&info->bl_mutex);
2793 if (info->bl_dev) {
2794 down(&info->bl_dev->sem);
2795 info->bl_dev->props->power = FB_BLANK_POWERDOWN;
2796 info->bl_dev->props->update_status(info->bl_dev);
2797 up(&info->bl_dev->sem);
2798 }
2799 mutex_unlock(&info->bl_mutex);
2800 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07002801#elif defined(CONFIG_FB_ATY_GENERIC_LCD)
Ville Syrjälä480913f2006-01-09 20:53:28 -08002802 if (par->lcd_table && blank > FB_BLANK_NORMAL &&
Linus Torvalds1da177e2005-04-16 15:20:36 -07002803 (aty_ld_lcd(LCD_GEN_CNTL, par) & LCD_ON)) {
2804 u32 pm = aty_ld_lcd(POWER_MANAGEMENT, par);
2805 pm &= ~PWR_BLON;
2806 aty_st_lcd(POWER_MANAGEMENT, pm, par);
2807 }
2808#endif
2809
Ville Syrjälä480913f2006-01-09 20:53:28 -08002810 gen_cntl = aty_ld_le32(CRTC_GEN_CNTL, par);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002811 switch (blank) {
2812 case FB_BLANK_UNBLANK:
Ville Syrjälä480913f2006-01-09 20:53:28 -08002813 gen_cntl &= ~0x400004c;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002814 break;
2815 case FB_BLANK_NORMAL:
Ville Syrjälä480913f2006-01-09 20:53:28 -08002816 gen_cntl |= 0x4000040;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002817 break;
2818 case FB_BLANK_VSYNC_SUSPEND:
Ville Syrjälä480913f2006-01-09 20:53:28 -08002819 gen_cntl |= 0x4000048;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002820 break;
2821 case FB_BLANK_HSYNC_SUSPEND:
Ville Syrjälä480913f2006-01-09 20:53:28 -08002822 gen_cntl |= 0x4000044;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002823 break;
2824 case FB_BLANK_POWERDOWN:
Ville Syrjälä480913f2006-01-09 20:53:28 -08002825 gen_cntl |= 0x400004c;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002826 break;
2827 }
Ville Syrjälä480913f2006-01-09 20:53:28 -08002828 aty_st_le32(CRTC_GEN_CNTL, gen_cntl, par);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002829
2830#ifdef CONFIG_PMAC_BACKLIGHT
Michael Hanselmann5474c122006-06-25 05:47:08 -07002831 if (machine_is(powermac) && blank <= FB_BLANK_NORMAL) {
2832 mutex_lock(&info->bl_mutex);
2833 if (info->bl_dev) {
2834 down(&info->bl_dev->sem);
2835 info->bl_dev->props->power = FB_BLANK_UNBLANK;
2836 info->bl_dev->props->update_status(info->bl_dev);
2837 up(&info->bl_dev->sem);
2838 }
2839 mutex_unlock(&info->bl_mutex);
2840 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07002841#elif defined(CONFIG_FB_ATY_GENERIC_LCD)
Ville Syrjälä480913f2006-01-09 20:53:28 -08002842 if (par->lcd_table && blank <= FB_BLANK_NORMAL &&
Linus Torvalds1da177e2005-04-16 15:20:36 -07002843 (aty_ld_lcd(LCD_GEN_CNTL, par) & LCD_ON)) {
2844 u32 pm = aty_ld_lcd(POWER_MANAGEMENT, par);
2845 pm |= PWR_BLON;
2846 aty_st_lcd(POWER_MANAGEMENT, pm, par);
2847 }
2848#endif
2849
2850 return 0;
2851}
2852
2853static void aty_st_pal(u_int regno, u_int red, u_int green, u_int blue,
2854 const struct atyfb_par *par)
2855{
2856#ifdef CONFIG_ATARI
2857 out_8(&par->aty_cmap_regs->windex, regno);
2858 out_8(&par->aty_cmap_regs->lut, red);
2859 out_8(&par->aty_cmap_regs->lut, green);
2860 out_8(&par->aty_cmap_regs->lut, blue);
2861#else
2862 writeb(regno, &par->aty_cmap_regs->windex);
2863 writeb(red, &par->aty_cmap_regs->lut);
2864 writeb(green, &par->aty_cmap_regs->lut);
2865 writeb(blue, &par->aty_cmap_regs->lut);
2866#endif
2867}
2868
2869 /*
2870 * Set a single color register. The values supplied are already
2871 * rounded down to the hardware's capabilities (according to the
2872 * entries in the var structure). Return != 0 for invalid regno.
2873 * !! 4 & 8 = PSEUDO, > 8 = DIRECTCOLOR
2874 */
2875
2876static int atyfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
2877 u_int transp, struct fb_info *info)
2878{
2879 struct atyfb_par *par = (struct atyfb_par *) info->par;
2880 int i, depth;
2881 u32 *pal = info->pseudo_palette;
2882
2883 depth = info->var.bits_per_pixel;
2884 if (depth == 16)
2885 depth = (info->var.green.length == 5) ? 15 : 16;
2886
2887 if (par->asleep)
2888 return 0;
2889
2890 if (regno > 255 ||
2891 (depth == 16 && regno > 63) ||
2892 (depth == 15 && regno > 31))
2893 return 1;
2894
2895 red >>= 8;
2896 green >>= 8;
2897 blue >>= 8;
2898
2899 par->palette[regno].red = red;
2900 par->palette[regno].green = green;
2901 par->palette[regno].blue = blue;
2902
2903 if (regno < 16) {
2904 switch (depth) {
2905 case 15:
2906 pal[regno] = (regno << 10) | (regno << 5) | regno;
2907 break;
2908 case 16:
2909 pal[regno] = (regno << 11) | (regno << 5) | regno;
2910 break;
2911 case 24:
2912 pal[regno] = (regno << 16) | (regno << 8) | regno;
2913 break;
2914 case 32:
2915 i = (regno << 8) | regno;
2916 pal[regno] = (i << 16) | i;
2917 break;
2918 }
2919 }
2920
2921 i = aty_ld_8(DAC_CNTL, par) & 0xfc;
2922 if (M64_HAS(EXTRA_BRIGHT))
2923 i |= 0x2; /* DAC_CNTL | 0x2 turns off the extra brightness for gt */
2924 aty_st_8(DAC_CNTL, i, par);
2925 aty_st_8(DAC_MASK, 0xff, par);
2926
2927 if (M64_HAS(INTEGRATED)) {
2928 if (depth == 16) {
2929 if (regno < 32)
2930 aty_st_pal(regno << 3, red,
2931 par->palette[regno<<1].green,
2932 blue, par);
2933 red = par->palette[regno>>1].red;
2934 blue = par->palette[regno>>1].blue;
2935 regno <<= 2;
2936 } else if (depth == 15) {
2937 regno <<= 3;
2938 for(i = 0; i < 8; i++) {
2939 aty_st_pal(regno + i, red, green, blue, par);
2940 }
2941 }
2942 }
2943 aty_st_pal(regno, red, green, blue, par);
2944
2945 return 0;
2946}
2947
2948#ifdef CONFIG_PCI
2949
2950#ifdef __sparc__
2951
2952extern void (*prom_palette) (int);
2953
2954static int __devinit atyfb_setup_sparc(struct pci_dev *pdev,
2955 struct fb_info *info, unsigned long addr)
2956{
2957 extern int con_is_present(void);
2958
2959 struct atyfb_par *par = info->par;
2960 struct pcidev_cookie *pcp;
2961 char prop[128];
2962 int node, len, i, j, ret;
2963 u32 mem, chip_id;
2964
2965 /* Do not attach when we have a serial console. */
2966 if (!con_is_present())
2967 return -ENXIO;
2968
2969 /*
2970 * Map memory-mapped registers.
2971 */
2972 par->ati_regbase = (void *)addr + 0x7ffc00UL;
2973 info->fix.mmio_start = addr + 0x7ffc00UL;
2974
2975 /*
2976 * Map in big-endian aperture.
2977 */
2978 info->screen_base = (char *) (addr + 0x800000UL);
2979 info->fix.smem_start = addr + 0x800000UL;
2980
2981 /*
2982 * Figure mmap addresses from PCI config space.
2983 * Split Framebuffer in big- and little-endian halfs.
2984 */
2985 for (i = 0; i < 6 && pdev->resource[i].start; i++)
2986 /* nothing */ ;
2987 j = i + 4;
2988
2989 par->mmap_map = kmalloc(j * sizeof(*par->mmap_map), GFP_ATOMIC);
2990 if (!par->mmap_map) {
2991 PRINTKE("atyfb_setup_sparc() can't alloc mmap_map\n");
2992 return -ENOMEM;
2993 }
2994 memset(par->mmap_map, 0, j * sizeof(*par->mmap_map));
2995
2996 for (i = 0, j = 2; i < 6 && pdev->resource[i].start; i++) {
2997 struct resource *rp = &pdev->resource[i];
2998 int io, breg = PCI_BASE_ADDRESS_0 + (i << 2);
2999 unsigned long base;
3000 u32 size, pbase;
3001
3002 base = rp->start;
3003
3004 io = (rp->flags & IORESOURCE_IO);
3005
3006 size = rp->end - base + 1;
3007
3008 pci_read_config_dword(pdev, breg, &pbase);
3009
3010 if (io)
3011 size &= ~1;
3012
3013 /*
3014 * Map the framebuffer a second time, this time without
3015 * the braindead _PAGE_IE setting. This is used by the
3016 * fixed Xserver, but we need to maintain the old mapping
3017 * to stay compatible with older ones...
3018 */
3019 if (base == addr) {
3020 par->mmap_map[j].voff = (pbase + 0x10000000) & PAGE_MASK;
3021 par->mmap_map[j].poff = base & PAGE_MASK;
3022 par->mmap_map[j].size = (size + ~PAGE_MASK) & PAGE_MASK;
3023 par->mmap_map[j].prot_mask = _PAGE_CACHE;
3024 par->mmap_map[j].prot_flag = _PAGE_E;
3025 j++;
3026 }
3027
3028 /*
3029 * Here comes the old framebuffer mapping with _PAGE_IE
3030 * set for the big endian half of the framebuffer...
3031 */
3032 if (base == addr) {
3033 par->mmap_map[j].voff = (pbase + 0x800000) & PAGE_MASK;
3034 par->mmap_map[j].poff = (base + 0x800000) & PAGE_MASK;
3035 par->mmap_map[j].size = 0x800000;
3036 par->mmap_map[j].prot_mask = _PAGE_CACHE;
3037 par->mmap_map[j].prot_flag = _PAGE_E | _PAGE_IE;
3038 size -= 0x800000;
3039 j++;
3040 }
3041
3042 par->mmap_map[j].voff = pbase & PAGE_MASK;
3043 par->mmap_map[j].poff = base & PAGE_MASK;
3044 par->mmap_map[j].size = (size + ~PAGE_MASK) & PAGE_MASK;
3045 par->mmap_map[j].prot_mask = _PAGE_CACHE;
3046 par->mmap_map[j].prot_flag = _PAGE_E;
3047 j++;
3048 }
3049
3050 if((ret = correct_chipset(par)))
3051 return ret;
3052
3053 if (IS_XL(pdev->device)) {
3054 /*
3055 * Fix PROMs idea of MEM_CNTL settings...
3056 */
3057 mem = aty_ld_le32(MEM_CNTL, par);
3058 chip_id = aty_ld_le32(CONFIG_CHIP_ID, par);
3059 if (((chip_id & CFG_CHIP_TYPE) == VT_CHIP_ID) && !((chip_id >> 24) & 1)) {
3060 switch (mem & 0x0f) {
3061 case 3:
3062 mem = (mem & ~(0x0f)) | 2;
3063 break;
3064 case 7:
3065 mem = (mem & ~(0x0f)) | 3;
3066 break;
3067 case 9:
3068 mem = (mem & ~(0x0f)) | 4;
3069 break;
3070 case 11:
3071 mem = (mem & ~(0x0f)) | 5;
3072 break;
3073 default:
3074 break;
3075 }
3076 if ((aty_ld_le32(CONFIG_STAT0, par) & 7) >= SDRAM)
3077 mem &= ~(0x00700000);
3078 }
3079 mem &= ~(0xcf80e000); /* Turn off all undocumented bits. */
3080 aty_st_le32(MEM_CNTL, mem, par);
3081 }
3082
3083 /*
3084 * If this is the console device, we will set default video
3085 * settings to what the PROM left us with.
3086 */
3087 node = prom_getchild(prom_root_node);
3088 node = prom_searchsiblings(node, "aliases");
3089 if (node) {
3090 len = prom_getproperty(node, "screen", prop, sizeof(prop));
3091 if (len > 0) {
3092 prop[len] = '\0';
3093 node = prom_finddevice(prop);
3094 } else
3095 node = 0;
3096 }
3097
3098 pcp = pdev->sysdata;
David S. Millerde8d28b2006-06-22 16:18:54 -07003099 if (node == pcp->prom_node->node) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07003100 struct fb_var_screeninfo *var = &default_var;
3101 unsigned int N, P, Q, M, T, R;
3102 u32 v_total, h_total;
3103 struct crtc crtc;
3104 u8 pll_regs[16];
3105 u8 clock_cntl;
3106
3107 crtc.vxres = prom_getintdefault(node, "width", 1024);
3108 crtc.vyres = prom_getintdefault(node, "height", 768);
3109 var->bits_per_pixel = prom_getintdefault(node, "depth", 8);
3110 var->xoffset = var->yoffset = 0;
3111 crtc.h_tot_disp = aty_ld_le32(CRTC_H_TOTAL_DISP, par);
3112 crtc.h_sync_strt_wid = aty_ld_le32(CRTC_H_SYNC_STRT_WID, par);
3113 crtc.v_tot_disp = aty_ld_le32(CRTC_V_TOTAL_DISP, par);
3114 crtc.v_sync_strt_wid = aty_ld_le32(CRTC_V_SYNC_STRT_WID, par);
3115 crtc.gen_cntl = aty_ld_le32(CRTC_GEN_CNTL, par);
3116 aty_crtc_to_var(&crtc, var);
3117
3118 h_total = var->xres + var->right_margin + var->hsync_len + var->left_margin;
3119 v_total = var->yres + var->lower_margin + var->vsync_len + var->upper_margin;
3120
3121 /*
3122 * Read the PLL to figure actual Refresh Rate.
3123 */
3124 clock_cntl = aty_ld_8(CLOCK_CNTL, par);
3125 /* DPRINTK("CLOCK_CNTL %02x\n", clock_cntl); */
3126 for (i = 0; i < 16; i++)
3127 pll_regs[i] = aty_ld_pll_ct(i, par);
3128
3129 /*
3130 * PLL Reference Divider M:
3131 */
3132 M = pll_regs[2];
3133
3134 /*
3135 * PLL Feedback Divider N (Dependant on CLOCK_CNTL):
3136 */
3137 N = pll_regs[7 + (clock_cntl & 3)];
3138
3139 /*
3140 * PLL Post Divider P (Dependant on CLOCK_CNTL):
3141 */
3142 P = 1 << (pll_regs[6] >> ((clock_cntl & 3) << 1));
3143
3144 /*
3145 * PLL Divider Q:
3146 */
3147 Q = N / P;
3148
3149 /*
3150 * Target Frequency:
3151 *
3152 * T * M
3153 * Q = -------
3154 * 2 * R
3155 *
3156 * where R is XTALIN (= 14318 or 29498 kHz).
3157 */
3158 if (IS_XL(pdev->device))
3159 R = 29498;
3160 else
3161 R = 14318;
3162
3163 T = 2 * Q * R / M;
3164
3165 default_var.pixclock = 1000000000 / T;
3166 }
3167
3168 return 0;
3169}
3170
3171#else /* __sparc__ */
3172
3173#ifdef __i386__
3174#ifdef CONFIG_FB_ATY_GENERIC_LCD
3175static void aty_init_lcd(struct atyfb_par *par, u32 bios_base)
3176{
3177 u32 driv_inf_tab, sig;
3178 u16 lcd_ofs;
3179
3180 /* To support an LCD panel, we should know it's dimensions and
3181 * it's desired pixel clock.
3182 * There are two ways to do it:
3183 * - Check the startup video mode and calculate the panel
3184 * size from it. This is unreliable.
3185 * - Read it from the driver information table in the video BIOS.
3186 */
3187 /* Address of driver information table is at offset 0x78. */
3188 driv_inf_tab = bios_base + *((u16 *)(bios_base+0x78));
3189
3190 /* Check for the driver information table signature. */
3191 sig = (*(u32 *)driv_inf_tab);
3192 if ((sig == 0x54504c24) || /* Rage LT pro */
3193 (sig == 0x544d5224) || /* Rage mobility */
3194 (sig == 0x54435824) || /* Rage XC */
3195 (sig == 0x544c5824)) { /* Rage XL */
3196 PRINTKI("BIOS contains driver information table.\n");
3197 lcd_ofs = (*(u16 *)(driv_inf_tab + 10));
3198 par->lcd_table = 0;
3199 if (lcd_ofs != 0) {
3200 par->lcd_table = bios_base + lcd_ofs;
3201 }
3202 }
3203
3204 if (par->lcd_table != 0) {
3205 char model[24];
3206 char strbuf[16];
3207 char refresh_rates_buf[100];
3208 int id, tech, f, i, m, default_refresh_rate;
3209 char *txtcolour;
3210 char *txtmonitor;
3211 char *txtdual;
3212 char *txtformat;
3213 u16 width, height, panel_type, refresh_rates;
3214 u16 *lcdmodeptr;
3215 u32 format;
3216 u8 lcd_refresh_rates[16] = {50,56,60,67,70,72,75,76,85,90,100,120,140,150,160,200};
3217 /* The most important information is the panel size at
3218 * offset 25 and 27, but there's some other nice information
3219 * which we print to the screen.
3220 */
3221 id = *(u8 *)par->lcd_table;
3222 strncpy(model,(char *)par->lcd_table+1,24);
3223 model[23]=0;
3224
3225 width = par->lcd_width = *(u16 *)(par->lcd_table+25);
3226 height = par->lcd_height = *(u16 *)(par->lcd_table+27);
3227 panel_type = *(u16 *)(par->lcd_table+29);
3228 if (panel_type & 1)
3229 txtcolour = "colour";
3230 else
3231 txtcolour = "monochrome";
3232 if (panel_type & 2)
3233 txtdual = "dual (split) ";
3234 else
3235 txtdual = "";
3236 tech = (panel_type>>2) & 63;
3237 switch (tech) {
3238 case 0:
3239 txtmonitor = "passive matrix";
3240 break;
3241 case 1:
3242 txtmonitor = "active matrix";
3243 break;
3244 case 2:
3245 txtmonitor = "active addressed STN";
3246 break;
3247 case 3:
3248 txtmonitor = "EL";
3249 break;
3250 case 4:
3251 txtmonitor = "plasma";
3252 break;
3253 default:
3254 txtmonitor = "unknown";
3255 }
3256 format = *(u32 *)(par->lcd_table+57);
3257 if (tech == 0 || tech == 2) {
3258 switch (format & 7) {
3259 case 0:
3260 txtformat = "12 bit interface";
3261 break;
3262 case 1:
3263 txtformat = "16 bit interface";
3264 break;
3265 case 2:
3266 txtformat = "24 bit interface";
3267 break;
3268 default:
3269 txtformat = "unkown format";
3270 }
3271 } else {
3272 switch (format & 7) {
3273 case 0:
3274 txtformat = "8 colours";
3275 break;
3276 case 1:
3277 txtformat = "512 colours";
3278 break;
3279 case 2:
3280 txtformat = "4096 colours";
3281 break;
3282 case 4:
3283 txtformat = "262144 colours (LT mode)";
3284 break;
3285 case 5:
3286 txtformat = "16777216 colours";
3287 break;
3288 case 6:
3289 txtformat = "262144 colours (FDPI-2 mode)";
3290 break;
3291 default:
3292 txtformat = "unkown format";
3293 }
3294 }
3295 PRINTKI("%s%s %s monitor detected: %s\n",
3296 txtdual ,txtcolour, txtmonitor, model);
3297 PRINTKI(" id=%d, %dx%d pixels, %s\n",
3298 id, width, height, txtformat);
3299 refresh_rates_buf[0] = 0;
3300 refresh_rates = *(u16 *)(par->lcd_table+62);
3301 m = 1;
3302 f = 0;
3303 for (i=0;i<16;i++) {
3304 if (refresh_rates & m) {
3305 if (f == 0) {
3306 sprintf(strbuf, "%d", lcd_refresh_rates[i]);
3307 f++;
3308 } else {
3309 sprintf(strbuf, ",%d", lcd_refresh_rates[i]);
3310 }
3311 strcat(refresh_rates_buf,strbuf);
3312 }
3313 m = m << 1;
3314 }
3315 default_refresh_rate = (*(u8 *)(par->lcd_table+61) & 0xf0) >> 4;
3316 PRINTKI(" supports refresh rates [%s], default %d Hz\n",
3317 refresh_rates_buf, lcd_refresh_rates[default_refresh_rate]);
3318 par->lcd_refreshrate = lcd_refresh_rates[default_refresh_rate];
3319 /* We now need to determine the crtc parameters for the
Ville Syrjäläcd4617b2006-01-09 20:53:21 -08003320 * LCD monitor. This is tricky, because they are not stored
Linus Torvalds1da177e2005-04-16 15:20:36 -07003321 * individually in the BIOS. Instead, the BIOS contains a
3322 * table of display modes that work for this monitor.
3323 *
3324 * The idea is that we search for a mode of the same dimensions
Ville Syrjäläcd4617b2006-01-09 20:53:21 -08003325 * as the dimensions of the LCD monitor. Say our LCD monitor
Linus Torvalds1da177e2005-04-16 15:20:36 -07003326 * is 800x600 pixels, we search for a 800x600 monitor.
3327 * The CRTC parameters we find here are the ones that we need
Ville Syrjäläcd4617b2006-01-09 20:53:21 -08003328 * to use to simulate other resolutions on the LCD screen.
Linus Torvalds1da177e2005-04-16 15:20:36 -07003329 */
3330 lcdmodeptr = (u16 *)(par->lcd_table + 64);
3331 while (*lcdmodeptr != 0) {
3332 u32 modeptr;
3333 u16 mwidth, mheight, lcd_hsync_start, lcd_vsync_start;
3334 modeptr = bios_base + *lcdmodeptr;
3335
3336 mwidth = *((u16 *)(modeptr+0));
3337 mheight = *((u16 *)(modeptr+2));
3338
3339 if (mwidth == width && mheight == height) {
3340 par->lcd_pixclock = 100000000 / *((u16 *)(modeptr+9));
3341 par->lcd_htotal = *((u16 *)(modeptr+17)) & 511;
3342 par->lcd_hdisp = *((u16 *)(modeptr+19)) & 511;
3343 lcd_hsync_start = *((u16 *)(modeptr+21)) & 511;
3344 par->lcd_hsync_dly = (*((u16 *)(modeptr+21)) >> 9) & 7;
3345 par->lcd_hsync_len = *((u8 *)(modeptr+23)) & 63;
3346
3347 par->lcd_vtotal = *((u16 *)(modeptr+24)) & 2047;
3348 par->lcd_vdisp = *((u16 *)(modeptr+26)) & 2047;
3349 lcd_vsync_start = *((u16 *)(modeptr+28)) & 2047;
3350 par->lcd_vsync_len = (*((u16 *)(modeptr+28)) >> 11) & 31;
3351
3352 par->lcd_htotal = (par->lcd_htotal + 1) * 8;
3353 par->lcd_hdisp = (par->lcd_hdisp + 1) * 8;
3354 lcd_hsync_start = (lcd_hsync_start + 1) * 8;
3355 par->lcd_hsync_len = par->lcd_hsync_len * 8;
3356
3357 par->lcd_vtotal++;
3358 par->lcd_vdisp++;
3359 lcd_vsync_start++;
3360
3361 par->lcd_right_margin = lcd_hsync_start - par->lcd_hdisp;
3362 par->lcd_lower_margin = lcd_vsync_start - par->lcd_vdisp;
3363 par->lcd_hblank_len = par->lcd_htotal - par->lcd_hdisp;
3364 par->lcd_vblank_len = par->lcd_vtotal - par->lcd_vdisp;
3365 break;
3366 }
3367
3368 lcdmodeptr++;
3369 }
3370 if (*lcdmodeptr == 0) {
3371 PRINTKE("LCD monitor CRTC parameters not found!!!\n");
3372 /* To do: Switch to CRT if possible. */
3373 } else {
3374 PRINTKI(" LCD CRTC parameters: %d.%d %d %d %d %d %d %d %d %d\n",
3375 1000000 / par->lcd_pixclock, 1000000 % par->lcd_pixclock,
3376 par->lcd_hdisp,
3377 par->lcd_hdisp + par->lcd_right_margin,
3378 par->lcd_hdisp + par->lcd_right_margin
3379 + par->lcd_hsync_dly + par->lcd_hsync_len,
3380 par->lcd_htotal,
3381 par->lcd_vdisp,
3382 par->lcd_vdisp + par->lcd_lower_margin,
3383 par->lcd_vdisp + par->lcd_lower_margin + par->lcd_vsync_len,
3384 par->lcd_vtotal);
3385 PRINTKI(" : %d %d %d %d %d %d %d %d %d\n",
3386 par->lcd_pixclock,
3387 par->lcd_hblank_len - (par->lcd_right_margin +
3388 par->lcd_hsync_dly + par->lcd_hsync_len),
3389 par->lcd_hdisp,
3390 par->lcd_right_margin,
3391 par->lcd_hsync_len,
3392 par->lcd_vblank_len - (par->lcd_lower_margin + par->lcd_vsync_len),
3393 par->lcd_vdisp,
3394 par->lcd_lower_margin,
3395 par->lcd_vsync_len);
3396 }
3397 }
3398}
3399#endif /* CONFIG_FB_ATY_GENERIC_LCD */
3400
3401static int __devinit init_from_bios(struct atyfb_par *par)
3402{
3403 u32 bios_base, rom_addr;
3404 int ret;
3405
3406 rom_addr = 0xc0000 + ((aty_ld_le32(SCRATCH_REG1, par) & 0x7f) << 11);
3407 bios_base = (unsigned long)ioremap(rom_addr, 0x10000);
3408
3409 /* The BIOS starts with 0xaa55. */
3410 if (*((u16 *)bios_base) == 0xaa55) {
3411
3412 u8 *bios_ptr;
3413 u16 rom_table_offset, freq_table_offset;
3414 PLL_BLOCK_MACH64 pll_block;
3415
3416 PRINTKI("Mach64 BIOS is located at %x, mapped at %x.\n", rom_addr, bios_base);
3417
3418 /* check for frequncy table */
3419 bios_ptr = (u8*)bios_base;
3420 rom_table_offset = (u16)(bios_ptr[0x48] | (bios_ptr[0x49] << 8));
3421 freq_table_offset = bios_ptr[rom_table_offset + 16] | (bios_ptr[rom_table_offset + 17] << 8);
3422 memcpy(&pll_block, bios_ptr + freq_table_offset, sizeof(PLL_BLOCK_MACH64));
3423
3424 PRINTKI("BIOS frequency table:\n");
3425 PRINTKI("PCLK_min_freq %d, PCLK_max_freq %d, ref_freq %d, ref_divider %d\n",
3426 pll_block.PCLK_min_freq, pll_block.PCLK_max_freq,
3427 pll_block.ref_freq, pll_block.ref_divider);
3428 PRINTKI("MCLK_pwd %d, MCLK_max_freq %d, XCLK_max_freq %d, SCLK_freq %d\n",
3429 pll_block.MCLK_pwd, pll_block.MCLK_max_freq,
3430 pll_block.XCLK_max_freq, pll_block.SCLK_freq);
3431
3432 par->pll_limits.pll_min = pll_block.PCLK_min_freq/100;
3433 par->pll_limits.pll_max = pll_block.PCLK_max_freq/100;
3434 par->pll_limits.ref_clk = pll_block.ref_freq/100;
3435 par->pll_limits.ref_div = pll_block.ref_divider;
3436 par->pll_limits.sclk = pll_block.SCLK_freq/100;
3437 par->pll_limits.mclk = pll_block.MCLK_max_freq/100;
3438 par->pll_limits.mclk_pm = pll_block.MCLK_pwd/100;
3439 par->pll_limits.xclk = pll_block.XCLK_max_freq/100;
3440#ifdef CONFIG_FB_ATY_GENERIC_LCD
3441 aty_init_lcd(par, bios_base);
3442#endif
3443 ret = 0;
3444 } else {
3445 PRINTKE("no BIOS frequency table found, use parameters\n");
3446 ret = -ENXIO;
3447 }
3448 iounmap((void* __iomem )bios_base);
3449
3450 return ret;
3451}
3452#endif /* __i386__ */
3453
3454static int __devinit atyfb_setup_generic(struct pci_dev *pdev, struct fb_info *info, unsigned long addr)
3455{
3456 struct atyfb_par *par = info->par;
3457 u16 tmp;
3458 unsigned long raddr;
3459 struct resource *rrp;
3460 int ret = 0;
3461
3462 raddr = addr + 0x7ff000UL;
3463 rrp = &pdev->resource[2];
3464 if ((rrp->flags & IORESOURCE_MEM) && request_mem_region(rrp->start, rrp->end - rrp->start + 1, "atyfb")) {
3465 par->aux_start = rrp->start;
3466 par->aux_size = rrp->end - rrp->start + 1;
3467 raddr = rrp->start;
3468 PRINTKI("using auxiliary register aperture\n");
3469 }
3470
3471 info->fix.mmio_start = raddr;
3472 par->ati_regbase = ioremap(info->fix.mmio_start, 0x1000);
3473 if (par->ati_regbase == 0)
3474 return -ENOMEM;
3475
3476 info->fix.mmio_start += par->aux_start ? 0x400 : 0xc00;
3477 par->ati_regbase += par->aux_start ? 0x400 : 0xc00;
3478
3479 /*
3480 * Enable memory-space accesses using config-space
3481 * command register.
3482 */
3483 pci_read_config_word(pdev, PCI_COMMAND, &tmp);
3484 if (!(tmp & PCI_COMMAND_MEMORY)) {
3485 tmp |= PCI_COMMAND_MEMORY;
3486 pci_write_config_word(pdev, PCI_COMMAND, tmp);
3487 }
3488#ifdef __BIG_ENDIAN
3489 /* Use the big-endian aperture */
3490 addr += 0x800000;
3491#endif
3492
3493 /* Map in frame buffer */
3494 info->fix.smem_start = addr;
3495 info->screen_base = ioremap(addr, 0x800000);
3496 if (info->screen_base == NULL) {
3497 ret = -ENOMEM;
3498 goto atyfb_setup_generic_fail;
3499 }
3500
3501 if((ret = correct_chipset(par)))
3502 goto atyfb_setup_generic_fail;
3503#ifdef __i386__
3504 if((ret = init_from_bios(par)))
3505 goto atyfb_setup_generic_fail;
3506#endif
3507 if (!(aty_ld_le32(CRTC_GEN_CNTL, par) & CRTC_EXT_DISP_EN))
3508 par->clk_wr_offset = (inb(R_GENMO) & 0x0CU) >> 2;
3509 else
3510 par->clk_wr_offset = aty_ld_8(CLOCK_CNTL, par) & 0x03U;
3511
3512 /* according to ATI, we should use clock 3 for acelerated mode */
3513 par->clk_wr_offset = 3;
3514
3515 return 0;
3516
3517atyfb_setup_generic_fail:
3518 iounmap(par->ati_regbase);
3519 par->ati_regbase = NULL;
3520 return ret;
3521}
3522
3523#endif /* !__sparc__ */
3524
3525static int __devinit atyfb_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
3526{
3527 unsigned long addr, res_start, res_size;
3528 struct fb_info *info;
3529 struct resource *rp;
3530 struct atyfb_par *par;
3531 int i, rc = -ENOMEM;
3532
Adrian Bunk9ec85c02006-04-10 22:55:45 -07003533 for (i = ARRAY_SIZE(aty_chips) - 1; i >= 0; i--)
Linus Torvalds1da177e2005-04-16 15:20:36 -07003534 if (pdev->device == aty_chips[i].pci_id)
3535 break;
3536
3537 if (i < 0)
3538 return -ENODEV;
3539
3540 /* Enable device in PCI config */
3541 if (pci_enable_device(pdev)) {
3542 PRINTKE("Cannot enable PCI device\n");
3543 return -ENXIO;
3544 }
3545
3546 /* Find which resource to use */
3547 rp = &pdev->resource[0];
3548 if (rp->flags & IORESOURCE_IO)
3549 rp = &pdev->resource[1];
3550 addr = rp->start;
3551 if (!addr)
3552 return -ENXIO;
3553
3554 /* Reserve space */
3555 res_start = rp->start;
3556 res_size = rp->end - rp->start + 1;
3557 if (!request_mem_region (res_start, res_size, "atyfb"))
3558 return -EBUSY;
3559
3560 /* Allocate framebuffer */
3561 info = framebuffer_alloc(sizeof(struct atyfb_par), &pdev->dev);
3562 if (!info) {
3563 PRINTKE("atyfb_pci_probe() can't alloc fb_info\n");
3564 return -ENOMEM;
3565 }
3566 par = info->par;
3567 info->fix = atyfb_fix;
3568 info->device = &pdev->dev;
3569 par->pci_id = aty_chips[i].pci_id;
3570 par->res_start = res_start;
3571 par->res_size = res_size;
3572 par->irq = pdev->irq;
Michael Hanselmann5474c122006-06-25 05:47:08 -07003573 par->pdev = pdev;
Linus Torvalds1da177e2005-04-16 15:20:36 -07003574
3575 /* Setup "info" structure */
3576#ifdef __sparc__
3577 rc = atyfb_setup_sparc(pdev, info, addr);
3578#else
3579 rc = atyfb_setup_generic(pdev, info, addr);
3580#endif
3581 if (rc)
3582 goto err_release_mem;
3583
3584 pci_set_drvdata(pdev, info);
3585
3586 /* Init chip & register framebuffer */
3587 if (aty_init(info, "PCI"))
3588 goto err_release_io;
3589
3590#ifdef __sparc__
3591 if (!prom_palette)
3592 prom_palette = atyfb_palette;
3593
3594 /*
3595 * Add /dev/fb mmap values.
3596 */
3597 par->mmap_map[0].voff = 0x8000000000000000UL;
3598 par->mmap_map[0].poff = (unsigned long) info->screen_base & PAGE_MASK;
3599 par->mmap_map[0].size = info->fix.smem_len;
3600 par->mmap_map[0].prot_mask = _PAGE_CACHE;
3601 par->mmap_map[0].prot_flag = _PAGE_E;
3602 par->mmap_map[1].voff = par->mmap_map[0].voff + info->fix.smem_len;
3603 par->mmap_map[1].poff = (long)par->ati_regbase & PAGE_MASK;
3604 par->mmap_map[1].size = PAGE_SIZE;
3605 par->mmap_map[1].prot_mask = _PAGE_CACHE;
3606 par->mmap_map[1].prot_flag = _PAGE_E;
3607#endif /* __sparc__ */
3608
3609 return 0;
3610
3611err_release_io:
3612#ifdef __sparc__
3613 kfree(par->mmap_map);
3614#else
3615 if (par->ati_regbase)
3616 iounmap(par->ati_regbase);
3617 if (info->screen_base)
3618 iounmap(info->screen_base);
3619#endif
3620err_release_mem:
3621 if (par->aux_start)
3622 release_mem_region(par->aux_start, par->aux_size);
3623
3624 release_mem_region(par->res_start, par->res_size);
3625 framebuffer_release(info);
3626
3627 return rc;
3628}
3629
3630#endif /* CONFIG_PCI */
3631
3632#ifdef CONFIG_ATARI
3633
3634static int __devinit atyfb_atari_probe(void)
3635{
Al Virocef46b12006-01-12 01:06:13 -08003636 struct atyfb_par *par;
Linus Torvalds1da177e2005-04-16 15:20:36 -07003637 struct fb_info *info;
3638 int m64_num;
3639 u32 clock_r;
3640
3641 for (m64_num = 0; m64_num < mach64_count; m64_num++) {
3642 if (!phys_vmembase[m64_num] || !phys_size[m64_num] ||
3643 !phys_guiregbase[m64_num]) {
3644 PRINTKI("phys_*[%d] parameters not set => returning early. \n", m64_num);
3645 continue;
3646 }
3647
3648 info = framebuffer_alloc(sizeof(struct atyfb_par), NULL);
3649 if (!info) {
3650 PRINTKE("atyfb_atari_probe() can't alloc fb_info\n");
3651 return -ENOMEM;
3652 }
3653 par = info->par;
3654
3655 info->fix = atyfb_fix;
3656
3657 par->irq = (unsigned int) -1; /* something invalid */
3658
3659 /*
3660 * Map the video memory (physical address given) to somewhere in the
3661 * kernel address space.
3662 */
3663 info->screen_base = ioremap(phys_vmembase[m64_num], phys_size[m64_num]);
3664 info->fix.smem_start = (unsigned long)info->screen_base; /* Fake! */
3665 par->ati_regbase = ioremap(phys_guiregbase[m64_num], 0x10000) +
3666 0xFC00ul;
3667 info->fix.mmio_start = (unsigned long)par->ati_regbase; /* Fake! */
3668
3669 aty_st_le32(CLOCK_CNTL, 0x12345678, par);
3670 clock_r = aty_ld_le32(CLOCK_CNTL, par);
3671
3672 switch (clock_r & 0x003F) {
3673 case 0x12:
3674 par->clk_wr_offset = 3; /* */
3675 break;
3676 case 0x34:
3677 par->clk_wr_offset = 2; /* Medusa ST-IO ISA Adapter etc. */
3678 break;
3679 case 0x16:
3680 par->clk_wr_offset = 1; /* */
3681 break;
3682 case 0x38:
3683 par->clk_wr_offset = 0; /* Panther 1 ISA Adapter (Gerald) */
3684 break;
3685 }
3686
3687 if (aty_init(info, "ISA bus")) {
3688 framebuffer_release(info);
3689 /* This is insufficient! kernel_map has added two large chunks!! */
3690 return -ENXIO;
3691 }
3692 }
3693}
3694
3695#endif /* CONFIG_ATARI */
3696
3697static void __devexit atyfb_remove(struct fb_info *info)
3698{
3699 struct atyfb_par *par = (struct atyfb_par *) info->par;
3700
3701 /* restore video mode */
3702 aty_set_crtc(par, &saved_crtc);
3703 par->pll_ops->set_pll(info, &saved_pll);
3704
Michael Hanselmann5474c122006-06-25 05:47:08 -07003705#ifdef CONFIG_FB_ATY_BACKLIGHT
3706 if (M64_HAS(MOBIL_BUS))
3707 aty_bl_exit(par);
3708#endif
3709
Linus Torvalds1da177e2005-04-16 15:20:36 -07003710 unregister_framebuffer(info);
3711
3712#ifdef CONFIG_MTRR
3713 if (par->mtrr_reg >= 0) {
3714 mtrr_del(par->mtrr_reg, 0, 0);
3715 par->mtrr_reg = -1;
3716 }
3717 if (par->mtrr_aper >= 0) {
3718 mtrr_del(par->mtrr_aper, 0, 0);
3719 par->mtrr_aper = -1;
3720 }
3721#endif
3722#ifndef __sparc__
3723 if (par->ati_regbase)
3724 iounmap(par->ati_regbase);
3725 if (info->screen_base)
3726 iounmap(info->screen_base);
3727#ifdef __BIG_ENDIAN
3728 if (info->sprite.addr)
3729 iounmap(info->sprite.addr);
3730#endif
3731#endif
3732#ifdef __sparc__
3733 kfree(par->mmap_map);
3734#endif
3735 if (par->aux_start)
3736 release_mem_region(par->aux_start, par->aux_size);
3737
3738 if (par->res_start)
3739 release_mem_region(par->res_start, par->res_size);
3740
3741 framebuffer_release(info);
3742}
3743
3744#ifdef CONFIG_PCI
3745
3746static void __devexit atyfb_pci_remove(struct pci_dev *pdev)
3747{
3748 struct fb_info *info = pci_get_drvdata(pdev);
3749
3750 atyfb_remove(info);
3751}
3752
3753/*
3754 * This driver uses its own matching table. That will be more difficult
3755 * to fix, so for now, we just match against any ATI ID and let the
3756 * probe() function find out what's up. That also mean we don't have
3757 * a module ID table though.
3758 */
3759static struct pci_device_id atyfb_pci_tbl[] = {
3760 { PCI_VENDOR_ID_ATI, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
3761 PCI_BASE_CLASS_DISPLAY << 16, 0xff0000, 0 },
3762 { 0, }
3763};
3764
3765static struct pci_driver atyfb_driver = {
3766 .name = "atyfb",
3767 .id_table = atyfb_pci_tbl,
3768 .probe = atyfb_pci_probe,
3769 .remove = __devexit_p(atyfb_pci_remove),
3770#ifdef CONFIG_PM
3771 .suspend = atyfb_pci_suspend,
3772 .resume = atyfb_pci_resume,
3773#endif /* CONFIG_PM */
3774};
3775
3776#endif /* CONFIG_PCI */
3777
3778#ifndef MODULE
3779static int __init atyfb_setup(char *options)
3780{
3781 char *this_opt;
3782
3783 if (!options || !*options)
3784 return 0;
3785
3786 while ((this_opt = strsep(&options, ",")) != NULL) {
3787 if (!strncmp(this_opt, "noaccel", 7)) {
3788 noaccel = 1;
3789#ifdef CONFIG_MTRR
3790 } else if (!strncmp(this_opt, "nomtrr", 6)) {
3791 nomtrr = 1;
3792#endif
3793 } else if (!strncmp(this_opt, "vram:", 5))
3794 vram = simple_strtoul(this_opt + 5, NULL, 0);
3795 else if (!strncmp(this_opt, "pll:", 4))
3796 pll = simple_strtoul(this_opt + 4, NULL, 0);
3797 else if (!strncmp(this_opt, "mclk:", 5))
3798 mclk = simple_strtoul(this_opt + 5, NULL, 0);
3799 else if (!strncmp(this_opt, "xclk:", 5))
3800 xclk = simple_strtoul(this_opt+5, NULL, 0);
3801 else if (!strncmp(this_opt, "comp_sync:", 10))
3802 comp_sync = simple_strtoul(this_opt+10, NULL, 0);
3803#ifdef CONFIG_PPC
3804 else if (!strncmp(this_opt, "vmode:", 6)) {
3805 unsigned int vmode =
3806 simple_strtoul(this_opt + 6, NULL, 0);
3807 if (vmode > 0 && vmode <= VMODE_MAX)
3808 default_vmode = vmode;
3809 } else if (!strncmp(this_opt, "cmode:", 6)) {
3810 unsigned int cmode =
3811 simple_strtoul(this_opt + 6, NULL, 0);
3812 switch (cmode) {
3813 case 0:
3814 case 8:
3815 default_cmode = CMODE_8;
3816 break;
3817 case 15:
3818 case 16:
3819 default_cmode = CMODE_16;
3820 break;
3821 case 24:
3822 case 32:
3823 default_cmode = CMODE_32;
3824 break;
3825 }
3826 }
3827#endif
3828#ifdef CONFIG_ATARI
3829 /*
3830 * Why do we need this silly Mach64 argument?
3831 * We are already here because of mach64= so its redundant.
3832 */
3833 else if (MACH_IS_ATARI
3834 && (!strncmp(this_opt, "Mach64:", 7))) {
3835 static unsigned char m64_num;
3836 static char mach64_str[80];
3837 strlcpy(mach64_str, this_opt + 7, sizeof(mach64_str));
3838 if (!store_video_par(mach64_str, m64_num)) {
3839 m64_num++;
3840 mach64_count = m64_num;
3841 }
3842 }
3843#endif
3844 else
3845 mode = this_opt;
3846 }
3847 return 0;
3848}
3849#endif /* MODULE */
3850
3851static int __init atyfb_init(void)
3852{
3853#ifndef MODULE
3854 char *option = NULL;
3855
3856 if (fb_get_options("atyfb", &option))
3857 return -ENODEV;
3858 atyfb_setup(option);
3859#endif
3860
Roman Zippel078517e2006-06-23 02:04:53 -07003861#ifdef CONFIG_PCI
Linus Torvalds1da177e2005-04-16 15:20:36 -07003862 pci_register_driver(&atyfb_driver);
Roman Zippel078517e2006-06-23 02:04:53 -07003863#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -07003864#ifdef CONFIG_ATARI
3865 atyfb_atari_probe();
3866#endif
3867 return 0;
3868}
3869
3870static void __exit atyfb_exit(void)
3871{
Roman Zippel078517e2006-06-23 02:04:53 -07003872#ifdef CONFIG_PCI
Linus Torvalds1da177e2005-04-16 15:20:36 -07003873 pci_unregister_driver(&atyfb_driver);
Roman Zippel078517e2006-06-23 02:04:53 -07003874#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -07003875}
3876
3877module_init(atyfb_init);
3878module_exit(atyfb_exit);
3879
3880MODULE_DESCRIPTION("FBDev driver for ATI Mach64 cards");
3881MODULE_LICENSE("GPL");
3882module_param(noaccel, bool, 0);
3883MODULE_PARM_DESC(noaccel, "bool: disable acceleration");
3884module_param(vram, int, 0);
3885MODULE_PARM_DESC(vram, "int: override size of video ram");
3886module_param(pll, int, 0);
3887MODULE_PARM_DESC(pll, "int: override video clock");
3888module_param(mclk, int, 0);
3889MODULE_PARM_DESC(mclk, "int: override memory clock");
3890module_param(xclk, int, 0);
3891MODULE_PARM_DESC(xclk, "int: override accelerated engine clock");
3892module_param(comp_sync, int, 0);
3893MODULE_PARM_DESC(comp_sync,
3894 "Set composite sync signal to low (0) or high (1)");
3895module_param(mode, charp, 0);
3896MODULE_PARM_DESC(mode, "Specify resolution as \"<xres>x<yres>[-<bpp>][@<refresh>]\" ");
3897#ifdef CONFIG_MTRR
3898module_param(nomtrr, bool, 0);
3899MODULE_PARM_DESC(nomtrr, "bool: disable use of MTRR registers");
3900#endif