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Suresh Siddha61c46282008-03-10 15:28:04 -07001#include <linux/errno.h>
2#include <linux/kernel.h>
3#include <linux/mm.h>
4#include <linux/smp.h>
Jeremy Fitzhardinge389d1fb2009-02-27 13:25:28 -08005#include <linux/prctl.h>
Suresh Siddha61c46282008-03-10 15:28:04 -07006#include <linux/slab.h>
7#include <linux/sched.h>
Peter Zijlstra7f424a82008-04-25 17:39:01 +02008#include <linux/module.h>
9#include <linux/pm.h>
Thomas Gleixneraa276e12008-06-09 19:15:00 +020010#include <linux/clockchips.h>
Amerigo Wang9d62dcd2009-05-11 22:05:28 -040011#include <linux/random.h>
Avi Kivity7c68af62009-09-19 09:40:22 +030012#include <linux/user-return-notifier.h>
Arjan van de Ven61613522009-09-17 16:11:28 +020013#include <trace/events/power.h>
Zhao Yakuic1e3b372008-06-24 17:58:53 +080014#include <asm/system.h>
Ivan Vecerad3ec5ca2008-11-11 14:33:44 +010015#include <asm/apic.h>
Jaswinder Singh Rajput2c1b2842009-04-11 00:03:10 +053016#include <asm/syscalls.h>
Jeremy Fitzhardinge389d1fb2009-02-27 13:25:28 -080017#include <asm/idle.h>
18#include <asm/uaccess.h>
19#include <asm/i387.h>
Markus Metzger2311f0d2009-04-03 16:43:46 +020020#include <asm/ds.h>
Zhao Yakuic1e3b372008-06-24 17:58:53 +080021
22unsigned long idle_halt;
23EXPORT_SYMBOL(idle_halt);
Zhao Yakuida5e09a2008-06-24 18:01:09 +080024unsigned long idle_nomwait;
25EXPORT_SYMBOL(idle_nomwait);
Suresh Siddha61c46282008-03-10 15:28:04 -070026
Suresh Siddhaaa283f42008-03-10 15:28:05 -070027struct kmem_cache *task_xstate_cachep;
Suresh Siddha61c46282008-03-10 15:28:04 -070028
29int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src)
30{
31 *dst = *src;
Suresh Siddhaaa283f42008-03-10 15:28:05 -070032 if (src->thread.xstate) {
33 dst->thread.xstate = kmem_cache_alloc(task_xstate_cachep,
34 GFP_KERNEL);
35 if (!dst->thread.xstate)
36 return -ENOMEM;
37 WARN_ON((unsigned long)dst->thread.xstate & 15);
38 memcpy(dst->thread.xstate, src->thread.xstate, xstate_size);
39 }
Suresh Siddha61c46282008-03-10 15:28:04 -070040 return 0;
41}
42
Suresh Siddhaaa283f42008-03-10 15:28:05 -070043void free_thread_xstate(struct task_struct *tsk)
44{
45 if (tsk->thread.xstate) {
46 kmem_cache_free(task_xstate_cachep, tsk->thread.xstate);
47 tsk->thread.xstate = NULL;
48 }
Markus Metzger2311f0d2009-04-03 16:43:46 +020049
50 WARN(tsk->thread.ds_ctx, "leaking DS context\n");
Suresh Siddhaaa283f42008-03-10 15:28:05 -070051}
52
Suresh Siddha61c46282008-03-10 15:28:04 -070053void free_thread_info(struct thread_info *ti)
54{
Suresh Siddhaaa283f42008-03-10 15:28:05 -070055 free_thread_xstate(ti->task);
Suresh Siddha1679f272008-04-16 10:27:53 +020056 free_pages((unsigned long)ti, get_order(THREAD_SIZE));
Suresh Siddha61c46282008-03-10 15:28:04 -070057}
58
59void arch_task_cache_init(void)
60{
61 task_xstate_cachep =
62 kmem_cache_create("task_xstate", xstate_size,
63 __alignof__(union thread_xstate),
Vegard Nossum2dff4402008-05-31 15:56:17 +020064 SLAB_PANIC | SLAB_NOTRACK, NULL);
Suresh Siddha61c46282008-03-10 15:28:04 -070065}
Peter Zijlstra7f424a82008-04-25 17:39:01 +020066
Thomas Gleixner00dba562008-06-09 18:35:28 +020067/*
Jeremy Fitzhardinge389d1fb2009-02-27 13:25:28 -080068 * Free current thread data structures etc..
69 */
70void exit_thread(void)
71{
72 struct task_struct *me = current;
73 struct thread_struct *t = &me->thread;
Thomas Gleixner250981e2009-03-16 13:07:21 +010074 unsigned long *bp = t->io_bitmap_ptr;
Jeremy Fitzhardinge389d1fb2009-02-27 13:25:28 -080075
Thomas Gleixner250981e2009-03-16 13:07:21 +010076 if (bp) {
Jeremy Fitzhardinge389d1fb2009-02-27 13:25:28 -080077 struct tss_struct *tss = &per_cpu(init_tss, get_cpu());
78
Jeremy Fitzhardinge389d1fb2009-02-27 13:25:28 -080079 t->io_bitmap_ptr = NULL;
80 clear_thread_flag(TIF_IO_BITMAP);
81 /*
82 * Careful, clear this in the TSS too:
83 */
84 memset(tss->io_bitmap, 0xff, t->io_bitmap_max);
85 t->io_bitmap_max = 0;
86 put_cpu();
Thomas Gleixner250981e2009-03-16 13:07:21 +010087 kfree(bp);
Jeremy Fitzhardinge389d1fb2009-02-27 13:25:28 -080088 }
Jeremy Fitzhardinge389d1fb2009-02-27 13:25:28 -080089}
90
91void flush_thread(void)
92{
93 struct task_struct *tsk = current;
94
95#ifdef CONFIG_X86_64
96 if (test_tsk_thread_flag(tsk, TIF_ABI_PENDING)) {
97 clear_tsk_thread_flag(tsk, TIF_ABI_PENDING);
98 if (test_tsk_thread_flag(tsk, TIF_IA32)) {
99 clear_tsk_thread_flag(tsk, TIF_IA32);
100 } else {
101 set_tsk_thread_flag(tsk, TIF_IA32);
102 current_thread_info()->status |= TS_COMPAT;
103 }
104 }
105#endif
106
107 clear_tsk_thread_flag(tsk, TIF_DEBUG);
108
109 tsk->thread.debugreg0 = 0;
110 tsk->thread.debugreg1 = 0;
111 tsk->thread.debugreg2 = 0;
112 tsk->thread.debugreg3 = 0;
113 tsk->thread.debugreg6 = 0;
114 tsk->thread.debugreg7 = 0;
115 memset(tsk->thread.tls_array, 0, sizeof(tsk->thread.tls_array));
116 /*
117 * Forget coprocessor state..
118 */
119 tsk->fpu_counter = 0;
120 clear_fpu(tsk);
121 clear_used_math();
122}
123
124static void hard_disable_TSC(void)
125{
126 write_cr4(read_cr4() | X86_CR4_TSD);
127}
128
129void disable_TSC(void)
130{
131 preempt_disable();
132 if (!test_and_set_thread_flag(TIF_NOTSC))
133 /*
134 * Must flip the CPU state synchronously with
135 * TIF_NOTSC in the current running context.
136 */
137 hard_disable_TSC();
138 preempt_enable();
139}
140
141static void hard_enable_TSC(void)
142{
143 write_cr4(read_cr4() & ~X86_CR4_TSD);
144}
145
146static void enable_TSC(void)
147{
148 preempt_disable();
149 if (test_and_clear_thread_flag(TIF_NOTSC))
150 /*
151 * Must flip the CPU state synchronously with
152 * TIF_NOTSC in the current running context.
153 */
154 hard_enable_TSC();
155 preempt_enable();
156}
157
158int get_tsc_mode(unsigned long adr)
159{
160 unsigned int val;
161
162 if (test_thread_flag(TIF_NOTSC))
163 val = PR_TSC_SIGSEGV;
164 else
165 val = PR_TSC_ENABLE;
166
167 return put_user(val, (unsigned int __user *)adr);
168}
169
170int set_tsc_mode(unsigned int val)
171{
172 if (val == PR_TSC_SIGSEGV)
173 disable_TSC();
174 else if (val == PR_TSC_ENABLE)
175 enable_TSC();
176 else
177 return -EINVAL;
178
179 return 0;
180}
181
182void __switch_to_xtra(struct task_struct *prev_p, struct task_struct *next_p,
183 struct tss_struct *tss)
184{
185 struct thread_struct *prev, *next;
186
187 prev = &prev_p->thread;
188 next = &next_p->thread;
189
190 if (test_tsk_thread_flag(next_p, TIF_DS_AREA_MSR) ||
191 test_tsk_thread_flag(prev_p, TIF_DS_AREA_MSR))
192 ds_switch_to(prev_p, next_p);
193 else if (next->debugctlmsr != prev->debugctlmsr)
194 update_debugctlmsr(next->debugctlmsr);
195
196 if (test_tsk_thread_flag(next_p, TIF_DEBUG)) {
197 set_debugreg(next->debugreg0, 0);
198 set_debugreg(next->debugreg1, 1);
199 set_debugreg(next->debugreg2, 2);
200 set_debugreg(next->debugreg3, 3);
201 /* no 4 and 5 */
202 set_debugreg(next->debugreg6, 6);
203 set_debugreg(next->debugreg7, 7);
204 }
205
206 if (test_tsk_thread_flag(prev_p, TIF_NOTSC) ^
207 test_tsk_thread_flag(next_p, TIF_NOTSC)) {
208 /* prev and next are different */
209 if (test_tsk_thread_flag(next_p, TIF_NOTSC))
210 hard_disable_TSC();
211 else
212 hard_enable_TSC();
213 }
214
215 if (test_tsk_thread_flag(next_p, TIF_IO_BITMAP)) {
216 /*
217 * Copy the relevant range of the IO bitmap.
218 * Normally this is 128 bytes or less:
219 */
220 memcpy(tss->io_bitmap, next->io_bitmap_ptr,
221 max(prev->io_bitmap_max, next->io_bitmap_max));
222 } else if (test_tsk_thread_flag(prev_p, TIF_IO_BITMAP)) {
223 /*
224 * Clear any possible leftover bits:
225 */
226 memset(tss->io_bitmap, 0xff, prev->io_bitmap_max);
227 }
Avi Kivity7c68af62009-09-19 09:40:22 +0300228 propagate_user_return_notify(prev_p, next_p);
Jeremy Fitzhardinge389d1fb2009-02-27 13:25:28 -0800229}
230
231int sys_fork(struct pt_regs *regs)
232{
233 return do_fork(SIGCHLD, regs->sp, regs, 0, NULL, NULL);
234}
235
236/*
237 * This is trivial, and on the face of it looks like it
238 * could equally well be done in user mode.
239 *
240 * Not so, for quite unobvious reasons - register pressure.
241 * In user mode vfork() cannot have a stack frame, and if
242 * done by calling the "clone()" system call directly, you
243 * do not have enough call-clobbered registers to hold all
244 * the information you need.
245 */
246int sys_vfork(struct pt_regs *regs)
247{
248 return do_fork(CLONE_VFORK | CLONE_VM | SIGCHLD, regs->sp, regs, 0,
249 NULL, NULL);
250}
251
252
253/*
Thomas Gleixner00dba562008-06-09 18:35:28 +0200254 * Idle related variables and functions
255 */
256unsigned long boot_option_idle_override = 0;
257EXPORT_SYMBOL(boot_option_idle_override);
258
259/*
260 * Powermanagement idle function, if any..
261 */
262void (*pm_idle)(void);
263EXPORT_SYMBOL(pm_idle);
264
265#ifdef CONFIG_X86_32
266/*
267 * This halt magic was a workaround for ancient floppy DMA
268 * wreckage. It should be safe to remove.
269 */
270static int hlt_counter;
271void disable_hlt(void)
272{
273 hlt_counter++;
274}
275EXPORT_SYMBOL(disable_hlt);
276
277void enable_hlt(void)
278{
279 hlt_counter--;
280}
281EXPORT_SYMBOL(enable_hlt);
282
283static inline int hlt_use_halt(void)
284{
285 return (!hlt_counter && boot_cpu_data.hlt_works_ok);
286}
287#else
288static inline int hlt_use_halt(void)
289{
290 return 1;
291}
292#endif
293
294/*
295 * We use this if we don't have any better
296 * idle routine..
297 */
298void default_idle(void)
299{
300 if (hlt_use_halt()) {
Arjan van de Ven61613522009-09-17 16:11:28 +0200301 trace_power_start(POWER_CSTATE, 1);
Thomas Gleixner00dba562008-06-09 18:35:28 +0200302 current_thread_info()->status &= ~TS_POLLING;
303 /*
304 * TS_POLLING-cleared state must be visible before we
305 * test NEED_RESCHED:
306 */
307 smp_mb();
308
309 if (!need_resched())
310 safe_halt(); /* enables interrupts racelessly */
311 else
312 local_irq_enable();
313 current_thread_info()->status |= TS_POLLING;
314 } else {
315 local_irq_enable();
316 /* loop is done by the caller */
317 cpu_relax();
318 }
319}
320#ifdef CONFIG_APM_MODULE
321EXPORT_SYMBOL(default_idle);
322#endif
323
Ivan Vecerad3ec5ca2008-11-11 14:33:44 +0100324void stop_this_cpu(void *dummy)
325{
326 local_irq_disable();
327 /*
328 * Remove this CPU:
329 */
Rusty Russell4f062892009-03-13 14:49:54 +1030330 set_cpu_online(smp_processor_id(), false);
Ivan Vecerad3ec5ca2008-11-11 14:33:44 +0100331 disable_local_APIC();
332
333 for (;;) {
334 if (hlt_works(smp_processor_id()))
335 halt();
336 }
337}
338
Peter Zijlstra7f424a82008-04-25 17:39:01 +0200339static void do_nothing(void *unused)
340{
341}
342
343/*
344 * cpu_idle_wait - Used to ensure that all the CPUs discard old value of
345 * pm_idle and update to new pm_idle value. Required while changing pm_idle
346 * handler on SMP systems.
347 *
348 * Caller must have changed pm_idle to the new value before the call. Old
349 * pm_idle value will not be used by any CPU after the return of this function.
350 */
351void cpu_idle_wait(void)
352{
353 smp_mb();
354 /* kick all the CPUs so that they exit out of pm_idle */
Ingo Molnar127a2372008-06-27 11:48:22 +0200355 smp_call_function(do_nothing, NULL, 1);
Peter Zijlstra7f424a82008-04-25 17:39:01 +0200356}
357EXPORT_SYMBOL_GPL(cpu_idle_wait);
358
359/*
360 * This uses new MONITOR/MWAIT instructions on P4 processors with PNI,
361 * which can obviate IPI to trigger checking of need_resched.
362 * We execute MONITOR against need_resched and enter optimized wait state
363 * through MWAIT. Whenever someone changes need_resched, we would be woken
364 * up from MWAIT (without an IPI).
365 *
366 * New with Core Duo processors, MWAIT can take some hints based on CPU
367 * capability.
368 */
369void mwait_idle_with_hints(unsigned long ax, unsigned long cx)
370{
Arjan van de Ven61613522009-09-17 16:11:28 +0200371 trace_power_start(POWER_CSTATE, (ax>>4)+1);
Peter Zijlstra7f424a82008-04-25 17:39:01 +0200372 if (!need_resched()) {
Pallipadi, Venkateshe736ad52009-02-06 16:52:05 -0800373 if (cpu_has(&current_cpu_data, X86_FEATURE_CLFLUSH_MONITOR))
374 clflush((void *)&current_thread_info()->flags);
375
Peter Zijlstra7f424a82008-04-25 17:39:01 +0200376 __monitor((void *)&current_thread_info()->flags, 0, 0);
377 smp_mb();
378 if (!need_resched())
379 __mwait(ax, cx);
380 }
381}
382
383/* Default MONITOR/MWAIT with no hints, used for default C1 state */
384static void mwait_idle(void)
385{
386 if (!need_resched()) {
Arjan van de Ven61613522009-09-17 16:11:28 +0200387 trace_power_start(POWER_CSTATE, 1);
Pallipadi, Venkateshe736ad52009-02-06 16:52:05 -0800388 if (cpu_has(&current_cpu_data, X86_FEATURE_CLFLUSH_MONITOR))
389 clflush((void *)&current_thread_info()->flags);
390
Peter Zijlstra7f424a82008-04-25 17:39:01 +0200391 __monitor((void *)&current_thread_info()->flags, 0, 0);
392 smp_mb();
393 if (!need_resched())
394 __sti_mwait(0, 0);
395 else
396 local_irq_enable();
397 } else
398 local_irq_enable();
399}
400
Peter Zijlstra7f424a82008-04-25 17:39:01 +0200401/*
402 * On SMP it's slightly faster (but much more power-consuming!)
403 * to poll the ->work.need_resched flag instead of waiting for the
404 * cross-CPU IPI to arrive. Use this option with caution.
405 */
406static void poll_idle(void)
407{
Arjan van de Ven61613522009-09-17 16:11:28 +0200408 trace_power_start(POWER_CSTATE, 0);
Peter Zijlstra7f424a82008-04-25 17:39:01 +0200409 local_irq_enable();
Joe Korty2c7e9fd2008-08-27 10:35:06 -0400410 while (!need_resched())
411 cpu_relax();
Arjan van de Ven61613522009-09-17 16:11:28 +0200412 trace_power_end(0);
Peter Zijlstra7f424a82008-04-25 17:39:01 +0200413}
414
Thomas Gleixnere9623b32008-05-16 22:55:26 +0200415/*
416 * mwait selection logic:
417 *
418 * It depends on the CPU. For AMD CPUs that support MWAIT this is
419 * wrong. Family 0x10 and 0x11 CPUs will enter C1 on HLT. Powersavings
420 * then depend on a clock divisor and current Pstate of the core. If
421 * all cores of a processor are in halt state (C1) the processor can
422 * enter the C1E (C1 enhanced) state. If mwait is used this will never
423 * happen.
424 *
425 * idle=mwait overrides this decision and forces the usage of mwait.
426 */
Jan Beulich08ad8af2008-07-18 13:45:20 +0100427static int __cpuinitdata force_mwait;
Thomas Gleixner09fd4b42008-06-09 18:04:27 +0200428
429#define MWAIT_INFO 0x05
430#define MWAIT_ECX_EXTENDED_INFO 0x01
431#define MWAIT_EDX_C1 0xf0
432
Thomas Gleixnere9623b32008-05-16 22:55:26 +0200433static int __cpuinit mwait_usable(const struct cpuinfo_x86 *c)
434{
Thomas Gleixner09fd4b42008-06-09 18:04:27 +0200435 u32 eax, ebx, ecx, edx;
436
Thomas Gleixnere9623b32008-05-16 22:55:26 +0200437 if (force_mwait)
438 return 1;
439
Thomas Gleixner09fd4b42008-06-09 18:04:27 +0200440 if (c->cpuid_level < MWAIT_INFO)
441 return 0;
442
443 cpuid(MWAIT_INFO, &eax, &ebx, &ecx, &edx);
444 /* Check, whether EDX has extended info about MWAIT */
445 if (!(ecx & MWAIT_ECX_EXTENDED_INFO))
446 return 1;
447
448 /*
449 * edx enumeratios MONITOR/MWAIT extensions. Check, whether
450 * C1 supports MWAIT
451 */
452 return (edx & MWAIT_EDX_C1);
Thomas Gleixnere9623b32008-05-16 22:55:26 +0200453}
454
Thomas Gleixneraa276e12008-06-09 19:15:00 +0200455/*
456 * Check for AMD CPUs, which have potentially C1E support
457 */
458static int __cpuinit check_c1e_idle(const struct cpuinfo_x86 *c)
459{
460 if (c->x86_vendor != X86_VENDOR_AMD)
461 return 0;
462
463 if (c->x86 < 0x0F)
464 return 0;
465
466 /* Family 0x0f models < rev F do not have C1E */
467 if (c->x86 == 0x0f && c->x86_model < 0x40)
468 return 0;
469
470 return 1;
471}
472
Rusty Russellbc9b83d2009-03-13 14:49:49 +1030473static cpumask_var_t c1e_mask;
Thomas Gleixner4faac972008-09-22 18:54:29 +0200474static int c1e_detected;
475
476void c1e_remove_cpu(int cpu)
477{
Rusty Russell30e1e6d2009-03-17 14:50:34 +1030478 if (c1e_mask != NULL)
479 cpumask_clear_cpu(cpu, c1e_mask);
Thomas Gleixner4faac972008-09-22 18:54:29 +0200480}
481
Thomas Gleixneraa276e12008-06-09 19:15:00 +0200482/*
483 * C1E aware idle routine. We check for C1E active in the interrupt
484 * pending message MSR. If we detect C1E, then we handle it the same
485 * way as C3 power states (local apic timer and TSC stop)
486 */
487static void c1e_idle(void)
488{
Thomas Gleixneraa276e12008-06-09 19:15:00 +0200489 if (need_resched())
490 return;
491
492 if (!c1e_detected) {
493 u32 lo, hi;
494
495 rdmsr(MSR_K8_INT_PENDING_MSG, lo, hi);
496 if (lo & K8_INTP_C1E_ACTIVE_MASK) {
497 c1e_detected = 1;
Venki Pallipadi40fb1712008-11-17 16:11:37 -0800498 if (!boot_cpu_has(X86_FEATURE_NONSTOP_TSC))
Andreas Herrmann09bfeea2008-09-18 21:12:10 +0200499 mark_tsc_unstable("TSC halt in AMD C1E");
500 printk(KERN_INFO "System has AMD C1E enabled\n");
Thomas Gleixnera8d68292008-09-22 19:02:25 +0200501 set_cpu_cap(&boot_cpu_data, X86_FEATURE_AMDC1E);
Thomas Gleixneraa276e12008-06-09 19:15:00 +0200502 }
503 }
504
505 if (c1e_detected) {
506 int cpu = smp_processor_id();
507
Rusty Russellbc9b83d2009-03-13 14:49:49 +1030508 if (!cpumask_test_cpu(cpu, c1e_mask)) {
509 cpumask_set_cpu(cpu, c1e_mask);
Thomas Gleixner0beefa22008-06-17 09:12:03 +0200510 /*
Suresh Siddhaf833bab2009-08-17 14:34:59 -0700511 * Force broadcast so ACPI can not interfere.
Thomas Gleixner0beefa22008-06-17 09:12:03 +0200512 */
Thomas Gleixneraa276e12008-06-09 19:15:00 +0200513 clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_FORCE,
514 &cpu);
515 printk(KERN_INFO "Switch to broadcast mode on CPU%d\n",
516 cpu);
517 }
518 clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &cpu);
Thomas Gleixner0beefa22008-06-17 09:12:03 +0200519
Thomas Gleixneraa276e12008-06-09 19:15:00 +0200520 default_idle();
Thomas Gleixner0beefa22008-06-17 09:12:03 +0200521
522 /*
523 * The switch back from broadcast mode needs to be
524 * called with interrupts disabled.
525 */
526 local_irq_disable();
527 clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &cpu);
528 local_irq_enable();
Thomas Gleixneraa276e12008-06-09 19:15:00 +0200529 } else
530 default_idle();
531}
532
Peter Zijlstra7f424a82008-04-25 17:39:01 +0200533void __cpuinit select_idle_routine(const struct cpuinfo_x86 *c)
534{
Ingo Molnar3e5095d2009-01-27 17:07:08 +0100535#ifdef CONFIG_SMP
Peter Zijlstra7f424a82008-04-25 17:39:01 +0200536 if (pm_idle == poll_idle && smp_num_siblings > 1) {
537 printk(KERN_WARNING "WARNING: polling idle and HT enabled,"
538 " performance may degrade.\n");
539 }
540#endif
Thomas Gleixner6ddd2a22008-06-09 16:59:53 +0200541 if (pm_idle)
542 return;
543
Thomas Gleixnere9623b32008-05-16 22:55:26 +0200544 if (cpu_has(c, X86_FEATURE_MWAIT) && mwait_usable(c)) {
Peter Zijlstra7f424a82008-04-25 17:39:01 +0200545 /*
Peter Zijlstra7f424a82008-04-25 17:39:01 +0200546 * One CPU supports mwait => All CPUs supports mwait
547 */
Thomas Gleixner6ddd2a22008-06-09 16:59:53 +0200548 printk(KERN_INFO "using mwait in idle threads.\n");
549 pm_idle = mwait_idle;
Thomas Gleixneraa276e12008-06-09 19:15:00 +0200550 } else if (check_c1e_idle(c)) {
551 printk(KERN_INFO "using C1E aware idle routine\n");
552 pm_idle = c1e_idle;
Thomas Gleixner6ddd2a22008-06-09 16:59:53 +0200553 } else
554 pm_idle = default_idle;
Peter Zijlstra7f424a82008-04-25 17:39:01 +0200555}
556
Rusty Russell30e1e6d2009-03-17 14:50:34 +1030557void __init init_c1e_mask(void)
558{
559 /* If we're using c1e_idle, we need to allocate c1e_mask. */
Li Zefan79f55992009-06-15 14:58:26 +0800560 if (pm_idle == c1e_idle)
561 zalloc_cpumask_var(&c1e_mask, GFP_KERNEL);
Rusty Russell30e1e6d2009-03-17 14:50:34 +1030562}
563
Peter Zijlstra7f424a82008-04-25 17:39:01 +0200564static int __init idle_setup(char *str)
565{
Cyrill Gorcunovab6bc3e2008-07-05 15:53:36 +0400566 if (!str)
567 return -EINVAL;
568
Peter Zijlstra7f424a82008-04-25 17:39:01 +0200569 if (!strcmp(str, "poll")) {
570 printk("using polling idle threads.\n");
571 pm_idle = poll_idle;
572 } else if (!strcmp(str, "mwait"))
573 force_mwait = 1;
Zhao Yakuic1e3b372008-06-24 17:58:53 +0800574 else if (!strcmp(str, "halt")) {
575 /*
576 * When the boot option of idle=halt is added, halt is
577 * forced to be used for CPU idle. In such case CPU C2/C3
578 * won't be used again.
579 * To continue to load the CPU idle driver, don't touch
580 * the boot_option_idle_override.
581 */
582 pm_idle = default_idle;
583 idle_halt = 1;
584 return 0;
Zhao Yakuida5e09a2008-06-24 18:01:09 +0800585 } else if (!strcmp(str, "nomwait")) {
586 /*
587 * If the boot option of "idle=nomwait" is added,
588 * it means that mwait will be disabled for CPU C2/C3
589 * states. In such case it won't touch the variable
590 * of boot_option_idle_override.
591 */
592 idle_nomwait = 1;
593 return 0;
Zhao Yakuic1e3b372008-06-24 17:58:53 +0800594 } else
Peter Zijlstra7f424a82008-04-25 17:39:01 +0200595 return -1;
596
597 boot_option_idle_override = 1;
598 return 0;
599}
600early_param("idle", idle_setup);
601
Amerigo Wang9d62dcd2009-05-11 22:05:28 -0400602unsigned long arch_align_stack(unsigned long sp)
603{
604 if (!(current->personality & ADDR_NO_RANDOMIZE) && randomize_va_space)
605 sp -= get_random_int() % 8192;
606 return sp & ~0xf;
607}
608
609unsigned long arch_randomize_brk(struct mm_struct *mm)
610{
611 unsigned long range_end = mm->brk + 0x02000000;
612 return randomize_range(mm->brk, range_end, 0) ? : mm->brk;
613}
614