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review.evervolv.com / android_kernel_htc_msm8960 / 7dfc4b284ca395a035e7da058f86dfb4275dd509 / . / drivers / video / msm / mdp4_util.c
blob: 08849e6a698dab44a9d6a2c9dc35ae47e1ea09bc [file] [log] [blame]
Siddhartha Agrawalee8d2272012-09-12 18:47:41 -0700[diff] [blame]1/* Copyright (c) 2009-2013, Code Aurora Forum. All rights reserved.
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 *
12 */
13
14#include <linux/module.h>
15#include <linux/kernel.h>
16#include <linux/sched.h>
17#include <linux/time.h>
18#include <linux/init.h>
19#include <linux/interrupt.h>
20#include <linux/spinlock.h>
21#include <linux/hrtimer.h>
22#include <linux/clk.h>
23#include <linux/io.h>
24#include <linux/debugfs.h>
25#include <linux/semaphore.h>
26#include <linux/uaccess.h>
Pravin Tamkhane85153bd2011-12-13 13:56:46 -0800[diff] [blame]27#include <linux/msm_mdp.h>
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]28#include <asm/system.h>
29#include <asm/mach-types.h>
30#include <mach/hardware.h>
Ravishangar Kalyanam6bc448a2012-03-14 11:31:52 -0700[diff] [blame]31#include <mach/iommu_domains.h>
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]32#include "mdp.h"
33#include "msm_fb.h"
34#include "mdp4.h"
35
36struct mdp4_statistic mdp4_stat;
37
Kalyan Thota4c5e9262012-08-13 17:33:26 +0530[diff] [blame]38struct mdp_csc_cfg_data csc_cfg_matrix[CSC_MAX_BLOCKS] = {
39 {
40 .block = MDP_BLOCK_VG_1,
41 .csc_data = {
42 (MDP_CSC_FLAG_YUV_OUT),
43 {
44 0x0254, 0x0000, 0x0331,
45 0x0254, 0xff37, 0xfe60,
46 0x0254, 0x0409, 0x0000,
47 },
48 {
49 0xfff0, 0xff80, 0xff80,
50 },
51 {
52 0, 0, 0,
53 },
54 {
55 0, 0xff, 0, 0xff, 0, 0xff,
56 },
57 {
58 0, 0xff, 0, 0xff, 0, 0xff,
59 },
60 },
61 },
62 {
63 .block = MDP_BLOCK_VG_2,
64 .csc_data = {
65 (MDP_CSC_FLAG_YUV_OUT),
66 {
67 0x0254, 0x0000, 0x0331,
68 0x0254, 0xff37, 0xfe60,
69 0x0254, 0x0409, 0x0000,
70 },
71 {
72 0xfff0, 0xff80, 0xff80,
73 },
74 {
75 0, 0, 0,
76 },
77 {
78 0, 0xff, 0, 0xff, 0, 0xff,
79 },
80 {
81 0, 0xff, 0, 0xff, 0, 0xff,
82 },
83 },
84 },
85 {
86 .block = MDP_BLOCK_DMA_P,
87 .csc_data = {
88 (0),
89 {
90 0x0200, 0x0000, 0x0000,
91 0x0000, 0x0200, 0x0000,
92 0x0000, 0x0000, 0x0200,
93 },
94 {
95 0x0, 0x0, 0x0,
96 },
97 {
98 0, 0, 0,
99 },
100 {
101 0, 0xff, 0, 0xff, 0, 0xff,
102 },
103 {
104 0, 0xff, 0, 0xff, 0, 0xff,
105 },
106 },
107 },
108 {
109 .block = MDP_BLOCK_OVERLAY_1,
110 .csc_data = {
111 (0),
112 {
Kalyan Thota79b217a2012-09-20 16:57:51 +0530[diff] [blame]113 0x0083, 0x0102, 0x0032,
114 0x1fb5, 0x1f6c, 0x00e1,
115 0x00e1, 0x1f45, 0x1fdc,
Kalyan Thota4c5e9262012-08-13 17:33:26 +0530[diff] [blame]116 },
117 {
118 0x0, 0x0, 0x0,
119 },
120 {
Kalyan Thota79b217a2012-09-20 16:57:51 +0530[diff] [blame]121 0x0010, 0x0080, 0x0080,
Kalyan Thota4c5e9262012-08-13 17:33:26 +0530[diff] [blame]122 },
123 {
124 0, 0xff, 0, 0xff, 0, 0xff,
125 },
126 {
Kalyan Thota79b217a2012-09-20 16:57:51 +0530[diff] [blame]127 0x0010, 0x00eb, 0x0010,
128 0x00f0, 0x0010, 0x00f0,
Kalyan Thota4c5e9262012-08-13 17:33:26 +0530[diff] [blame]129 },
130 },
131 },
132 {
133 .block = MDP_BLOCK_OVERLAY_2,
134 .csc_data = {
135 (0),
136 {
Kalyan Thota79b217a2012-09-20 16:57:51 +0530[diff] [blame]137 0x0083, 0x0102, 0x0032,
138 0x1fb5, 0x1f6c, 0x00e1,
139 0x00e1, 0x1f45, 0x1fdc,
Kalyan Thota4c5e9262012-08-13 17:33:26 +0530[diff] [blame]140 },
141 {
142 0x0, 0x0, 0x0,
143 },
144 {
Kalyan Thota79b217a2012-09-20 16:57:51 +0530[diff] [blame]145 0x0010, 0x0080, 0x0080,
Kalyan Thota4c5e9262012-08-13 17:33:26 +0530[diff] [blame]146 },
147 {
148 0, 0xff, 0, 0xff, 0, 0xff,
149 },
150 {
Kalyan Thota79b217a2012-09-20 16:57:51 +0530[diff] [blame]151 0x0010, 0x00eb, 0x0010,
152 0x00f0, 0x0010, 0x00f0,
Kalyan Thota4c5e9262012-08-13 17:33:26 +0530[diff] [blame]153 },
154 },
155 },
156 {
157 .block = MDP_BLOCK_DMA_S,
158 .csc_data = {
159 (0),
160 {
161 0x0200, 0x0000, 0x0000,
162 0x0000, 0x0200, 0x0000,
163 0x0000, 0x0000, 0x0200,
164 },
165 {
166 0x0, 0x0, 0x0,
167 },
168 {
169 0, 0, 0,
170 },
171 {
172 0, 0xff, 0, 0xff, 0, 0xff,
173 },
174 {
175 0, 0xff, 0, 0xff, 0, 0xff,
176 },
177 },
178 },
179};
180
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]181unsigned is_mdp4_hw_reset(void)
182{
183 unsigned hw_reset = 0;
184
185 /* Only revisions > v2.1 may be reset or powered off/on at runtime */
186 if (mdp_hw_revision > MDP4_REVISION_V2_1) {
187 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
188 hw_reset = !inpdw(MDP_BASE + 0x003c);
189 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
190 }
191
192 return hw_reset;
193}
194
195void mdp4_sw_reset(ulong bits)
196{
197 /* MDP cmd block enable */
198 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
199
200 bits &= 0x1f; /* 5 bits */
201 outpdw(MDP_BASE + 0x001c, bits); /* MDP_SW_RESET */
202
203 while (inpdw(MDP_BASE + 0x001c) & bits) /* self clear when complete */
204 ;
205 /* MDP cmd block disable */
206 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
207
208 MSM_FB_DEBUG("mdp4_sw_reset: 0x%x\n", (int)bits);
209}
210
211void mdp4_overlay_cfg(int overlayer, int blt_mode, int refresh, int direct_out)
212{
213 ulong bits = 0;
214
215 if (blt_mode)
216 bits |= (1 << 3);
217 refresh &= 0x03; /* 2 bites */
218 bits |= (refresh << 1);
219 direct_out &= 0x01;
220 bits |= direct_out;
221 /* MDP cmd block enable */
222 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
223
224
225 if (overlayer == MDP4_MIXER0)
226 outpdw(MDP_BASE + 0x10004, bits); /* MDP_OVERLAY0_CFG */
Rajesh Sastrulab52368b2011-12-22 12:09:17 -0800[diff] [blame]227 else if (overlayer == MDP4_MIXER1)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]228 outpdw(MDP_BASE + 0x18004, bits); /* MDP_OVERLAY1_CFG */
229
230 MSM_FB_DEBUG("mdp4_overlay_cfg: 0x%x\n",
231 (int)inpdw(MDP_BASE + 0x10004));
232 /* MDP cmd block disable */
233 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
234}
235
236void mdp4_display_intf_sel(int output, ulong intf)
237{
238 ulong bits, mask, data;
239 /* MDP cmd block enable */
240 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
241
242 bits = inpdw(MDP_BASE + 0x0038); /* MDP_DISP_INTF_SEL */
243
244 if (intf == DSI_VIDEO_INTF) {
245 data = 0x40; /* bit 6 */
246 intf = MDDI_LCDC_INTF;
247 if (output == SECONDARY_INTF_SEL) {
248 MSM_FB_INFO("%s: Illegal INTF selected, output=%d \
249 intf=%d\n", __func__, output, (int)intf);
250 }
251 } else if (intf == DSI_CMD_INTF) {
252 data = 0x80; /* bit 7 */
253 intf = MDDI_INTF;
254 if (output == EXTERNAL_INTF_SEL) {
255 MSM_FB_INFO("%s: Illegal INTF selected, output=%d \
256 intf=%d\n", __func__, output, (int)intf);
257 }
258 } else
259 data = 0;
260
261 mask = 0x03; /* 2 bits */
262 intf &= 0x03; /* 2 bits */
263
264 switch (output) {
265 case EXTERNAL_INTF_SEL:
266 intf <<= 4;
267 mask <<= 4;
268 break;
269 case SECONDARY_INTF_SEL:
270 intf &= 0x02; /* only MDDI and EBI2 support */
271 intf <<= 2;
272 mask <<= 2;
273 break;
274 default:
275 break;
276 }
277
278 intf |= data;
279 mask |= data;
280
281 bits &= ~mask;
282 bits |= intf;
283
284 outpdw(MDP_BASE + 0x0038, bits); /* MDP_DISP_INTF_SEL */
285 /* MDP cmd block disable */
286 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
287
288 MSM_FB_DEBUG("mdp4_display_intf_sel: 0x%x\n", (int)inpdw(MDP_BASE + 0x0038));
289}
290
291unsigned long mdp4_display_status(void)
292{
293 ulong status;
294 /* MDP cmd block enable */
295 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
296
297 status = inpdw(MDP_BASE + 0x0018) & 0x3ff; /* MDP_DISPLAY_STATUS */
298
299 /* MDP cmd block disable */
300 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
301 return status;
302}
303
304void mdp4_ebi2_lcd_setup(int lcd, ulong base, int ystride)
305{
306 /* always use memory map */
307 ystride &= 0x01fff; /* 13 bits */
308 /* MDP cmd block enable */
309 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
310
311 if (lcd == EBI2_LCD0) {
312 outpdw(MDP_BASE + 0x0060, base);/* MDP_EBI2_LCD0 */
313 outpdw(MDP_BASE + 0x0068, ystride);/* MDP_EBI2_LCD0_YSTRIDE */
314 } else {
315 outpdw(MDP_BASE + 0x0064, base);/* MDP_EBI2_LCD1 */
316 outpdw(MDP_BASE + 0x006c, ystride);/* MDP_EBI2_LCD1_YSTRIDE */
317 }
318 /* MDP cmd block disable */
319 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
320}
321
322void mdp4_mddi_setup(int mddi, unsigned long id)
323{
324 ulong bits;
325
326 if (mddi == MDDI_EXTERNAL_SET)
327 bits = 0x02;
328 else if (mddi == MDDI_SECONDARY_SET)
329 bits = 0x01;
330 else
331 bits = 0; /* PRIMARY_SET */
332
333 id <<= 16;
334
335 bits |= id;
336 /* MDP cmd block enable */
337 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
338
339 outpdw(MDP_BASE + 0x0090, bits); /* MDP_MDDI_PARAM_WR_SEL */
340 /* MDP cmd block disable */
341 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
342}
343
344int mdp_ppp_blit(struct fb_info *info, struct mdp_blit_req *req)
345{
346
347 /* not implemented yet */
348 return -1;
349}
350
351void mdp4_fetch_cfg(uint32 core_clk)
352{
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]353 uint32 dmap_data, vg_data;
354 char *base;
355 int i;
356 /* MDP cmd block enable */
357 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
358
Adrian Salido-Moreno3436dae2011-08-08 12:13:07 -0700[diff] [blame]359 if (mdp_rev >= MDP_REV_41 || core_clk >= 90000000) { /* 90 Mhz */
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]360 dmap_data = 0x47; /* 16 bytes-burst x 8 req */
361 vg_data = 0x47; /* 16 bytes-burs x 8 req */
362 } else {
363 dmap_data = 0x27; /* 8 bytes-burst x 8 req */
364 vg_data = 0x43; /* 16 bytes-burst x 4 req */
365 }
366
367 MSM_FB_DEBUG("mdp4_fetch_cfg: dmap=%x vg=%x\n",
368 dmap_data, vg_data);
369
370 /* dma_p fetch config */
371 outpdw(MDP_BASE + 0x91004, dmap_data);
372 /* dma_e fetch config */
373 outpdw(MDP_BASE + 0xB1004, dmap_data);
374
375 /*
376 * set up two vg pipes and two rgb pipes
377 */
378 base = MDP_BASE + MDP4_VIDEO_BASE;
379 for (i = 0; i < 4; i++) {
380 outpdw(base + 0x1004, vg_data);
381 base += MDP4_VIDEO_OFF;
382 }
383 /* MDP cmd block disable */
384 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
385}
386
387void mdp4_hw_init(void)
388{
389 ulong bits;
Ravishangar Kalyanam419051b2011-08-31 19:07:53 -0700[diff] [blame]390 uint32 clk_rate;
Kalyan Thota4c5e9262012-08-13 17:33:26 +0530[diff] [blame]391 int i;
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]392 /* MDP cmd block enable */
393 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
394
395#ifdef MDP4_ERROR
396 /*
397 * Issue software reset on DMA_P will casue DMA_P dma engine stall
398 * on LCDC mode. However DMA_P does not stall at MDDI mode.
399 * This need further investigation.
400 */
401 mdp4_sw_reset(0x17);
402#endif
403
kuogee hsieh4b910f22011-11-15 09:43:04 -0800[diff] [blame]404 if (mdp_rev > MDP_REV_41) {
405 /* mdp chip select controller */
406 outpdw(MDP_BASE + 0x00c0, CS_CONTROLLER_0);
407 outpdw(MDP_BASE + 0x00c4, CS_CONTROLLER_1);
408 }
409
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]410 mdp4_clear_lcdc();
411
412 mdp4_mixer_blend_init(0);
413 mdp4_mixer_blend_init(1);
414 mdp4_vg_qseed_init(0);
415 mdp4_vg_qseed_init(1);
416
Kalyan Thota4c5e9262012-08-13 17:33:26 +0530[diff] [blame]417 for (i = 0; i < CSC_MAX_BLOCKS; i++)
418 mdp4_csc_config(&csc_cfg_matrix[i]);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]419
Ravishangar Kalyaname7833e22011-07-22 16:20:19 -0700[diff] [blame]420 if (mdp_rev <= MDP_REV_41) {
421 mdp4_mixer_gc_lut_setup(0);
422 mdp4_mixer_gc_lut_setup(1);
423 }
424
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]425 mdp4_vg_igc_lut_setup(0);
426 mdp4_vg_igc_lut_setup(1);
427
428 mdp4_rgb_igc_lut_setup(0);
429 mdp4_rgb_igc_lut_setup(1);
430
431 outp32(MDP_EBI2_PORTMAP_MODE, 0x3);
432
433 /* system interrupts */
434
435 bits = mdp_intr_mask;
436 outpdw(MDP_BASE + 0x0050, bits);/* enable specififed interrupts */
437
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]438 /* For the max read pending cmd config below, if the MDP clock */
439 /* is less than the AXI clock, then we must use 3 pending */
440 /* pending requests. Otherwise, we should use 8 pending requests. */
441 /* In the future we should do this detection automatically. */
442
443 /* max read pending cmd config */
444 outpdw(MDP_BASE + 0x004c, 0x02222); /* 3 pending requests */
Siddhartha Agrawalee8d2272012-09-12 18:47:41 -0700[diff] [blame]445 outpdw(MDP_BASE + 0x0400, 0x7FF);
446 outpdw(MDP_BASE + 0x0404, 0x30050);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]447
448#ifndef CONFIG_FB_MSM_OVERLAY
449 /* both REFRESH_MODE and DIRECT_OUT are ignored at BLT mode */
450 mdp4_overlay_cfg(MDP4_MIXER0, OVERLAY_MODE_BLT, 0, 0);
451 mdp4_overlay_cfg(MDP4_MIXER1, OVERLAY_MODE_BLT, 0, 0);
452#endif
453
Ravishangar Kalyanam419051b2011-08-31 19:07:53 -0700[diff] [blame]454 clk_rate = mdp_get_core_clk();
455 mdp4_fetch_cfg(clk_rate);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]456
Kuogee Hsieh56f85302013-01-18 10:55:36 -0800[diff] [blame]457 if (mdp_rev >= MDP_REV_42) {
458 /* MDP_LAYERMIXER_IN_CFG_UPDATE_METHOD */
459 outpdw(MDP_BASE + 0x100fc, 0x01);
460 }
461
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]462 /* Mark hardware as initialized. Only revisions > v2.1 have a register
463 * for tracking core reset status. */
464 if (mdp_hw_revision > MDP4_REVISION_V2_1)
465 outpdw(MDP_BASE + 0x003c, 1);
Ravishangar Kalyanam419051b2011-08-31 19:07:53 -0700[diff] [blame]466
467 /* MDP cmd block disable */
468 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]469}
470
471
472void mdp4_clear_lcdc(void)
473{
474 uint32 bits;
475
476 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
477
478 bits = inpdw(MDP_BASE + 0xc0000);
479 if (bits & 0x01) { /* enabled already */
480 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
481 return;
482 }
483
484 outpdw(MDP_BASE + 0xc0004, 0); /* vsync ctrl out */
485 outpdw(MDP_BASE + 0xc0008, 0); /* vsync period */
486 outpdw(MDP_BASE + 0xc000c, 0); /* vsync pusle width */
487 outpdw(MDP_BASE + 0xc0010, 0); /* lcdc display HCTL */
488 outpdw(MDP_BASE + 0xc0014, 0); /* lcdc display v start */
489 outpdw(MDP_BASE + 0xc0018, 0); /* lcdc display v end */
490 outpdw(MDP_BASE + 0xc001c, 0); /* lcdc active hctl */
491 outpdw(MDP_BASE + 0xc0020, 0); /* lcdc active v start */
492 outpdw(MDP_BASE + 0xc0024, 0); /* lcdc active v end */
493 outpdw(MDP_BASE + 0xc0028, 0); /* lcdc board color */
494 outpdw(MDP_BASE + 0xc002c, 0); /* lcdc underflow ctrl */
495 outpdw(MDP_BASE + 0xc0030, 0); /* lcdc hsync skew */
496 outpdw(MDP_BASE + 0xc0034, 0); /* lcdc test ctl */
497 outpdw(MDP_BASE + 0xc0038, 0); /* lcdc ctl polarity */
498
499 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
500}
501
502irqreturn_t mdp4_isr(int irq, void *ptr)
503{
504 uint32 isr, mask, panel;
505 struct mdp_dma_data *dma;
Carl Vanderlip7b8b6402012-03-01 10:58:03 -0800[diff] [blame]506 struct mdp_hist_mgmt *mgmt = NULL;
Carl Vanderlip7b8b6402012-03-01 10:58:03 -0800[diff] [blame]507 int i, ret;
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]508
509 mdp_is_in_isr = TRUE;
510
511 /* complete all the reads before reading the interrupt
512 * status register - eliminate effects of speculative
513 * reads by the cpu
514 */
515 rmb();
516 isr = inpdw(MDP_INTR_STATUS);
517 if (isr == 0)
518 goto out;
519
520 mdp4_stat.intr_tot++;
521 mask = inpdw(MDP_INTR_ENABLE);
522 outpdw(MDP_INTR_CLEAR, isr);
523
524 if (isr & INTR_PRIMARY_INTF_UDERRUN) {
kuogee hsieh1ce7e4c2012-01-13 14:05:54 -0800[diff] [blame]525 pr_debug("%s: UNDERRUN -- primary\n", __func__);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]526 mdp4_stat.intr_underrun_p++;
527 /* When underun occurs mdp clear the histogram registers
528 that are set before in hw_init so restore them back so
529 that histogram works.*/
Carl Vanderlip7b8b6402012-03-01 10:58:03 -0800[diff] [blame]530 for (i = 0; i < MDP_HIST_MGMT_MAX; i++) {
531 mgmt = mdp_hist_mgmt_array[i];
532 if (!mgmt)
533 continue;
Carl Vanderlip7b8b6402012-03-01 10:58:03 -0800[diff] [blame]534 mgmt->mdp_is_hist_valid = FALSE;
Carl Vanderlip7b8b6402012-03-01 10:58:03 -0800[diff] [blame]535 }
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]536 }
537
kuogee hsieh1ce7e4c2012-01-13 14:05:54 -0800[diff] [blame]538 if (isr & INTR_EXTERNAL_INTF_UDERRUN) {
539 pr_debug("%s: UNDERRUN -- external\n", __func__);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]540 mdp4_stat.intr_underrun_e++;
kuogee hsieh1ce7e4c2012-01-13 14:05:54 -0800[diff] [blame]541 }
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]542
543 isr &= mask;
544
545 if (isr == 0)
546 goto out;
547
548 panel = mdp4_overlay_panel_list();
Kuogee Hsieh586fd162012-02-14 15:24:16 -0800[diff] [blame]549
550 if (isr & INTR_DMA_P_DONE) {
551 mdp4_stat.intr_dma_p++;
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]552 dma = &dma2_data;
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]553 if (panel & MDP4_PANEL_LCDC)
Kuogee Hsieh586fd162012-02-14 15:24:16 -0800[diff] [blame]554 mdp4_dmap_done_lcdc(0);
555#ifdef CONFIG_FB_MSM_OVERLAY
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]556#ifdef CONFIG_FB_MSM_MIPI_DSI
557 else if (panel & MDP4_PANEL_DSI_VIDEO)
Kuogee Hsieh586fd162012-02-14 15:24:16 -0800[diff] [blame]558 mdp4_dmap_done_dsi_video(0);
559 else if (panel & MDP4_PANEL_DSI_CMD)
560 mdp4_dmap_done_dsi_cmd(0);
561#else
562 else { /* MDDI */
563 mdp4_dma_p_done_mddi(dma);
564 mdp_pipe_ctrl(MDP_DMA2_BLOCK,
565 MDP_BLOCK_POWER_OFF, TRUE);
566 complete(&dma->comp);
567 }
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]568#endif
Kuogee Hsieh586fd162012-02-14 15:24:16 -0800[diff] [blame]569#else
570 else {
571 spin_lock(&mdp_spin_lock);
572 dma->busy = FALSE;
573 spin_unlock(&mdp_spin_lock);
574 complete(&dma->comp);
575 }
576#endif
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]577 }
Kuogee Hsieh586fd162012-02-14 15:24:16 -0800[diff] [blame]578 if (isr & INTR_DMA_S_DONE) {
579 mdp4_stat.intr_dma_s++;
580#if defined(CONFIG_FB_MSM_OVERLAY) && defined(CONFIG_FB_MSM_MDDI)
581 dma = &dma2_data;
582#else
583 dma = &dma_s_data;
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]584#endif
kuogee hsieh40a43402011-10-04 08:48:18 -0700[diff] [blame]585
Kuogee Hsieh586fd162012-02-14 15:24:16 -0800[diff] [blame]586 dma->busy = FALSE;
587 mdp_pipe_ctrl(MDP_DMA_S_BLOCK,
588 MDP_BLOCK_POWER_OFF, TRUE);
589 complete(&dma->comp);
590 }
591 if (isr & INTR_DMA_E_DONE) {
592 mdp4_stat.intr_dma_e++;
593 if (panel & MDP4_PANEL_DTV)
594 mdp4_dmae_done_dtv();
595 }
kuogee hsieh40a43402011-10-04 08:48:18 -0700[diff] [blame]596#ifdef CONFIG_FB_MSM_OVERLAY
597 if (isr & INTR_OVERLAY0_DONE) {
598 mdp4_stat.intr_overlay0++;
599 dma = &dma2_data;
600 if (panel & (MDP4_PANEL_LCDC | MDP4_PANEL_DSI_VIDEO)) {
601 /* disable LCDC interrupt */
kuogee hsieh40a43402011-10-04 08:48:18 -0700[diff] [blame]602 if (panel & MDP4_PANEL_LCDC)
Kuogee Hsieh586fd162012-02-14 15:24:16 -0800[diff] [blame]603 mdp4_overlay0_done_lcdc(0);
kuogee hsieh40a43402011-10-04 08:48:18 -0700[diff] [blame]604#ifdef CONFIG_FB_MSM_MIPI_DSI
605 else if (panel & MDP4_PANEL_DSI_VIDEO)
Kuogee Hsieh586fd162012-02-14 15:24:16 -0800[diff] [blame]606 mdp4_overlay0_done_dsi_video(0);
kuogee hsieh40a43402011-10-04 08:48:18 -0700[diff] [blame]607#endif
608 } else { /* MDDI, DSI_CMD */
609#ifdef CONFIG_FB_MSM_MIPI_DSI
610 if (panel & MDP4_PANEL_DSI_CMD)
Kuogee Hsieh586fd162012-02-14 15:24:16 -0800[diff] [blame]611 mdp4_overlay0_done_dsi_cmd(0);
kuogee hsieh40a43402011-10-04 08:48:18 -0700[diff] [blame]612#else
613 if (panel & MDP4_PANEL_MDDI)
614 mdp4_overlay0_done_mddi(dma);
615#endif
616 }
617 mdp_hw_cursor_done();
618 }
619 if (isr & INTR_OVERLAY1_DONE) {
620 mdp4_stat.intr_overlay1++;
621 /* disable DTV interrupt */
622 dma = &dma_e_data;
623 spin_lock(&mdp_spin_lock);
624 mdp_intr_mask &= ~INTR_OVERLAY1_DONE;
625 outp32(MDP_INTR_ENABLE, mdp_intr_mask);
626 dma->waiting = FALSE;
627 spin_unlock(&mdp_spin_lock);
628#if defined(CONFIG_FB_MSM_DTV)
629 if (panel & MDP4_PANEL_DTV)
630 mdp4_overlay1_done_dtv();
631#endif
632#if defined(CONFIG_FB_MSM_TVOUT)
633 if (panel & MDP4_PANEL_ATV)
634 mdp4_overlay1_done_atv();
635#endif
Rajesh Sastrulab52368b2011-12-22 12:09:17 -0800[diff] [blame]636 }
Vinay Kalia27020d12011-10-14 17:50:29 -0700[diff] [blame]637#if defined(CONFIG_FB_MSM_WRITEBACK_MSM_PANEL)
Rajesh Sastrulab52368b2011-12-22 12:09:17 -0800[diff] [blame]638 if (isr & INTR_OVERLAY2_DONE) {
639 mdp4_stat.intr_overlay2++;
640 /* disable DTV interrupt */
Vinay Kalia27020d12011-10-14 17:50:29 -0700[diff] [blame]641 if (panel & MDP4_PANEL_WRITEBACK)
Kuogee Hsieh357b9c72012-09-05 09:05:58 -0700[diff] [blame]642 mdp4_overlay2_done_wfd(&dma_wb_data);
kuogee hsieh40a43402011-10-04 08:48:18 -0700[diff] [blame]643 }
Rajesh Sastrulab52368b2011-12-22 12:09:17 -0800[diff] [blame]644#endif
kuogee hsieh40a43402011-10-04 08:48:18 -0700[diff] [blame]645#endif /* OVERLAY */
646
Kuogee Hsieh586fd162012-02-14 15:24:16 -0800[diff] [blame]647 if (isr & INTR_PRIMARY_VSYNC) {
648 mdp4_stat.intr_vsync_p++;
649 if (panel & MDP4_PANEL_LCDC)
650 mdp4_primary_vsync_lcdc();
651 else if (panel & MDP4_PANEL_DSI_VIDEO)
652 mdp4_primary_vsync_dsi_video();
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]653 }
Kuogee Hsieh586fd162012-02-14 15:24:16 -0800[diff] [blame]654#ifdef CONFIG_FB_MSM_DTV
655 if (isr & INTR_EXTERNAL_VSYNC) {
656 mdp4_stat.intr_vsync_e++;
657 if (panel & MDP4_PANEL_DTV)
658 mdp4_external_vsync_dtv();
659 }
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]660#endif
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]661 if (isr & INTR_DMA_P_HISTOGRAM) {
kuogee hsieh0948c682011-10-31 16:50:43 -0700[diff] [blame]662 mdp4_stat.intr_histogram++;
Carl Vanderlip7b8b6402012-03-01 10:58:03 -0800[diff] [blame]663 ret = mdp_histogram_block2mgmt(MDP_BLOCK_DMA_P, &mgmt);
664 if (!ret)
665 mdp_histogram_handle_isr(mgmt);
666 }
667 if (isr & INTR_DMA_S_HISTOGRAM) {
668 mdp4_stat.intr_histogram++;
669 ret = mdp_histogram_block2mgmt(MDP_BLOCK_DMA_S, &mgmt);
670 if (!ret)
671 mdp_histogram_handle_isr(mgmt);
672 }
673 if (isr & INTR_VG1_HISTOGRAM) {
674 mdp4_stat.intr_histogram++;
675 ret = mdp_histogram_block2mgmt(MDP_BLOCK_VG_1, &mgmt);
676 if (!ret)
677 mdp_histogram_handle_isr(mgmt);
678 }
679 if (isr & INTR_VG2_HISTOGRAM) {
680 mdp4_stat.intr_histogram++;
681 ret = mdp_histogram_block2mgmt(MDP_BLOCK_VG_2, &mgmt);
682 if (!ret)
683 mdp_histogram_handle_isr(mgmt);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]684 }
Kuogee Hsieh586fd162012-02-14 15:24:16 -0800[diff] [blame]685 if (isr & INTR_PRIMARY_RDPTR) {
686 mdp4_stat.intr_rdptr++;
687 mdp4_primary_rdptr();
688 }
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]689
690out:
691 mdp_is_in_isr = FALSE;
692
693 return IRQ_HANDLED;
694}
695
696
697/*
698 * QSEED tables
699 */
700
701static uint32 vg_qseed_table0[] = {
702 0x5556aaff, 0x00000000, 0x00000000, 0x00000000
703};
704
705static uint32 vg_qseed_table1[] = {
Carl Vanderlipd89c0e72012-03-28 10:17:20 -0700[diff] [blame]706 0x00000000, 0x20000000,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]707};
708
709static uint32 vg_qseed_table2[] = {
710 0x02000000, 0x00000000, 0x01ff0ff9, 0x00000008,
711 0x01fb0ff2, 0x00000013, 0x01f50fed, 0x0ffe0020,
712 0x01ed0fe8, 0x0ffd002e, 0x01e30fe4, 0x0ffb003e,
713 0x01d80fe1, 0x0ff9004e, 0x01cb0fde, 0x0ff70060,
714 0x01bc0fdc, 0x0ff40074, 0x01ac0fdb, 0x0ff20087,
715 0x019a0fdb, 0x0fef009c, 0x01870fdb, 0x0fed00b1,
716 0x01740fdb, 0x0fea00c7, 0x01600fdc, 0x0fe700dd,
717 0x014b0fdd, 0x0fe500f3, 0x01350fdf, 0x0fe30109,
718 0x01200fe0, 0x0fe00120, 0x01090fe3, 0x0fdf0135,
719 0x00f30fe5, 0x0fdd014b, 0x00dd0fe7, 0x0fdc0160,
720 0x00c70fea, 0x0fdb0174, 0x00b10fed, 0x0fdb0187,
721 0x009c0fef, 0x0fdb019a, 0x00870ff2, 0x0fdb01ac,
722 0x00740ff4, 0x0fdc01bc, 0x00600ff7, 0x0fde01cb,
723 0x004e0ff9, 0x0fe101d8, 0x003e0ffb, 0x0fe401e3,
724 0x002e0ffd, 0x0fe801ed, 0x00200ffe, 0x0fed01f5,
725 0x00130000, 0x0ff201fb, 0x00080000, 0x0ff901ff,
726
727 0x02000000, 0x00000000, 0x02000000, 0x00000000,
728 0x02000000, 0x00000000, 0x02000000, 0x00000000,
729 0x02000000, 0x00000000, 0x02000000, 0x00000000,
730 0x02000000, 0x00000000, 0x02000000, 0x00000000,
731 0x02000000, 0x00000000, 0x02000000, 0x00000000,
732 0x02000000, 0x00000000, 0x02000000, 0x00000000,
733 0x02000000, 0x00000000, 0x02000000, 0x00000000,
734 0x02000000, 0x00000000, 0x02000000, 0x00000000,
735 0x02000000, 0x00000000, 0x02000000, 0x00000000,
736 0x02000000, 0x00000000, 0x02000000, 0x00000000,
737 0x02000000, 0x00000000, 0x02000000, 0x00000000,
738 0x02000000, 0x00000000, 0x02000000, 0x00000000,
739 0x02000000, 0x00000000, 0x02000000, 0x00000000,
740 0x02000000, 0x00000000, 0x02000000, 0x00000000,
741 0x02000000, 0x00000000, 0x02000000, 0x00000000,
742 0x02000000, 0x00000000, 0x02000000, 0x00000000,
743
744 0x02000000, 0x00000000, 0x01fc0ff9, 0x0ffe000d,
745 0x01f60ff3, 0x0ffb001c, 0x01ef0fed, 0x0ff9002b,
746 0x01e60fe8, 0x0ff6003c, 0x01dc0fe4, 0x0ff3004d,
747 0x01d00fe0, 0x0ff1005f, 0x01c30fde, 0x0fee0071,
748 0x01b50fdb, 0x0feb0085, 0x01a70fd9, 0x0fe80098,
749 0x01960fd8, 0x0fe600ac, 0x01850fd7, 0x0fe300c1,
750 0x01730fd7, 0x0fe100d5, 0x01610fd7, 0x0fdf00e9,
751 0x014e0fd8, 0x0fdd00fd, 0x013b0fd8, 0x0fdb0112,
752 0x01250fda, 0x0fda0127, 0x01120fdb, 0x0fd8013b,
753 0x00fd0fdd, 0x0fd8014e, 0x00e90fdf, 0x0fd70161,
754 0x00d50fe1, 0x0fd70173, 0x00c10fe3, 0x0fd70185,
755 0x00ac0fe6, 0x0fd80196, 0x00980fe8, 0x0fd901a7,
756 0x00850feb, 0x0fdb01b5, 0x00710fee, 0x0fde01c3,
757 0x005f0ff1, 0x0fe001d0, 0x004d0ff3, 0x0fe401dc,
758 0x003c0ff6, 0x0fe801e6, 0x002b0ff9, 0x0fed01ef,
759 0x001c0ffb, 0x0ff301f6, 0x000d0ffe, 0x0ff901fc,
760
761 0x020f0034, 0x0f7a0043, 0x01e80023, 0x0fa8004d,
762 0x01d30016, 0x0fbe0059, 0x01c6000a, 0x0fc90067,
763 0x01bd0000, 0x0fce0075, 0x01b50ff7, 0x0fcf0085,
764 0x01ae0fee, 0x0fcf0095, 0x01a70fe6, 0x0fcd00a6,
765 0x019d0fe0, 0x0fcb00b8, 0x01940fd9, 0x0fc900ca,
766 0x01890fd4, 0x0fc700dc, 0x017d0fcf, 0x0fc600ee,
767 0x01700fcc, 0x0fc40100, 0x01620fc9, 0x0fc40111,
768 0x01540fc6, 0x0fc30123, 0x01430fc5, 0x0fc40134,
769 0x01340fc4, 0x0fc50143, 0x01230fc3, 0x0fc60154,
770 0x01110fc4, 0x0fc90162, 0x01000fc4, 0x0fcc0170,
771 0x00ee0fc6, 0x0fcf017d, 0x00dc0fc7, 0x0fd40189,
772 0x00ca0fc9, 0x0fd90194, 0x00b80fcb, 0x0fe0019d,
773 0x00a60fcd, 0x0fe601a7, 0x00950fcf, 0x0fee01ae,
774 0x00850fcf, 0x0ff701b5, 0x00750fce, 0x000001bd,
775 0x00670fc9, 0x000a01c6, 0x00590fbe, 0x001601d3,
776 0x004d0fa8, 0x002301e8, 0x00430f7a, 0x0034020f,
777
778 0x015c005e, 0x0fde0068, 0x015c0054, 0x0fdd0073,
779 0x015b004b, 0x0fdc007e, 0x015a0042, 0x0fdb0089,
780 0x01590039, 0x0fda0094, 0x01560030, 0x0fda00a0,
781 0x01530028, 0x0fda00ab, 0x014f0020, 0x0fda00b7,
782 0x014a0019, 0x0fdb00c2, 0x01450011, 0x0fdc00ce,
783 0x013e000b, 0x0fde00d9, 0x01390004, 0x0fdf00e4,
784 0x01310ffe, 0x0fe200ef, 0x01290ff9, 0x0fe400fa,
785 0x01200ff4, 0x0fe80104, 0x01180fef, 0x0feb010e,
786 0x010e0feb, 0x0fef0118, 0x01040fe8, 0x0ff40120,
787 0x00fa0fe4, 0x0ff90129, 0x00ef0fe2, 0x0ffe0131,
788 0x00e40fdf, 0x00040139, 0x00d90fde, 0x000b013e,
789 0x00ce0fdc, 0x00110145, 0x00c20fdb, 0x0019014a,
790 0x00b70fda, 0x0020014f, 0x00ab0fda, 0x00280153,
791 0x00a00fda, 0x00300156, 0x00940fda, 0x00390159,
792 0x00890fdb, 0x0042015a, 0x007e0fdc, 0x004b015b,
793 0x00730fdd, 0x0054015c, 0x00680fde, 0x005e015c,
794
795 0x01300068, 0x0ff80070, 0x01300060, 0x0ff80078,
796 0x012f0059, 0x0ff80080, 0x012d0052, 0x0ff80089,
797 0x012b004b, 0x0ff90091, 0x01290044, 0x0ff9009a,
798 0x0126003d, 0x0ffa00a3, 0x01220037, 0x0ffb00ac,
799 0x011f0031, 0x0ffc00b4, 0x011a002b, 0x0ffe00bd,
800 0x01150026, 0x000000c5, 0x010f0021, 0x000200ce,
801 0x010a001c, 0x000400d6, 0x01030018, 0x000600df,
802 0x00fd0014, 0x000900e6, 0x00f60010, 0x000c00ee,
803 0x00ee000c, 0x001000f6, 0x00e60009, 0x001400fd,
804 0x00df0006, 0x00180103, 0x00d60004, 0x001c010a,
805 0x00ce0002, 0x0021010f, 0x00c50000, 0x00260115,
806 0x00bd0ffe, 0x002b011a, 0x00b40ffc, 0x0031011f,
807 0x00ac0ffb, 0x00370122, 0x00a30ffa, 0x003d0126,
808 0x009a0ff9, 0x00440129, 0x00910ff9, 0x004b012b,
809 0x00890ff8, 0x0052012d, 0x00800ff8, 0x0059012f,
810 0x00780ff8, 0x00600130, 0x00700ff8, 0x00680130,
811
812 0x01050079, 0x0003007f, 0x01040073, 0x00030086,
813 0x0103006d, 0x0004008c, 0x01030066, 0x00050092,
814 0x01010060, 0x00060099, 0x0100005a, 0x0007009f,
815 0x00fe0054, 0x000900a5, 0x00fa004f, 0x000b00ac,
816 0x00f80049, 0x000d00b2, 0x00f50044, 0x000f00b8,
817 0x00f2003f, 0x001200bd, 0x00ef0039, 0x001500c3,
818 0x00ea0035, 0x001800c9, 0x00e60030, 0x001c00ce,
819 0x00e3002b, 0x001f00d3, 0x00dd0027, 0x002300d9,
820 0x00d90023, 0x002700dd, 0x00d3001f, 0x002b00e3,
821 0x00ce001c, 0x003000e6, 0x00c90018, 0x003500ea,
822 0x00c30015, 0x003900ef, 0x00bd0012, 0x003f00f2,
823 0x00b8000f, 0x004400f5, 0x00b2000d, 0x004900f8,
824 0x00ac000b, 0x004f00fa, 0x00a50009, 0x005400fe,
825 0x009f0007, 0x005a0100, 0x00990006, 0x00600101,
826 0x00920005, 0x00660103, 0x008c0004, 0x006d0103,
827 0x00860003, 0x00730104, 0x007f0003, 0x00790105,
828
829 0x00cf0088, 0x001d008c, 0x00ce0084, 0x0020008e,
830 0x00cd0080, 0x00210092, 0x00cd007b, 0x00240094,
831 0x00ca0077, 0x00270098, 0x00c90073, 0x0029009b,
832 0x00c8006f, 0x002c009d, 0x00c6006b, 0x002f00a0,
833 0x00c50067, 0x003200a2, 0x00c30062, 0x003600a5,
834 0x00c0005f, 0x003900a8, 0x00c0005b, 0x003b00aa,
835 0x00be0057, 0x003e00ad, 0x00ba0054, 0x004200b0,
836 0x00b90050, 0x004500b2, 0x00b7004c, 0x004900b4,
837 0x00b40049, 0x004c00b7, 0x00b20045, 0x005000b9,
838 0x00b00042, 0x005400ba, 0x00ad003e, 0x005700be,
839 0x00aa003b, 0x005b00c0, 0x00a80039, 0x005f00c0,
840 0x00a50036, 0x006200c3, 0x00a20032, 0x006700c5,
841 0x00a0002f, 0x006b00c6, 0x009d002c, 0x006f00c8,
842 0x009b0029, 0x007300c9, 0x00980027, 0x007700ca,
843 0x00940024, 0x007b00cd, 0x00920021, 0x008000cd,
844 0x008e0020, 0x008400ce, 0x008c001d, 0x008800cf,
845
846 0x008e0083, 0x006b0084, 0x008d0083, 0x006c0084,
847 0x008d0082, 0x006d0084, 0x008d0081, 0x006d0085,
848 0x008d0080, 0x006e0085, 0x008c007f, 0x006f0086,
849 0x008b007f, 0x00700086, 0x008b007e, 0x00710086,
850 0x008b007d, 0x00720086, 0x008a007d, 0x00730086,
851 0x008a007c, 0x00730087, 0x008a007b, 0x00740087,
852 0x0089007b, 0x00750087, 0x008a0079, 0x00750088,
853 0x008a0078, 0x00760088, 0x008a0077, 0x00770088,
854 0x00880077, 0x0077008a, 0x00880076, 0x0078008a,
855 0x00880075, 0x0079008a, 0x00870075, 0x007b0089,
856 0x00870074, 0x007b008a, 0x00870073, 0x007c008a,
857 0x00860073, 0x007d008a, 0x00860072, 0x007d008b,
858 0x00860071, 0x007e008b, 0x00860070, 0x007f008b,
859 0x0086006f, 0x007f008c, 0x0085006e, 0x0080008d,
860 0x0085006d, 0x0081008d, 0x0084006d, 0x0082008d,
861 0x0084006c, 0x0083008d, 0x0084006b, 0x0083008e,
862
863 0x023c0fe2, 0x00000fe2, 0x023a0fdb, 0x00000feb,
864 0x02360fd3, 0x0fff0ff8, 0x022e0fcf, 0x0ffc0007,
865 0x02250fca, 0x0ffa0017, 0x021a0fc6, 0x0ff70029,
866 0x020c0fc4, 0x0ff4003c, 0x01fd0fc1, 0x0ff10051,
867 0x01eb0fc0, 0x0fed0068, 0x01d80fc0, 0x0fe9007f,
868 0x01c30fc1, 0x0fe50097, 0x01ac0fc2, 0x0fe200b0,
869 0x01960fc3, 0x0fdd00ca, 0x017e0fc5, 0x0fd900e4,
870 0x01650fc8, 0x0fd500fe, 0x014b0fcb, 0x0fd20118,
871 0x01330fcd, 0x0fcd0133, 0x01180fd2, 0x0fcb014b,
872 0x00fe0fd5, 0x0fc80165, 0x00e40fd9, 0x0fc5017e,
873 0x00ca0fdd, 0x0fc30196, 0x00b00fe2, 0x0fc201ac,
874 0x00970fe5, 0x0fc101c3, 0x007f0fe9, 0x0fc001d8,
875 0x00680fed, 0x0fc001eb, 0x00510ff1, 0x0fc101fd,
876 0x003c0ff4, 0x0fc4020c, 0x00290ff7, 0x0fc6021a,
877 0x00170ffa, 0x0fca0225, 0x00070ffc, 0x0fcf022e,
878 0x0ff80fff, 0x0fd30236, 0x0feb0000, 0x0fdb023a,
879
880 0x02780fc4, 0x00000fc4, 0x02770fbc, 0x0fff0fce,
881 0x02710fb5, 0x0ffe0fdc, 0x02690fb0, 0x0ffa0fed,
882 0x025f0fab, 0x0ff70fff, 0x02500fa8, 0x0ff30015,
883 0x02410fa6, 0x0fef002a, 0x022f0fa4, 0x0feb0042,
884 0x021a0fa4, 0x0fe5005d, 0x02040fa5, 0x0fe10076,
885 0x01eb0fa7, 0x0fdb0093, 0x01d20fa9, 0x0fd600af,
886 0x01b80fab, 0x0fd000cd, 0x019d0faf, 0x0fca00ea,
887 0x01810fb2, 0x0fc50108, 0x01620fb7, 0x0fc10126,
888 0x01440fbb, 0x0fbb0146, 0x01260fc1, 0x0fb70162,
889 0x01080fc5, 0x0fb20181, 0x00ea0fca, 0x0faf019d,
890 0x00cd0fd0, 0x0fab01b8, 0x00af0fd6, 0x0fa901d2,
891 0x00930fdb, 0x0fa701eb, 0x00760fe1, 0x0fa50204,
892 0x005d0fe5, 0x0fa4021a, 0x00420feb, 0x0fa4022f,
893 0x002a0fef, 0x0fa60241, 0x00150ff3, 0x0fa80250,
894 0x0fff0ff7, 0x0fab025f, 0x0fed0ffa, 0x0fb00269,
895 0x0fdc0ffe, 0x0fb50271, 0x0fce0fff, 0x0fbc0277,
896
897 0x02a00fb0, 0x00000fb0, 0x029e0fa8, 0x0fff0fbb,
898 0x02980fa1, 0x0ffd0fca, 0x028f0f9c, 0x0ff90fdc,
899 0x02840f97, 0x0ff50ff0, 0x02740f94, 0x0ff10007,
900 0x02640f92, 0x0fec001e, 0x02500f91, 0x0fe70038,
901 0x023a0f91, 0x0fe00055, 0x02220f92, 0x0fdb0071,
902 0x02080f95, 0x0fd4008f, 0x01ec0f98, 0x0fce00ae,
903 0x01cf0f9b, 0x0fc700cf, 0x01b10f9f, 0x0fc100ef,
904 0x01920fa4, 0x0fbb010f, 0x01710faa, 0x0fb50130,
905 0x01520fae, 0x0fae0152, 0x01300fb5, 0x0faa0171,
906 0x010f0fbb, 0x0fa40192, 0x00ef0fc1, 0x0f9f01b1,
907 0x00cf0fc7, 0x0f9b01cf, 0x00ae0fce, 0x0f9801ec,
908 0x008f0fd4, 0x0f950208, 0x00710fdb, 0x0f920222,
909 0x00550fe0, 0x0f91023a, 0x00380fe7, 0x0f910250,
910 0x001e0fec, 0x0f920264, 0x00070ff1, 0x0f940274,
911 0x0ff00ff5, 0x0f970284, 0x0fdc0ff9, 0x0f9c028f,
912 0x0fca0ffd, 0x0fa10298, 0x0fbb0fff, 0x0fa8029e,
913
914 0x02c80f9c, 0x00000f9c, 0x02c70f94, 0x0ffe0fa7,
915 0x02c10f8c, 0x0ffc0fb7, 0x02b70f87, 0x0ff70fcb,
916 0x02aa0f83, 0x0ff30fe0, 0x02990f80, 0x0fee0ff9,
917 0x02870f7f, 0x0fe80012, 0x02720f7e, 0x0fe2002e,
918 0x025a0f7e, 0x0fdb004d, 0x02400f80, 0x0fd5006b,
919 0x02230f84, 0x0fcd008c, 0x02050f87, 0x0fc700ad,
920 0x01e60f8b, 0x0fbf00d0, 0x01c60f90, 0x0fb700f3,
921 0x01a30f96, 0x0fb00117, 0x01800f9c, 0x0faa013a,
922 0x015d0fa2, 0x0fa2015f, 0x013a0faa, 0x0f9c0180,
923 0x01170fb0, 0x0f9601a3, 0x00f30fb7, 0x0f9001c6,
924 0x00d00fbf, 0x0f8b01e6, 0x00ad0fc7, 0x0f870205,
925 0x008c0fcd, 0x0f840223, 0x006b0fd5, 0x0f800240,
926 0x004d0fdb, 0x0f7e025a, 0x002e0fe2, 0x0f7e0272,
927 0x00120fe8, 0x0f7f0287, 0x0ff90fee, 0x0f800299,
928 0x0fe00ff3, 0x0f8302aa, 0x0fcb0ff7, 0x0f8702b7,
929 0x0fb70ffc, 0x0f8c02c1, 0x0fa70ffe, 0x0f9402c7,
930
931 0x02f00f88, 0x00000f88, 0x02ee0f80, 0x0ffe0f94,
932 0x02e70f78, 0x0ffc0fa5, 0x02dd0f73, 0x0ff60fba,
933 0x02ce0f6f, 0x0ff20fd1, 0x02be0f6c, 0x0feb0feb,
934 0x02aa0f6b, 0x0fe50006, 0x02940f6a, 0x0fde0024,
935 0x02790f6c, 0x0fd60045, 0x025e0f6e, 0x0fcf0065,
936 0x023f0f72, 0x0fc60089, 0x021d0f77, 0x0fbf00ad,
937 0x01fd0f7b, 0x0fb600d2, 0x01da0f81, 0x0fad00f8,
938 0x01b50f87, 0x0fa6011e, 0x018f0f8f, 0x0f9e0144,
939 0x016b0f95, 0x0f95016b, 0x01440f9e, 0x0f8f018f,
940 0x011e0fa6, 0x0f8701b5, 0x00f80fad, 0x0f8101da,
941 0x00d20fb6, 0x0f7b01fd, 0x00ad0fbf, 0x0f77021d,
942 0x00890fc6, 0x0f72023f, 0x00650fcf, 0x0f6e025e,
943 0x00450fd6, 0x0f6c0279, 0x00240fde, 0x0f6a0294,
944 0x00060fe5, 0x0f6b02aa, 0x0feb0feb, 0x0f6c02be,
945 0x0fd10ff2, 0x0f6f02ce, 0x0fba0ff6, 0x0f7302dd,
946 0x0fa50ffc, 0x0f7802e7, 0x0f940ffe, 0x0f8002ee,
947
948 0x03180f74, 0x00000f74, 0x03160f6b, 0x0ffe0f81,
949 0x030e0f64, 0x0ffb0f93, 0x03030f5f, 0x0ff50fa9,
950 0x02f40f5b, 0x0ff00fc1, 0x02e20f58, 0x0fe90fdd,
951 0x02cd0f57, 0x0fe20ffa, 0x02b60f57, 0x0fda0019,
952 0x02990f59, 0x0fd1003d, 0x027b0f5c, 0x0fc90060,
953 0x02590f61, 0x0fc00086, 0x02370f66, 0x0fb700ac,
954 0x02130f6b, 0x0fae00d4, 0x01ee0f72, 0x0fa400fc,
955 0x01c70f79, 0x0f9b0125, 0x019f0f81, 0x0f93014d,
956 0x01760f89, 0x0f890178, 0x014d0f93, 0x0f81019f,
957 0x01250f9b, 0x0f7901c7, 0x00fc0fa4, 0x0f7201ee,
958 0x00d40fae, 0x0f6b0213, 0x00ac0fb7, 0x0f660237,
959 0x00860fc0, 0x0f610259, 0x00600fc9, 0x0f5c027b,
960 0x003d0fd1, 0x0f590299, 0x00190fda, 0x0f5702b6,
961 0x0ffa0fe2, 0x0f5702cd, 0x0fdd0fe9, 0x0f5802e2,
962 0x0fc10ff0, 0x0f5b02f4, 0x0fa90ff5, 0x0f5f0303,
963 0x0f930ffb, 0x0f64030e, 0x0f810ffe, 0x0f6b0316,
964
965 0x03400f60, 0x00000f60, 0x033e0f57, 0x0ffe0f6d,
966 0x03370f4f, 0x0ffa0f80, 0x032a0f4b, 0x0ff30f98,
967 0x031a0f46, 0x0fee0fb2, 0x03070f44, 0x0fe60fcf,
968 0x02f10f44, 0x0fde0fed, 0x02d70f44, 0x0fd6000f,
969 0x02b80f46, 0x0fcc0036, 0x02990f4a, 0x0fc3005a,
970 0x02750f4f, 0x0fb90083, 0x02500f55, 0x0fb000ab,
971 0x022a0f5b, 0x0fa500d6, 0x02020f63, 0x0f9a0101,
972 0x01d80f6b, 0x0f91012c, 0x01ae0f74, 0x0f870157,
973 0x01840f7c, 0x0f7c0184, 0x01570f87, 0x0f7401ae,
974 0x012c0f91, 0x0f6b01d8, 0x01010f9a, 0x0f630202,
975 0x00d60fa5, 0x0f5b022a, 0x00ab0fb0, 0x0f550250,
976 0x00830fb9, 0x0f4f0275, 0x005a0fc3, 0x0f4a0299,
977 0x00360fcc, 0x0f4602b8, 0x000f0fd6, 0x0f4402d7,
978 0x0fed0fde, 0x0f4402f1, 0x0fcf0fe6, 0x0f440307,
979 0x0fb20fee, 0x0f46031a, 0x0f980ff3, 0x0f4b032a,
980 0x0f800ffa, 0x0f4f0337, 0x0f6d0ffe, 0x0f57033e,
981
982 0x02000000, 0x00000000, 0x01ff0ff9, 0x00000008,
983 0x01fb0ff2, 0x00000013, 0x01f50fed, 0x0ffe0020,
984 0x01ed0fe8, 0x0ffd002e, 0x01e30fe4, 0x0ffb003e,
985 0x01d80fe1, 0x0ff9004e, 0x01cb0fde, 0x0ff70060,
986 0x01bc0fdc, 0x0ff40074, 0x01ac0fdb, 0x0ff20087,
987 0x019a0fdb, 0x0fef009c, 0x01870fdb, 0x0fed00b1,
988 0x01740fdb, 0x0fea00c7, 0x01600fdc, 0x0fe700dd,
989 0x014b0fdd, 0x0fe500f3, 0x01350fdf, 0x0fe30109,
990 0x01200fe0, 0x0fe00120, 0x01090fe3, 0x0fdf0135,
991 0x00f30fe5, 0x0fdd014b, 0x00dd0fe7, 0x0fdc0160,
992 0x00c70fea, 0x0fdb0174, 0x00b10fed, 0x0fdb0187,
993 0x009c0fef, 0x0fdb019a, 0x00870ff2, 0x0fdb01ac,
994 0x00740ff4, 0x0fdc01bc, 0x00600ff7, 0x0fde01cb,
995 0x004e0ff9, 0x0fe101d8, 0x003e0ffb, 0x0fe401e3,
996 0x002e0ffd, 0x0fe801ed, 0x00200ffe, 0x0fed01f5,
997 0x00130000, 0x0ff201fb, 0x00080000, 0x0ff901ff,
998
999 0x02000000, 0x00000000, 0x02000000, 0x00000000,
1000 0x02000000, 0x00000000, 0x02000000, 0x00000000,
1001 0x02000000, 0x00000000, 0x02000000, 0x00000000,
1002 0x02000000, 0x00000000, 0x02000000, 0x00000000,
1003 0x02000000, 0x00000000, 0x02000000, 0x00000000,
1004 0x02000000, 0x00000000, 0x02000000, 0x00000000,
1005 0x02000000, 0x00000000, 0x02000000, 0x00000000,
1006 0x02000000, 0x00000000, 0x02000000, 0x00000000,
1007 0x02000000, 0x00000000, 0x02000000, 0x00000000,
1008 0x02000000, 0x00000000, 0x02000000, 0x00000000,
1009 0x02000000, 0x00000000, 0x02000000, 0x00000000,
1010 0x02000000, 0x00000000, 0x02000000, 0x00000000,
1011 0x02000000, 0x00000000, 0x02000000, 0x00000000,
1012 0x02000000, 0x00000000, 0x02000000, 0x00000000,
1013 0x02000000, 0x00000000, 0x02000000, 0x00000000,
1014 0x02000000, 0x00000000, 0x02000000, 0x00000000,
1015
1016 0x02000000, 0x00000000, 0x01fc0ff9, 0x0ffe000d,
1017 0x01f60ff3, 0x0ffb001c, 0x01ef0fed, 0x0ff9002b,
1018 0x01e60fe8, 0x0ff6003c, 0x01dc0fe4, 0x0ff3004d,
1019 0x01d00fe0, 0x0ff1005f, 0x01c30fde, 0x0fee0071,
1020 0x01b50fdb, 0x0feb0085, 0x01a70fd9, 0x0fe80098,
1021 0x01960fd8, 0x0fe600ac, 0x01850fd7, 0x0fe300c1,
1022 0x01730fd7, 0x0fe100d5, 0x01610fd7, 0x0fdf00e9,
1023 0x014e0fd8, 0x0fdd00fd, 0x013b0fd8, 0x0fdb0112,
1024 0x01250fda, 0x0fda0127, 0x01120fdb, 0x0fd8013b,
1025 0x00fd0fdd, 0x0fd8014e, 0x00e90fdf, 0x0fd70161,
1026 0x00d50fe1, 0x0fd70173, 0x00c10fe3, 0x0fd70185,
1027 0x00ac0fe6, 0x0fd80196, 0x00980fe8, 0x0fd901a7,
1028 0x00850feb, 0x0fdb01b5, 0x00710fee, 0x0fde01c3,
1029 0x005f0ff1, 0x0fe001d0, 0x004d0ff3, 0x0fe401dc,
1030 0x003c0ff6, 0x0fe801e6, 0x002b0ff9, 0x0fed01ef,
1031 0x001c0ffb, 0x0ff301f6, 0x000d0ffe, 0x0ff901fc,
1032
1033 0x020f0034, 0x0f7a0043, 0x01e80023, 0x0fa8004d,
1034 0x01d30016, 0x0fbe0059, 0x01c6000a, 0x0fc90067,
1035 0x01bd0000, 0x0fce0075, 0x01b50ff7, 0x0fcf0085,
1036 0x01ae0fee, 0x0fcf0095, 0x01a70fe6, 0x0fcd00a6,
1037 0x019d0fe0, 0x0fcb00b8, 0x01940fd9, 0x0fc900ca,
1038 0x01890fd4, 0x0fc700dc, 0x017d0fcf, 0x0fc600ee,
1039 0x01700fcc, 0x0fc40100, 0x01620fc9, 0x0fc40111,
1040 0x01540fc6, 0x0fc30123, 0x01430fc5, 0x0fc40134,
1041 0x01340fc4, 0x0fc50143, 0x01230fc3, 0x0fc60154,
1042 0x01110fc4, 0x0fc90162, 0x01000fc4, 0x0fcc0170,
1043 0x00ee0fc6, 0x0fcf017d, 0x00dc0fc7, 0x0fd40189,
1044 0x00ca0fc9, 0x0fd90194, 0x00b80fcb, 0x0fe0019d,
1045 0x00a60fcd, 0x0fe601a7, 0x00950fcf, 0x0fee01ae,
1046 0x00850fcf, 0x0ff701b5, 0x00750fce, 0x000001bd,
1047 0x00670fc9, 0x000a01c6, 0x00590fbe, 0x001601d3,
1048 0x004d0fa8, 0x002301e8, 0x00430f7a, 0x0034020f,
1049
1050 0x015c005e, 0x0fde0068, 0x015c0054, 0x0fdd0073,
1051 0x015b004b, 0x0fdc007e, 0x015a0042, 0x0fdb0089,
1052 0x01590039, 0x0fda0094, 0x01560030, 0x0fda00a0,
1053 0x01530028, 0x0fda00ab, 0x014f0020, 0x0fda00b7,
1054 0x014a0019, 0x0fdb00c2, 0x01450011, 0x0fdc00ce,
1055 0x013e000b, 0x0fde00d9, 0x01390004, 0x0fdf00e4,
1056 0x01310ffe, 0x0fe200ef, 0x01290ff9, 0x0fe400fa,
1057 0x01200ff4, 0x0fe80104, 0x01180fef, 0x0feb010e,
1058 0x010e0feb, 0x0fef0118, 0x01040fe8, 0x0ff40120,
1059 0x00fa0fe4, 0x0ff90129, 0x00ef0fe2, 0x0ffe0131,
1060 0x00e40fdf, 0x00040139, 0x00d90fde, 0x000b013e,
1061 0x00ce0fdc, 0x00110145, 0x00c20fdb, 0x0019014a,
1062 0x00b70fda, 0x0020014f, 0x00ab0fda, 0x00280153,
1063 0x00a00fda, 0x00300156, 0x00940fda, 0x00390159,
1064 0x00890fdb, 0x0042015a, 0x007e0fdc, 0x004b015b,
1065 0x00730fdd, 0x0054015c, 0x00680fde, 0x005e015c,
1066
1067 0x01300068, 0x0ff80070, 0x01300060, 0x0ff80078,
1068 0x012f0059, 0x0ff80080, 0x012d0052, 0x0ff80089,
1069 0x012b004b, 0x0ff90091, 0x01290044, 0x0ff9009a,
1070 0x0126003d, 0x0ffa00a3, 0x01220037, 0x0ffb00ac,
1071 0x011f0031, 0x0ffc00b4, 0x011a002b, 0x0ffe00bd,
1072 0x01150026, 0x000000c5, 0x010f0021, 0x000200ce,
1073 0x010a001c, 0x000400d6, 0x01030018, 0x000600df,
1074 0x00fd0014, 0x000900e6, 0x00f60010, 0x000c00ee,
1075 0x00ee000c, 0x001000f6, 0x00e60009, 0x001400fd,
1076 0x00df0006, 0x00180103, 0x00d60004, 0x001c010a,
1077 0x00ce0002, 0x0021010f, 0x00c50000, 0x00260115,
1078 0x00bd0ffe, 0x002b011a, 0x00b40ffc, 0x0031011f,
1079 0x00ac0ffb, 0x00370122, 0x00a30ffa, 0x003d0126,
1080 0x009a0ff9, 0x00440129, 0x00910ff9, 0x004b012b,
1081 0x00890ff8, 0x0052012d, 0x00800ff8, 0x0059012f,
1082 0x00780ff8, 0x00600130, 0x00700ff8, 0x00680130,
1083
1084 0x01050079, 0x0003007f, 0x01040073, 0x00030086,
1085 0x0103006d, 0x0004008c, 0x01030066, 0x00050092,
1086 0x01010060, 0x00060099, 0x0100005a, 0x0007009f,
1087 0x00fe0054, 0x000900a5, 0x00fa004f, 0x000b00ac,
1088 0x00f80049, 0x000d00b2, 0x00f50044, 0x000f00b8,
1089 0x00f2003f, 0x001200bd, 0x00ef0039, 0x001500c3,
1090 0x00ea0035, 0x001800c9, 0x00e60030, 0x001c00ce,
1091 0x00e3002b, 0x001f00d3, 0x00dd0027, 0x002300d9,
1092 0x00d90023, 0x002700dd, 0x00d3001f, 0x002b00e3,
1093 0x00ce001c, 0x003000e6, 0x00c90018, 0x003500ea,
1094 0x00c30015, 0x003900ef, 0x00bd0012, 0x003f00f2,
1095 0x00b8000f, 0x004400f5, 0x00b2000d, 0x004900f8,
1096 0x00ac000b, 0x004f00fa, 0x00a50009, 0x005400fe,
1097 0x009f0007, 0x005a0100, 0x00990006, 0x00600101,
1098 0x00920005, 0x00660103, 0x008c0004, 0x006d0103,
1099 0x00860003, 0x00730104, 0x007f0003, 0x00790105,
1100
1101 0x00cf0088, 0x001d008c, 0x00ce0084, 0x0020008e,
1102 0x00cd0080, 0x00210092, 0x00cd007b, 0x00240094,
1103 0x00ca0077, 0x00270098, 0x00c90073, 0x0029009b,
1104 0x00c8006f, 0x002c009d, 0x00c6006b, 0x002f00a0,
1105 0x00c50067, 0x003200a2, 0x00c30062, 0x003600a5,
1106 0x00c0005f, 0x003900a8, 0x00c0005b, 0x003b00aa,
1107 0x00be0057, 0x003e00ad, 0x00ba0054, 0x004200b0,
1108 0x00b90050, 0x004500b2, 0x00b7004c, 0x004900b4,
1109 0x00b40049, 0x004c00b7, 0x00b20045, 0x005000b9,
1110 0x00b00042, 0x005400ba, 0x00ad003e, 0x005700be,
1111 0x00aa003b, 0x005b00c0, 0x00a80039, 0x005f00c0,
1112 0x00a50036, 0x006200c3, 0x00a20032, 0x006700c5,
1113 0x00a0002f, 0x006b00c6, 0x009d002c, 0x006f00c8,
1114 0x009b0029, 0x007300c9, 0x00980027, 0x007700ca,
1115 0x00940024, 0x007b00cd, 0x00920021, 0x008000cd,
1116 0x008e0020, 0x008400ce, 0x008c001d, 0x008800cf,
1117
1118 0x008e0083, 0x006b0084, 0x008d0083, 0x006c0084,
1119 0x008d0082, 0x006d0084, 0x008d0081, 0x006d0085,
1120 0x008d0080, 0x006e0085, 0x008c007f, 0x006f0086,
1121 0x008b007f, 0x00700086, 0x008b007e, 0x00710086,
1122 0x008b007d, 0x00720086, 0x008a007d, 0x00730086,
1123 0x008a007c, 0x00730087, 0x008a007b, 0x00740087,
1124 0x0089007b, 0x00750087, 0x008a0079, 0x00750088,
1125 0x008a0078, 0x00760088, 0x008a0077, 0x00770088,
1126 0x00880077, 0x0077008a, 0x00880076, 0x0078008a,
1127 0x00880075, 0x0079008a, 0x00870075, 0x007b0089,
1128 0x00870074, 0x007b008a, 0x00870073, 0x007c008a,
1129 0x00860073, 0x007d008a, 0x00860072, 0x007d008b,
1130 0x00860071, 0x007e008b, 0x00860070, 0x007f008b,
1131 0x0086006f, 0x007f008c, 0x0085006e, 0x0080008d,
1132 0x0085006d, 0x0081008d, 0x0084006d, 0x0082008d,
1133 0x0084006c, 0x0083008d, 0x0084006b, 0x0083008e,
1134
1135 0x023c0fe2, 0x00000fe2, 0x023a0fdb, 0x00000feb,
1136 0x02360fd3, 0x0fff0ff8, 0x022e0fcf, 0x0ffc0007,
1137 0x02250fca, 0x0ffa0017, 0x021a0fc6, 0x0ff70029,
1138 0x020c0fc4, 0x0ff4003c, 0x01fd0fc1, 0x0ff10051,
1139 0x01eb0fc0, 0x0fed0068, 0x01d80fc0, 0x0fe9007f,
1140 0x01c30fc1, 0x0fe50097, 0x01ac0fc2, 0x0fe200b0,
1141 0x01960fc3, 0x0fdd00ca, 0x017e0fc5, 0x0fd900e4,
1142 0x01650fc8, 0x0fd500fe, 0x014b0fcb, 0x0fd20118,
1143 0x01330fcd, 0x0fcd0133, 0x01180fd2, 0x0fcb014b,
1144 0x00fe0fd5, 0x0fc80165, 0x00e40fd9, 0x0fc5017e,
1145 0x00ca0fdd, 0x0fc30196, 0x00b00fe2, 0x0fc201ac,
1146 0x00970fe5, 0x0fc101c3, 0x007f0fe9, 0x0fc001d8,
1147 0x00680fed, 0x0fc001eb, 0x00510ff1, 0x0fc101fd,
1148 0x003c0ff4, 0x0fc4020c, 0x00290ff7, 0x0fc6021a,
1149 0x00170ffa, 0x0fca0225, 0x00070ffc, 0x0fcf022e,
1150 0x0ff80fff, 0x0fd30236, 0x0feb0000, 0x0fdb023a,
1151
1152 0x02780fc4, 0x00000fc4, 0x02770fbc, 0x0fff0fce,
1153 0x02710fb5, 0x0ffe0fdc, 0x02690fb0, 0x0ffa0fed,
1154 0x025f0fab, 0x0ff70fff, 0x02500fa8, 0x0ff30015,
1155 0x02410fa6, 0x0fef002a, 0x022f0fa4, 0x0feb0042,
1156 0x021a0fa4, 0x0fe5005d, 0x02040fa5, 0x0fe10076,
1157 0x01eb0fa7, 0x0fdb0093, 0x01d20fa9, 0x0fd600af,
1158 0x01b80fab, 0x0fd000cd, 0x019d0faf, 0x0fca00ea,
1159 0x01810fb2, 0x0fc50108, 0x01620fb7, 0x0fc10126,
1160 0x01440fbb, 0x0fbb0146, 0x01260fc1, 0x0fb70162,
1161 0x01080fc5, 0x0fb20181, 0x00ea0fca, 0x0faf019d,
1162 0x00cd0fd0, 0x0fab01b8, 0x00af0fd6, 0x0fa901d2,
1163 0x00930fdb, 0x0fa701eb, 0x00760fe1, 0x0fa50204,
1164 0x005d0fe5, 0x0fa4021a, 0x00420feb, 0x0fa4022f,
1165 0x002a0fef, 0x0fa60241, 0x00150ff3, 0x0fa80250,
1166 0x0fff0ff7, 0x0fab025f, 0x0fed0ffa, 0x0fb00269,
1167 0x0fdc0ffe, 0x0fb50271, 0x0fce0fff, 0x0fbc0277,
1168
1169 0x02a00fb0, 0x00000fb0, 0x029e0fa8, 0x0fff0fbb,
1170 0x02980fa1, 0x0ffd0fca, 0x028f0f9c, 0x0ff90fdc,
1171 0x02840f97, 0x0ff50ff0, 0x02740f94, 0x0ff10007,
1172 0x02640f92, 0x0fec001e, 0x02500f91, 0x0fe70038,
1173 0x023a0f91, 0x0fe00055, 0x02220f92, 0x0fdb0071,
1174 0x02080f95, 0x0fd4008f, 0x01ec0f98, 0x0fce00ae,
1175 0x01cf0f9b, 0x0fc700cf, 0x01b10f9f, 0x0fc100ef,
1176 0x01920fa4, 0x0fbb010f, 0x01710faa, 0x0fb50130,
1177 0x01520fae, 0x0fae0152, 0x01300fb5, 0x0faa0171,
1178 0x010f0fbb, 0x0fa40192, 0x00ef0fc1, 0x0f9f01b1,
1179 0x00cf0fc7, 0x0f9b01cf, 0x00ae0fce, 0x0f9801ec,
1180 0x008f0fd4, 0x0f950208, 0x00710fdb, 0x0f920222,
1181 0x00550fe0, 0x0f91023a, 0x00380fe7, 0x0f910250,
1182 0x001e0fec, 0x0f920264, 0x00070ff1, 0x0f940274,
1183 0x0ff00ff5, 0x0f970284, 0x0fdc0ff9, 0x0f9c028f,
1184 0x0fca0ffd, 0x0fa10298, 0x0fbb0fff, 0x0fa8029e,
1185
1186 0x02c80f9c, 0x00000f9c, 0x02c70f94, 0x0ffe0fa7,
1187 0x02c10f8c, 0x0ffc0fb7, 0x02b70f87, 0x0ff70fcb,
1188 0x02aa0f83, 0x0ff30fe0, 0x02990f80, 0x0fee0ff9,
1189 0x02870f7f, 0x0fe80012, 0x02720f7e, 0x0fe2002e,
1190 0x025a0f7e, 0x0fdb004d, 0x02400f80, 0x0fd5006b,
1191 0x02230f84, 0x0fcd008c, 0x02050f87, 0x0fc700ad,
1192 0x01e60f8b, 0x0fbf00d0, 0x01c60f90, 0x0fb700f3,
1193 0x01a30f96, 0x0fb00117, 0x01800f9c, 0x0faa013a,
1194 0x015d0fa2, 0x0fa2015f, 0x013a0faa, 0x0f9c0180,
1195 0x01170fb0, 0x0f9601a3, 0x00f30fb7, 0x0f9001c6,
1196 0x00d00fbf, 0x0f8b01e6, 0x00ad0fc7, 0x0f870205,
1197 0x008c0fcd, 0x0f840223, 0x006b0fd5, 0x0f800240,
1198 0x004d0fdb, 0x0f7e025a, 0x002e0fe2, 0x0f7e0272,
1199 0x00120fe8, 0x0f7f0287, 0x0ff90fee, 0x0f800299,
1200 0x0fe00ff3, 0x0f8302aa, 0x0fcb0ff7, 0x0f8702b7,
1201 0x0fb70ffc, 0x0f8c02c1, 0x0fa70ffe, 0x0f9402c7,
1202
1203 0x02f00f88, 0x00000f88, 0x02ee0f80, 0x0ffe0f94,
1204 0x02e70f78, 0x0ffc0fa5, 0x02dd0f73, 0x0ff60fba,
1205 0x02ce0f6f, 0x0ff20fd1, 0x02be0f6c, 0x0feb0feb,
1206 0x02aa0f6b, 0x0fe50006, 0x02940f6a, 0x0fde0024,
1207 0x02790f6c, 0x0fd60045, 0x025e0f6e, 0x0fcf0065,
1208 0x023f0f72, 0x0fc60089, 0x021d0f77, 0x0fbf00ad,
1209 0x01fd0f7b, 0x0fb600d2, 0x01da0f81, 0x0fad00f8,
1210 0x01b50f87, 0x0fa6011e, 0x018f0f8f, 0x0f9e0144,
1211 0x016b0f95, 0x0f95016b, 0x01440f9e, 0x0f8f018f,
1212 0x011e0fa6, 0x0f8701b5, 0x00f80fad, 0x0f8101da,
1213 0x00d20fb6, 0x0f7b01fd, 0x00ad0fbf, 0x0f77021d,
1214 0x00890fc6, 0x0f72023f, 0x00650fcf, 0x0f6e025e,
1215 0x00450fd6, 0x0f6c0279, 0x00240fde, 0x0f6a0294,
1216 0x00060fe5, 0x0f6b02aa, 0x0feb0feb, 0x0f6c02be,
1217 0x0fd10ff2, 0x0f6f02ce, 0x0fba0ff6, 0x0f7302dd,
1218 0x0fa50ffc, 0x0f7802e7, 0x0f940ffe, 0x0f8002ee,
1219
1220 0x03180f74, 0x00000f74, 0x03160f6b, 0x0ffe0f81,
1221 0x030e0f64, 0x0ffb0f93, 0x03030f5f, 0x0ff50fa9,
1222 0x02f40f5b, 0x0ff00fc1, 0x02e20f58, 0x0fe90fdd,
1223 0x02cd0f57, 0x0fe20ffa, 0x02b60f57, 0x0fda0019,
1224 0x02990f59, 0x0fd1003d, 0x027b0f5c, 0x0fc90060,
1225 0x02590f61, 0x0fc00086, 0x02370f66, 0x0fb700ac,
1226 0x02130f6b, 0x0fae00d4, 0x01ee0f72, 0x0fa400fc,
1227 0x01c70f79, 0x0f9b0125, 0x019f0f81, 0x0f93014d,
1228 0x01760f89, 0x0f890178, 0x014d0f93, 0x0f81019f,
1229 0x01250f9b, 0x0f7901c7, 0x00fc0fa4, 0x0f7201ee,
1230 0x00d40fae, 0x0f6b0213, 0x00ac0fb7, 0x0f660237,
1231 0x00860fc0, 0x0f610259, 0x00600fc9, 0x0f5c027b,
1232 0x003d0fd1, 0x0f590299, 0x00190fda, 0x0f5702b6,
1233 0x0ffa0fe2, 0x0f5702cd, 0x0fdd0fe9, 0x0f5802e2,
1234 0x0fc10ff0, 0x0f5b02f4, 0x0fa90ff5, 0x0f5f0303,
1235 0x0f930ffb, 0x0f64030e, 0x0f810ffe, 0x0f6b0316,
1236
1237 0x03400f60, 0x00000f60, 0x033e0f57, 0x0ffe0f6d,
1238 0x03370f4f, 0x0ffa0f80, 0x032a0f4b, 0x0ff30f98,
1239 0x031a0f46, 0x0fee0fb2, 0x03070f44, 0x0fe60fcf,
1240 0x02f10f44, 0x0fde0fed, 0x02d70f44, 0x0fd6000f,
1241 0x02b80f46, 0x0fcc0036, 0x02990f4a, 0x0fc3005a,
1242 0x02750f4f, 0x0fb90083, 0x02500f55, 0x0fb000ab,
1243 0x022a0f5b, 0x0fa500d6, 0x02020f63, 0x0f9a0101,
1244 0x01d80f6b, 0x0f91012c, 0x01ae0f74, 0x0f870157,
1245 0x01840f7c, 0x0f7c0184, 0x01570f87, 0x0f7401ae,
1246 0x012c0f91, 0x0f6b01d8, 0x01010f9a, 0x0f630202,
1247 0x00d60fa5, 0x0f5b022a, 0x00ab0fb0, 0x0f550250,
1248 0x00830fb9, 0x0f4f0275, 0x005a0fc3, 0x0f4a0299,
1249 0x00360fcc, 0x0f4602b8, 0x000f0fd6, 0x0f4402d7,
1250 0x0fed0fde, 0x0f4402f1, 0x0fcf0fe6, 0x0f440307,
1251 0x0fb20fee, 0x0f46031a, 0x0f980ff3, 0x0f4b032a,
1252 0x0f800ffa, 0x0f4f0337, 0x0f6d0ffe, 0x0f57033e
1253};
1254
1255
1256#define MDP4_QSEED_TABLE0_OFF 0x8100
1257#define MDP4_QSEED_TABLE1_OFF 0x8200
1258#define MDP4_QSEED_TABLE2_OFF 0x9000
1259
1260void mdp4_vg_qseed_init(int vp_num)
1261{
1262 uint32 *off;
1263 int i, voff;
1264
1265 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
1266
1267 voff = MDP4_VIDEO_OFF * vp_num;
1268 off = (uint32 *)(MDP_BASE + MDP4_VIDEO_BASE + voff +
1269 MDP4_QSEED_TABLE0_OFF);
1270 for (i = 0; i < (sizeof(vg_qseed_table0) / sizeof(uint32)); i++) {
1271 outpdw(off, vg_qseed_table0[i]);
1272 off++;
1273 /* This code is added to workaround the 1K Boundary AXI
1274 Interleave operations from Scorpion that can potentially
1275 corrupt the QSEED table. The idea is to complete the prevous
1276 to the buffer before making the next write when address is
1277 1KB aligned to ensure the write has been committed prior to
1278 next instruction write that can go out from the secondary AXI
1279 port.This happens also because of the expected write sequence
1280 from QSEED table, where LSP has to be written first then the
1281 MSP to trigger both to write out to SRAM, if this has not been
1282 the expectation, then corruption wouldn't have happened.*/
1283
1284 if (!((uint32)off & 0x3FF))
1285 wmb();
1286 }
1287
1288 off = (uint32 *)(MDP_BASE + MDP4_VIDEO_BASE + voff +
1289 MDP4_QSEED_TABLE1_OFF);
1290 for (i = 0; i < (sizeof(vg_qseed_table1) / sizeof(uint32)); i++) {
1291 outpdw(off, vg_qseed_table1[i]);
1292 off++;
1293 if (!((uint32)off & 0x3FF))
1294 wmb();
1295 }
1296
1297 off = (uint32 *)(MDP_BASE + MDP4_VIDEO_BASE + voff +
1298 MDP4_QSEED_TABLE2_OFF);
1299 for (i = 0; i < (sizeof(vg_qseed_table2) / sizeof(uint32)); i++) {
1300 outpdw(off, vg_qseed_table2[i]);
1301 off++;
1302 if (!((uint32)off & 0x3FF))
1303 wmb();
1304 }
1305
1306 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
1307
1308}
1309
1310void mdp4_mixer_blend_init(mixer_num)
1311{
1312 unsigned char *overlay_base;
1313 int off;
1314
1315 if (mixer_num) /* mixer number, /dev/fb0, /dev/fb1 */
1316 overlay_base = MDP_BASE + MDP4_OVERLAYPROC1_BASE;/* 0x18000 */
1317 else
1318 overlay_base = MDP_BASE + MDP4_OVERLAYPROC0_BASE;/* 0x10000 */
1319
1320 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
1321
1322 /* stage 0 to stage 2 */
1323 off = 0;
1324 outpdw(overlay_base + off + 0x104, 0x010);
1325 outpdw(overlay_base + off + 0x108, 0xff);/* FG */
1326 outpdw(overlay_base + off + 0x10c, 0x00);/* BG */
1327
1328 off += 0x20;
1329 outpdw(overlay_base + off + 0x104, 0x010);
1330 outpdw(overlay_base + off + 0x108, 0xff);/* FG */
1331 outpdw(overlay_base + off + 0x10c, 0x00);/* BG */
1332
1333 off += 0x20;
1334 outpdw(overlay_base + off + 0x104, 0x010);
1335 outpdw(overlay_base + off + 0x108, 0xff);/* FG */
1336 outpdw(overlay_base + off + 0x10c, 0x00);/* BG */
1337
1338 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
1339}
1340
Carl Vanderlipfa1de672011-12-05 12:37:59 -0800[diff] [blame]1341struct mdp_csc_cfg mdp_csc_convert[4] = {
1342 { /*RGB2RGB*/
1343 0,
1344 {
1345 0x0200, 0x0000, 0x0000,
1346 0x0000, 0x0200, 0x0000,
1347 0x0000, 0x0000, 0x0200,
1348 },
1349 { 0x0, 0x0, 0x0, },
1350 { 0x0, 0x0, 0x0, },
1351 { 0x0, 0xff, 0x0, 0xff, 0x0, 0xff, },
1352 { 0x0, 0xff, 0x0, 0xff, 0x0, 0xff, },
1353 },
1354 { /*YUV2RGB*/
1355 0,
1356 {
1357 0x0254, 0x0000, 0x0331,
1358 0x0254, 0xff37, 0xfe60,
1359 0x0254, 0x0409, 0x0000,
1360 },
1361 { 0xfff0, 0xff80, 0xff80, },
1362 { 0x0, 0x0, 0x0, },
1363 { 0x0, 0xff, 0x0, 0xff, 0x0, 0xff, },
1364 { 0x0, 0xff, 0x0, 0xff, 0x0, 0xff, },
1365 },
1366 { /*RGB2YUV*/
1367 0,
1368 {
1369 0x0083, 0x0102, 0x0032,
1370 0x1fb5, 0x1f6c, 0x00e1,
1371 0x00e1, 0x1f45, 0x1fdc
1372 },
1373 { 0x0, 0x0, 0x0, },
1374 { 0x0010, 0x0080, 0x0080, },
1375 { 0x0, 0xff, 0x0, 0xff, 0x0, 0xff, },
1376 { 0x0010, 0x00eb, 0x0010, 0x00f0, 0x0010, 0x00f0, },
1377 },
1378 { /*YUV2YUV ???*/
1379 0,
1380 {
1381 0x0200, 0x0000, 0x0000,
1382 0x0000, 0x0200, 0x0000,
1383 0x0000, 0x0000, 0x0200,
1384 },
1385 { 0x0, 0x0, 0x0, },
1386 { 0x0, 0x0, 0x0, },
1387 { 0x0, 0xff, 0x0, 0xff, 0x0, 0xff, },
1388 { 0x0, 0xff, 0x0, 0xff, 0x0, 0xff, },
1389 },
1390};
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]1391
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]1392
Nagamalleswararao Ganji4b991722011-01-28 13:24:34 -0800[diff] [blame]1393void mdp4_vg_csc_update(struct mdp_csc *p)
1394{
1395 struct mdp4_overlay_pipe *pipe;
Kalyan Thota4c5e9262012-08-13 17:33:26 +0530[diff] [blame]1396 uint32_t block = 0;
1397 int i = 0;
Nagamalleswararao Ganji4b991722011-01-28 13:24:34 -0800[diff] [blame]1398
1399 pipe = mdp4_overlay_ndx2pipe(p->id);
1400 if (pipe == NULL) {
1401 pr_err("%s: p->id = %d Error\n", __func__, p->id);
1402 return;
1403 }
Kalyan Thota4c5e9262012-08-13 17:33:26 +0530[diff] [blame]1404 if (pipe->pipe_num == OVERLAY_PIPE_VG1)
1405 block = MDP_BLOCK_VG_1;
1406 else if (pipe->pipe_num == OVERLAY_PIPE_VG2)
1407 block = MDP_BLOCK_VG_2;
Rajesh Sastrulab52368b2011-12-22 12:09:17 -0800[diff] [blame]1408 else
Kalyan Thota4c5e9262012-08-13 17:33:26 +0530[diff] [blame]1409 return;
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]1410
Kalyan Thota4c5e9262012-08-13 17:33:26 +0530[diff] [blame]1411 for (i = 0; i < CSC_MAX_BLOCKS; i++) {
1412 if (csc_cfg_matrix[i].block == block)
1413 break;
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]1414 }
Kalyan Thota4c5e9262012-08-13 17:33:26 +0530[diff] [blame]1415 if (i == CSC_MAX_BLOCKS)
1416 return;
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]1417
Kalyan Thota4c5e9262012-08-13 17:33:26 +0530[diff] [blame]1418 memcpy(&csc_cfg_matrix[i].csc_data.csc_mv, p->csc_mv,
1419 sizeof(p->csc_mv));
1420 memcpy(&csc_cfg_matrix[i].csc_data.csc_pre_bv, p->csc_pre_bv,
1421 sizeof(p->csc_pre_bv));
1422 memcpy(&csc_cfg_matrix[i].csc_data.csc_post_bv, p->csc_post_bv,
1423 sizeof(p->csc_post_bv));
1424 memcpy(&csc_cfg_matrix[i].csc_data.csc_pre_lv, p->csc_pre_lv,
1425 sizeof(p->csc_pre_lv));
1426 memcpy(&csc_cfg_matrix[i].csc_data.csc_post_lv, p->csc_post_lv,
1427 sizeof(p->csc_post_lv));
1428 csc_cfg_matrix[i].csc_data.flags = MDP_CSC_FLAG_YUV_OUT;
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]1429
Kalyan Thota4c5e9262012-08-13 17:33:26 +0530[diff] [blame]1430 mdp4_csc_config(&csc_cfg_matrix[i]);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]1431
Carl Vanderlipdaa069f2011-11-28 14:09:24 -0800[diff] [blame]1432}
1433
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700[diff] [blame]1434char gc_lut[] = {
1435 0x0, 0x1, 0x2, 0x2, 0x3, 0x4, 0x5, 0x6,
1436 0x6, 0x7, 0x8, 0x9, 0xA, 0xA, 0xB, 0xC,
1437 0xD, 0xD, 0xE, 0xF, 0xF, 0x10, 0x10, 0x11,
1438 0x12, 0x12, 0x13, 0x13, 0x14, 0x14, 0x15, 0x15,
1439 0x16, 0x16, 0x17, 0x17, 0x17, 0x18, 0x18, 0x19,
1440 0x19, 0x19, 0x1A, 0x1A, 0x1B, 0x1B, 0x1B, 0x1C,
1441 0x1C, 0x1D, 0x1D, 0x1D, 0x1E, 0x1E, 0x1E, 0x1F,
1442 0x1F, 0x1F, 0x20, 0x20, 0x20, 0x21, 0x21, 0x21,
1443 0x22, 0x22, 0x22, 0x22, 0x23, 0x23, 0x23, 0x24,
1444 0x24, 0x24, 0x25, 0x25, 0x25, 0x25, 0x26, 0x26,
1445 0x26, 0x26, 0x27, 0x27, 0x27, 0x28, 0x28, 0x28,
1446 0x28, 0x29, 0x29, 0x29, 0x29, 0x2A, 0x2A, 0x2A,
1447 0x2A, 0x2B, 0x2B, 0x2B, 0x2B, 0x2B, 0x2C, 0x2C,
1448 0x2C, 0x2C, 0x2D, 0x2D, 0x2D, 0x2D, 0x2E, 0x2E,
1449 0x2E, 0x2E, 0x2E, 0x2F, 0x2F, 0x2F, 0x2F, 0x30,
1450 0x30, 0x30, 0x30, 0x30, 0x31, 0x31, 0x31, 0x31,
1451 0x31, 0x32, 0x32, 0x32, 0x32, 0x32, 0x33, 0x33,
1452 0x33, 0x33, 0x33, 0x34, 0x34, 0x34, 0x34, 0x34,
1453 0x35, 0x35, 0x35, 0x35, 0x35, 0x36, 0x36, 0x36,
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1500 0x64, 0x64, 0x64, 0x64, 0x64, 0x64, 0x64, 0x64,
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1544 0x7F, 0x7F, 0x7F, 0x7F, 0x7F, 0x80, 0x80, 0x80,
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1608 0x9D, 0x9D, 0x9D, 0x9D, 0x9D, 0x9D, 0x9D, 0x9E,
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1611 0x9E, 0x9E, 0x9F, 0x9F, 0x9F, 0x9F, 0x9F, 0x9F,
1612 0x9F, 0x9F, 0x9F, 0x9F, 0x9F, 0x9F, 0x9F, 0x9F,
1613 0x9F, 0x9F, 0x9F, 0x9F, 0x9F, 0x9F, 0xA0, 0xA0,
1614 0xA0, 0xA0, 0xA0, 0xA0, 0xA0, 0xA0, 0xA0, 0xA0,
1615 0xA0, 0xA0, 0xA0, 0xA0, 0xA0, 0xA0, 0xA0, 0xA0,
1616 0xA0, 0xA0, 0xA1, 0xA1, 0xA1, 0xA1, 0xA1, 0xA1,
1617 0xA1, 0xA1, 0xA1, 0xA1, 0xA1, 0xA1, 0xA1, 0xA1,
1618 0xA1, 0xA1, 0xA1, 0xA1, 0xA1, 0xA1, 0xA2, 0xA2,
1619 0xA2, 0xA2, 0xA2, 0xA2, 0xA2, 0xA2, 0xA2, 0xA2,
1620 0xA2, 0xA2, 0xA2, 0xA2, 0xA2, 0xA2, 0xA2, 0xA2,
1621 0xA2, 0xA2, 0xA3, 0xA3, 0xA3, 0xA3, 0xA3, 0xA3,
1622 0xA3, 0xA3, 0xA3, 0xA3, 0xA3, 0xA3, 0xA3, 0xA3,
1623 0xA3, 0xA3, 0xA3, 0xA3, 0xA3, 0xA3, 0xA4, 0xA4,
1624 0xA4, 0xA4, 0xA4, 0xA4, 0xA4, 0xA4, 0xA4, 0xA4,
1625 0xA4, 0xA4, 0xA4, 0xA4, 0xA4, 0xA4, 0xA4, 0xA4,
1626 0xA4, 0xA4, 0xA4, 0xA5, 0xA5, 0xA5, 0xA5, 0xA5,
1627 0xA5, 0xA5, 0xA5, 0xA5, 0xA5, 0xA5, 0xA5, 0xA5,
1628 0xA5, 0xA5, 0xA5, 0xA5, 0xA5, 0xA5, 0xA5, 0xA5,
1629 0xA6, 0xA6, 0xA6, 0xA6, 0xA6, 0xA6, 0xA6, 0xA6,
1630 0xA6, 0xA6, 0xA6, 0xA6, 0xA6, 0xA6, 0xA6, 0xA6,
1631 0xA6, 0xA6, 0xA6, 0xA6, 0xA7, 0xA7, 0xA7, 0xA7,
1632 0xA7, 0xA7, 0xA7, 0xA7, 0xA7, 0xA7, 0xA7, 0xA7,
1633 0xA7, 0xA7, 0xA7, 0xA7, 0xA7, 0xA7, 0xA7, 0xA7,
1634 0xA7, 0xA8, 0xA8, 0xA8, 0xA8, 0xA8, 0xA8, 0xA8,
1635 0xA8, 0xA8, 0xA8, 0xA8, 0xA8, 0xA8, 0xA8, 0xA8,
1636 0xA8, 0xA8, 0xA8, 0xA8, 0xA8, 0xA8, 0xA8, 0xA9,
1637 0xA9, 0xA9, 0xA9, 0xA9, 0xA9, 0xA9, 0xA9, 0xA9,
1638 0xA9, 0xA9, 0xA9, 0xA9, 0xA9, 0xA9, 0xA9, 0xA9,
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1640 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA, 0xAA,
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1655 0xAF, 0xAF, 0xAF, 0xAF, 0xAF, 0xAF, 0xAF, 0xB0,
1656 0xB0, 0xB0, 0xB0, 0xB0, 0xB0, 0xB0, 0xB0, 0xB0,
1657 0xB0, 0xB0, 0xB0, 0xB0, 0xB0, 0xB0, 0xB0, 0xB0,
1658 0xB0, 0xB0, 0xB0, 0xB0, 0xB0, 0xB0, 0xB1, 0xB1,
1659 0xB1, 0xB1, 0xB1, 0xB1, 0xB1, 0xB1, 0xB1, 0xB1,
1660 0xB1, 0xB1, 0xB1, 0xB1, 0xB1, 0xB1, 0xB1, 0xB1,
1661 0xB1, 0xB1, 0xB1, 0xB1, 0xB2, 0xB2, 0xB2, 0xB2,
1662 0xB2, 0xB2, 0xB2, 0xB2, 0xB2, 0xB2, 0xB2, 0xB2,
1663 0xB2, 0xB2, 0xB2, 0xB2, 0xB2, 0xB2, 0xB2, 0xB2,
1664 0xB2, 0xB2, 0xB2, 0xB3, 0xB3, 0xB3, 0xB3, 0xB3,
1665 0xB3, 0xB3, 0xB3, 0xB3, 0xB3, 0xB3, 0xB3, 0xB3,
1666 0xB3, 0xB3, 0xB3, 0xB3, 0xB3, 0xB3, 0xB3, 0xB3,
1667 0xB3, 0xB3, 0xB4, 0xB4, 0xB4, 0xB4, 0xB4, 0xB4,
1668 0xB4, 0xB4, 0xB4, 0xB4, 0xB4, 0xB4, 0xB4, 0xB4,
1669 0xB4, 0xB4, 0xB4, 0xB4, 0xB4, 0xB4, 0xB4, 0xB4,
1670 0xB4, 0xB5, 0xB5, 0xB5, 0xB5, 0xB5, 0xB5, 0xB5,
1671 0xB5, 0xB5, 0xB5, 0xB5, 0xB5, 0xB5, 0xB5, 0xB5,
1672 0xB5, 0xB5, 0xB5, 0xB5, 0xB5, 0xB5, 0xB5, 0xB5,
1673 0xB6, 0xB6, 0xB6, 0xB6, 0xB6, 0xB6, 0xB6, 0xB6,
1674 0xB6, 0xB6, 0xB6, 0xB6, 0xB6, 0xB6, 0xB6, 0xB6,
1675 0xB6, 0xB6, 0xB6, 0xB6, 0xB6, 0xB6, 0xB6, 0xB6,
1676 0xB7, 0xB7, 0xB7, 0xB7, 0xB7, 0xB7, 0xB7, 0xB7,
1677 0xB7, 0xB7, 0xB7, 0xB7, 0xB7, 0xB7, 0xB7, 0xB7,
1678 0xB7, 0xB7, 0xB7, 0xB7, 0xB7, 0xB7, 0xB7, 0xB8,
1679 0xB8, 0xB8, 0xB8, 0xB8, 0xB8, 0xB8, 0xB8, 0xB8,
1680 0xB8, 0xB8, 0xB8, 0xB8, 0xB8, 0xB8, 0xB8, 0xB8,
1681 0xB8, 0xB8, 0xB8, 0xB8, 0xB8, 0xB8, 0xB8, 0xB9,
1682 0xB9, 0xB9, 0xB9, 0xB9, 0xB9, 0xB9, 0xB9, 0xB9,
1683 0xB9, 0xB9, 0xB9, 0xB9, 0xB9, 0xB9, 0xB9, 0xB9,
1684 0xB9, 0xB9, 0xB9, 0xB9, 0xB9, 0xB9, 0xB9, 0xBA,
1685 0xBA, 0xBA, 0xBA, 0xBA, 0xBA, 0xBA, 0xBA, 0xBA,
1686 0xBA, 0xBA, 0xBA, 0xBA, 0xBA, 0xBA, 0xBA, 0xBA,
1687 0xBA, 0xBA, 0xBA, 0xBA, 0xBA, 0xBA, 0xBA, 0xBB,
1688 0xBB, 0xBB, 0xBB, 0xBB, 0xBB, 0xBB, 0xBB, 0xBB,
1689 0xBB, 0xBB, 0xBB, 0xBB, 0xBB, 0xBB, 0xBB, 0xBB,
1690 0xBB, 0xBB, 0xBB, 0xBB, 0xBB, 0xBB, 0xBB, 0xBB,
1691 0xBC, 0xBC, 0xBC, 0xBC, 0xBC, 0xBC, 0xBC, 0xBC,
1692 0xBC, 0xBC, 0xBC, 0xBC, 0xBC, 0xBC, 0xBC, 0xBC,
1693 0xBC, 0xBC, 0xBC, 0xBC, 0xBC, 0xBC, 0xBC, 0xBC,
1694 0xBD, 0xBD, 0xBD, 0xBD, 0xBD, 0xBD, 0xBD, 0xBD,
1695 0xBD, 0xBD, 0xBD, 0xBD, 0xBD, 0xBD, 0xBD, 0xBD,
1696 0xBD, 0xBD, 0xBD, 0xBD, 0xBD, 0xBD, 0xBD, 0xBD,
1697 0xBD, 0xBE, 0xBE, 0xBE, 0xBE, 0xBE, 0xBE, 0xBE,
1698 0xBE, 0xBE, 0xBE, 0xBE, 0xBE, 0xBE, 0xBE, 0xBE,
1699 0xBE, 0xBE, 0xBE, 0xBE, 0xBE, 0xBE, 0xBE, 0xBE,
1700 0xBE, 0xBE, 0xBF, 0xBF, 0xBF, 0xBF, 0xBF, 0xBF,
1701 0xBF, 0xBF, 0xBF, 0xBF, 0xBF, 0xBF, 0xBF, 0xBF,
1702 0xBF, 0xBF, 0xBF, 0xBF, 0xBF, 0xBF, 0xBF, 0xBF,
1703 0xBF, 0xBF, 0xC0, 0xC0, 0xC0, 0xC0, 0xC0, 0xC0,
1704 0xC0, 0xC0, 0xC0, 0xC0, 0xC0, 0xC0, 0xC0, 0xC0,
1705 0xC0, 0xC0, 0xC0, 0xC0, 0xC0, 0xC0, 0xC0, 0xC0,
1706 0xC0, 0xC0, 0xC0, 0xC0, 0xC1, 0xC1, 0xC1, 0xC1,
1707 0xC1, 0xC1, 0xC1, 0xC1, 0xC1, 0xC1, 0xC1, 0xC1,
1708 0xC1, 0xC1, 0xC1, 0xC1, 0xC1, 0xC1, 0xC1, 0xC1,
1709 0xC1, 0xC1, 0xC1, 0xC1, 0xC1, 0xC2, 0xC2, 0xC2,
1710 0xC2, 0xC2, 0xC2, 0xC2, 0xC2, 0xC2, 0xC2, 0xC2,
1711 0xC2, 0xC2, 0xC2, 0xC2, 0xC2, 0xC2, 0xC2, 0xC2,
1712 0xC2, 0xC2, 0xC2, 0xC2, 0xC2, 0xC2, 0xC3, 0xC3,
1713 0xC3, 0xC3, 0xC3, 0xC3, 0xC3, 0xC3, 0xC3, 0xC3,
1714 0xC3, 0xC3, 0xC3, 0xC3, 0xC3, 0xC3, 0xC3, 0xC3,
1715 0xC3, 0xC3, 0xC3, 0xC3, 0xC3, 0xC3, 0xC3, 0xC3,
1716 0xC4, 0xC4, 0xC4, 0xC4, 0xC4, 0xC4, 0xC4, 0xC4,
1717 0xC4, 0xC4, 0xC4, 0xC4, 0xC4, 0xC4, 0xC4, 0xC4,
1718 0xC4, 0xC4, 0xC4, 0xC4, 0xC4, 0xC4, 0xC4, 0xC4,
1719 0xC4, 0xC4, 0xC5, 0xC5, 0xC5, 0xC5, 0xC5, 0xC5,
1720 0xC5, 0xC5, 0xC5, 0xC5, 0xC5, 0xC5, 0xC5, 0xC5,
1721 0xC5, 0xC5, 0xC5, 0xC5, 0xC5, 0xC5, 0xC5, 0xC5,
1722 0xC5, 0xC5, 0xC5, 0xC5, 0xC6, 0xC6, 0xC6, 0xC6,
1723 0xC6, 0xC6, 0xC6, 0xC6, 0xC6, 0xC6, 0xC6, 0xC6,
1724 0xC6, 0xC6, 0xC6, 0xC6, 0xC6, 0xC6, 0xC6, 0xC6,
1725 0xC6, 0xC6, 0xC6, 0xC6, 0xC6, 0xC6, 0xC7, 0xC7,
1726 0xC7, 0xC7, 0xC7, 0xC7, 0xC7, 0xC7, 0xC7, 0xC7,
1727 0xC7, 0xC7, 0xC7, 0xC7, 0xC7, 0xC7, 0xC7, 0xC7,
1728 0xC7, 0xC7, 0xC7, 0xC7, 0xC7, 0xC7, 0xC7, 0xC7,
1729 0xC8, 0xC8, 0xC8, 0xC8, 0xC8, 0xC8, 0xC8, 0xC8,
1730 0xC8, 0xC8, 0xC8, 0xC8, 0xC8, 0xC8, 0xC8, 0xC8,
1731 0xC8, 0xC8, 0xC8, 0xC8, 0xC8, 0xC8, 0xC8, 0xC8,
1732 0xC8, 0xC8, 0xC8, 0xC9, 0xC9, 0xC9, 0xC9, 0xC9,
1733 0xC9, 0xC9, 0xC9, 0xC9, 0xC9, 0xC9, 0xC9, 0xC9,
1734 0xC9, 0xC9, 0xC9, 0xC9, 0xC9, 0xC9, 0xC9, 0xC9,
1735 0xC9, 0xC9, 0xC9, 0xC9, 0xC9, 0xC9, 0xCA, 0xCA,
1736 0xCA, 0xCA, 0xCA, 0xCA, 0xCA, 0xCA, 0xCA, 0xCA,
1737 0xCA, 0xCA, 0xCA, 0xCA, 0xCA, 0xCA, 0xCA, 0xCA,
1738 0xCA, 0xCA, 0xCA, 0xCA, 0xCA, 0xCA, 0xCA, 0xCA,
1739 0xCA, 0xCB, 0xCB, 0xCB, 0xCB, 0xCB, 0xCB, 0xCB,
1740 0xCB, 0xCB, 0xCB, 0xCB, 0xCB, 0xCB, 0xCB, 0xCB,
1741 0xCB, 0xCB, 0xCB, 0xCB, 0xCB, 0xCB, 0xCB, 0xCB,
1742 0xCB, 0xCB, 0xCB, 0xCB, 0xCC, 0xCC, 0xCC, 0xCC,
1743 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
1744 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC,
1745 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCC, 0xCD,
1746 0xCD, 0xCD, 0xCD, 0xCD, 0xCD, 0xCD, 0xCD, 0xCD,
1747 0xCD, 0xCD, 0xCD, 0xCD, 0xCD, 0xCD, 0xCD, 0xCD,
1748 0xCD, 0xCD, 0xCD, 0xCD, 0xCD, 0xCD, 0xCD, 0xCD,
1749 0xCD, 0xCD, 0xCE, 0xCE, 0xCE, 0xCE, 0xCE, 0xCE,
1750 0xCE, 0xCE, 0xCE, 0xCE, 0xCE, 0xCE, 0xCE, 0xCE,
1751 0xCE, 0xCE, 0xCE, 0xCE, 0xCE, 0xCE, 0xCE, 0xCE,
1752 0xCE, 0xCE, 0xCE, 0xCE, 0xCE, 0xCE, 0xCF, 0xCF,
1753 0xCF, 0xCF, 0xCF, 0xCF, 0xCF, 0xCF, 0xCF, 0xCF,
1754 0xCF, 0xCF, 0xCF, 0xCF, 0xCF, 0xCF, 0xCF, 0xCF,
1755 0xCF, 0xCF, 0xCF, 0xCF, 0xCF, 0xCF, 0xCF, 0xCF,
1756 0xCF, 0xCF, 0xD0, 0xD0, 0xD0, 0xD0, 0xD0, 0xD0,
1757 0xD0, 0xD0, 0xD0, 0xD0, 0xD0, 0xD0, 0xD0, 0xD0,
1758 0xD0, 0xD0, 0xD0, 0xD0, 0xD0, 0xD0, 0xD0, 0xD0,
1759 0xD0, 0xD0, 0xD0, 0xD0, 0xD0, 0xD1, 0xD1, 0xD1,
1760 0xD1, 0xD1, 0xD1, 0xD1, 0xD1, 0xD1, 0xD1, 0xD1,
1761 0xD1, 0xD1, 0xD1, 0xD1, 0xD1, 0xD1, 0xD1, 0xD1,
1762 0xD1, 0xD1, 0xD1, 0xD1, 0xD1, 0xD1, 0xD1, 0xD1,
1763 0xD1, 0xD1, 0xD2, 0xD2, 0xD2, 0xD2, 0xD2, 0xD2,
1764 0xD2, 0xD2, 0xD2, 0xD2, 0xD2, 0xD2, 0xD2, 0xD2,
1765 0xD2, 0xD2, 0xD2, 0xD2, 0xD2, 0xD2, 0xD2, 0xD2,
1766 0xD2, 0xD2, 0xD2, 0xD2, 0xD2, 0xD2, 0xD3, 0xD3,
1767 0xD3, 0xD3, 0xD3, 0xD3, 0xD3, 0xD3, 0xD3, 0xD3,
1768 0xD3, 0xD3, 0xD3, 0xD3, 0xD3, 0xD3, 0xD3, 0xD3,
1769 0xD3, 0xD3, 0xD3, 0xD3, 0xD3, 0xD3, 0xD3, 0xD3,
1770 0xD3, 0xD3, 0xD4, 0xD4, 0xD4, 0xD4, 0xD4, 0xD4,
1771 0xD4, 0xD4, 0xD4, 0xD4, 0xD4, 0xD4, 0xD4, 0xD4,
1772 0xD4, 0xD4, 0xD4, 0xD4, 0xD4, 0xD4, 0xD4, 0xD4,
1773 0xD4, 0xD4, 0xD4, 0xD4, 0xD4, 0xD4, 0xD4, 0xD5,
1774 0xD5, 0xD5, 0xD5, 0xD5, 0xD5, 0xD5, 0xD5, 0xD5,
1775 0xD5, 0xD5, 0xD5, 0xD5, 0xD5, 0xD5, 0xD5, 0xD5,
1776 0xD5, 0xD5, 0xD5, 0xD5, 0xD5, 0xD5, 0xD5, 0xD5,
1777 0xD5, 0xD5, 0xD5, 0xD5, 0xD6, 0xD6, 0xD6, 0xD6,
1778 0xD6, 0xD6, 0xD6, 0xD6, 0xD6, 0xD6, 0xD6, 0xD6,
1779 0xD6, 0xD6, 0xD6, 0xD6, 0xD6, 0xD6, 0xD6, 0xD6,
1780 0xD6, 0xD6, 0xD6, 0xD6, 0xD6, 0xD6, 0xD6, 0xD6,
1781 0xD6, 0xD7, 0xD7, 0xD7, 0xD7, 0xD7, 0xD7, 0xD7,
1782 0xD7, 0xD7, 0xD7, 0xD7, 0xD7, 0xD7, 0xD7, 0xD7,
1783 0xD7, 0xD7, 0xD7, 0xD7, 0xD7, 0xD7, 0xD7, 0xD7,
1784 0xD7, 0xD7, 0xD7, 0xD7, 0xD7, 0xD7, 0xD8, 0xD8,
1785 0xD8, 0xD8, 0xD8, 0xD8, 0xD8, 0xD8, 0xD8, 0xD8,
1786 0xD8, 0xD8, 0xD8, 0xD8, 0xD8, 0xD8, 0xD8, 0xD8,
1787 0xD8, 0xD8, 0xD8, 0xD8, 0xD8, 0xD8, 0xD8, 0xD8,
1788 0xD8, 0xD8, 0xD8, 0xD9, 0xD9, 0xD9, 0xD9, 0xD9,
1789 0xD9, 0xD9, 0xD9, 0xD9, 0xD9, 0xD9, 0xD9, 0xD9,
1790 0xD9, 0xD9, 0xD9, 0xD9, 0xD9, 0xD9, 0xD9, 0xD9,
1791 0xD9, 0xD9, 0xD9, 0xD9, 0xD9, 0xD9, 0xD9, 0xD9,
1792 0xD9, 0xDA, 0xDA, 0xDA, 0xDA, 0xDA, 0xDA, 0xDA,
1793 0xDA, 0xDA, 0xDA, 0xDA, 0xDA, 0xDA, 0xDA, 0xDA,
1794 0xDA, 0xDA, 0xDA, 0xDA, 0xDA, 0xDA, 0xDA, 0xDA,
1795 0xDA, 0xDA, 0xDA, 0xDA, 0xDA, 0xDA, 0xDB, 0xDB,
1796 0xDB, 0xDB, 0xDB, 0xDB, 0xDB, 0xDB, 0xDB, 0xDB,
1797 0xDB, 0xDB, 0xDB, 0xDB, 0xDB, 0xDB, 0xDB, 0xDB,
1798 0xDB, 0xDB, 0xDB, 0xDB, 0xDB, 0xDB, 0xDB, 0xDB,
1799 0xDB, 0xDB, 0xDB, 0xDB, 0xDC, 0xDC, 0xDC, 0xDC,
1800 0xDC, 0xDC, 0xDC, 0xDC, 0xDC, 0xDC, 0xDC, 0xDC,
1801 0xDC, 0xDC, 0xDC, 0xDC, 0xDC, 0xDC, 0xDC, 0xDC,
1802 0xDC, 0xDC, 0xDC, 0xDC, 0xDC, 0xDC, 0xDC, 0xDC,
1803 0xDC, 0xDC, 0xDD, 0xDD, 0xDD, 0xDD, 0xDD, 0xDD,
1804 0xDD, 0xDD, 0xDD, 0xDD, 0xDD, 0xDD, 0xDD, 0xDD,
1805 0xDD, 0xDD, 0xDD, 0xDD, 0xDD, 0xDD, 0xDD, 0xDD,
1806 0xDD, 0xDD, 0xDD, 0xDD, 0xDD, 0xDD, 0xDD, 0xDD,
1807 0xDD, 0xDE, 0xDE, 0xDE, 0xDE, 0xDE, 0xDE, 0xDE,
1808 0xDE, 0xDE, 0xDE, 0xDE, 0xDE, 0xDE, 0xDE, 0xDE,
1809 0xDE, 0xDE, 0xDE, 0xDE, 0xDE, 0xDE, 0xDE, 0xDE,
1810 0xDE, 0xDE, 0xDE, 0xDE, 0xDE, 0xDE, 0xDE, 0xDF,
1811 0xDF, 0xDF, 0xDF, 0xDF, 0xDF, 0xDF, 0xDF, 0xDF,
1812 0xDF, 0xDF, 0xDF, 0xDF, 0xDF, 0xDF, 0xDF, 0xDF,
1813 0xDF, 0xDF, 0xDF, 0xDF, 0xDF, 0xDF, 0xDF, 0xDF,
1814 0xDF, 0xDF, 0xDF, 0xDF, 0xDF, 0xDF, 0xE0, 0xE0,
1815 0xE0, 0xE0, 0xE0, 0xE0, 0xE0, 0xE0, 0xE0, 0xE0,
1816 0xE0, 0xE0, 0xE0, 0xE0, 0xE0, 0xE0, 0xE0, 0xE0,
1817 0xE0, 0xE0, 0xE0, 0xE0, 0xE0, 0xE0, 0xE0, 0xE0,
1818 0xE0, 0xE0, 0xE0, 0xE0, 0xE1, 0xE1, 0xE1, 0xE1,
1819 0xE1, 0xE1, 0xE1, 0xE1, 0xE1, 0xE1, 0xE1, 0xE1,
1820 0xE1, 0xE1, 0xE1, 0xE1, 0xE1, 0xE1, 0xE1, 0xE1,
1821 0xE1, 0xE1, 0xE1, 0xE1, 0xE1, 0xE1, 0xE1, 0xE1,
1822 0xE1, 0xE1, 0xE1, 0xE2, 0xE2, 0xE2, 0xE2, 0xE2,
1823 0xE2, 0xE2, 0xE2, 0xE2, 0xE2, 0xE2, 0xE2, 0xE2,
1824 0xE2, 0xE2, 0xE2, 0xE2, 0xE2, 0xE2, 0xE2, 0xE2,
1825 0xE2, 0xE2, 0xE2, 0xE2, 0xE2, 0xE2, 0xE2, 0xE2,
1826 0xE2, 0xE2, 0xE3, 0xE3, 0xE3, 0xE3, 0xE3, 0xE3,
1827 0xE3, 0xE3, 0xE3, 0xE3, 0xE3, 0xE3, 0xE3, 0xE3,
1828 0xE3, 0xE3, 0xE3, 0xE3, 0xE3, 0xE3, 0xE3, 0xE3,
1829 0xE3, 0xE3, 0xE3, 0xE3, 0xE3, 0xE3, 0xE3, 0xE3,
1830 0xE3, 0xE3, 0xE4, 0xE4, 0xE4, 0xE4, 0xE4, 0xE4,
1831 0xE4, 0xE4, 0xE4, 0xE4, 0xE4, 0xE4, 0xE4, 0xE4,
1832 0xE4, 0xE4, 0xE4, 0xE4, 0xE4, 0xE4, 0xE4, 0xE4,
1833 0xE4, 0xE4, 0xE4, 0xE4, 0xE4, 0xE4, 0xE4, 0xE4,
1834 0xE4, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5,
1835 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5,
1836 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5,
1837 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5, 0xE5,
1838 0xE5, 0xE6, 0xE6, 0xE6, 0xE6, 0xE6, 0xE6, 0xE6,
1839 0xE6, 0xE6, 0xE6, 0xE6, 0xE6, 0xE6, 0xE6, 0xE6,
1840 0xE6, 0xE6, 0xE6, 0xE6, 0xE6, 0xE6, 0xE6, 0xE6,
1841 0xE6, 0xE6, 0xE6, 0xE6, 0xE6, 0xE6, 0xE6, 0xE6,
1842 0xE6, 0xE7, 0xE7, 0xE7, 0xE7, 0xE7, 0xE7, 0xE7,
1843 0xE7, 0xE7, 0xE7, 0xE7, 0xE7, 0xE7, 0xE7, 0xE7,
1844 0xE7, 0xE7, 0xE7, 0xE7, 0xE7, 0xE7, 0xE7, 0xE7,
1845 0xE7, 0xE7, 0xE7, 0xE7, 0xE7, 0xE7, 0xE7, 0xE7,
1846 0xE7, 0xE8, 0xE8, 0xE8, 0xE8, 0xE8, 0xE8, 0xE8,
1847 0xE8, 0xE8, 0xE8, 0xE8, 0xE8, 0xE8, 0xE8, 0xE8,
1848 0xE8, 0xE8, 0xE8, 0xE8, 0xE8, 0xE8, 0xE8, 0xE8,
1849 0xE8, 0xE8, 0xE8, 0xE8, 0xE8, 0xE8, 0xE8, 0xE8,
1850 0xE8, 0xE9, 0xE9, 0xE9, 0xE9, 0xE9, 0xE9, 0xE9,
1851 0xE9, 0xE9, 0xE9, 0xE9, 0xE9, 0xE9, 0xE9, 0xE9,
1852 0xE9, 0xE9, 0xE9, 0xE9, 0xE9, 0xE9, 0xE9, 0xE9,
1853 0xE9, 0xE9, 0xE9, 0xE9, 0xE9, 0xE9, 0xE9, 0xE9,
1854 0xE9, 0xE9, 0xEA, 0xEA, 0xEA, 0xEA, 0xEA, 0xEA,
1855 0xEA, 0xEA, 0xEA, 0xEA, 0xEA, 0xEA, 0xEA, 0xEA,
1856 0xEA, 0xEA, 0xEA, 0xEA, 0xEA, 0xEA, 0xEA, 0xEA,
1857 0xEA, 0xEA, 0xEA, 0xEA, 0xEA, 0xEA, 0xEA, 0xEA,
1858 0xEA, 0xEA, 0xEB, 0xEB, 0xEB, 0xEB, 0xEB, 0xEB,
1859 0xEB, 0xEB, 0xEB, 0xEB, 0xEB, 0xEB, 0xEB, 0xEB,
1860 0xEB, 0xEB, 0xEB, 0xEB, 0xEB, 0xEB, 0xEB, 0xEB,
1861 0xEB, 0xEB, 0xEB, 0xEB, 0xEB, 0xEB, 0xEB, 0xEB,
1862 0xEB, 0xEB, 0xEB, 0xEC, 0xEC, 0xEC, 0xEC, 0xEC,
1863 0xEC, 0xEC, 0xEC, 0xEC, 0xEC, 0xEC, 0xEC, 0xEC,
1864 0xEC, 0xEC, 0xEC, 0xEC, 0xEC, 0xEC, 0xEC, 0xEC,
1865 0xEC, 0xEC, 0xEC, 0xEC, 0xEC, 0xEC, 0xEC, 0xEC,
1866 0xEC, 0xEC, 0xEC, 0xEC, 0xED, 0xED, 0xED, 0xED,
1867 0xED, 0xED, 0xED, 0xED, 0xED, 0xED, 0xED, 0xED,
1868 0xED, 0xED, 0xED, 0xED, 0xED, 0xED, 0xED, 0xED,
1869 0xED, 0xED, 0xED, 0xED, 0xED, 0xED, 0xED, 0xED,
1870 0xED, 0xED, 0xED, 0xED, 0xED, 0xEE, 0xEE, 0xEE,
1871 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE,
1872 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE,
1873 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE,
1874 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEE, 0xEF, 0xEF,
1875 0xEF, 0xEF, 0xEF, 0xEF, 0xEF, 0xEF, 0xEF, 0xEF,
1876 0xEF, 0xEF, 0xEF, 0xEF, 0xEF, 0xEF, 0xEF, 0xEF,
1877 0xEF, 0xEF, 0xEF, 0xEF, 0xEF, 0xEF, 0xEF, 0xEF,
1878 0xEF, 0xEF, 0xEF, 0xEF, 0xEF, 0xEF, 0xEF, 0xEF,
1879 0xF0, 0xF0, 0xF0, 0xF0, 0xF0, 0xF0, 0xF0, 0xF0,
1880 0xF0, 0xF0, 0xF0, 0xF0, 0xF0, 0xF0, 0xF0, 0xF0,
1881 0xF0, 0xF0, 0xF0, 0xF0, 0xF0, 0xF0, 0xF0, 0xF0,
1882 0xF0, 0xF0, 0xF0, 0xF0, 0xF0, 0xF0, 0xF0, 0xF0,
1883 0xF0, 0xF0, 0xF1, 0xF1, 0xF1, 0xF1, 0xF1, 0xF1,
1884 0xF1, 0xF1, 0xF1, 0xF1, 0xF1, 0xF1, 0xF1, 0xF1,
1885 0xF1, 0xF1, 0xF1, 0xF1, 0xF1, 0xF1, 0xF1, 0xF1,
1886 0xF1, 0xF1, 0xF1, 0xF1, 0xF1, 0xF1, 0xF1, 0xF1,
1887 0xF1, 0xF1, 0xF1, 0xF1, 0xF2, 0xF2, 0xF2, 0xF2,
1888 0xF2, 0xF2, 0xF2, 0xF2, 0xF2, 0xF2, 0xF2, 0xF2,
1889 0xF2, 0xF2, 0xF2, 0xF2, 0xF2, 0xF2, 0xF2, 0xF2,
1890 0xF2, 0xF2, 0xF2, 0xF2, 0xF2, 0xF2, 0xF2, 0xF2,
1891 0xF2, 0xF2, 0xF2, 0xF2, 0xF2, 0xF2, 0xF3, 0xF3,
1892 0xF3, 0xF3, 0xF3, 0xF3, 0xF3, 0xF3, 0xF3, 0xF3,
1893 0xF3, 0xF3, 0xF3, 0xF3, 0xF3, 0xF3, 0xF3, 0xF3,
1894 0xF3, 0xF3, 0xF3, 0xF3, 0xF3, 0xF3, 0xF3, 0xF3,
1895 0xF3, 0xF3, 0xF3, 0xF3, 0xF3, 0xF3, 0xF3, 0xF3,
1896 0xF4, 0xF4, 0xF4, 0xF4, 0xF4, 0xF4, 0xF4, 0xF4,
1897 0xF4, 0xF4, 0xF4, 0xF4, 0xF4, 0xF4, 0xF4, 0xF4,
1898 0xF4, 0xF4, 0xF4, 0xF4, 0xF4, 0xF4, 0xF4, 0xF4,
1899 0xF4, 0xF4, 0xF4, 0xF4, 0xF4, 0xF4, 0xF4, 0xF4,
1900 0xF4, 0xF4, 0xF5, 0xF5, 0xF5, 0xF5, 0xF5, 0xF5,
1901 0xF5, 0xF5, 0xF5, 0xF5, 0xF5, 0xF5, 0xF5, 0xF5,
1902 0xF5, 0xF5, 0xF5, 0xF5, 0xF5, 0xF5, 0xF5, 0xF5,
1903 0xF5, 0xF5, 0xF5, 0xF5, 0xF5, 0xF5, 0xF5, 0xF5,
1904 0xF5, 0xF5, 0xF5, 0xF5, 0xF5, 0xF6, 0xF6, 0xF6,
1905 0xF6, 0xF6, 0xF6, 0xF6, 0xF6, 0xF6, 0xF6, 0xF6,
1906 0xF6, 0xF6, 0xF6, 0xF6, 0xF6, 0xF6, 0xF6, 0xF6,
1907 0xF6, 0xF6, 0xF6, 0xF6, 0xF6, 0xF6, 0xF6, 0xF6,
1908 0xF6, 0xF6, 0xF6, 0xF6, 0xF6, 0xF6, 0xF6, 0xF6,
1909 0xF7, 0xF7, 0xF7, 0xF7, 0xF7, 0xF7, 0xF7, 0xF7,
1910 0xF7, 0xF7, 0xF7, 0xF7, 0xF7, 0xF7, 0xF7, 0xF7,
1911 0xF7, 0xF7, 0xF7, 0xF7, 0xF7, 0xF7, 0xF7, 0xF7,
1912 0xF7, 0xF7, 0xF7, 0xF7, 0xF7, 0xF7, 0xF7, 0xF7,
1913 0xF7, 0xF7, 0xF7, 0xF8, 0xF8, 0xF8, 0xF8, 0xF8,
1914 0xF8, 0xF8, 0xF8, 0xF8, 0xF8, 0xF8, 0xF8, 0xF8,
1915 0xF8, 0xF8, 0xF8, 0xF8, 0xF8, 0xF8, 0xF8, 0xF8,
1916 0xF8, 0xF8, 0xF8, 0xF8, 0xF8, 0xF8, 0xF8, 0xF8,
1917 0xF8, 0xF8, 0xF8, 0xF8, 0xF8, 0xF8, 0xF9, 0xF9,
1918 0xF9, 0xF9, 0xF9, 0xF9, 0xF9, 0xF9, 0xF9, 0xF9,
1919 0xF9, 0xF9, 0xF9, 0xF9, 0xF9, 0xF9, 0xF9, 0xF9,
1920 0xF9, 0xF9, 0xF9, 0xF9, 0xF9, 0xF9, 0xF9, 0xF9,
1921 0xF9, 0xF9, 0xF9, 0xF9, 0xF9, 0xF9, 0xF9, 0xF9,
1922 0xF9, 0xFA, 0xFA, 0xFA, 0xFA, 0xFA, 0xFA, 0xFA,
1923 0xFA, 0xFA, 0xFA, 0xFA, 0xFA, 0xFA, 0xFA, 0xFA,
1924 0xFA, 0xFA, 0xFA, 0xFA, 0xFA, 0xFA, 0xFA, 0xFA,
1925 0xFA, 0xFA, 0xFA, 0xFA, 0xFA, 0xFA, 0xFA, 0xFA,
1926 0xFA, 0xFA, 0xFA, 0xFA, 0xFA, 0xFB, 0xFB, 0xFB,
1927 0xFB, 0xFB, 0xFB, 0xFB, 0xFB, 0xFB, 0xFB, 0xFB,
1928 0xFB, 0xFB, 0xFB, 0xFB, 0xFB, 0xFB, 0xFB, 0xFB,
1929 0xFB, 0xFB, 0xFB, 0xFB, 0xFB, 0xFB, 0xFB, 0xFB,
1930 0xFB, 0xFB, 0xFB, 0xFB, 0xFB, 0xFB, 0xFB, 0xFB,
1931 0xFB, 0xFC, 0xFC, 0xFC, 0xFC, 0xFC, 0xFC, 0xFC,
1932 0xFC, 0xFC, 0xFC, 0xFC, 0xFC, 0xFC, 0xFC, 0xFC,
1933 0xFC, 0xFC, 0xFC, 0xFC, 0xFC, 0xFC, 0xFC, 0xFC,
1934 0xFC, 0xFC, 0xFC, 0xFC, 0xFC, 0xFC, 0xFC, 0xFC,
1935 0xFC, 0xFC, 0xFC, 0xFC, 0xFC, 0xFD, 0xFD, 0xFD,
1936 0xFD, 0xFD, 0xFD, 0xFD, 0xFD, 0xFD, 0xFD, 0xFD,
1937 0xFD, 0xFD, 0xFD, 0xFD, 0xFD, 0xFD, 0xFD, 0xFD,
1938 0xFD, 0xFD, 0xFD, 0xFD, 0xFD, 0xFD, 0xFD, 0xFD,
1939 0xFD, 0xFD, 0xFD, 0xFD, 0xFD, 0xFD, 0xFD, 0xFD,
1940 0xFD, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE,
1941 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE,
1942 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE,
1943 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE,
1944 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFF, 0xFF, 0xFF,
1945 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
1946 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
1947};
1948
1949void mdp4_mixer_gc_lut_setup(int mixer_num)
1950{
1951 unsigned char *base;
1952 uint32 data;
1953 char val;
1954 int i, off;
1955
1956 if (mixer_num) /* mixer number, /dev/fb0, /dev/fb1 */
1957 base = MDP_BASE + MDP4_OVERLAYPROC1_BASE;/* 0x18000 */
1958 else
1959 base = MDP_BASE + MDP4_OVERLAYPROC0_BASE;/* 0x10000 */
1960
1961 base += 0x4000; /* GC_LUT offset */
1962
1963 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
1964 off = 0;
1965 for (i = 0; i < 4096; i++) {
1966 val = gc_lut[i];
1967 data = (val << 16 | val << 8 | val); /* R, B, and G are same */
1968 outpdw(base + off, data);
1969 off += 4;
1970 }
1971 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
1972}
1973
1974uint32 igc_video_lut[] = { /* non linear */
1975 0x0, 0x1, 0x2, 0x4, 0x5, 0x6, 0x7, 0x9,
1976 0xA, 0xB, 0xC, 0xE, 0xF, 0x10, 0x12, 0x14,
1977 0x15, 0x17, 0x19, 0x1B, 0x1D, 0x1F, 0x21, 0x23,
1978 0x25, 0x28, 0x2A, 0x2D, 0x30, 0x32, 0x35, 0x38,
1979 0x3B, 0x3E, 0x42, 0x45, 0x48, 0x4C, 0x4F, 0x53,
1980 0x57, 0x5B, 0x5F, 0x63, 0x67, 0x6B, 0x70, 0x74,
1981 0x79, 0x7E, 0x83, 0x88, 0x8D, 0x92, 0x97, 0x9C,
1982 0xA2, 0xA8, 0xAD, 0xB3, 0xB9, 0xBF, 0xC5, 0xCC,
1983 0xD2, 0xD8, 0xDF, 0xE6, 0xED, 0xF4, 0xFB, 0x102,
1984 0x109, 0x111, 0x118, 0x120, 0x128, 0x130, 0x138, 0x140,
1985 0x149, 0x151, 0x15A, 0x162, 0x16B, 0x174, 0x17D, 0x186,
1986 0x190, 0x199, 0x1A3, 0x1AC, 0x1B6, 0x1C0, 0x1CA, 0x1D5,
1987 0x1DF, 0x1EA, 0x1F4, 0x1FF, 0x20A, 0x215, 0x220, 0x22B,
1988 0x237, 0x242, 0x24E, 0x25A, 0x266, 0x272, 0x27F, 0x28B,
1989 0x298, 0x2A4, 0x2B1, 0x2BE, 0x2CB, 0x2D8, 0x2E6, 0x2F3,
1990 0x301, 0x30F, 0x31D, 0x32B, 0x339, 0x348, 0x356, 0x365,
1991 0x374, 0x383, 0x392, 0x3A1, 0x3B1, 0x3C0, 0x3D0, 0x3E0,
1992 0x3F0, 0x400, 0x411, 0x421, 0x432, 0x443, 0x454, 0x465,
1993 0x476, 0x487, 0x499, 0x4AB, 0x4BD, 0x4CF, 0x4E1, 0x4F3,
1994 0x506, 0x518, 0x52B, 0x53E, 0x551, 0x565, 0x578, 0x58C,
1995 0x5A0, 0x5B3, 0x5C8, 0x5DC, 0x5F0, 0x605, 0x61A, 0x62E,
1996 0x643, 0x659, 0x66E, 0x684, 0x699, 0x6AF, 0x6C5, 0x6DB,
1997 0x6F2, 0x708, 0x71F, 0x736, 0x74D, 0x764, 0x77C, 0x793,
1998 0x7AB, 0x7C3, 0x7DB, 0x7F3, 0x80B, 0x824, 0x83D, 0x855,
1999 0x86F, 0x888, 0x8A1, 0x8BB, 0x8D4, 0x8EE, 0x908, 0x923,
2000 0x93D, 0x958, 0x973, 0x98E, 0x9A9, 0x9C4, 0x9DF, 0x9FB,
2001 0xA17, 0xA33, 0xA4F, 0xA6C, 0xA88, 0xAA5, 0xAC2, 0xADF,
2002 0xAFC, 0xB19, 0xB37, 0xB55, 0xB73, 0xB91, 0xBAF, 0xBCE,
2003 0xBEC, 0xC0B, 0xC2A, 0xC4A, 0xC69, 0xC89, 0xCA8, 0xCC8,
2004 0xCE8, 0xD09, 0xD29, 0xD4A, 0xD6B, 0xD8C, 0xDAD, 0xDCF,
2005 0xDF0, 0xE12, 0xE34, 0xE56, 0xE79, 0xE9B, 0xEBE, 0xEE1,
2006 0xF04, 0xF27, 0xF4B, 0xF6E, 0xF92, 0xFB6, 0xFDB, 0xFFF,
2007};
2008
2009void mdp4_vg_igc_lut_setup(int vp_num)
2010{
2011 unsigned char *base;
2012 int i, voff, off;
2013 uint32 data, val;
2014
2015 voff = MDP4_VIDEO_OFF * vp_num;
2016 base = MDP_BASE + MDP4_VIDEO_BASE + voff + 0x5000;
2017
2018 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
2019 off = 0;
2020 for (i = 0; i < 256; i++) {
2021 val = igc_video_lut[i];
2022 data = (val << 16 | val); /* color 0 and 1 */
2023 outpdw(base + off, data);
2024 outpdw(base + off + 0x800, val); /* color 2 */
2025 off += 4;
2026 }
2027 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
2028}
2029
2030uint32 igc_rgb_lut[] = { /* linear */
2031 0x0, 0x10, 0x20, 0x30, 0x40, 0x50, 0x60, 0x70,
2032 0x80, 0x91, 0xA1, 0xB1, 0xC1, 0xD1, 0xE1, 0xF1,
2033 0x101, 0x111, 0x121, 0x131, 0x141, 0x151, 0x161, 0x171,
2034 0x181, 0x191, 0x1A2, 0x1B2, 0x1C2, 0x1D2, 0x1E2, 0x1F2,
2035 0x202, 0x212, 0x222, 0x232, 0x242, 0x252, 0x262, 0x272,
2036 0x282, 0x292, 0x2A2, 0x2B3, 0x2C3, 0x2D3, 0x2E3, 0x2F3,
2037 0x303, 0x313, 0x323, 0x333, 0x343, 0x353, 0x363, 0x373,
2038 0x383, 0x393, 0x3A3, 0x3B3, 0x3C4, 0x3D4, 0x3E4, 0x3F4,
2039 0x404, 0x414, 0x424, 0x434, 0x444, 0x454, 0x464, 0x474,
2040 0x484, 0x494, 0x4A4, 0x4B4, 0x4C4, 0x4D5, 0x4E5, 0x4F5,
2041 0x505, 0x515, 0x525, 0x535, 0x545, 0x555, 0x565, 0x575,
2042 0x585, 0x595, 0x5A5, 0x5B5, 0x5C5, 0x5D5, 0x5E6, 0x5F6,
2043 0x606, 0x616, 0x626, 0x636, 0x646, 0x656, 0x666, 0x676,
2044 0x686, 0x696, 0x6A6, 0x6B6, 0x6C6, 0x6D6, 0x6E6, 0x6F7,
2045 0x707, 0x717, 0x727, 0x737, 0x747, 0x757, 0x767, 0x777,
2046 0x787, 0x797, 0x7A7, 0x7B7, 0x7C7, 0x7D7, 0x7E7, 0x7F7,
2047 0x808, 0x818, 0x828, 0x838, 0x848, 0x858, 0x868, 0x878,
2048 0x888, 0x898, 0x8A8, 0x8B8, 0x8C8, 0x8D8, 0x8E8, 0x8F8,
2049 0x908, 0x919, 0x929, 0x939, 0x949, 0x959, 0x969, 0x979,
2050 0x989, 0x999, 0x9A9, 0x9B9, 0x9C9, 0x9D9, 0x9E9, 0x9F9,
2051 0xA09, 0xA19, 0xA2A, 0xA3A, 0xA4A, 0xA5A, 0xA6A, 0xA7A,
2052 0xA8A, 0xA9A, 0xAAA, 0xABA, 0xACA, 0xADA, 0xAEA, 0xAFA,
2053 0xB0A, 0xB1A, 0xB2A, 0xB3B, 0xB4B, 0xB5B, 0xB6B, 0xB7B,
2054 0xB8B, 0xB9B, 0xBAB, 0xBBB, 0xBCB, 0xBDB, 0xBEB, 0xBFB,
2055 0xC0B, 0xC1B, 0xC2B, 0xC3B, 0xC4C, 0xC5C, 0xC6C, 0xC7C,
2056 0xC8C, 0xC9C, 0xCAC, 0xCBC, 0xCCC, 0xCDC, 0xCEC, 0xCFC,
2057 0xD0C, 0xD1C, 0xD2C, 0xD3C, 0xD4C, 0xD5D, 0xD6D, 0xD7D,
2058 0xD8D, 0xD9D, 0xDAD, 0xDBD, 0xDCD, 0xDDD, 0xDED, 0xDFD,
2059 0xE0D, 0xE1D, 0xE2D, 0xE3D, 0xE4D, 0xE5D, 0xE6E, 0xE7E,
2060 0xE8E, 0xE9E, 0xEAE, 0xEBE, 0xECE, 0xEDE, 0xEEE, 0xEFE,
2061 0xF0E, 0xF1E, 0xF2E, 0xF3E, 0xF4E, 0xF5E, 0xF6E, 0xF7F,
2062 0xF8F, 0xF9F, 0xFAF, 0xFBF, 0xFCF, 0xFDF, 0xFEF, 0xFFF,
2063};
2064
2065void mdp4_rgb_igc_lut_setup(int num)
2066{
2067 unsigned char *base;
2068 int i, voff, off;
2069 uint32 data, val;
2070
2071 voff = MDP4_RGB_OFF * num;
2072 base = MDP_BASE + MDP4_RGB_BASE + voff + 0x5000;
2073
2074 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
2075 off = 0;
2076 for (i = 0; i < 256; i++) {
2077 val = igc_rgb_lut[i];
2078 data = (val << 16 | val); /* color 0 and 1 */
2079 outpdw(base + off, data);
2080 outpdw(base + off + 0x800, val); /* color 2 */
2081 off += 4;
2082 }
2083 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
2084}
2085
2086uint32 mdp4_rgb_igc_lut_cvt(uint32 ndx)
2087{
2088 return igc_rgb_lut[ndx & 0x0ff];
2089}
2090
2091uint32_t mdp4_ss_table_value(int8_t value, int8_t index)
2092{
2093 uint32_t out = 0x0;
2094 int8_t level = -1;
2095 uint32_t mask = 0xffffffff;
2096
2097 if (value < 0) {
2098 if (value == -128)
2099 value = 127;
2100 else
2101 value = -value;
2102 out = 0x11111111;
2103 } else {
2104 out = 0x88888888;
2105 mask = 0x0fffffff;
2106 }
2107
2108 if (value == 0)
2109 level = 0;
2110 else {
2111 while (value > 0 && level < 7) {
2112 level++;
2113 value -= 16;
2114 }
2115 }
2116
2117 if (level == 0) {
2118 if (index == 0)
2119 out = 0x0;
2120 else
2121 out = 0x20000000;
2122 } else {
2123 out += (0x11111111 * level);
2124 if (index == 1)
2125 out &= mask;
2126 }
2127
2128 return out;
2129}
2130
Carl Vanderlipdaa069f2011-11-28 14:09:24 -0800[diff] [blame]2131static uint32_t mdp4_csc_block2base(uint32_t block)
2132{
2133 uint32_t base = 0x0;
2134 switch (block) {
2135 case MDP_BLOCK_OVERLAY_1:
2136 base = 0x1A000;
2137 break;
Pravin Tamkhaneb18c9e22012-04-13 18:29:34 -0700[diff] [blame]2138 case MDP_BLOCK_OVERLAY_2:
Kalyan Thota79b217a2012-09-20 16:57:51 +0530[diff] [blame]2139 base = (mdp_rev >= MDP_REV_43) ? 0x8A000 : 0x0;
Pravin Tamkhaneb18c9e22012-04-13 18:29:34 -0700[diff] [blame]2140 break;
Carl Vanderlipdaa069f2011-11-28 14:09:24 -0800[diff] [blame]2141 case MDP_BLOCK_VG_1:
2142 base = 0x24000;
2143 break;
2144 case MDP_BLOCK_VG_2:
2145 base = 0x34000;
2146 break;
2147 case MDP_BLOCK_DMA_P:
2148 base = 0x93000;
2149 break;
Carl Vanderlipfa1de672011-12-05 12:37:59 -0800[diff] [blame]2150 case MDP_BLOCK_DMA_S:
2151 base = (mdp_rev >= MDP_REV_42) ? 0xA3000 : 0x0;
Carl Vanderlipdaa069f2011-11-28 14:09:24 -0800[diff] [blame]2152 default:
2153 break;
2154 }
2155 return base;
2156}
2157
Carl Vanderlipfa1de672011-12-05 12:37:59 -0800[diff] [blame]2158int mdp4_csc_enable(struct mdp_csc_cfg_data *config)
Carl Vanderlipdaa069f2011-11-28 14:09:24 -0800[diff] [blame]2159{
2160 uint32_t output, base, temp, mask;
2161
2162 switch (config->block) {
2163 case MDP_BLOCK_DMA_P:
2164 base = 0x90070;
2165 output = (config->csc_data.flags << 3) & (0x08);
2166 temp = (config->csc_data.flags << 10) & (0x1800);
2167 output |= temp;
2168 mask = 0x08 | 0x1800;
2169 break;
Carl Vanderlipfa1de672011-12-05 12:37:59 -0800[diff] [blame]2170 case MDP_BLOCK_DMA_S:
2171 base = 0xA0028;
2172 output = (config->csc_data.flags << 3) & (0x08);
2173 temp = (config->csc_data.flags << 10) & (0x1800);
2174 output |= temp;
2175 mask = 0x08 | 0x1800;
2176 break;
Carl Vanderlipdaa069f2011-11-28 14:09:24 -0800[diff] [blame]2177 case MDP_BLOCK_VG_1:
Carl Vanderlipfa1de672011-12-05 12:37:59 -0800[diff] [blame]2178 base = 0x20058;
2179 output = (config->csc_data.flags << 11) & (0x800);
2180 temp = (config->csc_data.flags << 8) & (0x600);
2181 output |= temp;
2182 mask = 0x800 | 0x600;
2183 break;
Carl Vanderlipdaa069f2011-11-28 14:09:24 -0800[diff] [blame]2184 case MDP_BLOCK_VG_2:
Carl Vanderlipfa1de672011-12-05 12:37:59 -0800[diff] [blame]2185 base = 0x30058;
2186 output = (config->csc_data.flags << 11) & (0x800);
2187 temp = (config->csc_data.flags << 8) & (0x600);
2188 output |= temp;
2189 mask = 0x800 | 0x600;
2190 break;
Carl Vanderlipdaa069f2011-11-28 14:09:24 -0800[diff] [blame]2191 case MDP_BLOCK_OVERLAY_1:
Carl Vanderlipfa1de672011-12-05 12:37:59 -0800[diff] [blame]2192 base = 0x18200;
2193 output = config->csc_data.flags;
2194 mask = 0x07;
2195 break;
Pravin Tamkhaneb18c9e22012-04-13 18:29:34 -0700[diff] [blame]2196 case MDP_BLOCK_OVERLAY_2:
2197 base = 0x88200;
2198 output = config->csc_data.flags;
2199 mask = 0x07;
2200 break;
Carl Vanderlipdaa069f2011-11-28 14:09:24 -0800[diff] [blame]2201 default:
2202 pr_err("%s - CSC block does not exist on MDP_BLOCK = %d\n",
2203 __func__, config->block);
2204 return -EINVAL;
2205 }
2206
2207 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
2208 temp = inpdw(MDP_BASE + base) & ~mask;
2209 output |= temp;
2210 outpdw(MDP_BASE + base, output);
2211 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
2212 return 0;
2213}
2214
2215#define CSC_MV_OFF 0x400
2216#define CSC_BV_OFF 0x500
2217#define CSC_LV_OFF 0x600
2218#define CSC_POST_OFF 0x80
2219
Carl Vanderlipfa1de672011-12-05 12:37:59 -0800[diff] [blame]2220void mdp4_csc_write(struct mdp_csc_cfg *data, uint32_t base)
Carl Vanderlipdaa069f2011-11-28 14:09:24 -0800[diff] [blame]2221{
Carl Vanderlipdaa069f2011-11-28 14:09:24 -0800[diff] [blame]2222 int i;
Carl Vanderlipfa1de672011-12-05 12:37:59 -0800[diff] [blame]2223 uint32_t *off;
Carl Vanderlipdaa069f2011-11-28 14:09:24 -0800[diff] [blame]2224
2225 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
Carl Vanderlipfa1de672011-12-05 12:37:59 -0800[diff] [blame]2226 off = (uint32_t *) ((uint32_t) base + CSC_MV_OFF);
Carl Vanderlipdaa069f2011-11-28 14:09:24 -0800[diff] [blame]2227 for (i = 0; i < 9; i++) {
Carl Vanderlipfa1de672011-12-05 12:37:59 -0800[diff] [blame]2228 outpdw(off, data->csc_mv[i]);
Carl Vanderlipdaa069f2011-11-28 14:09:24 -0800[diff] [blame]2229 off++;
2230 }
2231
Carl Vanderlipfa1de672011-12-05 12:37:59 -0800[diff] [blame]2232 off = (uint32_t *) ((uint32_t) base + CSC_BV_OFF);
Carl Vanderlipdaa069f2011-11-28 14:09:24 -0800[diff] [blame]2233 for (i = 0; i < 3; i++) {
Carl Vanderlipfa1de672011-12-05 12:37:59 -0800[diff] [blame]2234 outpdw(off, data->csc_pre_bv[i]);
Carl Vanderlipdaa069f2011-11-28 14:09:24 -0800[diff] [blame]2235 outpdw((uint32_t *)((uint32_t)off + CSC_POST_OFF),
Carl Vanderlipfa1de672011-12-05 12:37:59 -0800[diff] [blame]2236 data->csc_post_bv[i]);
Carl Vanderlipdaa069f2011-11-28 14:09:24 -0800[diff] [blame]2237 off++;
2238 }
2239
Carl Vanderlipfa1de672011-12-05 12:37:59 -0800[diff] [blame]2240 off = (uint32_t *) ((uint32_t) base + CSC_LV_OFF);
Carl Vanderlipdaa069f2011-11-28 14:09:24 -0800[diff] [blame]2241 for (i = 0; i < 6; i++) {
Carl Vanderlipfa1de672011-12-05 12:37:59 -0800[diff] [blame]2242 outpdw(off, data->csc_pre_lv[i]);
Carl Vanderlipdaa069f2011-11-28 14:09:24 -0800[diff] [blame]2243 outpdw((uint32_t *)((uint32_t)off + CSC_POST_OFF),
Carl Vanderlipfa1de672011-12-05 12:37:59 -0800[diff] [blame]2244 data->csc_post_lv[i]);
Carl Vanderlipdaa069f2011-11-28 14:09:24 -0800[diff] [blame]2245 off++;
2246 }
2247 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
Carl Vanderlipfa1de672011-12-05 12:37:59 -0800[diff] [blame]2248}
2249
2250int mdp4_csc_config(struct mdp_csc_cfg_data *config)
2251{
2252 int ret = 0;
2253 uint32_t base;
2254
2255 base = mdp4_csc_block2base(config->block);
2256 if (!base) {
2257 pr_warn("%s: Block type %d isn't supported by CSC.\n",
2258 __func__, config->block);
2259 return -EINVAL;
2260 }
2261
2262 mdp4_csc_write(&config->csc_data, (uint32_t) (MDP_BASE + base));
Carl Vanderlipdaa069f2011-11-28 14:09:24 -0800[diff] [blame]2263
2264 ret = mdp4_csc_enable(config);
2265
2266 return ret;
2267}
2268
Nagamalleswararao Ganji880f8472011-12-14 03:52:28 -0800[diff] [blame]2269void mdp4_init_writeback_buf(struct msm_fb_data_type *mfd, u32 mix_num)
2270{
2271 struct mdp_buf_type *buf;
2272
2273 if (mix_num == MDP4_MIXER0)
2274 buf = mfd->ov0_wb_buf;
2275 else
2276 buf = mfd->ov1_wb_buf;
2277
2278 buf->ihdl = NULL;
Ravishangar Kalyanam97c332d2012-06-13 11:25:38 -0700[diff] [blame]2279 buf->write_addr = 0;
2280 buf->read_addr = 0;
Nagamalleswararao Ganji880f8472011-12-14 03:52:28 -0800[diff] [blame]2281}
2282
2283u32 mdp4_allocate_writeback_buf(struct msm_fb_data_type *mfd, u32 mix_num)
2284{
2285 struct mdp_buf_type *buf;
Ravishangar Kalyanam97c332d2012-06-13 11:25:38 -0700[diff] [blame]2286 ion_phys_addr_t addr, read_addr = 0;
Ravishangar Kalyanam6b7005c2012-04-06 18:58:44 -0700[diff] [blame]2287 size_t buffer_size;
Ravishangar Kalyanam6bc448a2012-03-14 11:31:52 -0700[diff] [blame]2288 unsigned long len;
Nagamalleswararao Ganji880f8472011-12-14 03:52:28 -0800[diff] [blame]2289
2290 if (mix_num == MDP4_MIXER0)
2291 buf = mfd->ov0_wb_buf;
2292 else
2293 buf = mfd->ov1_wb_buf;
2294
Ravishangar Kalyanam97c332d2012-06-13 11:25:38 -0700[diff] [blame]2295 if (buf->write_addr || !IS_ERR_OR_NULL(buf->ihdl))
Nagamalleswararao Ganji880f8472011-12-14 03:52:28 -0800[diff] [blame]2296 return 0;
2297
2298 if (!buf->size) {
Ravishangar Kalyanam175d1282012-01-20 16:57:23 -0800[diff] [blame]2299 pr_err("%s:%d In valid size\n", __func__, __LINE__);
Nagamalleswararao Ganji880f8472011-12-14 03:52:28 -0800[diff] [blame]2300 return -EINVAL;
2301 }
2302
Ravishangar Kalyanam6b7005c2012-04-06 18:58:44 -0700[diff] [blame]2303 buffer_size = roundup(mfd->panel_info.xres * \
2304 mfd->panel_info.yres * 3 * 2, SZ_4K);
2305
Nagamalleswararao Ganji880f8472011-12-14 03:52:28 -0800[diff] [blame]2306 if (!IS_ERR_OR_NULL(mfd->iclient)) {
Ravishangar Kalyanama3b168b2012-03-26 11:13:11 -0700[diff] [blame]2307 pr_info("%s:%d ion based allocation mfd->mem_hid 0x%x\n",
2308 __func__, __LINE__, mfd->mem_hid);
Ravishangar Kalyanam6b7005c2012-04-06 18:58:44 -0700[diff] [blame]2309 buf->ihdl = ion_alloc(mfd->iclient, buffer_size, SZ_4K,
Hanumant Singh2ac41c92012-08-29 18:39:44 -0700[diff] [blame]2310 mfd->mem_hid, 0);
Nagamalleswararao Ganji880f8472011-12-14 03:52:28 -0800[diff] [blame]2311 if (!IS_ERR_OR_NULL(buf->ihdl)) {
Olav Hauganef95ae32012-05-15 09:50:30 -0700[diff] [blame]2312 if (mdp_iommu_split_domain) {
Ravishangar Kalyanam97c332d2012-06-13 11:25:38 -0700[diff] [blame]2313 if (ion_map_iommu(mfd->iclient, buf->ihdl,
2314 DISPLAY_READ_DOMAIN, GEN_POOL, SZ_4K,
2315 0, &read_addr, &len, 0, 0)) {
2316 pr_err("ion_map_iommu() read failed\n");
2317 return -ENOMEM;
2318 }
Olav Hauganef95ae32012-05-15 09:50:30 -0700[diff] [blame]2319 if (mfd->mem_hid & ION_SECURE) {
2320 if (ion_phys(mfd->iclient, buf->ihdl,
2321 &addr, (size_t *)&len)) {
2322 pr_err("%s:%d: ion_phys map failed\n",
2323 __func__, __LINE__);
2324 return -ENOMEM;
2325 }
2326 } else {
2327 if (ion_map_iommu(mfd->iclient,
2328 buf->ihdl, DISPLAY_WRITE_DOMAIN,
2329 GEN_POOL, SZ_4K, 0, &addr, &len,
2330 0, 0)) {
2331 pr_err("ion_map_iommu() failed\n");
2332 return -ENOMEM;
2333 }
2334 }
2335 } else {
2336 if (ion_map_iommu(mfd->iclient, buf->ihdl,
2337 DISPLAY_READ_DOMAIN, GEN_POOL, SZ_4K,
2338 0, &addr, &len, 0, 0)) {
Ravishangar Kalyanam97c332d2012-06-13 11:25:38 -0700[diff] [blame]2339 pr_err("ion_map_iommu() write failed\n");
Olav Hauganef95ae32012-05-15 09:50:30 -0700[diff] [blame]2340 return -ENOMEM;
2341 }
Nagamalleswararao Ganji880f8472011-12-14 03:52:28 -0800[diff] [blame]2342 }
2343 } else {
Ravishangar Kalyanam175d1282012-01-20 16:57:23 -0800[diff] [blame]2344 pr_err("%s:%d: ion_alloc failed\n", __func__,
Nagamalleswararao Ganji880f8472011-12-14 03:52:28 -0800[diff] [blame]2345 __LINE__);
2346 return -ENOMEM;
2347 }
2348 } else {
Ravishangar Kalyanam6b7005c2012-04-06 18:58:44 -0700[diff] [blame]2349 addr = allocate_contiguous_memory_nomap(buffer_size,
Nagamalleswararao Ganji880f8472011-12-14 03:52:28 -0800[diff] [blame]2350 mfd->mem_hid, 4);
2351 }
2352 if (addr) {
2353 pr_info("allocating %d bytes at %x for mdp writeback\n",
Ravishangar Kalyanam6b7005c2012-04-06 18:58:44 -0700[diff] [blame]2354 buffer_size, (u32) addr);
Ravishangar Kalyanam97c332d2012-06-13 11:25:38 -0700[diff] [blame]2355 buf->write_addr = addr;
2356
2357 if (read_addr)
2358 buf->read_addr = read_addr;
2359 else
2360 buf->read_addr = buf->write_addr;
2361
Nagamalleswararao Ganji880f8472011-12-14 03:52:28 -0800[diff] [blame]2362 return 0;
2363 } else {
2364 pr_err("%s cannot allocate memory for mdp writeback!\n",
2365 __func__);
2366 return -ENOMEM;
2367 }
2368}
2369
2370void mdp4_free_writeback_buf(struct msm_fb_data_type *mfd, u32 mix_num)
2371{
2372 struct mdp_buf_type *buf;
2373
2374 if (mix_num == MDP4_MIXER0)
2375 buf = mfd->ov0_wb_buf;
2376 else
2377 buf = mfd->ov1_wb_buf;
2378
2379 if (!IS_ERR_OR_NULL(mfd->iclient)) {
Ravishangar Kalyanam175d1282012-01-20 16:57:23 -0800[diff] [blame]2380 if (!IS_ERR_OR_NULL(buf->ihdl)) {
Olav Hauganef95ae32012-05-15 09:50:30 -0700[diff] [blame]2381 if (mdp_iommu_split_domain) {
2382 if (!(mfd->mem_hid & ION_SECURE))
2383 ion_unmap_iommu(mfd->iclient, buf->ihdl,
2384 DISPLAY_WRITE_DOMAIN, GEN_POOL);
Ravishangar Kalyanam97c332d2012-06-13 11:25:38 -0700[diff] [blame]2385 ion_unmap_iommu(mfd->iclient, buf->ihdl,
2386 DISPLAY_READ_DOMAIN, GEN_POOL);
Olav Hauganef95ae32012-05-15 09:50:30 -0700[diff] [blame]2387 } else {
2388 ion_unmap_iommu(mfd->iclient, buf->ihdl,
2389 DISPLAY_READ_DOMAIN, GEN_POOL);
2390 }
Nagamalleswararao Ganji880f8472011-12-14 03:52:28 -0800[diff] [blame]2391 ion_free(mfd->iclient, buf->ihdl);
Ravishangar Kalyanam175d1282012-01-20 16:57:23 -0800[diff] [blame]2392 buf->ihdl = NULL;
Kuogee Hsieh586fd162012-02-14 15:24:16 -0800[diff] [blame]2393 pr_info("%s:%d free ION writeback imem",
2394 __func__, __LINE__);
Ravishangar Kalyanam175d1282012-01-20 16:57:23 -0800[diff] [blame]2395 }
Nagamalleswararao Ganji880f8472011-12-14 03:52:28 -0800[diff] [blame]2396 } else {
Ravishangar Kalyanam97c332d2012-06-13 11:25:38 -0700[diff] [blame]2397 if (buf->write_addr) {
2398 free_contiguous_memory_by_paddr(buf->write_addr);
Jeff Ohlstein9cb0ead2011-12-16 13:30:08 -0800[diff] [blame]2399 pr_debug("%s:%d free writeback pmem\n", __func__,
Ravishangar Kalyanam175d1282012-01-20 16:57:23 -0800[diff] [blame]2400 __LINE__);
2401 }
Nagamalleswararao Ganji880f8472011-12-14 03:52:28 -0800[diff] [blame]2402 }
Ravishangar Kalyanam97c332d2012-06-13 11:25:38 -0700[diff] [blame]2403 buf->write_addr = 0;
2404 buf->read_addr = 0;
Nagamalleswararao Ganji880f8472011-12-14 03:52:28 -0800[diff] [blame]2405}
Pravin Tamkhane85153bd2011-12-13 13:56:46 -0800[diff] [blame]2406
2407static int mdp4_update_pcc_regs(uint32_t offset,
2408 struct mdp_pcc_cfg_data *cfg_ptr)
2409{
2410 int ret = -1;
2411
2412 if (offset && cfg_ptr) {
2413
2414 outpdw(offset, cfg_ptr->r.c);
2415 outpdw(offset + 0x30, cfg_ptr->g.c);
2416 outpdw(offset + 0x60, cfg_ptr->b.c);
2417 offset += 4;
2418
2419 outpdw(offset, cfg_ptr->r.r);
2420 outpdw(offset + 0x30, cfg_ptr->g.r);
2421 outpdw(offset + 0x60, cfg_ptr->b.r);
2422 offset += 4;
2423
2424 outpdw(offset, cfg_ptr->r.g);
2425 outpdw(offset + 0x30, cfg_ptr->g.g);
2426 outpdw(offset + 0x60, cfg_ptr->b.g);
2427 offset += 4;
2428
2429 outpdw(offset, cfg_ptr->r.b);
2430 outpdw(offset + 0x30, cfg_ptr->g.b);
2431 outpdw(offset + 0x60, cfg_ptr->b.b);
2432 offset += 4;
2433
2434 outpdw(offset, cfg_ptr->r.rr);
2435 outpdw(offset + 0x30, cfg_ptr->g.rr);
2436 outpdw(offset + 0x60, cfg_ptr->b.rr);
2437 offset += 4;
2438
2439 outpdw(offset, cfg_ptr->r.gg);
2440 outpdw(offset + 0x30, cfg_ptr->g.gg);
2441 outpdw(offset + 0x60, cfg_ptr->b.gg);
2442 offset += 4;
2443
2444 outpdw(offset, cfg_ptr->r.bb);
2445 outpdw(offset + 0x30, cfg_ptr->g.bb);
2446 outpdw(offset + 0x60, cfg_ptr->b.bb);
2447 offset += 4;
2448
2449 outpdw(offset, cfg_ptr->r.rg);
2450 outpdw(offset + 0x30, cfg_ptr->g.rg);
2451 outpdw(offset + 0x60, cfg_ptr->b.rg);
2452 offset += 4;
2453
2454 outpdw(offset, cfg_ptr->r.gb);
2455 outpdw(offset + 0x30, cfg_ptr->g.gb);
2456 outpdw(offset + 0x60, cfg_ptr->b.gb);
2457 offset += 4;
2458
2459 outpdw(offset, cfg_ptr->r.rb);
2460 outpdw(offset + 0x30, cfg_ptr->g.rb);
2461 outpdw(offset + 0x60, cfg_ptr->b.rb);
2462 offset += 4;
2463
2464 outpdw(offset, cfg_ptr->r.rgb_0);
2465 outpdw(offset + 0x30, cfg_ptr->g.rgb_0);
2466 outpdw(offset + 0x60, cfg_ptr->b.rgb_0);
2467 offset += 4;
2468
2469 outpdw(offset, cfg_ptr->r.rgb_1);
2470 outpdw(offset + 0x30, cfg_ptr->g.rgb_1);
2471 outpdw(offset + 0x60, cfg_ptr->b.rgb_1);
2472
2473 ret = 0;
2474 }
2475
2476 return ret;
2477}
2478
2479static int mdp4_read_pcc_regs(uint32_t offset,
2480 struct mdp_pcc_cfg_data *cfg_ptr)
2481{
2482 int ret = -1;
2483
2484 if (offset && cfg_ptr) {
2485 cfg_ptr->r.c = inpdw(offset);
2486 cfg_ptr->g.c = inpdw(offset + 0x30);
2487 cfg_ptr->b.c = inpdw(offset + 0x60);
2488 offset += 4;
2489
2490 cfg_ptr->r.r = inpdw(offset);
2491 cfg_ptr->g.r = inpdw(offset + 0x30);
2492 cfg_ptr->b.r = inpdw(offset + 0x60);
2493 offset += 4;
2494
2495 cfg_ptr->r.g = inpdw(offset);
2496 cfg_ptr->g.g = inpdw(offset + 0x30);
2497 cfg_ptr->b.g = inpdw(offset + 0x60);
2498 offset += 4;
2499
2500 cfg_ptr->r.b = inpdw(offset);
2501 cfg_ptr->g.b = inpdw(offset + 0x30);
2502 cfg_ptr->b.b = inpdw(offset + 0x60);
2503 offset += 4;
2504
2505 cfg_ptr->r.rr = inpdw(offset);
2506 cfg_ptr->g.rr = inpdw(offset + 0x30);
2507 cfg_ptr->b.rr = inpdw(offset + 0x60);
2508 offset += 4;
2509
2510 cfg_ptr->r.gg = inpdw(offset);
2511 cfg_ptr->g.gg = inpdw(offset + 0x30);
2512 cfg_ptr->b.gg = inpdw(offset + 0x60);
2513 offset += 4;
2514
2515 cfg_ptr->r.bb = inpdw(offset);
2516 cfg_ptr->g.bb = inpdw(offset + 0x30);
2517 cfg_ptr->b.bb = inpdw(offset + 0x60);
2518 offset += 4;
2519
2520 cfg_ptr->r.rg = inpdw(offset);
2521 cfg_ptr->g.rg = inpdw(offset + 0x30);
2522 cfg_ptr->b.rg = inpdw(offset + 0x60);
2523 offset += 4;
2524
2525 cfg_ptr->r.gb = inpdw(offset);
2526 cfg_ptr->g.gb = inpdw(offset + 0x30);
2527 cfg_ptr->b.gb = inpdw(offset + 0x60);
2528 offset += 4;
2529
2530 cfg_ptr->r.rb = inpdw(offset);
2531 cfg_ptr->g.rb = inpdw(offset + 0x30);
2532 cfg_ptr->b.rb = inpdw(offset + 0x60);
2533 offset += 4;
2534
2535 cfg_ptr->r.rgb_0 = inpdw(offset);
2536 cfg_ptr->g.rgb_0 = inpdw(offset + 0x30);
2537 cfg_ptr->b.rgb_0 = inpdw(offset + 0x60);
2538 offset += 4;
2539
2540 cfg_ptr->r.rgb_1 = inpdw(offset);
2541 cfg_ptr->g.rgb_1 = inpdw(offset + 0x30);
2542 cfg_ptr->b.rgb_1 = inpdw(offset + 0x60);
2543
2544 ret = 0;
2545 }
2546
2547 return ret;
2548}
2549
Pravin Tamkhane85153bd2011-12-13 13:56:46 -0800[diff] [blame]2550
2551#define MDP_PCC_OFFSET 0xA000
Pravin Tamkhane22515242012-03-01 17:45:52 -0800[diff] [blame]2552#define MDP_DMA_GC_OFFSET 0x8800
Pravin Tamkhaneb18c9e22012-04-13 18:29:34 -0700[diff] [blame]2553#define MDP_LM_GC_OFFSET 0x4800
Pravin Tamkhane85153bd2011-12-13 13:56:46 -0800[diff] [blame]2554
2555#define MDP_DMA_P_OP_MODE_OFFSET 0x70
2556#define MDP_DMA_S_OP_MODE_OFFSET 0x28
Pravin Tamkhaneb18c9e22012-04-13 18:29:34 -0700[diff] [blame]2557#define MDP_LM_OP_MODE_OFFSET 0x14
Pravin Tamkhane85153bd2011-12-13 13:56:46 -0800[diff] [blame]2558
2559#define DMA_PCC_R2_OFFSET 0x100
2560
Pravin Tamkhane22515242012-03-01 17:45:52 -0800[diff] [blame]2561#define MDP_GC_COLOR_OFFSET 0x100
2562#define MDP_GC_PARMS_OFFSET 0x80
2563
2564#define MDP_AR_GC_MAX_STAGES 16
2565
2566static uint32_t mdp_pp_block2pcc(uint32_t block)
2567{
2568 uint32_t valid = 0;
2569
2570 switch (block) {
2571 case MDP_BLOCK_DMA_P:
2572 case MDP_BLOCK_DMA_S:
2573 valid = (mdp_rev >= MDP_REV_42) ? 1 : 0;
2574 break;
2575
2576 default:
2577 break;
2578 }
2579
2580 return valid;
2581}
2582
Pravin Tamkhane85153bd2011-12-13 13:56:46 -0800[diff] [blame]2583int mdp4_pcc_cfg(struct mdp_pcc_cfg_data *cfg_ptr)
2584{
2585 int ret = -1;
2586 uint32_t pcc_offset = 0, mdp_cfg_offset = 0;
2587 uint32_t mdp_dma_op_mode = 0;
Pravin Tamkhane22515242012-03-01 17:45:52 -0800[diff] [blame]2588 uint32_t blockbase;
2589
2590 if (!mdp_pp_block2pcc(cfg_ptr->block))
2591 return ret;
2592
2593 blockbase = mdp_block2base(cfg_ptr->block);
2594 if (!blockbase)
2595 return ret;
2596
2597 blockbase += (uint32_t) MDP_BASE;
Pravin Tamkhane85153bd2011-12-13 13:56:46 -0800[diff] [blame]2598
2599 switch (cfg_ptr->block) {
2600 case MDP_BLOCK_DMA_P:
Pravin Tamkhane85153bd2011-12-13 13:56:46 -0800[diff] [blame]2601 case MDP_BLOCK_DMA_S:
Pravin Tamkhane22515242012-03-01 17:45:52 -0800[diff] [blame]2602 pcc_offset = blockbase + MDP_PCC_OFFSET;
2603 mdp_cfg_offset = blockbase;
2604 mdp_dma_op_mode = blockbase +
2605 (MDP_BLOCK_DMA_P == cfg_ptr->block ?
2606 MDP_DMA_P_OP_MODE_OFFSET
2607 : MDP_DMA_S_OP_MODE_OFFSET);
Pravin Tamkhane85153bd2011-12-13 13:56:46 -0800[diff] [blame]2608 break;
2609
2610 default:
2611 break;
2612 }
2613
2614 if (0x8 & cfg_ptr->ops)
2615 pcc_offset += DMA_PCC_R2_OFFSET;
2616
2617 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
2618
2619 switch ((0x6 & cfg_ptr->ops)>>1) {
2620 case 0x1:
2621 ret = mdp4_read_pcc_regs(pcc_offset, cfg_ptr);
2622 break;
2623
2624 case 0x2:
2625 ret = mdp4_update_pcc_regs(pcc_offset, cfg_ptr);
2626 break;
2627
2628 default:
2629 break;
2630 }
2631
2632 if (0x8 & cfg_ptr->ops)
2633 outpdw(mdp_dma_op_mode,
Carl Vanderlip59e7b0e2012-04-06 15:51:44 -0700[diff] [blame]2634 ((inpdw(mdp_dma_op_mode) & ~(0x1<<10)) |
2635 ((0x8 & cfg_ptr->ops)<<10)));
Pravin Tamkhane85153bd2011-12-13 13:56:46 -0800[diff] [blame]2636
2637 outpdw(mdp_cfg_offset,
Carl Vanderlip59e7b0e2012-04-06 15:51:44 -0700[diff] [blame]2638 ((inpdw(mdp_cfg_offset) & ~(0x1<<29)) |
2639 ((cfg_ptr->ops & 0x1)<<29)));
Pravin Tamkhane85153bd2011-12-13 13:56:46 -0800[diff] [blame]2640
2641 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
2642
2643 return ret;
2644}
2645
Pravin Tamkhane22515242012-03-01 17:45:52 -0800[diff] [blame]2646static uint32_t mdp_pp_block2argc(uint32_t block)
2647{
2648 uint32_t valid = 0;
Pravin Tamkhanec7a7cc62011-12-15 16:25:45 -0800[diff] [blame]2649
Pravin Tamkhane22515242012-03-01 17:45:52 -0800[diff] [blame]2650 switch (block) {
2651 case MDP_BLOCK_DMA_P:
2652 case MDP_BLOCK_DMA_S:
2653 case MDP_BLOCK_OVERLAY_0:
2654 case MDP_BLOCK_OVERLAY_1:
2655 valid = (mdp_rev >= MDP_REV_42) ? 1 : 0;
2656 break;
Pravin Tamkhanec7a7cc62011-12-15 16:25:45 -0800[diff] [blame]2657
Pravin Tamkhaneb18c9e22012-04-13 18:29:34 -0700[diff] [blame]2658 case MDP_BLOCK_OVERLAY_2:
Kalyan Thota79b217a2012-09-20 16:57:51 +0530[diff] [blame]2659 valid = (mdp_rev >= MDP_REV_43) ? 1 : 0;
Pravin Tamkhaneb18c9e22012-04-13 18:29:34 -0700[diff] [blame]2660 break;
2661
Pravin Tamkhane22515242012-03-01 17:45:52 -0800[diff] [blame]2662 default:
2663 break;
2664 }
Pravin Tamkhanec7a7cc62011-12-15 16:25:45 -0800[diff] [blame]2665
Pravin Tamkhane22515242012-03-01 17:45:52 -0800[diff] [blame]2666 return valid;
2667}
Pravin Tamkhanec7a7cc62011-12-15 16:25:45 -0800[diff] [blame]2668
2669static int update_ar_gc_lut(uint32_t *offset, struct mdp_pgc_lut_data *lut_data)
2670{
Pravin Tamkhane5c1fa462012-03-07 17:49:09 -0800[diff] [blame]2671 int count = 0;
Pravin Tamkhanec7a7cc62011-12-15 16:25:45 -0800[diff] [blame]2672
2673 uint32_t *c0_offset = offset;
2674 uint32_t *c0_params_offset = (uint32_t *)((uint32_t)c0_offset
2675 + MDP_GC_PARMS_OFFSET);
2676
2677 uint32_t *c1_offset = (uint32_t *)((uint32_t)offset
2678 + MDP_GC_COLOR_OFFSET);
2679
2680 uint32_t *c1_params_offset = (uint32_t *)((uint32_t)c1_offset
2681 + MDP_GC_PARMS_OFFSET);
2682
2683 uint32_t *c2_offset = (uint32_t *)((uint32_t)offset
2684 + 2*MDP_GC_COLOR_OFFSET);
2685
2686 uint32_t *c2_params_offset = (uint32_t *)((uint32_t)c2_offset
2687 +MDP_GC_PARMS_OFFSET);
2688
2689
Pravin Tamkhane5c1fa462012-03-07 17:49:09 -0800[diff] [blame]2690 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
Pravin Tamkhanec7a7cc62011-12-15 16:25:45 -0800[diff] [blame]2691 for (count = 0; count < MDP_AR_GC_MAX_STAGES; count++) {
2692 if (count < lut_data->num_r_stages) {
2693 outpdw(c0_offset+count,
2694 ((0xfff & lut_data->r_data[count].x_start)
2695 | 0x10000));
2696
2697 outpdw(c0_params_offset+count,
2698 ((0x7fff & lut_data->r_data[count].slope)
2699 | ((0xffff
2700 & lut_data->r_data[count].offset)
2701 << 16)));
2702 } else
2703 outpdw(c0_offset+count, 0);
2704
2705 if (count < lut_data->num_b_stages) {
2706 outpdw(c1_offset+count,
2707 ((0xfff & lut_data->b_data[count].x_start)
2708 | 0x10000));
2709
2710 outpdw(c1_params_offset+count,
2711 ((0x7fff & lut_data->b_data[count].slope)
2712 | ((0xffff
2713 & lut_data->b_data[count].offset)
2714 << 16)));
2715 } else
2716 outpdw(c1_offset+count, 0);
2717
2718 if (count < lut_data->num_g_stages) {
2719 outpdw(c2_offset+count,
2720 ((0xfff & lut_data->g_data[count].x_start)
2721 | 0x10000));
2722
2723 outpdw(c2_params_offset+count,
2724 ((0x7fff & lut_data->g_data[count].slope)
2725 | ((0xffff
2726 & lut_data->g_data[count].offset)
2727 << 16)));
2728 } else
2729 outpdw(c2_offset+count, 0);
2730 }
2731
Pravin Tamkhane5c1fa462012-03-07 17:49:09 -0800[diff] [blame]2732 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
Pravin Tamkhanec7a7cc62011-12-15 16:25:45 -0800[diff] [blame]2733
Pravin Tamkhane5c1fa462012-03-07 17:49:09 -0800[diff] [blame]2734 return 0;
Pravin Tamkhanec7a7cc62011-12-15 16:25:45 -0800[diff] [blame]2735}
2736
Pravin Tamkhane5c1fa462012-03-07 17:49:09 -0800[diff] [blame]2737static int mdp4_argc_process_write_req(uint32_t *offset,
2738 struct mdp_pgc_lut_data *pgc_ptr)
Pravin Tamkhanec7a7cc62011-12-15 16:25:45 -0800[diff] [blame]2739{
Pravin Tamkhane22515242012-03-01 17:45:52 -0800[diff] [blame]2740 int ret = -1;
Pravin Tamkhanec7a7cc62011-12-15 16:25:45 -0800[diff] [blame]2741 struct mdp_ar_gc_lut_data r[MDP_AR_GC_MAX_STAGES];
2742 struct mdp_ar_gc_lut_data g[MDP_AR_GC_MAX_STAGES];
2743 struct mdp_ar_gc_lut_data b[MDP_AR_GC_MAX_STAGES];
2744
2745 ret = copy_from_user(&r[0], pgc_ptr->r_data,
Pravin Tamkhane22515242012-03-01 17:45:52 -0800[diff] [blame]2746 pgc_ptr->num_r_stages * sizeof(struct mdp_ar_gc_lut_data));
2747
Pravin Tamkhanec7a7cc62011-12-15 16:25:45 -0800[diff] [blame]2748 if (!ret) {
2749 ret = copy_from_user(&g[0],
Pravin Tamkhane22515242012-03-01 17:45:52 -0800[diff] [blame]2750 pgc_ptr->g_data,
2751 pgc_ptr->num_g_stages
2752 * sizeof(struct mdp_ar_gc_lut_data));
Pravin Tamkhanec7a7cc62011-12-15 16:25:45 -0800[diff] [blame]2753 if (!ret)
2754 ret = copy_from_user(&b[0],
Pravin Tamkhane22515242012-03-01 17:45:52 -0800[diff] [blame]2755 pgc_ptr->b_data,
2756 pgc_ptr->num_b_stages
2757 * sizeof(struct mdp_ar_gc_lut_data));
Pravin Tamkhanec7a7cc62011-12-15 16:25:45 -0800[diff] [blame]2758 }
2759
2760 if (ret)
2761 return ret;
2762
2763 pgc_ptr->r_data = &r[0];
2764 pgc_ptr->g_data = &g[0];
2765 pgc_ptr->b_data = &b[0];
2766
Pravin Tamkhane5c1fa462012-03-07 17:49:09 -0800[diff] [blame]2767 ret = update_ar_gc_lut(offset, pgc_ptr);
2768 return ret;
2769}
2770
2771int mdp4_argc_cfg(struct mdp_pgc_lut_data *pgc_ptr)
2772{
2773 int ret = -1;
2774 uint32_t *offset = 0, *pgc_enable_offset = 0, lshift_bits = 0;
2775 uint32_t blockbase;
2776
2777 if (!mdp_pp_block2argc(pgc_ptr->block))
2778 return ret;
2779
2780 blockbase = mdp_block2base(pgc_ptr->block);
2781 if (!blockbase)
2782 return ret;
2783
Pravin Tamkhane22515242012-03-01 17:45:52 -0800[diff] [blame]2784 blockbase += (uint32_t) MDP_BASE;
Pravin Tamkhane5c1fa462012-03-07 17:49:09 -0800[diff] [blame]2785 ret = 0;
Pravin Tamkhane22515242012-03-01 17:45:52 -0800[diff] [blame]2786
Pravin Tamkhanec7a7cc62011-12-15 16:25:45 -0800[diff] [blame]2787 switch (pgc_ptr->block) {
2788 case MDP_BLOCK_DMA_P:
Pravin Tamkhanec7a7cc62011-12-15 16:25:45 -0800[diff] [blame]2789 case MDP_BLOCK_DMA_S:
Pravin Tamkhane22515242012-03-01 17:45:52 -0800[diff] [blame]2790 offset = (uint32_t *)(blockbase + MDP_DMA_GC_OFFSET);
2791 pgc_enable_offset = (uint32_t *) blockbase;
Pravin Tamkhanec7a7cc62011-12-15 16:25:45 -0800[diff] [blame]2792 lshift_bits = 28;
2793 break;
2794
2795 case MDP_BLOCK_OVERLAY_0:
Pravin Tamkhanec7a7cc62011-12-15 16:25:45 -0800[diff] [blame]2796 case MDP_BLOCK_OVERLAY_1:
Pravin Tamkhaneb18c9e22012-04-13 18:29:34 -0700[diff] [blame]2797 case MDP_BLOCK_OVERLAY_2:
2798 offset = (uint32_t *)(blockbase + MDP_LM_GC_OFFSET);
Pravin Tamkhane22515242012-03-01 17:45:52 -0800[diff] [blame]2799 pgc_enable_offset = (uint32_t *)(blockbase
2800 + MDP_LM_OP_MODE_OFFSET);
Pravin Tamkhanec7a7cc62011-12-15 16:25:45 -0800[diff] [blame]2801 lshift_bits = 2;
2802 break;
2803
2804 default:
2805 ret = -1;
2806 break;
2807 }
2808
2809 if (!ret) {
Pravin Tamkhanec7a7cc62011-12-15 16:25:45 -0800[diff] [blame]2810
Pravin Tamkhane5c1fa462012-03-07 17:49:09 -0800[diff] [blame]2811 switch ((0x6 & pgc_ptr->flags)>>1) {
2812 case 0x1:
2813 ret = -ENOTTY;
2814 break;
Pravin Tamkhanec7a7cc62011-12-15 16:25:45 -0800[diff] [blame]2815
Pravin Tamkhane5c1fa462012-03-07 17:49:09 -0800[diff] [blame]2816 case 0x2:
2817 ret = mdp4_argc_process_write_req(offset, pgc_ptr);
2818 break;
2819
2820 default:
2821 break;
2822 }
2823
2824 if (!ret) {
2825 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
Carl Vanderlip59e7b0e2012-04-06 15:51:44 -0700[diff] [blame]2826 outpdw(pgc_enable_offset, (inpdw(pgc_enable_offset) &
2827 ~(0x1<<lshift_bits)) |
2828 ((0x1 & pgc_ptr->flags) << lshift_bits));
Pravin Tamkhane5c1fa462012-03-07 17:49:09 -0800[diff] [blame]2829 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF,
2830 FALSE);
2831 }
Pravin Tamkhanec7a7cc62011-12-15 16:25:45 -0800[diff] [blame]2832 }
2833
2834 return ret;
2835}
2836
Carl Vanderlipacde4b62011-12-16 15:50:56 -0800[diff] [blame]2837static uint32_t mdp4_pp_block2igc(uint32_t block)
2838{
2839 uint32_t valid = 0;
2840 switch (block) {
2841 case MDP_BLOCK_VG_1:
2842 valid = 0x1;
2843 break;
2844 case MDP_BLOCK_VG_2:
2845 valid = 0x1;
2846 break;
2847 case MDP_BLOCK_RGB_1:
2848 valid = 0x1;
2849 break;
2850 case MDP_BLOCK_RGB_2:
2851 valid = 0x1;
2852 break;
2853 case MDP_BLOCK_DMA_P:
2854 valid = (mdp_rev >= MDP_REV_40) ? 1 : 0;
2855 break;
2856 case MDP_BLOCK_DMA_S:
2857 valid = (mdp_rev >= MDP_REV_40) ? 1 : 0;
2858 break;
2859 default:
2860 break;
2861 }
2862 return valid;
2863}
2864
2865static int mdp4_igc_lut_write(struct mdp_igc_lut_data *cfg, uint32_t en_off,
2866 uint32_t lut_off)
2867{
2868 int i;
2869 uint32_t base, *off_low, *off_high;
2870 uint32_t low[cfg->len];
2871 uint32_t high[cfg->len];
2872
2873 base = mdp_block2base(cfg->block);
2874
2875 if (cfg->len != 256)
2876 return -EINVAL;
2877
2878 off_low = (uint32_t *)(MDP_BASE + base + lut_off);
2879 off_high = (uint32_t *)(MDP_BASE + base + lut_off + 0x800);
2880 if (copy_from_user(&low, cfg->c0_c1_data, cfg->len * sizeof(uint32_t)))
2881 return -EFAULT;
2882 if (copy_from_user(&high, cfg->c2_data, cfg->len * sizeof(uint32_t)))
2883 return -EFAULT;
2884
2885 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
2886 for (i = 0; i < cfg->len; i++) {
2887 MDP_OUTP(off_low++, low[i]);
2888 /*low address write should occur before high address write*/
2889 wmb();
2890 MDP_OUTP(off_high++, high[i]);
2891 }
2892 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
2893 return 0;
2894}
2895
2896static int mdp4_igc_lut_ctrl(struct mdp_igc_lut_data *cfg)
2897{
2898 uint32_t mask, out;
2899 uint32_t base = mdp_block2base(cfg->block);
2900 int8_t shift = 0;
2901
2902 switch (cfg->block) {
2903 case MDP_BLOCK_DMA_P:
2904 case MDP_BLOCK_DMA_S:
2905 base = base;
2906 shift = 30;
2907 break;
2908 case MDP_BLOCK_VG_1:
2909 case MDP_BLOCK_VG_2:
2910 case MDP_BLOCK_RGB_1:
2911 case MDP_BLOCK_RGB_2:
2912 base += 0x58;
2913 shift = 16;
2914 break;
2915 default:
2916 return -EINVAL;
2917
2918 }
2919 out = 1<<shift;
2920 mask = ~out;
2921 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
2922 out = inpdw(MDP_BASE + base) & mask;
2923 MDP_OUTP(MDP_BASE + base, out | ((cfg->ops & 0x1)<<shift));
2924 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
2925
2926 return 0;
2927}
2928
2929static int mdp4_igc_lut_write_cfg(struct mdp_igc_lut_data *cfg)
2930{
2931 int ret = 0;
2932
2933 switch (cfg->block) {
2934 case MDP_BLOCK_DMA_P:
2935 case MDP_BLOCK_DMA_S:
2936 ret = mdp4_igc_lut_write(cfg, 0x00, 0x9000);
2937 break;
2938 case MDP_BLOCK_VG_1:
2939 case MDP_BLOCK_VG_2:
2940 case MDP_BLOCK_RGB_1:
2941 case MDP_BLOCK_RGB_2:
2942 ret = mdp4_igc_lut_write(cfg, 0x58, 0x5000);
2943 break;
2944 default:
2945 ret = -EINVAL;
2946 }
2947
2948 return ret;
2949}
2950
2951int mdp4_igc_lut_config(struct mdp_igc_lut_data *cfg)
2952{
2953 int ret = 0;
2954
2955 if (!mdp4_pp_block2igc(cfg->block)) {
2956 ret = -ENOTTY;
2957 goto error;
2958 }
2959
2960 switch ((cfg->ops & 0x6) >> 1) {
2961 case 0x1:
2962 pr_info("%s: IGC LUT read not supported\n", __func__);
2963 break;
2964 case 0x2:
2965 ret = mdp4_igc_lut_write_cfg(cfg);
2966 if (ret)
2967 goto error;
2968 break;
2969 default:
2970 break;
2971 }
2972
2973 ret = mdp4_igc_lut_ctrl(cfg);
2974
2975error:
2976 return ret;
2977}
Carl Vanderlipe01bb5a2012-04-24 15:14:26 -0700[diff] [blame]2978
2979#define QSEED_TABLE_1_COUNT 2
2980#define QSEED_TABLE_2_COUNT 1024
2981
2982static uint32_t mdp4_pp_block2qseed(uint32_t block)
2983{
2984 uint32_t valid = 0;
2985 switch (block) {
2986 case MDP_BLOCK_VG_1:
2987 case MDP_BLOCK_VG_2:
2988 valid = 0x1;
2989 break;
2990 default:
2991 break;
2992 }
2993 return valid;
2994}
2995
Carl Vanderlipdfe57512012-07-23 12:34:47 -0700[diff] [blame]2996int mdp4_qseed_access_cfg(struct mdp_qseed_cfg *config, uint32_t base)
Carl Vanderlipe01bb5a2012-04-24 15:14:26 -0700[diff] [blame]2997{
2998 int i, ret = 0;
Carl Vanderlipe01bb5a2012-04-24 15:14:26 -0700[diff] [blame]2999 uint32_t *values;
3000
Carl Vanderlipdfe57512012-07-23 12:34:47 -0700[diff] [blame]3001 if ((config->table_num != 1) && (config->table_num != 2)) {
Carl Vanderlipe01bb5a2012-04-24 15:14:26 -0700[diff] [blame]3002 ret = -ENOTTY;
3003 goto error;
3004 }
3005
Carl Vanderlipdfe57512012-07-23 12:34:47 -0700[diff] [blame]3006 if (((config->table_num == 1) && (config->len != QSEED_TABLE_1_COUNT))
3007 || ((config->table_num == 2) &&
3008 (config->len != QSEED_TABLE_2_COUNT))) {
Carl Vanderlipe01bb5a2012-04-24 15:14:26 -0700[diff] [blame]3009 ret = -EINVAL;
3010 goto error;
3011 }
3012
Carl Vanderlipdfe57512012-07-23 12:34:47 -0700[diff] [blame]3013 values = kmalloc(config->len * sizeof(uint32_t), GFP_KERNEL);
Carl Vanderlipe01bb5a2012-04-24 15:14:26 -0700[diff] [blame]3014 if (!values) {
3015 ret = -ENOMEM;
3016 goto error;
3017 }
3018
Carl Vanderlipdfe57512012-07-23 12:34:47 -0700[diff] [blame]3019 base += (config->table_num == 1) ? MDP4_QSEED_TABLE1_OFF :
Carl Vanderlipfbf46722012-05-16 16:43:39 -0700[diff] [blame]3020 MDP4_QSEED_TABLE2_OFF;
3021
Carl Vanderlipdfe57512012-07-23 12:34:47 -0700[diff] [blame]3022 if (config->ops & MDP_PP_OPS_WRITE) {
3023 ret = copy_from_user(values, config->data,
3024 sizeof(uint32_t) * config->len);
Carl Vanderlipfbf46722012-05-16 16:43:39 -0700[diff] [blame]3025 if (ret) {
3026 pr_warn("%s: Error copying from user, %d", __func__,
3027 ret);
3028 ret = -EINVAL;
3029 goto err_mem;
3030 }
Carl Vanderlipdfe57512012-07-23 12:34:47 -0700[diff] [blame]3031 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
3032 for (i = 0; i < config->len; i++) {
Carl Vanderlip382b00b2012-05-16 16:45:07 -0700[diff] [blame]3033 if (!(base & 0x3FF))
3034 wmb();
Carl Vanderlipfbf46722012-05-16 16:43:39 -0700[diff] [blame]3035 MDP_OUTP(base , values[i]);
3036 base += sizeof(uint32_t);
3037 }
Carl Vanderlipdfe57512012-07-23 12:34:47 -0700[diff] [blame]3038 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
3039 } else if (config->ops & MDP_PP_OPS_READ) {
3040 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
3041 for (i = 0; i < config->len; i++) {
Carl Vanderlipfbf46722012-05-16 16:43:39 -0700[diff] [blame]3042 values[i] = inpdw(base);
Carl Vanderlip382b00b2012-05-16 16:45:07 -0700[diff] [blame]3043 if (!(base & 0x3FF))
3044 rmb();
Carl Vanderlipfbf46722012-05-16 16:43:39 -0700[diff] [blame]3045 base += sizeof(uint32_t);
3046 }
Carl Vanderlipdfe57512012-07-23 12:34:47 -0700[diff] [blame]3047 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
3048 ret = copy_to_user(config->data, values,
3049 sizeof(uint32_t) * config->len);
Carl Vanderlipfbf46722012-05-16 16:43:39 -0700[diff] [blame]3050 if (ret) {
3051 pr_warn("%s: Error copying to user, %d", __func__, ret);
3052 ret = -EINVAL;
3053 goto err_mem;
3054 }
Carl Vanderlipe01bb5a2012-04-24 15:14:26 -0700[diff] [blame]3055 }
3056
Carl Vanderlipfbf46722012-05-16 16:43:39 -0700[diff] [blame]3057err_mem:
Carl Vanderlipe01bb5a2012-04-24 15:14:26 -0700[diff] [blame]3058 kfree(values);
3059error:
3060 return ret;
3061}
3062
Carl Vanderlipdfe57512012-07-23 12:34:47 -0700[diff] [blame]3063int mdp4_qseed_cfg(struct mdp_qseed_cfg_data *config)
Carl Vanderlipe01bb5a2012-04-24 15:14:26 -0700[diff] [blame]3064{
3065 int ret = 0;
Carl Vanderlipdfe57512012-07-23 12:34:47 -0700[diff] [blame]3066 struct mdp_qseed_cfg *cfg = &config->qseed_data;
3067 uint32_t base;
Carl Vanderlipe01bb5a2012-04-24 15:14:26 -0700[diff] [blame]3068
Carl Vanderlipdfe57512012-07-23 12:34:47 -0700[diff] [blame]3069 if (!mdp4_pp_block2qseed(config->block)) {
Carl Vanderlipe01bb5a2012-04-24 15:14:26 -0700[diff] [blame]3070 ret = -ENOTTY;
3071 goto error;
3072 }
3073
Carl Vanderlipfbf46722012-05-16 16:43:39 -0700[diff] [blame]3074 if ((cfg->ops & MDP_PP_OPS_READ) && (cfg->ops & MDP_PP_OPS_WRITE)) {
3075 ret = -EPERM;
3076 pr_warn("%s: Cannot read and write on the same request\n",
3077 __func__);
3078 goto error;
Carl Vanderlipe01bb5a2012-04-24 15:14:26 -0700[diff] [blame]3079 }
Carl Vanderlipdfe57512012-07-23 12:34:47 -0700[diff] [blame]3080 base = (uint32_t) (MDP_BASE + mdp_block2base(config->block));
3081 ret = mdp4_qseed_access_cfg(cfg, base);
Carl Vanderlipfbf46722012-05-16 16:43:39 -0700[diff] [blame]3082
Carl Vanderlipe01bb5a2012-04-24 15:14:26 -0700[diff] [blame]3083error:
3084 return ret;
3085}