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Sarah Sharp7f84eef2009-04-27 19:53:56 -07001/*
2 * xHCI host controller driver
3 *
4 * Copyright (C) 2008 Intel Corp.
5 *
6 * Author: Sarah Sharp
7 * Some code borrowed from the Linux EHCI driver.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16 * for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software Foundation,
20 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 */
22
23/*
24 * Ring initialization rules:
25 * 1. Each segment is initialized to zero, except for link TRBs.
26 * 2. Ring cycle state = 0. This represents Producer Cycle State (PCS) or
27 * Consumer Cycle State (CCS), depending on ring function.
28 * 3. Enqueue pointer = dequeue pointer = address of first TRB in the segment.
29 *
30 * Ring behavior rules:
31 * 1. A ring is empty if enqueue == dequeue. This means there will always be at
32 * least one free TRB in the ring. This is useful if you want to turn that
33 * into a link TRB and expand the ring.
34 * 2. When incrementing an enqueue or dequeue pointer, if the next TRB is a
35 * link TRB, then load the pointer with the address in the link TRB. If the
36 * link TRB had its toggle bit set, you may need to update the ring cycle
37 * state (see cycle bit rules). You may have to do this multiple times
38 * until you reach a non-link TRB.
39 * 3. A ring is full if enqueue++ (for the definition of increment above)
40 * equals the dequeue pointer.
41 *
42 * Cycle bit rules:
43 * 1. When a consumer increments a dequeue pointer and encounters a toggle bit
44 * in a link TRB, it must toggle the ring cycle state.
45 * 2. When a producer increments an enqueue pointer and encounters a toggle bit
46 * in a link TRB, it must toggle the ring cycle state.
47 *
48 * Producer rules:
49 * 1. Check if ring is full before you enqueue.
50 * 2. Write the ring cycle state to the cycle bit in the TRB you're enqueuing.
51 * Update enqueue pointer between each write (which may update the ring
52 * cycle state).
53 * 3. Notify consumer. If SW is producer, it rings the doorbell for command
54 * and endpoint rings. If HC is the producer for the event ring,
55 * and it generates an interrupt according to interrupt modulation rules.
56 *
57 * Consumer rules:
58 * 1. Check if TRB belongs to you. If the cycle bit == your ring cycle state,
59 * the TRB is owned by the consumer.
60 * 2. Update dequeue pointer (which may update the ring cycle state) and
61 * continue processing TRBs until you reach a TRB which is not owned by you.
62 * 3. Notify the producer. SW is the consumer for the event ring, and it
63 * updates event ring dequeue pointer. HC is the consumer for the command and
64 * endpoint rings; it generates events on the event ring for these.
65 */
66
Sarah Sharp8a96c052009-04-27 19:59:19 -070067#include <linux/scatterlist.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090068#include <linux/slab.h>
Sarah Sharp7f84eef2009-04-27 19:53:56 -070069#include "xhci.h"
70
Andiry Xube88fe42010-10-14 07:22:57 -070071static int handle_cmd_in_cmd_wait_list(struct xhci_hcd *xhci,
72 struct xhci_virt_device *virt_dev,
73 struct xhci_event_cmd *event);
74
Sarah Sharp7f84eef2009-04-27 19:53:56 -070075/*
76 * Returns zero if the TRB isn't in this segment, otherwise it returns the DMA
77 * address of the TRB.
78 */
Sarah Sharp23e3be12009-04-29 19:05:20 -070079dma_addr_t xhci_trb_virt_to_dma(struct xhci_segment *seg,
Sarah Sharp7f84eef2009-04-27 19:53:56 -070080 union xhci_trb *trb)
81{
Sarah Sharp6071d832009-05-14 11:44:14 -070082 unsigned long segment_offset;
Sarah Sharp7f84eef2009-04-27 19:53:56 -070083
Sarah Sharp6071d832009-05-14 11:44:14 -070084 if (!seg || !trb || trb < seg->trbs)
Sarah Sharp7f84eef2009-04-27 19:53:56 -070085 return 0;
Sarah Sharp6071d832009-05-14 11:44:14 -070086 /* offset in TRBs */
87 segment_offset = trb - seg->trbs;
88 if (segment_offset > TRBS_PER_SEGMENT)
Sarah Sharp7f84eef2009-04-27 19:53:56 -070089 return 0;
Sarah Sharp6071d832009-05-14 11:44:14 -070090 return seg->dma + (segment_offset * sizeof(*trb));
Sarah Sharp7f84eef2009-04-27 19:53:56 -070091}
92
93/* Does this link TRB point to the first segment in a ring,
94 * or was the previous TRB the last TRB on the last segment in the ERST?
95 */
Dmitry Torokhov575688e2011-03-20 02:15:16 -070096static bool last_trb_on_last_seg(struct xhci_hcd *xhci, struct xhci_ring *ring,
Sarah Sharp7f84eef2009-04-27 19:53:56 -070097 struct xhci_segment *seg, union xhci_trb *trb)
98{
99 if (ring == xhci->event_ring)
100 return (trb == &seg->trbs[TRBS_PER_SEGMENT]) &&
101 (seg->next == xhci->event_ring->first_seg);
102 else
Matt Evans28ccd292011-03-29 13:40:46 +1100103 return le32_to_cpu(trb->link.control) & LINK_TOGGLE;
Sarah Sharp7f84eef2009-04-27 19:53:56 -0700104}
105
106/* Is this TRB a link TRB or was the last TRB the last TRB in this event ring
107 * segment? I.e. would the updated event TRB pointer step off the end of the
108 * event seg?
109 */
Dmitry Torokhov575688e2011-03-20 02:15:16 -0700110static int last_trb(struct xhci_hcd *xhci, struct xhci_ring *ring,
Sarah Sharp7f84eef2009-04-27 19:53:56 -0700111 struct xhci_segment *seg, union xhci_trb *trb)
112{
113 if (ring == xhci->event_ring)
114 return trb == &seg->trbs[TRBS_PER_SEGMENT];
115 else
Matt Evansf5960b62011-06-01 10:22:55 +1000116 return TRB_TYPE_LINK_LE32(trb->link.control);
Sarah Sharp7f84eef2009-04-27 19:53:56 -0700117}
118
Dmitry Torokhov575688e2011-03-20 02:15:16 -0700119static int enqueue_is_link_trb(struct xhci_ring *ring)
John Youn6c12db92010-05-10 15:33:00 -0700120{
121 struct xhci_link_trb *link = &ring->enqueue->link;
Matt Evansf5960b62011-06-01 10:22:55 +1000122 return TRB_TYPE_LINK_LE32(link->control);
John Youn6c12db92010-05-10 15:33:00 -0700123}
124
Sarah Sharpae636742009-04-29 19:02:31 -0700125/* Updates trb to point to the next TRB in the ring, and updates seg if the next
126 * TRB is in a new segment. This does not skip over link TRBs, and it does not
127 * effect the ring dequeue or enqueue pointers.
128 */
129static void next_trb(struct xhci_hcd *xhci,
130 struct xhci_ring *ring,
131 struct xhci_segment **seg,
132 union xhci_trb **trb)
133{
134 if (last_trb(xhci, ring, *seg, *trb)) {
135 *seg = (*seg)->next;
136 *trb = ((*seg)->trbs);
137 } else {
John Youna1669b22010-08-09 13:56:11 -0700138 (*trb)++;
Sarah Sharpae636742009-04-29 19:02:31 -0700139 }
140}
141
Sarah Sharp7f84eef2009-04-27 19:53:56 -0700142/*
143 * See Cycle bit rules. SW is the consumer for the event ring only.
144 * Don't make a ring full of link TRBs. That would be dumb and this would loop.
145 */
146static void inc_deq(struct xhci_hcd *xhci, struct xhci_ring *ring, bool consumer)
147{
148 union xhci_trb *next = ++(ring->dequeue);
Sarah Sharp66e49d82009-07-27 12:03:46 -0700149 unsigned long long addr;
Sarah Sharp7f84eef2009-04-27 19:53:56 -0700150
151 ring->deq_updates++;
152 /* Update the dequeue pointer further if that was a link TRB or we're at
153 * the end of an event ring segment (which doesn't have link TRBS)
154 */
155 while (last_trb(xhci, ring, ring->deq_seg, next)) {
156 if (consumer && last_trb_on_last_seg(xhci, ring, ring->deq_seg, next)) {
157 ring->cycle_state = (ring->cycle_state ? 0 : 1);
158 if (!in_interrupt())
Greg Kroah-Hartman700e2052009-04-29 19:14:08 -0700159 xhci_dbg(xhci, "Toggle cycle state for ring %p = %i\n",
160 ring,
Sarah Sharp7f84eef2009-04-27 19:53:56 -0700161 (unsigned int) ring->cycle_state);
162 }
163 ring->deq_seg = ring->deq_seg->next;
164 ring->dequeue = ring->deq_seg->trbs;
165 next = ring->dequeue;
166 }
Sarah Sharp66e49d82009-07-27 12:03:46 -0700167 addr = (unsigned long long) xhci_trb_virt_to_dma(ring->deq_seg, ring->dequeue);
Sarah Sharp7f84eef2009-04-27 19:53:56 -0700168}
169
170/*
171 * See Cycle bit rules. SW is the consumer for the event ring only.
172 * Don't make a ring full of link TRBs. That would be dumb and this would loop.
173 *
174 * If we've just enqueued a TRB that is in the middle of a TD (meaning the
175 * chain bit is set), then set the chain bit in all the following link TRBs.
176 * If we've enqueued the last TRB in a TD, make sure the following link TRBs
177 * have their chain bit cleared (so that each Link TRB is a separate TD).
178 *
179 * Section 6.4.4.1 of the 0.95 spec says link TRBs cannot have the chain bit
Sarah Sharpb0567b32009-08-07 14:04:36 -0700180 * set, but other sections talk about dealing with the chain bit set. This was
181 * fixed in the 0.96 specification errata, but we have to assume that all 0.95
182 * xHCI hardware can't handle the chain bit being cleared on a link TRB.
Sarah Sharp6cc30d82010-06-10 12:25:28 -0700183 *
184 * @more_trbs_coming: Will you enqueue more TRBs before calling
185 * prepare_transfer()?
Sarah Sharp7f84eef2009-04-27 19:53:56 -0700186 */
Sarah Sharp6cc30d82010-06-10 12:25:28 -0700187static void inc_enq(struct xhci_hcd *xhci, struct xhci_ring *ring,
Andiry Xu7e393a82011-09-23 14:19:54 -0700188 bool consumer, bool more_trbs_coming, bool isoc)
Sarah Sharp7f84eef2009-04-27 19:53:56 -0700189{
190 u32 chain;
191 union xhci_trb *next;
Sarah Sharp66e49d82009-07-27 12:03:46 -0700192 unsigned long long addr;
Sarah Sharp7f84eef2009-04-27 19:53:56 -0700193
Matt Evans28ccd292011-03-29 13:40:46 +1100194 chain = le32_to_cpu(ring->enqueue->generic.field[3]) & TRB_CHAIN;
Sarah Sharp7f84eef2009-04-27 19:53:56 -0700195 next = ++(ring->enqueue);
196
197 ring->enq_updates++;
198 /* Update the dequeue pointer further if that was a link TRB or we're at
199 * the end of an event ring segment (which doesn't have link TRBS)
200 */
201 while (last_trb(xhci, ring, ring->enq_seg, next)) {
202 if (!consumer) {
203 if (ring != xhci->event_ring) {
Sarah Sharp6cc30d82010-06-10 12:25:28 -0700204 /*
205 * If the caller doesn't plan on enqueueing more
206 * TDs before ringing the doorbell, then we
207 * don't want to give the link TRB to the
208 * hardware just yet. We'll give the link TRB
209 * back in prepare_ring() just before we enqueue
210 * the TD at the top of the ring.
211 */
212 if (!chain && !more_trbs_coming)
John Youn6c12db92010-05-10 15:33:00 -0700213 break;
Sarah Sharp6cc30d82010-06-10 12:25:28 -0700214
Andiry Xu7e393a82011-09-23 14:19:54 -0700215 /* If we're not dealing with 0.95 hardware or
216 * isoc rings on AMD 0.96 host,
Sarah Sharp6cc30d82010-06-10 12:25:28 -0700217 * carry over the chain bit of the previous TRB
218 * (which may mean the chain bit is cleared).
219 */
Andiry Xu7e393a82011-09-23 14:19:54 -0700220 if (!(isoc && (xhci->quirks & XHCI_AMD_0x96_HOST))
221 && !xhci_link_trb_quirk(xhci)) {
Matt Evans28ccd292011-03-29 13:40:46 +1100222 next->link.control &=
223 cpu_to_le32(~TRB_CHAIN);
224 next->link.control |=
225 cpu_to_le32(chain);
Sarah Sharpb0567b32009-08-07 14:04:36 -0700226 }
Sarah Sharp6cc30d82010-06-10 12:25:28 -0700227 /* Give this link TRB to the hardware */
228 wmb();
Matt Evans28ccd292011-03-29 13:40:46 +1100229 next->link.control ^= cpu_to_le32(TRB_CYCLE);
Sarah Sharp7f84eef2009-04-27 19:53:56 -0700230 }
231 /* Toggle the cycle bit after the last ring segment. */
232 if (last_trb_on_last_seg(xhci, ring, ring->enq_seg, next)) {
233 ring->cycle_state = (ring->cycle_state ? 0 : 1);
234 if (!in_interrupt())
Greg Kroah-Hartman700e2052009-04-29 19:14:08 -0700235 xhci_dbg(xhci, "Toggle cycle state for ring %p = %i\n",
236 ring,
Sarah Sharp7f84eef2009-04-27 19:53:56 -0700237 (unsigned int) ring->cycle_state);
238 }
239 }
240 ring->enq_seg = ring->enq_seg->next;
241 ring->enqueue = ring->enq_seg->trbs;
242 next = ring->enqueue;
243 }
Sarah Sharp66e49d82009-07-27 12:03:46 -0700244 addr = (unsigned long long) xhci_trb_virt_to_dma(ring->enq_seg, ring->enqueue);
Sarah Sharp7f84eef2009-04-27 19:53:56 -0700245}
246
247/*
248 * Check to see if there's room to enqueue num_trbs on the ring. See rules
249 * above.
250 * FIXME: this would be simpler and faster if we just kept track of the number
251 * of free TRBs in a ring.
252 */
253static int room_on_ring(struct xhci_hcd *xhci, struct xhci_ring *ring,
254 unsigned int num_trbs)
255{
256 int i;
257 union xhci_trb *enq = ring->enqueue;
258 struct xhci_segment *enq_seg = ring->enq_seg;
Sarah Sharp44ebd032010-05-18 16:05:26 -0700259 struct xhci_segment *cur_seg;
260 unsigned int left_on_ring;
Sarah Sharp7f84eef2009-04-27 19:53:56 -0700261
John Youn6c12db92010-05-10 15:33:00 -0700262 /* If we are currently pointing to a link TRB, advance the
263 * enqueue pointer before checking for space */
264 while (last_trb(xhci, ring, enq_seg, enq)) {
265 enq_seg = enq_seg->next;
266 enq = enq_seg->trbs;
267 }
268
Sarah Sharp7f84eef2009-04-27 19:53:56 -0700269 /* Check if ring is empty */
Sarah Sharp44ebd032010-05-18 16:05:26 -0700270 if (enq == ring->dequeue) {
271 /* Can't use link trbs */
272 left_on_ring = TRBS_PER_SEGMENT - 1;
273 for (cur_seg = enq_seg->next; cur_seg != enq_seg;
274 cur_seg = cur_seg->next)
275 left_on_ring += TRBS_PER_SEGMENT - 1;
276
277 /* Always need one TRB free in the ring. */
278 left_on_ring -= 1;
279 if (num_trbs > left_on_ring) {
280 xhci_warn(xhci, "Not enough room on ring; "
281 "need %u TRBs, %u TRBs left\n",
282 num_trbs, left_on_ring);
283 return 0;
284 }
Sarah Sharp7f84eef2009-04-27 19:53:56 -0700285 return 1;
Sarah Sharp44ebd032010-05-18 16:05:26 -0700286 }
Sarah Sharp7f84eef2009-04-27 19:53:56 -0700287 /* Make sure there's an extra empty TRB available */
288 for (i = 0; i <= num_trbs; ++i) {
289 if (enq == ring->dequeue)
290 return 0;
291 enq++;
292 while (last_trb(xhci, ring, enq_seg, enq)) {
293 enq_seg = enq_seg->next;
294 enq = enq_seg->trbs;
295 }
296 }
297 return 1;
298}
299
Sarah Sharp7f84eef2009-04-27 19:53:56 -0700300/* Ring the host controller doorbell after placing a command on the ring */
Sarah Sharp23e3be12009-04-29 19:05:20 -0700301void xhci_ring_cmd_db(struct xhci_hcd *xhci)
Sarah Sharp7f84eef2009-04-27 19:53:56 -0700302{
Sarah Sharp7f84eef2009-04-27 19:53:56 -0700303 xhci_dbg(xhci, "// Ding dong!\n");
Matthew Wilcox50d64672010-12-15 14:18:11 -0500304 xhci_writel(xhci, DB_VALUE_HOST, &xhci->dba->doorbell[0]);
Sarah Sharp7f84eef2009-04-27 19:53:56 -0700305 /* Flush PCI posted writes */
306 xhci_readl(xhci, &xhci->dba->doorbell[0]);
307}
308
Andiry Xube88fe42010-10-14 07:22:57 -0700309void xhci_ring_ep_doorbell(struct xhci_hcd *xhci,
Sarah Sharpae636742009-04-29 19:02:31 -0700310 unsigned int slot_id,
Sarah Sharpe9df17e2010-04-02 15:34:43 -0700311 unsigned int ep_index,
312 unsigned int stream_id)
Sarah Sharpae636742009-04-29 19:02:31 -0700313{
Matt Evans28ccd292011-03-29 13:40:46 +1100314 __le32 __iomem *db_addr = &xhci->dba->doorbell[slot_id];
Matthew Wilcox50d64672010-12-15 14:18:11 -0500315 struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index];
316 unsigned int ep_state = ep->ep_state;
Sarah Sharpae636742009-04-29 19:02:31 -0700317
Sarah Sharpae636742009-04-29 19:02:31 -0700318 /* Don't ring the doorbell for this endpoint if there are pending
Matthew Wilcox50d64672010-12-15 14:18:11 -0500319 * cancellations because we don't want to interrupt processing.
Sarah Sharp8df75f42010-04-02 15:34:16 -0700320 * We don't want to restart any stream rings if there's a set dequeue
321 * pointer command pending because the device can choose to start any
322 * stream once the endpoint is on the HW schedule.
323 * FIXME - check all the stream rings for pending cancellations.
Sarah Sharpae636742009-04-29 19:02:31 -0700324 */
Matthew Wilcox50d64672010-12-15 14:18:11 -0500325 if ((ep_state & EP_HALT_PENDING) || (ep_state & SET_DEQ_PENDING) ||
326 (ep_state & EP_HALTED))
327 return;
328 xhci_writel(xhci, DB_VALUE(ep_index, stream_id), db_addr);
329 /* The CPU has better things to do at this point than wait for a
330 * write-posting flush. It'll get there soon enough.
331 */
Sarah Sharpae636742009-04-29 19:02:31 -0700332}
333
Sarah Sharpe9df17e2010-04-02 15:34:43 -0700334/* Ring the doorbell for any rings with pending URBs */
335static void ring_doorbell_for_active_rings(struct xhci_hcd *xhci,
336 unsigned int slot_id,
337 unsigned int ep_index)
338{
339 unsigned int stream_id;
340 struct xhci_virt_ep *ep;
341
342 ep = &xhci->devs[slot_id]->eps[ep_index];
343
344 /* A ring has pending URBs if its TD list is not empty */
345 if (!(ep->ep_state & EP_HAS_STREAMS)) {
346 if (!(list_empty(&ep->ring->td_list)))
Andiry Xube88fe42010-10-14 07:22:57 -0700347 xhci_ring_ep_doorbell(xhci, slot_id, ep_index, 0);
Sarah Sharpe9df17e2010-04-02 15:34:43 -0700348 return;
349 }
350
351 for (stream_id = 1; stream_id < ep->stream_info->num_streams;
352 stream_id++) {
353 struct xhci_stream_info *stream_info = ep->stream_info;
354 if (!list_empty(&stream_info->stream_rings[stream_id]->td_list))
Andiry Xube88fe42010-10-14 07:22:57 -0700355 xhci_ring_ep_doorbell(xhci, slot_id, ep_index,
356 stream_id);
Sarah Sharpe9df17e2010-04-02 15:34:43 -0700357 }
358}
359
Sarah Sharpae636742009-04-29 19:02:31 -0700360/*
361 * Find the segment that trb is in. Start searching in start_seg.
362 * If we must move past a segment that has a link TRB with a toggle cycle state
363 * bit set, then we will toggle the value pointed at by cycle_state.
364 */
365static struct xhci_segment *find_trb_seg(
366 struct xhci_segment *start_seg,
367 union xhci_trb *trb, int *cycle_state)
368{
369 struct xhci_segment *cur_seg = start_seg;
370 struct xhci_generic_trb *generic_trb;
371
372 while (cur_seg->trbs > trb ||
373 &cur_seg->trbs[TRBS_PER_SEGMENT - 1] < trb) {
374 generic_trb = &cur_seg->trbs[TRBS_PER_SEGMENT - 1].generic;
Matt Evansf5960b62011-06-01 10:22:55 +1000375 if (generic_trb->field[3] & cpu_to_le32(LINK_TOGGLE))
Sarah Sharpba0a4d92011-02-23 18:13:43 -0800376 *cycle_state ^= 0x1;
Sarah Sharpae636742009-04-29 19:02:31 -0700377 cur_seg = cur_seg->next;
378 if (cur_seg == start_seg)
379 /* Looped over the entire list. Oops! */
Randy Dunlap326b4812010-04-19 08:53:50 -0700380 return NULL;
Sarah Sharpae636742009-04-29 19:02:31 -0700381 }
382 return cur_seg;
383}
384
Sarah Sharp021bff92010-07-29 22:12:20 -0700385
386static struct xhci_ring *xhci_triad_to_transfer_ring(struct xhci_hcd *xhci,
387 unsigned int slot_id, unsigned int ep_index,
388 unsigned int stream_id)
389{
390 struct xhci_virt_ep *ep;
391
392 ep = &xhci->devs[slot_id]->eps[ep_index];
393 /* Common case: no streams */
394 if (!(ep->ep_state & EP_HAS_STREAMS))
395 return ep->ring;
396
397 if (stream_id == 0) {
398 xhci_warn(xhci,
399 "WARN: Slot ID %u, ep index %u has streams, "
400 "but URB has no stream ID.\n",
401 slot_id, ep_index);
402 return NULL;
403 }
404
405 if (stream_id < ep->stream_info->num_streams)
406 return ep->stream_info->stream_rings[stream_id];
407
408 xhci_warn(xhci,
409 "WARN: Slot ID %u, ep index %u has "
410 "stream IDs 1 to %u allocated, "
411 "but stream ID %u is requested.\n",
412 slot_id, ep_index,
413 ep->stream_info->num_streams - 1,
414 stream_id);
415 return NULL;
416}
417
418/* Get the right ring for the given URB.
419 * If the endpoint supports streams, boundary check the URB's stream ID.
420 * If the endpoint doesn't support streams, return the singular endpoint ring.
421 */
422static struct xhci_ring *xhci_urb_to_transfer_ring(struct xhci_hcd *xhci,
423 struct urb *urb)
424{
425 return xhci_triad_to_transfer_ring(xhci, urb->dev->slot_id,
426 xhci_get_endpoint_index(&urb->ep->desc), urb->stream_id);
427}
428
Sarah Sharpae636742009-04-29 19:02:31 -0700429/*
430 * Move the xHC's endpoint ring dequeue pointer past cur_td.
431 * Record the new state of the xHC's endpoint ring dequeue segment,
432 * dequeue pointer, and new consumer cycle state in state.
433 * Update our internal representation of the ring's dequeue pointer.
434 *
435 * We do this in three jumps:
436 * - First we update our new ring state to be the same as when the xHC stopped.
437 * - Then we traverse the ring to find the segment that contains
438 * the last TRB in the TD. We toggle the xHC's new cycle state when we pass
439 * any link TRBs with the toggle cycle bit set.
440 * - Finally we move the dequeue state one TRB further, toggling the cycle bit
441 * if we've moved it past a link TRB with the toggle cycle bit set.
Matt Evans28ccd292011-03-29 13:40:46 +1100442 *
443 * Some of the uses of xhci_generic_trb are grotty, but if they're done
444 * with correct __le32 accesses they should work fine. Only users of this are
445 * in here.
Sarah Sharpae636742009-04-29 19:02:31 -0700446 */
Sarah Sharpc92bcfa2009-07-27 12:05:21 -0700447void xhci_find_new_dequeue_state(struct xhci_hcd *xhci,
Sarah Sharpae636742009-04-29 19:02:31 -0700448 unsigned int slot_id, unsigned int ep_index,
Sarah Sharpe9df17e2010-04-02 15:34:43 -0700449 unsigned int stream_id, struct xhci_td *cur_td,
450 struct xhci_dequeue_state *state)
Sarah Sharpae636742009-04-29 19:02:31 -0700451{
452 struct xhci_virt_device *dev = xhci->devs[slot_id];
Sarah Sharpe9df17e2010-04-02 15:34:43 -0700453 struct xhci_ring *ep_ring;
Sarah Sharpae636742009-04-29 19:02:31 -0700454 struct xhci_generic_trb *trb;
John Yound115b042009-07-27 12:05:15 -0700455 struct xhci_ep_ctx *ep_ctx;
Sarah Sharpc92bcfa2009-07-27 12:05:21 -0700456 dma_addr_t addr;
Sarah Sharpae636742009-04-29 19:02:31 -0700457
Sarah Sharpe9df17e2010-04-02 15:34:43 -0700458 ep_ring = xhci_triad_to_transfer_ring(xhci, slot_id,
459 ep_index, stream_id);
460 if (!ep_ring) {
461 xhci_warn(xhci, "WARN can't find new dequeue state "
462 "for invalid stream ID %u.\n",
463 stream_id);
464 return;
465 }
Sarah Sharpae636742009-04-29 19:02:31 -0700466 state->new_cycle_state = 0;
Sarah Sharpc92bcfa2009-07-27 12:05:21 -0700467 xhci_dbg(xhci, "Finding segment containing stopped TRB.\n");
Sarah Sharpae636742009-04-29 19:02:31 -0700468 state->new_deq_seg = find_trb_seg(cur_td->start_seg,
Sarah Sharp63a0d9a2009-09-04 10:53:09 -0700469 dev->eps[ep_index].stopped_trb,
Sarah Sharpae636742009-04-29 19:02:31 -0700470 &state->new_cycle_state);
Paul Zimmerman68e41c52011-02-12 14:06:06 -0800471 if (!state->new_deq_seg) {
472 WARN_ON(1);
473 return;
474 }
475
Sarah Sharpae636742009-04-29 19:02:31 -0700476 /* Dig out the cycle state saved by the xHC during the stop ep cmd */
Sarah Sharpc92bcfa2009-07-27 12:05:21 -0700477 xhci_dbg(xhci, "Finding endpoint context\n");
John Yound115b042009-07-27 12:05:15 -0700478 ep_ctx = xhci_get_ep_ctx(xhci, dev->out_ctx, ep_index);
Matt Evans28ccd292011-03-29 13:40:46 +1100479 state->new_cycle_state = 0x1 & le64_to_cpu(ep_ctx->deq);
Sarah Sharpae636742009-04-29 19:02:31 -0700480
481 state->new_deq_ptr = cur_td->last_trb;
Sarah Sharpc92bcfa2009-07-27 12:05:21 -0700482 xhci_dbg(xhci, "Finding segment containing last TRB in TD.\n");
Sarah Sharpae636742009-04-29 19:02:31 -0700483 state->new_deq_seg = find_trb_seg(state->new_deq_seg,
484 state->new_deq_ptr,
485 &state->new_cycle_state);
Paul Zimmerman68e41c52011-02-12 14:06:06 -0800486 if (!state->new_deq_seg) {
487 WARN_ON(1);
488 return;
489 }
Sarah Sharpae636742009-04-29 19:02:31 -0700490
491 trb = &state->new_deq_ptr->generic;
Matt Evansf5960b62011-06-01 10:22:55 +1000492 if (TRB_TYPE_LINK_LE32(trb->field[3]) &&
493 (trb->field[3] & cpu_to_le32(LINK_TOGGLE)))
Sarah Sharpba0a4d92011-02-23 18:13:43 -0800494 state->new_cycle_state ^= 0x1;
Sarah Sharpae636742009-04-29 19:02:31 -0700495 next_trb(xhci, ep_ring, &state->new_deq_seg, &state->new_deq_ptr);
496
Sarah Sharp01a1fdb2011-02-23 18:12:29 -0800497 /*
498 * If there is only one segment in a ring, find_trb_seg()'s while loop
499 * will not run, and it will return before it has a chance to see if it
500 * needs to toggle the cycle bit. It can't tell if the stalled transfer
501 * ended just before the link TRB on a one-segment ring, or if the TD
502 * wrapped around the top of the ring, because it doesn't have the TD in
503 * question. Look for the one-segment case where stalled TRB's address
504 * is greater than the new dequeue pointer address.
505 */
506 if (ep_ring->first_seg == ep_ring->first_seg->next &&
507 state->new_deq_ptr < dev->eps[ep_index].stopped_trb)
508 state->new_cycle_state ^= 0x1;
509 xhci_dbg(xhci, "Cycle state = 0x%x\n", state->new_cycle_state);
510
Sarah Sharpae636742009-04-29 19:02:31 -0700511 /* Don't update the ring cycle state for the producer (us). */
Sarah Sharpc92bcfa2009-07-27 12:05:21 -0700512 xhci_dbg(xhci, "New dequeue segment = %p (virtual)\n",
513 state->new_deq_seg);
514 addr = xhci_trb_virt_to_dma(state->new_deq_seg, state->new_deq_ptr);
515 xhci_dbg(xhci, "New dequeue pointer = 0x%llx (DMA)\n",
516 (unsigned long long) addr);
Sarah Sharpae636742009-04-29 19:02:31 -0700517}
518
Sarah Sharp522989a2011-07-29 12:44:32 -0700519/* flip_cycle means flip the cycle bit of all but the first and last TRB.
520 * (The last TRB actually points to the ring enqueue pointer, which is not part
521 * of this TD.) This is used to remove partially enqueued isoc TDs from a ring.
522 */
Sarah Sharp23e3be12009-04-29 19:05:20 -0700523static void td_to_noop(struct xhci_hcd *xhci, struct xhci_ring *ep_ring,
Sarah Sharp522989a2011-07-29 12:44:32 -0700524 struct xhci_td *cur_td, bool flip_cycle)
Sarah Sharpae636742009-04-29 19:02:31 -0700525{
526 struct xhci_segment *cur_seg;
527 union xhci_trb *cur_trb;
528
529 for (cur_seg = cur_td->start_seg, cur_trb = cur_td->first_trb;
530 true;
531 next_trb(xhci, ep_ring, &cur_seg, &cur_trb)) {
Matt Evansf5960b62011-06-01 10:22:55 +1000532 if (TRB_TYPE_LINK_LE32(cur_trb->generic.field[3])) {
Sarah Sharpae636742009-04-29 19:02:31 -0700533 /* Unchain any chained Link TRBs, but
534 * leave the pointers intact.
535 */
Matt Evans28ccd292011-03-29 13:40:46 +1100536 cur_trb->generic.field[3] &= cpu_to_le32(~TRB_CHAIN);
Sarah Sharp522989a2011-07-29 12:44:32 -0700537 /* Flip the cycle bit (link TRBs can't be the first
538 * or last TRB).
539 */
540 if (flip_cycle)
541 cur_trb->generic.field[3] ^=
542 cpu_to_le32(TRB_CYCLE);
Sarah Sharpae636742009-04-29 19:02:31 -0700543 xhci_dbg(xhci, "Cancel (unchain) link TRB\n");
Greg Kroah-Hartman700e2052009-04-29 19:14:08 -0700544 xhci_dbg(xhci, "Address = %p (0x%llx dma); "
545 "in seg %p (0x%llx dma)\n",
546 cur_trb,
Sarah Sharp23e3be12009-04-29 19:05:20 -0700547 (unsigned long long)xhci_trb_virt_to_dma(cur_seg, cur_trb),
Greg Kroah-Hartman700e2052009-04-29 19:14:08 -0700548 cur_seg,
549 (unsigned long long)cur_seg->dma);
Sarah Sharpae636742009-04-29 19:02:31 -0700550 } else {
551 cur_trb->generic.field[0] = 0;
552 cur_trb->generic.field[1] = 0;
553 cur_trb->generic.field[2] = 0;
554 /* Preserve only the cycle bit of this TRB */
Matt Evans28ccd292011-03-29 13:40:46 +1100555 cur_trb->generic.field[3] &= cpu_to_le32(TRB_CYCLE);
Sarah Sharp522989a2011-07-29 12:44:32 -0700556 /* Flip the cycle bit except on the first or last TRB */
557 if (flip_cycle && cur_trb != cur_td->first_trb &&
558 cur_trb != cur_td->last_trb)
559 cur_trb->generic.field[3] ^=
560 cpu_to_le32(TRB_CYCLE);
Matt Evans28ccd292011-03-29 13:40:46 +1100561 cur_trb->generic.field[3] |= cpu_to_le32(
562 TRB_TYPE(TRB_TR_NOOP));
Greg Kroah-Hartman700e2052009-04-29 19:14:08 -0700563 xhci_dbg(xhci, "Cancel TRB %p (0x%llx dma) "
564 "in seg %p (0x%llx dma)\n",
565 cur_trb,
Sarah Sharp23e3be12009-04-29 19:05:20 -0700566 (unsigned long long)xhci_trb_virt_to_dma(cur_seg, cur_trb),
Greg Kroah-Hartman700e2052009-04-29 19:14:08 -0700567 cur_seg,
568 (unsigned long long)cur_seg->dma);
Sarah Sharpae636742009-04-29 19:02:31 -0700569 }
570 if (cur_trb == cur_td->last_trb)
571 break;
572 }
573}
574
575static int queue_set_tr_deq(struct xhci_hcd *xhci, int slot_id,
Sarah Sharpe9df17e2010-04-02 15:34:43 -0700576 unsigned int ep_index, unsigned int stream_id,
577 struct xhci_segment *deq_seg,
Sarah Sharpae636742009-04-29 19:02:31 -0700578 union xhci_trb *deq_ptr, u32 cycle_state);
579
Sarah Sharpc92bcfa2009-07-27 12:05:21 -0700580void xhci_queue_new_dequeue_state(struct xhci_hcd *xhci,
Sarah Sharp63a0d9a2009-09-04 10:53:09 -0700581 unsigned int slot_id, unsigned int ep_index,
Sarah Sharpe9df17e2010-04-02 15:34:43 -0700582 unsigned int stream_id,
Sarah Sharp63a0d9a2009-09-04 10:53:09 -0700583 struct xhci_dequeue_state *deq_state)
Sarah Sharpc92bcfa2009-07-27 12:05:21 -0700584{
Sarah Sharp63a0d9a2009-09-04 10:53:09 -0700585 struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index];
586
Sarah Sharpc92bcfa2009-07-27 12:05:21 -0700587 xhci_dbg(xhci, "Set TR Deq Ptr cmd, new deq seg = %p (0x%llx dma), "
588 "new deq ptr = %p (0x%llx dma), new cycle = %u\n",
589 deq_state->new_deq_seg,
590 (unsigned long long)deq_state->new_deq_seg->dma,
591 deq_state->new_deq_ptr,
592 (unsigned long long)xhci_trb_virt_to_dma(deq_state->new_deq_seg, deq_state->new_deq_ptr),
593 deq_state->new_cycle_state);
Sarah Sharpe9df17e2010-04-02 15:34:43 -0700594 queue_set_tr_deq(xhci, slot_id, ep_index, stream_id,
Sarah Sharpc92bcfa2009-07-27 12:05:21 -0700595 deq_state->new_deq_seg,
596 deq_state->new_deq_ptr,
597 (u32) deq_state->new_cycle_state);
598 /* Stop the TD queueing code from ringing the doorbell until
599 * this command completes. The HC won't set the dequeue pointer
600 * if the ring is running, and ringing the doorbell starts the
601 * ring running.
602 */
Sarah Sharp63a0d9a2009-09-04 10:53:09 -0700603 ep->ep_state |= SET_DEQ_PENDING;
Sarah Sharpc92bcfa2009-07-27 12:05:21 -0700604}
605
Dmitry Torokhov575688e2011-03-20 02:15:16 -0700606static void xhci_stop_watchdog_timer_in_irq(struct xhci_hcd *xhci,
Sarah Sharp6f5165c2009-10-27 10:57:01 -0700607 struct xhci_virt_ep *ep)
608{
609 ep->ep_state &= ~EP_HALT_PENDING;
610 /* Can't del_timer_sync in interrupt, so we attempt to cancel. If the
611 * timer is running on another CPU, we don't decrement stop_cmds_pending
612 * (since we didn't successfully stop the watchdog timer).
613 */
614 if (del_timer(&ep->stop_cmd_timer))
615 ep->stop_cmds_pending--;
616}
617
618/* Must be called with xhci->lock held in interrupt context */
619static void xhci_giveback_urb_in_irq(struct xhci_hcd *xhci,
620 struct xhci_td *cur_td, int status, char *adjective)
621{
Sarah Sharp214f76f2010-10-26 11:22:02 -0700622 struct usb_hcd *hcd;
Andiry Xu8e51adc2010-07-22 15:23:31 -0700623 struct urb *urb;
624 struct urb_priv *urb_priv;
Sarah Sharp6f5165c2009-10-27 10:57:01 -0700625
Andiry Xu8e51adc2010-07-22 15:23:31 -0700626 urb = cur_td->urb;
627 urb_priv = urb->hcpriv;
628 urb_priv->td_cnt++;
Sarah Sharp214f76f2010-10-26 11:22:02 -0700629 hcd = bus_to_hcd(urb->dev->bus);
Sarah Sharp6f5165c2009-10-27 10:57:01 -0700630
Andiry Xu8e51adc2010-07-22 15:23:31 -0700631 /* Only giveback urb when this is the last td in urb */
632 if (urb_priv->td_cnt == urb_priv->length) {
Andiry Xuc41136b2011-03-22 17:08:14 +0800633 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
634 xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs--;
635 if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs == 0) {
636 if (xhci->quirks & XHCI_AMD_PLL_FIX)
637 usb_amd_quirk_pll_enable();
638 }
639 }
Andiry Xu8e51adc2010-07-22 15:23:31 -0700640 usb_hcd_unlink_urb_from_ep(hcd, urb);
Andiry Xu8e51adc2010-07-22 15:23:31 -0700641
642 spin_unlock(&xhci->lock);
643 usb_hcd_giveback_urb(hcd, urb, status);
644 xhci_urb_free_priv(xhci, urb_priv);
645 spin_lock(&xhci->lock);
Andiry Xu8e51adc2010-07-22 15:23:31 -0700646 }
Sarah Sharp6f5165c2009-10-27 10:57:01 -0700647}
648
Sarah Sharpae636742009-04-29 19:02:31 -0700649/*
650 * When we get a command completion for a Stop Endpoint Command, we need to
651 * unlink any cancelled TDs from the ring. There are two ways to do that:
652 *
653 * 1. If the HW was in the middle of processing the TD that needs to be
654 * cancelled, then we must move the ring's dequeue pointer past the last TRB
655 * in the TD with a Set Dequeue Pointer Command.
656 * 2. Otherwise, we turn all the TRBs in the TD into No-op TRBs (with the chain
657 * bit cleared) so that the HW will skip over them.
658 */
659static void handle_stopped_endpoint(struct xhci_hcd *xhci,
Andiry Xube88fe42010-10-14 07:22:57 -0700660 union xhci_trb *trb, struct xhci_event_cmd *event)
Sarah Sharpae636742009-04-29 19:02:31 -0700661{
662 unsigned int slot_id;
663 unsigned int ep_index;
Andiry Xube88fe42010-10-14 07:22:57 -0700664 struct xhci_virt_device *virt_dev;
Sarah Sharpae636742009-04-29 19:02:31 -0700665 struct xhci_ring *ep_ring;
Sarah Sharp63a0d9a2009-09-04 10:53:09 -0700666 struct xhci_virt_ep *ep;
Sarah Sharpae636742009-04-29 19:02:31 -0700667 struct list_head *entry;
Randy Dunlap326b4812010-04-19 08:53:50 -0700668 struct xhci_td *cur_td = NULL;
Sarah Sharpae636742009-04-29 19:02:31 -0700669 struct xhci_td *last_unlinked_td;
670
Sarah Sharpc92bcfa2009-07-27 12:05:21 -0700671 struct xhci_dequeue_state deq_state;
Sarah Sharpae636742009-04-29 19:02:31 -0700672
Andiry Xube88fe42010-10-14 07:22:57 -0700673 if (unlikely(TRB_TO_SUSPEND_PORT(
Matt Evans28ccd292011-03-29 13:40:46 +1100674 le32_to_cpu(xhci->cmd_ring->dequeue->generic.field[3])))) {
Andiry Xube88fe42010-10-14 07:22:57 -0700675 slot_id = TRB_TO_SLOT_ID(
Matt Evans28ccd292011-03-29 13:40:46 +1100676 le32_to_cpu(xhci->cmd_ring->dequeue->generic.field[3]));
Andiry Xube88fe42010-10-14 07:22:57 -0700677 virt_dev = xhci->devs[slot_id];
678 if (virt_dev)
679 handle_cmd_in_cmd_wait_list(xhci, virt_dev,
680 event);
681 else
682 xhci_warn(xhci, "Stop endpoint command "
683 "completion for disabled slot %u\n",
684 slot_id);
685 return;
686 }
687
Sarah Sharpae636742009-04-29 19:02:31 -0700688 memset(&deq_state, 0, sizeof(deq_state));
Matt Evans28ccd292011-03-29 13:40:46 +1100689 slot_id = TRB_TO_SLOT_ID(le32_to_cpu(trb->generic.field[3]));
690 ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3]));
Sarah Sharp63a0d9a2009-09-04 10:53:09 -0700691 ep = &xhci->devs[slot_id]->eps[ep_index];
Sarah Sharpae636742009-04-29 19:02:31 -0700692
Sarah Sharp678539c2009-10-27 10:55:52 -0700693 if (list_empty(&ep->cancelled_td_list)) {
Sarah Sharp6f5165c2009-10-27 10:57:01 -0700694 xhci_stop_watchdog_timer_in_irq(xhci, ep);
Sarah Sharp0714a572011-05-24 11:53:29 -0700695 ep->stopped_td = NULL;
696 ep->stopped_trb = NULL;
Sarah Sharpe9df17e2010-04-02 15:34:43 -0700697 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
Sarah Sharpae636742009-04-29 19:02:31 -0700698 return;
Sarah Sharp678539c2009-10-27 10:55:52 -0700699 }
Sarah Sharpae636742009-04-29 19:02:31 -0700700
701 /* Fix up the ep ring first, so HW stops executing cancelled TDs.
702 * We have the xHCI lock, so nothing can modify this list until we drop
703 * it. We're also in the event handler, so we can't get re-interrupted
704 * if another Stop Endpoint command completes
705 */
Sarah Sharp63a0d9a2009-09-04 10:53:09 -0700706 list_for_each(entry, &ep->cancelled_td_list) {
Sarah Sharpae636742009-04-29 19:02:31 -0700707 cur_td = list_entry(entry, struct xhci_td, cancelled_td_list);
Greg Kroah-Hartman700e2052009-04-29 19:14:08 -0700708 xhci_dbg(xhci, "Cancelling TD starting at %p, 0x%llx (dma).\n",
709 cur_td->first_trb,
Sarah Sharp23e3be12009-04-29 19:05:20 -0700710 (unsigned long long)xhci_trb_virt_to_dma(cur_td->start_seg, cur_td->first_trb));
Sarah Sharpe9df17e2010-04-02 15:34:43 -0700711 ep_ring = xhci_urb_to_transfer_ring(xhci, cur_td->urb);
712 if (!ep_ring) {
713 /* This shouldn't happen unless a driver is mucking
714 * with the stream ID after submission. This will
715 * leave the TD on the hardware ring, and the hardware
716 * will try to execute it, and may access a buffer
717 * that has already been freed. In the best case, the
718 * hardware will execute it, and the event handler will
719 * ignore the completion event for that TD, since it was
720 * removed from the td_list for that endpoint. In
721 * short, don't muck with the stream ID after
722 * submission.
723 */
724 xhci_warn(xhci, "WARN Cancelled URB %p "
725 "has invalid stream ID %u.\n",
726 cur_td->urb,
727 cur_td->urb->stream_id);
728 goto remove_finished_td;
729 }
Sarah Sharpae636742009-04-29 19:02:31 -0700730 /*
731 * If we stopped on the TD we need to cancel, then we have to
732 * move the xHC endpoint ring dequeue pointer past this TD.
733 */
Sarah Sharp63a0d9a2009-09-04 10:53:09 -0700734 if (cur_td == ep->stopped_td)
Sarah Sharpe9df17e2010-04-02 15:34:43 -0700735 xhci_find_new_dequeue_state(xhci, slot_id, ep_index,
736 cur_td->urb->stream_id,
737 cur_td, &deq_state);
Sarah Sharpae636742009-04-29 19:02:31 -0700738 else
Sarah Sharp522989a2011-07-29 12:44:32 -0700739 td_to_noop(xhci, ep_ring, cur_td, false);
Sarah Sharpe9df17e2010-04-02 15:34:43 -0700740remove_finished_td:
Sarah Sharpae636742009-04-29 19:02:31 -0700741 /*
742 * The event handler won't see a completion for this TD anymore,
743 * so remove it from the endpoint ring's TD list. Keep it in
744 * the cancelled TD list for URB completion later.
745 */
Sarah Sharp585df1d2011-08-02 15:43:40 -0700746 list_del_init(&cur_td->td_list);
Sarah Sharpae636742009-04-29 19:02:31 -0700747 }
748 last_unlinked_td = cur_td;
Sarah Sharp6f5165c2009-10-27 10:57:01 -0700749 xhci_stop_watchdog_timer_in_irq(xhci, ep);
Sarah Sharpae636742009-04-29 19:02:31 -0700750
751 /* If necessary, queue a Set Transfer Ring Dequeue Pointer command */
752 if (deq_state.new_deq_ptr && deq_state.new_deq_seg) {
Sarah Sharp63a0d9a2009-09-04 10:53:09 -0700753 xhci_queue_new_dequeue_state(xhci,
Sarah Sharpe9df17e2010-04-02 15:34:43 -0700754 slot_id, ep_index,
755 ep->stopped_td->urb->stream_id,
756 &deq_state);
Sarah Sharpac9d8fe2009-08-07 14:04:55 -0700757 xhci_ring_cmd_db(xhci);
Sarah Sharpae636742009-04-29 19:02:31 -0700758 } else {
Sarah Sharpe9df17e2010-04-02 15:34:43 -0700759 /* Otherwise ring the doorbell(s) to restart queued transfers */
760 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
Sarah Sharpae636742009-04-29 19:02:31 -0700761 }
Sarah Sharp1624ae12010-05-06 13:40:08 -0700762 ep->stopped_td = NULL;
763 ep->stopped_trb = NULL;
Sarah Sharpae636742009-04-29 19:02:31 -0700764
765 /*
766 * Drop the lock and complete the URBs in the cancelled TD list.
767 * New TDs to be cancelled might be added to the end of the list before
768 * we can complete all the URBs for the TDs we already unlinked.
769 * So stop when we've completed the URB for the last TD we unlinked.
770 */
771 do {
Sarah Sharp63a0d9a2009-09-04 10:53:09 -0700772 cur_td = list_entry(ep->cancelled_td_list.next,
Sarah Sharpae636742009-04-29 19:02:31 -0700773 struct xhci_td, cancelled_td_list);
Sarah Sharp585df1d2011-08-02 15:43:40 -0700774 list_del_init(&cur_td->cancelled_td_list);
Sarah Sharpae636742009-04-29 19:02:31 -0700775
776 /* Clean up the cancelled URB */
Sarah Sharpae636742009-04-29 19:02:31 -0700777 /* Doesn't matter what we pass for status, since the core will
778 * just overwrite it (because the URB has been unlinked).
779 */
Sarah Sharp6f5165c2009-10-27 10:57:01 -0700780 xhci_giveback_urb_in_irq(xhci, cur_td, 0, "cancelled");
Sarah Sharpae636742009-04-29 19:02:31 -0700781
Sarah Sharp6f5165c2009-10-27 10:57:01 -0700782 /* Stop processing the cancelled list if the watchdog timer is
783 * running.
784 */
785 if (xhci->xhc_state & XHCI_STATE_DYING)
786 return;
Sarah Sharpae636742009-04-29 19:02:31 -0700787 } while (cur_td != last_unlinked_td);
788
789 /* Return to the event handler with xhci->lock re-acquired */
790}
791
Sarah Sharp6f5165c2009-10-27 10:57:01 -0700792/* Watchdog timer function for when a stop endpoint command fails to complete.
793 * In this case, we assume the host controller is broken or dying or dead. The
794 * host may still be completing some other events, so we have to be careful to
795 * let the event ring handler and the URB dequeueing/enqueueing functions know
796 * through xhci->state.
797 *
798 * The timer may also fire if the host takes a very long time to respond to the
799 * command, and the stop endpoint command completion handler cannot delete the
800 * timer before the timer function is called. Another endpoint cancellation may
801 * sneak in before the timer function can grab the lock, and that may queue
802 * another stop endpoint command and add the timer back. So we cannot use a
803 * simple flag to say whether there is a pending stop endpoint command for a
804 * particular endpoint.
805 *
806 * Instead we use a combination of that flag and a counter for the number of
807 * pending stop endpoint commands. If the timer is the tail end of the last
808 * stop endpoint command, and the endpoint's command is still pending, we assume
809 * the host is dying.
810 */
811void xhci_stop_endpoint_command_watchdog(unsigned long arg)
812{
813 struct xhci_hcd *xhci;
814 struct xhci_virt_ep *ep;
815 struct xhci_virt_ep *temp_ep;
816 struct xhci_ring *ring;
817 struct xhci_td *cur_td;
818 int ret, i, j;
819
820 ep = (struct xhci_virt_ep *) arg;
821 xhci = ep->xhci;
822
823 spin_lock(&xhci->lock);
824
825 ep->stop_cmds_pending--;
826 if (xhci->xhc_state & XHCI_STATE_DYING) {
827 xhci_dbg(xhci, "Stop EP timer ran, but another timer marked "
828 "xHCI as DYING, exiting.\n");
829 spin_unlock(&xhci->lock);
830 return;
831 }
832 if (!(ep->stop_cmds_pending == 0 && (ep->ep_state & EP_HALT_PENDING))) {
833 xhci_dbg(xhci, "Stop EP timer ran, but no command pending, "
834 "exiting.\n");
835 spin_unlock(&xhci->lock);
836 return;
837 }
838
839 xhci_warn(xhci, "xHCI host not responding to stop endpoint command.\n");
840 xhci_warn(xhci, "Assuming host is dying, halting host.\n");
841 /* Oops, HC is dead or dying or at least not responding to the stop
842 * endpoint command.
843 */
844 xhci->xhc_state |= XHCI_STATE_DYING;
845 /* Disable interrupts from the host controller and start halting it */
846 xhci_quiesce(xhci);
847 spin_unlock(&xhci->lock);
848
849 ret = xhci_halt(xhci);
850
851 spin_lock(&xhci->lock);
852 if (ret < 0) {
853 /* This is bad; the host is not responding to commands and it's
854 * not allowing itself to be halted. At least interrupts are
Sarah Sharpac04e6f2011-03-11 08:47:33 -0800855 * disabled. If we call usb_hc_died(), it will attempt to
Sarah Sharp6f5165c2009-10-27 10:57:01 -0700856 * disconnect all device drivers under this host. Those
857 * disconnect() methods will wait for all URBs to be unlinked,
858 * so we must complete them.
859 */
860 xhci_warn(xhci, "Non-responsive xHCI host is not halting.\n");
861 xhci_warn(xhci, "Completing active URBs anyway.\n");
862 /* We could turn all TDs on the rings to no-ops. This won't
863 * help if the host has cached part of the ring, and is slow if
864 * we want to preserve the cycle bit. Skip it and hope the host
865 * doesn't touch the memory.
866 */
867 }
868 for (i = 0; i < MAX_HC_SLOTS; i++) {
869 if (!xhci->devs[i])
870 continue;
871 for (j = 0; j < 31; j++) {
872 temp_ep = &xhci->devs[i]->eps[j];
873 ring = temp_ep->ring;
874 if (!ring)
875 continue;
876 xhci_dbg(xhci, "Killing URBs for slot ID %u, "
877 "ep index %u\n", i, j);
878 while (!list_empty(&ring->td_list)) {
879 cur_td = list_first_entry(&ring->td_list,
880 struct xhci_td,
881 td_list);
Sarah Sharp585df1d2011-08-02 15:43:40 -0700882 list_del_init(&cur_td->td_list);
Sarah Sharp6f5165c2009-10-27 10:57:01 -0700883 if (!list_empty(&cur_td->cancelled_td_list))
Sarah Sharp585df1d2011-08-02 15:43:40 -0700884 list_del_init(&cur_td->cancelled_td_list);
Sarah Sharp6f5165c2009-10-27 10:57:01 -0700885 xhci_giveback_urb_in_irq(xhci, cur_td,
886 -ESHUTDOWN, "killed");
887 }
888 while (!list_empty(&temp_ep->cancelled_td_list)) {
889 cur_td = list_first_entry(
890 &temp_ep->cancelled_td_list,
891 struct xhci_td,
892 cancelled_td_list);
Sarah Sharp585df1d2011-08-02 15:43:40 -0700893 list_del_init(&cur_td->cancelled_td_list);
Sarah Sharp6f5165c2009-10-27 10:57:01 -0700894 xhci_giveback_urb_in_irq(xhci, cur_td,
895 -ESHUTDOWN, "killed");
896 }
897 }
898 }
899 spin_unlock(&xhci->lock);
Sarah Sharp6f5165c2009-10-27 10:57:01 -0700900 xhci_dbg(xhci, "Calling usb_hc_died()\n");
Sarah Sharpf6ff0ac2010-12-16 11:21:10 -0800901 usb_hc_died(xhci_to_hcd(xhci)->primary_hcd);
Sarah Sharp6f5165c2009-10-27 10:57:01 -0700902 xhci_dbg(xhci, "xHCI host controller is dead.\n");
903}
904
Sarah Sharpae636742009-04-29 19:02:31 -0700905/*
906 * When we get a completion for a Set Transfer Ring Dequeue Pointer command,
907 * we need to clear the set deq pending flag in the endpoint ring state, so that
908 * the TD queueing code can ring the doorbell again. We also need to ring the
909 * endpoint doorbell to restart the ring, but only if there aren't more
910 * cancellations pending.
911 */
912static void handle_set_deq_completion(struct xhci_hcd *xhci,
913 struct xhci_event_cmd *event,
914 union xhci_trb *trb)
915{
916 unsigned int slot_id;
917 unsigned int ep_index;
Sarah Sharpe9df17e2010-04-02 15:34:43 -0700918 unsigned int stream_id;
Sarah Sharpae636742009-04-29 19:02:31 -0700919 struct xhci_ring *ep_ring;
920 struct xhci_virt_device *dev;
John Yound115b042009-07-27 12:05:15 -0700921 struct xhci_ep_ctx *ep_ctx;
922 struct xhci_slot_ctx *slot_ctx;
Sarah Sharpae636742009-04-29 19:02:31 -0700923
Matt Evans28ccd292011-03-29 13:40:46 +1100924 slot_id = TRB_TO_SLOT_ID(le32_to_cpu(trb->generic.field[3]));
925 ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3]));
926 stream_id = TRB_TO_STREAM_ID(le32_to_cpu(trb->generic.field[2]));
Sarah Sharpae636742009-04-29 19:02:31 -0700927 dev = xhci->devs[slot_id];
Sarah Sharpe9df17e2010-04-02 15:34:43 -0700928
929 ep_ring = xhci_stream_id_to_ring(dev, ep_index, stream_id);
930 if (!ep_ring) {
931 xhci_warn(xhci, "WARN Set TR deq ptr command for "
932 "freed stream ID %u\n",
933 stream_id);
934 /* XXX: Harmless??? */
935 dev->eps[ep_index].ep_state &= ~SET_DEQ_PENDING;
936 return;
937 }
938
John Yound115b042009-07-27 12:05:15 -0700939 ep_ctx = xhci_get_ep_ctx(xhci, dev->out_ctx, ep_index);
940 slot_ctx = xhci_get_slot_ctx(xhci, dev->out_ctx);
Sarah Sharpae636742009-04-29 19:02:31 -0700941
Matt Evans28ccd292011-03-29 13:40:46 +1100942 if (GET_COMP_CODE(le32_to_cpu(event->status)) != COMP_SUCCESS) {
Sarah Sharpae636742009-04-29 19:02:31 -0700943 unsigned int ep_state;
944 unsigned int slot_state;
945
Matt Evans28ccd292011-03-29 13:40:46 +1100946 switch (GET_COMP_CODE(le32_to_cpu(event->status))) {
Sarah Sharpae636742009-04-29 19:02:31 -0700947 case COMP_TRB_ERR:
948 xhci_warn(xhci, "WARN Set TR Deq Ptr cmd invalid because "
949 "of stream ID configuration\n");
950 break;
951 case COMP_CTX_STATE:
952 xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed due "
953 "to incorrect slot or ep state.\n");
Matt Evans28ccd292011-03-29 13:40:46 +1100954 ep_state = le32_to_cpu(ep_ctx->ep_info);
Sarah Sharpae636742009-04-29 19:02:31 -0700955 ep_state &= EP_STATE_MASK;
Matt Evans28ccd292011-03-29 13:40:46 +1100956 slot_state = le32_to_cpu(slot_ctx->dev_state);
Sarah Sharpae636742009-04-29 19:02:31 -0700957 slot_state = GET_SLOT_STATE(slot_state);
958 xhci_dbg(xhci, "Slot state = %u, EP state = %u\n",
959 slot_state, ep_state);
960 break;
961 case COMP_EBADSLT:
962 xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed because "
963 "slot %u was not enabled.\n", slot_id);
964 break;
965 default:
966 xhci_warn(xhci, "WARN Set TR Deq Ptr cmd with unknown "
967 "completion code of %u.\n",
Matt Evans28ccd292011-03-29 13:40:46 +1100968 GET_COMP_CODE(le32_to_cpu(event->status)));
Sarah Sharpae636742009-04-29 19:02:31 -0700969 break;
970 }
971 /* OK what do we do now? The endpoint state is hosed, and we
972 * should never get to this point if the synchronization between
973 * queueing, and endpoint state are correct. This might happen
974 * if the device gets disconnected after we've finished
975 * cancelling URBs, which might not be an error...
976 */
977 } else {
Sarah Sharp8e595a52009-07-27 12:03:31 -0700978 xhci_dbg(xhci, "Successful Set TR Deq Ptr cmd, deq = @%08llx\n",
Matt Evans28ccd292011-03-29 13:40:46 +1100979 le64_to_cpu(ep_ctx->deq));
Sarah Sharpbf161e82011-02-23 15:46:42 -0800980 if (xhci_trb_virt_to_dma(dev->eps[ep_index].queued_deq_seg,
Matt Evans28ccd292011-03-29 13:40:46 +1100981 dev->eps[ep_index].queued_deq_ptr) ==
982 (le64_to_cpu(ep_ctx->deq) & ~(EP_CTX_CYCLE_MASK))) {
Sarah Sharpbf161e82011-02-23 15:46:42 -0800983 /* Update the ring's dequeue segment and dequeue pointer
984 * to reflect the new position.
985 */
986 ep_ring->deq_seg = dev->eps[ep_index].queued_deq_seg;
987 ep_ring->dequeue = dev->eps[ep_index].queued_deq_ptr;
988 } else {
989 xhci_warn(xhci, "Mismatch between completed Set TR Deq "
990 "Ptr command & xHCI internal state.\n");
991 xhci_warn(xhci, "ep deq seg = %p, deq ptr = %p\n",
992 dev->eps[ep_index].queued_deq_seg,
993 dev->eps[ep_index].queued_deq_ptr);
994 }
Sarah Sharpae636742009-04-29 19:02:31 -0700995 }
996
Sarah Sharp63a0d9a2009-09-04 10:53:09 -0700997 dev->eps[ep_index].ep_state &= ~SET_DEQ_PENDING;
Sarah Sharpbf161e82011-02-23 15:46:42 -0800998 dev->eps[ep_index].queued_deq_seg = NULL;
999 dev->eps[ep_index].queued_deq_ptr = NULL;
Sarah Sharpe9df17e2010-04-02 15:34:43 -07001000 /* Restart any rings with pending URBs */
1001 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
Sarah Sharpae636742009-04-29 19:02:31 -07001002}
1003
Sarah Sharpa1587d92009-07-27 12:03:15 -07001004static void handle_reset_ep_completion(struct xhci_hcd *xhci,
1005 struct xhci_event_cmd *event,
1006 union xhci_trb *trb)
1007{
1008 int slot_id;
1009 unsigned int ep_index;
1010
Matt Evans28ccd292011-03-29 13:40:46 +11001011 slot_id = TRB_TO_SLOT_ID(le32_to_cpu(trb->generic.field[3]));
1012 ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3]));
Sarah Sharpa1587d92009-07-27 12:03:15 -07001013 /* This command will only fail if the endpoint wasn't halted,
1014 * but we don't care.
1015 */
1016 xhci_dbg(xhci, "Ignoring reset ep completion code of %u\n",
Matt Evansf5960b62011-06-01 10:22:55 +10001017 GET_COMP_CODE(le32_to_cpu(event->status)));
Sarah Sharpa1587d92009-07-27 12:03:15 -07001018
Sarah Sharpac9d8fe2009-08-07 14:04:55 -07001019 /* HW with the reset endpoint quirk needs to have a configure endpoint
1020 * command complete before the endpoint can be used. Queue that here
1021 * because the HW can't handle two commands being queued in a row.
1022 */
1023 if (xhci->quirks & XHCI_RESET_EP_QUIRK) {
1024 xhci_dbg(xhci, "Queueing configure endpoint command\n");
1025 xhci_queue_configure_endpoint(xhci,
Sarah Sharp913a8a32009-09-04 10:53:13 -07001026 xhci->devs[slot_id]->in_ctx->dma, slot_id,
1027 false);
Sarah Sharpac9d8fe2009-08-07 14:04:55 -07001028 xhci_ring_cmd_db(xhci);
1029 } else {
Sarah Sharpe9df17e2010-04-02 15:34:43 -07001030 /* Clear our internal halted state and restart the ring(s) */
Sarah Sharp63a0d9a2009-09-04 10:53:09 -07001031 xhci->devs[slot_id]->eps[ep_index].ep_state &= ~EP_HALTED;
Sarah Sharpe9df17e2010-04-02 15:34:43 -07001032 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
Sarah Sharpac9d8fe2009-08-07 14:04:55 -07001033 }
Sarah Sharpa1587d92009-07-27 12:03:15 -07001034}
Sarah Sharpae636742009-04-29 19:02:31 -07001035
Sarah Sharpa50c8aa2009-09-04 10:53:15 -07001036/* Check to see if a command in the device's command queue matches this one.
1037 * Signal the completion or free the command, and return 1. Return 0 if the
1038 * completed command isn't at the head of the command list.
1039 */
1040static int handle_cmd_in_cmd_wait_list(struct xhci_hcd *xhci,
1041 struct xhci_virt_device *virt_dev,
1042 struct xhci_event_cmd *event)
1043{
1044 struct xhci_command *command;
1045
1046 if (list_empty(&virt_dev->cmd_list))
1047 return 0;
1048
1049 command = list_entry(virt_dev->cmd_list.next,
1050 struct xhci_command, cmd_list);
1051 if (xhci->cmd_ring->dequeue != command->command_trb)
1052 return 0;
1053
Matt Evans28ccd292011-03-29 13:40:46 +11001054 command->status = GET_COMP_CODE(le32_to_cpu(event->status));
Sarah Sharpa50c8aa2009-09-04 10:53:15 -07001055 list_del(&command->cmd_list);
1056 if (command->completion)
1057 complete(command->completion);
1058 else
1059 xhci_free_command(xhci, command);
1060 return 1;
1061}
1062
Sarah Sharp7f84eef2009-04-27 19:53:56 -07001063static void handle_cmd_completion(struct xhci_hcd *xhci,
1064 struct xhci_event_cmd *event)
1065{
Matt Evans28ccd292011-03-29 13:40:46 +11001066 int slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
Sarah Sharp7f84eef2009-04-27 19:53:56 -07001067 u64 cmd_dma;
1068 dma_addr_t cmd_dequeue_dma;
Sarah Sharpac9d8fe2009-08-07 14:04:55 -07001069 struct xhci_input_control_ctx *ctrl_ctx;
Sarah Sharp913a8a32009-09-04 10:53:13 -07001070 struct xhci_virt_device *virt_dev;
Sarah Sharpac9d8fe2009-08-07 14:04:55 -07001071 unsigned int ep_index;
1072 struct xhci_ring *ep_ring;
1073 unsigned int ep_state;
Sarah Sharp7f84eef2009-04-27 19:53:56 -07001074
Matt Evans28ccd292011-03-29 13:40:46 +11001075 cmd_dma = le64_to_cpu(event->cmd_trb);
Sarah Sharp23e3be12009-04-29 19:05:20 -07001076 cmd_dequeue_dma = xhci_trb_virt_to_dma(xhci->cmd_ring->deq_seg,
Sarah Sharp7f84eef2009-04-27 19:53:56 -07001077 xhci->cmd_ring->dequeue);
1078 /* Is the command ring deq ptr out of sync with the deq seg ptr? */
1079 if (cmd_dequeue_dma == 0) {
1080 xhci->error_bitmask |= 1 << 4;
1081 return;
1082 }
1083 /* Does the DMA address match our internal dequeue pointer address? */
1084 if (cmd_dma != (u64) cmd_dequeue_dma) {
1085 xhci->error_bitmask |= 1 << 5;
1086 return;
1087 }
Matt Evans28ccd292011-03-29 13:40:46 +11001088 switch (le32_to_cpu(xhci->cmd_ring->dequeue->generic.field[3])
1089 & TRB_TYPE_BITMASK) {
Sarah Sharp3ffbba92009-04-27 19:57:38 -07001090 case TRB_TYPE(TRB_ENABLE_SLOT):
Matt Evans28ccd292011-03-29 13:40:46 +11001091 if (GET_COMP_CODE(le32_to_cpu(event->status)) == COMP_SUCCESS)
Sarah Sharp3ffbba92009-04-27 19:57:38 -07001092 xhci->slot_id = slot_id;
1093 else
1094 xhci->slot_id = 0;
1095 complete(&xhci->addr_dev);
1096 break;
1097 case TRB_TYPE(TRB_DISABLE_SLOT):
Sarah Sharp2cf95c12011-05-11 16:14:58 -07001098 if (xhci->devs[slot_id]) {
1099 if (xhci->quirks & XHCI_EP_LIMIT_QUIRK)
1100 /* Delete default control endpoint resources */
1101 xhci_free_device_endpoint_resources(xhci,
1102 xhci->devs[slot_id], true);
Sarah Sharp3ffbba92009-04-27 19:57:38 -07001103 xhci_free_virt_device(xhci, slot_id);
Sarah Sharp2cf95c12011-05-11 16:14:58 -07001104 }
Sarah Sharp3ffbba92009-04-27 19:57:38 -07001105 break;
Sarah Sharpf94e01862009-04-27 19:58:38 -07001106 case TRB_TYPE(TRB_CONFIG_EP):
Sarah Sharp913a8a32009-09-04 10:53:13 -07001107 virt_dev = xhci->devs[slot_id];
Sarah Sharpa50c8aa2009-09-04 10:53:15 -07001108 if (handle_cmd_in_cmd_wait_list(xhci, virt_dev, event))
Sarah Sharp913a8a32009-09-04 10:53:13 -07001109 break;
Sarah Sharpac9d8fe2009-08-07 14:04:55 -07001110 /*
1111 * Configure endpoint commands can come from the USB core
1112 * configuration or alt setting changes, or because the HW
1113 * needed an extra configure endpoint command after a reset
Sarah Sharp8df75f42010-04-02 15:34:16 -07001114 * endpoint command or streams were being configured.
1115 * If the command was for a halted endpoint, the xHCI driver
1116 * is not waiting on the configure endpoint command.
Sarah Sharpac9d8fe2009-08-07 14:04:55 -07001117 */
1118 ctrl_ctx = xhci_get_input_control_ctx(xhci,
Sarah Sharp913a8a32009-09-04 10:53:13 -07001119 virt_dev->in_ctx);
Sarah Sharpac9d8fe2009-08-07 14:04:55 -07001120 /* Input ctx add_flags are the endpoint index plus one */
Matt Evans28ccd292011-03-29 13:40:46 +11001121 ep_index = xhci_last_valid_endpoint(le32_to_cpu(ctrl_ctx->add_flags)) - 1;
Sarah Sharp06df5722009-12-03 09:44:31 -08001122 /* A usb_set_interface() call directly after clearing a halted
Sarah Sharpe9df17e2010-04-02 15:34:43 -07001123 * condition may race on this quirky hardware. Not worth
1124 * worrying about, since this is prototype hardware. Not sure
1125 * if this will work for streams, but streams support was
1126 * untested on this prototype.
Sarah Sharp06df5722009-12-03 09:44:31 -08001127 */
Sarah Sharpac9d8fe2009-08-07 14:04:55 -07001128 if (xhci->quirks & XHCI_RESET_EP_QUIRK &&
Sarah Sharp06df5722009-12-03 09:44:31 -08001129 ep_index != (unsigned int) -1 &&
Matt Evans28ccd292011-03-29 13:40:46 +11001130 le32_to_cpu(ctrl_ctx->add_flags) - SLOT_FLAG ==
1131 le32_to_cpu(ctrl_ctx->drop_flags)) {
Sarah Sharp06df5722009-12-03 09:44:31 -08001132 ep_ring = xhci->devs[slot_id]->eps[ep_index].ring;
1133 ep_state = xhci->devs[slot_id]->eps[ep_index].ep_state;
1134 if (!(ep_state & EP_HALTED))
1135 goto bandwidth_change;
1136 xhci_dbg(xhci, "Completed config ep cmd - "
1137 "last ep index = %d, state = %d\n",
1138 ep_index, ep_state);
Sarah Sharpe9df17e2010-04-02 15:34:43 -07001139 /* Clear internal halted state and restart ring(s) */
Sarah Sharp63a0d9a2009-09-04 10:53:09 -07001140 xhci->devs[slot_id]->eps[ep_index].ep_state &=
Sarah Sharpac9d8fe2009-08-07 14:04:55 -07001141 ~EP_HALTED;
Sarah Sharpe9df17e2010-04-02 15:34:43 -07001142 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
Sarah Sharp06df5722009-12-03 09:44:31 -08001143 break;
Sarah Sharpac9d8fe2009-08-07 14:04:55 -07001144 }
Sarah Sharp06df5722009-12-03 09:44:31 -08001145bandwidth_change:
1146 xhci_dbg(xhci, "Completed config ep cmd\n");
1147 xhci->devs[slot_id]->cmd_status =
Matt Evans28ccd292011-03-29 13:40:46 +11001148 GET_COMP_CODE(le32_to_cpu(event->status));
Sarah Sharp06df5722009-12-03 09:44:31 -08001149 complete(&xhci->devs[slot_id]->cmd_completion);
Sarah Sharpf94e01862009-04-27 19:58:38 -07001150 break;
Sarah Sharp2d3f1fa2009-08-07 14:04:49 -07001151 case TRB_TYPE(TRB_EVAL_CONTEXT):
Sarah Sharpac1c1b72009-09-04 10:53:20 -07001152 virt_dev = xhci->devs[slot_id];
1153 if (handle_cmd_in_cmd_wait_list(xhci, virt_dev, event))
1154 break;
Matt Evans28ccd292011-03-29 13:40:46 +11001155 xhci->devs[slot_id]->cmd_status = GET_COMP_CODE(le32_to_cpu(event->status));
Sarah Sharp2d3f1fa2009-08-07 14:04:49 -07001156 complete(&xhci->devs[slot_id]->cmd_completion);
1157 break;
Sarah Sharp3ffbba92009-04-27 19:57:38 -07001158 case TRB_TYPE(TRB_ADDR_DEV):
Matt Evans28ccd292011-03-29 13:40:46 +11001159 xhci->devs[slot_id]->cmd_status = GET_COMP_CODE(le32_to_cpu(event->status));
Sarah Sharp3ffbba92009-04-27 19:57:38 -07001160 complete(&xhci->addr_dev);
1161 break;
Sarah Sharpae636742009-04-29 19:02:31 -07001162 case TRB_TYPE(TRB_STOP_RING):
Andiry Xube88fe42010-10-14 07:22:57 -07001163 handle_stopped_endpoint(xhci, xhci->cmd_ring->dequeue, event);
Sarah Sharpae636742009-04-29 19:02:31 -07001164 break;
1165 case TRB_TYPE(TRB_SET_DEQ):
1166 handle_set_deq_completion(xhci, event, xhci->cmd_ring->dequeue);
1167 break;
Sarah Sharp7f84eef2009-04-27 19:53:56 -07001168 case TRB_TYPE(TRB_CMD_NOOP):
Sarah Sharp7f84eef2009-04-27 19:53:56 -07001169 break;
Sarah Sharpa1587d92009-07-27 12:03:15 -07001170 case TRB_TYPE(TRB_RESET_EP):
1171 handle_reset_ep_completion(xhci, event, xhci->cmd_ring->dequeue);
1172 break;
Sarah Sharp2a8f82c2009-12-09 15:59:13 -08001173 case TRB_TYPE(TRB_RESET_DEV):
1174 xhci_dbg(xhci, "Completed reset device command.\n");
1175 slot_id = TRB_TO_SLOT_ID(
Matt Evans28ccd292011-03-29 13:40:46 +11001176 le32_to_cpu(xhci->cmd_ring->dequeue->generic.field[3]));
Sarah Sharp2a8f82c2009-12-09 15:59:13 -08001177 virt_dev = xhci->devs[slot_id];
1178 if (virt_dev)
1179 handle_cmd_in_cmd_wait_list(xhci, virt_dev, event);
1180 else
1181 xhci_warn(xhci, "Reset device command completion "
1182 "for disabled slot %u\n", slot_id);
1183 break;
Sarah Sharp02386342010-05-24 13:25:28 -07001184 case TRB_TYPE(TRB_NEC_GET_FW):
1185 if (!(xhci->quirks & XHCI_NEC_HOST)) {
1186 xhci->error_bitmask |= 1 << 6;
1187 break;
1188 }
1189 xhci_dbg(xhci, "NEC firmware version %2x.%02x\n",
Matt Evans28ccd292011-03-29 13:40:46 +11001190 NEC_FW_MAJOR(le32_to_cpu(event->status)),
1191 NEC_FW_MINOR(le32_to_cpu(event->status)));
Sarah Sharp02386342010-05-24 13:25:28 -07001192 break;
Sarah Sharp7f84eef2009-04-27 19:53:56 -07001193 default:
1194 /* Skip over unknown commands on the event ring */
1195 xhci->error_bitmask |= 1 << 6;
1196 break;
1197 }
1198 inc_deq(xhci, xhci->cmd_ring, false);
1199}
1200
Sarah Sharp02386342010-05-24 13:25:28 -07001201static void handle_vendor_event(struct xhci_hcd *xhci,
1202 union xhci_trb *event)
1203{
1204 u32 trb_type;
1205
Matt Evans28ccd292011-03-29 13:40:46 +11001206 trb_type = TRB_FIELD_TO_TYPE(le32_to_cpu(event->generic.field[3]));
Sarah Sharp02386342010-05-24 13:25:28 -07001207 xhci_dbg(xhci, "Vendor specific event TRB type = %u\n", trb_type);
1208 if (trb_type == TRB_NEC_CMD_COMP && (xhci->quirks & XHCI_NEC_HOST))
1209 handle_cmd_completion(xhci, &event->event_cmd);
1210}
1211
Sarah Sharpf6ff0ac2010-12-16 11:21:10 -08001212/* @port_id: the one-based port ID from the hardware (indexed from array of all
1213 * port registers -- USB 3.0 and USB 2.0).
1214 *
1215 * Returns a zero-based port number, which is suitable for indexing into each of
1216 * the split roothubs' port arrays and bus state arrays.
1217 */
1218static unsigned int find_faked_portnum_from_hw_portnum(struct usb_hcd *hcd,
1219 struct xhci_hcd *xhci, u32 port_id)
1220{
1221 unsigned int i;
1222 unsigned int num_similar_speed_ports = 0;
1223
1224 /* port_id from the hardware is 1-based, but port_array[], usb3_ports[],
1225 * and usb2_ports are 0-based indexes. Count the number of similar
1226 * speed ports, up to 1 port before this port.
1227 */
1228 for (i = 0; i < (port_id - 1); i++) {
1229 u8 port_speed = xhci->port_array[i];
1230
1231 /*
1232 * Skip ports that don't have known speeds, or have duplicate
1233 * Extended Capabilities port speed entries.
1234 */
Dan Carpenter22e04872011-03-17 22:39:49 +03001235 if (port_speed == 0 || port_speed == DUPLICATE_ENTRY)
Sarah Sharpf6ff0ac2010-12-16 11:21:10 -08001236 continue;
1237
1238 /*
1239 * USB 3.0 ports are always under a USB 3.0 hub. USB 2.0 and
1240 * 1.1 ports are under the USB 2.0 hub. If the port speed
1241 * matches the device speed, it's a similar speed port.
1242 */
1243 if ((port_speed == 0x03) == (hcd->speed == HCD_USB3))
1244 num_similar_speed_ports++;
1245 }
1246 return num_similar_speed_ports;
1247}
1248
Sarah Sharp0f2a7932009-04-27 19:57:12 -07001249static void handle_port_status(struct xhci_hcd *xhci,
1250 union xhci_trb *event)
1251{
Sarah Sharpf6ff0ac2010-12-16 11:21:10 -08001252 struct usb_hcd *hcd;
Sarah Sharp0f2a7932009-04-27 19:57:12 -07001253 u32 port_id;
Andiry Xu56192532010-10-14 07:23:00 -07001254 u32 temp, temp1;
Sarah Sharp518e8482010-12-15 11:56:29 -08001255 int max_ports;
Andiry Xu56192532010-10-14 07:23:00 -07001256 int slot_id;
Sarah Sharp5308a912010-12-01 11:34:59 -08001257 unsigned int faked_port_index;
Sarah Sharpf6ff0ac2010-12-16 11:21:10 -08001258 u8 major_revision;
Sarah Sharp20b67cf2010-12-15 12:47:14 -08001259 struct xhci_bus_state *bus_state;
Matt Evans28ccd292011-03-29 13:40:46 +11001260 __le32 __iomem **port_array;
Sarah Sharp386139d2011-03-24 08:02:58 -07001261 bool bogus_port_status = false;
Sarah Sharp0f2a7932009-04-27 19:57:12 -07001262
1263 /* Port status change events always have a successful completion code */
Matt Evans28ccd292011-03-29 13:40:46 +11001264 if (GET_COMP_CODE(le32_to_cpu(event->generic.field[2])) != COMP_SUCCESS) {
Sarah Sharp0f2a7932009-04-27 19:57:12 -07001265 xhci_warn(xhci, "WARN: xHC returned failed port status event\n");
1266 xhci->error_bitmask |= 1 << 8;
1267 }
Matt Evans28ccd292011-03-29 13:40:46 +11001268 port_id = GET_PORT_ID(le32_to_cpu(event->generic.field[0]));
Sarah Sharp0f2a7932009-04-27 19:57:12 -07001269 xhci_dbg(xhci, "Port Status Change Event for port %d\n", port_id);
1270
Sarah Sharp518e8482010-12-15 11:56:29 -08001271 max_ports = HCS_MAX_PORTS(xhci->hcs_params1);
1272 if ((port_id <= 0) || (port_id > max_ports)) {
Andiry Xu56192532010-10-14 07:23:00 -07001273 xhci_warn(xhci, "Invalid port id %d\n", port_id);
Sarah Sharp386139d2011-03-24 08:02:58 -07001274 bogus_port_status = true;
Andiry Xu56192532010-10-14 07:23:00 -07001275 goto cleanup;
1276 }
1277
Sarah Sharpf6ff0ac2010-12-16 11:21:10 -08001278 /* Figure out which usb_hcd this port is attached to:
1279 * is it a USB 3.0 port or a USB 2.0/1.1 port?
1280 */
1281 major_revision = xhci->port_array[port_id - 1];
1282 if (major_revision == 0) {
1283 xhci_warn(xhci, "Event for port %u not in "
1284 "Extended Capabilities, ignoring.\n",
1285 port_id);
Sarah Sharp386139d2011-03-24 08:02:58 -07001286 bogus_port_status = true;
Sarah Sharpf6ff0ac2010-12-16 11:21:10 -08001287 goto cleanup;
1288 }
Dan Carpenter22e04872011-03-17 22:39:49 +03001289 if (major_revision == DUPLICATE_ENTRY) {
Sarah Sharpf6ff0ac2010-12-16 11:21:10 -08001290 xhci_warn(xhci, "Event for port %u duplicated in"
1291 "Extended Capabilities, ignoring.\n",
1292 port_id);
Sarah Sharp386139d2011-03-24 08:02:58 -07001293 bogus_port_status = true;
Sarah Sharpf6ff0ac2010-12-16 11:21:10 -08001294 goto cleanup;
Sarah Sharp5308a912010-12-01 11:34:59 -08001295 }
1296
Sarah Sharpf6ff0ac2010-12-16 11:21:10 -08001297 /*
1298 * Hardware port IDs reported by a Port Status Change Event include USB
1299 * 3.0 and USB 2.0 ports. We want to check if the port has reported a
1300 * resume event, but we first need to translate the hardware port ID
1301 * into the index into the ports on the correct split roothub, and the
1302 * correct bus_state structure.
1303 */
1304 /* Find the right roothub. */
1305 hcd = xhci_to_hcd(xhci);
1306 if ((major_revision == 0x03) != (hcd->speed == HCD_USB3))
1307 hcd = xhci->shared_hcd;
1308 bus_state = &xhci->bus_state[hcd_index(hcd)];
1309 if (hcd->speed == HCD_USB3)
1310 port_array = xhci->usb3_ports;
1311 else
1312 port_array = xhci->usb2_ports;
1313 /* Find the faked port hub number */
1314 faked_port_index = find_faked_portnum_from_hw_portnum(hcd, xhci,
1315 port_id);
1316
Sarah Sharp5308a912010-12-01 11:34:59 -08001317 temp = xhci_readl(xhci, port_array[faked_port_index]);
Sarah Sharp7111ebc2010-12-14 13:24:55 -08001318 if (hcd->state == HC_STATE_SUSPENDED) {
Andiry Xu56192532010-10-14 07:23:00 -07001319 xhci_dbg(xhci, "resume root hub\n");
1320 usb_hcd_resume_root_hub(hcd);
1321 }
1322
1323 if ((temp & PORT_PLC) && (temp & PORT_PLS_MASK) == XDEV_RESUME) {
1324 xhci_dbg(xhci, "port resume event for port %d\n", port_id);
1325
1326 temp1 = xhci_readl(xhci, &xhci->op_regs->command);
1327 if (!(temp1 & CMD_RUN)) {
1328 xhci_warn(xhci, "xHC is not running.\n");
1329 goto cleanup;
1330 }
1331
1332 if (DEV_SUPERSPEED(temp)) {
1333 xhci_dbg(xhci, "resume SS port %d\n", port_id);
Andiry Xuc9682df2011-09-23 14:19:48 -07001334 xhci_set_link_state(xhci, port_array, faked_port_index,
1335 XDEV_U0);
Sarah Sharp52336302010-12-16 10:49:09 -08001336 slot_id = xhci_find_slot_id_by_port(hcd, xhci,
1337 faked_port_index);
Andiry Xu56192532010-10-14 07:23:00 -07001338 if (!slot_id) {
1339 xhci_dbg(xhci, "slot_id is zero\n");
1340 goto cleanup;
1341 }
1342 xhci_ring_device(xhci, slot_id);
1343 xhci_dbg(xhci, "resume SS port %d finished\n", port_id);
1344 /* Clear PORT_PLC */
Andiry Xud2f52c92011-09-23 14:19:49 -07001345 xhci_test_and_clear_bit(xhci, port_array,
1346 faked_port_index, PORT_PLC);
Andiry Xu56192532010-10-14 07:23:00 -07001347 } else {
1348 xhci_dbg(xhci, "resume HS port %d\n", port_id);
Sarah Sharpf6ff0ac2010-12-16 11:21:10 -08001349 bus_state->resume_done[faked_port_index] = jiffies +
Andiry Xu56192532010-10-14 07:23:00 -07001350 msecs_to_jiffies(20);
1351 mod_timer(&hcd->rh_timer,
Sarah Sharpf6ff0ac2010-12-16 11:21:10 -08001352 bus_state->resume_done[faked_port_index]);
Andiry Xu56192532010-10-14 07:23:00 -07001353 /* Do the rest in GetPortStatus */
1354 }
1355 }
1356
Andiry Xu6fd45622011-09-23 14:19:50 -07001357 if (hcd->speed != HCD_USB3)
1358 xhci_test_and_clear_bit(xhci, port_array, faked_port_index,
1359 PORT_PLC);
1360
Andiry Xu56192532010-10-14 07:23:00 -07001361cleanup:
Sarah Sharp0f2a7932009-04-27 19:57:12 -07001362 /* Update event ring dequeue pointer before dropping the lock */
1363 inc_deq(xhci, xhci->event_ring, true);
Sarah Sharp0f2a7932009-04-27 19:57:12 -07001364
Sarah Sharp386139d2011-03-24 08:02:58 -07001365 /* Don't make the USB core poll the roothub if we got a bad port status
1366 * change event. Besides, at that point we can't tell which roothub
1367 * (USB 2.0 or USB 3.0) to kick.
1368 */
1369 if (bogus_port_status)
1370 return;
1371
Sarah Sharp0f2a7932009-04-27 19:57:12 -07001372 spin_unlock(&xhci->lock);
1373 /* Pass this up to the core */
Sarah Sharpf6ff0ac2010-12-16 11:21:10 -08001374 usb_hcd_poll_rh_status(hcd);
Sarah Sharp0f2a7932009-04-27 19:57:12 -07001375 spin_lock(&xhci->lock);
1376}
1377
1378/*
Sarah Sharpd0e96f52009-04-27 19:58:01 -07001379 * This TD is defined by the TRBs starting at start_trb in start_seg and ending
1380 * at end_trb, which may be in another segment. If the suspect DMA address is a
1381 * TRB in this TD, this function returns that TRB's segment. Otherwise it
1382 * returns 0.
1383 */
Sarah Sharp6648f292009-11-09 13:35:23 -08001384struct xhci_segment *trb_in_td(struct xhci_segment *start_seg,
Sarah Sharpd0e96f52009-04-27 19:58:01 -07001385 union xhci_trb *start_trb,
1386 union xhci_trb *end_trb,
1387 dma_addr_t suspect_dma)
1388{
1389 dma_addr_t start_dma;
1390 dma_addr_t end_seg_dma;
1391 dma_addr_t end_trb_dma;
1392 struct xhci_segment *cur_seg;
1393
Sarah Sharp23e3be12009-04-29 19:05:20 -07001394 start_dma = xhci_trb_virt_to_dma(start_seg, start_trb);
Sarah Sharpd0e96f52009-04-27 19:58:01 -07001395 cur_seg = start_seg;
1396
1397 do {
Sarah Sharp2fa88da2009-11-03 22:02:24 -08001398 if (start_dma == 0)
Randy Dunlap326b4812010-04-19 08:53:50 -07001399 return NULL;
Sarah Sharpae636742009-04-29 19:02:31 -07001400 /* We may get an event for a Link TRB in the middle of a TD */
Sarah Sharp23e3be12009-04-29 19:05:20 -07001401 end_seg_dma = xhci_trb_virt_to_dma(cur_seg,
Sarah Sharp2fa88da2009-11-03 22:02:24 -08001402 &cur_seg->trbs[TRBS_PER_SEGMENT - 1]);
Sarah Sharpd0e96f52009-04-27 19:58:01 -07001403 /* If the end TRB isn't in this segment, this is set to 0 */
Sarah Sharp23e3be12009-04-29 19:05:20 -07001404 end_trb_dma = xhci_trb_virt_to_dma(cur_seg, end_trb);
Sarah Sharpd0e96f52009-04-27 19:58:01 -07001405
1406 if (end_trb_dma > 0) {
1407 /* The end TRB is in this segment, so suspect should be here */
1408 if (start_dma <= end_trb_dma) {
1409 if (suspect_dma >= start_dma && suspect_dma <= end_trb_dma)
1410 return cur_seg;
1411 } else {
1412 /* Case for one segment with
1413 * a TD wrapped around to the top
1414 */
1415 if ((suspect_dma >= start_dma &&
1416 suspect_dma <= end_seg_dma) ||
1417 (suspect_dma >= cur_seg->dma &&
1418 suspect_dma <= end_trb_dma))
1419 return cur_seg;
1420 }
Randy Dunlap326b4812010-04-19 08:53:50 -07001421 return NULL;
Sarah Sharpd0e96f52009-04-27 19:58:01 -07001422 } else {
1423 /* Might still be somewhere in this segment */
1424 if (suspect_dma >= start_dma && suspect_dma <= end_seg_dma)
1425 return cur_seg;
1426 }
1427 cur_seg = cur_seg->next;
Sarah Sharp23e3be12009-04-29 19:05:20 -07001428 start_dma = xhci_trb_virt_to_dma(cur_seg, &cur_seg->trbs[0]);
Sarah Sharp2fa88da2009-11-03 22:02:24 -08001429 } while (cur_seg != start_seg);
Sarah Sharpd0e96f52009-04-27 19:58:01 -07001430
Randy Dunlap326b4812010-04-19 08:53:50 -07001431 return NULL;
Sarah Sharpd0e96f52009-04-27 19:58:01 -07001432}
1433
Sarah Sharpbcef3fd2009-11-11 10:28:44 -08001434static void xhci_cleanup_halted_endpoint(struct xhci_hcd *xhci,
1435 unsigned int slot_id, unsigned int ep_index,
Sarah Sharpe9df17e2010-04-02 15:34:43 -07001436 unsigned int stream_id,
Sarah Sharpbcef3fd2009-11-11 10:28:44 -08001437 struct xhci_td *td, union xhci_trb *event_trb)
1438{
1439 struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index];
1440 ep->ep_state |= EP_HALTED;
1441 ep->stopped_td = td;
1442 ep->stopped_trb = event_trb;
Sarah Sharpe9df17e2010-04-02 15:34:43 -07001443 ep->stopped_stream = stream_id;
Sarah Sharp1624ae12010-05-06 13:40:08 -07001444
Sarah Sharpbcef3fd2009-11-11 10:28:44 -08001445 xhci_queue_reset_ep(xhci, slot_id, ep_index);
1446 xhci_cleanup_stalled_ring(xhci, td->urb->dev, ep_index);
Sarah Sharp1624ae12010-05-06 13:40:08 -07001447
1448 ep->stopped_td = NULL;
1449 ep->stopped_trb = NULL;
Sarah Sharp5e5cf6f2010-05-06 13:40:18 -07001450 ep->stopped_stream = 0;
Sarah Sharp1624ae12010-05-06 13:40:08 -07001451
Sarah Sharpbcef3fd2009-11-11 10:28:44 -08001452 xhci_ring_cmd_db(xhci);
1453}
1454
1455/* Check if an error has halted the endpoint ring. The class driver will
1456 * cleanup the halt for a non-default control endpoint if we indicate a stall.
1457 * However, a babble and other errors also halt the endpoint ring, and the class
1458 * driver won't clear the halt in that case, so we need to issue a Set Transfer
1459 * Ring Dequeue Pointer command manually.
1460 */
1461static int xhci_requires_manual_halt_cleanup(struct xhci_hcd *xhci,
1462 struct xhci_ep_ctx *ep_ctx,
1463 unsigned int trb_comp_code)
1464{
1465 /* TRB completion codes that may require a manual halt cleanup */
1466 if (trb_comp_code == COMP_TX_ERR ||
1467 trb_comp_code == COMP_BABBLE ||
1468 trb_comp_code == COMP_SPLIT_ERR)
1469 /* The 0.96 spec says a babbling control endpoint
1470 * is not halted. The 0.96 spec says it is. Some HW
1471 * claims to be 0.95 compliant, but it halts the control
1472 * endpoint anyway. Check if a babble halted the
1473 * endpoint.
1474 */
Matt Evansf5960b62011-06-01 10:22:55 +10001475 if ((ep_ctx->ep_info & cpu_to_le32(EP_STATE_MASK)) ==
1476 cpu_to_le32(EP_STATE_HALTED))
Sarah Sharpbcef3fd2009-11-11 10:28:44 -08001477 return 1;
1478
1479 return 0;
1480}
1481
Sarah Sharpb45b5062009-12-09 15:59:06 -08001482int xhci_is_vendor_info_code(struct xhci_hcd *xhci, unsigned int trb_comp_code)
1483{
1484 if (trb_comp_code >= 224 && trb_comp_code <= 255) {
1485 /* Vendor defined "informational" completion code,
1486 * treat as not-an-error.
1487 */
1488 xhci_dbg(xhci, "Vendor defined info completion code %u\n",
1489 trb_comp_code);
1490 xhci_dbg(xhci, "Treating code as success.\n");
1491 return 1;
1492 }
1493 return 0;
1494}
1495
Sarah Sharpd0e96f52009-04-27 19:58:01 -07001496/*
Andiry Xu4422da62010-07-22 15:22:55 -07001497 * Finish the td processing, remove the td from td list;
1498 * Return 1 if the urb can be given back.
1499 */
1500static int finish_td(struct xhci_hcd *xhci, struct xhci_td *td,
1501 union xhci_trb *event_trb, struct xhci_transfer_event *event,
1502 struct xhci_virt_ep *ep, int *status, bool skip)
1503{
1504 struct xhci_virt_device *xdev;
1505 struct xhci_ring *ep_ring;
1506 unsigned int slot_id;
1507 int ep_index;
1508 struct urb *urb = NULL;
1509 struct xhci_ep_ctx *ep_ctx;
1510 int ret = 0;
Andiry Xu8e51adc2010-07-22 15:23:31 -07001511 struct urb_priv *urb_priv;
Andiry Xu4422da62010-07-22 15:22:55 -07001512 u32 trb_comp_code;
1513
Matt Evans28ccd292011-03-29 13:40:46 +11001514 slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
Andiry Xu4422da62010-07-22 15:22:55 -07001515 xdev = xhci->devs[slot_id];
Matt Evans28ccd292011-03-29 13:40:46 +11001516 ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1;
1517 ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
Andiry Xu4422da62010-07-22 15:22:55 -07001518 ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
Matt Evans28ccd292011-03-29 13:40:46 +11001519 trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
Andiry Xu4422da62010-07-22 15:22:55 -07001520
1521 if (skip)
1522 goto td_cleanup;
1523
1524 if (trb_comp_code == COMP_STOP_INVAL ||
1525 trb_comp_code == COMP_STOP) {
1526 /* The Endpoint Stop Command completion will take care of any
1527 * stopped TDs. A stopped TD may be restarted, so don't update
1528 * the ring dequeue pointer or take this TD off any lists yet.
1529 */
1530 ep->stopped_td = td;
1531 ep->stopped_trb = event_trb;
1532 return 0;
1533 } else {
1534 if (trb_comp_code == COMP_STALL) {
1535 /* The transfer is completed from the driver's
1536 * perspective, but we need to issue a set dequeue
1537 * command for this stalled endpoint to move the dequeue
1538 * pointer past the TD. We can't do that here because
1539 * the halt condition must be cleared first. Let the
1540 * USB class driver clear the stall later.
1541 */
1542 ep->stopped_td = td;
1543 ep->stopped_trb = event_trb;
1544 ep->stopped_stream = ep_ring->stream_id;
1545 } else if (xhci_requires_manual_halt_cleanup(xhci,
1546 ep_ctx, trb_comp_code)) {
1547 /* Other types of errors halt the endpoint, but the
1548 * class driver doesn't call usb_reset_endpoint() unless
1549 * the error is -EPIPE. Clear the halted status in the
1550 * xHCI hardware manually.
1551 */
1552 xhci_cleanup_halted_endpoint(xhci,
1553 slot_id, ep_index, ep_ring->stream_id,
1554 td, event_trb);
1555 } else {
1556 /* Update ring dequeue pointer */
1557 while (ep_ring->dequeue != td->last_trb)
1558 inc_deq(xhci, ep_ring, false);
1559 inc_deq(xhci, ep_ring, false);
1560 }
1561
1562td_cleanup:
1563 /* Clean up the endpoint's TD list */
1564 urb = td->urb;
Andiry Xu8e51adc2010-07-22 15:23:31 -07001565 urb_priv = urb->hcpriv;
Andiry Xu4422da62010-07-22 15:22:55 -07001566
1567 /* Do one last check of the actual transfer length.
1568 * If the host controller said we transferred more data than
1569 * the buffer length, urb->actual_length will be a very big
1570 * number (since it's unsigned). Play it safe and say we didn't
1571 * transfer anything.
1572 */
1573 if (urb->actual_length > urb->transfer_buffer_length) {
1574 xhci_warn(xhci, "URB transfer length is wrong, "
1575 "xHC issue? req. len = %u, "
1576 "act. len = %u\n",
1577 urb->transfer_buffer_length,
1578 urb->actual_length);
1579 urb->actual_length = 0;
1580 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
1581 *status = -EREMOTEIO;
1582 else
1583 *status = 0;
1584 }
Sarah Sharp585df1d2011-08-02 15:43:40 -07001585 list_del_init(&td->td_list);
Andiry Xu4422da62010-07-22 15:22:55 -07001586 /* Was this TD slated to be cancelled but completed anyway? */
1587 if (!list_empty(&td->cancelled_td_list))
Sarah Sharp585df1d2011-08-02 15:43:40 -07001588 list_del_init(&td->cancelled_td_list);
Andiry Xu4422da62010-07-22 15:22:55 -07001589
Andiry Xu8e51adc2010-07-22 15:23:31 -07001590 urb_priv->td_cnt++;
1591 /* Giveback the urb when all the tds are completed */
Andiry Xuc41136b2011-03-22 17:08:14 +08001592 if (urb_priv->td_cnt == urb_priv->length) {
Andiry Xu8e51adc2010-07-22 15:23:31 -07001593 ret = 1;
Andiry Xuc41136b2011-03-22 17:08:14 +08001594 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
1595 xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs--;
1596 if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs
1597 == 0) {
1598 if (xhci->quirks & XHCI_AMD_PLL_FIX)
1599 usb_amd_quirk_pll_enable();
1600 }
1601 }
1602 }
Andiry Xu4422da62010-07-22 15:22:55 -07001603 }
1604
1605 return ret;
1606}
1607
1608/*
Andiry Xu8af56be2010-07-22 15:23:03 -07001609 * Process control tds, update urb status and actual_length.
1610 */
1611static int process_ctrl_td(struct xhci_hcd *xhci, struct xhci_td *td,
1612 union xhci_trb *event_trb, struct xhci_transfer_event *event,
1613 struct xhci_virt_ep *ep, int *status)
1614{
1615 struct xhci_virt_device *xdev;
1616 struct xhci_ring *ep_ring;
1617 unsigned int slot_id;
1618 int ep_index;
1619 struct xhci_ep_ctx *ep_ctx;
1620 u32 trb_comp_code;
1621
Matt Evans28ccd292011-03-29 13:40:46 +11001622 slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
Andiry Xu8af56be2010-07-22 15:23:03 -07001623 xdev = xhci->devs[slot_id];
Matt Evans28ccd292011-03-29 13:40:46 +11001624 ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1;
1625 ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
Andiry Xu8af56be2010-07-22 15:23:03 -07001626 ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
Matt Evans28ccd292011-03-29 13:40:46 +11001627 trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
Andiry Xu8af56be2010-07-22 15:23:03 -07001628
1629 xhci_debug_trb(xhci, xhci->event_ring->dequeue);
1630 switch (trb_comp_code) {
1631 case COMP_SUCCESS:
1632 if (event_trb == ep_ring->dequeue) {
1633 xhci_warn(xhci, "WARN: Success on ctrl setup TRB "
1634 "without IOC set??\n");
1635 *status = -ESHUTDOWN;
1636 } else if (event_trb != td->last_trb) {
1637 xhci_warn(xhci, "WARN: Success on ctrl data TRB "
1638 "without IOC set??\n");
1639 *status = -ESHUTDOWN;
1640 } else {
Andiry Xu8af56be2010-07-22 15:23:03 -07001641 *status = 0;
1642 }
1643 break;
1644 case COMP_SHORT_TX:
1645 xhci_warn(xhci, "WARN: short transfer on control ep\n");
1646 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
1647 *status = -EREMOTEIO;
1648 else
1649 *status = 0;
1650 break;
Sarah Sharp3abeca92011-05-05 19:08:09 -07001651 case COMP_STOP_INVAL:
1652 case COMP_STOP:
1653 return finish_td(xhci, td, event_trb, event, ep, status, false);
Andiry Xu8af56be2010-07-22 15:23:03 -07001654 default:
1655 if (!xhci_requires_manual_halt_cleanup(xhci,
1656 ep_ctx, trb_comp_code))
1657 break;
1658 xhci_dbg(xhci, "TRB error code %u, "
1659 "halted endpoint index = %u\n",
1660 trb_comp_code, ep_index);
1661 /* else fall through */
1662 case COMP_STALL:
1663 /* Did we transfer part of the data (middle) phase? */
1664 if (event_trb != ep_ring->dequeue &&
1665 event_trb != td->last_trb)
1666 td->urb->actual_length =
1667 td->urb->transfer_buffer_length
Matt Evans28ccd292011-03-29 13:40:46 +11001668 - TRB_LEN(le32_to_cpu(event->transfer_len));
Andiry Xu8af56be2010-07-22 15:23:03 -07001669 else
1670 td->urb->actual_length = 0;
1671
1672 xhci_cleanup_halted_endpoint(xhci,
1673 slot_id, ep_index, 0, td, event_trb);
1674 return finish_td(xhci, td, event_trb, event, ep, status, true);
1675 }
1676 /*
1677 * Did we transfer any data, despite the errors that might have
1678 * happened? I.e. did we get past the setup stage?
1679 */
1680 if (event_trb != ep_ring->dequeue) {
1681 /* The event was for the status stage */
1682 if (event_trb == td->last_trb) {
1683 if (td->urb->actual_length != 0) {
1684 /* Don't overwrite a previously set error code
1685 */
1686 if ((*status == -EINPROGRESS || *status == 0) &&
1687 (td->urb->transfer_flags
1688 & URB_SHORT_NOT_OK))
1689 /* Did we already see a short data
1690 * stage? */
1691 *status = -EREMOTEIO;
1692 } else {
1693 td->urb->actual_length =
1694 td->urb->transfer_buffer_length;
1695 }
1696 } else {
1697 /* Maybe the event was for the data stage? */
Sarah Sharp3abeca92011-05-05 19:08:09 -07001698 td->urb->actual_length =
1699 td->urb->transfer_buffer_length -
1700 TRB_LEN(le32_to_cpu(event->transfer_len));
1701 xhci_dbg(xhci, "Waiting for status "
1702 "stage event\n");
1703 return 0;
Andiry Xu8af56be2010-07-22 15:23:03 -07001704 }
1705 }
1706
1707 return finish_td(xhci, td, event_trb, event, ep, status, false);
1708}
1709
1710/*
Andiry Xu04e51902010-07-22 15:23:39 -07001711 * Process isochronous tds, update urb packet status and actual_length.
1712 */
1713static int process_isoc_td(struct xhci_hcd *xhci, struct xhci_td *td,
1714 union xhci_trb *event_trb, struct xhci_transfer_event *event,
1715 struct xhci_virt_ep *ep, int *status)
1716{
1717 struct xhci_ring *ep_ring;
1718 struct urb_priv *urb_priv;
1719 int idx;
1720 int len = 0;
Andiry Xu04e51902010-07-22 15:23:39 -07001721 union xhci_trb *cur_trb;
1722 struct xhci_segment *cur_seg;
Dmitry Torokhov926008c2011-03-23 20:47:05 -07001723 struct usb_iso_packet_descriptor *frame;
Andiry Xu04e51902010-07-22 15:23:39 -07001724 u32 trb_comp_code;
Dmitry Torokhov926008c2011-03-23 20:47:05 -07001725 bool skip_td = false;
Andiry Xu04e51902010-07-22 15:23:39 -07001726
Matt Evans28ccd292011-03-29 13:40:46 +11001727 ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
1728 trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
Andiry Xu04e51902010-07-22 15:23:39 -07001729 urb_priv = td->urb->hcpriv;
1730 idx = urb_priv->td_cnt;
Dmitry Torokhov926008c2011-03-23 20:47:05 -07001731 frame = &td->urb->iso_frame_desc[idx];
Andiry Xu04e51902010-07-22 15:23:39 -07001732
Dmitry Torokhov926008c2011-03-23 20:47:05 -07001733 /* handle completion code */
1734 switch (trb_comp_code) {
1735 case COMP_SUCCESS:
1736 frame->status = 0;
Dmitry Torokhov926008c2011-03-23 20:47:05 -07001737 break;
1738 case COMP_SHORT_TX:
1739 frame->status = td->urb->transfer_flags & URB_SHORT_NOT_OK ?
1740 -EREMOTEIO : 0;
1741 break;
1742 case COMP_BW_OVER:
1743 frame->status = -ECOMM;
1744 skip_td = true;
1745 break;
1746 case COMP_BUFF_OVER:
1747 case COMP_BABBLE:
1748 frame->status = -EOVERFLOW;
1749 skip_td = true;
1750 break;
Alex Hef6ba6fe2011-06-08 18:34:06 +08001751 case COMP_DEV_ERR:
Dmitry Torokhov926008c2011-03-23 20:47:05 -07001752 case COMP_STALL:
1753 frame->status = -EPROTO;
1754 skip_td = true;
1755 break;
1756 case COMP_STOP:
1757 case COMP_STOP_INVAL:
1758 break;
1759 default:
1760 frame->status = -1;
1761 break;
Andiry Xu04e51902010-07-22 15:23:39 -07001762 }
1763
Dmitry Torokhov926008c2011-03-23 20:47:05 -07001764 if (trb_comp_code == COMP_SUCCESS || skip_td) {
1765 frame->actual_length = frame->length;
1766 td->urb->actual_length += frame->length;
Andiry Xu04e51902010-07-22 15:23:39 -07001767 } else {
1768 for (cur_trb = ep_ring->dequeue,
1769 cur_seg = ep_ring->deq_seg; cur_trb != event_trb;
1770 next_trb(xhci, ep_ring, &cur_seg, &cur_trb)) {
Matt Evansf5960b62011-06-01 10:22:55 +10001771 if (!TRB_TYPE_NOOP_LE32(cur_trb->generic.field[3]) &&
1772 !TRB_TYPE_LINK_LE32(cur_trb->generic.field[3]))
Matt Evans28ccd292011-03-29 13:40:46 +11001773 len += TRB_LEN(le32_to_cpu(cur_trb->generic.field[2]));
Andiry Xu04e51902010-07-22 15:23:39 -07001774 }
Matt Evans28ccd292011-03-29 13:40:46 +11001775 len += TRB_LEN(le32_to_cpu(cur_trb->generic.field[2])) -
1776 TRB_LEN(le32_to_cpu(event->transfer_len));
Andiry Xu04e51902010-07-22 15:23:39 -07001777
1778 if (trb_comp_code != COMP_STOP_INVAL) {
Dmitry Torokhov926008c2011-03-23 20:47:05 -07001779 frame->actual_length = len;
Andiry Xu04e51902010-07-22 15:23:39 -07001780 td->urb->actual_length += len;
1781 }
1782 }
1783
Andiry Xu04e51902010-07-22 15:23:39 -07001784 return finish_td(xhci, td, event_trb, event, ep, status, false);
1785}
1786
Dmitry Torokhov926008c2011-03-23 20:47:05 -07001787static int skip_isoc_td(struct xhci_hcd *xhci, struct xhci_td *td,
1788 struct xhci_transfer_event *event,
1789 struct xhci_virt_ep *ep, int *status)
1790{
1791 struct xhci_ring *ep_ring;
1792 struct urb_priv *urb_priv;
1793 struct usb_iso_packet_descriptor *frame;
1794 int idx;
1795
Matt Evansf6975312011-06-01 13:01:01 +10001796 ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
Dmitry Torokhov926008c2011-03-23 20:47:05 -07001797 urb_priv = td->urb->hcpriv;
1798 idx = urb_priv->td_cnt;
1799 frame = &td->urb->iso_frame_desc[idx];
1800
Sarah Sharpb3df3f92011-06-15 19:57:46 -07001801 /* The transfer is partly done. */
Dmitry Torokhov926008c2011-03-23 20:47:05 -07001802 frame->status = -EXDEV;
1803
1804 /* calc actual length */
1805 frame->actual_length = 0;
1806
1807 /* Update ring dequeue pointer */
1808 while (ep_ring->dequeue != td->last_trb)
1809 inc_deq(xhci, ep_ring, false);
1810 inc_deq(xhci, ep_ring, false);
1811
1812 return finish_td(xhci, td, NULL, event, ep, status, true);
1813}
1814
Andiry Xu04e51902010-07-22 15:23:39 -07001815/*
Andiry Xu22405ed2010-07-22 15:23:08 -07001816 * Process bulk and interrupt tds, update urb status and actual_length.
1817 */
1818static int process_bulk_intr_td(struct xhci_hcd *xhci, struct xhci_td *td,
1819 union xhci_trb *event_trb, struct xhci_transfer_event *event,
1820 struct xhci_virt_ep *ep, int *status)
1821{
1822 struct xhci_ring *ep_ring;
1823 union xhci_trb *cur_trb;
1824 struct xhci_segment *cur_seg;
1825 u32 trb_comp_code;
1826
Matt Evans28ccd292011-03-29 13:40:46 +11001827 ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
1828 trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
Andiry Xu22405ed2010-07-22 15:23:08 -07001829
1830 switch (trb_comp_code) {
1831 case COMP_SUCCESS:
1832 /* Double check that the HW transferred everything. */
1833 if (event_trb != td->last_trb) {
1834 xhci_warn(xhci, "WARN Successful completion "
1835 "on short TX\n");
1836 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
1837 *status = -EREMOTEIO;
1838 else
1839 *status = 0;
1840 } else {
Andiry Xu22405ed2010-07-22 15:23:08 -07001841 *status = 0;
1842 }
1843 break;
1844 case COMP_SHORT_TX:
1845 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
1846 *status = -EREMOTEIO;
1847 else
1848 *status = 0;
1849 break;
1850 default:
1851 /* Others already handled above */
1852 break;
1853 }
Sarah Sharpf444ff22011-04-05 15:53:47 -07001854 if (trb_comp_code == COMP_SHORT_TX)
1855 xhci_dbg(xhci, "ep %#x - asked for %d bytes, "
1856 "%d bytes untransferred\n",
1857 td->urb->ep->desc.bEndpointAddress,
1858 td->urb->transfer_buffer_length,
1859 TRB_LEN(le32_to_cpu(event->transfer_len)));
Andiry Xu22405ed2010-07-22 15:23:08 -07001860 /* Fast path - was this the last TRB in the TD for this URB? */
1861 if (event_trb == td->last_trb) {
Matt Evans28ccd292011-03-29 13:40:46 +11001862 if (TRB_LEN(le32_to_cpu(event->transfer_len)) != 0) {
Andiry Xu22405ed2010-07-22 15:23:08 -07001863 td->urb->actual_length =
1864 td->urb->transfer_buffer_length -
Matt Evans28ccd292011-03-29 13:40:46 +11001865 TRB_LEN(le32_to_cpu(event->transfer_len));
Andiry Xu22405ed2010-07-22 15:23:08 -07001866 if (td->urb->transfer_buffer_length <
1867 td->urb->actual_length) {
1868 xhci_warn(xhci, "HC gave bad length "
1869 "of %d bytes left\n",
Matt Evans28ccd292011-03-29 13:40:46 +11001870 TRB_LEN(le32_to_cpu(event->transfer_len)));
Andiry Xu22405ed2010-07-22 15:23:08 -07001871 td->urb->actual_length = 0;
1872 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
1873 *status = -EREMOTEIO;
1874 else
1875 *status = 0;
1876 }
1877 /* Don't overwrite a previously set error code */
1878 if (*status == -EINPROGRESS) {
1879 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
1880 *status = -EREMOTEIO;
1881 else
1882 *status = 0;
1883 }
1884 } else {
1885 td->urb->actual_length =
1886 td->urb->transfer_buffer_length;
1887 /* Ignore a short packet completion if the
1888 * untransferred length was zero.
1889 */
1890 if (*status == -EREMOTEIO)
1891 *status = 0;
1892 }
1893 } else {
1894 /* Slow path - walk the list, starting from the dequeue
1895 * pointer, to get the actual length transferred.
1896 */
1897 td->urb->actual_length = 0;
1898 for (cur_trb = ep_ring->dequeue, cur_seg = ep_ring->deq_seg;
1899 cur_trb != event_trb;
1900 next_trb(xhci, ep_ring, &cur_seg, &cur_trb)) {
Matt Evansf5960b62011-06-01 10:22:55 +10001901 if (!TRB_TYPE_NOOP_LE32(cur_trb->generic.field[3]) &&
1902 !TRB_TYPE_LINK_LE32(cur_trb->generic.field[3]))
Andiry Xu22405ed2010-07-22 15:23:08 -07001903 td->urb->actual_length +=
Matt Evans28ccd292011-03-29 13:40:46 +11001904 TRB_LEN(le32_to_cpu(cur_trb->generic.field[2]));
Andiry Xu22405ed2010-07-22 15:23:08 -07001905 }
1906 /* If the ring didn't stop on a Link or No-op TRB, add
1907 * in the actual bytes transferred from the Normal TRB
1908 */
1909 if (trb_comp_code != COMP_STOP_INVAL)
1910 td->urb->actual_length +=
Matt Evans28ccd292011-03-29 13:40:46 +11001911 TRB_LEN(le32_to_cpu(cur_trb->generic.field[2])) -
1912 TRB_LEN(le32_to_cpu(event->transfer_len));
Andiry Xu22405ed2010-07-22 15:23:08 -07001913 }
1914
1915 return finish_td(xhci, td, event_trb, event, ep, status, false);
1916}
1917
1918/*
Sarah Sharpd0e96f52009-04-27 19:58:01 -07001919 * If this function returns an error condition, it means it got a Transfer
1920 * event with a corrupted Slot ID, Endpoint ID, or TRB DMA address.
1921 * At this point, the host controller is probably hosed and should be reset.
1922 */
1923static int handle_tx_event(struct xhci_hcd *xhci,
1924 struct xhci_transfer_event *event)
1925{
1926 struct xhci_virt_device *xdev;
Sarah Sharp63a0d9a2009-09-04 10:53:09 -07001927 struct xhci_virt_ep *ep;
Sarah Sharpd0e96f52009-04-27 19:58:01 -07001928 struct xhci_ring *ep_ring;
Sarah Sharp82d10092009-08-07 14:04:52 -07001929 unsigned int slot_id;
Sarah Sharpd0e96f52009-04-27 19:58:01 -07001930 int ep_index;
Randy Dunlap326b4812010-04-19 08:53:50 -07001931 struct xhci_td *td = NULL;
Sarah Sharpd0e96f52009-04-27 19:58:01 -07001932 dma_addr_t event_dma;
1933 struct xhci_segment *event_seg;
1934 union xhci_trb *event_trb;
Randy Dunlap326b4812010-04-19 08:53:50 -07001935 struct urb *urb = NULL;
Sarah Sharpd0e96f52009-04-27 19:58:01 -07001936 int status = -EINPROGRESS;
Andiry Xu8e51adc2010-07-22 15:23:31 -07001937 struct urb_priv *urb_priv;
John Yound115b042009-07-27 12:05:15 -07001938 struct xhci_ep_ctx *ep_ctx;
Sarah Sharp66d1eeb2009-08-27 14:35:53 -07001939 u32 trb_comp_code;
Andiry Xu4422da62010-07-22 15:22:55 -07001940 int ret = 0;
Sarah Sharpd0e96f52009-04-27 19:58:01 -07001941
Matt Evans28ccd292011-03-29 13:40:46 +11001942 slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
Sarah Sharp82d10092009-08-07 14:04:52 -07001943 xdev = xhci->devs[slot_id];
Sarah Sharpd0e96f52009-04-27 19:58:01 -07001944 if (!xdev) {
1945 xhci_err(xhci, "ERROR Transfer event pointed to bad slot\n");
1946 return -ENODEV;
1947 }
1948
1949 /* Endpoint ID is 1 based, our index is zero based */
Matt Evans28ccd292011-03-29 13:40:46 +11001950 ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1;
Sarah Sharp63a0d9a2009-09-04 10:53:09 -07001951 ep = &xdev->eps[ep_index];
Matt Evans28ccd292011-03-29 13:40:46 +11001952 ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
John Yound115b042009-07-27 12:05:15 -07001953 ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
Andiry Xu986a92d2010-07-22 15:23:20 -07001954 if (!ep_ring ||
Matt Evans28ccd292011-03-29 13:40:46 +11001955 (le32_to_cpu(ep_ctx->ep_info) & EP_STATE_MASK) ==
1956 EP_STATE_DISABLED) {
Sarah Sharpe9df17e2010-04-02 15:34:43 -07001957 xhci_err(xhci, "ERROR Transfer event for disabled endpoint "
1958 "or incorrect stream ring\n");
Sarah Sharpd0e96f52009-04-27 19:58:01 -07001959 return -ENODEV;
1960 }
1961
Matt Evans28ccd292011-03-29 13:40:46 +11001962 event_dma = le64_to_cpu(event->buffer);
1963 trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
Andiry Xu986a92d2010-07-22 15:23:20 -07001964 /* Look for common error cases */
Sarah Sharp66d1eeb2009-08-27 14:35:53 -07001965 switch (trb_comp_code) {
Sarah Sharpb10de142009-04-27 19:58:50 -07001966 /* Skip codes that require special handling depending on
1967 * transfer type
1968 */
1969 case COMP_SUCCESS:
1970 case COMP_SHORT_TX:
1971 break;
Sarah Sharpae636742009-04-29 19:02:31 -07001972 case COMP_STOP:
1973 xhci_dbg(xhci, "Stopped on Transfer TRB\n");
1974 break;
1975 case COMP_STOP_INVAL:
1976 xhci_dbg(xhci, "Stopped on No-op or Link TRB\n");
1977 break;
Sarah Sharpb10de142009-04-27 19:58:50 -07001978 case COMP_STALL:
1979 xhci_warn(xhci, "WARN: Stalled endpoint\n");
Sarah Sharp63a0d9a2009-09-04 10:53:09 -07001980 ep->ep_state |= EP_HALTED;
Sarah Sharpb10de142009-04-27 19:58:50 -07001981 status = -EPIPE;
1982 break;
1983 case COMP_TRB_ERR:
1984 xhci_warn(xhci, "WARN: TRB error on endpoint\n");
1985 status = -EILSEQ;
1986 break;
Sarah Sharpec74e402009-11-11 10:28:36 -08001987 case COMP_SPLIT_ERR:
Sarah Sharpb10de142009-04-27 19:58:50 -07001988 case COMP_TX_ERR:
1989 xhci_warn(xhci, "WARN: transfer error on endpoint\n");
1990 status = -EPROTO;
1991 break;
Sarah Sharp4a731432009-07-27 12:04:32 -07001992 case COMP_BABBLE:
1993 xhci_warn(xhci, "WARN: babble error on endpoint\n");
1994 status = -EOVERFLOW;
1995 break;
Sarah Sharpb10de142009-04-27 19:58:50 -07001996 case COMP_DB_ERR:
1997 xhci_warn(xhci, "WARN: HC couldn't access mem fast enough\n");
1998 status = -ENOSR;
1999 break;
Andiry Xu986a92d2010-07-22 15:23:20 -07002000 case COMP_BW_OVER:
2001 xhci_warn(xhci, "WARN: bandwidth overrun event on endpoint\n");
2002 break;
2003 case COMP_BUFF_OVER:
2004 xhci_warn(xhci, "WARN: buffer overrun event on endpoint\n");
2005 break;
2006 case COMP_UNDERRUN:
2007 /*
2008 * When the Isoch ring is empty, the xHC will generate
2009 * a Ring Overrun Event for IN Isoch endpoint or Ring
2010 * Underrun Event for OUT Isoch endpoint.
2011 */
2012 xhci_dbg(xhci, "underrun event on endpoint\n");
2013 if (!list_empty(&ep_ring->td_list))
2014 xhci_dbg(xhci, "Underrun Event for slot %d ep %d "
2015 "still with TDs queued?\n",
Matt Evans28ccd292011-03-29 13:40:46 +11002016 TRB_TO_SLOT_ID(le32_to_cpu(event->flags)),
2017 ep_index);
Andiry Xu986a92d2010-07-22 15:23:20 -07002018 goto cleanup;
2019 case COMP_OVERRUN:
2020 xhci_dbg(xhci, "overrun event on endpoint\n");
2021 if (!list_empty(&ep_ring->td_list))
2022 xhci_dbg(xhci, "Overrun Event for slot %d ep %d "
2023 "still with TDs queued?\n",
Matt Evans28ccd292011-03-29 13:40:46 +11002024 TRB_TO_SLOT_ID(le32_to_cpu(event->flags)),
2025 ep_index);
Andiry Xu986a92d2010-07-22 15:23:20 -07002026 goto cleanup;
Alex Hef6ba6fe2011-06-08 18:34:06 +08002027 case COMP_DEV_ERR:
2028 xhci_warn(xhci, "WARN: detect an incompatible device");
2029 status = -EPROTO;
2030 break;
Andiry Xud18240d2010-07-22 15:23:25 -07002031 case COMP_MISSED_INT:
2032 /*
2033 * When encounter missed service error, one or more isoc tds
2034 * may be missed by xHC.
2035 * Set skip flag of the ep_ring; Complete the missed tds as
2036 * short transfer when process the ep_ring next time.
2037 */
2038 ep->skip = true;
2039 xhci_dbg(xhci, "Miss service interval error, set skip flag\n");
2040 goto cleanup;
Sarah Sharpb10de142009-04-27 19:58:50 -07002041 default:
Sarah Sharpb45b5062009-12-09 15:59:06 -08002042 if (xhci_is_vendor_info_code(xhci, trb_comp_code)) {
Sarah Sharp5ad6a522009-11-11 10:28:40 -08002043 status = 0;
2044 break;
2045 }
Andiry Xu986a92d2010-07-22 15:23:20 -07002046 xhci_warn(xhci, "ERROR Unknown event condition, HC probably "
2047 "busted\n");
Sarah Sharpb10de142009-04-27 19:58:50 -07002048 goto cleanup;
2049 }
Andiry Xu986a92d2010-07-22 15:23:20 -07002050
Andiry Xud18240d2010-07-22 15:23:25 -07002051 do {
2052 /* This TRB should be in the TD at the head of this ring's
2053 * TD list.
2054 */
2055 if (list_empty(&ep_ring->td_list)) {
2056 xhci_warn(xhci, "WARN Event TRB for slot %d ep %d "
2057 "with no TDs queued?\n",
Matt Evans28ccd292011-03-29 13:40:46 +11002058 TRB_TO_SLOT_ID(le32_to_cpu(event->flags)),
2059 ep_index);
Andiry Xud18240d2010-07-22 15:23:25 -07002060 xhci_dbg(xhci, "Event TRB with TRB type ID %u\n",
Matt Evansf5960b62011-06-01 10:22:55 +10002061 (le32_to_cpu(event->flags) &
2062 TRB_TYPE_BITMASK)>>10);
Andiry Xud18240d2010-07-22 15:23:25 -07002063 xhci_print_trb_offsets(xhci, (union xhci_trb *) event);
2064 if (ep->skip) {
2065 ep->skip = false;
2066 xhci_dbg(xhci, "td_list is empty while skip "
2067 "flag set. Clear skip flag.\n");
2068 }
2069 ret = 0;
2070 goto cleanup;
2071 }
Andiry Xu986a92d2010-07-22 15:23:20 -07002072
Andiry Xud18240d2010-07-22 15:23:25 -07002073 td = list_entry(ep_ring->td_list.next, struct xhci_td, td_list);
Dmitry Torokhov926008c2011-03-23 20:47:05 -07002074
Andiry Xud18240d2010-07-22 15:23:25 -07002075 /* Is this a TRB in the currently executing TD? */
2076 event_seg = trb_in_td(ep_ring->deq_seg, ep_ring->dequeue,
2077 td->last_trb, event_dma);
Alex Hee1cf4862011-06-03 15:58:25 +08002078
2079 /*
2080 * Skip the Force Stopped Event. The event_trb(event_dma) of FSE
2081 * is not in the current TD pointed by ep_ring->dequeue because
2082 * that the hardware dequeue pointer still at the previous TRB
2083 * of the current TD. The previous TRB maybe a Link TD or the
2084 * last TRB of the previous TD. The command completion handle
2085 * will take care the rest.
2086 */
2087 if (!event_seg && trb_comp_code == COMP_STOP_INVAL) {
2088 ret = 0;
2089 goto cleanup;
2090 }
2091
Dmitry Torokhov926008c2011-03-23 20:47:05 -07002092 if (!event_seg) {
2093 if (!ep->skip ||
2094 !usb_endpoint_xfer_isoc(&td->urb->ep->desc)) {
Sarah Sharpad808332011-05-25 10:43:56 -07002095 /* Some host controllers give a spurious
2096 * successful event after a short transfer.
2097 * Ignore it.
2098 */
2099 if ((xhci->quirks & XHCI_SPURIOUS_SUCCESS) &&
2100 ep_ring->last_td_was_short) {
2101 ep_ring->last_td_was_short = false;
2102 ret = 0;
2103 goto cleanup;
2104 }
Dmitry Torokhov926008c2011-03-23 20:47:05 -07002105 /* HC is busted, give up! */
2106 xhci_err(xhci,
2107 "ERROR Transfer event TRB DMA ptr not "
2108 "part of current TD\n");
2109 return -ESHUTDOWN;
2110 }
2111
2112 ret = skip_isoc_td(xhci, td, event, ep, &status);
2113 goto cleanup;
2114 }
Sarah Sharpad808332011-05-25 10:43:56 -07002115 if (trb_comp_code == COMP_SHORT_TX)
2116 ep_ring->last_td_was_short = true;
2117 else
2118 ep_ring->last_td_was_short = false;
Dmitry Torokhov926008c2011-03-23 20:47:05 -07002119
2120 if (ep->skip) {
Andiry Xud18240d2010-07-22 15:23:25 -07002121 xhci_dbg(xhci, "Found td. Clear skip flag.\n");
2122 ep->skip = false;
2123 }
Andiry Xu986a92d2010-07-22 15:23:20 -07002124
Dmitry Torokhov926008c2011-03-23 20:47:05 -07002125 event_trb = &event_seg->trbs[(event_dma - event_seg->dma) /
2126 sizeof(*event_trb)];
2127 /*
2128 * No-op TRB should not trigger interrupts.
2129 * If event_trb is a no-op TRB, it means the
2130 * corresponding TD has been cancelled. Just ignore
2131 * the TD.
2132 */
Matt Evansf5960b62011-06-01 10:22:55 +10002133 if (TRB_TYPE_NOOP_LE32(event_trb->generic.field[3])) {
Dmitry Torokhov926008c2011-03-23 20:47:05 -07002134 xhci_dbg(xhci,
2135 "event_trb is a no-op TRB. Skip it\n");
2136 goto cleanup;
Andiry Xud18240d2010-07-22 15:23:25 -07002137 }
2138
2139 /* Now update the urb's actual_length and give back to
2140 * the core
2141 */
2142 if (usb_endpoint_xfer_control(&td->urb->ep->desc))
2143 ret = process_ctrl_td(xhci, td, event_trb, event, ep,
2144 &status);
Andiry Xu04e51902010-07-22 15:23:39 -07002145 else if (usb_endpoint_xfer_isoc(&td->urb->ep->desc))
2146 ret = process_isoc_td(xhci, td, event_trb, event, ep,
2147 &status);
Andiry Xud18240d2010-07-22 15:23:25 -07002148 else
2149 ret = process_bulk_intr_td(xhci, td, event_trb, event,
2150 ep, &status);
Andiry Xu4422da62010-07-22 15:22:55 -07002151
2152cleanup:
Andiry Xud18240d2010-07-22 15:23:25 -07002153 /*
2154 * Do not update event ring dequeue pointer if ep->skip is set.
2155 * Will roll back to continue process missed tds.
Sarah Sharp82d10092009-08-07 14:04:52 -07002156 */
Andiry Xud18240d2010-07-22 15:23:25 -07002157 if (trb_comp_code == COMP_MISSED_INT || !ep->skip) {
2158 inc_deq(xhci, xhci->event_ring, true);
Andiry Xud18240d2010-07-22 15:23:25 -07002159 }
Sarah Sharpd0e96f52009-04-27 19:58:01 -07002160
Andiry Xud18240d2010-07-22 15:23:25 -07002161 if (ret) {
2162 urb = td->urb;
Andiry Xu8e51adc2010-07-22 15:23:31 -07002163 urb_priv = urb->hcpriv;
Andiry Xud18240d2010-07-22 15:23:25 -07002164 /* Leave the TD around for the reset endpoint function
2165 * to use(but only if it's not a control endpoint,
2166 * since we already queued the Set TR dequeue pointer
2167 * command for stalled control endpoints).
2168 */
2169 if (usb_endpoint_xfer_control(&urb->ep->desc) ||
2170 (trb_comp_code != COMP_STALL &&
2171 trb_comp_code != COMP_BABBLE))
Andiry Xu8e51adc2010-07-22 15:23:31 -07002172 xhci_urb_free_priv(xhci, urb_priv);
Andiry Xud18240d2010-07-22 15:23:25 -07002173
Sarah Sharp214f76f2010-10-26 11:22:02 -07002174 usb_hcd_unlink_urb_from_ep(bus_to_hcd(urb->dev->bus), urb);
Sarah Sharpf444ff22011-04-05 15:53:47 -07002175 if ((urb->actual_length != urb->transfer_buffer_length &&
2176 (urb->transfer_flags &
2177 URB_SHORT_NOT_OK)) ||
Sarah Sharpfd984d22011-09-02 11:05:56 -07002178 (status != 0 &&
2179 !usb_endpoint_xfer_isoc(&urb->ep->desc)))
Sarah Sharpf444ff22011-04-05 15:53:47 -07002180 xhci_dbg(xhci, "Giveback URB %p, len = %d, "
2181 "expected = %x, status = %d\n",
2182 urb, urb->actual_length,
2183 urb->transfer_buffer_length,
2184 status);
Andiry Xud18240d2010-07-22 15:23:25 -07002185 spin_unlock(&xhci->lock);
Sarah Sharpb3df3f92011-06-15 19:57:46 -07002186 /* EHCI, UHCI, and OHCI always unconditionally set the
2187 * urb->status of an isochronous endpoint to 0.
2188 */
2189 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS)
2190 status = 0;
Sarah Sharp214f76f2010-10-26 11:22:02 -07002191 usb_hcd_giveback_urb(bus_to_hcd(urb->dev->bus), urb, status);
Andiry Xud18240d2010-07-22 15:23:25 -07002192 spin_lock(&xhci->lock);
2193 }
2194
2195 /*
2196 * If ep->skip is set, it means there are missed tds on the
2197 * endpoint ring need to take care of.
2198 * Process them as short transfer until reach the td pointed by
2199 * the event.
2200 */
2201 } while (ep->skip && trb_comp_code != COMP_MISSED_INT);
2202
Sarah Sharpd0e96f52009-04-27 19:58:01 -07002203 return 0;
2204}
2205
2206/*
Sarah Sharp0f2a7932009-04-27 19:57:12 -07002207 * This function handles all OS-owned events on the event ring. It may drop
2208 * xhci->lock between event processing (e.g. to pass up port status changes).
Matt Evans9dee9a22011-03-29 13:41:02 +11002209 * Returns >0 for "possibly more events to process" (caller should call again),
2210 * otherwise 0 if done. In future, <0 returns should indicate error code.
Sarah Sharp0f2a7932009-04-27 19:57:12 -07002211 */
Matt Evans9dee9a22011-03-29 13:41:02 +11002212static int xhci_handle_event(struct xhci_hcd *xhci)
Sarah Sharp7f84eef2009-04-27 19:53:56 -07002213{
2214 union xhci_trb *event;
Sarah Sharp0f2a7932009-04-27 19:57:12 -07002215 int update_ptrs = 1;
Sarah Sharpd0e96f52009-04-27 19:58:01 -07002216 int ret;
Sarah Sharp7f84eef2009-04-27 19:53:56 -07002217
2218 if (!xhci->event_ring || !xhci->event_ring->dequeue) {
2219 xhci->error_bitmask |= 1 << 1;
Matt Evans9dee9a22011-03-29 13:41:02 +11002220 return 0;
Sarah Sharp7f84eef2009-04-27 19:53:56 -07002221 }
2222
2223 event = xhci->event_ring->dequeue;
2224 /* Does the HC or OS own the TRB? */
Matt Evans28ccd292011-03-29 13:40:46 +11002225 if ((le32_to_cpu(event->event_cmd.flags) & TRB_CYCLE) !=
2226 xhci->event_ring->cycle_state) {
Sarah Sharp7f84eef2009-04-27 19:53:56 -07002227 xhci->error_bitmask |= 1 << 2;
Matt Evans9dee9a22011-03-29 13:41:02 +11002228 return 0;
Sarah Sharp7f84eef2009-04-27 19:53:56 -07002229 }
2230
Matt Evans92a3da42011-03-29 13:40:51 +11002231 /*
2232 * Barrier between reading the TRB_CYCLE (valid) flag above and any
2233 * speculative reads of the event's flags/data below.
2234 */
2235 rmb();
Sarah Sharp0f2a7932009-04-27 19:57:12 -07002236 /* FIXME: Handle more event types. */
Matt Evans28ccd292011-03-29 13:40:46 +11002237 switch ((le32_to_cpu(event->event_cmd.flags) & TRB_TYPE_BITMASK)) {
Sarah Sharp7f84eef2009-04-27 19:53:56 -07002238 case TRB_TYPE(TRB_COMPLETION):
2239 handle_cmd_completion(xhci, &event->event_cmd);
2240 break;
Sarah Sharp0f2a7932009-04-27 19:57:12 -07002241 case TRB_TYPE(TRB_PORT_STATUS):
2242 handle_port_status(xhci, event);
2243 update_ptrs = 0;
2244 break;
Sarah Sharpd0e96f52009-04-27 19:58:01 -07002245 case TRB_TYPE(TRB_TRANSFER):
2246 ret = handle_tx_event(xhci, &event->trans_event);
2247 if (ret < 0)
2248 xhci->error_bitmask |= 1 << 9;
2249 else
2250 update_ptrs = 0;
2251 break;
Sarah Sharp7f84eef2009-04-27 19:53:56 -07002252 default:
Matt Evans28ccd292011-03-29 13:40:46 +11002253 if ((le32_to_cpu(event->event_cmd.flags) & TRB_TYPE_BITMASK) >=
2254 TRB_TYPE(48))
Sarah Sharp02386342010-05-24 13:25:28 -07002255 handle_vendor_event(xhci, event);
2256 else
2257 xhci->error_bitmask |= 1 << 3;
Sarah Sharp7f84eef2009-04-27 19:53:56 -07002258 }
Sarah Sharp6f5165c2009-10-27 10:57:01 -07002259 /* Any of the above functions may drop and re-acquire the lock, so check
2260 * to make sure a watchdog timer didn't mark the host as non-responsive.
2261 */
2262 if (xhci->xhc_state & XHCI_STATE_DYING) {
2263 xhci_dbg(xhci, "xHCI host dying, returning from "
2264 "event handler.\n");
Matt Evans9dee9a22011-03-29 13:41:02 +11002265 return 0;
Sarah Sharp6f5165c2009-10-27 10:57:01 -07002266 }
Sarah Sharp7f84eef2009-04-27 19:53:56 -07002267
Sarah Sharpc06d68b2010-07-29 22:12:49 -07002268 if (update_ptrs)
2269 /* Update SW event ring dequeue pointer */
Sarah Sharp0f2a7932009-04-27 19:57:12 -07002270 inc_deq(xhci, xhci->event_ring, true);
Sarah Sharpc06d68b2010-07-29 22:12:49 -07002271
Matt Evans9dee9a22011-03-29 13:41:02 +11002272 /* Are there more items on the event ring? Caller will call us again to
2273 * check.
2274 */
2275 return 1;
Sarah Sharp7f84eef2009-04-27 19:53:56 -07002276}
Sarah Sharp9032cd52010-07-29 22:12:29 -07002277
2278/*
2279 * xHCI spec says we can get an interrupt, and if the HC has an error condition,
2280 * we might get bad data out of the event ring. Section 4.10.2.7 has a list of
2281 * indicators of an event TRB error, but we check the status *first* to be safe.
2282 */
2283irqreturn_t xhci_irq(struct usb_hcd *hcd)
2284{
2285 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
Sarah Sharpc21599a2010-07-29 22:13:00 -07002286 u32 status;
Sarah Sharp9032cd52010-07-29 22:12:29 -07002287 union xhci_trb *trb;
Sarah Sharpbda53142010-07-29 22:12:38 -07002288 u64 temp_64;
Sarah Sharpc06d68b2010-07-29 22:12:49 -07002289 union xhci_trb *event_ring_deq;
2290 dma_addr_t deq;
Sarah Sharp9032cd52010-07-29 22:12:29 -07002291
2292 spin_lock(&xhci->lock);
2293 trb = xhci->event_ring->dequeue;
2294 /* Check if the xHC generated the interrupt, or the irq is shared */
Sarah Sharp27e0dd42010-07-29 22:12:43 -07002295 status = xhci_readl(xhci, &xhci->op_regs->status);
Sarah Sharpc21599a2010-07-29 22:13:00 -07002296 if (status == 0xffffffff)
Sarah Sharp9032cd52010-07-29 22:12:29 -07002297 goto hw_died;
2298
Sarah Sharpc21599a2010-07-29 22:13:00 -07002299 if (!(status & STS_EINT)) {
Sarah Sharp9032cd52010-07-29 22:12:29 -07002300 spin_unlock(&xhci->lock);
Sarah Sharp9032cd52010-07-29 22:12:29 -07002301 return IRQ_NONE;
2302 }
Sarah Sharp27e0dd42010-07-29 22:12:43 -07002303 if (status & STS_FATAL) {
Sarah Sharp9032cd52010-07-29 22:12:29 -07002304 xhci_warn(xhci, "WARNING: Host System Error\n");
2305 xhci_halt(xhci);
2306hw_died:
Sarah Sharp9032cd52010-07-29 22:12:29 -07002307 spin_unlock(&xhci->lock);
2308 return -ESHUTDOWN;
2309 }
2310
Sarah Sharpbda53142010-07-29 22:12:38 -07002311 /*
2312 * Clear the op reg interrupt status first,
2313 * so we can receive interrupts from other MSI-X interrupters.
2314 * Write 1 to clear the interrupt status.
2315 */
Sarah Sharp27e0dd42010-07-29 22:12:43 -07002316 status |= STS_EINT;
2317 xhci_writel(xhci, status, &xhci->op_regs->status);
Sarah Sharpbda53142010-07-29 22:12:38 -07002318 /* FIXME when MSI-X is supported and there are multiple vectors */
2319 /* Clear the MSI-X event interrupt status */
2320
Sarah Sharpc21599a2010-07-29 22:13:00 -07002321 if (hcd->irq != -1) {
2322 u32 irq_pending;
2323 /* Acknowledge the PCI interrupt */
2324 irq_pending = xhci_readl(xhci, &xhci->ir_set->irq_pending);
2325 irq_pending |= 0x3;
2326 xhci_writel(xhci, irq_pending, &xhci->ir_set->irq_pending);
2327 }
Sarah Sharpbda53142010-07-29 22:12:38 -07002328
Sarah Sharpc06d68b2010-07-29 22:12:49 -07002329 if (xhci->xhc_state & XHCI_STATE_DYING) {
Sarah Sharpbda53142010-07-29 22:12:38 -07002330 xhci_dbg(xhci, "xHCI dying, ignoring interrupt. "
2331 "Shouldn't IRQs be disabled?\n");
Sarah Sharpc06d68b2010-07-29 22:12:49 -07002332 /* Clear the event handler busy flag (RW1C);
2333 * the event ring should be empty.
Sarah Sharpbda53142010-07-29 22:12:38 -07002334 */
Sarah Sharpc06d68b2010-07-29 22:12:49 -07002335 temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
2336 xhci_write_64(xhci, temp_64 | ERST_EHB,
2337 &xhci->ir_set->erst_dequeue);
2338 spin_unlock(&xhci->lock);
2339
2340 return IRQ_HANDLED;
2341 }
2342
2343 event_ring_deq = xhci->event_ring->dequeue;
2344 /* FIXME this should be a delayed service routine
2345 * that clears the EHB.
2346 */
Matt Evans9dee9a22011-03-29 13:41:02 +11002347 while (xhci_handle_event(xhci) > 0) {}
Sarah Sharpc06d68b2010-07-29 22:12:49 -07002348
2349 temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
2350 /* If necessary, update the HW's version of the event ring deq ptr. */
2351 if (event_ring_deq != xhci->event_ring->dequeue) {
2352 deq = xhci_trb_virt_to_dma(xhci->event_ring->deq_seg,
2353 xhci->event_ring->dequeue);
2354 if (deq == 0)
2355 xhci_warn(xhci, "WARN something wrong with SW event "
2356 "ring dequeue ptr.\n");
2357 /* Update HC event ring dequeue pointer */
2358 temp_64 &= ERST_PTR_MASK;
2359 temp_64 |= ((u64) deq & (u64) ~ERST_PTR_MASK);
2360 }
Sarah Sharpbda53142010-07-29 22:12:38 -07002361
2362 /* Clear the event handler busy flag (RW1C); event ring is empty. */
Sarah Sharpc06d68b2010-07-29 22:12:49 -07002363 temp_64 |= ERST_EHB;
2364 xhci_write_64(xhci, temp_64, &xhci->ir_set->erst_dequeue);
2365
Sarah Sharp9032cd52010-07-29 22:12:29 -07002366 spin_unlock(&xhci->lock);
2367
2368 return IRQ_HANDLED;
2369}
2370
2371irqreturn_t xhci_msi_irq(int irq, struct usb_hcd *hcd)
2372{
2373 irqreturn_t ret;
Sarah Sharpb3209372011-03-07 11:24:07 -08002374 struct xhci_hcd *xhci;
Sarah Sharp9032cd52010-07-29 22:12:29 -07002375
Sarah Sharpb3209372011-03-07 11:24:07 -08002376 xhci = hcd_to_xhci(hcd);
Sarah Sharp9032cd52010-07-29 22:12:29 -07002377 set_bit(HCD_FLAG_SAW_IRQ, &hcd->flags);
Sarah Sharpb3209372011-03-07 11:24:07 -08002378 if (xhci->shared_hcd)
2379 set_bit(HCD_FLAG_SAW_IRQ, &xhci->shared_hcd->flags);
Sarah Sharp9032cd52010-07-29 22:12:29 -07002380
2381 ret = xhci_irq(hcd);
2382
2383 return ret;
2384}
Sarah Sharp7f84eef2009-04-27 19:53:56 -07002385
Sarah Sharpd0e96f52009-04-27 19:58:01 -07002386/**** Endpoint Ring Operations ****/
2387
Sarah Sharp7f84eef2009-04-27 19:53:56 -07002388/*
2389 * Generic function for queueing a TRB on a ring.
2390 * The caller must have checked to make sure there's room on the ring.
Sarah Sharp6cc30d82010-06-10 12:25:28 -07002391 *
2392 * @more_trbs_coming: Will you enqueue more TRBs before calling
2393 * prepare_transfer()?
Sarah Sharp7f84eef2009-04-27 19:53:56 -07002394 */
2395static void queue_trb(struct xhci_hcd *xhci, struct xhci_ring *ring,
Andiry Xu7e393a82011-09-23 14:19:54 -07002396 bool consumer, bool more_trbs_coming, bool isoc,
Sarah Sharp7f84eef2009-04-27 19:53:56 -07002397 u32 field1, u32 field2, u32 field3, u32 field4)
2398{
2399 struct xhci_generic_trb *trb;
2400
2401 trb = &ring->enqueue->generic;
Matt Evans28ccd292011-03-29 13:40:46 +11002402 trb->field[0] = cpu_to_le32(field1);
2403 trb->field[1] = cpu_to_le32(field2);
2404 trb->field[2] = cpu_to_le32(field3);
2405 trb->field[3] = cpu_to_le32(field4);
Andiry Xu7e393a82011-09-23 14:19:54 -07002406 inc_enq(xhci, ring, consumer, more_trbs_coming, isoc);
Sarah Sharp7f84eef2009-04-27 19:53:56 -07002407}
2408
Sarah Sharpd0e96f52009-04-27 19:58:01 -07002409/*
2410 * Does various checks on the endpoint ring, and makes it ready to queue num_trbs.
2411 * FIXME allocate segments if the ring is full.
2412 */
2413static int prepare_ring(struct xhci_hcd *xhci, struct xhci_ring *ep_ring,
Andiry Xu7e393a82011-09-23 14:19:54 -07002414 u32 ep_state, unsigned int num_trbs, bool isoc, gfp_t mem_flags)
Sarah Sharpd0e96f52009-04-27 19:58:01 -07002415{
2416 /* Make sure the endpoint has been added to xHC schedule */
Sarah Sharpd0e96f52009-04-27 19:58:01 -07002417 switch (ep_state) {
2418 case EP_STATE_DISABLED:
2419 /*
2420 * USB core changed config/interfaces without notifying us,
2421 * or hardware is reporting the wrong state.
2422 */
2423 xhci_warn(xhci, "WARN urb submitted to disabled ep\n");
2424 return -ENOENT;
Sarah Sharpd0e96f52009-04-27 19:58:01 -07002425 case EP_STATE_ERROR:
Sarah Sharpc92bcfa2009-07-27 12:05:21 -07002426 xhci_warn(xhci, "WARN waiting for error on ep to be cleared\n");
Sarah Sharpd0e96f52009-04-27 19:58:01 -07002427 /* FIXME event handling code for error needs to clear it */
2428 /* XXX not sure if this should be -ENOENT or not */
2429 return -EINVAL;
Sarah Sharpc92bcfa2009-07-27 12:05:21 -07002430 case EP_STATE_HALTED:
2431 xhci_dbg(xhci, "WARN halted endpoint, queueing URB anyway.\n");
Sarah Sharpd0e96f52009-04-27 19:58:01 -07002432 case EP_STATE_STOPPED:
2433 case EP_STATE_RUNNING:
2434 break;
2435 default:
2436 xhci_err(xhci, "ERROR unknown endpoint state for ep\n");
2437 /*
2438 * FIXME issue Configure Endpoint command to try to get the HC
2439 * back into a known state.
2440 */
2441 return -EINVAL;
2442 }
2443 if (!room_on_ring(xhci, ep_ring, num_trbs)) {
2444 /* FIXME allocate more room */
2445 xhci_err(xhci, "ERROR no room on ep ring\n");
2446 return -ENOMEM;
2447 }
John Youn6c12db92010-05-10 15:33:00 -07002448
2449 if (enqueue_is_link_trb(ep_ring)) {
2450 struct xhci_ring *ring = ep_ring;
2451 union xhci_trb *next;
John Youn6c12db92010-05-10 15:33:00 -07002452
John Youn6c12db92010-05-10 15:33:00 -07002453 next = ring->enqueue;
2454
2455 while (last_trb(xhci, ring, ring->enq_seg, next)) {
Andiry Xu7e393a82011-09-23 14:19:54 -07002456 /* If we're not dealing with 0.95 hardware or isoc rings
2457 * on AMD 0.96 host, clear the chain bit.
John Youn6c12db92010-05-10 15:33:00 -07002458 */
Andiry Xu7e393a82011-09-23 14:19:54 -07002459 if (!xhci_link_trb_quirk(xhci) && !(isoc &&
2460 (xhci->quirks & XHCI_AMD_0x96_HOST)))
Matt Evans28ccd292011-03-29 13:40:46 +11002461 next->link.control &= cpu_to_le32(~TRB_CHAIN);
John Youn6c12db92010-05-10 15:33:00 -07002462 else
Matt Evans28ccd292011-03-29 13:40:46 +11002463 next->link.control |= cpu_to_le32(TRB_CHAIN);
John Youn6c12db92010-05-10 15:33:00 -07002464
2465 wmb();
Matt Evansf5960b62011-06-01 10:22:55 +10002466 next->link.control ^= cpu_to_le32(TRB_CYCLE);
John Youn6c12db92010-05-10 15:33:00 -07002467
2468 /* Toggle the cycle bit after the last ring segment. */
2469 if (last_trb_on_last_seg(xhci, ring, ring->enq_seg, next)) {
2470 ring->cycle_state = (ring->cycle_state ? 0 : 1);
2471 if (!in_interrupt()) {
2472 xhci_dbg(xhci, "queue_trb: Toggle cycle "
2473 "state for ring %p = %i\n",
2474 ring, (unsigned int)ring->cycle_state);
2475 }
2476 }
2477 ring->enq_seg = ring->enq_seg->next;
2478 ring->enqueue = ring->enq_seg->trbs;
2479 next = ring->enqueue;
2480 }
2481 }
2482
Sarah Sharpd0e96f52009-04-27 19:58:01 -07002483 return 0;
2484}
2485
Sarah Sharp23e3be12009-04-29 19:05:20 -07002486static int prepare_transfer(struct xhci_hcd *xhci,
Sarah Sharpd0e96f52009-04-27 19:58:01 -07002487 struct xhci_virt_device *xdev,
2488 unsigned int ep_index,
Sarah Sharpe9df17e2010-04-02 15:34:43 -07002489 unsigned int stream_id,
Sarah Sharpd0e96f52009-04-27 19:58:01 -07002490 unsigned int num_trbs,
2491 struct urb *urb,
Andiry Xu8e51adc2010-07-22 15:23:31 -07002492 unsigned int td_index,
Andiry Xu7e393a82011-09-23 14:19:54 -07002493 bool isoc,
Sarah Sharpd0e96f52009-04-27 19:58:01 -07002494 gfp_t mem_flags)
2495{
2496 int ret;
Andiry Xu8e51adc2010-07-22 15:23:31 -07002497 struct urb_priv *urb_priv;
2498 struct xhci_td *td;
Sarah Sharpe9df17e2010-04-02 15:34:43 -07002499 struct xhci_ring *ep_ring;
John Yound115b042009-07-27 12:05:15 -07002500 struct xhci_ep_ctx *ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
Sarah Sharpe9df17e2010-04-02 15:34:43 -07002501
2502 ep_ring = xhci_stream_id_to_ring(xdev, ep_index, stream_id);
2503 if (!ep_ring) {
2504 xhci_dbg(xhci, "Can't prepare ring for bad stream ID %u\n",
2505 stream_id);
2506 return -EINVAL;
2507 }
2508
2509 ret = prepare_ring(xhci, ep_ring,
Matt Evans28ccd292011-03-29 13:40:46 +11002510 le32_to_cpu(ep_ctx->ep_info) & EP_STATE_MASK,
Andiry Xu7e393a82011-09-23 14:19:54 -07002511 num_trbs, isoc, mem_flags);
Sarah Sharpd0e96f52009-04-27 19:58:01 -07002512 if (ret)
2513 return ret;
Sarah Sharpd0e96f52009-04-27 19:58:01 -07002514
Andiry Xu8e51adc2010-07-22 15:23:31 -07002515 urb_priv = urb->hcpriv;
2516 td = urb_priv->td[td_index];
2517
2518 INIT_LIST_HEAD(&td->td_list);
2519 INIT_LIST_HEAD(&td->cancelled_td_list);
2520
2521 if (td_index == 0) {
Sarah Sharp214f76f2010-10-26 11:22:02 -07002522 ret = usb_hcd_link_urb_to_ep(bus_to_hcd(urb->dev->bus), urb);
Sarah Sharpd13565c2011-07-22 14:34:34 -07002523 if (unlikely(ret))
Andiry Xu8e51adc2010-07-22 15:23:31 -07002524 return ret;
Sarah Sharpd0e96f52009-04-27 19:58:01 -07002525 }
2526
Andiry Xu8e51adc2010-07-22 15:23:31 -07002527 td->urb = urb;
Sarah Sharpd0e96f52009-04-27 19:58:01 -07002528 /* Add this TD to the tail of the endpoint ring's TD list */
Andiry Xu8e51adc2010-07-22 15:23:31 -07002529 list_add_tail(&td->td_list, &ep_ring->td_list);
2530 td->start_seg = ep_ring->enq_seg;
2531 td->first_trb = ep_ring->enqueue;
2532
2533 urb_priv->td[td_index] = td;
Sarah Sharpd0e96f52009-04-27 19:58:01 -07002534
2535 return 0;
2536}
2537
Sarah Sharp23e3be12009-04-29 19:05:20 -07002538static unsigned int count_sg_trbs_needed(struct xhci_hcd *xhci, struct urb *urb)
Sarah Sharp8a96c052009-04-27 19:59:19 -07002539{
2540 int num_sgs, num_trbs, running_total, temp, i;
2541 struct scatterlist *sg;
2542
2543 sg = NULL;
2544 num_sgs = urb->num_sgs;
2545 temp = urb->transfer_buffer_length;
2546
2547 xhci_dbg(xhci, "count sg list trbs: \n");
2548 num_trbs = 0;
Matthew Wilcox910f8d02010-05-01 12:20:01 -06002549 for_each_sg(urb->sg, sg, num_sgs, i) {
Sarah Sharp8a96c052009-04-27 19:59:19 -07002550 unsigned int previous_total_trbs = num_trbs;
2551 unsigned int len = sg_dma_len(sg);
2552
2553 /* Scatter gather list entries may cross 64KB boundaries */
2554 running_total = TRB_MAX_BUFF_SIZE -
Paul Zimmermana2490182011-02-12 14:06:44 -08002555 (sg_dma_address(sg) & (TRB_MAX_BUFF_SIZE - 1));
Paul Zimmerman58077952011-02-12 14:07:20 -08002556 running_total &= TRB_MAX_BUFF_SIZE - 1;
Sarah Sharp8a96c052009-04-27 19:59:19 -07002557 if (running_total != 0)
2558 num_trbs++;
2559
2560 /* How many more 64KB chunks to transfer, how many more TRBs? */
Paul Zimmermanbcd2fde2011-02-12 14:07:57 -08002561 while (running_total < sg_dma_len(sg) && running_total < temp) {
Sarah Sharp8a96c052009-04-27 19:59:19 -07002562 num_trbs++;
2563 running_total += TRB_MAX_BUFF_SIZE;
2564 }
Greg Kroah-Hartman700e2052009-04-29 19:14:08 -07002565 xhci_dbg(xhci, " sg #%d: dma = %#llx, len = %#x (%d), num_trbs = %d\n",
2566 i, (unsigned long long)sg_dma_address(sg),
2567 len, len, num_trbs - previous_total_trbs);
Sarah Sharp8a96c052009-04-27 19:59:19 -07002568
2569 len = min_t(int, len, temp);
2570 temp -= len;
2571 if (temp == 0)
2572 break;
2573 }
2574 xhci_dbg(xhci, "\n");
2575 if (!in_interrupt())
Andiry Xuf2c565e2010-12-20 17:12:24 +08002576 xhci_dbg(xhci, "ep %#x - urb len = %d, sglist used, "
2577 "num_trbs = %d\n",
Sarah Sharp8a96c052009-04-27 19:59:19 -07002578 urb->ep->desc.bEndpointAddress,
2579 urb->transfer_buffer_length,
2580 num_trbs);
2581 return num_trbs;
2582}
2583
Sarah Sharp23e3be12009-04-29 19:05:20 -07002584static void check_trb_math(struct urb *urb, int num_trbs, int running_total)
Sarah Sharp8a96c052009-04-27 19:59:19 -07002585{
2586 if (num_trbs != 0)
Paul Zimmermana2490182011-02-12 14:06:44 -08002587 dev_err(&urb->dev->dev, "%s - ep %#x - Miscalculated number of "
Sarah Sharp8a96c052009-04-27 19:59:19 -07002588 "TRBs, %d left\n", __func__,
2589 urb->ep->desc.bEndpointAddress, num_trbs);
2590 if (running_total != urb->transfer_buffer_length)
Paul Zimmermana2490182011-02-12 14:06:44 -08002591 dev_err(&urb->dev->dev, "%s - ep %#x - Miscalculated tx length, "
Sarah Sharp8a96c052009-04-27 19:59:19 -07002592 "queued %#x (%d), asked for %#x (%d)\n",
2593 __func__,
2594 urb->ep->desc.bEndpointAddress,
2595 running_total, running_total,
2596 urb->transfer_buffer_length,
2597 urb->transfer_buffer_length);
2598}
2599
Sarah Sharp23e3be12009-04-29 19:05:20 -07002600static void giveback_first_trb(struct xhci_hcd *xhci, int slot_id,
Sarah Sharpe9df17e2010-04-02 15:34:43 -07002601 unsigned int ep_index, unsigned int stream_id, int start_cycle,
Andiry Xue1eab2e2011-01-04 16:30:39 -08002602 struct xhci_generic_trb *start_trb)
Sarah Sharp8a96c052009-04-27 19:59:19 -07002603{
Sarah Sharp8a96c052009-04-27 19:59:19 -07002604 /*
2605 * Pass all the TRBs to the hardware at once and make sure this write
2606 * isn't reordered.
2607 */
2608 wmb();
Andiry Xu50f7b522010-12-20 15:09:34 +08002609 if (start_cycle)
Matt Evans28ccd292011-03-29 13:40:46 +11002610 start_trb->field[3] |= cpu_to_le32(start_cycle);
Andiry Xu50f7b522010-12-20 15:09:34 +08002611 else
Matt Evans28ccd292011-03-29 13:40:46 +11002612 start_trb->field[3] &= cpu_to_le32(~TRB_CYCLE);
Andiry Xube88fe42010-10-14 07:22:57 -07002613 xhci_ring_ep_doorbell(xhci, slot_id, ep_index, stream_id);
Sarah Sharp8a96c052009-04-27 19:59:19 -07002614}
2615
Sarah Sharp624defa2009-09-02 12:14:28 -07002616/*
2617 * xHCI uses normal TRBs for both bulk and interrupt. When the interrupt
2618 * endpoint is to be serviced, the xHC will consume (at most) one TD. A TD
2619 * (comprised of sg list entries) can take several service intervals to
2620 * transmit.
2621 */
2622int xhci_queue_intr_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
2623 struct urb *urb, int slot_id, unsigned int ep_index)
2624{
2625 struct xhci_ep_ctx *ep_ctx = xhci_get_ep_ctx(xhci,
2626 xhci->devs[slot_id]->out_ctx, ep_index);
2627 int xhci_interval;
2628 int ep_interval;
2629
Matt Evans28ccd292011-03-29 13:40:46 +11002630 xhci_interval = EP_INTERVAL_TO_UFRAMES(le32_to_cpu(ep_ctx->ep_info));
Sarah Sharp624defa2009-09-02 12:14:28 -07002631 ep_interval = urb->interval;
2632 /* Convert to microframes */
2633 if (urb->dev->speed == USB_SPEED_LOW ||
2634 urb->dev->speed == USB_SPEED_FULL)
2635 ep_interval *= 8;
2636 /* FIXME change this to a warning and a suggestion to use the new API
2637 * to set the polling interval (once the API is added).
2638 */
2639 if (xhci_interval != ep_interval) {
Andiry Xu7961acd2010-12-20 17:14:20 +08002640 if (printk_ratelimit())
Sarah Sharp624defa2009-09-02 12:14:28 -07002641 dev_dbg(&urb->dev->dev, "Driver uses different interval"
2642 " (%d microframe%s) than xHCI "
2643 "(%d microframe%s)\n",
2644 ep_interval,
2645 ep_interval == 1 ? "" : "s",
2646 xhci_interval,
2647 xhci_interval == 1 ? "" : "s");
2648 urb->interval = xhci_interval;
2649 /* Convert back to frames for LS/FS devices */
2650 if (urb->dev->speed == USB_SPEED_LOW ||
2651 urb->dev->speed == USB_SPEED_FULL)
2652 urb->interval /= 8;
2653 }
2654 return xhci_queue_bulk_tx(xhci, GFP_ATOMIC, urb, slot_id, ep_index);
2655}
2656
Sarah Sharp04dd9502009-11-11 10:28:30 -08002657/*
2658 * The TD size is the number of bytes remaining in the TD (including this TRB),
2659 * right shifted by 10.
2660 * It must fit in bits 21:17, so it can't be bigger than 31.
2661 */
2662static u32 xhci_td_remainder(unsigned int remainder)
2663{
2664 u32 max = (1 << (21 - 17 + 1)) - 1;
2665
2666 if ((remainder >> 10) >= max)
2667 return max << 17;
2668 else
2669 return (remainder >> 10) << 17;
2670}
2671
Sarah Sharp4da6e6f2011-04-01 14:01:30 -07002672/*
2673 * For xHCI 1.0 host controllers, TD size is the number of packets remaining in
2674 * the TD (*not* including this TRB).
2675 *
2676 * Total TD packet count = total_packet_count =
2677 * roundup(TD size in bytes / wMaxPacketSize)
2678 *
2679 * Packets transferred up to and including this TRB = packets_transferred =
2680 * rounddown(total bytes transferred including this TRB / wMaxPacketSize)
2681 *
2682 * TD size = total_packet_count - packets_transferred
2683 *
2684 * It must fit in bits 21:17, so it can't be bigger than 31.
2685 */
2686
2687static u32 xhci_v1_0_td_remainder(int running_total, int trb_buff_len,
2688 unsigned int total_packet_count, struct urb *urb)
2689{
2690 int packets_transferred;
2691
Sarah Sharp48df4a62011-08-12 10:23:01 -07002692 /* One TRB with a zero-length data packet. */
2693 if (running_total == 0 && trb_buff_len == 0)
2694 return 0;
2695
Sarah Sharp4da6e6f2011-04-01 14:01:30 -07002696 /* All the TRB queueing functions don't count the current TRB in
2697 * running_total.
2698 */
2699 packets_transferred = (running_total + trb_buff_len) /
Kuninori Morimoto29cc8892011-08-23 03:12:03 -07002700 usb_endpoint_maxp(&urb->ep->desc);
Sarah Sharp4da6e6f2011-04-01 14:01:30 -07002701
2702 return xhci_td_remainder(total_packet_count - packets_transferred);
2703}
2704
Sarah Sharp23e3be12009-04-29 19:05:20 -07002705static int queue_bulk_sg_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
Sarah Sharp8a96c052009-04-27 19:59:19 -07002706 struct urb *urb, int slot_id, unsigned int ep_index)
2707{
2708 struct xhci_ring *ep_ring;
2709 unsigned int num_trbs;
Andiry Xu8e51adc2010-07-22 15:23:31 -07002710 struct urb_priv *urb_priv;
Sarah Sharp8a96c052009-04-27 19:59:19 -07002711 struct xhci_td *td;
2712 struct scatterlist *sg;
2713 int num_sgs;
2714 int trb_buff_len, this_sg_len, running_total;
Sarah Sharp4da6e6f2011-04-01 14:01:30 -07002715 unsigned int total_packet_count;
Sarah Sharp8a96c052009-04-27 19:59:19 -07002716 bool first_trb;
2717 u64 addr;
Sarah Sharp6cc30d82010-06-10 12:25:28 -07002718 bool more_trbs_coming;
Sarah Sharp8a96c052009-04-27 19:59:19 -07002719
2720 struct xhci_generic_trb *start_trb;
2721 int start_cycle;
2722
Sarah Sharpe9df17e2010-04-02 15:34:43 -07002723 ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
2724 if (!ep_ring)
2725 return -EINVAL;
2726
Sarah Sharp8a96c052009-04-27 19:59:19 -07002727 num_trbs = count_sg_trbs_needed(xhci, urb);
2728 num_sgs = urb->num_sgs;
Sarah Sharp4da6e6f2011-04-01 14:01:30 -07002729 total_packet_count = roundup(urb->transfer_buffer_length,
Kuninori Morimoto29cc8892011-08-23 03:12:03 -07002730 usb_endpoint_maxp(&urb->ep->desc));
Sarah Sharp8a96c052009-04-27 19:59:19 -07002731
Sarah Sharp23e3be12009-04-29 19:05:20 -07002732 trb_buff_len = prepare_transfer(xhci, xhci->devs[slot_id],
Sarah Sharpe9df17e2010-04-02 15:34:43 -07002733 ep_index, urb->stream_id,
Andiry Xu7e393a82011-09-23 14:19:54 -07002734 num_trbs, urb, 0, false, mem_flags);
Sarah Sharp8a96c052009-04-27 19:59:19 -07002735 if (trb_buff_len < 0)
2736 return trb_buff_len;
Andiry Xu8e51adc2010-07-22 15:23:31 -07002737
2738 urb_priv = urb->hcpriv;
2739 td = urb_priv->td[0];
2740
Sarah Sharp8a96c052009-04-27 19:59:19 -07002741 /*
2742 * Don't give the first TRB to the hardware (by toggling the cycle bit)
2743 * until we've finished creating all the other TRBs. The ring's cycle
2744 * state may change as we enqueue the other TRBs, so save it too.
2745 */
2746 start_trb = &ep_ring->enqueue->generic;
2747 start_cycle = ep_ring->cycle_state;
2748
2749 running_total = 0;
2750 /*
2751 * How much data is in the first TRB?
2752 *
2753 * There are three forces at work for TRB buffer pointers and lengths:
2754 * 1. We don't want to walk off the end of this sg-list entry buffer.
2755 * 2. The transfer length that the driver requested may be smaller than
2756 * the amount of memory allocated for this scatter-gather list.
2757 * 3. TRBs buffers can't cross 64KB boundaries.
2758 */
Matthew Wilcox910f8d02010-05-01 12:20:01 -06002759 sg = urb->sg;
Sarah Sharp8a96c052009-04-27 19:59:19 -07002760 addr = (u64) sg_dma_address(sg);
2761 this_sg_len = sg_dma_len(sg);
Paul Zimmermana2490182011-02-12 14:06:44 -08002762 trb_buff_len = TRB_MAX_BUFF_SIZE - (addr & (TRB_MAX_BUFF_SIZE - 1));
Sarah Sharp8a96c052009-04-27 19:59:19 -07002763 trb_buff_len = min_t(int, trb_buff_len, this_sg_len);
2764 if (trb_buff_len > urb->transfer_buffer_length)
2765 trb_buff_len = urb->transfer_buffer_length;
2766 xhci_dbg(xhci, "First length to xfer from 1st sglist entry = %u\n",
2767 trb_buff_len);
2768
2769 first_trb = true;
2770 /* Queue the first TRB, even if it's zero-length */
2771 do {
2772 u32 field = 0;
Sarah Sharpf9dc68f2009-07-27 12:03:07 -07002773 u32 length_field = 0;
Sarah Sharp04dd9502009-11-11 10:28:30 -08002774 u32 remainder = 0;
Sarah Sharp8a96c052009-04-27 19:59:19 -07002775
2776 /* Don't change the cycle bit of the first TRB until later */
Andiry Xu50f7b522010-12-20 15:09:34 +08002777 if (first_trb) {
Sarah Sharp8a96c052009-04-27 19:59:19 -07002778 first_trb = false;
Andiry Xu50f7b522010-12-20 15:09:34 +08002779 if (start_cycle == 0)
2780 field |= 0x1;
2781 } else
Sarah Sharp8a96c052009-04-27 19:59:19 -07002782 field |= ep_ring->cycle_state;
2783
2784 /* Chain all the TRBs together; clear the chain bit in the last
2785 * TRB to indicate it's the last TRB in the chain.
2786 */
2787 if (num_trbs > 1) {
2788 field |= TRB_CHAIN;
2789 } else {
2790 /* FIXME - add check for ZERO_PACKET flag before this */
2791 td->last_trb = ep_ring->enqueue;
2792 field |= TRB_IOC;
2793 }
Sarah Sharpaf8b9e62011-03-23 16:26:26 -07002794
2795 /* Only set interrupt on short packet for IN endpoints */
2796 if (usb_urb_dir_in(urb))
2797 field |= TRB_ISP;
2798
Sarah Sharp8a96c052009-04-27 19:59:19 -07002799 xhci_dbg(xhci, " sg entry: dma = %#x, len = %#x (%d), "
2800 "64KB boundary at %#x, end dma = %#x\n",
2801 (unsigned int) addr, trb_buff_len, trb_buff_len,
2802 (unsigned int) (addr + TRB_MAX_BUFF_SIZE) & ~(TRB_MAX_BUFF_SIZE - 1),
2803 (unsigned int) addr + trb_buff_len);
2804 if (TRB_MAX_BUFF_SIZE -
Paul Zimmermana2490182011-02-12 14:06:44 -08002805 (addr & (TRB_MAX_BUFF_SIZE - 1)) < trb_buff_len) {
Sarah Sharp8a96c052009-04-27 19:59:19 -07002806 xhci_warn(xhci, "WARN: sg dma xfer crosses 64KB boundaries!\n");
2807 xhci_dbg(xhci, "Next boundary at %#x, end dma = %#x\n",
2808 (unsigned int) (addr + TRB_MAX_BUFF_SIZE) & ~(TRB_MAX_BUFF_SIZE - 1),
2809 (unsigned int) addr + trb_buff_len);
2810 }
Sarah Sharp4da6e6f2011-04-01 14:01:30 -07002811
2812 /* Set the TRB length, TD size, and interrupter fields. */
2813 if (xhci->hci_version < 0x100) {
2814 remainder = xhci_td_remainder(
2815 urb->transfer_buffer_length -
2816 running_total);
2817 } else {
2818 remainder = xhci_v1_0_td_remainder(running_total,
2819 trb_buff_len, total_packet_count, urb);
2820 }
Sarah Sharpf9dc68f2009-07-27 12:03:07 -07002821 length_field = TRB_LEN(trb_buff_len) |
Sarah Sharp04dd9502009-11-11 10:28:30 -08002822 remainder |
Sarah Sharpf9dc68f2009-07-27 12:03:07 -07002823 TRB_INTR_TARGET(0);
Sarah Sharp4da6e6f2011-04-01 14:01:30 -07002824
Sarah Sharp6cc30d82010-06-10 12:25:28 -07002825 if (num_trbs > 1)
2826 more_trbs_coming = true;
2827 else
2828 more_trbs_coming = false;
Andiry Xu7e393a82011-09-23 14:19:54 -07002829 queue_trb(xhci, ep_ring, false, more_trbs_coming, false,
Sarah Sharp8e595a52009-07-27 12:03:31 -07002830 lower_32_bits(addr),
2831 upper_32_bits(addr),
Sarah Sharpf9dc68f2009-07-27 12:03:07 -07002832 length_field,
Sarah Sharpaf8b9e62011-03-23 16:26:26 -07002833 field | TRB_TYPE(TRB_NORMAL));
Sarah Sharp8a96c052009-04-27 19:59:19 -07002834 --num_trbs;
2835 running_total += trb_buff_len;
2836
2837 /* Calculate length for next transfer --
2838 * Are we done queueing all the TRBs for this sg entry?
2839 */
2840 this_sg_len -= trb_buff_len;
2841 if (this_sg_len == 0) {
2842 --num_sgs;
2843 if (num_sgs == 0)
2844 break;
2845 sg = sg_next(sg);
2846 addr = (u64) sg_dma_address(sg);
2847 this_sg_len = sg_dma_len(sg);
2848 } else {
2849 addr += trb_buff_len;
2850 }
2851
2852 trb_buff_len = TRB_MAX_BUFF_SIZE -
Paul Zimmermana2490182011-02-12 14:06:44 -08002853 (addr & (TRB_MAX_BUFF_SIZE - 1));
Sarah Sharp8a96c052009-04-27 19:59:19 -07002854 trb_buff_len = min_t(int, trb_buff_len, this_sg_len);
2855 if (running_total + trb_buff_len > urb->transfer_buffer_length)
2856 trb_buff_len =
2857 urb->transfer_buffer_length - running_total;
2858 } while (running_total < urb->transfer_buffer_length);
2859
2860 check_trb_math(urb, num_trbs, running_total);
Sarah Sharpe9df17e2010-04-02 15:34:43 -07002861 giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id,
Andiry Xue1eab2e2011-01-04 16:30:39 -08002862 start_cycle, start_trb);
Sarah Sharp8a96c052009-04-27 19:59:19 -07002863 return 0;
2864}
2865
Sarah Sharpb10de142009-04-27 19:58:50 -07002866/* This is very similar to what ehci-q.c qtd_fill() does */
Sarah Sharp23e3be12009-04-29 19:05:20 -07002867int xhci_queue_bulk_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
Sarah Sharpb10de142009-04-27 19:58:50 -07002868 struct urb *urb, int slot_id, unsigned int ep_index)
2869{
2870 struct xhci_ring *ep_ring;
Andiry Xu8e51adc2010-07-22 15:23:31 -07002871 struct urb_priv *urb_priv;
Sarah Sharpb10de142009-04-27 19:58:50 -07002872 struct xhci_td *td;
2873 int num_trbs;
2874 struct xhci_generic_trb *start_trb;
2875 bool first_trb;
Sarah Sharp6cc30d82010-06-10 12:25:28 -07002876 bool more_trbs_coming;
Sarah Sharpb10de142009-04-27 19:58:50 -07002877 int start_cycle;
Sarah Sharpf9dc68f2009-07-27 12:03:07 -07002878 u32 field, length_field;
Sarah Sharpb10de142009-04-27 19:58:50 -07002879
2880 int running_total, trb_buff_len, ret;
Sarah Sharp4da6e6f2011-04-01 14:01:30 -07002881 unsigned int total_packet_count;
Sarah Sharpb10de142009-04-27 19:58:50 -07002882 u64 addr;
2883
Alan Sternff9c8952010-04-02 13:27:28 -04002884 if (urb->num_sgs)
Sarah Sharp8a96c052009-04-27 19:59:19 -07002885 return queue_bulk_sg_tx(xhci, mem_flags, urb, slot_id, ep_index);
2886
Sarah Sharpe9df17e2010-04-02 15:34:43 -07002887 ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
2888 if (!ep_ring)
2889 return -EINVAL;
Sarah Sharpb10de142009-04-27 19:58:50 -07002890
2891 num_trbs = 0;
2892 /* How much data is (potentially) left before the 64KB boundary? */
2893 running_total = TRB_MAX_BUFF_SIZE -
Paul Zimmermana2490182011-02-12 14:06:44 -08002894 (urb->transfer_dma & (TRB_MAX_BUFF_SIZE - 1));
Paul Zimmerman58077952011-02-12 14:07:20 -08002895 running_total &= TRB_MAX_BUFF_SIZE - 1;
Sarah Sharpb10de142009-04-27 19:58:50 -07002896
2897 /* If there's some data on this 64KB chunk, or we have to send a
2898 * zero-length transfer, we need at least one TRB
2899 */
2900 if (running_total != 0 || urb->transfer_buffer_length == 0)
2901 num_trbs++;
2902 /* How many more 64KB chunks to transfer, how many more TRBs? */
2903 while (running_total < urb->transfer_buffer_length) {
2904 num_trbs++;
2905 running_total += TRB_MAX_BUFF_SIZE;
2906 }
2907 /* FIXME: this doesn't deal with URB_ZERO_PACKET - need one more */
2908
2909 if (!in_interrupt())
Andiry Xuf2c565e2010-12-20 17:12:24 +08002910 xhci_dbg(xhci, "ep %#x - urb len = %#x (%d), "
2911 "addr = %#llx, num_trbs = %d\n",
Sarah Sharpb10de142009-04-27 19:58:50 -07002912 urb->ep->desc.bEndpointAddress,
Sarah Sharp8a96c052009-04-27 19:59:19 -07002913 urb->transfer_buffer_length,
2914 urb->transfer_buffer_length,
Greg Kroah-Hartman700e2052009-04-29 19:14:08 -07002915 (unsigned long long)urb->transfer_dma,
Sarah Sharpb10de142009-04-27 19:58:50 -07002916 num_trbs);
Sarah Sharp8a96c052009-04-27 19:59:19 -07002917
Sarah Sharpe9df17e2010-04-02 15:34:43 -07002918 ret = prepare_transfer(xhci, xhci->devs[slot_id],
2919 ep_index, urb->stream_id,
Andiry Xu7e393a82011-09-23 14:19:54 -07002920 num_trbs, urb, 0, false, mem_flags);
Sarah Sharpb10de142009-04-27 19:58:50 -07002921 if (ret < 0)
2922 return ret;
2923
Andiry Xu8e51adc2010-07-22 15:23:31 -07002924 urb_priv = urb->hcpriv;
2925 td = urb_priv->td[0];
2926
Sarah Sharpb10de142009-04-27 19:58:50 -07002927 /*
2928 * Don't give the first TRB to the hardware (by toggling the cycle bit)
2929 * until we've finished creating all the other TRBs. The ring's cycle
2930 * state may change as we enqueue the other TRBs, so save it too.
2931 */
2932 start_trb = &ep_ring->enqueue->generic;
2933 start_cycle = ep_ring->cycle_state;
2934
2935 running_total = 0;
Sarah Sharp4da6e6f2011-04-01 14:01:30 -07002936 total_packet_count = roundup(urb->transfer_buffer_length,
Kuninori Morimoto29cc8892011-08-23 03:12:03 -07002937 usb_endpoint_maxp(&urb->ep->desc));
Sarah Sharpb10de142009-04-27 19:58:50 -07002938 /* How much data is in the first TRB? */
2939 addr = (u64) urb->transfer_dma;
2940 trb_buff_len = TRB_MAX_BUFF_SIZE -
Paul Zimmermana2490182011-02-12 14:06:44 -08002941 (urb->transfer_dma & (TRB_MAX_BUFF_SIZE - 1));
2942 if (trb_buff_len > urb->transfer_buffer_length)
Sarah Sharpb10de142009-04-27 19:58:50 -07002943 trb_buff_len = urb->transfer_buffer_length;
2944
2945 first_trb = true;
2946
2947 /* Queue the first TRB, even if it's zero-length */
2948 do {
Sarah Sharp04dd9502009-11-11 10:28:30 -08002949 u32 remainder = 0;
Sarah Sharpb10de142009-04-27 19:58:50 -07002950 field = 0;
2951
2952 /* Don't change the cycle bit of the first TRB until later */
Andiry Xu50f7b522010-12-20 15:09:34 +08002953 if (first_trb) {
Sarah Sharpb10de142009-04-27 19:58:50 -07002954 first_trb = false;
Andiry Xu50f7b522010-12-20 15:09:34 +08002955 if (start_cycle == 0)
2956 field |= 0x1;
2957 } else
Sarah Sharpb10de142009-04-27 19:58:50 -07002958 field |= ep_ring->cycle_state;
2959
2960 /* Chain all the TRBs together; clear the chain bit in the last
2961 * TRB to indicate it's the last TRB in the chain.
2962 */
2963 if (num_trbs > 1) {
2964 field |= TRB_CHAIN;
2965 } else {
2966 /* FIXME - add check for ZERO_PACKET flag before this */
2967 td->last_trb = ep_ring->enqueue;
2968 field |= TRB_IOC;
2969 }
Sarah Sharpaf8b9e62011-03-23 16:26:26 -07002970
2971 /* Only set interrupt on short packet for IN endpoints */
2972 if (usb_urb_dir_in(urb))
2973 field |= TRB_ISP;
2974
Sarah Sharp4da6e6f2011-04-01 14:01:30 -07002975 /* Set the TRB length, TD size, and interrupter fields. */
2976 if (xhci->hci_version < 0x100) {
2977 remainder = xhci_td_remainder(
2978 urb->transfer_buffer_length -
2979 running_total);
2980 } else {
2981 remainder = xhci_v1_0_td_remainder(running_total,
2982 trb_buff_len, total_packet_count, urb);
2983 }
Sarah Sharpf9dc68f2009-07-27 12:03:07 -07002984 length_field = TRB_LEN(trb_buff_len) |
Sarah Sharp04dd9502009-11-11 10:28:30 -08002985 remainder |
Sarah Sharpf9dc68f2009-07-27 12:03:07 -07002986 TRB_INTR_TARGET(0);
Sarah Sharp4da6e6f2011-04-01 14:01:30 -07002987
Sarah Sharp6cc30d82010-06-10 12:25:28 -07002988 if (num_trbs > 1)
2989 more_trbs_coming = true;
2990 else
2991 more_trbs_coming = false;
Andiry Xu7e393a82011-09-23 14:19:54 -07002992 queue_trb(xhci, ep_ring, false, more_trbs_coming, false,
Sarah Sharp8e595a52009-07-27 12:03:31 -07002993 lower_32_bits(addr),
2994 upper_32_bits(addr),
Sarah Sharpf9dc68f2009-07-27 12:03:07 -07002995 length_field,
Sarah Sharpaf8b9e62011-03-23 16:26:26 -07002996 field | TRB_TYPE(TRB_NORMAL));
Sarah Sharpb10de142009-04-27 19:58:50 -07002997 --num_trbs;
2998 running_total += trb_buff_len;
2999
3000 /* Calculate length for next transfer */
3001 addr += trb_buff_len;
3002 trb_buff_len = urb->transfer_buffer_length - running_total;
3003 if (trb_buff_len > TRB_MAX_BUFF_SIZE)
3004 trb_buff_len = TRB_MAX_BUFF_SIZE;
3005 } while (running_total < urb->transfer_buffer_length);
3006
Sarah Sharp8a96c052009-04-27 19:59:19 -07003007 check_trb_math(urb, num_trbs, running_total);
Sarah Sharpe9df17e2010-04-02 15:34:43 -07003008 giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id,
Andiry Xue1eab2e2011-01-04 16:30:39 -08003009 start_cycle, start_trb);
Sarah Sharpb10de142009-04-27 19:58:50 -07003010 return 0;
3011}
3012
Sarah Sharpd0e96f52009-04-27 19:58:01 -07003013/* Caller must have locked xhci->lock */
Sarah Sharp23e3be12009-04-29 19:05:20 -07003014int xhci_queue_ctrl_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
Sarah Sharpd0e96f52009-04-27 19:58:01 -07003015 struct urb *urb, int slot_id, unsigned int ep_index)
3016{
3017 struct xhci_ring *ep_ring;
3018 int num_trbs;
3019 int ret;
3020 struct usb_ctrlrequest *setup;
3021 struct xhci_generic_trb *start_trb;
3022 int start_cycle;
Sarah Sharpf9dc68f2009-07-27 12:03:07 -07003023 u32 field, length_field;
Andiry Xu8e51adc2010-07-22 15:23:31 -07003024 struct urb_priv *urb_priv;
Sarah Sharpd0e96f52009-04-27 19:58:01 -07003025 struct xhci_td *td;
3026
Sarah Sharpe9df17e2010-04-02 15:34:43 -07003027 ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
3028 if (!ep_ring)
3029 return -EINVAL;
Sarah Sharpd0e96f52009-04-27 19:58:01 -07003030
3031 /*
3032 * Need to copy setup packet into setup TRB, so we can't use the setup
3033 * DMA address.
3034 */
3035 if (!urb->setup_packet)
3036 return -EINVAL;
3037
3038 if (!in_interrupt())
3039 xhci_dbg(xhci, "Queueing ctrl tx for slot id %d, ep %d\n",
3040 slot_id, ep_index);
3041 /* 1 TRB for setup, 1 for status */
3042 num_trbs = 2;
3043 /*
3044 * Don't need to check if we need additional event data and normal TRBs,
3045 * since data in control transfers will never get bigger than 16MB
3046 * XXX: can we get a buffer that crosses 64KB boundaries?
3047 */
3048 if (urb->transfer_buffer_length > 0)
3049 num_trbs++;
Sarah Sharpe9df17e2010-04-02 15:34:43 -07003050 ret = prepare_transfer(xhci, xhci->devs[slot_id],
3051 ep_index, urb->stream_id,
Andiry Xu7e393a82011-09-23 14:19:54 -07003052 num_trbs, urb, 0, false, mem_flags);
Sarah Sharpd0e96f52009-04-27 19:58:01 -07003053 if (ret < 0)
3054 return ret;
3055
Andiry Xu8e51adc2010-07-22 15:23:31 -07003056 urb_priv = urb->hcpriv;
3057 td = urb_priv->td[0];
3058
Sarah Sharpd0e96f52009-04-27 19:58:01 -07003059 /*
3060 * Don't give the first TRB to the hardware (by toggling the cycle bit)
3061 * until we've finished creating all the other TRBs. The ring's cycle
3062 * state may change as we enqueue the other TRBs, so save it too.
3063 */
3064 start_trb = &ep_ring->enqueue->generic;
3065 start_cycle = ep_ring->cycle_state;
3066
3067 /* Queue setup TRB - see section 6.4.1.2.1 */
3068 /* FIXME better way to translate setup_packet into two u32 fields? */
3069 setup = (struct usb_ctrlrequest *) urb->setup_packet;
Andiry Xu50f7b522010-12-20 15:09:34 +08003070 field = 0;
3071 field |= TRB_IDT | TRB_TYPE(TRB_SETUP);
3072 if (start_cycle == 0)
3073 field |= 0x1;
Andiry Xub83cdc82011-05-05 18:13:56 +08003074
3075 /* xHCI 1.0 6.4.1.2.1: Transfer Type field */
3076 if (xhci->hci_version == 0x100) {
3077 if (urb->transfer_buffer_length > 0) {
3078 if (setup->bRequestType & USB_DIR_IN)
3079 field |= TRB_TX_TYPE(TRB_DATA_IN);
3080 else
3081 field |= TRB_TX_TYPE(TRB_DATA_OUT);
3082 }
3083 }
3084
Andiry Xu7e393a82011-09-23 14:19:54 -07003085 queue_trb(xhci, ep_ring, false, true, false,
Matt Evans28ccd292011-03-29 13:40:46 +11003086 setup->bRequestType | setup->bRequest << 8 | le16_to_cpu(setup->wValue) << 16,
3087 le16_to_cpu(setup->wIndex) | le16_to_cpu(setup->wLength) << 16,
3088 TRB_LEN(8) | TRB_INTR_TARGET(0),
3089 /* Immediate data in pointer */
3090 field);
Sarah Sharpd0e96f52009-04-27 19:58:01 -07003091
3092 /* If there's data, queue data TRBs */
Sarah Sharpaf8b9e62011-03-23 16:26:26 -07003093 /* Only set interrupt on short packet for IN endpoints */
3094 if (usb_urb_dir_in(urb))
3095 field = TRB_ISP | TRB_TYPE(TRB_DATA);
3096 else
3097 field = TRB_TYPE(TRB_DATA);
3098
Sarah Sharpf9dc68f2009-07-27 12:03:07 -07003099 length_field = TRB_LEN(urb->transfer_buffer_length) |
Sarah Sharp04dd9502009-11-11 10:28:30 -08003100 xhci_td_remainder(urb->transfer_buffer_length) |
Sarah Sharpf9dc68f2009-07-27 12:03:07 -07003101 TRB_INTR_TARGET(0);
Sarah Sharpd0e96f52009-04-27 19:58:01 -07003102 if (urb->transfer_buffer_length > 0) {
3103 if (setup->bRequestType & USB_DIR_IN)
3104 field |= TRB_DIR_IN;
Andiry Xu7e393a82011-09-23 14:19:54 -07003105 queue_trb(xhci, ep_ring, false, true, false,
Sarah Sharpd0e96f52009-04-27 19:58:01 -07003106 lower_32_bits(urb->transfer_dma),
3107 upper_32_bits(urb->transfer_dma),
Sarah Sharpf9dc68f2009-07-27 12:03:07 -07003108 length_field,
Sarah Sharpaf8b9e62011-03-23 16:26:26 -07003109 field | ep_ring->cycle_state);
Sarah Sharpd0e96f52009-04-27 19:58:01 -07003110 }
3111
3112 /* Save the DMA address of the last TRB in the TD */
3113 td->last_trb = ep_ring->enqueue;
3114
3115 /* Queue status TRB - see Table 7 and sections 4.11.2.2 and 6.4.1.2.3 */
3116 /* If the device sent data, the status stage is an OUT transfer */
3117 if (urb->transfer_buffer_length > 0 && setup->bRequestType & USB_DIR_IN)
3118 field = 0;
3119 else
3120 field = TRB_DIR_IN;
Andiry Xu7e393a82011-09-23 14:19:54 -07003121 queue_trb(xhci, ep_ring, false, false, false,
Sarah Sharpd0e96f52009-04-27 19:58:01 -07003122 0,
3123 0,
3124 TRB_INTR_TARGET(0),
3125 /* Event on completion */
3126 field | TRB_IOC | TRB_TYPE(TRB_STATUS) | ep_ring->cycle_state);
3127
Sarah Sharpe9df17e2010-04-02 15:34:43 -07003128 giveback_first_trb(xhci, slot_id, ep_index, 0,
Andiry Xue1eab2e2011-01-04 16:30:39 -08003129 start_cycle, start_trb);
Sarah Sharpd0e96f52009-04-27 19:58:01 -07003130 return 0;
3131}
3132
Andiry Xu04e51902010-07-22 15:23:39 -07003133static int count_isoc_trbs_needed(struct xhci_hcd *xhci,
3134 struct urb *urb, int i)
3135{
3136 int num_trbs = 0;
Sarah Sharp48df4a62011-08-12 10:23:01 -07003137 u64 addr, td_len;
Andiry Xu04e51902010-07-22 15:23:39 -07003138
3139 addr = (u64) (urb->transfer_dma + urb->iso_frame_desc[i].offset);
3140 td_len = urb->iso_frame_desc[i].length;
3141
Sarah Sharp48df4a62011-08-12 10:23:01 -07003142 num_trbs = DIV_ROUND_UP(td_len + (addr & (TRB_MAX_BUFF_SIZE - 1)),
3143 TRB_MAX_BUFF_SIZE);
3144 if (num_trbs == 0)
Andiry Xu04e51902010-07-22 15:23:39 -07003145 num_trbs++;
3146
Andiry Xu04e51902010-07-22 15:23:39 -07003147 return num_trbs;
3148}
3149
Sarah Sharp5cd43e32011-04-08 09:37:29 -07003150/*
3151 * The transfer burst count field of the isochronous TRB defines the number of
3152 * bursts that are required to move all packets in this TD. Only SuperSpeed
3153 * devices can burst up to bMaxBurst number of packets per service interval.
3154 * This field is zero based, meaning a value of zero in the field means one
3155 * burst. Basically, for everything but SuperSpeed devices, this field will be
3156 * zero. Only xHCI 1.0 host controllers support this field.
3157 */
3158static unsigned int xhci_get_burst_count(struct xhci_hcd *xhci,
3159 struct usb_device *udev,
3160 struct urb *urb, unsigned int total_packet_count)
3161{
3162 unsigned int max_burst;
3163
3164 if (xhci->hci_version < 0x100 || udev->speed != USB_SPEED_SUPER)
3165 return 0;
3166
3167 max_burst = urb->ep->ss_ep_comp.bMaxBurst;
3168 return roundup(total_packet_count, max_burst + 1) - 1;
3169}
3170
Sarah Sharpb61d3782011-04-19 17:43:33 -07003171/*
3172 * Returns the number of packets in the last "burst" of packets. This field is
3173 * valid for all speeds of devices. USB 2.0 devices can only do one "burst", so
3174 * the last burst packet count is equal to the total number of packets in the
3175 * TD. SuperSpeed endpoints can have up to 3 bursts. All but the last burst
3176 * must contain (bMaxBurst + 1) number of packets, but the last burst can
3177 * contain 1 to (bMaxBurst + 1) packets.
3178 */
3179static unsigned int xhci_get_last_burst_packet_count(struct xhci_hcd *xhci,
3180 struct usb_device *udev,
3181 struct urb *urb, unsigned int total_packet_count)
3182{
3183 unsigned int max_burst;
3184 unsigned int residue;
3185
3186 if (xhci->hci_version < 0x100)
3187 return 0;
3188
3189 switch (udev->speed) {
3190 case USB_SPEED_SUPER:
3191 /* bMaxBurst is zero based: 0 means 1 packet per burst */
3192 max_burst = urb->ep->ss_ep_comp.bMaxBurst;
3193 residue = total_packet_count % (max_burst + 1);
3194 /* If residue is zero, the last burst contains (max_burst + 1)
3195 * number of packets, but the TLBPC field is zero-based.
3196 */
3197 if (residue == 0)
3198 return max_burst;
3199 return residue - 1;
3200 default:
3201 if (total_packet_count == 0)
3202 return 0;
3203 return total_packet_count - 1;
3204 }
3205}
3206
Andiry Xu04e51902010-07-22 15:23:39 -07003207/* This is for isoc transfer */
3208static int xhci_queue_isoc_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3209 struct urb *urb, int slot_id, unsigned int ep_index)
3210{
3211 struct xhci_ring *ep_ring;
3212 struct urb_priv *urb_priv;
3213 struct xhci_td *td;
3214 int num_tds, trbs_per_td;
3215 struct xhci_generic_trb *start_trb;
3216 bool first_trb;
3217 int start_cycle;
3218 u32 field, length_field;
3219 int running_total, trb_buff_len, td_len, td_remain_len, ret;
3220 u64 start_addr, addr;
3221 int i, j;
Andiry Xu47cbf692010-12-20 14:49:48 +08003222 bool more_trbs_coming;
Andiry Xu04e51902010-07-22 15:23:39 -07003223
3224 ep_ring = xhci->devs[slot_id]->eps[ep_index].ring;
3225
3226 num_tds = urb->number_of_packets;
3227 if (num_tds < 1) {
3228 xhci_dbg(xhci, "Isoc URB with zero packets?\n");
3229 return -EINVAL;
3230 }
3231
3232 if (!in_interrupt())
Andiry Xuf2c565e2010-12-20 17:12:24 +08003233 xhci_dbg(xhci, "ep %#x - urb len = %#x (%d),"
Andiry Xu04e51902010-07-22 15:23:39 -07003234 " addr = %#llx, num_tds = %d\n",
3235 urb->ep->desc.bEndpointAddress,
3236 urb->transfer_buffer_length,
3237 urb->transfer_buffer_length,
3238 (unsigned long long)urb->transfer_dma,
3239 num_tds);
3240
3241 start_addr = (u64) urb->transfer_dma;
3242 start_trb = &ep_ring->enqueue->generic;
3243 start_cycle = ep_ring->cycle_state;
3244
Sarah Sharp522989a2011-07-29 12:44:32 -07003245 urb_priv = urb->hcpriv;
Andiry Xu04e51902010-07-22 15:23:39 -07003246 /* Queue the first TRB, even if it's zero-length */
3247 for (i = 0; i < num_tds; i++) {
Sarah Sharp4da6e6f2011-04-01 14:01:30 -07003248 unsigned int total_packet_count;
Sarah Sharp5cd43e32011-04-08 09:37:29 -07003249 unsigned int burst_count;
Sarah Sharpb61d3782011-04-19 17:43:33 -07003250 unsigned int residue;
Andiry Xu04e51902010-07-22 15:23:39 -07003251
Sarah Sharp4da6e6f2011-04-01 14:01:30 -07003252 first_trb = true;
Andiry Xu04e51902010-07-22 15:23:39 -07003253 running_total = 0;
3254 addr = start_addr + urb->iso_frame_desc[i].offset;
3255 td_len = urb->iso_frame_desc[i].length;
3256 td_remain_len = td_len;
Sarah Sharp4da6e6f2011-04-01 14:01:30 -07003257 total_packet_count = roundup(td_len,
Kuninori Morimoto29cc8892011-08-23 03:12:03 -07003258 usb_endpoint_maxp(&urb->ep->desc));
Sarah Sharp48df4a62011-08-12 10:23:01 -07003259 /* A zero-length transfer still involves at least one packet. */
3260 if (total_packet_count == 0)
3261 total_packet_count++;
Sarah Sharp5cd43e32011-04-08 09:37:29 -07003262 burst_count = xhci_get_burst_count(xhci, urb->dev, urb,
3263 total_packet_count);
Sarah Sharpb61d3782011-04-19 17:43:33 -07003264 residue = xhci_get_last_burst_packet_count(xhci,
3265 urb->dev, urb, total_packet_count);
Andiry Xu04e51902010-07-22 15:23:39 -07003266
3267 trbs_per_td = count_isoc_trbs_needed(xhci, urb, i);
3268
3269 ret = prepare_transfer(xhci, xhci->devs[slot_id], ep_index,
Andiry Xu7e393a82011-09-23 14:19:54 -07003270 urb->stream_id, trbs_per_td, urb, i, true,
3271 mem_flags);
Sarah Sharp522989a2011-07-29 12:44:32 -07003272 if (ret < 0) {
3273 if (i == 0)
3274 return ret;
3275 goto cleanup;
3276 }
Andiry Xu04e51902010-07-22 15:23:39 -07003277
Andiry Xu04e51902010-07-22 15:23:39 -07003278 td = urb_priv->td[i];
Andiry Xu04e51902010-07-22 15:23:39 -07003279 for (j = 0; j < trbs_per_td; j++) {
3280 u32 remainder = 0;
Sarah Sharpb61d3782011-04-19 17:43:33 -07003281 field = TRB_TBC(burst_count) | TRB_TLBPC(residue);
Andiry Xu04e51902010-07-22 15:23:39 -07003282
3283 if (first_trb) {
3284 /* Queue the isoc TRB */
3285 field |= TRB_TYPE(TRB_ISOC);
3286 /* Assume URB_ISO_ASAP is set */
3287 field |= TRB_SIA;
Andiry Xu50f7b522010-12-20 15:09:34 +08003288 if (i == 0) {
3289 if (start_cycle == 0)
3290 field |= 0x1;
3291 } else
Andiry Xu04e51902010-07-22 15:23:39 -07003292 field |= ep_ring->cycle_state;
3293 first_trb = false;
3294 } else {
3295 /* Queue other normal TRBs */
3296 field |= TRB_TYPE(TRB_NORMAL);
3297 field |= ep_ring->cycle_state;
3298 }
3299
Sarah Sharpaf8b9e62011-03-23 16:26:26 -07003300 /* Only set interrupt on short packet for IN EPs */
3301 if (usb_urb_dir_in(urb))
3302 field |= TRB_ISP;
3303
Andiry Xu04e51902010-07-22 15:23:39 -07003304 /* Chain all the TRBs together; clear the chain bit in
3305 * the last TRB to indicate it's the last TRB in the
3306 * chain.
3307 */
3308 if (j < trbs_per_td - 1) {
3309 field |= TRB_CHAIN;
Andiry Xu47cbf692010-12-20 14:49:48 +08003310 more_trbs_coming = true;
Andiry Xu04e51902010-07-22 15:23:39 -07003311 } else {
3312 td->last_trb = ep_ring->enqueue;
3313 field |= TRB_IOC;
Andiry Xuad106f22011-05-05 18:14:02 +08003314 if (xhci->hci_version == 0x100) {
3315 /* Set BEI bit except for the last td */
3316 if (i < num_tds - 1)
3317 field |= TRB_BEI;
3318 }
Andiry Xu47cbf692010-12-20 14:49:48 +08003319 more_trbs_coming = false;
Andiry Xu04e51902010-07-22 15:23:39 -07003320 }
3321
3322 /* Calculate TRB length */
3323 trb_buff_len = TRB_MAX_BUFF_SIZE -
3324 (addr & ((1 << TRB_MAX_BUFF_SHIFT) - 1));
3325 if (trb_buff_len > td_remain_len)
3326 trb_buff_len = td_remain_len;
3327
Sarah Sharp4da6e6f2011-04-01 14:01:30 -07003328 /* Set the TRB length, TD size, & interrupter fields. */
3329 if (xhci->hci_version < 0x100) {
3330 remainder = xhci_td_remainder(
3331 td_len - running_total);
3332 } else {
3333 remainder = xhci_v1_0_td_remainder(
3334 running_total, trb_buff_len,
3335 total_packet_count, urb);
3336 }
Andiry Xu04e51902010-07-22 15:23:39 -07003337 length_field = TRB_LEN(trb_buff_len) |
3338 remainder |
3339 TRB_INTR_TARGET(0);
Sarah Sharp4da6e6f2011-04-01 14:01:30 -07003340
Andiry Xu7e393a82011-09-23 14:19:54 -07003341 queue_trb(xhci, ep_ring, false, more_trbs_coming, true,
Andiry Xu04e51902010-07-22 15:23:39 -07003342 lower_32_bits(addr),
3343 upper_32_bits(addr),
3344 length_field,
Sarah Sharpaf8b9e62011-03-23 16:26:26 -07003345 field);
Andiry Xu04e51902010-07-22 15:23:39 -07003346 running_total += trb_buff_len;
3347
3348 addr += trb_buff_len;
3349 td_remain_len -= trb_buff_len;
3350 }
3351
3352 /* Check TD length */
3353 if (running_total != td_len) {
3354 xhci_err(xhci, "ISOC TD length unmatch\n");
3355 return -EINVAL;
3356 }
3357 }
3358
Andiry Xuc41136b2011-03-22 17:08:14 +08003359 if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs == 0) {
3360 if (xhci->quirks & XHCI_AMD_PLL_FIX)
3361 usb_amd_quirk_pll_disable();
3362 }
3363 xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs++;
3364
Andiry Xue1eab2e2011-01-04 16:30:39 -08003365 giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id,
3366 start_cycle, start_trb);
Andiry Xu04e51902010-07-22 15:23:39 -07003367 return 0;
Sarah Sharp522989a2011-07-29 12:44:32 -07003368cleanup:
3369 /* Clean up a partially enqueued isoc transfer. */
3370
3371 for (i--; i >= 0; i--)
Sarah Sharp585df1d2011-08-02 15:43:40 -07003372 list_del_init(&urb_priv->td[i]->td_list);
Sarah Sharp522989a2011-07-29 12:44:32 -07003373
3374 /* Use the first TD as a temporary variable to turn the TDs we've queued
3375 * into No-ops with a software-owned cycle bit. That way the hardware
3376 * won't accidentally start executing bogus TDs when we partially
3377 * overwrite them. td->first_trb and td->start_seg are already set.
3378 */
3379 urb_priv->td[0]->last_trb = ep_ring->enqueue;
3380 /* Every TRB except the first & last will have its cycle bit flipped. */
3381 td_to_noop(xhci, ep_ring, urb_priv->td[0], true);
3382
3383 /* Reset the ring enqueue back to the first TRB and its cycle bit. */
3384 ep_ring->enqueue = urb_priv->td[0]->first_trb;
3385 ep_ring->enq_seg = urb_priv->td[0]->start_seg;
3386 ep_ring->cycle_state = start_cycle;
3387 usb_hcd_unlink_urb_from_ep(bus_to_hcd(urb->dev->bus), urb);
3388 return ret;
Andiry Xu04e51902010-07-22 15:23:39 -07003389}
3390
3391/*
3392 * Check transfer ring to guarantee there is enough room for the urb.
3393 * Update ISO URB start_frame and interval.
3394 * Update interval as xhci_queue_intr_tx does. Just use xhci frame_index to
3395 * update the urb->start_frame by now.
3396 * Always assume URB_ISO_ASAP set, and NEVER use urb->start_frame as input.
3397 */
3398int xhci_queue_isoc_tx_prepare(struct xhci_hcd *xhci, gfp_t mem_flags,
3399 struct urb *urb, int slot_id, unsigned int ep_index)
3400{
3401 struct xhci_virt_device *xdev;
3402 struct xhci_ring *ep_ring;
3403 struct xhci_ep_ctx *ep_ctx;
3404 int start_frame;
3405 int xhci_interval;
3406 int ep_interval;
3407 int num_tds, num_trbs, i;
3408 int ret;
3409
3410 xdev = xhci->devs[slot_id];
3411 ep_ring = xdev->eps[ep_index].ring;
3412 ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
3413
3414 num_trbs = 0;
3415 num_tds = urb->number_of_packets;
3416 for (i = 0; i < num_tds; i++)
3417 num_trbs += count_isoc_trbs_needed(xhci, urb, i);
3418
3419 /* Check the ring to guarantee there is enough room for the whole urb.
3420 * Do not insert any td of the urb to the ring if the check failed.
3421 */
Matt Evans28ccd292011-03-29 13:40:46 +11003422 ret = prepare_ring(xhci, ep_ring, le32_to_cpu(ep_ctx->ep_info) & EP_STATE_MASK,
Andiry Xu7e393a82011-09-23 14:19:54 -07003423 num_trbs, true, mem_flags);
Andiry Xu04e51902010-07-22 15:23:39 -07003424 if (ret)
3425 return ret;
3426
3427 start_frame = xhci_readl(xhci, &xhci->run_regs->microframe_index);
3428 start_frame &= 0x3fff;
3429
3430 urb->start_frame = start_frame;
3431 if (urb->dev->speed == USB_SPEED_LOW ||
3432 urb->dev->speed == USB_SPEED_FULL)
3433 urb->start_frame >>= 3;
3434
Matt Evans28ccd292011-03-29 13:40:46 +11003435 xhci_interval = EP_INTERVAL_TO_UFRAMES(le32_to_cpu(ep_ctx->ep_info));
Andiry Xu04e51902010-07-22 15:23:39 -07003436 ep_interval = urb->interval;
3437 /* Convert to microframes */
3438 if (urb->dev->speed == USB_SPEED_LOW ||
3439 urb->dev->speed == USB_SPEED_FULL)
3440 ep_interval *= 8;
3441 /* FIXME change this to a warning and a suggestion to use the new API
3442 * to set the polling interval (once the API is added).
3443 */
3444 if (xhci_interval != ep_interval) {
Andiry Xu7961acd2010-12-20 17:14:20 +08003445 if (printk_ratelimit())
Andiry Xu04e51902010-07-22 15:23:39 -07003446 dev_dbg(&urb->dev->dev, "Driver uses different interval"
3447 " (%d microframe%s) than xHCI "
3448 "(%d microframe%s)\n",
3449 ep_interval,
3450 ep_interval == 1 ? "" : "s",
3451 xhci_interval,
3452 xhci_interval == 1 ? "" : "s");
3453 urb->interval = xhci_interval;
3454 /* Convert back to frames for LS/FS devices */
3455 if (urb->dev->speed == USB_SPEED_LOW ||
3456 urb->dev->speed == USB_SPEED_FULL)
3457 urb->interval /= 8;
3458 }
3459 return xhci_queue_isoc_tx(xhci, GFP_ATOMIC, urb, slot_id, ep_index);
3460}
3461
Sarah Sharpd0e96f52009-04-27 19:58:01 -07003462/**** Command Ring Operations ****/
3463
Sarah Sharp913a8a32009-09-04 10:53:13 -07003464/* Generic function for queueing a command TRB on the command ring.
3465 * Check to make sure there's room on the command ring for one command TRB.
3466 * Also check that there's room reserved for commands that must not fail.
3467 * If this is a command that must not fail, meaning command_must_succeed = TRUE,
3468 * then only check for the number of reserved spots.
3469 * Don't decrement xhci->cmd_ring_reserved_trbs after we've queued the TRB
3470 * because the command event handler may want to resubmit a failed command.
3471 */
3472static int queue_command(struct xhci_hcd *xhci, u32 field1, u32 field2,
3473 u32 field3, u32 field4, bool command_must_succeed)
Sarah Sharp7f84eef2009-04-27 19:53:56 -07003474{
Sarah Sharp913a8a32009-09-04 10:53:13 -07003475 int reserved_trbs = xhci->cmd_ring_reserved_trbs;
Sarah Sharpd1dc9082010-07-09 17:08:38 +02003476 int ret;
3477
Sarah Sharp913a8a32009-09-04 10:53:13 -07003478 if (!command_must_succeed)
3479 reserved_trbs++;
3480
Sarah Sharpd1dc9082010-07-09 17:08:38 +02003481 ret = prepare_ring(xhci, xhci->cmd_ring, EP_STATE_RUNNING,
Andiry Xu7e393a82011-09-23 14:19:54 -07003482 reserved_trbs, false, GFP_ATOMIC);
Sarah Sharpd1dc9082010-07-09 17:08:38 +02003483 if (ret < 0) {
3484 xhci_err(xhci, "ERR: No room for command on command ring\n");
Sarah Sharp913a8a32009-09-04 10:53:13 -07003485 if (command_must_succeed)
3486 xhci_err(xhci, "ERR: Reserved TRB counting for "
3487 "unfailable commands failed.\n");
Sarah Sharpd1dc9082010-07-09 17:08:38 +02003488 return ret;
Sarah Sharp7f84eef2009-04-27 19:53:56 -07003489 }
Andiry Xu7e393a82011-09-23 14:19:54 -07003490 queue_trb(xhci, xhci->cmd_ring, false, false, false, field1, field2,
3491 field3, field4 | xhci->cmd_ring->cycle_state);
Sarah Sharp7f84eef2009-04-27 19:53:56 -07003492 return 0;
3493}
3494
Sarah Sharp3ffbba92009-04-27 19:57:38 -07003495/* Queue a slot enable or disable request on the command ring */
Sarah Sharp23e3be12009-04-29 19:05:20 -07003496int xhci_queue_slot_control(struct xhci_hcd *xhci, u32 trb_type, u32 slot_id)
Sarah Sharp3ffbba92009-04-27 19:57:38 -07003497{
3498 return queue_command(xhci, 0, 0, 0,
Sarah Sharp913a8a32009-09-04 10:53:13 -07003499 TRB_TYPE(trb_type) | SLOT_ID_FOR_TRB(slot_id), false);
Sarah Sharp3ffbba92009-04-27 19:57:38 -07003500}
3501
3502/* Queue an address device command TRB */
Sarah Sharp23e3be12009-04-29 19:05:20 -07003503int xhci_queue_address_device(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr,
3504 u32 slot_id)
Sarah Sharp3ffbba92009-04-27 19:57:38 -07003505{
Sarah Sharp8e595a52009-07-27 12:03:31 -07003506 return queue_command(xhci, lower_32_bits(in_ctx_ptr),
3507 upper_32_bits(in_ctx_ptr), 0,
Sarah Sharp913a8a32009-09-04 10:53:13 -07003508 TRB_TYPE(TRB_ADDR_DEV) | SLOT_ID_FOR_TRB(slot_id),
3509 false);
Sarah Sharp3ffbba92009-04-27 19:57:38 -07003510}
Sarah Sharpf94e01862009-04-27 19:58:38 -07003511
Sarah Sharp02386342010-05-24 13:25:28 -07003512int xhci_queue_vendor_command(struct xhci_hcd *xhci,
3513 u32 field1, u32 field2, u32 field3, u32 field4)
3514{
3515 return queue_command(xhci, field1, field2, field3, field4, false);
3516}
3517
Sarah Sharp2a8f82c2009-12-09 15:59:13 -08003518/* Queue a reset device command TRB */
3519int xhci_queue_reset_device(struct xhci_hcd *xhci, u32 slot_id)
3520{
3521 return queue_command(xhci, 0, 0, 0,
3522 TRB_TYPE(TRB_RESET_DEV) | SLOT_ID_FOR_TRB(slot_id),
3523 false);
3524}
3525
Sarah Sharpf94e01862009-04-27 19:58:38 -07003526/* Queue a configure endpoint command TRB */
Sarah Sharp23e3be12009-04-29 19:05:20 -07003527int xhci_queue_configure_endpoint(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr,
Sarah Sharp913a8a32009-09-04 10:53:13 -07003528 u32 slot_id, bool command_must_succeed)
Sarah Sharpf94e01862009-04-27 19:58:38 -07003529{
Sarah Sharp8e595a52009-07-27 12:03:31 -07003530 return queue_command(xhci, lower_32_bits(in_ctx_ptr),
3531 upper_32_bits(in_ctx_ptr), 0,
Sarah Sharp913a8a32009-09-04 10:53:13 -07003532 TRB_TYPE(TRB_CONFIG_EP) | SLOT_ID_FOR_TRB(slot_id),
3533 command_must_succeed);
Sarah Sharpf94e01862009-04-27 19:58:38 -07003534}
Sarah Sharpae636742009-04-29 19:02:31 -07003535
Sarah Sharpf2217e82009-08-07 14:04:43 -07003536/* Queue an evaluate context command TRB */
3537int xhci_queue_evaluate_context(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr,
3538 u32 slot_id)
3539{
3540 return queue_command(xhci, lower_32_bits(in_ctx_ptr),
3541 upper_32_bits(in_ctx_ptr), 0,
Sarah Sharp913a8a32009-09-04 10:53:13 -07003542 TRB_TYPE(TRB_EVAL_CONTEXT) | SLOT_ID_FOR_TRB(slot_id),
3543 false);
Sarah Sharpf2217e82009-08-07 14:04:43 -07003544}
3545
Andiry Xube88fe42010-10-14 07:22:57 -07003546/*
3547 * Suspend is set to indicate "Stop Endpoint Command" is being issued to stop
3548 * activity on an endpoint that is about to be suspended.
3549 */
Sarah Sharp23e3be12009-04-29 19:05:20 -07003550int xhci_queue_stop_endpoint(struct xhci_hcd *xhci, int slot_id,
Andiry Xube88fe42010-10-14 07:22:57 -07003551 unsigned int ep_index, int suspend)
Sarah Sharpae636742009-04-29 19:02:31 -07003552{
3553 u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
3554 u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
3555 u32 type = TRB_TYPE(TRB_STOP_RING);
Andiry Xube88fe42010-10-14 07:22:57 -07003556 u32 trb_suspend = SUSPEND_PORT_FOR_TRB(suspend);
Sarah Sharpae636742009-04-29 19:02:31 -07003557
3558 return queue_command(xhci, 0, 0, 0,
Andiry Xube88fe42010-10-14 07:22:57 -07003559 trb_slot_id | trb_ep_index | type | trb_suspend, false);
Sarah Sharpae636742009-04-29 19:02:31 -07003560}
3561
3562/* Set Transfer Ring Dequeue Pointer command.
3563 * This should not be used for endpoints that have streams enabled.
3564 */
3565static int queue_set_tr_deq(struct xhci_hcd *xhci, int slot_id,
Sarah Sharpe9df17e2010-04-02 15:34:43 -07003566 unsigned int ep_index, unsigned int stream_id,
3567 struct xhci_segment *deq_seg,
Sarah Sharpae636742009-04-29 19:02:31 -07003568 union xhci_trb *deq_ptr, u32 cycle_state)
3569{
3570 dma_addr_t addr;
3571 u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
3572 u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
Sarah Sharpe9df17e2010-04-02 15:34:43 -07003573 u32 trb_stream_id = STREAM_ID_FOR_TRB(stream_id);
Sarah Sharpae636742009-04-29 19:02:31 -07003574 u32 type = TRB_TYPE(TRB_SET_DEQ);
Sarah Sharpbf161e82011-02-23 15:46:42 -08003575 struct xhci_virt_ep *ep;
Sarah Sharpae636742009-04-29 19:02:31 -07003576
Sarah Sharp23e3be12009-04-29 19:05:20 -07003577 addr = xhci_trb_virt_to_dma(deq_seg, deq_ptr);
Sarah Sharpc92bcfa2009-07-27 12:05:21 -07003578 if (addr == 0) {
Sarah Sharpae636742009-04-29 19:02:31 -07003579 xhci_warn(xhci, "WARN Cannot submit Set TR Deq Ptr\n");
Greg Kroah-Hartman700e2052009-04-29 19:14:08 -07003580 xhci_warn(xhci, "WARN deq seg = %p, deq pt = %p\n",
3581 deq_seg, deq_ptr);
Sarah Sharpc92bcfa2009-07-27 12:05:21 -07003582 return 0;
3583 }
Sarah Sharpbf161e82011-02-23 15:46:42 -08003584 ep = &xhci->devs[slot_id]->eps[ep_index];
3585 if ((ep->ep_state & SET_DEQ_PENDING)) {
3586 xhci_warn(xhci, "WARN Cannot submit Set TR Deq Ptr\n");
3587 xhci_warn(xhci, "A Set TR Deq Ptr command is pending.\n");
3588 return 0;
3589 }
3590 ep->queued_deq_seg = deq_seg;
3591 ep->queued_deq_ptr = deq_ptr;
Sarah Sharp8e595a52009-07-27 12:03:31 -07003592 return queue_command(xhci, lower_32_bits(addr) | cycle_state,
Sarah Sharpe9df17e2010-04-02 15:34:43 -07003593 upper_32_bits(addr), trb_stream_id,
Sarah Sharp913a8a32009-09-04 10:53:13 -07003594 trb_slot_id | trb_ep_index | type, false);
Sarah Sharpae636742009-04-29 19:02:31 -07003595}
Sarah Sharpa1587d92009-07-27 12:03:15 -07003596
3597int xhci_queue_reset_ep(struct xhci_hcd *xhci, int slot_id,
3598 unsigned int ep_index)
3599{
3600 u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
3601 u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
3602 u32 type = TRB_TYPE(TRB_RESET_EP);
3603
Sarah Sharp913a8a32009-09-04 10:53:13 -07003604 return queue_command(xhci, 0, 0, 0, trb_slot_id | trb_ep_index | type,
3605 false);
Sarah Sharpa1587d92009-07-27 12:03:15 -07003606}