| Hans-Christian Egtvedt | eb1f293 | 2007-10-16 23:26:11 -0700 | [diff] [blame] | 1 | #ifndef __INCLUDE_ATMEL_SSC_H |
| 2 | #define __INCLUDE_ATMEL_SSC_H |
| 3 | |
| 4 | #include <linux/platform_device.h> |
| 5 | #include <linux/list.h> |
| 6 | |
| 7 | struct ssc_device { |
| 8 | struct list_head list; |
| 9 | void __iomem *regs; |
| 10 | struct platform_device *pdev; |
| 11 | struct clk *clk; |
| 12 | int user; |
| 13 | int irq; |
| 14 | }; |
| 15 | |
| 16 | struct ssc_device * __must_check ssc_request(unsigned int ssc_num); |
| 17 | void ssc_free(struct ssc_device *ssc); |
| 18 | |
| 19 | /* SSC register offsets */ |
| 20 | |
| 21 | /* SSC Control Register */ |
| 22 | #define SSC_CR 0x00000000 |
| 23 | #define SSC_CR_RXDIS_SIZE 1 |
| 24 | #define SSC_CR_RXDIS_OFFSET 1 |
| 25 | #define SSC_CR_RXEN_SIZE 1 |
| 26 | #define SSC_CR_RXEN_OFFSET 0 |
| 27 | #define SSC_CR_SWRST_SIZE 1 |
| 28 | #define SSC_CR_SWRST_OFFSET 15 |
| 29 | #define SSC_CR_TXDIS_SIZE 1 |
| 30 | #define SSC_CR_TXDIS_OFFSET 9 |
| 31 | #define SSC_CR_TXEN_SIZE 1 |
| 32 | #define SSC_CR_TXEN_OFFSET 8 |
| 33 | |
| 34 | /* SSC Clock Mode Register */ |
| 35 | #define SSC_CMR 0x00000004 |
| 36 | #define SSC_CMR_DIV_SIZE 12 |
| 37 | #define SSC_CMR_DIV_OFFSET 0 |
| 38 | |
| 39 | /* SSC Receive Clock Mode Register */ |
| 40 | #define SSC_RCMR 0x00000010 |
| 41 | #define SSC_RCMR_CKG_SIZE 2 |
| 42 | #define SSC_RCMR_CKG_OFFSET 6 |
| 43 | #define SSC_RCMR_CKI_SIZE 1 |
| 44 | #define SSC_RCMR_CKI_OFFSET 5 |
| 45 | #define SSC_RCMR_CKO_SIZE 3 |
| 46 | #define SSC_RCMR_CKO_OFFSET 2 |
| 47 | #define SSC_RCMR_CKS_SIZE 2 |
| 48 | #define SSC_RCMR_CKS_OFFSET 0 |
| 49 | #define SSC_RCMR_PERIOD_SIZE 8 |
| 50 | #define SSC_RCMR_PERIOD_OFFSET 24 |
| 51 | #define SSC_RCMR_START_SIZE 4 |
| 52 | #define SSC_RCMR_START_OFFSET 8 |
| 53 | #define SSC_RCMR_STOP_SIZE 1 |
| 54 | #define SSC_RCMR_STOP_OFFSET 12 |
| 55 | #define SSC_RCMR_STTDLY_SIZE 8 |
| 56 | #define SSC_RCMR_STTDLY_OFFSET 16 |
| 57 | |
| 58 | /* SSC Receive Frame Mode Register */ |
| 59 | #define SSC_RFMR 0x00000014 |
| 60 | #define SSC_RFMR_DATLEN_SIZE 5 |
| 61 | #define SSC_RFMR_DATLEN_OFFSET 0 |
| 62 | #define SSC_RFMR_DATNB_SIZE 4 |
| 63 | #define SSC_RFMR_DATNB_OFFSET 8 |
| 64 | #define SSC_RFMR_FSEDGE_SIZE 1 |
| 65 | #define SSC_RFMR_FSEDGE_OFFSET 24 |
| 66 | #define SSC_RFMR_FSLEN_SIZE 4 |
| 67 | #define SSC_RFMR_FSLEN_OFFSET 16 |
| 68 | #define SSC_RFMR_FSOS_SIZE 4 |
| 69 | #define SSC_RFMR_FSOS_OFFSET 20 |
| 70 | #define SSC_RFMR_LOOP_SIZE 1 |
| 71 | #define SSC_RFMR_LOOP_OFFSET 5 |
| 72 | #define SSC_RFMR_MSBF_SIZE 1 |
| 73 | #define SSC_RFMR_MSBF_OFFSET 7 |
| 74 | |
| 75 | /* SSC Transmit Clock Mode Register */ |
| 76 | #define SSC_TCMR 0x00000018 |
| 77 | #define SSC_TCMR_CKG_SIZE 2 |
| 78 | #define SSC_TCMR_CKG_OFFSET 6 |
| 79 | #define SSC_TCMR_CKI_SIZE 1 |
| 80 | #define SSC_TCMR_CKI_OFFSET 5 |
| 81 | #define SSC_TCMR_CKO_SIZE 3 |
| 82 | #define SSC_TCMR_CKO_OFFSET 2 |
| 83 | #define SSC_TCMR_CKS_SIZE 2 |
| 84 | #define SSC_TCMR_CKS_OFFSET 0 |
| 85 | #define SSC_TCMR_PERIOD_SIZE 8 |
| 86 | #define SSC_TCMR_PERIOD_OFFSET 24 |
| 87 | #define SSC_TCMR_START_SIZE 4 |
| 88 | #define SSC_TCMR_START_OFFSET 8 |
| 89 | #define SSC_TCMR_STTDLY_SIZE 8 |
| 90 | #define SSC_TCMR_STTDLY_OFFSET 16 |
| 91 | |
| 92 | /* SSC Transmit Frame Mode Register */ |
| 93 | #define SSC_TFMR 0x0000001c |
| 94 | #define SSC_TFMR_DATDEF_SIZE 1 |
| 95 | #define SSC_TFMR_DATDEF_OFFSET 5 |
| 96 | #define SSC_TFMR_DATLEN_SIZE 5 |
| 97 | #define SSC_TFMR_DATLEN_OFFSET 0 |
| 98 | #define SSC_TFMR_DATNB_SIZE 4 |
| 99 | #define SSC_TFMR_DATNB_OFFSET 8 |
| 100 | #define SSC_TFMR_FSDEN_SIZE 1 |
| 101 | #define SSC_TFMR_FSDEN_OFFSET 23 |
| 102 | #define SSC_TFMR_FSEDGE_SIZE 1 |
| 103 | #define SSC_TFMR_FSEDGE_OFFSET 24 |
| 104 | #define SSC_TFMR_FSLEN_SIZE 4 |
| 105 | #define SSC_TFMR_FSLEN_OFFSET 16 |
| 106 | #define SSC_TFMR_FSOS_SIZE 3 |
| 107 | #define SSC_TFMR_FSOS_OFFSET 20 |
| 108 | #define SSC_TFMR_MSBF_SIZE 1 |
| 109 | #define SSC_TFMR_MSBF_OFFSET 7 |
| 110 | |
| 111 | /* SSC Receive Hold Register */ |
| 112 | #define SSC_RHR 0x00000020 |
| 113 | #define SSC_RHR_RDAT_SIZE 32 |
| 114 | #define SSC_RHR_RDAT_OFFSET 0 |
| 115 | |
| 116 | /* SSC Transmit Hold Register */ |
| 117 | #define SSC_THR 0x00000024 |
| 118 | #define SSC_THR_TDAT_SIZE 32 |
| 119 | #define SSC_THR_TDAT_OFFSET 0 |
| 120 | |
| 121 | /* SSC Receive Sync. Holding Register */ |
| 122 | #define SSC_RSHR 0x00000030 |
| 123 | #define SSC_RSHR_RSDAT_SIZE 16 |
| 124 | #define SSC_RSHR_RSDAT_OFFSET 0 |
| 125 | |
| 126 | /* SSC Transmit Sync. Holding Register */ |
| 127 | #define SSC_TSHR 0x00000034 |
| 128 | #define SSC_TSHR_TSDAT_SIZE 16 |
| 129 | #define SSC_TSHR_RSDAT_OFFSET 0 |
| 130 | |
| 131 | /* SSC Receive Compare 0 Register */ |
| 132 | #define SSC_RC0R 0x00000038 |
| 133 | #define SSC_RC0R_CP0_SIZE 16 |
| 134 | #define SSC_RC0R_CP0_OFFSET 0 |
| 135 | |
| 136 | /* SSC Receive Compare 1 Register */ |
| 137 | #define SSC_RC1R 0x0000003c |
| 138 | #define SSC_RC1R_CP1_SIZE 16 |
| 139 | #define SSC_RC1R_CP1_OFFSET 0 |
| 140 | |
| 141 | /* SSC Status Register */ |
| 142 | #define SSC_SR 0x00000040 |
| 143 | #define SSC_SR_CP0_SIZE 1 |
| 144 | #define SSC_SR_CP0_OFFSET 8 |
| 145 | #define SSC_SR_CP1_SIZE 1 |
| 146 | #define SSC_SR_CP1_OFFSET 9 |
| 147 | #define SSC_SR_ENDRX_SIZE 1 |
| 148 | #define SSC_SR_ENDRX_OFFSET 6 |
| 149 | #define SSC_SR_ENDTX_SIZE 1 |
| 150 | #define SSC_SR_ENDTX_OFFSET 2 |
| 151 | #define SSC_SR_OVRUN_SIZE 1 |
| 152 | #define SSC_SR_OVRUN_OFFSET 5 |
| 153 | #define SSC_SR_RXBUFF_SIZE 1 |
| 154 | #define SSC_SR_RXBUFF_OFFSET 7 |
| 155 | #define SSC_SR_RXEN_SIZE 1 |
| 156 | #define SSC_SR_RXEN_OFFSET 17 |
| 157 | #define SSC_SR_RXRDY_SIZE 1 |
| 158 | #define SSC_SR_RXRDY_OFFSET 4 |
| 159 | #define SSC_SR_RXSYN_SIZE 1 |
| 160 | #define SSC_SR_RXSYN_OFFSET 11 |
| 161 | #define SSC_SR_TXBUFE_SIZE 1 |
| 162 | #define SSC_SR_TXBUFE_OFFSET 3 |
| 163 | #define SSC_SR_TXEMPTY_SIZE 1 |
| 164 | #define SSC_SR_TXEMPTY_OFFSET 1 |
| 165 | #define SSC_SR_TXEN_SIZE 1 |
| 166 | #define SSC_SR_TXEN_OFFSET 16 |
| 167 | #define SSC_SR_TXRDY_SIZE 1 |
| 168 | #define SSC_SR_TXRDY_OFFSET 0 |
| 169 | #define SSC_SR_TXSYN_SIZE 1 |
| 170 | #define SSC_SR_TXSYN_OFFSET 10 |
| 171 | |
| 172 | /* SSC Interrupt Enable Register */ |
| 173 | #define SSC_IER 0x00000044 |
| 174 | #define SSC_IER_CP0_SIZE 1 |
| 175 | #define SSC_IER_CP0_OFFSET 8 |
| 176 | #define SSC_IER_CP1_SIZE 1 |
| 177 | #define SSC_IER_CP1_OFFSET 9 |
| 178 | #define SSC_IER_ENDRX_SIZE 1 |
| 179 | #define SSC_IER_ENDRX_OFFSET 6 |
| 180 | #define SSC_IER_ENDTX_SIZE 1 |
| 181 | #define SSC_IER_ENDTX_OFFSET 2 |
| 182 | #define SSC_IER_OVRUN_SIZE 1 |
| 183 | #define SSC_IER_OVRUN_OFFSET 5 |
| 184 | #define SSC_IER_RXBUFF_SIZE 1 |
| 185 | #define SSC_IER_RXBUFF_OFFSET 7 |
| 186 | #define SSC_IER_RXRDY_SIZE 1 |
| 187 | #define SSC_IER_RXRDY_OFFSET 4 |
| 188 | #define SSC_IER_RXSYN_SIZE 1 |
| 189 | #define SSC_IER_RXSYN_OFFSET 11 |
| 190 | #define SSC_IER_TXBUFE_SIZE 1 |
| 191 | #define SSC_IER_TXBUFE_OFFSET 3 |
| 192 | #define SSC_IER_TXEMPTY_SIZE 1 |
| 193 | #define SSC_IER_TXEMPTY_OFFSET 1 |
| 194 | #define SSC_IER_TXRDY_SIZE 1 |
| 195 | #define SSC_IER_TXRDY_OFFSET 0 |
| 196 | #define SSC_IER_TXSYN_SIZE 1 |
| 197 | #define SSC_IER_TXSYN_OFFSET 10 |
| 198 | |
| 199 | /* SSC Interrupt Disable Register */ |
| 200 | #define SSC_IDR 0x00000048 |
| 201 | #define SSC_IDR_CP0_SIZE 1 |
| 202 | #define SSC_IDR_CP0_OFFSET 8 |
| 203 | #define SSC_IDR_CP1_SIZE 1 |
| 204 | #define SSC_IDR_CP1_OFFSET 9 |
| 205 | #define SSC_IDR_ENDRX_SIZE 1 |
| 206 | #define SSC_IDR_ENDRX_OFFSET 6 |
| 207 | #define SSC_IDR_ENDTX_SIZE 1 |
| 208 | #define SSC_IDR_ENDTX_OFFSET 2 |
| 209 | #define SSC_IDR_OVRUN_SIZE 1 |
| 210 | #define SSC_IDR_OVRUN_OFFSET 5 |
| 211 | #define SSC_IDR_RXBUFF_SIZE 1 |
| 212 | #define SSC_IDR_RXBUFF_OFFSET 7 |
| 213 | #define SSC_IDR_RXRDY_SIZE 1 |
| 214 | #define SSC_IDR_RXRDY_OFFSET 4 |
| 215 | #define SSC_IDR_RXSYN_SIZE 1 |
| 216 | #define SSC_IDR_RXSYN_OFFSET 11 |
| 217 | #define SSC_IDR_TXBUFE_SIZE 1 |
| 218 | #define SSC_IDR_TXBUFE_OFFSET 3 |
| 219 | #define SSC_IDR_TXEMPTY_SIZE 1 |
| 220 | #define SSC_IDR_TXEMPTY_OFFSET 1 |
| 221 | #define SSC_IDR_TXRDY_SIZE 1 |
| 222 | #define SSC_IDR_TXRDY_OFFSET 0 |
| 223 | #define SSC_IDR_TXSYN_SIZE 1 |
| 224 | #define SSC_IDR_TXSYN_OFFSET 10 |
| 225 | |
| 226 | /* SSC Interrupt Mask Register */ |
| 227 | #define SSC_IMR 0x0000004c |
| 228 | #define SSC_IMR_CP0_SIZE 1 |
| 229 | #define SSC_IMR_CP0_OFFSET 8 |
| 230 | #define SSC_IMR_CP1_SIZE 1 |
| 231 | #define SSC_IMR_CP1_OFFSET 9 |
| 232 | #define SSC_IMR_ENDRX_SIZE 1 |
| 233 | #define SSC_IMR_ENDRX_OFFSET 6 |
| 234 | #define SSC_IMR_ENDTX_SIZE 1 |
| 235 | #define SSC_IMR_ENDTX_OFFSET 2 |
| 236 | #define SSC_IMR_OVRUN_SIZE 1 |
| 237 | #define SSC_IMR_OVRUN_OFFSET 5 |
| 238 | #define SSC_IMR_RXBUFF_SIZE 1 |
| 239 | #define SSC_IMR_RXBUFF_OFFSET 7 |
| 240 | #define SSC_IMR_RXRDY_SIZE 1 |
| 241 | #define SSC_IMR_RXRDY_OFFSET 4 |
| 242 | #define SSC_IMR_RXSYN_SIZE 1 |
| 243 | #define SSC_IMR_RXSYN_OFFSET 11 |
| 244 | #define SSC_IMR_TXBUFE_SIZE 1 |
| 245 | #define SSC_IMR_TXBUFE_OFFSET 3 |
| 246 | #define SSC_IMR_TXEMPTY_SIZE 1 |
| 247 | #define SSC_IMR_TXEMPTY_OFFSET 1 |
| 248 | #define SSC_IMR_TXRDY_SIZE 1 |
| 249 | #define SSC_IMR_TXRDY_OFFSET 0 |
| 250 | #define SSC_IMR_TXSYN_SIZE 1 |
| 251 | #define SSC_IMR_TXSYN_OFFSET 10 |
| 252 | |
| 253 | /* SSC PDC Receive Pointer Register */ |
| 254 | #define SSC_PDC_RPR 0x00000100 |
| 255 | |
| 256 | /* SSC PDC Receive Counter Register */ |
| 257 | #define SSC_PDC_RCR 0x00000104 |
| 258 | |
| 259 | /* SSC PDC Transmit Pointer Register */ |
| 260 | #define SSC_PDC_TPR 0x00000108 |
| 261 | |
| 262 | /* SSC PDC Receive Next Pointer Register */ |
| 263 | #define SSC_PDC_RNPR 0x00000110 |
| 264 | |
| 265 | /* SSC PDC Receive Next Counter Register */ |
| 266 | #define SSC_PDC_RNCR 0x00000114 |
| 267 | |
| 268 | /* SSC PDC Transmit Counter Register */ |
| 269 | #define SSC_PDC_TCR 0x0000010c |
| 270 | |
| 271 | /* SSC PDC Transmit Next Pointer Register */ |
| 272 | #define SSC_PDC_TNPR 0x00000118 |
| 273 | |
| 274 | /* SSC PDC Transmit Next Counter Register */ |
| 275 | #define SSC_PDC_TNCR 0x0000011c |
| 276 | |
| 277 | /* SSC PDC Transfer Control Register */ |
| 278 | #define SSC_PDC_PTCR 0x00000120 |
| 279 | #define SSC_PDC_PTCR_RXTDIS_SIZE 1 |
| 280 | #define SSC_PDC_PTCR_RXTDIS_OFFSET 1 |
| 281 | #define SSC_PDC_PTCR_RXTEN_SIZE 1 |
| 282 | #define SSC_PDC_PTCR_RXTEN_OFFSET 0 |
| 283 | #define SSC_PDC_PTCR_TXTDIS_SIZE 1 |
| 284 | #define SSC_PDC_PTCR_TXTDIS_OFFSET 9 |
| 285 | #define SSC_PDC_PTCR_TXTEN_SIZE 1 |
| 286 | #define SSC_PDC_PTCR_TXTEN_OFFSET 8 |
| 287 | |
| 288 | /* SSC PDC Transfer Status Register */ |
| 289 | #define SSC_PDC_PTSR 0x00000124 |
| 290 | #define SSC_PDC_PTSR_RXTEN_SIZE 1 |
| 291 | #define SSC_PDC_PTSR_RXTEN_OFFSET 0 |
| 292 | #define SSC_PDC_PTSR_TXTEN_SIZE 1 |
| 293 | #define SSC_PDC_PTSR_TXTEN_OFFSET 8 |
| 294 | |
| 295 | /* Bit manipulation macros */ |
| 296 | #define SSC_BIT(name) \ |
| 297 | (1 << SSC_##name##_OFFSET) |
| 298 | #define SSC_BF(name, value) \ |
| 299 | (((value) & ((1 << SSC_##name##_SIZE) - 1)) \ |
| 300 | << SSC_##name##_OFFSET) |
| 301 | #define SSC_BFEXT(name, value) \ |
| 302 | (((value) >> SSC_##name##_OFFSET) \ |
| 303 | & ((1 << SSC_##name##_SIZE) - 1)) |
| 304 | #define SSC_BFINS(name, value, old) \ |
| 305 | (((old) & ~(((1 << SSC_##name##_SIZE) - 1) \ |
| 306 | << SSC_##name##_OFFSET)) | SSC_BF(name, value)) |
| 307 | |
| 308 | /* Register access macros */ |
| 309 | #define ssc_readl(base, reg) __raw_readl(base + SSC_##reg) |
| 310 | #define ssc_writel(base, reg, value) __raw_writel((value), base + SSC_##reg) |
| 311 | |
| 312 | #endif /* __INCLUDE_ATMEL_SSC_H */ |