| Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | /* | 
|  | 2 | * arch/arm/mach-pxa/time.c | 
|  | 3 | * | 
| Bill Gatliff | 7bbb18c | 2007-07-21 03:39:36 +0100 | [diff] [blame] | 4 | * PXA clocksource, clockevents, and OST interrupt handlers. | 
|  | 5 | * Copyright (c) 2007 by Bill Gatliff <bgat@billgatliff.com>. | 
|  | 6 | * | 
|  | 7 | * Derived from Nicolas Pitre's PXA timer handler Copyright (c) 2001 | 
|  | 8 | * by MontaVista Software, Inc.  (Nico, your code rocks!) | 
| Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 9 | * | 
|  | 10 | * This program is free software; you can redistribute it and/or modify | 
|  | 11 | * it under the terms of the GNU General Public License version 2 as | 
|  | 12 | * published by the Free Software Foundation. | 
|  | 13 | */ | 
|  | 14 |  | 
| Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 15 | #include <linux/kernel.h> | 
|  | 16 | #include <linux/init.h> | 
| Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 17 | #include <linux/interrupt.h> | 
| Bill Gatliff | 7bbb18c | 2007-07-21 03:39:36 +0100 | [diff] [blame] | 18 | #include <linux/clockchips.h> | 
| Nicolas Pitre | 6c3a158 | 2007-08-17 16:55:22 +0100 | [diff] [blame] | 19 | #include <linux/sched.h> | 
| Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 20 |  | 
| Nicolas Pitre | 6c3a158 | 2007-08-17 16:55:22 +0100 | [diff] [blame] | 21 | #include <asm/div64.h> | 
| Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 22 | #include <asm/mach/irq.h> | 
|  | 23 | #include <asm/mach/time.h> | 
| Russell King | 7ce8301 | 2010-12-15 21:48:15 +0000 | [diff] [blame] | 24 | #include <asm/sched_clock.h> | 
| Eric Miao | 5bf3df3 | 2009-01-20 11:04:16 +0800 | [diff] [blame] | 25 | #include <mach/regs-ost.h> | 
| Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 26 |  | 
| Nicolas Pitre | 6c3a158 | 2007-08-17 16:55:22 +0100 | [diff] [blame] | 27 | /* | 
|  | 28 | * This is PXA's sched_clock implementation. This has a resolution | 
|  | 29 | * of at least 308 ns and a maximum value of 208 days. | 
|  | 30 | * | 
|  | 31 | * The return value is guaranteed to be monotonic in that range as | 
|  | 32 | * long as there is always less than 582 seconds between successive | 
|  | 33 | * calls to sched_clock() which should always be the case in practice. | 
|  | 34 | */ | 
| Russell King | 7ce8301 | 2010-12-15 21:48:15 +0000 | [diff] [blame] | 35 | static DEFINE_CLOCK_DATA(cd); | 
| Nicolas Pitre | 6c3a158 | 2007-08-17 16:55:22 +0100 | [diff] [blame] | 36 |  | 
| Russell King | 5e06b64 | 2010-12-15 19:19:25 +0000 | [diff] [blame] | 37 | unsigned long long notrace sched_clock(void) | 
| Nicolas Pitre | 6c3a158 | 2007-08-17 16:55:22 +0100 | [diff] [blame] | 38 | { | 
| Russell King | 7ce8301 | 2010-12-15 21:48:15 +0000 | [diff] [blame] | 39 | u32 cyc = OSCR; | 
|  | 40 | return cyc_to_sched_clock(&cd, cyc, (u32)~0); | 
|  | 41 | } | 
|  | 42 |  | 
|  | 43 | static void notrace pxa_update_sched_clock(void) | 
|  | 44 | { | 
|  | 45 | u32 cyc = OSCR; | 
|  | 46 | update_sched_clock(&cd, cyc, (u32)~0); | 
| Nicolas Pitre | 6c3a158 | 2007-08-17 16:55:22 +0100 | [diff] [blame] | 47 | } | 
|  | 48 |  | 
|  | 49 |  | 
| Russell King | a88264c | 2007-11-12 22:45:16 +0000 | [diff] [blame] | 50 | #define MIN_OSCR_DELTA 16 | 
|  | 51 |  | 
| Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 52 | static irqreturn_t | 
| Bill Gatliff | 7bbb18c | 2007-07-21 03:39:36 +0100 | [diff] [blame] | 53 | pxa_ost0_interrupt(int irq, void *dev_id) | 
| Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 54 | { | 
| Bill Gatliff | 7bbb18c | 2007-07-21 03:39:36 +0100 | [diff] [blame] | 55 | struct clock_event_device *c = dev_id; | 
| Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 56 |  | 
| Russell King | a88264c | 2007-11-12 22:45:16 +0000 | [diff] [blame] | 57 | /* Disarm the compare/match, signal the event. */ | 
|  | 58 | OIER &= ~OIER_E0; | 
|  | 59 | OSSR = OSSR_M0; | 
|  | 60 | c->event_handler(c); | 
| Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 61 |  | 
|  | 62 | return IRQ_HANDLED; | 
|  | 63 | } | 
|  | 64 |  | 
| Bill Gatliff | 7bbb18c | 2007-07-21 03:39:36 +0100 | [diff] [blame] | 65 | static int | 
|  | 66 | pxa_osmr0_set_next_event(unsigned long delta, struct clock_event_device *dev) | 
|  | 67 | { | 
| Uwe Kleine-König | a602f0f | 2009-12-17 12:43:29 +0100 | [diff] [blame] | 68 | unsigned long next, oscr; | 
| Bill Gatliff | 7bbb18c | 2007-07-21 03:39:36 +0100 | [diff] [blame] | 69 |  | 
| Bill Gatliff | 7bbb18c | 2007-07-21 03:39:36 +0100 | [diff] [blame] | 70 | OIER |= OIER_E0; | 
| Russell King | 91bc51d | 2007-11-08 23:35:46 +0000 | [diff] [blame] | 71 | next = OSCR + delta; | 
|  | 72 | OSMR0 = next; | 
|  | 73 | oscr = OSCR; | 
| Russell King | 91bc51d | 2007-11-08 23:35:46 +0000 | [diff] [blame] | 74 |  | 
|  | 75 | return (signed)(next - oscr) <= MIN_OSCR_DELTA ? -ETIME : 0; | 
| Bill Gatliff | 7bbb18c | 2007-07-21 03:39:36 +0100 | [diff] [blame] | 76 | } | 
|  | 77 |  | 
|  | 78 | static void | 
|  | 79 | pxa_osmr0_set_mode(enum clock_event_mode mode, struct clock_event_device *dev) | 
|  | 80 | { | 
| Bill Gatliff | 7bbb18c | 2007-07-21 03:39:36 +0100 | [diff] [blame] | 81 | switch (mode) { | 
| Bill Gatliff | 7bbb18c | 2007-07-21 03:39:36 +0100 | [diff] [blame] | 82 | case CLOCK_EVT_MODE_ONESHOT: | 
| Bill Gatliff | 7bbb18c | 2007-07-21 03:39:36 +0100 | [diff] [blame] | 83 | OIER &= ~OIER_E0; | 
| Russell King | 91bc51d | 2007-11-08 23:35:46 +0000 | [diff] [blame] | 84 | OSSR = OSSR_M0; | 
| Bill Gatliff | 7bbb18c | 2007-07-21 03:39:36 +0100 | [diff] [blame] | 85 | break; | 
|  | 86 |  | 
|  | 87 | case CLOCK_EVT_MODE_UNUSED: | 
|  | 88 | case CLOCK_EVT_MODE_SHUTDOWN: | 
|  | 89 | /* initializing, released, or preparing for suspend */ | 
| Bill Gatliff | 7bbb18c | 2007-07-21 03:39:36 +0100 | [diff] [blame] | 90 | OIER &= ~OIER_E0; | 
| Russell King | 91bc51d | 2007-11-08 23:35:46 +0000 | [diff] [blame] | 91 | OSSR = OSSR_M0; | 
| Bill Gatliff | 7bbb18c | 2007-07-21 03:39:36 +0100 | [diff] [blame] | 92 | break; | 
| Russell King | df43309 | 2007-10-27 15:15:49 +0100 | [diff] [blame] | 93 |  | 
|  | 94 | case CLOCK_EVT_MODE_RESUME: | 
| Russell King | a88264c | 2007-11-12 22:45:16 +0000 | [diff] [blame] | 95 | case CLOCK_EVT_MODE_PERIODIC: | 
| Russell King | df43309 | 2007-10-27 15:15:49 +0100 | [diff] [blame] | 96 | break; | 
| Bill Gatliff | 7bbb18c | 2007-07-21 03:39:36 +0100 | [diff] [blame] | 97 | } | 
|  | 98 | } | 
|  | 99 |  | 
|  | 100 | static struct clock_event_device ckevt_pxa_osmr0 = { | 
|  | 101 | .name		= "osmr0", | 
| Russell King | a88264c | 2007-11-12 22:45:16 +0000 | [diff] [blame] | 102 | .features	= CLOCK_EVT_FEAT_ONESHOT, | 
| Bill Gatliff | 7bbb18c | 2007-07-21 03:39:36 +0100 | [diff] [blame] | 103 | .rating		= 200, | 
| Bill Gatliff | 7bbb18c | 2007-07-21 03:39:36 +0100 | [diff] [blame] | 104 | .set_next_event	= pxa_osmr0_set_next_event, | 
|  | 105 | .set_mode	= pxa_osmr0_set_mode, | 
| Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 106 | }; | 
|  | 107 |  | 
| Bill Gatliff | 7bbb18c | 2007-07-21 03:39:36 +0100 | [diff] [blame] | 108 | static struct irqaction pxa_ost0_irq = { | 
|  | 109 | .name		= "ost0", | 
|  | 110 | .flags		= IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL, | 
|  | 111 | .handler	= pxa_ost0_interrupt, | 
|  | 112 | .dev_id		= &ckevt_pxa_osmr0, | 
|  | 113 | }; | 
|  | 114 |  | 
| Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 115 | static void __init pxa_timer_init(void) | 
|  | 116 | { | 
| Eric Miao | 6769717 | 2008-12-18 11:10:32 +0800 | [diff] [blame] | 117 | unsigned long clock_tick_rate = get_clock_tick_rate(); | 
| Russell King | 08197f6 | 2007-09-01 21:12:50 +0100 | [diff] [blame] | 118 |  | 
| Bill Gatliff | 7bbb18c | 2007-07-21 03:39:36 +0100 | [diff] [blame] | 119 | OIER = 0; | 
|  | 120 | OSSR = OSSR_M0 | OSSR_M1 | OSSR_M2 | OSSR_M3; | 
| Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 121 |  | 
| Russell King | 7ce8301 | 2010-12-15 21:48:15 +0000 | [diff] [blame] | 122 | init_sched_clock(&cd, pxa_update_sched_clock, 32, clock_tick_rate); | 
| Nicolas Pitre | 6c3a158 | 2007-08-17 16:55:22 +0100 | [diff] [blame] | 123 |  | 
| Haojian Zhuang | ccc46e2 | 2010-11-24 11:54:23 +0800 | [diff] [blame] | 124 | clockevents_calc_mult_shift(&ckevt_pxa_osmr0, clock_tick_rate, 4); | 
| Bill Gatliff | 7bbb18c | 2007-07-21 03:39:36 +0100 | [diff] [blame] | 125 | ckevt_pxa_osmr0.max_delta_ns = | 
|  | 126 | clockevent_delta2ns(0x7fffffff, &ckevt_pxa_osmr0); | 
|  | 127 | ckevt_pxa_osmr0.min_delta_ns = | 
| Russell King | dd01b2f | 2008-01-23 12:34:16 +0000 | [diff] [blame] | 128 | clockevent_delta2ns(MIN_OSCR_DELTA * 2, &ckevt_pxa_osmr0) + 1; | 
| Rusty Russell | 320ab2b | 2008-12-13 21:20:26 +1030 | [diff] [blame] | 129 | ckevt_pxa_osmr0.cpumask = cpumask_of(0); | 
| Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 130 |  | 
| Bill Gatliff | 7bbb18c | 2007-07-21 03:39:36 +0100 | [diff] [blame] | 131 | setup_irq(IRQ_OST0, &pxa_ost0_irq); | 
|  | 132 |  | 
| Russell King | 234b6ce | 2011-05-08 14:09:47 +0100 | [diff] [blame] | 133 | clocksource_mmio_init(&OSCR, "oscr0", clock_tick_rate, 200, 32, | 
|  | 134 | clocksource_mmio_readl_up); | 
| Bill Gatliff | 7bbb18c | 2007-07-21 03:39:36 +0100 | [diff] [blame] | 135 | clockevents_register_device(&ckevt_pxa_osmr0); | 
| Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 136 | } | 
|  | 137 |  | 
|  | 138 | #ifdef CONFIG_PM | 
| Russell King | 4ae7806 | 2007-11-12 22:48:12 +0000 | [diff] [blame] | 139 | static unsigned long osmr[4], oier, oscr; | 
| Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 140 |  | 
|  | 141 | static void pxa_timer_suspend(void) | 
|  | 142 | { | 
|  | 143 | osmr[0] = OSMR0; | 
|  | 144 | osmr[1] = OSMR1; | 
|  | 145 | osmr[2] = OSMR2; | 
|  | 146 | osmr[3] = OSMR3; | 
|  | 147 | oier = OIER; | 
| Russell King | 4ae7806 | 2007-11-12 22:48:12 +0000 | [diff] [blame] | 148 | oscr = OSCR; | 
| Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 149 | } | 
|  | 150 |  | 
|  | 151 | static void pxa_timer_resume(void) | 
|  | 152 | { | 
| Russell King | 4ae7806 | 2007-11-12 22:48:12 +0000 | [diff] [blame] | 153 | /* | 
|  | 154 | * Ensure that we have at least MIN_OSCR_DELTA between match | 
|  | 155 | * register 0 and the OSCR, to guarantee that we will receive | 
|  | 156 | * the one-shot timer interrupt.  We adjust OSMR0 in preference | 
|  | 157 | * to OSCR to guarantee that OSCR is monotonically incrementing. | 
|  | 158 | */ | 
|  | 159 | if (osmr[0] - oscr < MIN_OSCR_DELTA) | 
|  | 160 | osmr[0] += MIN_OSCR_DELTA; | 
|  | 161 |  | 
| Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 162 | OSMR0 = osmr[0]; | 
|  | 163 | OSMR1 = osmr[1]; | 
|  | 164 | OSMR2 = osmr[2]; | 
|  | 165 | OSMR3 = osmr[3]; | 
|  | 166 | OIER = oier; | 
| Russell King | 4ae7806 | 2007-11-12 22:48:12 +0000 | [diff] [blame] | 167 | OSCR = oscr; | 
| Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 168 | } | 
|  | 169 | #else | 
|  | 170 | #define pxa_timer_suspend NULL | 
|  | 171 | #define pxa_timer_resume NULL | 
|  | 172 | #endif | 
|  | 173 |  | 
|  | 174 | struct sys_timer pxa_timer = { | 
|  | 175 | .init		= pxa_timer_init, | 
|  | 176 | .suspend	= pxa_timer_suspend, | 
|  | 177 | .resume		= pxa_timer_resume, | 
| Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 178 | }; |