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review.evervolv.com / android_kernel_htc_msm8960 / 7febe2be36035e5c75128e8cc3baeb1f30fa2bc4 / . / arch / s390 / kernel / reipl64.S
blob: 9eabbc90795d832ee54710a91b958a71255cf081 [file] [log] [blame]
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]1/*
Heiko Carstensc70d0fe2009-03-26 15:24:57 +0100[diff] [blame]2 * Copyright IBM Corp 2000,2009
3 * Author(s): Holger Smolinski <Holger.Smolinski@de.ibm.com>,
4 * Denis Joseph Barrow,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]5 */
6
Heiko Carstenscbb870c2010-02-26 22:37:43 +0100[diff] [blame]7#include <asm/asm-offsets.h>
Heiko Carstensc5dd8582007-03-05 23:35:43 +0100[diff] [blame]8
9#
10# do_reipl_asm
11# Parameter: r2 = schid of reipl device
12#
13
Michael Holzheuff6b8ea2006-09-20 15:58:49 +0200[diff] [blame]14 .globl do_reipl_asm
15do_reipl_asm: basr %r13,0
Heiko Carstens15e9b582006-12-04 15:40:26 +0100[diff] [blame]16.Lpg0: lpswe .Lnewpsw-.Lpg0(%r13)
17.Lpg1: # do store status of all registers
Michael Holzheuff6b8ea2006-09-20 15:58:49 +0200[diff] [blame]18
Heiko Carstens15e9b582006-12-04 15:40:26 +0100[diff] [blame]19 stg %r1,.Lregsave-.Lpg0(%r13)
Michael Holzheuff6b8ea2006-09-20 15:58:49 +0200[diff] [blame]20 lghi %r1,0x1000
21 stmg %r0,%r15,__LC_GPREGS_SAVE_AREA-0x1000(%r1)
22 lg %r0,.Lregsave-.Lpg0(%r13)
23 stg %r0,__LC_GPREGS_SAVE_AREA-0x1000+8(%r1)
24 stctg %c0,%c15,__LC_CREGS_SAVE_AREA-0x1000(%r1)
25 stam %a0,%a15,__LC_AREGS_SAVE_AREA-0x1000(%r1)
Heiko Carstensc5dd8582007-03-05 23:35:43 +0100[diff] [blame]26 lg %r10,.Ldump_pfx-.Lpg0(%r13)
27 mvc __LC_PREFIX_SAVE_AREA-0x1000(4,%r1),0(%r10)
Michael Holzheuff6b8ea2006-09-20 15:58:49 +0200[diff] [blame]28 stfpc __LC_FP_CREG_SAVE_AREA-0x1000(%r1)
29 stckc .Lclkcmp-.Lpg0(%r13)
Heiko Carstensc70d0fe2009-03-26 15:24:57 +0100[diff] [blame]30 mvc __LC_CLOCK_COMP_SAVE_AREA-0x1000(7,%r1),.Lclkcmp-.Lpg0(%r13)
Michael Holzheuff6b8ea2006-09-20 15:58:49 +0200[diff] [blame]31 stpt __LC_CPU_TIMER_SAVE_AREA-0x1000(%r1)
32 stg %r13, __LC_PSW_SAVE_AREA-0x1000+8(%r1)
33
Heiko Carstens15e9b582006-12-04 15:40:26 +0100[diff] [blame]34 lctlg %c6,%c6,.Lall-.Lpg0(%r13)
Heiko Carstens25d83cb2006-09-28 16:56:37 +0200[diff] [blame]35 lgr %r1,%r2
36 mvc __LC_PGM_NEW_PSW(16),.Lpcnew-.Lpg0(%r13)
37 stsch .Lschib-.Lpg0(%r13)
38 oi .Lschib+5-.Lpg0(%r13),0x84
39.Lecs: xi .Lschib+27-.Lpg0(%r13),0x01
40 msch .Lschib-.Lpg0(%r13)
41 lghi %r0,5
42.Lssch: ssch .Liplorb-.Lpg0(%r13)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]43 jz .L001
Heiko Carstens25d83cb2006-09-28 16:56:37 +0200[diff] [blame]44 brct %r0,.Lssch
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]45 bas %r14,.Ldisab-.Lpg0(%r13)
Heiko Carstens25d83cb2006-09-28 16:56:37 +0200[diff] [blame]46.L001: mvc __LC_IO_NEW_PSW(16),.Lionew-.Lpg0(%r13)
47.Ltpi: lpswe .Lwaitpsw-.Lpg0(%r13)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]48.Lcont: c %r1,__LC_SUBCHANNEL_ID
49 jnz .Ltpi
50 clc __LC_IO_INT_PARM(4),.Liplorb-.Lpg0(%r13)
51 jnz .Ltpi
Heiko Carstens25d83cb2006-09-28 16:56:37 +0200[diff] [blame]52 tsch .Liplirb-.Lpg0(%r13)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]53 tm .Liplirb+9-.Lpg0(%r13),0xbf
Heiko Carstens25d83cb2006-09-28 16:56:37 +0200[diff] [blame]54 jz .L002
55 bas %r14,.Ldisab-.Lpg0(%r13)
56.L002: tm .Liplirb+8-.Lpg0(%r13),0xf3
57 jz .L003
58 bas %r14,.Ldisab-.Lpg0(%r13)
Heiko Carstens15e9b582006-12-04 15:40:26 +0100[diff] [blame]59.L003: st %r1,__LC_SUBCHANNEL_ID
Heiko Carstens25d83cb2006-09-28 16:56:37 +0200[diff] [blame]60 lhi %r1,0 # mode 0 = esa
61 slr %r0,%r0 # set cpuid to zero
62 sigp %r1,%r0,0x12 # switch to esa mode
63 lpsw 0
64.Ldisab: sll %r14,1
65 srl %r14,1 # need to kill hi bit to avoid specification exceptions.
66 st %r14,.Ldispsw+12-.Lpg0(%r13)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]67 lpswe .Ldispsw-.Lpg0(%r13)
Heiko Carstens25d83cb2006-09-28 16:56:37 +0200[diff] [blame]68 .align 8
Michael Holzheuff6b8ea2006-09-20 15:58:49 +0200[diff] [blame]69.Lclkcmp: .quad 0x0000000000000000
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]70.Lall: .quad 0x00000000ff000000
Heiko Carstensc5dd8582007-03-05 23:35:43 +0100[diff] [blame]71.Ldump_pfx: .quad dump_prefix_page
Michael Holzheuff6b8ea2006-09-20 15:58:49 +0200[diff] [blame]72.Lregsave: .quad 0x0000000000000000
Heiko Carstens25d83cb2006-09-28 16:56:37 +0200[diff] [blame]73 .align 16
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]74/*
75 * These addresses have to be 31 bit otherwise
76 * the sigp will throw a specifcation exception
77 * when switching to ESA mode as bit 31 be set
78 * in the ESA psw.
79 * Bit 31 of the addresses has to be 0 for the
80 * 31bit lpswe instruction a fact they appear to have
Lucas De Marchi25985ed2011-03-30 22:57:33 -0300[diff] [blame]81 * omitted from the pop.
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]82 */
Heiko Carstens25d83cb2006-09-28 16:56:37 +0200[diff] [blame]83.Lnewpsw: .quad 0x0000000080000000
84 .quad .Lpg1
85.Lpcnew: .quad 0x0000000080000000
86 .quad .Lecs
87.Lionew: .quad 0x0000000080000000
88 .quad .Lcont
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]89.Lwaitpsw: .quad 0x0202000080000000
Heiko Carstens25d83cb2006-09-28 16:56:37 +0200[diff] [blame]90 .quad .Ltpi
91.Ldispsw: .quad 0x0002000080000000
92 .quad 0x0000000000000000
93.Liplccws: .long 0x02000000,0x60000018
94 .long 0x08000008,0x20000001
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]95.Liplorb: .long 0x0049504c,0x0040ff80
96 .long 0x00000000+.Liplccws
Heiko Carstens25d83cb2006-09-28 16:56:37 +0200[diff] [blame]97.Lschib: .long 0x00000000,0x00000000
98 .long 0x00000000,0x00000000
99 .long 0x00000000,0x00000000
100 .long 0x00000000,0x00000000
101 .long 0x00000000,0x00000000
102 .long 0x00000000,0x00000000
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]103.Liplirb: .long 0x00000000,0x00000000
104 .long 0x00000000,0x00000000
105 .long 0x00000000,0x00000000
106 .long 0x00000000,0x00000000
107 .long 0x00000000,0x00000000
108 .long 0x00000000,0x00000000
109 .long 0x00000000,0x00000000
110 .long 0x00000000,0x00000000