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David Gibsonea20ff52007-05-08 14:09:18 +10001/*
2 * Device Tree Source for IBM Ebony
3 *
4 * Copyright (c) 2006, 2007 IBM Corp.
5 * Josh Boyer <jwboyer@linux.vnet.ibm.com>, David Gibson <dwg@au1.ibm.com>
6 *
7 * FIXME: Draft only!
8 *
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without
11 * any warranty of any kind, whether express or implied.
12 *
13 * To build:
14 * dtc -I dts -O asm -o ebony.S -b 0 ebony.dts
15 * dtc -I dts -O dtb -o ebony.dtb -b 0 ebony.dts
16 */
17
18/ {
19 #address-cells = <2>;
20 #size-cells = <1>;
21 model = "ibm,ebony";
22 compatible = "ibm,ebony";
23 dcr-parent = <&/cpus/PowerPC,440GP@0>;
24
25 cpus {
26 #address-cells = <1>;
27 #size-cells = <0>;
28
29 PowerPC,440GP@0 {
30 device_type = "cpu";
31 reg = <0>;
32 clock-frequency = <0>; // Filled in by zImage
33 timebase-frequency = <0>; // Filled in by zImage
Li Yang8203c172007-07-10 16:59:39 +100034 i-cache-line-size = <20>;
35 d-cache-line-size = <20>;
David Gibsonc72ea772007-05-16 13:48:50 +100036 i-cache-size = <8000>; /* 32 kB */
37 d-cache-size = <8000>; /* 32 kB */
David Gibsonea20ff52007-05-08 14:09:18 +100038 dcr-controller;
39 dcr-access-method = "native";
40 };
41 };
42
43 memory {
44 device_type = "memory";
45 reg = <0 0 0>; // Filled in by zImage
46 };
47
48 UIC0: interrupt-controller0 {
David Gibsonea20ff52007-05-08 14:09:18 +100049 compatible = "ibm,uic-440gp", "ibm,uic";
50 interrupt-controller;
51 cell-index = <0>;
52 dcr-reg = <0c0 009>;
53 #address-cells = <0>;
54 #size-cells = <0>;
55 #interrupt-cells = <2>;
56
57 };
58
59 UIC1: interrupt-controller1 {
David Gibsonea20ff52007-05-08 14:09:18 +100060 compatible = "ibm,uic-440gp", "ibm,uic";
61 interrupt-controller;
62 cell-index = <1>;
63 dcr-reg = <0d0 009>;
64 #address-cells = <0>;
65 #size-cells = <0>;
66 #interrupt-cells = <2>;
67 interrupts = <1e 4 1f 4>; /* cascade */
68 interrupt-parent = <&UIC0>;
69 };
70
71 CPC0: cpc {
David Gibsonea20ff52007-05-08 14:09:18 +100072 compatible = "ibm,cpc-440gp";
73 dcr-reg = <0b0 003 0e0 010>;
74 // FIXME: anything else?
75 };
76
77 plb {
David Gibsonea20ff52007-05-08 14:09:18 +100078 compatible = "ibm,plb-440gp", "ibm,plb4";
79 #address-cells = <2>;
80 #size-cells = <1>;
81 ranges;
82 clock-frequency = <0>; // Filled in by zImage
83
David Gibsonc72ea772007-05-16 13:48:50 +100084 SDRAM0: memory-controller {
85 compatible = "ibm,sdram-440gp";
David Gibsonea20ff52007-05-08 14:09:18 +100086 dcr-reg = <010 2>;
87 // FIXME: anything else?
88 };
89
David Gibsonc72ea772007-05-16 13:48:50 +100090 SRAM0: sram {
91 compatible = "ibm,sram-440gp";
92 dcr-reg = <020 8 00a 1>;
93 };
94
David Gibsonea20ff52007-05-08 14:09:18 +100095 DMA0: dma {
96 // FIXME: ???
David Gibsonc72ea772007-05-16 13:48:50 +100097 compatible = "ibm,dma-440gp";
David Gibsonea20ff52007-05-08 14:09:18 +100098 dcr-reg = <100 027>;
99 };
100
101 MAL0: mcmal {
David Gibsonea20ff52007-05-08 14:09:18 +1000102 compatible = "ibm,mcmal-440gp", "ibm,mcmal";
103 dcr-reg = <180 62>;
104 num-tx-chans = <4>;
105 num-rx-chans = <4>;
106 interrupt-parent = <&MAL0>;
107 interrupts = <0 1 2 3 4>;
108 #interrupt-cells = <1>;
109 #address-cells = <0>;
110 #size-cells = <0>;
111 interrupt-map = </*TXEOB*/ 0 &UIC0 a 4
112 /*RXEOB*/ 1 &UIC0 b 4
113 /*SERR*/ 2 &UIC1 0 4
114 /*TXDE*/ 3 &UIC1 1 4
115 /*RXDE*/ 4 &UIC1 2 4>;
116 interrupt-map-mask = <ffffffff>;
117 };
118
119 POB0: opb {
David Gibsonea20ff52007-05-08 14:09:18 +1000120 compatible = "ibm,opb-440gp", "ibm,opb";
121 #address-cells = <1>;
122 #size-cells = <1>;
123 /* Wish there was a nicer way of specifying a full 32-bit
124 range */
125 ranges = <00000000 1 00000000 80000000
126 80000000 1 80000000 80000000>;
127 dcr-reg = <090 00b>;
128 interrupt-parent = <&UIC1>;
129 interrupts = <7 4>;
130 clock-frequency = <0>; // Filled in by zImage
131
132 EBC0: ebc {
David Gibsonc72ea772007-05-16 13:48:50 +1000133 compatible = "ibm,ebc-440gp", "ibm,ebc";
David Gibsonea20ff52007-05-08 14:09:18 +1000134 dcr-reg = <012 2>;
135 #address-cells = <2>;
136 #size-cells = <1>;
137 clock-frequency = <0>; // Filled in by zImage
David Gibsonb2ba34f2007-06-13 14:52:59 +1000138 // ranges property is supplied by zImage
139 // based on firmware's configuration of the
140 // EBC bridge
David Gibsonea20ff52007-05-08 14:09:18 +1000141 interrupts = <5 4>;
142 interrupt-parent = <&UIC1>;
143
David Gibsonc72ea772007-05-16 13:48:50 +1000144 small-flash@0,80000 {
David Gibsonea20ff52007-05-08 14:09:18 +1000145 device_type = "rom";
146 compatible = "direct-mapped";
147 probe-type = "JEDEC";
148 bank-width = <1>;
149 partitions = <0 80000>;
150 partition-names = "OpenBIOS";
151 reg = <0 80000 80000>;
152 };
153
154 ds1743@1,0 {
155 /* NVRAM & RTC */
David Gibsonea20ff52007-05-08 14:09:18 +1000156 compatible = "ds1743";
157 reg = <1 0 2000>;
158 };
159
160 large-flash@2,0 {
161 device_type = "rom";
162 compatible = "direct-mapped";
163 probe-type = "JEDEC";
164 bank-width = <1>;
165 partitions = <0 380000
David Gibsonc72ea772007-05-16 13:48:50 +1000166 380000 80000>;
David Gibsonea20ff52007-05-08 14:09:18 +1000167 partition-names = "fs", "firmware";
168 reg = <2 0 400000>;
169 };
170
171 ir@3,0 {
172 reg = <3 0 10>;
173 };
174
175 fpga@7,0 {
176 compatible = "Ebony-FPGA";
177 reg = <7 0 10>;
178 };
179 };
180
181 UART0: serial@40000200 {
182 device_type = "serial";
183 compatible = "ns16550";
184 reg = <40000200 8>;
185 virtual-reg = <e0000200>;
186 clock-frequency = <A8C000>;
187 current-speed = <2580>;
188 interrupt-parent = <&UIC0>;
189 interrupts = <0 4>;
190 };
191
192 UART1: serial@40000300 {
193 device_type = "serial";
194 compatible = "ns16550";
195 reg = <40000300 8>;
196 virtual-reg = <e0000300>;
197 clock-frequency = <A8C000>;
198 current-speed = <2580>;
199 interrupt-parent = <&UIC0>;
200 interrupts = <1 4>;
201 };
202
203 IIC0: i2c@40000400 {
204 /* FIXME */
205 device_type = "i2c";
206 compatible = "ibm,iic-440gp", "ibm,iic";
207 reg = <40000400 14>;
208 interrupt-parent = <&UIC0>;
209 interrupts = <2 4>;
210 };
211 IIC1: i2c@40000500 {
212 /* FIXME */
213 device_type = "i2c";
214 compatible = "ibm,iic-440gp", "ibm,iic";
215 reg = <40000500 14>;
216 interrupt-parent = <&UIC0>;
217 interrupts = <3 4>;
218 };
219
220 GPIO0: gpio@40000700 {
221 /* FIXME */
David Gibsonea20ff52007-05-08 14:09:18 +1000222 compatible = "ibm,gpio-440gp";
223 reg = <40000700 20>;
224 };
225
226 ZMII0: emac-zmii@40000780 {
David Gibsonea20ff52007-05-08 14:09:18 +1000227 compatible = "ibm,zmii-440gp", "ibm,zmii";
228 reg = <40000780 c>;
229 };
230
231 EMAC0: ethernet@40000800 {
232 linux,network-index = <0>;
233 device_type = "network";
234 compatible = "ibm,emac-440gp", "ibm,emac";
235 interrupt-parent = <&UIC1>;
236 interrupts = <1c 4 1d 4>;
237 reg = <40000800 70>;
238 local-mac-address = [000000000000]; // Filled in by zImage
239 mal-device = <&MAL0>;
240 mal-tx-channel = <0 1>;
241 mal-rx-channel = <0>;
242 cell-index = <0>;
243 max-frame-size = <5dc>;
244 rx-fifo-size = <1000>;
245 tx-fifo-size = <800>;
246 phy-mode = "rmii";
247 phy-map = <00000001>;
248 zmii-device = <&ZMII0>;
249 zmii-channel = <0>;
250 };
251 EMAC1: ethernet@40000900 {
252 linux,network-index = <1>;
253 device_type = "network";
254 compatible = "ibm,emac-440gp", "ibm,emac";
255 interrupt-parent = <&UIC1>;
256 interrupts = <1e 4 1f 4>;
257 reg = <40000900 70>;
258 local-mac-address = [000000000000]; // Filled in by zImage
259 mal-device = <&MAL0>;
260 mal-tx-channel = <2 3>;
261 mal-rx-channel = <1>;
262 cell-index = <1>;
263 max-frame-size = <5dc>;
264 rx-fifo-size = <1000>;
265 tx-fifo-size = <800>;
266 phy-mode = "rmii";
267 phy-map = <00000001>;
268 zmii-device = <&ZMII0>;
269 zmii-channel = <1>;
270 };
271
272
273 GPT0: gpt@40000a00 {
274 /* FIXME */
275 reg = <40000a00 d4>;
276 interrupt-parent = <&UIC0>;
277 interrupts = <12 4 13 4 14 4 15 4 16 4>;
278 };
279
280 };
281
282 PCIX0: pci@1234 {
283 device_type = "pci";
284 /* FIXME */
285 reg = <2 0ec00000 8
286 2 0ec80000 f0
287 2 0ec80100 fc>;
288 };
289 };
290
291 chosen {
292 linux,stdout-path = "/plb/opb/serial@40000200";
David Gibsonea20ff52007-05-08 14:09:18 +1000293 };
294};