blob: 8f8deac32da7a64a311c87a25d6bb6fdaefb95eb [file] [log] [blame]
Sathish Ambley9d69ac32012-03-21 10:28:26 -07001/* Copyright (c) 2012, Code Aurora Forum. All rights reserved.
2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 */
Sathish Ambley4df614c2011-10-07 16:30:46 -070012
13/include/ "skeleton.dtsi"
Abhimanyu Kapur90ced6e2012-06-26 17:41:25 -070014/include/ "msm8974_pm.dtsi"
David Collinsb20f6362012-04-19 16:36:51 -070015/include/ "msm-pm8x41-rpm-regulator.dtsi"
David Collins153d45a2012-03-26 11:57:50 -070016/include/ "msm-pm8841.dtsi"
17/include/ "msm-pm8941.dtsi"
Abhimanyu Kapur90ced6e2012-06-26 17:41:25 -070018/include/ "msm8974-regulator.dtsi"
19/include/ "msm8974-gpio.dtsi"
20/include/ "msm8974-iommu.dtsi"
Matt Wagantallfc727212012-01-06 18:18:25 -080021/include/ "msm-gdsc.dtsi"
Sathish Ambley4df614c2011-10-07 16:30:46 -070022
23/ {
Abhimanyu Kapur90ced6e2012-06-26 17:41:25 -070024 model = "Qualcomm MSM 8974";
25 compatible = "qcom,msm8974";
Sathish Ambley4df614c2011-10-07 16:30:46 -070026 interrupt-parent = <&intc>;
27
28 intc: interrupt-controller@F9000000 {
29 compatible = "qcom,msm-qgic2";
30 interrupt-controller;
Michael Bohanc7224532012-01-06 16:02:52 -080031 #interrupt-cells = <3>;
Sathish Ambley4df614c2011-10-07 16:30:46 -070032 reg = <0xF9000000 0x1000>,
33 <0xF9002000 0x1000>;
34 };
Sathish Ambley3d50c762011-10-25 15:26:00 -070035
Sathish Ambleye046b242012-04-09 12:38:05 -070036 msmgpio: gpio@fd510000 {
Michael Bohan0425f6f2012-01-17 14:36:39 -080037 compatible = "qcom,msm-gpio";
38 interrupt-controller;
39 #interrupt-cells = <2>;
Sathish Ambleye046b242012-04-09 12:38:05 -070040 reg = <0xfd510000 0x4000>;
41 #gpio-cells = <2>;
Michael Bohan0425f6f2012-01-17 14:36:39 -080042 };
43
Sathish Ambley098f9bd2011-11-09 16:32:53 -080044 timer {
Sathish Ambley2f27a172012-03-16 10:46:28 -070045 compatible = "qcom,msm-qtimer", "arm,armv7-timer";
Sathish Ambleyddd099e2012-04-25 13:24:47 -070046 interrupts = <1 2 0 1 3 0>;
Sathish Ambley2f27a172012-03-16 10:46:28 -070047 clock-frequency = <19200000>;
Sathish Ambley098f9bd2011-11-09 16:32:53 -080048 };
49
Praneeth Paladugu4b73ec82012-02-08 12:55:59 -080050 qcom,vidc@fdc00000 {
51 compatible = "qcom,msm-vidc";
52 reg = <0xfdc00000 0xff000>;
53 interrupts = <0 44 0>;
54 };
55
David Brown225abee2012-02-09 22:28:50 -080056 serial@f991f000 {
Sathish Ambley3d50c762011-10-25 15:26:00 -070057 compatible = "qcom,msm-lsuart-v14";
David Brown225abee2012-02-09 22:28:50 -080058 reg = <0xf991f000 0x1000>;
Michael Bohanc7224532012-01-06 16:02:52 -080059 interrupts = <0 109 0>;
Sathish Ambley3d50c762011-10-25 15:26:00 -070060 };
Pavankumar Kondetieaea7fe2011-10-27 14:46:45 +053061
Sathish Ambley9d69ac32012-03-21 10:28:26 -070062 serial@f995e000 {
63 compatible = "qcom,msm-lsuart-v14";
64 reg = <0xf995e000 0x1000>;
65 interrupts = <0 114 0>;
66 };
67
David Brown225abee2012-02-09 22:28:50 -080068 usb@f9a55000 {
Pavankumar Kondetieaea7fe2011-10-27 14:46:45 +053069 compatible = "qcom,hsusb-otg";
David Brown225abee2012-02-09 22:28:50 -080070 reg = <0xf9a55000 0x400>;
Michael Bohanc7224532012-01-06 16:02:52 -080071 interrupts = <0 134 0>;
Michael Bohane66a3a92012-03-26 12:47:28 -070072 HSUSB_VDDCX-supply = <&pm8841_s2>;
73 HSUSB_1p8-supply = <&pm8941_l6>;
74 HSUSB_3p3-supply = <&pm8941_l24>;
Pavankumar Kondetieaea7fe2011-10-27 14:46:45 +053075
76 qcom,hsusb-otg-phy-type = <2>;
77 qcom,hsusb-otg-mode = <1>;
78 qcom,hsusb-otg-otg-control = <1>;
79 };
Sujit Reddy Thumma7285c2e2011-11-04 10:18:15 +053080
Sujit Reddy Thumma85fc52c2012-05-02 12:53:45 +053081 qcom,sdcc@f9824000 {
Sujit Reddy Thumma7285c2e2011-11-04 10:18:15 +053082 cell-index = <1>;
83 compatible = "qcom,msm-sdcc";
Sujit Reddy Thumma85fc52c2012-05-02 12:53:45 +053084 reg = <0xf9824000 0x1000>;
Michael Bohanc7224532012-01-06 16:02:52 -080085 interrupts = <0 123 0>;
Sujit Reddy Thummab9ff7f02012-05-04 09:57:49 +053086 vdd-supply = <&pm8941_l20>;
87 vdd-io-supply = <&pm8941_s3>;
88
89 qcom,sdcc-vdd-voltage_level = <2950000 2950000>;
90 qcom,sdcc-vdd-current_level = <800 500000>;
91
92 qcom,sdcc-vdd-io-always_on;
93 qcom,sdcc-vdd-io-voltage_level = <1800000 1800000>;
94 qcom,sdcc-vdd-io-current_level = <250 154000>;
Sujit Reddy Thumma7285c2e2011-11-04 10:18:15 +053095
Sujit Reddy Thumma85fc52c2012-05-02 12:53:45 +053096 qcom,sdcc-clk-rates = <400000 25000000 50000000 100000000 200000000>;
97 qcom,sdcc-sup-voltages = <2950 2950>;
Sujit Reddy Thumma7285c2e2011-11-04 10:18:15 +053098 qcom,sdcc-bus-width = <8>;
99 qcom,sdcc-nonremovable;
Sujit Reddy Thumma824b7522012-05-30 13:04:34 +0530100 qcom,sdcc-bus-speed-mode = "HS200_1p8v", "DDR_1p8v";
Sujit Reddy Thumma7285c2e2011-11-04 10:18:15 +0530101 };
102
Sujit Reddy Thumma85fc52c2012-05-02 12:53:45 +0530103 qcom,sdcc@f98a4000 {
104 cell-index = <2>;
105 compatible = "qcom,msm-sdcc";
106 reg = <0xf98a4000 0x1000>;
107 interrupts = <0 125 0>;
Sujit Reddy Thummab9ff7f02012-05-04 09:57:49 +0530108 vdd-supply = <&pm8941_l21>;
109 vdd-io-supply = <&pm8941_l13>;
110
111 qcom,sdcc-vdd-voltage_level = <2950000 2950000>;
112 qcom,sdcc-vdd-current_level = <9000 800000>;
113
114 qcom,sdcc-vdd-io-always_on;
115 qcom,sdcc-vdd-io-lpm_sup;
116 qcom,sdcc-vdd-io-voltage_level = <1800000 2950000>;
117 qcom,sdcc-vdd-io-current_level = <6 22000>;
Sujit Reddy Thumma85fc52c2012-05-02 12:53:45 +0530118
119 qcom,sdcc-clk-rates = <400000 25000000 50000000 100000000 200000000>;
120 qcom,sdcc-sup-voltages = <2950 2950>;
121 qcom,sdcc-bus-width = <4>;
Sujit Reddy Thumma824b7522012-05-30 13:04:34 +0530122 qcom,sdcc-xpc;
123 qcom,sdcc-bus-speed-mode = "SDR12", "SDR25", "SDR50", "DDR50", "SDR104";
124 qcom,sdcc-current-limit = <800>;
Sujit Reddy Thumma85fc52c2012-05-02 12:53:45 +0530125 };
126
127 qcom,sdcc@f9864000 {
Sujit Reddy Thumma7285c2e2011-11-04 10:18:15 +0530128 cell-index = <3>;
129 compatible = "qcom,msm-sdcc";
Sujit Reddy Thumma85fc52c2012-05-02 12:53:45 +0530130 reg = <0xf9864000 0x1000>;
Michael Bohanc7224532012-01-06 16:02:52 -0800131 interrupts = <0 127 0>;
Sujit Reddy Thumma7285c2e2011-11-04 10:18:15 +0530132
Sujit Reddy Thumma85fc52c2012-05-02 12:53:45 +0530133 qcom,sdcc-clk-rates = <400000 25000000 50000000 100000000>;
134 qcom,sdcc-sup-voltages = <1800 1800>;
Sujit Reddy Thumma7285c2e2011-11-04 10:18:15 +0530135 qcom,sdcc-bus-width = <4>;
Sujit Reddy Thumma824b7522012-05-30 13:04:34 +0530136 qcom,sdcc-bus-speed-mode = "SDR12", "SDR25", "SDR50", "DDR50";
Sujit Reddy Thumma7138b3e2012-06-04 09:10:11 +0530137 status = "disable";
Sujit Reddy Thumma85fc52c2012-05-02 12:53:45 +0530138 };
139
140 qcom,sdcc@f98e4000 {
141 cell-index = <4>;
142 compatible = "qcom,msm-sdcc";
143 reg = <0xf98e4000 0x1000>;
144 interrupts = <0 129 0>;
145
146 qcom,sdcc-clk-rates = <400000 25000000 50000000 100000000>;
147 qcom,sdcc-sup-voltages = <1800 1800>;
148 qcom,sdcc-bus-width = <4>;
Sujit Reddy Thumma824b7522012-05-30 13:04:34 +0530149 qcom,sdcc-bus-speed-mode = "SDR12", "SDR25", "SDR50", "DDR50";
Sujit Reddy Thumma7138b3e2012-06-04 09:10:11 +0530150 status = "disable";
Sujit Reddy Thumma7285c2e2011-11-04 10:18:15 +0530151 };
Yan He1466daa2011-11-30 17:25:38 -0800152
David Brown225abee2012-02-09 22:28:50 -0800153 qcom,sps@f9980000 {
Yan He1466daa2011-11-30 17:25:38 -0800154 compatible = "qcom,msm_sps";
David Brown225abee2012-02-09 22:28:50 -0800155 reg = <0xf9984000 0x15000>,
156 <0xf9999000 0xb000>;
Michael Bohanc7224532012-01-06 16:02:52 -0800157 interrupts = <0 94 0>;
Yan He1466daa2011-11-30 17:25:38 -0800158
159 qcom,bam-dma-res-pipes = <6>;
160 };
161
Hariprasad Dhalinarasimhade991f02012-05-31 13:15:51 -0700162
Harini Jayaraman5f98dbb2011-12-20 13:38:19 -0700163 spi@f9924000 {
164 compatible = "qcom,spi-qup-v2";
165 reg = <0xf9924000 0x1000>;
Michael Bohan857c8ac2012-01-23 16:57:34 -0800166 interrupts = <0 96 0>;
Vikram Mulukutla703e5722012-05-24 21:53:40 -0700167 spi-max-frequency = <25000000>;
Harini Jayaraman5f98dbb2011-12-20 13:38:19 -0700168 };
Kenneth Heitkef3c829c2012-01-13 17:02:43 -0700169
Sagar Dhariaa316a962012-03-21 16:13:22 -0600170 slim@fe12f000 {
171 cell-index = <1>;
172 compatible = "qcom,slim-msm";
173 reg = <0xfe12f000 0x35000>,
174 <0xfe104000 0x20000>;
175 reg-names = "slimbus_physical", "slimbus_bam_physical";
176 interrupts = <0 163 0 0 164 0>;
177 interrupt-names = "slimbus_irq", "slimbus_bam_irq";
178 qcom,min-clk-gear = <10>;
179 };
180
Kenneth Heitkef3c829c2012-01-13 17:02:43 -0700181 qcom,spmi@fc4c0000 {
182 cell-index = <0>;
183 compatible = "qcom,spmi-pmic-arb";
184 reg = <0xfc4cf000 0x1000>,
185 <0Xfc4cb000 0x1000>;
186 /* 190,ee0_krait_hlos_spmi_periph_irq */
187 /* 187,channel_0_krait_hlos_trans_done_irq */
188 interrupts = <0 190 0 0 187 0>;
189 qcom,pmic-arb-ee = <0>;
190 qcom,pmic-arb-channel = <0>;
Gilad Avidova11c0b52012-02-15 15:30:49 -0700191 qcom,pmic-arb-ppid-map = <0x13000000>, /* PM8941_LDO1 */
192 <0x13100001>, /* PM8941_LDO2 */
193 <0x13200002>, /* PM8941_LDO3 */
194 <0x13300003>, /* PM8941_LDO4 */
195 <0x13400004>, /* PM8941_LDO5 */
196 <0x13500005>, /* PM8941_LDO6 */
197 <0x13600006>, /* PM8941_LDO7 */
198 <0x13700007>, /* PM8941_LDO8 */
199 <0x13800008>, /* PM8941_LDO9 */
200 <0x13900009>, /* PM8941_LDO10 */
201 <0x13a0000a>, /* PM8941_LDO11 */
202 <0x13b0000b>, /* PM8941_LDO12 */
203 <0x13c0000c>, /* PM8941_LDO13 */
204 <0x13d0000d>, /* PM8941_LDO14 */
205 <0x13e0000e>, /* PM8941_LDO15 */
206 <0x13f0000f>, /* PM8941_LDO16 */
207 <0x14000010>, /* PM8941_LDO17 */
208 <0x14100011>, /* PM8941_LDO18 */
209 <0x14200012>, /* PM8941_LDO19 */
210 <0x14300013>, /* PM8941_LDO20 */
211 <0x14400014>, /* PM8941_LDO21 */
212 <0x14500015>, /* PM8941_LDO22 */
213 <0x14600016>, /* PM8941_LDO23 */
214 <0x14700017>, /* PM8941_LDO24 */
215 <0x14800018>, /* PM8941_LDO25 */
216 <0x14900019>, /* PM8941_LDO26 */
217 <0x0c00001a>, /* PM8941_GPIO1 */
218 <0x0c10001b>, /* PM8941_GPIO2 */
219 <0x0c20001c>, /* PM8941_GPIO3 */
220 <0x0c30001d>, /* PM8941_GPIO4 */
221 <0x0c40001e>, /* PM8941_GPIO5 */
222 <0x0c50001f>, /* PM8941_GPIO6 */
223 <0x0c600020>, /* PM8941_GPIO7 */
224 <0x0c700021>, /* PM8941_GPIO8 */
225 <0x0c800022>, /* PM8941_GPIO9 */
226 <0x0c900023>, /* PM8941_GPIO10 */
227 <0x0ca00024>, /* PM8941_GPIO11 */
228 <0x0cb00025>, /* PM8941_GPIO12 */
229 <0x0cc00026>, /* PM8941_GPIO13 */
230 <0x0cd00027>, /* PM8941_GPIO14 */
231 <0x0ce00028>, /* PM8941_GPIO15 */
232 <0x0cf00029>, /* PM8941_GPIO16 */
233 <0x0d00002a>, /* PM8941_GPIO17 */
234 <0x0d10002b>, /* PM8941_GPIO18 */
235 <0x0d20002c>, /* PM8941_GPIO19 */
236 <0x0d30002d>, /* PM8941_GPIO20 */
237 <0x0d40002e>, /* PM8941_GPIO21 */
238 <0x0d50002f>, /* PM8941_GPIO22 */
239 <0x0d600030>, /* PM8941_GPIO23 */
240 <0x0d700031>, /* PM8941_GPIO24 */
241 <0x0d800032>, /* PM8941_GPIO25 */
242 <0x0d900033>, /* PM8941_GPIO26 */
243 <0x0da00034>, /* PM8941_GPIO27 */
244 <0x0db00035>, /* PM8941_GPIO28 */
245 <0x0dc00036>, /* PM8941_GPIO29 */
246 <0x0dd00037>, /* PM8941_GPIO30 */
247 <0x0de00038>, /* PM8941_GPIO31 */
248 <0x0df00039>, /* PM8941_GPIO32 */
249 <0x0e00003a>, /* PM8941_GPIO33 */
250 <0x0e10003b>, /* PM8941_GPIO34 */
251 <0x0e20003c>, /* PM8941_GPIO35 */
252 <0x0e30003d>, /* PM8941_GPIO36 */
253 <0x0280003e>, /* COINCELL */
254 <0x0100003f>, /* SMBC_OVP */
255 <0x01100040>, /* SMBC_CHG */
256 <0x01200041>, /* SMBC_BIF */
257 <0x00500042>, /* INTERRUPT */
258 <0x00100043>, /* PM8941_0 */
259 <0x20100044>, /* PM8841_0 */
260 <0x10100045>, /* PM8941_1 */
261 <0x30100046>, /* PM8841_1 */
262 <0x00800047>, /* PON0 */
263 <0x20800048>, /* PON1 */
264 <0x11000049>, /* PM8941_SMPS1 */
265 <0x1110004a>, /* PM8941_SMPS2 */
266 <0x1120004b>, /* PM8941_SMPS3 */
267 <0x3100004c>, /* PM8841_SMPS1 */
268 <0x3110004d>, /* PM8841_SMPS2 */
269 <0x3120004e>, /* PM8841_SMPS3 */
270 <0x3130004f>, /* PM8841_SMPS4 */
271 <0x31400050>, /* PM8841_SMPS5 */
272 <0x31500051>, /* PM8841_SMPS6 */
273 <0x31600052>, /* PM8841_SMPS7 */
274 <0x31700053>, /* PM8841_SMPS8 */
275 <0x05000054>, /* SHARED_XO */
276 <0x05100055>, /* BB_CLK1 */
277 <0x05200056>, /* BB_CLK2 */
278 <0x05900057>, /* SLEEP_CLK */
279 <0x07000058>, /* PBS_CORE */
280 <0x07100059>, /* PBS_CLIENT1 */
281 <0x0720005a>; /* PBS_CLIENT2 */
Kenneth Heitkef3c829c2012-01-13 17:02:43 -0700282 };
Sagar Dharia218edb92012-01-15 18:03:01 -0700283
284 i2c@f9966000 {
285 cell-index = <0>;
286 compatible = "qcom,i2c-qup";
287 reg = <0Xf9966000 0x1000>;
288 reg-names = "qup_phys_addr";
289 interrupts = <0 104 0>;
290 interrupt-names = "qup_err_intr";
291 qcom,i2c-bus-freq = <100000>;
292 qcom,i2c-src-freq = <24000000>;
293 };
Matt Wagantalle9b715a2012-01-04 18:16:14 -0800294
Matt Wagantall48523022012-04-23 13:28:42 -0700295 qcom,acpuclk@f9000000 {
Abhimanyu Kapur90ced6e2012-06-26 17:41:25 -0700296 compatible = "qcom,acpuclk-8974";
Matt Wagantallbf9eb2c2012-05-31 09:44:22 -0700297 krait0-supply = <&krait0_vreg>;
298 krait1-supply = <&krait1_vreg>;
299 krait2-supply = <&krait2_vreg>;
300 krait3-supply = <&krait3_vreg>;
David Collins1c91ea72012-05-03 16:17:35 -0700301 krait0_mem-supply = <&pm8841_s1_ao>;
302 krait1_mem-supply = <&pm8841_s1_ao>;
303 krait2_mem-supply = <&pm8841_s1_ao>;
304 krait3_mem-supply = <&pm8841_s1_ao>;
305 krait0_dig-supply = <&pm8841_s2_corner_ao>;
306 krait1_dig-supply = <&pm8841_s2_corner_ao>;
307 krait2_dig-supply = <&pm8841_s2_corner_ao>;
308 krait3_dig-supply = <&pm8841_s2_corner_ao>;
Matt Wagantall337cdb72012-06-29 12:07:27 -0700309 krait0_hfpll_a-supply = <&pm8941_s2_ao>;
310 krait1_hfpll_a-supply = <&pm8941_s2_ao>;
311 krait2_hfpll_a-supply = <&pm8941_s2_ao>;
312 krait3_hfpll_a-supply = <&pm8941_s2_ao>;
313 l2_hfpll_a-supply = <&pm8941_s2_ao>;
314 krait0_hfpll_b-supply = <&pm8941_l12_ao>;
315 krait1_hfpll_b-supply = <&pm8941_l12_ao>;
316 krait2_hfpll_b-supply = <&pm8941_l12_ao>;
317 krait3_hfpll_b-supply = <&pm8941_l12_ao>;
318 l2_hfpll_b-supply = <&pm8941_l12_ao>;
Matt Wagantalle9b715a2012-01-04 18:16:14 -0800319 };
Ido Shayevitzef72ddd2012-03-28 18:55:55 +0200320
321 qcom,ssusb@F9200000 {
322 compatible = "qcom,dwc-usb3-msm";
Manu Gautam8c642812012-06-07 10:35:10 +0530323 reg = <0xF9200000 0xFA000>;
Manu Gautam17206c22012-06-21 10:17:53 +0530324 interrupts = <0 131 0 0 179 0>;
325 interrupt-names = "irq", "otg_irq";
Manu Gautam60e01352012-05-29 09:00:34 +0530326 SSUSB_VDDCX-supply = <&pm8841_s2>;
327 SSUSB_1p8-supply = <&pm8941_l6>;
328 HSUSB_VDDCX-supply = <&pm8841_s2>;
329 HSUSB_1p8-supply = <&pm8941_l6>;
330 HSUSB_3p3-supply = <&pm8941_l24>;
Ido Shayevitzef72ddd2012-03-28 18:55:55 +0200331 qcom,dwc-usb3-msm-dbm-eps = <4>;
332 };
Matt Wagantallc2bbdc32012-03-21 19:44:50 -0700333
Matt Wagantallfc727212012-01-06 18:18:25 -0800334 gdsc_oxili_gx: qcom,gdsc@fd8c4024 {
335 parent-supply = <&pm8841_s4>;
336 };
337
Matt Wagantallc2bbdc32012-03-21 19:44:50 -0700338 qcom,lpass@fe200000 {
339 compatible = "qcom,pil-q6v5-lpass";
340 reg = <0xfe200000 0x00100>,
Matt Wagantallc2bbdc32012-03-21 19:44:50 -0700341 <0xfd485100 0x00010>;
342
Matt Wagantall6e6b8cd2012-05-24 12:42:24 -0700343 qcom,firmware-name = "adsp";
Matt Wagantallc2bbdc32012-03-21 19:44:50 -0700344 };
Tianyi Gouc1e049f82011-11-23 14:20:16 -0800345
Phani Kumar Uppalapati87841c82012-06-14 21:28:43 -0700346 qcom,msm-pcm {
347 compatible = "qcom,msm-pcm-dsp";
348 };
Phani Kumar Uppalapatic6651692012-06-14 20:33:09 -0700349
Phani Kumar Uppalapati87841c82012-06-14 21:28:43 -0700350 qcom,msm-pcm-routing {
351 compatible = "qcom,msm-pcm-routing";
352 };
Phani Kumar Uppalapatic6651692012-06-14 20:33:09 -0700353
Phani Kumar Uppalapati87841c82012-06-14 21:28:43 -0700354 qcom,msm-pcm-lpa {
355 compatible = "qcom,msm-pcm-lpa";
356 };
Phani Kumar Uppalapatic6651692012-06-14 20:33:09 -0700357
Phani Kumar Uppalapati87841c82012-06-14 21:28:43 -0700358 qcom,msm-voip-dsp {
359 compatible = "qcom,msm-voip-dsp";
360 };
Phani Kumar Uppalapatic6651692012-06-14 20:33:09 -0700361
Phani Kumar Uppalapati87841c82012-06-14 21:28:43 -0700362 qcom,msm-stub-codec {
363 compatible = "qcom,msm-stub-codec";
364 };
Phani Kumar Uppalapatic6651692012-06-14 20:33:09 -0700365
Phani Kumar Uppalapati87841c82012-06-14 21:28:43 -0700366 qcom,msm-dai-fe {
367 compatible = "qcom,msm-dai-fe";
368 };
Phani Kumar Uppalapatic6651692012-06-14 20:33:09 -0700369
Phani Kumar Uppalapati87841c82012-06-14 21:28:43 -0700370 qcom,msm-auxpcm {
371 compatible = "qcom,msm-auxpcm-resource";
372 qcom,msm-cpudai-auxpcm-clk = "pcm_clk";
373 qcom,msm-cpudai-auxpcm-mode = <0>;
374 qcom,msm-cpudai-auxpcm-sync = <1>;
375 qcom,msm-cpudai-auxpcm-frame = <5>;
376 qcom,msm-cpudai-auxpcm-quant = <2>;
377 qcom,msm-cpudai-auxpcm-slot = <1>;
378 qcom,msm-cpudai-auxpcm-data = <0>;
379 qcom,msm-cpudai-auxpcm-pcm-clk-rate = <2048000>;
Phani Kumar Uppalapatic6651692012-06-14 20:33:09 -0700380
Phani Kumar Uppalapati87841c82012-06-14 21:28:43 -0700381 qcom,msm-auxpcm-rx {
382 qcom,msm-auxpcm-dev-id = <4106>;
383 compatible = "qcom,msm-auxpcm-dev";
384 };
Phani Kumar Uppalapatic6651692012-06-14 20:33:09 -0700385
Phani Kumar Uppalapati87841c82012-06-14 21:28:43 -0700386 qcom,msm-auxpcm-tx {
387 qcom,msm-auxpcm-dev-id = <4107>;
388 compatible = "qcom,msm-auxpcm-dev";
389 };
390 };
391
392 qcom,msm-pcm-hostless {
393 compatible = "qcom,msm-pcm-hostless";
394 };
Phani Kumar Uppalapatic6651692012-06-14 20:33:09 -0700395
Matt Wagantall4e2599e2012-03-21 22:31:35 -0700396 qcom,mss@fc880000 {
397 compatible = "qcom,pil-q6v5-mss";
398 reg = <0xfc880000 0x100>,
399 <0xfd485000 0x400>,
400 <0xfc820000 0x020>,
401 <0xfc401680 0x004>;
402 vdd_mss-supply = <&pm8841_s3>;
403
404 qcom,firmware-name = "mba";
405 qcom,pil-self-auth = <1>;
406 };
407
Matt Wagantalle6e00d52012-03-08 17:39:07 -0800408 qcom,mba@fc820000 {
409 compatible = "qcom,pil-mba";
410 reg = <0xfc820000 0x0020>,
411 <0x0d1fc000 0x4000>;
412
413 qcom,firmware-name = "modem";
414 qcom,depends-on = "mba";
415 };
416
Tianyi Gouc1e049f82011-11-23 14:20:16 -0800417 qcom,pronto@fb21b000 {
418 compatible = "qcom,pil-pronto";
419 reg = <0xfb21b000 0x3000>,
420 <0xfc401700 0x4>,
421 <0xfd485300 0xc>;
422 vdd_pronto_pll-supply = <&pm8941_l12>;
423
424 qcom,firmware-name = "wcnss";
425 };
Naveen Ramaraj51f5e8b2012-04-09 15:58:40 -0700426
427 qcom,ocmem@fdd00000 {
428 compatible = "qcom,msm_ocmem";
429 };
Mahesh Sivasubramanian3f0d0c72012-05-04 17:35:55 -0600430
431 qcom,rpm-smd {
432 compatible = "qcom,rpm-smd";
433 rpm-channel-name = "rpm_requests";
434 rpm-channel-type = <15>; /* SMD_APPS_RPM */
435 };
Hariprasad Dhalinarasimhade991f02012-05-31 13:15:51 -0700436
437 qcom,msm-rng@f9bff000 {
438 compatible = "qcom,msm-rng";
439 reg = <0xf9bff000 0x200>;
440 };
Ramesh Masavarapufb1f01e2012-06-14 09:40:40 -0700441
442 qcom,qseecom@fe806000 {
443 compatible = "qcom,qseecom";
444 };
Adrian Salido-Moreno5ef3ac02012-05-14 18:40:47 -0700445
446 qcom,mdss_mdp@fd900000 {
447 cell-index = <0>;
448 compatible = "qcom,mdss_mdp";
449 reg = <0xfd900000 0x22100>;
450 interrupts = <0 72 0>;
Matt Wagantall37320fb2012-06-26 14:50:28 -0700451 vdd-supply = <&gdsc_mdss>;
Adrian Salido-Moreno5ef3ac02012-05-14 18:40:47 -0700452 };
453
454 qcom,mdss_wb_panel {
455 cell-index = <1>;
456 compatible = "qcom,mdss_wb";
457 qcom,mdss_pan_res = <640 480>;
458 qcom,mdss_pan_bpp = <24>;
459 };
Hanumant72aec702012-06-25 11:51:07 -0700460
461 qcom,wdt@f9017000 {
462 compatible = "qcom,msm-watchdog";
463 reg = <0xf9017000 0x1000>;
464 interrupts = <0 3 0 0 4 0>;
465 qcom,bark-time = <11000>;
466 qcom,pet-time = <10000>;
467 qcom,ipi-ping = <1>;
468 };
Hariprasad Dhalinarasimha0fc258f2012-07-05 13:01:29 -0700469
470 qcom,tz-log@fe805720 {
471 compatible = "qcom,tz-log";
472 reg = <0xfe805720 0x1000>;
473 };
Tianyi Gou828798d2012-05-02 21:12:38 -0700474
475 qcom,venus@fdce0000 {
476 compatible = "qcom,pil-venus";
477 reg = <0xfdce0000 0x4000>,
478 <0xfdc80208 0x8>;
479 vdd-supply = <&gdsc_venus>;
480
481 qcom,firmware-name = "venus";
482 qcom,firmware-min-paddr = <0xF500000>;
483 qcom,firmware-max-paddr = <0xFA00000>;
484 };
Sathish Ambley4df614c2011-10-07 16:30:46 -0700485};