| Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | #ifndef __ASM_IPI_H |
| 2 | #define __ASM_IPI_H |
| 3 | |
| 4 | /* |
| 5 | * Copyright 2004 James Cleverdon, IBM. |
| 6 | * Subject to the GNU Public License, v.2 |
| 7 | * |
| 8 | * Generic APIC InterProcessor Interrupt code. |
| 9 | * |
| 10 | * Moved to include file by James Cleverdon from |
| 11 | * arch/x86-64/kernel/smp.c |
| 12 | * |
| 13 | * Copyrights from kernel/smp.c: |
| 14 | * |
| 15 | * (c) 1995 Alan Cox, Building #3 <alan@redhat.com> |
| 16 | * (c) 1998-99, 2000 Ingo Molnar <mingo@redhat.com> |
| 17 | * (c) 2002,2003 Andi Kleen, SuSE Labs. |
| 18 | * Subject to the GNU Public License, v.2 |
| 19 | */ |
| 20 | |
| 21 | #include <asm/fixmap.h> |
| 22 | #include <asm/hw_irq.h> |
| 23 | #include <asm/apicdef.h> |
| 24 | #include <asm/genapic.h> |
| 25 | |
| 26 | /* |
| 27 | * the following functions deal with sending IPIs between CPUs. |
| 28 | * |
| 29 | * We use 'broadcast', CPU->CPU IPIs and self-IPIs too. |
| 30 | */ |
| 31 | |
| 32 | static inline unsigned int __prepare_ICR (unsigned int shortcut, int vector, unsigned int dest) |
| 33 | { |
| 34 | unsigned int icr = APIC_DM_FIXED | shortcut | vector | dest; |
| 35 | if (vector == KDB_VECTOR) |
| 36 | icr = (icr & (~APIC_VECTOR_MASK)) | APIC_DM_NMI; |
| 37 | return icr; |
| 38 | } |
| 39 | |
| 40 | static inline int __prepare_ICR2 (unsigned int mask) |
| 41 | { |
| 42 | return SET_APIC_DEST_FIELD(mask); |
| 43 | } |
| 44 | |
| 45 | static inline void __send_IPI_shortcut(unsigned int shortcut, int vector, unsigned int dest) |
| 46 | { |
| 47 | /* |
| 48 | * Subtle. In the case of the 'never do double writes' workaround |
| 49 | * we have to lock out interrupts to be safe. As we don't care |
| 50 | * of the value read we use an atomic rmw access to avoid costly |
| 51 | * cli/sti. Otherwise we use an even cheaper single atomic write |
| 52 | * to the APIC. |
| 53 | */ |
| 54 | unsigned int cfg; |
| 55 | |
| 56 | /* |
| 57 | * Wait for idle. |
| 58 | */ |
| 59 | apic_wait_icr_idle(); |
| 60 | |
| 61 | /* |
| 62 | * No need to touch the target chip field |
| 63 | */ |
| 64 | cfg = __prepare_ICR(shortcut, vector, dest); |
| 65 | |
| 66 | /* |
| 67 | * Send the IPI. The write to APIC_ICR fires this off. |
| 68 | */ |
| 69 | apic_write_around(APIC_ICR, cfg); |
| 70 | } |
| 71 | |
| 72 | |
| 73 | static inline void send_IPI_mask_sequence(cpumask_t mask, int vector) |
| 74 | { |
| 75 | unsigned long cfg, flags; |
| 76 | unsigned long query_cpu; |
| 77 | |
| 78 | /* |
| 79 | * Hack. The clustered APIC addressing mode doesn't allow us to send |
| 80 | * to an arbitrary mask, so I do a unicast to each CPU instead. |
| 81 | * - mbligh |
| 82 | */ |
| 83 | local_irq_save(flags); |
| 84 | |
| 85 | for (query_cpu = 0; query_cpu < NR_CPUS; ++query_cpu) { |
| 86 | if (cpu_isset(query_cpu, mask)) { |
| 87 | |
| 88 | /* |
| 89 | * Wait for idle. |
| 90 | */ |
| 91 | apic_wait_icr_idle(); |
| 92 | |
| 93 | /* |
| 94 | * prepare target chip field |
| 95 | */ |
| 96 | cfg = __prepare_ICR2(x86_cpu_to_apicid[query_cpu]); |
| 97 | apic_write_around(APIC_ICR2, cfg); |
| 98 | |
| 99 | /* |
| 100 | * program the ICR |
| 101 | */ |
| 102 | cfg = __prepare_ICR(0, vector, APIC_DEST_PHYSICAL); |
| 103 | |
| 104 | /* |
| 105 | * Send the IPI. The write to APIC_ICR fires this off. |
| 106 | */ |
| 107 | apic_write_around(APIC_ICR, cfg); |
| 108 | } |
| 109 | } |
| 110 | local_irq_restore(flags); |
| 111 | } |
| 112 | |
| 113 | #endif /* __ASM_IPI_H */ |