Tony Lindgren | 3179a01 | 2005-11-10 14:26:48 +0000 | [diff] [blame] | 1 | /* |
| 2 | * linux/arch/arm/mach-omap1/clock.h |
| 3 | * |
| 4 | * Copyright (C) 2004 - 2005 Nokia corporation |
| 5 | * Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com> |
| 6 | * Based on clocks.h by Tony Lindgren, Gordon McNutt and RidgeRun, Inc |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or modify |
| 9 | * it under the terms of the GNU General Public License version 2 as |
| 10 | * published by the Free Software Foundation. |
| 11 | */ |
| 12 | |
| 13 | #ifndef __ARCH_ARM_MACH_OMAP1_CLOCK_H |
| 14 | #define __ARCH_ARM_MACH_OMAP1_CLOCK_H |
| 15 | |
Tony Lindgren | 3179a01 | 2005-11-10 14:26:48 +0000 | [diff] [blame] | 16 | static void omap1_ckctl_recalc(struct clk * clk); |
| 17 | static void omap1_watchdog_recalc(struct clk * clk); |
Imre Deak | df2c2e7 | 2007-03-05 17:22:58 +0200 | [diff] [blame] | 18 | static int omap1_set_sossi_rate(struct clk *clk, unsigned long rate); |
| 19 | static void omap1_sossi_recalc(struct clk *clk); |
Tony Lindgren | 3179a01 | 2005-11-10 14:26:48 +0000 | [diff] [blame] | 20 | static void omap1_ckctl_recalc_dsp_domain(struct clk * clk); |
Tony Lindgren | 3179a01 | 2005-11-10 14:26:48 +0000 | [diff] [blame] | 21 | static int omap1_clk_set_rate_dsp_domain(struct clk * clk, unsigned long rate); |
Tony Lindgren | 3179a01 | 2005-11-10 14:26:48 +0000 | [diff] [blame] | 22 | static int omap1_set_uart_rate(struct clk * clk, unsigned long rate); |
| 23 | static void omap1_uart_recalc(struct clk * clk); |
Tony Lindgren | 3179a01 | 2005-11-10 14:26:48 +0000 | [diff] [blame] | 24 | static int omap1_set_ext_clk_rate(struct clk * clk, unsigned long rate); |
| 25 | static long omap1_round_ext_clk_rate(struct clk * clk, unsigned long rate); |
| 26 | static void omap1_init_ext_clk(struct clk * clk); |
| 27 | static int omap1_select_table_rate(struct clk * clk, unsigned long rate); |
| 28 | static long omap1_round_to_table_rate(struct clk * clk, unsigned long rate); |
Tony Lindgren | 3179a01 | 2005-11-10 14:26:48 +0000 | [diff] [blame] | 29 | |
| 30 | struct mpu_rate { |
| 31 | unsigned long rate; |
| 32 | unsigned long xtal; |
| 33 | unsigned long pll_rate; |
| 34 | __u16 ckctl_val; |
| 35 | __u16 dpllctl_val; |
| 36 | }; |
| 37 | |
| 38 | struct uart_clk { |
| 39 | struct clk clk; |
| 40 | unsigned long sysc_addr; |
| 41 | }; |
| 42 | |
| 43 | /* Provide a method for preventing idling some ARM IDLECT clocks */ |
| 44 | struct arm_idlect1_clk { |
| 45 | struct clk clk; |
| 46 | unsigned long no_idle_count; |
| 47 | __u8 idlect_shift; |
| 48 | }; |
| 49 | |
| 50 | /* ARM_CKCTL bit shifts */ |
| 51 | #define CKCTL_PERDIV_OFFSET 0 |
| 52 | #define CKCTL_LCDDIV_OFFSET 2 |
| 53 | #define CKCTL_ARMDIV_OFFSET 4 |
| 54 | #define CKCTL_DSPDIV_OFFSET 6 |
| 55 | #define CKCTL_TCDIV_OFFSET 8 |
| 56 | #define CKCTL_DSPMMUDIV_OFFSET 10 |
| 57 | /*#define ARM_TIMXO 12*/ |
| 58 | #define EN_DSPCK 13 |
| 59 | /*#define ARM_INTHCK_SEL 14*/ /* Divide-by-2 for mpu inth_ck */ |
| 60 | /* DSP_CKCTL bit shifts */ |
| 61 | #define CKCTL_DSPPERDIV_OFFSET 0 |
| 62 | |
| 63 | /* ARM_IDLECT2 bit shifts */ |
| 64 | #define EN_WDTCK 0 |
| 65 | #define EN_XORPCK 1 |
| 66 | #define EN_PERCK 2 |
| 67 | #define EN_LCDCK 3 |
| 68 | #define EN_LBCK 4 /* Not on 1610/1710 */ |
| 69 | /*#define EN_HSABCK 5*/ |
| 70 | #define EN_APICK 6 |
| 71 | #define EN_TIMCK 7 |
| 72 | #define DMACK_REQ 8 |
| 73 | #define EN_GPIOCK 9 /* Not on 1610/1710 */ |
| 74 | /*#define EN_LBFREECK 10*/ |
| 75 | #define EN_CKOUT_ARM 11 |
| 76 | |
| 77 | /* ARM_IDLECT3 bit shifts */ |
| 78 | #define EN_OCPI_CK 0 |
| 79 | #define EN_TC1_CK 2 |
| 80 | #define EN_TC2_CK 4 |
| 81 | |
| 82 | /* DSP_IDLECT2 bit shifts (0,1,2 are same as for ARM_IDLECT2) */ |
| 83 | #define EN_DSPTIMCK 5 |
| 84 | |
| 85 | /* Various register defines for clock controls scattered around OMAP chip */ |
Tony Lindgren | 90afd5c | 2006-09-25 13:27:20 +0300 | [diff] [blame] | 86 | #define SDW_MCLK_INV_BIT 2 /* In ULPD_CLKC_CTRL */ |
Tony Lindgren | 3179a01 | 2005-11-10 14:26:48 +0000 | [diff] [blame] | 87 | #define USB_MCLK_EN_BIT 4 /* In ULPD_CLKC_CTRL */ |
| 88 | #define USB_HOST_HHC_UHOST_EN 9 /* In MOD_CONF_CTRL_0 */ |
| 89 | #define SWD_ULPD_PLL_CLK_REQ 1 /* In SWD_CLK_DIV_CTRL_SEL */ |
| 90 | #define COM_ULPD_PLL_CLK_REQ 1 /* In COM_CLK_DIV_CTRL_SEL */ |
| 91 | #define SWD_CLK_DIV_CTRL_SEL 0xfffe0874 |
| 92 | #define COM_CLK_DIV_CTRL_SEL 0xfffe0878 |
| 93 | #define SOFT_REQ_REG 0xfffe0834 |
| 94 | #define SOFT_REQ_REG2 0xfffe0880 |
| 95 | |
| 96 | /*------------------------------------------------------------------------- |
| 97 | * Omap1 MPU rate table |
| 98 | *-------------------------------------------------------------------------*/ |
| 99 | static struct mpu_rate rate_table[] = { |
| 100 | /* MPU MHz, xtal MHz, dpll1 MHz, CKCTL, DPLL_CTL |
| 101 | * NOTE: Comment order here is different from bits in CKCTL value: |
| 102 | * armdiv, dspdiv, dspmmu, tcdiv, perdiv, lcddiv |
| 103 | */ |
| 104 | #if defined(CONFIG_OMAP_ARM_216MHZ) |
| 105 | { 216000000, 12000000, 216000000, 0x050d, 0x2910 }, /* 1/1/2/2/2/8 */ |
| 106 | #endif |
| 107 | #if defined(CONFIG_OMAP_ARM_195MHZ) |
| 108 | { 195000000, 13000000, 195000000, 0x050e, 0x2790 }, /* 1/1/2/2/4/8 */ |
| 109 | #endif |
| 110 | #if defined(CONFIG_OMAP_ARM_192MHZ) |
| 111 | { 192000000, 19200000, 192000000, 0x050f, 0x2510 }, /* 1/1/2/2/8/8 */ |
| 112 | { 192000000, 12000000, 192000000, 0x050f, 0x2810 }, /* 1/1/2/2/8/8 */ |
| 113 | { 96000000, 12000000, 192000000, 0x055f, 0x2810 }, /* 2/2/2/2/8/8 */ |
| 114 | { 48000000, 12000000, 192000000, 0x0baf, 0x2810 }, /* 4/4/4/8/8/8 */ |
| 115 | { 24000000, 12000000, 192000000, 0x0fff, 0x2810 }, /* 8/8/8/8/8/8 */ |
| 116 | #endif |
| 117 | #if defined(CONFIG_OMAP_ARM_182MHZ) |
| 118 | { 182000000, 13000000, 182000000, 0x050e, 0x2710 }, /* 1/1/2/2/4/8 */ |
| 119 | #endif |
| 120 | #if defined(CONFIG_OMAP_ARM_168MHZ) |
| 121 | { 168000000, 12000000, 168000000, 0x010f, 0x2710 }, /* 1/1/1/2/8/8 */ |
| 122 | #endif |
| 123 | #if defined(CONFIG_OMAP_ARM_150MHZ) |
| 124 | { 150000000, 12000000, 150000000, 0x010a, 0x2cb0 }, /* 1/1/1/2/4/4 */ |
| 125 | #endif |
| 126 | #if defined(CONFIG_OMAP_ARM_120MHZ) |
| 127 | { 120000000, 12000000, 120000000, 0x010a, 0x2510 }, /* 1/1/1/2/4/4 */ |
| 128 | #endif |
| 129 | #if defined(CONFIG_OMAP_ARM_96MHZ) |
| 130 | { 96000000, 12000000, 96000000, 0x0005, 0x2410 }, /* 1/1/1/1/2/2 */ |
| 131 | #endif |
| 132 | #if defined(CONFIG_OMAP_ARM_60MHZ) |
| 133 | { 60000000, 12000000, 60000000, 0x0005, 0x2290 }, /* 1/1/1/1/2/2 */ |
| 134 | #endif |
| 135 | #if defined(CONFIG_OMAP_ARM_30MHZ) |
| 136 | { 30000000, 12000000, 60000000, 0x0555, 0x2290 }, /* 2/2/2/2/2/2 */ |
| 137 | #endif |
| 138 | { 0, 0, 0, 0, 0 }, |
| 139 | }; |
| 140 | |
| 141 | /*------------------------------------------------------------------------- |
| 142 | * Omap1 clocks |
| 143 | *-------------------------------------------------------------------------*/ |
| 144 | |
| 145 | static struct clk ck_ref = { |
| 146 | .name = "ck_ref", |
Russell King | 897dcde | 2008-11-04 16:35:03 +0000 | [diff] [blame^] | 147 | .ops = &clkops_null, |
Tony Lindgren | 3179a01 | 2005-11-10 14:26:48 +0000 | [diff] [blame] | 148 | .rate = 12000000, |
| 149 | .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | |
Russell King | 897dcde | 2008-11-04 16:35:03 +0000 | [diff] [blame^] | 150 | CLOCK_IN_OMAP310, |
Tony Lindgren | 3179a01 | 2005-11-10 14:26:48 +0000 | [diff] [blame] | 151 | }; |
| 152 | |
| 153 | static struct clk ck_dpll1 = { |
| 154 | .name = "ck_dpll1", |
Russell King | 897dcde | 2008-11-04 16:35:03 +0000 | [diff] [blame^] | 155 | .ops = &clkops_null, |
Tony Lindgren | 3179a01 | 2005-11-10 14:26:48 +0000 | [diff] [blame] | 156 | .parent = &ck_ref, |
| 157 | .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | |
Russell King | 897dcde | 2008-11-04 16:35:03 +0000 | [diff] [blame^] | 158 | CLOCK_IN_OMAP310 | RATE_PROPAGATES, |
Tony Lindgren | 3179a01 | 2005-11-10 14:26:48 +0000 | [diff] [blame] | 159 | }; |
| 160 | |
| 161 | static struct arm_idlect1_clk ck_dpll1out = { |
| 162 | .clk = { |
Imre Deak | df2c2e7 | 2007-03-05 17:22:58 +0200 | [diff] [blame] | 163 | .name = "ck_dpll1out", |
Russell King | 548d849 | 2008-11-04 14:02:46 +0000 | [diff] [blame] | 164 | .ops = &clkops_generic, |
Tony Lindgren | 3179a01 | 2005-11-10 14:26:48 +0000 | [diff] [blame] | 165 | .parent = &ck_dpll1, |
Imre Deak | df2c2e7 | 2007-03-05 17:22:58 +0200 | [diff] [blame] | 166 | .flags = CLOCK_IN_OMAP16XX | CLOCK_IDLE_CONTROL | |
| 167 | ENABLE_REG_32BIT | RATE_PROPAGATES, |
Tony Lindgren | 3179a01 | 2005-11-10 14:26:48 +0000 | [diff] [blame] | 168 | .enable_reg = (void __iomem *)ARM_IDLECT2, |
| 169 | .enable_bit = EN_CKOUT_ARM, |
| 170 | .recalc = &followparent_recalc, |
Tony Lindgren | 3179a01 | 2005-11-10 14:26:48 +0000 | [diff] [blame] | 171 | }, |
| 172 | .idlect_shift = 12, |
| 173 | }; |
| 174 | |
Imre Deak | df2c2e7 | 2007-03-05 17:22:58 +0200 | [diff] [blame] | 175 | static struct clk sossi_ck = { |
| 176 | .name = "ck_sossi", |
Russell King | 548d849 | 2008-11-04 14:02:46 +0000 | [diff] [blame] | 177 | .ops = &clkops_generic, |
Imre Deak | df2c2e7 | 2007-03-05 17:22:58 +0200 | [diff] [blame] | 178 | .parent = &ck_dpll1out.clk, |
| 179 | .flags = CLOCK_IN_OMAP16XX | CLOCK_NO_IDLE_PARENT | |
| 180 | ENABLE_REG_32BIT, |
| 181 | .enable_reg = (void __iomem *)MOD_CONF_CTRL_1, |
| 182 | .enable_bit = 16, |
| 183 | .recalc = &omap1_sossi_recalc, |
| 184 | .set_rate = &omap1_set_sossi_rate, |
Imre Deak | df2c2e7 | 2007-03-05 17:22:58 +0200 | [diff] [blame] | 185 | }; |
| 186 | |
Tony Lindgren | 3179a01 | 2005-11-10 14:26:48 +0000 | [diff] [blame] | 187 | static struct clk arm_ck = { |
| 188 | .name = "arm_ck", |
Russell King | 897dcde | 2008-11-04 16:35:03 +0000 | [diff] [blame^] | 189 | .ops = &clkops_null, |
Tony Lindgren | 3179a01 | 2005-11-10 14:26:48 +0000 | [diff] [blame] | 190 | .parent = &ck_dpll1, |
| 191 | .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | |
Russell King | 897dcde | 2008-11-04 16:35:03 +0000 | [diff] [blame^] | 192 | CLOCK_IN_OMAP310 | RATE_CKCTL | RATE_PROPAGATES, |
Tony Lindgren | 3179a01 | 2005-11-10 14:26:48 +0000 | [diff] [blame] | 193 | .rate_offset = CKCTL_ARMDIV_OFFSET, |
| 194 | .recalc = &omap1_ckctl_recalc, |
Tony Lindgren | 3179a01 | 2005-11-10 14:26:48 +0000 | [diff] [blame] | 195 | }; |
| 196 | |
| 197 | static struct arm_idlect1_clk armper_ck = { |
| 198 | .clk = { |
| 199 | .name = "armper_ck", |
Russell King | 548d849 | 2008-11-04 14:02:46 +0000 | [diff] [blame] | 200 | .ops = &clkops_generic, |
Tony Lindgren | 3179a01 | 2005-11-10 14:26:48 +0000 | [diff] [blame] | 201 | .parent = &ck_dpll1, |
| 202 | .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | |
Tony Lindgren | b824efa | 2006-04-02 17:46:20 +0100 | [diff] [blame] | 203 | CLOCK_IN_OMAP310 | RATE_CKCTL | |
| 204 | CLOCK_IDLE_CONTROL, |
Tony Lindgren | 3179a01 | 2005-11-10 14:26:48 +0000 | [diff] [blame] | 205 | .enable_reg = (void __iomem *)ARM_IDLECT2, |
| 206 | .enable_bit = EN_PERCK, |
| 207 | .rate_offset = CKCTL_PERDIV_OFFSET, |
| 208 | .recalc = &omap1_ckctl_recalc, |
Tony Lindgren | 3179a01 | 2005-11-10 14:26:48 +0000 | [diff] [blame] | 209 | }, |
| 210 | .idlect_shift = 2, |
| 211 | }; |
| 212 | |
| 213 | static struct clk arm_gpio_ck = { |
| 214 | .name = "arm_gpio_ck", |
Russell King | 548d849 | 2008-11-04 14:02:46 +0000 | [diff] [blame] | 215 | .ops = &clkops_generic, |
Tony Lindgren | 3179a01 | 2005-11-10 14:26:48 +0000 | [diff] [blame] | 216 | .parent = &ck_dpll1, |
Tony Lindgren | b824efa | 2006-04-02 17:46:20 +0100 | [diff] [blame] | 217 | .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310, |
Tony Lindgren | 3179a01 | 2005-11-10 14:26:48 +0000 | [diff] [blame] | 218 | .enable_reg = (void __iomem *)ARM_IDLECT2, |
| 219 | .enable_bit = EN_GPIOCK, |
| 220 | .recalc = &followparent_recalc, |
Tony Lindgren | 3179a01 | 2005-11-10 14:26:48 +0000 | [diff] [blame] | 221 | }; |
| 222 | |
| 223 | static struct arm_idlect1_clk armxor_ck = { |
| 224 | .clk = { |
| 225 | .name = "armxor_ck", |
Russell King | 548d849 | 2008-11-04 14:02:46 +0000 | [diff] [blame] | 226 | .ops = &clkops_generic, |
Tony Lindgren | 3179a01 | 2005-11-10 14:26:48 +0000 | [diff] [blame] | 227 | .parent = &ck_ref, |
| 228 | .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | |
Tony Lindgren | b824efa | 2006-04-02 17:46:20 +0100 | [diff] [blame] | 229 | CLOCK_IN_OMAP310 | CLOCK_IDLE_CONTROL, |
Tony Lindgren | 3179a01 | 2005-11-10 14:26:48 +0000 | [diff] [blame] | 230 | .enable_reg = (void __iomem *)ARM_IDLECT2, |
| 231 | .enable_bit = EN_XORPCK, |
| 232 | .recalc = &followparent_recalc, |
Tony Lindgren | 3179a01 | 2005-11-10 14:26:48 +0000 | [diff] [blame] | 233 | }, |
| 234 | .idlect_shift = 1, |
| 235 | }; |
| 236 | |
| 237 | static struct arm_idlect1_clk armtim_ck = { |
| 238 | .clk = { |
| 239 | .name = "armtim_ck", |
Russell King | 548d849 | 2008-11-04 14:02:46 +0000 | [diff] [blame] | 240 | .ops = &clkops_generic, |
Tony Lindgren | 3179a01 | 2005-11-10 14:26:48 +0000 | [diff] [blame] | 241 | .parent = &ck_ref, |
| 242 | .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | |
Tony Lindgren | b824efa | 2006-04-02 17:46:20 +0100 | [diff] [blame] | 243 | CLOCK_IN_OMAP310 | CLOCK_IDLE_CONTROL, |
Tony Lindgren | 3179a01 | 2005-11-10 14:26:48 +0000 | [diff] [blame] | 244 | .enable_reg = (void __iomem *)ARM_IDLECT2, |
| 245 | .enable_bit = EN_TIMCK, |
| 246 | .recalc = &followparent_recalc, |
Tony Lindgren | 3179a01 | 2005-11-10 14:26:48 +0000 | [diff] [blame] | 247 | }, |
| 248 | .idlect_shift = 9, |
| 249 | }; |
| 250 | |
| 251 | static struct arm_idlect1_clk armwdt_ck = { |
| 252 | .clk = { |
| 253 | .name = "armwdt_ck", |
Russell King | 548d849 | 2008-11-04 14:02:46 +0000 | [diff] [blame] | 254 | .ops = &clkops_generic, |
Tony Lindgren | 3179a01 | 2005-11-10 14:26:48 +0000 | [diff] [blame] | 255 | .parent = &ck_ref, |
| 256 | .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | |
Tony Lindgren | b824efa | 2006-04-02 17:46:20 +0100 | [diff] [blame] | 257 | CLOCK_IN_OMAP310 | CLOCK_IDLE_CONTROL, |
Tony Lindgren | 3179a01 | 2005-11-10 14:26:48 +0000 | [diff] [blame] | 258 | .enable_reg = (void __iomem *)ARM_IDLECT2, |
| 259 | .enable_bit = EN_WDTCK, |
| 260 | .recalc = &omap1_watchdog_recalc, |
Tony Lindgren | 3179a01 | 2005-11-10 14:26:48 +0000 | [diff] [blame] | 261 | }, |
| 262 | .idlect_shift = 0, |
| 263 | }; |
| 264 | |
| 265 | static struct clk arminth_ck16xx = { |
| 266 | .name = "arminth_ck", |
Russell King | 897dcde | 2008-11-04 16:35:03 +0000 | [diff] [blame^] | 267 | .ops = &clkops_null, |
Tony Lindgren | 3179a01 | 2005-11-10 14:26:48 +0000 | [diff] [blame] | 268 | .parent = &arm_ck, |
Russell King | 897dcde | 2008-11-04 16:35:03 +0000 | [diff] [blame^] | 269 | .flags = CLOCK_IN_OMAP16XX, |
Tony Lindgren | 3179a01 | 2005-11-10 14:26:48 +0000 | [diff] [blame] | 270 | .recalc = &followparent_recalc, |
| 271 | /* Note: On 16xx the frequency can be divided by 2 by programming |
| 272 | * ARM_CKCTL:ARM_INTHCK_SEL(14) to 1 |
| 273 | * |
| 274 | * 1510 version is in TC clocks. |
| 275 | */ |
Tony Lindgren | 3179a01 | 2005-11-10 14:26:48 +0000 | [diff] [blame] | 276 | }; |
| 277 | |
| 278 | static struct clk dsp_ck = { |
| 279 | .name = "dsp_ck", |
Russell King | 548d849 | 2008-11-04 14:02:46 +0000 | [diff] [blame] | 280 | .ops = &clkops_generic, |
Tony Lindgren | 3179a01 | 2005-11-10 14:26:48 +0000 | [diff] [blame] | 281 | .parent = &ck_dpll1, |
Marek Vasut | 6017e29 | 2006-12-06 17:13:55 -0800 | [diff] [blame] | 282 | .flags = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | |
Tony Lindgren | 3179a01 | 2005-11-10 14:26:48 +0000 | [diff] [blame] | 283 | RATE_CKCTL, |
| 284 | .enable_reg = (void __iomem *)ARM_CKCTL, |
| 285 | .enable_bit = EN_DSPCK, |
| 286 | .rate_offset = CKCTL_DSPDIV_OFFSET, |
| 287 | .recalc = &omap1_ckctl_recalc, |
Tony Lindgren | 3179a01 | 2005-11-10 14:26:48 +0000 | [diff] [blame] | 288 | }; |
| 289 | |
| 290 | static struct clk dspmmu_ck = { |
| 291 | .name = "dspmmu_ck", |
Russell King | 897dcde | 2008-11-04 16:35:03 +0000 | [diff] [blame^] | 292 | .ops = &clkops_null, |
Tony Lindgren | 3179a01 | 2005-11-10 14:26:48 +0000 | [diff] [blame] | 293 | .parent = &ck_dpll1, |
Marek Vasut | 6017e29 | 2006-12-06 17:13:55 -0800 | [diff] [blame] | 294 | .flags = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | |
Russell King | 897dcde | 2008-11-04 16:35:03 +0000 | [diff] [blame^] | 295 | RATE_CKCTL, |
Tony Lindgren | 3179a01 | 2005-11-10 14:26:48 +0000 | [diff] [blame] | 296 | .rate_offset = CKCTL_DSPMMUDIV_OFFSET, |
| 297 | .recalc = &omap1_ckctl_recalc, |
Tony Lindgren | 3179a01 | 2005-11-10 14:26:48 +0000 | [diff] [blame] | 298 | }; |
| 299 | |
| 300 | static struct clk dspper_ck = { |
| 301 | .name = "dspper_ck", |
Russell King | 548d849 | 2008-11-04 14:02:46 +0000 | [diff] [blame] | 302 | .ops = &clkops_dspck, |
Tony Lindgren | 3179a01 | 2005-11-10 14:26:48 +0000 | [diff] [blame] | 303 | .parent = &ck_dpll1, |
Marek Vasut | 6017e29 | 2006-12-06 17:13:55 -0800 | [diff] [blame] | 304 | .flags = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | |
Tony Lindgren | 3179a01 | 2005-11-10 14:26:48 +0000 | [diff] [blame] | 305 | RATE_CKCTL | VIRTUAL_IO_ADDRESS, |
Russell King | 397fcaf | 2008-09-05 15:46:19 +0100 | [diff] [blame] | 306 | .enable_reg = DSP_IDLECT2, |
Tony Lindgren | 3179a01 | 2005-11-10 14:26:48 +0000 | [diff] [blame] | 307 | .enable_bit = EN_PERCK, |
| 308 | .rate_offset = CKCTL_PERDIV_OFFSET, |
| 309 | .recalc = &omap1_ckctl_recalc_dsp_domain, |
| 310 | .set_rate = &omap1_clk_set_rate_dsp_domain, |
Tony Lindgren | 3179a01 | 2005-11-10 14:26:48 +0000 | [diff] [blame] | 311 | }; |
| 312 | |
| 313 | static struct clk dspxor_ck = { |
| 314 | .name = "dspxor_ck", |
Russell King | 548d849 | 2008-11-04 14:02:46 +0000 | [diff] [blame] | 315 | .ops = &clkops_dspck, |
Tony Lindgren | 3179a01 | 2005-11-10 14:26:48 +0000 | [diff] [blame] | 316 | .parent = &ck_ref, |
Marek Vasut | 6017e29 | 2006-12-06 17:13:55 -0800 | [diff] [blame] | 317 | .flags = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | |
Tony Lindgren | 3179a01 | 2005-11-10 14:26:48 +0000 | [diff] [blame] | 318 | VIRTUAL_IO_ADDRESS, |
Russell King | 397fcaf | 2008-09-05 15:46:19 +0100 | [diff] [blame] | 319 | .enable_reg = DSP_IDLECT2, |
Tony Lindgren | 3179a01 | 2005-11-10 14:26:48 +0000 | [diff] [blame] | 320 | .enable_bit = EN_XORPCK, |
| 321 | .recalc = &followparent_recalc, |
Tony Lindgren | 3179a01 | 2005-11-10 14:26:48 +0000 | [diff] [blame] | 322 | }; |
| 323 | |
| 324 | static struct clk dsptim_ck = { |
| 325 | .name = "dsptim_ck", |
Russell King | 548d849 | 2008-11-04 14:02:46 +0000 | [diff] [blame] | 326 | .ops = &clkops_dspck, |
Tony Lindgren | 3179a01 | 2005-11-10 14:26:48 +0000 | [diff] [blame] | 327 | .parent = &ck_ref, |
Marek Vasut | 6017e29 | 2006-12-06 17:13:55 -0800 | [diff] [blame] | 328 | .flags = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | |
Tony Lindgren | 3179a01 | 2005-11-10 14:26:48 +0000 | [diff] [blame] | 329 | VIRTUAL_IO_ADDRESS, |
Russell King | 397fcaf | 2008-09-05 15:46:19 +0100 | [diff] [blame] | 330 | .enable_reg = DSP_IDLECT2, |
Tony Lindgren | 3179a01 | 2005-11-10 14:26:48 +0000 | [diff] [blame] | 331 | .enable_bit = EN_DSPTIMCK, |
| 332 | .recalc = &followparent_recalc, |
Tony Lindgren | 3179a01 | 2005-11-10 14:26:48 +0000 | [diff] [blame] | 333 | }; |
| 334 | |
| 335 | /* Tie ARM_IDLECT1:IDLIF_ARM to this logical clock structure */ |
| 336 | static struct arm_idlect1_clk tc_ck = { |
| 337 | .clk = { |
| 338 | .name = "tc_ck", |
Russell King | 897dcde | 2008-11-04 16:35:03 +0000 | [diff] [blame^] | 339 | .ops = &clkops_null, |
Tony Lindgren | 3179a01 | 2005-11-10 14:26:48 +0000 | [diff] [blame] | 340 | .parent = &ck_dpll1, |
| 341 | .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | |
Tony Lindgren | b824efa | 2006-04-02 17:46:20 +0100 | [diff] [blame] | 342 | CLOCK_IN_OMAP730 | CLOCK_IN_OMAP310 | |
| 343 | RATE_CKCTL | RATE_PROPAGATES | |
Russell King | 897dcde | 2008-11-04 16:35:03 +0000 | [diff] [blame^] | 344 | CLOCK_IDLE_CONTROL, |
Tony Lindgren | 3179a01 | 2005-11-10 14:26:48 +0000 | [diff] [blame] | 345 | .rate_offset = CKCTL_TCDIV_OFFSET, |
| 346 | .recalc = &omap1_ckctl_recalc, |
Tony Lindgren | 3179a01 | 2005-11-10 14:26:48 +0000 | [diff] [blame] | 347 | }, |
| 348 | .idlect_shift = 6, |
| 349 | }; |
| 350 | |
| 351 | static struct clk arminth_ck1510 = { |
| 352 | .name = "arminth_ck", |
Russell King | 897dcde | 2008-11-04 16:35:03 +0000 | [diff] [blame^] | 353 | .ops = &clkops_null, |
Tony Lindgren | 3179a01 | 2005-11-10 14:26:48 +0000 | [diff] [blame] | 354 | .parent = &tc_ck.clk, |
Russell King | 897dcde | 2008-11-04 16:35:03 +0000 | [diff] [blame^] | 355 | .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310, |
Tony Lindgren | 3179a01 | 2005-11-10 14:26:48 +0000 | [diff] [blame] | 356 | .recalc = &followparent_recalc, |
| 357 | /* Note: On 1510 the frequency follows TC_CK |
| 358 | * |
| 359 | * 16xx version is in MPU clocks. |
| 360 | */ |
Tony Lindgren | 3179a01 | 2005-11-10 14:26:48 +0000 | [diff] [blame] | 361 | }; |
| 362 | |
| 363 | static struct clk tipb_ck = { |
| 364 | /* No-idle controlled by "tc_ck" */ |
Marek Vasut | 6017e29 | 2006-12-06 17:13:55 -0800 | [diff] [blame] | 365 | .name = "tipb_ck", |
Russell King | 897dcde | 2008-11-04 16:35:03 +0000 | [diff] [blame^] | 366 | .ops = &clkops_null, |
Tony Lindgren | 3179a01 | 2005-11-10 14:26:48 +0000 | [diff] [blame] | 367 | .parent = &tc_ck.clk, |
Russell King | 897dcde | 2008-11-04 16:35:03 +0000 | [diff] [blame^] | 368 | .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310, |
Tony Lindgren | 3179a01 | 2005-11-10 14:26:48 +0000 | [diff] [blame] | 369 | .recalc = &followparent_recalc, |
Tony Lindgren | 3179a01 | 2005-11-10 14:26:48 +0000 | [diff] [blame] | 370 | }; |
| 371 | |
| 372 | static struct clk l3_ocpi_ck = { |
| 373 | /* No-idle controlled by "tc_ck" */ |
| 374 | .name = "l3_ocpi_ck", |
Russell King | 548d849 | 2008-11-04 14:02:46 +0000 | [diff] [blame] | 375 | .ops = &clkops_generic, |
Tony Lindgren | 3179a01 | 2005-11-10 14:26:48 +0000 | [diff] [blame] | 376 | .parent = &tc_ck.clk, |
| 377 | .flags = CLOCK_IN_OMAP16XX, |
| 378 | .enable_reg = (void __iomem *)ARM_IDLECT3, |
| 379 | .enable_bit = EN_OCPI_CK, |
| 380 | .recalc = &followparent_recalc, |
Tony Lindgren | 3179a01 | 2005-11-10 14:26:48 +0000 | [diff] [blame] | 381 | }; |
| 382 | |
| 383 | static struct clk tc1_ck = { |
| 384 | .name = "tc1_ck", |
Russell King | 548d849 | 2008-11-04 14:02:46 +0000 | [diff] [blame] | 385 | .ops = &clkops_generic, |
Tony Lindgren | 3179a01 | 2005-11-10 14:26:48 +0000 | [diff] [blame] | 386 | .parent = &tc_ck.clk, |
| 387 | .flags = CLOCK_IN_OMAP16XX, |
| 388 | .enable_reg = (void __iomem *)ARM_IDLECT3, |
| 389 | .enable_bit = EN_TC1_CK, |
| 390 | .recalc = &followparent_recalc, |
Tony Lindgren | 3179a01 | 2005-11-10 14:26:48 +0000 | [diff] [blame] | 391 | }; |
| 392 | |
| 393 | static struct clk tc2_ck = { |
| 394 | .name = "tc2_ck", |
Russell King | 548d849 | 2008-11-04 14:02:46 +0000 | [diff] [blame] | 395 | .ops = &clkops_generic, |
Tony Lindgren | 3179a01 | 2005-11-10 14:26:48 +0000 | [diff] [blame] | 396 | .parent = &tc_ck.clk, |
| 397 | .flags = CLOCK_IN_OMAP16XX, |
| 398 | .enable_reg = (void __iomem *)ARM_IDLECT3, |
| 399 | .enable_bit = EN_TC2_CK, |
| 400 | .recalc = &followparent_recalc, |
Tony Lindgren | 3179a01 | 2005-11-10 14:26:48 +0000 | [diff] [blame] | 401 | }; |
| 402 | |
| 403 | static struct clk dma_ck = { |
| 404 | /* No-idle controlled by "tc_ck" */ |
| 405 | .name = "dma_ck", |
Russell King | 897dcde | 2008-11-04 16:35:03 +0000 | [diff] [blame^] | 406 | .ops = &clkops_null, |
Tony Lindgren | 3179a01 | 2005-11-10 14:26:48 +0000 | [diff] [blame] | 407 | .parent = &tc_ck.clk, |
| 408 | .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | |
Russell King | 897dcde | 2008-11-04 16:35:03 +0000 | [diff] [blame^] | 409 | CLOCK_IN_OMAP310, |
Tony Lindgren | 3179a01 | 2005-11-10 14:26:48 +0000 | [diff] [blame] | 410 | .recalc = &followparent_recalc, |
Tony Lindgren | 3179a01 | 2005-11-10 14:26:48 +0000 | [diff] [blame] | 411 | }; |
| 412 | |
| 413 | static struct clk dma_lcdfree_ck = { |
| 414 | .name = "dma_lcdfree_ck", |
Russell King | 897dcde | 2008-11-04 16:35:03 +0000 | [diff] [blame^] | 415 | .ops = &clkops_null, |
Tony Lindgren | 3179a01 | 2005-11-10 14:26:48 +0000 | [diff] [blame] | 416 | .parent = &tc_ck.clk, |
Russell King | 897dcde | 2008-11-04 16:35:03 +0000 | [diff] [blame^] | 417 | .flags = CLOCK_IN_OMAP16XX, |
Tony Lindgren | 3179a01 | 2005-11-10 14:26:48 +0000 | [diff] [blame] | 418 | .recalc = &followparent_recalc, |
Tony Lindgren | 3179a01 | 2005-11-10 14:26:48 +0000 | [diff] [blame] | 419 | }; |
| 420 | |
| 421 | static struct arm_idlect1_clk api_ck = { |
| 422 | .clk = { |
| 423 | .name = "api_ck", |
Russell King | 548d849 | 2008-11-04 14:02:46 +0000 | [diff] [blame] | 424 | .ops = &clkops_generic, |
Tony Lindgren | 3179a01 | 2005-11-10 14:26:48 +0000 | [diff] [blame] | 425 | .parent = &tc_ck.clk, |
| 426 | .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | |
Tony Lindgren | b824efa | 2006-04-02 17:46:20 +0100 | [diff] [blame] | 427 | CLOCK_IN_OMAP310 | CLOCK_IDLE_CONTROL, |
Tony Lindgren | 3179a01 | 2005-11-10 14:26:48 +0000 | [diff] [blame] | 428 | .enable_reg = (void __iomem *)ARM_IDLECT2, |
| 429 | .enable_bit = EN_APICK, |
| 430 | .recalc = &followparent_recalc, |
Tony Lindgren | 3179a01 | 2005-11-10 14:26:48 +0000 | [diff] [blame] | 431 | }, |
| 432 | .idlect_shift = 8, |
| 433 | }; |
| 434 | |
| 435 | static struct arm_idlect1_clk lb_ck = { |
| 436 | .clk = { |
| 437 | .name = "lb_ck", |
Russell King | 548d849 | 2008-11-04 14:02:46 +0000 | [diff] [blame] | 438 | .ops = &clkops_generic, |
Tony Lindgren | 3179a01 | 2005-11-10 14:26:48 +0000 | [diff] [blame] | 439 | .parent = &tc_ck.clk, |
Tony Lindgren | b824efa | 2006-04-02 17:46:20 +0100 | [diff] [blame] | 440 | .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310 | |
| 441 | CLOCK_IDLE_CONTROL, |
Tony Lindgren | 3179a01 | 2005-11-10 14:26:48 +0000 | [diff] [blame] | 442 | .enable_reg = (void __iomem *)ARM_IDLECT2, |
| 443 | .enable_bit = EN_LBCK, |
| 444 | .recalc = &followparent_recalc, |
Tony Lindgren | 3179a01 | 2005-11-10 14:26:48 +0000 | [diff] [blame] | 445 | }, |
| 446 | .idlect_shift = 4, |
| 447 | }; |
| 448 | |
| 449 | static struct clk rhea1_ck = { |
| 450 | .name = "rhea1_ck", |
Russell King | 897dcde | 2008-11-04 16:35:03 +0000 | [diff] [blame^] | 451 | .ops = &clkops_null, |
Tony Lindgren | 3179a01 | 2005-11-10 14:26:48 +0000 | [diff] [blame] | 452 | .parent = &tc_ck.clk, |
Russell King | 897dcde | 2008-11-04 16:35:03 +0000 | [diff] [blame^] | 453 | .flags = CLOCK_IN_OMAP16XX, |
Tony Lindgren | 3179a01 | 2005-11-10 14:26:48 +0000 | [diff] [blame] | 454 | .recalc = &followparent_recalc, |
Tony Lindgren | 3179a01 | 2005-11-10 14:26:48 +0000 | [diff] [blame] | 455 | }; |
| 456 | |
| 457 | static struct clk rhea2_ck = { |
| 458 | .name = "rhea2_ck", |
Russell King | 897dcde | 2008-11-04 16:35:03 +0000 | [diff] [blame^] | 459 | .ops = &clkops_null, |
Tony Lindgren | 3179a01 | 2005-11-10 14:26:48 +0000 | [diff] [blame] | 460 | .parent = &tc_ck.clk, |
Russell King | 897dcde | 2008-11-04 16:35:03 +0000 | [diff] [blame^] | 461 | .flags = CLOCK_IN_OMAP16XX, |
Tony Lindgren | 3179a01 | 2005-11-10 14:26:48 +0000 | [diff] [blame] | 462 | .recalc = &followparent_recalc, |
Tony Lindgren | 3179a01 | 2005-11-10 14:26:48 +0000 | [diff] [blame] | 463 | }; |
| 464 | |
| 465 | static struct clk lcd_ck_16xx = { |
| 466 | .name = "lcd_ck", |
Russell King | 548d849 | 2008-11-04 14:02:46 +0000 | [diff] [blame] | 467 | .ops = &clkops_generic, |
Tony Lindgren | 3179a01 | 2005-11-10 14:26:48 +0000 | [diff] [blame] | 468 | .parent = &ck_dpll1, |
| 469 | .flags = CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP730 | RATE_CKCTL, |
| 470 | .enable_reg = (void __iomem *)ARM_IDLECT2, |
| 471 | .enable_bit = EN_LCDCK, |
| 472 | .rate_offset = CKCTL_LCDDIV_OFFSET, |
| 473 | .recalc = &omap1_ckctl_recalc, |
Tony Lindgren | 3179a01 | 2005-11-10 14:26:48 +0000 | [diff] [blame] | 474 | }; |
| 475 | |
| 476 | static struct arm_idlect1_clk lcd_ck_1510 = { |
| 477 | .clk = { |
| 478 | .name = "lcd_ck", |
Russell King | 548d849 | 2008-11-04 14:02:46 +0000 | [diff] [blame] | 479 | .ops = &clkops_generic, |
Tony Lindgren | 3179a01 | 2005-11-10 14:26:48 +0000 | [diff] [blame] | 480 | .parent = &ck_dpll1, |
Tony Lindgren | b824efa | 2006-04-02 17:46:20 +0100 | [diff] [blame] | 481 | .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310 | |
| 482 | RATE_CKCTL | CLOCK_IDLE_CONTROL, |
Tony Lindgren | 3179a01 | 2005-11-10 14:26:48 +0000 | [diff] [blame] | 483 | .enable_reg = (void __iomem *)ARM_IDLECT2, |
| 484 | .enable_bit = EN_LCDCK, |
| 485 | .rate_offset = CKCTL_LCDDIV_OFFSET, |
| 486 | .recalc = &omap1_ckctl_recalc, |
Tony Lindgren | 3179a01 | 2005-11-10 14:26:48 +0000 | [diff] [blame] | 487 | }, |
| 488 | .idlect_shift = 3, |
| 489 | }; |
| 490 | |
| 491 | static struct clk uart1_1510 = { |
| 492 | .name = "uart1_ck", |
Russell King | 897dcde | 2008-11-04 16:35:03 +0000 | [diff] [blame^] | 493 | .ops = &clkops_null, |
Tony Lindgren | 3179a01 | 2005-11-10 14:26:48 +0000 | [diff] [blame] | 494 | /* Direct from ULPD, no real parent */ |
| 495 | .parent = &armper_ck.clk, |
| 496 | .rate = 12000000, |
Tony Lindgren | b824efa | 2006-04-02 17:46:20 +0100 | [diff] [blame] | 497 | .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310 | |
Russell King | 897dcde | 2008-11-04 16:35:03 +0000 | [diff] [blame^] | 498 | ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT, |
Tony Lindgren | 3179a01 | 2005-11-10 14:26:48 +0000 | [diff] [blame] | 499 | .enable_reg = (void __iomem *)MOD_CONF_CTRL_0, |
| 500 | .enable_bit = 29, /* Chooses between 12MHz and 48MHz */ |
| 501 | .set_rate = &omap1_set_uart_rate, |
| 502 | .recalc = &omap1_uart_recalc, |
Tony Lindgren | 3179a01 | 2005-11-10 14:26:48 +0000 | [diff] [blame] | 503 | }; |
| 504 | |
| 505 | static struct uart_clk uart1_16xx = { |
| 506 | .clk = { |
| 507 | .name = "uart1_ck", |
Russell King | 548d849 | 2008-11-04 14:02:46 +0000 | [diff] [blame] | 508 | .ops = &clkops_uart, |
Tony Lindgren | 3179a01 | 2005-11-10 14:26:48 +0000 | [diff] [blame] | 509 | /* Direct from ULPD, no real parent */ |
| 510 | .parent = &armper_ck.clk, |
| 511 | .rate = 48000000, |
| 512 | .flags = CLOCK_IN_OMAP16XX | RATE_FIXED | |
| 513 | ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT, |
| 514 | .enable_reg = (void __iomem *)MOD_CONF_CTRL_0, |
| 515 | .enable_bit = 29, |
Tony Lindgren | 3179a01 | 2005-11-10 14:26:48 +0000 | [diff] [blame] | 516 | }, |
| 517 | .sysc_addr = 0xfffb0054, |
| 518 | }; |
| 519 | |
| 520 | static struct clk uart2_ck = { |
| 521 | .name = "uart2_ck", |
Russell King | 897dcde | 2008-11-04 16:35:03 +0000 | [diff] [blame^] | 522 | .ops = &clkops_null, |
Tony Lindgren | 3179a01 | 2005-11-10 14:26:48 +0000 | [diff] [blame] | 523 | /* Direct from ULPD, no real parent */ |
| 524 | .parent = &armper_ck.clk, |
| 525 | .rate = 12000000, |
| 526 | .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | |
Tony Lindgren | b824efa | 2006-04-02 17:46:20 +0100 | [diff] [blame] | 527 | CLOCK_IN_OMAP310 | ENABLE_REG_32BIT | |
Russell King | 897dcde | 2008-11-04 16:35:03 +0000 | [diff] [blame^] | 528 | CLOCK_NO_IDLE_PARENT, |
Tony Lindgren | 3179a01 | 2005-11-10 14:26:48 +0000 | [diff] [blame] | 529 | .enable_reg = (void __iomem *)MOD_CONF_CTRL_0, |
| 530 | .enable_bit = 30, /* Chooses between 12MHz and 48MHz */ |
| 531 | .set_rate = &omap1_set_uart_rate, |
| 532 | .recalc = &omap1_uart_recalc, |
Tony Lindgren | 3179a01 | 2005-11-10 14:26:48 +0000 | [diff] [blame] | 533 | }; |
| 534 | |
| 535 | static struct clk uart3_1510 = { |
| 536 | .name = "uart3_ck", |
Russell King | 897dcde | 2008-11-04 16:35:03 +0000 | [diff] [blame^] | 537 | .ops = &clkops_null, |
Tony Lindgren | 3179a01 | 2005-11-10 14:26:48 +0000 | [diff] [blame] | 538 | /* Direct from ULPD, no real parent */ |
| 539 | .parent = &armper_ck.clk, |
| 540 | .rate = 12000000, |
Tony Lindgren | b824efa | 2006-04-02 17:46:20 +0100 | [diff] [blame] | 541 | .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310 | |
Russell King | 897dcde | 2008-11-04 16:35:03 +0000 | [diff] [blame^] | 542 | ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT, |
Tony Lindgren | 3179a01 | 2005-11-10 14:26:48 +0000 | [diff] [blame] | 543 | .enable_reg = (void __iomem *)MOD_CONF_CTRL_0, |
| 544 | .enable_bit = 31, /* Chooses between 12MHz and 48MHz */ |
| 545 | .set_rate = &omap1_set_uart_rate, |
| 546 | .recalc = &omap1_uart_recalc, |
Tony Lindgren | 3179a01 | 2005-11-10 14:26:48 +0000 | [diff] [blame] | 547 | }; |
| 548 | |
| 549 | static struct uart_clk uart3_16xx = { |
| 550 | .clk = { |
| 551 | .name = "uart3_ck", |
Russell King | 548d849 | 2008-11-04 14:02:46 +0000 | [diff] [blame] | 552 | .ops = &clkops_uart, |
Tony Lindgren | 3179a01 | 2005-11-10 14:26:48 +0000 | [diff] [blame] | 553 | /* Direct from ULPD, no real parent */ |
| 554 | .parent = &armper_ck.clk, |
| 555 | .rate = 48000000, |
| 556 | .flags = CLOCK_IN_OMAP16XX | RATE_FIXED | |
| 557 | ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT, |
| 558 | .enable_reg = (void __iomem *)MOD_CONF_CTRL_0, |
| 559 | .enable_bit = 31, |
Tony Lindgren | 3179a01 | 2005-11-10 14:26:48 +0000 | [diff] [blame] | 560 | }, |
| 561 | .sysc_addr = 0xfffb9854, |
| 562 | }; |
| 563 | |
| 564 | static struct clk usb_clko = { /* 6 MHz output on W4_USB_CLKO */ |
| 565 | .name = "usb_clko", |
Russell King | 548d849 | 2008-11-04 14:02:46 +0000 | [diff] [blame] | 566 | .ops = &clkops_generic, |
Tony Lindgren | 3179a01 | 2005-11-10 14:26:48 +0000 | [diff] [blame] | 567 | /* Direct from ULPD, no parent */ |
| 568 | .rate = 6000000, |
| 569 | .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | |
Tony Lindgren | b824efa | 2006-04-02 17:46:20 +0100 | [diff] [blame] | 570 | CLOCK_IN_OMAP310 | RATE_FIXED | ENABLE_REG_32BIT, |
Tony Lindgren | 3179a01 | 2005-11-10 14:26:48 +0000 | [diff] [blame] | 571 | .enable_reg = (void __iomem *)ULPD_CLOCK_CTRL, |
| 572 | .enable_bit = USB_MCLK_EN_BIT, |
Tony Lindgren | 3179a01 | 2005-11-10 14:26:48 +0000 | [diff] [blame] | 573 | }; |
| 574 | |
| 575 | static struct clk usb_hhc_ck1510 = { |
| 576 | .name = "usb_hhc_ck", |
Russell King | 548d849 | 2008-11-04 14:02:46 +0000 | [diff] [blame] | 577 | .ops = &clkops_generic, |
Tony Lindgren | 3179a01 | 2005-11-10 14:26:48 +0000 | [diff] [blame] | 578 | /* Direct from ULPD, no parent */ |
| 579 | .rate = 48000000, /* Actually 2 clocks, 12MHz and 48MHz */ |
Tony Lindgren | b824efa | 2006-04-02 17:46:20 +0100 | [diff] [blame] | 580 | .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310 | |
Tony Lindgren | 3179a01 | 2005-11-10 14:26:48 +0000 | [diff] [blame] | 581 | RATE_FIXED | ENABLE_REG_32BIT, |
| 582 | .enable_reg = (void __iomem *)MOD_CONF_CTRL_0, |
| 583 | .enable_bit = USB_HOST_HHC_UHOST_EN, |
Tony Lindgren | 3179a01 | 2005-11-10 14:26:48 +0000 | [diff] [blame] | 584 | }; |
| 585 | |
| 586 | static struct clk usb_hhc_ck16xx = { |
| 587 | .name = "usb_hhc_ck", |
Russell King | 548d849 | 2008-11-04 14:02:46 +0000 | [diff] [blame] | 588 | .ops = &clkops_generic, |
Tony Lindgren | 3179a01 | 2005-11-10 14:26:48 +0000 | [diff] [blame] | 589 | /* Direct from ULPD, no parent */ |
| 590 | .rate = 48000000, |
| 591 | /* OTG_SYSCON_2.OTG_PADEN == 0 (not 1510-compatible) */ |
| 592 | .flags = CLOCK_IN_OMAP16XX | |
| 593 | RATE_FIXED | ENABLE_REG_32BIT, |
| 594 | .enable_reg = (void __iomem *)OTG_BASE + 0x08 /* OTG_SYSCON_2 */, |
| 595 | .enable_bit = 8 /* UHOST_EN */, |
Tony Lindgren | 3179a01 | 2005-11-10 14:26:48 +0000 | [diff] [blame] | 596 | }; |
| 597 | |
| 598 | static struct clk usb_dc_ck = { |
| 599 | .name = "usb_dc_ck", |
Russell King | 548d849 | 2008-11-04 14:02:46 +0000 | [diff] [blame] | 600 | .ops = &clkops_generic, |
Tony Lindgren | 3179a01 | 2005-11-10 14:26:48 +0000 | [diff] [blame] | 601 | /* Direct from ULPD, no parent */ |
| 602 | .rate = 48000000, |
| 603 | .flags = CLOCK_IN_OMAP16XX | RATE_FIXED, |
| 604 | .enable_reg = (void __iomem *)SOFT_REQ_REG, |
| 605 | .enable_bit = 4, |
Tony Lindgren | 3179a01 | 2005-11-10 14:26:48 +0000 | [diff] [blame] | 606 | }; |
| 607 | |
| 608 | static struct clk mclk_1510 = { |
| 609 | .name = "mclk", |
Russell King | 548d849 | 2008-11-04 14:02:46 +0000 | [diff] [blame] | 610 | .ops = &clkops_generic, |
Tony Lindgren | 3179a01 | 2005-11-10 14:26:48 +0000 | [diff] [blame] | 611 | /* Direct from ULPD, no parent. May be enabled by ext hardware. */ |
| 612 | .rate = 12000000, |
Tony Lindgren | b824efa | 2006-04-02 17:46:20 +0100 | [diff] [blame] | 613 | .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310 | RATE_FIXED, |
| 614 | .enable_reg = (void __iomem *)SOFT_REQ_REG, |
| 615 | .enable_bit = 6, |
Tony Lindgren | 3179a01 | 2005-11-10 14:26:48 +0000 | [diff] [blame] | 616 | }; |
| 617 | |
| 618 | static struct clk mclk_16xx = { |
| 619 | .name = "mclk", |
Russell King | 548d849 | 2008-11-04 14:02:46 +0000 | [diff] [blame] | 620 | .ops = &clkops_generic, |
Tony Lindgren | 3179a01 | 2005-11-10 14:26:48 +0000 | [diff] [blame] | 621 | /* Direct from ULPD, no parent. May be enabled by ext hardware. */ |
| 622 | .flags = CLOCK_IN_OMAP16XX, |
| 623 | .enable_reg = (void __iomem *)COM_CLK_DIV_CTRL_SEL, |
| 624 | .enable_bit = COM_ULPD_PLL_CLK_REQ, |
| 625 | .set_rate = &omap1_set_ext_clk_rate, |
| 626 | .round_rate = &omap1_round_ext_clk_rate, |
| 627 | .init = &omap1_init_ext_clk, |
Tony Lindgren | 3179a01 | 2005-11-10 14:26:48 +0000 | [diff] [blame] | 628 | }; |
| 629 | |
| 630 | static struct clk bclk_1510 = { |
| 631 | .name = "bclk", |
Russell King | 548d849 | 2008-11-04 14:02:46 +0000 | [diff] [blame] | 632 | .ops = &clkops_generic, |
Tony Lindgren | 3179a01 | 2005-11-10 14:26:48 +0000 | [diff] [blame] | 633 | /* Direct from ULPD, no parent. May be enabled by ext hardware. */ |
| 634 | .rate = 12000000, |
Tony Lindgren | b824efa | 2006-04-02 17:46:20 +0100 | [diff] [blame] | 635 | .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310 | RATE_FIXED, |
Tony Lindgren | 3179a01 | 2005-11-10 14:26:48 +0000 | [diff] [blame] | 636 | }; |
| 637 | |
| 638 | static struct clk bclk_16xx = { |
| 639 | .name = "bclk", |
Russell King | 548d849 | 2008-11-04 14:02:46 +0000 | [diff] [blame] | 640 | .ops = &clkops_generic, |
Tony Lindgren | 3179a01 | 2005-11-10 14:26:48 +0000 | [diff] [blame] | 641 | /* Direct from ULPD, no parent. May be enabled by ext hardware. */ |
| 642 | .flags = CLOCK_IN_OMAP16XX, |
| 643 | .enable_reg = (void __iomem *)SWD_CLK_DIV_CTRL_SEL, |
| 644 | .enable_bit = SWD_ULPD_PLL_CLK_REQ, |
| 645 | .set_rate = &omap1_set_ext_clk_rate, |
| 646 | .round_rate = &omap1_round_ext_clk_rate, |
| 647 | .init = &omap1_init_ext_clk, |
Tony Lindgren | 3179a01 | 2005-11-10 14:26:48 +0000 | [diff] [blame] | 648 | }; |
| 649 | |
| 650 | static struct clk mmc1_ck = { |
Tony Lindgren | b824efa | 2006-04-02 17:46:20 +0100 | [diff] [blame] | 651 | .name = "mmc_ck", |
Russell King | 548d849 | 2008-11-04 14:02:46 +0000 | [diff] [blame] | 652 | .ops = &clkops_generic, |
Tony Lindgren | 3179a01 | 2005-11-10 14:26:48 +0000 | [diff] [blame] | 653 | /* Functional clock is direct from ULPD, interface clock is ARMPER */ |
| 654 | .parent = &armper_ck.clk, |
| 655 | .rate = 48000000, |
| 656 | .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | |
Tony Lindgren | b824efa | 2006-04-02 17:46:20 +0100 | [diff] [blame] | 657 | CLOCK_IN_OMAP310 | RATE_FIXED | ENABLE_REG_32BIT | |
| 658 | CLOCK_NO_IDLE_PARENT, |
Tony Lindgren | 3179a01 | 2005-11-10 14:26:48 +0000 | [diff] [blame] | 659 | .enable_reg = (void __iomem *)MOD_CONF_CTRL_0, |
| 660 | .enable_bit = 23, |
Tony Lindgren | 3179a01 | 2005-11-10 14:26:48 +0000 | [diff] [blame] | 661 | }; |
| 662 | |
| 663 | static struct clk mmc2_ck = { |
Tony Lindgren | b824efa | 2006-04-02 17:46:20 +0100 | [diff] [blame] | 664 | .name = "mmc_ck", |
Tony Lindgren | d887466 | 2008-12-10 17:37:16 -0800 | [diff] [blame] | 665 | .id = 1, |
Russell King | 548d849 | 2008-11-04 14:02:46 +0000 | [diff] [blame] | 666 | .ops = &clkops_generic, |
Tony Lindgren | 3179a01 | 2005-11-10 14:26:48 +0000 | [diff] [blame] | 667 | /* Functional clock is direct from ULPD, interface clock is ARMPER */ |
| 668 | .parent = &armper_ck.clk, |
| 669 | .rate = 48000000, |
| 670 | .flags = CLOCK_IN_OMAP16XX | |
| 671 | RATE_FIXED | ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT, |
| 672 | .enable_reg = (void __iomem *)MOD_CONF_CTRL_0, |
| 673 | .enable_bit = 20, |
Tony Lindgren | 3179a01 | 2005-11-10 14:26:48 +0000 | [diff] [blame] | 674 | }; |
| 675 | |
| 676 | static struct clk virtual_ck_mpu = { |
| 677 | .name = "mpu", |
Russell King | 897dcde | 2008-11-04 16:35:03 +0000 | [diff] [blame^] | 678 | .ops = &clkops_null, |
Tony Lindgren | 3179a01 | 2005-11-10 14:26:48 +0000 | [diff] [blame] | 679 | .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | |
Russell King | 897dcde | 2008-11-04 16:35:03 +0000 | [diff] [blame^] | 680 | CLOCK_IN_OMAP310, |
Tony Lindgren | 3179a01 | 2005-11-10 14:26:48 +0000 | [diff] [blame] | 681 | .parent = &arm_ck, /* Is smarter alias for */ |
| 682 | .recalc = &followparent_recalc, |
| 683 | .set_rate = &omap1_select_table_rate, |
| 684 | .round_rate = &omap1_round_to_table_rate, |
Tony Lindgren | 3179a01 | 2005-11-10 14:26:48 +0000 | [diff] [blame] | 685 | }; |
| 686 | |
Tony Lindgren | b824efa | 2006-04-02 17:46:20 +0100 | [diff] [blame] | 687 | /* virtual functional clock domain for I2C. Just for making sure that ARMXOR_CK |
| 688 | remains active during MPU idle whenever this is enabled */ |
| 689 | static struct clk i2c_fck = { |
| 690 | .name = "i2c_fck", |
| 691 | .id = 1, |
Russell King | 897dcde | 2008-11-04 16:35:03 +0000 | [diff] [blame^] | 692 | .ops = &clkops_null, |
Marek Vasut | 6017e29 | 2006-12-06 17:13:55 -0800 | [diff] [blame] | 693 | .flags = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | |
Russell King | 897dcde | 2008-11-04 16:35:03 +0000 | [diff] [blame^] | 694 | CLOCK_NO_IDLE_PARENT, |
Tony Lindgren | b824efa | 2006-04-02 17:46:20 +0100 | [diff] [blame] | 695 | .parent = &armxor_ck.clk, |
| 696 | .recalc = &followparent_recalc, |
Tony Lindgren | b824efa | 2006-04-02 17:46:20 +0100 | [diff] [blame] | 697 | }; |
| 698 | |
Tony Lindgren | 90afd5c | 2006-09-25 13:27:20 +0300 | [diff] [blame] | 699 | static struct clk i2c_ick = { |
| 700 | .name = "i2c_ick", |
| 701 | .id = 1, |
Russell King | 897dcde | 2008-11-04 16:35:03 +0000 | [diff] [blame^] | 702 | .ops = &clkops_null, |
| 703 | .flags = CLOCK_IN_OMAP16XX | CLOCK_NO_IDLE_PARENT, |
Tony Lindgren | 90afd5c | 2006-09-25 13:27:20 +0300 | [diff] [blame] | 704 | .parent = &armper_ck.clk, |
| 705 | .recalc = &followparent_recalc, |
Tony Lindgren | 90afd5c | 2006-09-25 13:27:20 +0300 | [diff] [blame] | 706 | }; |
| 707 | |
Tony Lindgren | 3179a01 | 2005-11-10 14:26:48 +0000 | [diff] [blame] | 708 | static struct clk * onchip_clks[] = { |
| 709 | /* non-ULPD clocks */ |
| 710 | &ck_ref, |
| 711 | &ck_dpll1, |
| 712 | /* CK_GEN1 clocks */ |
| 713 | &ck_dpll1out.clk, |
Imre Deak | df2c2e7 | 2007-03-05 17:22:58 +0200 | [diff] [blame] | 714 | &sossi_ck, |
Tony Lindgren | 3179a01 | 2005-11-10 14:26:48 +0000 | [diff] [blame] | 715 | &arm_ck, |
| 716 | &armper_ck.clk, |
| 717 | &arm_gpio_ck, |
| 718 | &armxor_ck.clk, |
| 719 | &armtim_ck.clk, |
| 720 | &armwdt_ck.clk, |
| 721 | &arminth_ck1510, &arminth_ck16xx, |
| 722 | /* CK_GEN2 clocks */ |
| 723 | &dsp_ck, |
| 724 | &dspmmu_ck, |
| 725 | &dspper_ck, |
| 726 | &dspxor_ck, |
| 727 | &dsptim_ck, |
| 728 | /* CK_GEN3 clocks */ |
| 729 | &tc_ck.clk, |
| 730 | &tipb_ck, |
| 731 | &l3_ocpi_ck, |
| 732 | &tc1_ck, |
| 733 | &tc2_ck, |
| 734 | &dma_ck, |
| 735 | &dma_lcdfree_ck, |
| 736 | &api_ck.clk, |
| 737 | &lb_ck.clk, |
| 738 | &rhea1_ck, |
| 739 | &rhea2_ck, |
| 740 | &lcd_ck_16xx, |
| 741 | &lcd_ck_1510.clk, |
| 742 | /* ULPD clocks */ |
| 743 | &uart1_1510, |
| 744 | &uart1_16xx.clk, |
| 745 | &uart2_ck, |
| 746 | &uart3_1510, |
| 747 | &uart3_16xx.clk, |
| 748 | &usb_clko, |
| 749 | &usb_hhc_ck1510, &usb_hhc_ck16xx, |
| 750 | &usb_dc_ck, |
| 751 | &mclk_1510, &mclk_16xx, |
| 752 | &bclk_1510, &bclk_16xx, |
| 753 | &mmc1_ck, |
| 754 | &mmc2_ck, |
| 755 | /* Virtual clocks */ |
| 756 | &virtual_ck_mpu, |
Tony Lindgren | b824efa | 2006-04-02 17:46:20 +0100 | [diff] [blame] | 757 | &i2c_fck, |
Tony Lindgren | 90afd5c | 2006-09-25 13:27:20 +0300 | [diff] [blame] | 758 | &i2c_ick, |
Tony Lindgren | 3179a01 | 2005-11-10 14:26:48 +0000 | [diff] [blame] | 759 | }; |
| 760 | |
| 761 | #endif |