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Tony Lindgren3179a012005-11-10 14:26:48 +00001/*
2 * linux/arch/arm/mach-omap1/clock.h
3 *
4 * Copyright (C) 2004 - 2005 Nokia corporation
5 * Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
6 * Based on clocks.h by Tony Lindgren, Gordon McNutt and RidgeRun, Inc
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13#ifndef __ARCH_ARM_MACH_OMAP1_CLOCK_H
14#define __ARCH_ARM_MACH_OMAP1_CLOCK_H
15
Tony Lindgren3179a012005-11-10 14:26:48 +000016static void omap1_ckctl_recalc(struct clk * clk);
17static void omap1_watchdog_recalc(struct clk * clk);
Imre Deakdf2c2e72007-03-05 17:22:58 +020018static int omap1_set_sossi_rate(struct clk *clk, unsigned long rate);
19static void omap1_sossi_recalc(struct clk *clk);
Tony Lindgren3179a012005-11-10 14:26:48 +000020static void omap1_ckctl_recalc_dsp_domain(struct clk * clk);
Tony Lindgren3179a012005-11-10 14:26:48 +000021static int omap1_clk_set_rate_dsp_domain(struct clk * clk, unsigned long rate);
Tony Lindgren3179a012005-11-10 14:26:48 +000022static int omap1_set_uart_rate(struct clk * clk, unsigned long rate);
23static void omap1_uart_recalc(struct clk * clk);
Tony Lindgren3179a012005-11-10 14:26:48 +000024static int omap1_set_ext_clk_rate(struct clk * clk, unsigned long rate);
25static long omap1_round_ext_clk_rate(struct clk * clk, unsigned long rate);
26static void omap1_init_ext_clk(struct clk * clk);
27static int omap1_select_table_rate(struct clk * clk, unsigned long rate);
28static long omap1_round_to_table_rate(struct clk * clk, unsigned long rate);
Tony Lindgren3179a012005-11-10 14:26:48 +000029
30struct mpu_rate {
31 unsigned long rate;
32 unsigned long xtal;
33 unsigned long pll_rate;
34 __u16 ckctl_val;
35 __u16 dpllctl_val;
36};
37
38struct uart_clk {
39 struct clk clk;
40 unsigned long sysc_addr;
41};
42
43/* Provide a method for preventing idling some ARM IDLECT clocks */
44struct arm_idlect1_clk {
45 struct clk clk;
46 unsigned long no_idle_count;
47 __u8 idlect_shift;
48};
49
50/* ARM_CKCTL bit shifts */
51#define CKCTL_PERDIV_OFFSET 0
52#define CKCTL_LCDDIV_OFFSET 2
53#define CKCTL_ARMDIV_OFFSET 4
54#define CKCTL_DSPDIV_OFFSET 6
55#define CKCTL_TCDIV_OFFSET 8
56#define CKCTL_DSPMMUDIV_OFFSET 10
57/*#define ARM_TIMXO 12*/
58#define EN_DSPCK 13
59/*#define ARM_INTHCK_SEL 14*/ /* Divide-by-2 for mpu inth_ck */
60/* DSP_CKCTL bit shifts */
61#define CKCTL_DSPPERDIV_OFFSET 0
62
63/* ARM_IDLECT2 bit shifts */
64#define EN_WDTCK 0
65#define EN_XORPCK 1
66#define EN_PERCK 2
67#define EN_LCDCK 3
68#define EN_LBCK 4 /* Not on 1610/1710 */
69/*#define EN_HSABCK 5*/
70#define EN_APICK 6
71#define EN_TIMCK 7
72#define DMACK_REQ 8
73#define EN_GPIOCK 9 /* Not on 1610/1710 */
74/*#define EN_LBFREECK 10*/
75#define EN_CKOUT_ARM 11
76
77/* ARM_IDLECT3 bit shifts */
78#define EN_OCPI_CK 0
79#define EN_TC1_CK 2
80#define EN_TC2_CK 4
81
82/* DSP_IDLECT2 bit shifts (0,1,2 are same as for ARM_IDLECT2) */
83#define EN_DSPTIMCK 5
84
85/* Various register defines for clock controls scattered around OMAP chip */
Tony Lindgren90afd5c2006-09-25 13:27:20 +030086#define SDW_MCLK_INV_BIT 2 /* In ULPD_CLKC_CTRL */
Tony Lindgren3179a012005-11-10 14:26:48 +000087#define USB_MCLK_EN_BIT 4 /* In ULPD_CLKC_CTRL */
88#define USB_HOST_HHC_UHOST_EN 9 /* In MOD_CONF_CTRL_0 */
89#define SWD_ULPD_PLL_CLK_REQ 1 /* In SWD_CLK_DIV_CTRL_SEL */
90#define COM_ULPD_PLL_CLK_REQ 1 /* In COM_CLK_DIV_CTRL_SEL */
91#define SWD_CLK_DIV_CTRL_SEL 0xfffe0874
92#define COM_CLK_DIV_CTRL_SEL 0xfffe0878
93#define SOFT_REQ_REG 0xfffe0834
94#define SOFT_REQ_REG2 0xfffe0880
95
96/*-------------------------------------------------------------------------
97 * Omap1 MPU rate table
98 *-------------------------------------------------------------------------*/
99static struct mpu_rate rate_table[] = {
100 /* MPU MHz, xtal MHz, dpll1 MHz, CKCTL, DPLL_CTL
101 * NOTE: Comment order here is different from bits in CKCTL value:
102 * armdiv, dspdiv, dspmmu, tcdiv, perdiv, lcddiv
103 */
104#if defined(CONFIG_OMAP_ARM_216MHZ)
105 { 216000000, 12000000, 216000000, 0x050d, 0x2910 }, /* 1/1/2/2/2/8 */
106#endif
107#if defined(CONFIG_OMAP_ARM_195MHZ)
108 { 195000000, 13000000, 195000000, 0x050e, 0x2790 }, /* 1/1/2/2/4/8 */
109#endif
110#if defined(CONFIG_OMAP_ARM_192MHZ)
111 { 192000000, 19200000, 192000000, 0x050f, 0x2510 }, /* 1/1/2/2/8/8 */
112 { 192000000, 12000000, 192000000, 0x050f, 0x2810 }, /* 1/1/2/2/8/8 */
113 { 96000000, 12000000, 192000000, 0x055f, 0x2810 }, /* 2/2/2/2/8/8 */
114 { 48000000, 12000000, 192000000, 0x0baf, 0x2810 }, /* 4/4/4/8/8/8 */
115 { 24000000, 12000000, 192000000, 0x0fff, 0x2810 }, /* 8/8/8/8/8/8 */
116#endif
117#if defined(CONFIG_OMAP_ARM_182MHZ)
118 { 182000000, 13000000, 182000000, 0x050e, 0x2710 }, /* 1/1/2/2/4/8 */
119#endif
120#if defined(CONFIG_OMAP_ARM_168MHZ)
121 { 168000000, 12000000, 168000000, 0x010f, 0x2710 }, /* 1/1/1/2/8/8 */
122#endif
123#if defined(CONFIG_OMAP_ARM_150MHZ)
124 { 150000000, 12000000, 150000000, 0x010a, 0x2cb0 }, /* 1/1/1/2/4/4 */
125#endif
126#if defined(CONFIG_OMAP_ARM_120MHZ)
127 { 120000000, 12000000, 120000000, 0x010a, 0x2510 }, /* 1/1/1/2/4/4 */
128#endif
129#if defined(CONFIG_OMAP_ARM_96MHZ)
130 { 96000000, 12000000, 96000000, 0x0005, 0x2410 }, /* 1/1/1/1/2/2 */
131#endif
132#if defined(CONFIG_OMAP_ARM_60MHZ)
133 { 60000000, 12000000, 60000000, 0x0005, 0x2290 }, /* 1/1/1/1/2/2 */
134#endif
135#if defined(CONFIG_OMAP_ARM_30MHZ)
136 { 30000000, 12000000, 60000000, 0x0555, 0x2290 }, /* 2/2/2/2/2/2 */
137#endif
138 { 0, 0, 0, 0, 0 },
139};
140
141/*-------------------------------------------------------------------------
142 * Omap1 clocks
143 *-------------------------------------------------------------------------*/
144
145static struct clk ck_ref = {
146 .name = "ck_ref",
Russell King897dcde2008-11-04 16:35:03 +0000147 .ops = &clkops_null,
Tony Lindgren3179a012005-11-10 14:26:48 +0000148 .rate = 12000000,
149 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
Russell King897dcde2008-11-04 16:35:03 +0000150 CLOCK_IN_OMAP310,
Tony Lindgren3179a012005-11-10 14:26:48 +0000151};
152
153static struct clk ck_dpll1 = {
154 .name = "ck_dpll1",
Russell King897dcde2008-11-04 16:35:03 +0000155 .ops = &clkops_null,
Tony Lindgren3179a012005-11-10 14:26:48 +0000156 .parent = &ck_ref,
157 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
Russell King897dcde2008-11-04 16:35:03 +0000158 CLOCK_IN_OMAP310 | RATE_PROPAGATES,
Tony Lindgren3179a012005-11-10 14:26:48 +0000159};
160
161static struct arm_idlect1_clk ck_dpll1out = {
162 .clk = {
Imre Deakdf2c2e72007-03-05 17:22:58 +0200163 .name = "ck_dpll1out",
Russell King548d8492008-11-04 14:02:46 +0000164 .ops = &clkops_generic,
Tony Lindgren3179a012005-11-10 14:26:48 +0000165 .parent = &ck_dpll1,
Imre Deakdf2c2e72007-03-05 17:22:58 +0200166 .flags = CLOCK_IN_OMAP16XX | CLOCK_IDLE_CONTROL |
167 ENABLE_REG_32BIT | RATE_PROPAGATES,
Tony Lindgren3179a012005-11-10 14:26:48 +0000168 .enable_reg = (void __iomem *)ARM_IDLECT2,
169 .enable_bit = EN_CKOUT_ARM,
170 .recalc = &followparent_recalc,
Tony Lindgren3179a012005-11-10 14:26:48 +0000171 },
172 .idlect_shift = 12,
173};
174
Imre Deakdf2c2e72007-03-05 17:22:58 +0200175static struct clk sossi_ck = {
176 .name = "ck_sossi",
Russell King548d8492008-11-04 14:02:46 +0000177 .ops = &clkops_generic,
Imre Deakdf2c2e72007-03-05 17:22:58 +0200178 .parent = &ck_dpll1out.clk,
179 .flags = CLOCK_IN_OMAP16XX | CLOCK_NO_IDLE_PARENT |
180 ENABLE_REG_32BIT,
181 .enable_reg = (void __iomem *)MOD_CONF_CTRL_1,
182 .enable_bit = 16,
183 .recalc = &omap1_sossi_recalc,
184 .set_rate = &omap1_set_sossi_rate,
Imre Deakdf2c2e72007-03-05 17:22:58 +0200185};
186
Tony Lindgren3179a012005-11-10 14:26:48 +0000187static struct clk arm_ck = {
188 .name = "arm_ck",
Russell King897dcde2008-11-04 16:35:03 +0000189 .ops = &clkops_null,
Tony Lindgren3179a012005-11-10 14:26:48 +0000190 .parent = &ck_dpll1,
191 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
Russell King897dcde2008-11-04 16:35:03 +0000192 CLOCK_IN_OMAP310 | RATE_CKCTL | RATE_PROPAGATES,
Tony Lindgren3179a012005-11-10 14:26:48 +0000193 .rate_offset = CKCTL_ARMDIV_OFFSET,
194 .recalc = &omap1_ckctl_recalc,
Tony Lindgren3179a012005-11-10 14:26:48 +0000195};
196
197static struct arm_idlect1_clk armper_ck = {
198 .clk = {
199 .name = "armper_ck",
Russell King548d8492008-11-04 14:02:46 +0000200 .ops = &clkops_generic,
Tony Lindgren3179a012005-11-10 14:26:48 +0000201 .parent = &ck_dpll1,
202 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
Tony Lindgrenb824efa2006-04-02 17:46:20 +0100203 CLOCK_IN_OMAP310 | RATE_CKCTL |
204 CLOCK_IDLE_CONTROL,
Tony Lindgren3179a012005-11-10 14:26:48 +0000205 .enable_reg = (void __iomem *)ARM_IDLECT2,
206 .enable_bit = EN_PERCK,
207 .rate_offset = CKCTL_PERDIV_OFFSET,
208 .recalc = &omap1_ckctl_recalc,
Tony Lindgren3179a012005-11-10 14:26:48 +0000209 },
210 .idlect_shift = 2,
211};
212
213static struct clk arm_gpio_ck = {
214 .name = "arm_gpio_ck",
Russell King548d8492008-11-04 14:02:46 +0000215 .ops = &clkops_generic,
Tony Lindgren3179a012005-11-10 14:26:48 +0000216 .parent = &ck_dpll1,
Tony Lindgrenb824efa2006-04-02 17:46:20 +0100217 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310,
Tony Lindgren3179a012005-11-10 14:26:48 +0000218 .enable_reg = (void __iomem *)ARM_IDLECT2,
219 .enable_bit = EN_GPIOCK,
220 .recalc = &followparent_recalc,
Tony Lindgren3179a012005-11-10 14:26:48 +0000221};
222
223static struct arm_idlect1_clk armxor_ck = {
224 .clk = {
225 .name = "armxor_ck",
Russell King548d8492008-11-04 14:02:46 +0000226 .ops = &clkops_generic,
Tony Lindgren3179a012005-11-10 14:26:48 +0000227 .parent = &ck_ref,
228 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
Tony Lindgrenb824efa2006-04-02 17:46:20 +0100229 CLOCK_IN_OMAP310 | CLOCK_IDLE_CONTROL,
Tony Lindgren3179a012005-11-10 14:26:48 +0000230 .enable_reg = (void __iomem *)ARM_IDLECT2,
231 .enable_bit = EN_XORPCK,
232 .recalc = &followparent_recalc,
Tony Lindgren3179a012005-11-10 14:26:48 +0000233 },
234 .idlect_shift = 1,
235};
236
237static struct arm_idlect1_clk armtim_ck = {
238 .clk = {
239 .name = "armtim_ck",
Russell King548d8492008-11-04 14:02:46 +0000240 .ops = &clkops_generic,
Tony Lindgren3179a012005-11-10 14:26:48 +0000241 .parent = &ck_ref,
242 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
Tony Lindgrenb824efa2006-04-02 17:46:20 +0100243 CLOCK_IN_OMAP310 | CLOCK_IDLE_CONTROL,
Tony Lindgren3179a012005-11-10 14:26:48 +0000244 .enable_reg = (void __iomem *)ARM_IDLECT2,
245 .enable_bit = EN_TIMCK,
246 .recalc = &followparent_recalc,
Tony Lindgren3179a012005-11-10 14:26:48 +0000247 },
248 .idlect_shift = 9,
249};
250
251static struct arm_idlect1_clk armwdt_ck = {
252 .clk = {
253 .name = "armwdt_ck",
Russell King548d8492008-11-04 14:02:46 +0000254 .ops = &clkops_generic,
Tony Lindgren3179a012005-11-10 14:26:48 +0000255 .parent = &ck_ref,
256 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
Tony Lindgrenb824efa2006-04-02 17:46:20 +0100257 CLOCK_IN_OMAP310 | CLOCK_IDLE_CONTROL,
Tony Lindgren3179a012005-11-10 14:26:48 +0000258 .enable_reg = (void __iomem *)ARM_IDLECT2,
259 .enable_bit = EN_WDTCK,
260 .recalc = &omap1_watchdog_recalc,
Tony Lindgren3179a012005-11-10 14:26:48 +0000261 },
262 .idlect_shift = 0,
263};
264
265static struct clk arminth_ck16xx = {
266 .name = "arminth_ck",
Russell King897dcde2008-11-04 16:35:03 +0000267 .ops = &clkops_null,
Tony Lindgren3179a012005-11-10 14:26:48 +0000268 .parent = &arm_ck,
Russell King897dcde2008-11-04 16:35:03 +0000269 .flags = CLOCK_IN_OMAP16XX,
Tony Lindgren3179a012005-11-10 14:26:48 +0000270 .recalc = &followparent_recalc,
271 /* Note: On 16xx the frequency can be divided by 2 by programming
272 * ARM_CKCTL:ARM_INTHCK_SEL(14) to 1
273 *
274 * 1510 version is in TC clocks.
275 */
Tony Lindgren3179a012005-11-10 14:26:48 +0000276};
277
278static struct clk dsp_ck = {
279 .name = "dsp_ck",
Russell King548d8492008-11-04 14:02:46 +0000280 .ops = &clkops_generic,
Tony Lindgren3179a012005-11-10 14:26:48 +0000281 .parent = &ck_dpll1,
Marek Vasut6017e292006-12-06 17:13:55 -0800282 .flags = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
Tony Lindgren3179a012005-11-10 14:26:48 +0000283 RATE_CKCTL,
284 .enable_reg = (void __iomem *)ARM_CKCTL,
285 .enable_bit = EN_DSPCK,
286 .rate_offset = CKCTL_DSPDIV_OFFSET,
287 .recalc = &omap1_ckctl_recalc,
Tony Lindgren3179a012005-11-10 14:26:48 +0000288};
289
290static struct clk dspmmu_ck = {
291 .name = "dspmmu_ck",
Russell King897dcde2008-11-04 16:35:03 +0000292 .ops = &clkops_null,
Tony Lindgren3179a012005-11-10 14:26:48 +0000293 .parent = &ck_dpll1,
Marek Vasut6017e292006-12-06 17:13:55 -0800294 .flags = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
Russell King897dcde2008-11-04 16:35:03 +0000295 RATE_CKCTL,
Tony Lindgren3179a012005-11-10 14:26:48 +0000296 .rate_offset = CKCTL_DSPMMUDIV_OFFSET,
297 .recalc = &omap1_ckctl_recalc,
Tony Lindgren3179a012005-11-10 14:26:48 +0000298};
299
300static struct clk dspper_ck = {
301 .name = "dspper_ck",
Russell King548d8492008-11-04 14:02:46 +0000302 .ops = &clkops_dspck,
Tony Lindgren3179a012005-11-10 14:26:48 +0000303 .parent = &ck_dpll1,
Marek Vasut6017e292006-12-06 17:13:55 -0800304 .flags = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
Tony Lindgren3179a012005-11-10 14:26:48 +0000305 RATE_CKCTL | VIRTUAL_IO_ADDRESS,
Russell King397fcaf2008-09-05 15:46:19 +0100306 .enable_reg = DSP_IDLECT2,
Tony Lindgren3179a012005-11-10 14:26:48 +0000307 .enable_bit = EN_PERCK,
308 .rate_offset = CKCTL_PERDIV_OFFSET,
309 .recalc = &omap1_ckctl_recalc_dsp_domain,
310 .set_rate = &omap1_clk_set_rate_dsp_domain,
Tony Lindgren3179a012005-11-10 14:26:48 +0000311};
312
313static struct clk dspxor_ck = {
314 .name = "dspxor_ck",
Russell King548d8492008-11-04 14:02:46 +0000315 .ops = &clkops_dspck,
Tony Lindgren3179a012005-11-10 14:26:48 +0000316 .parent = &ck_ref,
Marek Vasut6017e292006-12-06 17:13:55 -0800317 .flags = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
Tony Lindgren3179a012005-11-10 14:26:48 +0000318 VIRTUAL_IO_ADDRESS,
Russell King397fcaf2008-09-05 15:46:19 +0100319 .enable_reg = DSP_IDLECT2,
Tony Lindgren3179a012005-11-10 14:26:48 +0000320 .enable_bit = EN_XORPCK,
321 .recalc = &followparent_recalc,
Tony Lindgren3179a012005-11-10 14:26:48 +0000322};
323
324static struct clk dsptim_ck = {
325 .name = "dsptim_ck",
Russell King548d8492008-11-04 14:02:46 +0000326 .ops = &clkops_dspck,
Tony Lindgren3179a012005-11-10 14:26:48 +0000327 .parent = &ck_ref,
Marek Vasut6017e292006-12-06 17:13:55 -0800328 .flags = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
Tony Lindgren3179a012005-11-10 14:26:48 +0000329 VIRTUAL_IO_ADDRESS,
Russell King397fcaf2008-09-05 15:46:19 +0100330 .enable_reg = DSP_IDLECT2,
Tony Lindgren3179a012005-11-10 14:26:48 +0000331 .enable_bit = EN_DSPTIMCK,
332 .recalc = &followparent_recalc,
Tony Lindgren3179a012005-11-10 14:26:48 +0000333};
334
335/* Tie ARM_IDLECT1:IDLIF_ARM to this logical clock structure */
336static struct arm_idlect1_clk tc_ck = {
337 .clk = {
338 .name = "tc_ck",
Russell King897dcde2008-11-04 16:35:03 +0000339 .ops = &clkops_null,
Tony Lindgren3179a012005-11-10 14:26:48 +0000340 .parent = &ck_dpll1,
341 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
Tony Lindgrenb824efa2006-04-02 17:46:20 +0100342 CLOCK_IN_OMAP730 | CLOCK_IN_OMAP310 |
343 RATE_CKCTL | RATE_PROPAGATES |
Russell King897dcde2008-11-04 16:35:03 +0000344 CLOCK_IDLE_CONTROL,
Tony Lindgren3179a012005-11-10 14:26:48 +0000345 .rate_offset = CKCTL_TCDIV_OFFSET,
346 .recalc = &omap1_ckctl_recalc,
Tony Lindgren3179a012005-11-10 14:26:48 +0000347 },
348 .idlect_shift = 6,
349};
350
351static struct clk arminth_ck1510 = {
352 .name = "arminth_ck",
Russell King897dcde2008-11-04 16:35:03 +0000353 .ops = &clkops_null,
Tony Lindgren3179a012005-11-10 14:26:48 +0000354 .parent = &tc_ck.clk,
Russell King897dcde2008-11-04 16:35:03 +0000355 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310,
Tony Lindgren3179a012005-11-10 14:26:48 +0000356 .recalc = &followparent_recalc,
357 /* Note: On 1510 the frequency follows TC_CK
358 *
359 * 16xx version is in MPU clocks.
360 */
Tony Lindgren3179a012005-11-10 14:26:48 +0000361};
362
363static struct clk tipb_ck = {
364 /* No-idle controlled by "tc_ck" */
Marek Vasut6017e292006-12-06 17:13:55 -0800365 .name = "tipb_ck",
Russell King897dcde2008-11-04 16:35:03 +0000366 .ops = &clkops_null,
Tony Lindgren3179a012005-11-10 14:26:48 +0000367 .parent = &tc_ck.clk,
Russell King897dcde2008-11-04 16:35:03 +0000368 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310,
Tony Lindgren3179a012005-11-10 14:26:48 +0000369 .recalc = &followparent_recalc,
Tony Lindgren3179a012005-11-10 14:26:48 +0000370};
371
372static struct clk l3_ocpi_ck = {
373 /* No-idle controlled by "tc_ck" */
374 .name = "l3_ocpi_ck",
Russell King548d8492008-11-04 14:02:46 +0000375 .ops = &clkops_generic,
Tony Lindgren3179a012005-11-10 14:26:48 +0000376 .parent = &tc_ck.clk,
377 .flags = CLOCK_IN_OMAP16XX,
378 .enable_reg = (void __iomem *)ARM_IDLECT3,
379 .enable_bit = EN_OCPI_CK,
380 .recalc = &followparent_recalc,
Tony Lindgren3179a012005-11-10 14:26:48 +0000381};
382
383static struct clk tc1_ck = {
384 .name = "tc1_ck",
Russell King548d8492008-11-04 14:02:46 +0000385 .ops = &clkops_generic,
Tony Lindgren3179a012005-11-10 14:26:48 +0000386 .parent = &tc_ck.clk,
387 .flags = CLOCK_IN_OMAP16XX,
388 .enable_reg = (void __iomem *)ARM_IDLECT3,
389 .enable_bit = EN_TC1_CK,
390 .recalc = &followparent_recalc,
Tony Lindgren3179a012005-11-10 14:26:48 +0000391};
392
393static struct clk tc2_ck = {
394 .name = "tc2_ck",
Russell King548d8492008-11-04 14:02:46 +0000395 .ops = &clkops_generic,
Tony Lindgren3179a012005-11-10 14:26:48 +0000396 .parent = &tc_ck.clk,
397 .flags = CLOCK_IN_OMAP16XX,
398 .enable_reg = (void __iomem *)ARM_IDLECT3,
399 .enable_bit = EN_TC2_CK,
400 .recalc = &followparent_recalc,
Tony Lindgren3179a012005-11-10 14:26:48 +0000401};
402
403static struct clk dma_ck = {
404 /* No-idle controlled by "tc_ck" */
405 .name = "dma_ck",
Russell King897dcde2008-11-04 16:35:03 +0000406 .ops = &clkops_null,
Tony Lindgren3179a012005-11-10 14:26:48 +0000407 .parent = &tc_ck.clk,
408 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
Russell King897dcde2008-11-04 16:35:03 +0000409 CLOCK_IN_OMAP310,
Tony Lindgren3179a012005-11-10 14:26:48 +0000410 .recalc = &followparent_recalc,
Tony Lindgren3179a012005-11-10 14:26:48 +0000411};
412
413static struct clk dma_lcdfree_ck = {
414 .name = "dma_lcdfree_ck",
Russell King897dcde2008-11-04 16:35:03 +0000415 .ops = &clkops_null,
Tony Lindgren3179a012005-11-10 14:26:48 +0000416 .parent = &tc_ck.clk,
Russell King897dcde2008-11-04 16:35:03 +0000417 .flags = CLOCK_IN_OMAP16XX,
Tony Lindgren3179a012005-11-10 14:26:48 +0000418 .recalc = &followparent_recalc,
Tony Lindgren3179a012005-11-10 14:26:48 +0000419};
420
421static struct arm_idlect1_clk api_ck = {
422 .clk = {
423 .name = "api_ck",
Russell King548d8492008-11-04 14:02:46 +0000424 .ops = &clkops_generic,
Tony Lindgren3179a012005-11-10 14:26:48 +0000425 .parent = &tc_ck.clk,
426 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
Tony Lindgrenb824efa2006-04-02 17:46:20 +0100427 CLOCK_IN_OMAP310 | CLOCK_IDLE_CONTROL,
Tony Lindgren3179a012005-11-10 14:26:48 +0000428 .enable_reg = (void __iomem *)ARM_IDLECT2,
429 .enable_bit = EN_APICK,
430 .recalc = &followparent_recalc,
Tony Lindgren3179a012005-11-10 14:26:48 +0000431 },
432 .idlect_shift = 8,
433};
434
435static struct arm_idlect1_clk lb_ck = {
436 .clk = {
437 .name = "lb_ck",
Russell King548d8492008-11-04 14:02:46 +0000438 .ops = &clkops_generic,
Tony Lindgren3179a012005-11-10 14:26:48 +0000439 .parent = &tc_ck.clk,
Tony Lindgrenb824efa2006-04-02 17:46:20 +0100440 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310 |
441 CLOCK_IDLE_CONTROL,
Tony Lindgren3179a012005-11-10 14:26:48 +0000442 .enable_reg = (void __iomem *)ARM_IDLECT2,
443 .enable_bit = EN_LBCK,
444 .recalc = &followparent_recalc,
Tony Lindgren3179a012005-11-10 14:26:48 +0000445 },
446 .idlect_shift = 4,
447};
448
449static struct clk rhea1_ck = {
450 .name = "rhea1_ck",
Russell King897dcde2008-11-04 16:35:03 +0000451 .ops = &clkops_null,
Tony Lindgren3179a012005-11-10 14:26:48 +0000452 .parent = &tc_ck.clk,
Russell King897dcde2008-11-04 16:35:03 +0000453 .flags = CLOCK_IN_OMAP16XX,
Tony Lindgren3179a012005-11-10 14:26:48 +0000454 .recalc = &followparent_recalc,
Tony Lindgren3179a012005-11-10 14:26:48 +0000455};
456
457static struct clk rhea2_ck = {
458 .name = "rhea2_ck",
Russell King897dcde2008-11-04 16:35:03 +0000459 .ops = &clkops_null,
Tony Lindgren3179a012005-11-10 14:26:48 +0000460 .parent = &tc_ck.clk,
Russell King897dcde2008-11-04 16:35:03 +0000461 .flags = CLOCK_IN_OMAP16XX,
Tony Lindgren3179a012005-11-10 14:26:48 +0000462 .recalc = &followparent_recalc,
Tony Lindgren3179a012005-11-10 14:26:48 +0000463};
464
465static struct clk lcd_ck_16xx = {
466 .name = "lcd_ck",
Russell King548d8492008-11-04 14:02:46 +0000467 .ops = &clkops_generic,
Tony Lindgren3179a012005-11-10 14:26:48 +0000468 .parent = &ck_dpll1,
469 .flags = CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP730 | RATE_CKCTL,
470 .enable_reg = (void __iomem *)ARM_IDLECT2,
471 .enable_bit = EN_LCDCK,
472 .rate_offset = CKCTL_LCDDIV_OFFSET,
473 .recalc = &omap1_ckctl_recalc,
Tony Lindgren3179a012005-11-10 14:26:48 +0000474};
475
476static struct arm_idlect1_clk lcd_ck_1510 = {
477 .clk = {
478 .name = "lcd_ck",
Russell King548d8492008-11-04 14:02:46 +0000479 .ops = &clkops_generic,
Tony Lindgren3179a012005-11-10 14:26:48 +0000480 .parent = &ck_dpll1,
Tony Lindgrenb824efa2006-04-02 17:46:20 +0100481 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310 |
482 RATE_CKCTL | CLOCK_IDLE_CONTROL,
Tony Lindgren3179a012005-11-10 14:26:48 +0000483 .enable_reg = (void __iomem *)ARM_IDLECT2,
484 .enable_bit = EN_LCDCK,
485 .rate_offset = CKCTL_LCDDIV_OFFSET,
486 .recalc = &omap1_ckctl_recalc,
Tony Lindgren3179a012005-11-10 14:26:48 +0000487 },
488 .idlect_shift = 3,
489};
490
491static struct clk uart1_1510 = {
492 .name = "uart1_ck",
Russell King897dcde2008-11-04 16:35:03 +0000493 .ops = &clkops_null,
Tony Lindgren3179a012005-11-10 14:26:48 +0000494 /* Direct from ULPD, no real parent */
495 .parent = &armper_ck.clk,
496 .rate = 12000000,
Tony Lindgrenb824efa2006-04-02 17:46:20 +0100497 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310 |
Russell King897dcde2008-11-04 16:35:03 +0000498 ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
Tony Lindgren3179a012005-11-10 14:26:48 +0000499 .enable_reg = (void __iomem *)MOD_CONF_CTRL_0,
500 .enable_bit = 29, /* Chooses between 12MHz and 48MHz */
501 .set_rate = &omap1_set_uart_rate,
502 .recalc = &omap1_uart_recalc,
Tony Lindgren3179a012005-11-10 14:26:48 +0000503};
504
505static struct uart_clk uart1_16xx = {
506 .clk = {
507 .name = "uart1_ck",
Russell King548d8492008-11-04 14:02:46 +0000508 .ops = &clkops_uart,
Tony Lindgren3179a012005-11-10 14:26:48 +0000509 /* Direct from ULPD, no real parent */
510 .parent = &armper_ck.clk,
511 .rate = 48000000,
512 .flags = CLOCK_IN_OMAP16XX | RATE_FIXED |
513 ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
514 .enable_reg = (void __iomem *)MOD_CONF_CTRL_0,
515 .enable_bit = 29,
Tony Lindgren3179a012005-11-10 14:26:48 +0000516 },
517 .sysc_addr = 0xfffb0054,
518};
519
520static struct clk uart2_ck = {
521 .name = "uart2_ck",
Russell King897dcde2008-11-04 16:35:03 +0000522 .ops = &clkops_null,
Tony Lindgren3179a012005-11-10 14:26:48 +0000523 /* Direct from ULPD, no real parent */
524 .parent = &armper_ck.clk,
525 .rate = 12000000,
526 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
Tony Lindgrenb824efa2006-04-02 17:46:20 +0100527 CLOCK_IN_OMAP310 | ENABLE_REG_32BIT |
Russell King897dcde2008-11-04 16:35:03 +0000528 CLOCK_NO_IDLE_PARENT,
Tony Lindgren3179a012005-11-10 14:26:48 +0000529 .enable_reg = (void __iomem *)MOD_CONF_CTRL_0,
530 .enable_bit = 30, /* Chooses between 12MHz and 48MHz */
531 .set_rate = &omap1_set_uart_rate,
532 .recalc = &omap1_uart_recalc,
Tony Lindgren3179a012005-11-10 14:26:48 +0000533};
534
535static struct clk uart3_1510 = {
536 .name = "uart3_ck",
Russell King897dcde2008-11-04 16:35:03 +0000537 .ops = &clkops_null,
Tony Lindgren3179a012005-11-10 14:26:48 +0000538 /* Direct from ULPD, no real parent */
539 .parent = &armper_ck.clk,
540 .rate = 12000000,
Tony Lindgrenb824efa2006-04-02 17:46:20 +0100541 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310 |
Russell King897dcde2008-11-04 16:35:03 +0000542 ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
Tony Lindgren3179a012005-11-10 14:26:48 +0000543 .enable_reg = (void __iomem *)MOD_CONF_CTRL_0,
544 .enable_bit = 31, /* Chooses between 12MHz and 48MHz */
545 .set_rate = &omap1_set_uart_rate,
546 .recalc = &omap1_uart_recalc,
Tony Lindgren3179a012005-11-10 14:26:48 +0000547};
548
549static struct uart_clk uart3_16xx = {
550 .clk = {
551 .name = "uart3_ck",
Russell King548d8492008-11-04 14:02:46 +0000552 .ops = &clkops_uart,
Tony Lindgren3179a012005-11-10 14:26:48 +0000553 /* Direct from ULPD, no real parent */
554 .parent = &armper_ck.clk,
555 .rate = 48000000,
556 .flags = CLOCK_IN_OMAP16XX | RATE_FIXED |
557 ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
558 .enable_reg = (void __iomem *)MOD_CONF_CTRL_0,
559 .enable_bit = 31,
Tony Lindgren3179a012005-11-10 14:26:48 +0000560 },
561 .sysc_addr = 0xfffb9854,
562};
563
564static struct clk usb_clko = { /* 6 MHz output on W4_USB_CLKO */
565 .name = "usb_clko",
Russell King548d8492008-11-04 14:02:46 +0000566 .ops = &clkops_generic,
Tony Lindgren3179a012005-11-10 14:26:48 +0000567 /* Direct from ULPD, no parent */
568 .rate = 6000000,
569 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
Tony Lindgrenb824efa2006-04-02 17:46:20 +0100570 CLOCK_IN_OMAP310 | RATE_FIXED | ENABLE_REG_32BIT,
Tony Lindgren3179a012005-11-10 14:26:48 +0000571 .enable_reg = (void __iomem *)ULPD_CLOCK_CTRL,
572 .enable_bit = USB_MCLK_EN_BIT,
Tony Lindgren3179a012005-11-10 14:26:48 +0000573};
574
575static struct clk usb_hhc_ck1510 = {
576 .name = "usb_hhc_ck",
Russell King548d8492008-11-04 14:02:46 +0000577 .ops = &clkops_generic,
Tony Lindgren3179a012005-11-10 14:26:48 +0000578 /* Direct from ULPD, no parent */
579 .rate = 48000000, /* Actually 2 clocks, 12MHz and 48MHz */
Tony Lindgrenb824efa2006-04-02 17:46:20 +0100580 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310 |
Tony Lindgren3179a012005-11-10 14:26:48 +0000581 RATE_FIXED | ENABLE_REG_32BIT,
582 .enable_reg = (void __iomem *)MOD_CONF_CTRL_0,
583 .enable_bit = USB_HOST_HHC_UHOST_EN,
Tony Lindgren3179a012005-11-10 14:26:48 +0000584};
585
586static struct clk usb_hhc_ck16xx = {
587 .name = "usb_hhc_ck",
Russell King548d8492008-11-04 14:02:46 +0000588 .ops = &clkops_generic,
Tony Lindgren3179a012005-11-10 14:26:48 +0000589 /* Direct from ULPD, no parent */
590 .rate = 48000000,
591 /* OTG_SYSCON_2.OTG_PADEN == 0 (not 1510-compatible) */
592 .flags = CLOCK_IN_OMAP16XX |
593 RATE_FIXED | ENABLE_REG_32BIT,
594 .enable_reg = (void __iomem *)OTG_BASE + 0x08 /* OTG_SYSCON_2 */,
595 .enable_bit = 8 /* UHOST_EN */,
Tony Lindgren3179a012005-11-10 14:26:48 +0000596};
597
598static struct clk usb_dc_ck = {
599 .name = "usb_dc_ck",
Russell King548d8492008-11-04 14:02:46 +0000600 .ops = &clkops_generic,
Tony Lindgren3179a012005-11-10 14:26:48 +0000601 /* Direct from ULPD, no parent */
602 .rate = 48000000,
603 .flags = CLOCK_IN_OMAP16XX | RATE_FIXED,
604 .enable_reg = (void __iomem *)SOFT_REQ_REG,
605 .enable_bit = 4,
Tony Lindgren3179a012005-11-10 14:26:48 +0000606};
607
608static struct clk mclk_1510 = {
609 .name = "mclk",
Russell King548d8492008-11-04 14:02:46 +0000610 .ops = &clkops_generic,
Tony Lindgren3179a012005-11-10 14:26:48 +0000611 /* Direct from ULPD, no parent. May be enabled by ext hardware. */
612 .rate = 12000000,
Tony Lindgrenb824efa2006-04-02 17:46:20 +0100613 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310 | RATE_FIXED,
614 .enable_reg = (void __iomem *)SOFT_REQ_REG,
615 .enable_bit = 6,
Tony Lindgren3179a012005-11-10 14:26:48 +0000616};
617
618static struct clk mclk_16xx = {
619 .name = "mclk",
Russell King548d8492008-11-04 14:02:46 +0000620 .ops = &clkops_generic,
Tony Lindgren3179a012005-11-10 14:26:48 +0000621 /* Direct from ULPD, no parent. May be enabled by ext hardware. */
622 .flags = CLOCK_IN_OMAP16XX,
623 .enable_reg = (void __iomem *)COM_CLK_DIV_CTRL_SEL,
624 .enable_bit = COM_ULPD_PLL_CLK_REQ,
625 .set_rate = &omap1_set_ext_clk_rate,
626 .round_rate = &omap1_round_ext_clk_rate,
627 .init = &omap1_init_ext_clk,
Tony Lindgren3179a012005-11-10 14:26:48 +0000628};
629
630static struct clk bclk_1510 = {
631 .name = "bclk",
Russell King548d8492008-11-04 14:02:46 +0000632 .ops = &clkops_generic,
Tony Lindgren3179a012005-11-10 14:26:48 +0000633 /* Direct from ULPD, no parent. May be enabled by ext hardware. */
634 .rate = 12000000,
Tony Lindgrenb824efa2006-04-02 17:46:20 +0100635 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310 | RATE_FIXED,
Tony Lindgren3179a012005-11-10 14:26:48 +0000636};
637
638static struct clk bclk_16xx = {
639 .name = "bclk",
Russell King548d8492008-11-04 14:02:46 +0000640 .ops = &clkops_generic,
Tony Lindgren3179a012005-11-10 14:26:48 +0000641 /* Direct from ULPD, no parent. May be enabled by ext hardware. */
642 .flags = CLOCK_IN_OMAP16XX,
643 .enable_reg = (void __iomem *)SWD_CLK_DIV_CTRL_SEL,
644 .enable_bit = SWD_ULPD_PLL_CLK_REQ,
645 .set_rate = &omap1_set_ext_clk_rate,
646 .round_rate = &omap1_round_ext_clk_rate,
647 .init = &omap1_init_ext_clk,
Tony Lindgren3179a012005-11-10 14:26:48 +0000648};
649
650static struct clk mmc1_ck = {
Tony Lindgrenb824efa2006-04-02 17:46:20 +0100651 .name = "mmc_ck",
Russell King548d8492008-11-04 14:02:46 +0000652 .ops = &clkops_generic,
Tony Lindgren3179a012005-11-10 14:26:48 +0000653 /* Functional clock is direct from ULPD, interface clock is ARMPER */
654 .parent = &armper_ck.clk,
655 .rate = 48000000,
656 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
Tony Lindgrenb824efa2006-04-02 17:46:20 +0100657 CLOCK_IN_OMAP310 | RATE_FIXED | ENABLE_REG_32BIT |
658 CLOCK_NO_IDLE_PARENT,
Tony Lindgren3179a012005-11-10 14:26:48 +0000659 .enable_reg = (void __iomem *)MOD_CONF_CTRL_0,
660 .enable_bit = 23,
Tony Lindgren3179a012005-11-10 14:26:48 +0000661};
662
663static struct clk mmc2_ck = {
Tony Lindgrenb824efa2006-04-02 17:46:20 +0100664 .name = "mmc_ck",
Tony Lindgrend8874662008-12-10 17:37:16 -0800665 .id = 1,
Russell King548d8492008-11-04 14:02:46 +0000666 .ops = &clkops_generic,
Tony Lindgren3179a012005-11-10 14:26:48 +0000667 /* Functional clock is direct from ULPD, interface clock is ARMPER */
668 .parent = &armper_ck.clk,
669 .rate = 48000000,
670 .flags = CLOCK_IN_OMAP16XX |
671 RATE_FIXED | ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
672 .enable_reg = (void __iomem *)MOD_CONF_CTRL_0,
673 .enable_bit = 20,
Tony Lindgren3179a012005-11-10 14:26:48 +0000674};
675
676static struct clk virtual_ck_mpu = {
677 .name = "mpu",
Russell King897dcde2008-11-04 16:35:03 +0000678 .ops = &clkops_null,
Tony Lindgren3179a012005-11-10 14:26:48 +0000679 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
Russell King897dcde2008-11-04 16:35:03 +0000680 CLOCK_IN_OMAP310,
Tony Lindgren3179a012005-11-10 14:26:48 +0000681 .parent = &arm_ck, /* Is smarter alias for */
682 .recalc = &followparent_recalc,
683 .set_rate = &omap1_select_table_rate,
684 .round_rate = &omap1_round_to_table_rate,
Tony Lindgren3179a012005-11-10 14:26:48 +0000685};
686
Tony Lindgrenb824efa2006-04-02 17:46:20 +0100687/* virtual functional clock domain for I2C. Just for making sure that ARMXOR_CK
688remains active during MPU idle whenever this is enabled */
689static struct clk i2c_fck = {
690 .name = "i2c_fck",
691 .id = 1,
Russell King897dcde2008-11-04 16:35:03 +0000692 .ops = &clkops_null,
Marek Vasut6017e292006-12-06 17:13:55 -0800693 .flags = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
Russell King897dcde2008-11-04 16:35:03 +0000694 CLOCK_NO_IDLE_PARENT,
Tony Lindgrenb824efa2006-04-02 17:46:20 +0100695 .parent = &armxor_ck.clk,
696 .recalc = &followparent_recalc,
Tony Lindgrenb824efa2006-04-02 17:46:20 +0100697};
698
Tony Lindgren90afd5c2006-09-25 13:27:20 +0300699static struct clk i2c_ick = {
700 .name = "i2c_ick",
701 .id = 1,
Russell King897dcde2008-11-04 16:35:03 +0000702 .ops = &clkops_null,
703 .flags = CLOCK_IN_OMAP16XX | CLOCK_NO_IDLE_PARENT,
Tony Lindgren90afd5c2006-09-25 13:27:20 +0300704 .parent = &armper_ck.clk,
705 .recalc = &followparent_recalc,
Tony Lindgren90afd5c2006-09-25 13:27:20 +0300706};
707
Tony Lindgren3179a012005-11-10 14:26:48 +0000708static struct clk * onchip_clks[] = {
709 /* non-ULPD clocks */
710 &ck_ref,
711 &ck_dpll1,
712 /* CK_GEN1 clocks */
713 &ck_dpll1out.clk,
Imre Deakdf2c2e72007-03-05 17:22:58 +0200714 &sossi_ck,
Tony Lindgren3179a012005-11-10 14:26:48 +0000715 &arm_ck,
716 &armper_ck.clk,
717 &arm_gpio_ck,
718 &armxor_ck.clk,
719 &armtim_ck.clk,
720 &armwdt_ck.clk,
721 &arminth_ck1510, &arminth_ck16xx,
722 /* CK_GEN2 clocks */
723 &dsp_ck,
724 &dspmmu_ck,
725 &dspper_ck,
726 &dspxor_ck,
727 &dsptim_ck,
728 /* CK_GEN3 clocks */
729 &tc_ck.clk,
730 &tipb_ck,
731 &l3_ocpi_ck,
732 &tc1_ck,
733 &tc2_ck,
734 &dma_ck,
735 &dma_lcdfree_ck,
736 &api_ck.clk,
737 &lb_ck.clk,
738 &rhea1_ck,
739 &rhea2_ck,
740 &lcd_ck_16xx,
741 &lcd_ck_1510.clk,
742 /* ULPD clocks */
743 &uart1_1510,
744 &uart1_16xx.clk,
745 &uart2_ck,
746 &uart3_1510,
747 &uart3_16xx.clk,
748 &usb_clko,
749 &usb_hhc_ck1510, &usb_hhc_ck16xx,
750 &usb_dc_ck,
751 &mclk_1510, &mclk_16xx,
752 &bclk_1510, &bclk_16xx,
753 &mmc1_ck,
754 &mmc2_ck,
755 /* Virtual clocks */
756 &virtual_ck_mpu,
Tony Lindgrenb824efa2006-04-02 17:46:20 +0100757 &i2c_fck,
Tony Lindgren90afd5c2006-09-25 13:27:20 +0300758 &i2c_ick,
Tony Lindgren3179a012005-11-10 14:26:48 +0000759};
760
761#endif