blob: 31754c4bdc359553e094533fb92a1cbd6c3e2fc5 [file] [log] [blame]
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001/* Copyright (c) 2009-2011, Code Aurora Forum. All rights reserved.
Daniel Walker8d747cd2010-02-25 11:37:43 -08002 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 *
Daniel Walker8d747cd2010-02-25 11:37:43 -080012 */
13
14#include <linux/kernel.h>
15#include <linux/irq.h>
16#include <linux/gpio.h>
17#include <linux/platform_device.h>
18#include <linux/delay.h>
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070019#include <linux/bootmem.h>
Daniel Walker8d747cd2010-02-25 11:37:43 -080020#include <linux/io.h>
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070021#ifdef CONFIG_SPI_QSD
22#include <linux/spi/spi.h>
23#endif
Anirudh Ghayal9d9cdc22011-10-10 17:17:07 +053024#include <linux/msm_ssbi.h>
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070025#include <linux/mfd/pmic8058.h>
26#include <linux/mfd/marimba.h>
27#include <linux/i2c.h>
28#include <linux/input.h>
Daniel Walker8d747cd2010-02-25 11:37:43 -080029#include <linux/smsc911x.h>
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070030#include <linux/ofn_atlab.h>
31#include <linux/power_supply.h>
32#include <linux/input/pmic8058-keypad.h>
33#include <linux/i2c/isa1200.h>
34#include <linux/pwm.h>
35#include <linux/pmic8058-pwm.h>
36#include <linux/i2c/tsc2007.h>
37#include <linux/input/kp_flip_switch.h>
38#include <linux/leds-pmic8058.h>
39#include <linux/input/cy8c_ts.h>
40#include <linux/msm_adc.h>
41#include <linux/dma-mapping.h>
Daniel Walker8d747cd2010-02-25 11:37:43 -080042
43#include <asm/mach-types.h>
44#include <asm/mach/arch.h>
45#include <asm/setup.h>
46
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070047#include <mach/mpp.h>
Daniel Walker8d747cd2010-02-25 11:37:43 -080048#include <mach/board.h>
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070049#include <mach/camera.h>
50#include <mach/memory.h>
Daniel Walker8d747cd2010-02-25 11:37:43 -080051#include <mach/msm_iomap.h>
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070052#include <mach/msm_hsusb.h>
53#include <mach/rpc_hsusb.h>
54#include <mach/msm_spi.h>
55#include <mach/qdsp5v2/msm_lpa.h>
Daniel Walker8d747cd2010-02-25 11:37:43 -080056#include <mach/dma.h>
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070057#include <linux/android_pmem.h>
58#include <linux/input/msm_ts.h>
59#include <mach/pmic.h>
60#include <mach/rpc_pmapp.h>
61#include <mach/qdsp5v2/aux_pcm.h>
62#include <mach/qdsp5v2/mi2s.h>
63#include <mach/qdsp5v2/audio_dev_ctl.h>
64#include <mach/msm_battery.h>
65#include <mach/rpc_server_handset.h>
66#include <mach/msm_tsif.h>
67#include <mach/socinfo.h>
68#include <mach/msm_memtypes.h>
69#include <linux/cyttsp.h>
Daniel Walker8d747cd2010-02-25 11:37:43 -080070
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070071#include <asm/mach/mmc.h>
72#include <asm/mach/flash.h>
Daniel Walker8d747cd2010-02-25 11:37:43 -080073#include <mach/vreg.h>
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070074#include <linux/platform_data/qcom_crypto_device.h>
75
Daniel Walker8d747cd2010-02-25 11:37:43 -080076#include "devices.h"
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070077#include "timer.h"
78#ifdef CONFIG_USB_G_ANDROID
79#include <linux/usb/android.h>
80#include <mach/usbdiag.h>
81#endif
82#include "pm.h"
Maheshkumar Sivasubramanian8ccc16e2011-10-25 15:59:57 -060083#include "pm-boot.h"
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070084#include "spm.h"
Matt Wagantall6d9ebee2011-08-26 12:15:24 -070085#include "acpuclock.h"
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070086#include <mach/dal_axi.h>
87#include <mach/msm_serial_hs.h>
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070088#include <mach/qdsp5v2/mi2s.h>
89#include <mach/qdsp5v2/audio_dev_ctl.h>
90#include <mach/sdio_al.h>
91#include "smd_private.h"
92#include <linux/bma150.h>
Daniel Walker8d747cd2010-02-25 11:37:43 -080093
Justin Paupore637a25d2011-07-14 17:11:04 -070094#include "board-msm7x30-regulator.h"
95
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070096#define MSM_PMEM_SF_SIZE 0x1700000
97#ifdef CONFIG_FB_MSM_TRIPLE_BUFFER
98#define MSM_FB_SIZE 0x780000
99#else
100#define MSM_FB_SIZE 0x500000
101#endif
102#define MSM_PMEM_ADSP_SIZE 0x1E00000
103#define MSM_FLUID_PMEM_ADSP_SIZE 0x2800000
104#define PMEM_KERNEL_EBI0_SIZE 0x600000
105#define MSM_PMEM_AUDIO_SIZE 0x200000
Daniel Walker90e37c52010-05-12 14:24:15 -0700106
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700107#define PMIC_GPIO_INT 27
108#define PMIC_VREG_WLAN_LEVEL 2900
109#define PMIC_GPIO_SD_DET 36
110#define PMIC_GPIO_SDC4_EN_N 17 /* PMIC GPIO Number 18 */
111#define PMIC_GPIO_HDMI_5V_EN_V3 32 /* PMIC GPIO for V3 H/W */
112#define PMIC_GPIO_HDMI_5V_EN_V2 39 /* PMIC GPIO for V2 H/W */
113
114#define ADV7520_I2C_ADDR 0x39
115
116#define FPGA_SDCC_STATUS 0x8E0001A8
117
118#define FPGA_OPTNAV_GPIO_ADDR 0x8E000026
119#define OPTNAV_I2C_SLAVE_ADDR (0xB0 >> 1)
120#define OPTNAV_IRQ 20
121#define OPTNAV_CHIP_SELECT 19
122
123/* Macros assume PMIC GPIOs start at 0 */
124#define PM8058_GPIO_PM_TO_SYS(pm_gpio) (pm_gpio + NR_GPIO_IRQS)
125#define PM8058_GPIO_SYS_TO_PM(sys_gpio) (sys_gpio - NR_GPIO_IRQS)
126
127#define PMIC_GPIO_FLASH_BOOST_ENABLE 15 /* PMIC GPIO Number 16 */
128#define PMIC_GPIO_HAP_ENABLE 16 /* PMIC GPIO Number 17 */
129
130#define PMIC_GPIO_WLAN_EXT_POR 22 /* PMIC GPIO NUMBER 23 */
131
132#define BMA150_GPIO_INT 1
133
134#define HAP_LVL_SHFT_MSM_GPIO 24
135
136#define PMIC_GPIO_QUICKVX_CLK 37 /* PMIC GPIO 38 */
137
138#define PM_FLIP_MPP 5 /* PMIC MPP 06 */
139static int pm8058_gpios_init(void)
140{
141 int rc;
142 int pmic_gpio_hdmi_5v_en;
143
144#ifdef CONFIG_MMC_MSM_CARD_HW_DETECTION
145 struct pm8058_gpio sdcc_det = {
146 .direction = PM_GPIO_DIR_IN,
147 .pull = PM_GPIO_PULL_UP_1P5,
148 .vin_sel = 2,
149 .function = PM_GPIO_FUNC_NORMAL,
150 .inv_int_pol = 0,
151 };
152#endif
153 struct pm8058_gpio sdc4_en = {
154 .direction = PM_GPIO_DIR_OUT,
155 .pull = PM_GPIO_PULL_NO,
156 .vin_sel = PM_GPIO_VIN_L5,
157 .function = PM_GPIO_FUNC_NORMAL,
158 .inv_int_pol = 0,
159 .out_strength = PM_GPIO_STRENGTH_LOW,
160 .output_value = 0,
161 };
162
163 struct pm8058_gpio haptics_enable = {
164 .direction = PM_GPIO_DIR_OUT,
165 .pull = PM_GPIO_PULL_NO,
166 .out_strength = PM_GPIO_STRENGTH_HIGH,
167 .function = PM_GPIO_FUNC_NORMAL,
168 .inv_int_pol = 0,
169 .vin_sel = 2,
170 .output_buffer = PM_GPIO_OUT_BUF_CMOS,
171 .output_value = 0,
172 };
173
174 struct pm8058_gpio hdmi_5V_en = {
175 .direction = PM_GPIO_DIR_OUT,
176 .pull = PM_GPIO_PULL_NO,
177 .vin_sel = PM_GPIO_VIN_VPH,
178 .function = PM_GPIO_FUNC_NORMAL,
179 .out_strength = PM_GPIO_STRENGTH_LOW,
180 .output_value = 0,
181 };
182
183 struct pm8058_gpio flash_boost_enable = {
184 .direction = PM_GPIO_DIR_OUT,
185 .output_buffer = PM_GPIO_OUT_BUF_CMOS,
186 .output_value = 0,
187 .pull = PM_GPIO_PULL_NO,
188 .vin_sel = PM_GPIO_VIN_S3,
189 .out_strength = PM_GPIO_STRENGTH_HIGH,
190 .function = PM_GPIO_FUNC_2,
191 };
192
193 struct pm8058_gpio gpio23 = {
194 .direction = PM_GPIO_DIR_OUT,
195 .output_buffer = PM_GPIO_OUT_BUF_CMOS,
196 .output_value = 0,
197 .pull = PM_GPIO_PULL_NO,
198 .vin_sel = 2,
199 .out_strength = PM_GPIO_STRENGTH_LOW,
200 .function = PM_GPIO_FUNC_NORMAL,
201 };
202
203
204 if (machine_is_msm8x55_svlte_surf() || machine_is_msm8x55_svlte_ffa() ||
205 machine_is_msm7x30_fluid())
206 pmic_gpio_hdmi_5v_en = PMIC_GPIO_HDMI_5V_EN_V2 ;
207 else
208 pmic_gpio_hdmi_5v_en = PMIC_GPIO_HDMI_5V_EN_V3 ;
209
210 if (machine_is_msm7x30_fluid()) {
211 rc = pm8058_gpio_config(PMIC_GPIO_HAP_ENABLE, &haptics_enable);
212 if (rc) {
213 pr_err("%s: PMIC GPIO %d write failed\n", __func__,
214 (PMIC_GPIO_HAP_ENABLE + 1));
215 return rc;
216 }
217 rc = pm8058_gpio_config(PMIC_GPIO_FLASH_BOOST_ENABLE,
218 &flash_boost_enable);
219 if (rc) {
220 pr_err("%s: PMIC GPIO %d write failed\n", __func__,
221 (PMIC_GPIO_FLASH_BOOST_ENABLE + 1));
222 return rc;
223 }
224 }
225
226#ifdef CONFIG_MMC_MSM_CARD_HW_DETECTION
227 if (machine_is_msm7x30_fluid())
228 sdcc_det.inv_int_pol = 1;
229
230 rc = pm8058_gpio_config(PMIC_GPIO_SD_DET - 1, &sdcc_det);
231 if (rc) {
232 pr_err("%s PMIC_GPIO_SD_DET config failed\n", __func__);
233 return rc;
234 }
235#endif
236
237 rc = pm8058_gpio_config(pmic_gpio_hdmi_5v_en, &hdmi_5V_en);
238 if (rc) {
239 pr_err("%s PMIC_GPIO_HDMI_5V_EN config failed\n", __func__);
240 return rc;
241 }
242
243 /* Deassert GPIO#23 (source for Ext_POR on WLAN-Volans) */
244 rc = pm8058_gpio_config(PMIC_GPIO_WLAN_EXT_POR, &gpio23);
245 if (rc) {
246 pr_err("%s PMIC_GPIO_WLAN_EXT_POR config failed\n", __func__);
247 return rc;
248 }
249
250 if (machine_is_msm7x30_fluid()) {
251 rc = pm8058_gpio_config(PMIC_GPIO_SDC4_EN_N, &sdc4_en);
252 if (rc) {
253 pr_err("%s PMIC_GPIO_SDC4_EN_N config failed\n",
254 __func__);
255 return rc;
256 }
257 rc = gpio_request(PM8058_GPIO_PM_TO_SYS(PMIC_GPIO_SDC4_EN_N),
258 "sdc4_en");
259 if (rc) {
260 pr_err("%s PMIC_GPIO_SDC4_EN_N gpio_request failed\n",
261 __func__);
262 return rc;
263 }
264 gpio_set_value_cansleep(
265 PM8058_GPIO_PM_TO_SYS(PMIC_GPIO_SDC4_EN_N), 0);
266 }
267
268 return 0;
269}
270
Justin Paupore637a25d2011-07-14 17:11:04 -0700271/* Regulator API support */
272
273#ifdef CONFIG_MSM_PROC_COMM_REGULATOR
274static struct platform_device msm_proccomm_regulator_dev = {
275 .name = PROCCOMM_REGULATOR_DEV_NAME,
276 .id = -1,
277 .dev = {
278 .platform_data = &msm7x30_proccomm_regulator_data
279 }
280};
281#endif
282
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700283/*virtual key support */
284static ssize_t tma300_vkeys_show(struct kobject *kobj,
285 struct kobj_attribute *attr, char *buf)
286{
287 return sprintf(buf,
288 __stringify(EV_KEY) ":" __stringify(KEY_BACK) ":50:842:80:100"
289 ":" __stringify(EV_KEY) ":" __stringify(KEY_MENU) ":170:842:80:100"
290 ":" __stringify(EV_KEY) ":" __stringify(KEY_HOME) ":290:842:80:100"
291 ":" __stringify(EV_KEY) ":" __stringify(KEY_SEARCH) ":410:842:80:100"
292 "\n");
293}
294
295static struct kobj_attribute tma300_vkeys_attr = {
296 .attr = {
297 .mode = S_IRUGO,
298 },
299 .show = &tma300_vkeys_show,
Pavankumar Kondeti5155e2c2010-12-08 13:37:08 +0530300};
301
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700302static struct attribute *tma300_properties_attrs[] = {
303 &tma300_vkeys_attr.attr,
304 NULL
Pavankumar Kondeti5155e2c2010-12-08 13:37:08 +0530305};
306
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700307static struct attribute_group tma300_properties_attr_group = {
308 .attrs = tma300_properties_attrs,
309};
310
311static struct kobject *properties_kobj;
312
313#define CYTTSP_TS_GPIO_IRQ 150
314static int cyttsp_platform_init(struct i2c_client *client)
315{
316 int rc = -EINVAL;
317 struct vreg *vreg_ldo8, *vreg_ldo15;
318
319 vreg_ldo8 = vreg_get(NULL, "gp7");
320
321 if (!vreg_ldo8) {
322 pr_err("%s: VREG L8 get failed\n", __func__);
323 return rc;
324 }
325
326 rc = vreg_set_level(vreg_ldo8, 1800);
327 if (rc) {
328 pr_err("%s: VREG L8 set failed\n", __func__);
329 goto l8_put;
330 }
331
332 rc = vreg_enable(vreg_ldo8);
333 if (rc) {
334 pr_err("%s: VREG L8 enable failed\n", __func__);
335 goto l8_put;
336 }
337
338 vreg_ldo15 = vreg_get(NULL, "gp6");
339
340 if (!vreg_ldo15) {
341 pr_err("%s: VREG L15 get failed\n", __func__);
342 goto l8_disable;
343 }
344
345 rc = vreg_set_level(vreg_ldo15, 3050);
346 if (rc) {
347 pr_err("%s: VREG L15 set failed\n", __func__);
348 goto l8_disable;
349 }
350
351 rc = vreg_enable(vreg_ldo15);
352 if (rc) {
353 pr_err("%s: VREG L15 enable failed\n", __func__);
354 goto l8_disable;
355 }
356
357 /* check this device active by reading first byte/register */
358 rc = i2c_smbus_read_byte_data(client, 0x01);
359 if (rc < 0) {
360 pr_err("%s: i2c sanity check failed\n", __func__);
361 goto l8_disable;
362 }
363
364 rc = gpio_tlmm_config(GPIO_CFG(CYTTSP_TS_GPIO_IRQ, 0, GPIO_CFG_INPUT,
365 GPIO_CFG_PULL_UP, GPIO_CFG_6MA), GPIO_CFG_ENABLE);
366 if (rc) {
367 pr_err("%s: Could not configure gpio %d\n",
368 __func__, CYTTSP_TS_GPIO_IRQ);
369 goto l8_disable;
370 }
371
372 /* virtual keys */
373 tma300_vkeys_attr.attr.name = "virtualkeys.cyttsp-i2c";
374 properties_kobj = kobject_create_and_add("board_properties",
375 NULL);
376 if (properties_kobj)
377 rc = sysfs_create_group(properties_kobj,
378 &tma300_properties_attr_group);
379 if (!properties_kobj || rc)
380 pr_err("%s: failed to create board_properties\n",
381 __func__);
382
383 return CY_OK;
384
385l8_disable:
386 vreg_disable(vreg_ldo8);
387l8_put:
388 vreg_put(vreg_ldo8);
389 return rc;
390}
391
392static int cyttsp_platform_resume(struct i2c_client *client)
393{
394 /* add any special code to strobe a wakeup pin or chip reset */
395 mdelay(10);
396
397 return CY_OK;
398}
399
400static struct cyttsp_platform_data cyttsp_data = {
401 .fw_fname = "cyttsp_7630_fluid.hex",
402 .panel_maxx = 479,
403 .panel_maxy = 799,
404 .disp_maxx = 469,
405 .disp_maxy = 799,
406 .disp_minx = 10,
407 .disp_miny = 0,
408 .flags = 0,
409 .gen = CY_GEN3, /* or */
410 .use_st = CY_USE_ST,
411 .use_mt = CY_USE_MT,
412 .use_hndshk = CY_SEND_HNDSHK,
413 .use_trk_id = CY_USE_TRACKING_ID,
Anirudh Ghayal15187772011-06-22 17:39:41 +0530414 .use_sleep = CY_USE_DEEP_SLEEP_SEL | CY_USE_LOW_POWER_SEL,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700415 .use_gestures = CY_USE_GESTURES,
416 /* activate up to 4 groups
417 * and set active distance
418 */
419 .gest_set = CY_GEST_GRP1 | CY_GEST_GRP2 |
420 CY_GEST_GRP3 | CY_GEST_GRP4 |
421 CY_ACT_DIST,
422 /* change act_intrvl to customize the Active power state
423 * scanning/processing refresh interval for Operating mode
424 */
425 .act_intrvl = CY_ACT_INTRVL_DFLT,
426 /* change tch_tmout to customize the touch timeout for the
427 * Active power state for Operating mode
428 */
429 .tch_tmout = CY_TCH_TMOUT_DFLT,
430 /* change lp_intrvl to customize the Low Power power state
431 * scanning/processing refresh interval for Operating mode
432 */
433 .lp_intrvl = CY_LP_INTRVL_DFLT,
434 .resume = cyttsp_platform_resume,
435 .init = cyttsp_platform_init,
436 .sleep_gpio = -1,
437 .resout_gpio = -1,
438 .irq_gpio = CYTTSP_TS_GPIO_IRQ,
Mohan Pallaka49c37d62011-08-01 11:52:00 +0530439 .correct_fw_ver = 2,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700440};
441
442static int pm8058_pwm_config(struct pwm_device *pwm, int ch, int on)
443{
444 struct pm8058_gpio pwm_gpio_config = {
445 .direction = PM_GPIO_DIR_OUT,
446 .output_buffer = PM_GPIO_OUT_BUF_CMOS,
447 .output_value = 0,
448 .pull = PM_GPIO_PULL_NO,
449 .vin_sel = PM_GPIO_VIN_S3,
450 .out_strength = PM_GPIO_STRENGTH_HIGH,
451 .function = PM_GPIO_FUNC_2,
452 };
453 int rc = -EINVAL;
454 int id, mode, max_mA;
455
456 id = mode = max_mA = 0;
457 switch (ch) {
458 case 0:
459 case 1:
460 case 2:
461 if (on) {
462 id = 24 + ch;
463 rc = pm8058_gpio_config(id - 1, &pwm_gpio_config);
464 if (rc)
465 pr_err("%s: pm8058_gpio_config(%d): rc=%d\n",
466 __func__, id, rc);
467 }
468 break;
469
470 case 3:
471 id = PM_PWM_LED_KPD;
472 mode = PM_PWM_CONF_DTEST3;
473 max_mA = 200;
474 break;
475
476 case 4:
477 id = PM_PWM_LED_0;
478 mode = PM_PWM_CONF_PWM1;
479 max_mA = 40;
480 break;
481
482 case 5:
483 id = PM_PWM_LED_2;
484 mode = PM_PWM_CONF_PWM2;
485 max_mA = 40;
486 break;
487
488 case 6:
489 id = PM_PWM_LED_FLASH;
490 mode = PM_PWM_CONF_DTEST3;
491 max_mA = 200;
492 break;
493
494 default:
495 break;
496 }
497
498 if (ch >= 3 && ch <= 6) {
499 if (!on) {
500 mode = PM_PWM_CONF_NONE;
501 max_mA = 0;
502 }
503 rc = pm8058_pwm_config_led(pwm, id, mode, max_mA);
504 if (rc)
505 pr_err("%s: pm8058_pwm_config_led(ch=%d): rc=%d\n",
506 __func__, ch, rc);
507 }
508
509 return rc;
510}
511
512static int pm8058_pwm_enable(struct pwm_device *pwm, int ch, int on)
513{
514 int rc;
515
516 switch (ch) {
517 case 7:
518 rc = pm8058_pwm_set_dtest(pwm, on);
519 if (rc)
520 pr_err("%s: pwm_set_dtest(%d): rc=%d\n",
521 __func__, on, rc);
522 break;
523 default:
524 rc = -EINVAL;
525 break;
526 }
527 return rc;
528}
529
530static const unsigned int fluid_keymap[] = {
531 KEY(0, 0, KEY_7),
532 KEY(0, 1, KEY_ENTER),
533 KEY(0, 2, KEY_UP),
534 /* drop (0,3) as it always shows up in pair with(0,2) */
535 KEY(0, 4, KEY_DOWN),
536
537 KEY(1, 0, KEY_CAMERA_SNAPSHOT),
538 KEY(1, 1, KEY_SELECT),
539 KEY(1, 2, KEY_1),
540 KEY(1, 3, KEY_VOLUMEUP),
541 KEY(1, 4, KEY_VOLUMEDOWN),
542};
543
544static const unsigned int surf_keymap[] = {
545 KEY(0, 0, KEY_7),
546 KEY(0, 1, KEY_DOWN),
547 KEY(0, 2, KEY_UP),
548 KEY(0, 3, KEY_RIGHT),
549 KEY(0, 4, KEY_ENTER),
550 KEY(0, 5, KEY_L),
551 KEY(0, 6, KEY_BACK),
552 KEY(0, 7, KEY_M),
553
554 KEY(1, 0, KEY_LEFT),
555 KEY(1, 1, KEY_SEND),
556 KEY(1, 2, KEY_1),
557 KEY(1, 3, KEY_4),
558 KEY(1, 4, KEY_CLEAR),
559 KEY(1, 5, KEY_MSDOS),
560 KEY(1, 6, KEY_SPACE),
561 KEY(1, 7, KEY_COMMA),
562
563 KEY(2, 0, KEY_6),
564 KEY(2, 1, KEY_5),
565 KEY(2, 2, KEY_8),
566 KEY(2, 3, KEY_3),
567 KEY(2, 4, KEY_NUMERIC_STAR),
568 KEY(2, 5, KEY_UP),
569 KEY(2, 6, KEY_DOWN), /* SYN */
570 KEY(2, 7, KEY_LEFTSHIFT),
571
572 KEY(3, 0, KEY_9),
573 KEY(3, 1, KEY_NUMERIC_POUND),
574 KEY(3, 2, KEY_0),
575 KEY(3, 3, KEY_2),
576 KEY(3, 4, KEY_SLEEP),
577 KEY(3, 5, KEY_F1),
578 KEY(3, 6, KEY_F2),
579 KEY(3, 7, KEY_F3),
580
581 KEY(4, 0, KEY_BACK),
582 KEY(4, 1, KEY_HOME),
583 KEY(4, 2, KEY_MENU),
584 KEY(4, 3, KEY_VOLUMEUP),
585 KEY(4, 4, KEY_VOLUMEDOWN),
586 KEY(4, 5, KEY_F4),
587 KEY(4, 6, KEY_F5),
588 KEY(4, 7, KEY_F6),
589
590 KEY(5, 0, KEY_R),
591 KEY(5, 1, KEY_T),
592 KEY(5, 2, KEY_Y),
593 KEY(5, 3, KEY_LEFTALT),
594 KEY(5, 4, KEY_KPENTER),
595 KEY(5, 5, KEY_Q),
596 KEY(5, 6, KEY_W),
597 KEY(5, 7, KEY_E),
598
599 KEY(6, 0, KEY_F),
600 KEY(6, 1, KEY_G),
601 KEY(6, 2, KEY_H),
602 KEY(6, 3, KEY_CAPSLOCK),
603 KEY(6, 4, KEY_PAGEUP),
604 KEY(6, 5, KEY_A),
605 KEY(6, 6, KEY_S),
606 KEY(6, 7, KEY_D),
607
608 KEY(7, 0, KEY_V),
609 KEY(7, 1, KEY_B),
610 KEY(7, 2, KEY_N),
611 KEY(7, 3, KEY_MENU), /* REVISIT - SYM */
612 KEY(7, 4, KEY_PAGEDOWN),
613 KEY(7, 5, KEY_Z),
614 KEY(7, 6, KEY_X),
615 KEY(7, 7, KEY_C),
616
617 KEY(8, 0, KEY_P),
618 KEY(8, 1, KEY_J),
619 KEY(8, 2, KEY_K),
620 KEY(8, 3, KEY_INSERT),
621 KEY(8, 4, KEY_LINEFEED),
622 KEY(8, 5, KEY_U),
623 KEY(8, 6, KEY_I),
624 KEY(8, 7, KEY_O),
625
626 KEY(9, 0, KEY_4),
627 KEY(9, 1, KEY_5),
628 KEY(9, 2, KEY_6),
629 KEY(9, 3, KEY_7),
630 KEY(9, 4, KEY_8),
631 KEY(9, 5, KEY_1),
632 KEY(9, 6, KEY_2),
633 KEY(9, 7, KEY_3),
634
635 KEY(10, 0, KEY_F7),
636 KEY(10, 1, KEY_F8),
637 KEY(10, 2, KEY_F9),
638 KEY(10, 3, KEY_F10),
639 KEY(10, 4, KEY_FN),
640 KEY(10, 5, KEY_9),
641 KEY(10, 6, KEY_0),
642 KEY(10, 7, KEY_DOT),
643
644 KEY(11, 0, KEY_LEFTCTRL),
645 KEY(11, 1, KEY_F11), /* START */
646 KEY(11, 2, KEY_ENTER),
647 KEY(11, 3, KEY_SEARCH),
648 KEY(11, 4, KEY_DELETE),
649 KEY(11, 5, KEY_RIGHT),
650 KEY(11, 6, KEY_LEFT),
651 KEY(11, 7, KEY_RIGHTSHIFT),
652};
653
654static struct resource resources_keypad[] = {
655 {
656 .start = PM8058_KEYPAD_IRQ(PMIC8058_IRQ_BASE),
657 .end = PM8058_KEYPAD_IRQ(PMIC8058_IRQ_BASE),
658 .flags = IORESOURCE_IRQ,
Dima Zavinba5499e2011-01-10 11:00:30 -0800659 },
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700660 {
661 .start = PM8058_KEYSTUCK_IRQ(PMIC8058_IRQ_BASE),
662 .end = PM8058_KEYSTUCK_IRQ(PMIC8058_IRQ_BASE),
663 .flags = IORESOURCE_IRQ,
Dima Zavinba5499e2011-01-10 11:00:30 -0800664 },
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700665};
666
667static struct matrix_keymap_data surf_keymap_data = {
668 .keymap_size = ARRAY_SIZE(surf_keymap),
669 .keymap = surf_keymap,
670};
671
672
673static struct pmic8058_keypad_data surf_keypad_data = {
674 .input_name = "surf_keypad",
675 .input_phys_device = "surf_keypad/input0",
676 .num_rows = 12,
677 .num_cols = 8,
678 .rows_gpio_start = 8,
679 .cols_gpio_start = 0,
680 .debounce_ms = {8, 10},
681 .scan_delay_ms = 32,
682 .row_hold_ns = 91500,
683 .wakeup = 1,
684 .keymap_data = &surf_keymap_data,
685};
686
687static struct matrix_keymap_data fluid_keymap_data = {
688 .keymap_size = ARRAY_SIZE(fluid_keymap),
689 .keymap = fluid_keymap,
690};
691
692
693
694static struct pmic8058_keypad_data fluid_keypad_data = {
695 .input_name = "fluid-keypad",
696 .input_phys_device = "fluid-keypad/input0",
697 .num_rows = 5,
698 .num_cols = 5,
699 .rows_gpio_start = 8,
700 .cols_gpio_start = 0,
701 .debounce_ms = {8, 10},
702 .scan_delay_ms = 32,
703 .row_hold_ns = 91500,
704 .wakeup = 1,
705 .keymap_data = &fluid_keymap_data,
706};
707
708static struct pm8058_pwm_pdata pm8058_pwm_data = {
709 .config = pm8058_pwm_config,
710 .enable = pm8058_pwm_enable,
711};
712
713/* Put sub devices with fixed location first in sub_devices array */
714#define PM8058_SUBDEV_KPD 0
715#define PM8058_SUBDEV_LED 1
716
717static struct pm8058_gpio_platform_data pm8058_gpio_data = {
718 .gpio_base = PM8058_GPIO_PM_TO_SYS(0),
719 .irq_base = PM8058_GPIO_IRQ(PMIC8058_IRQ_BASE, 0),
720 .init = pm8058_gpios_init,
721};
722
723static struct pm8058_gpio_platform_data pm8058_mpp_data = {
724 .gpio_base = PM8058_GPIO_PM_TO_SYS(PM8058_GPIOS),
725 .irq_base = PM8058_MPP_IRQ(PMIC8058_IRQ_BASE, 0),
726};
727
728static struct pmic8058_led pmic8058_ffa_leds[] = {
729 [0] = {
730 .name = "keyboard-backlight",
731 .max_brightness = 15,
732 .id = PMIC8058_ID_LED_KB_LIGHT,
Dima Zavinba5499e2011-01-10 11:00:30 -0800733 },
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700734};
735
736static struct pmic8058_leds_platform_data pm8058_ffa_leds_data = {
737 .num_leds = ARRAY_SIZE(pmic8058_ffa_leds),
738 .leds = pmic8058_ffa_leds,
739};
740
741static struct pmic8058_led pmic8058_surf_leds[] = {
742 [0] = {
743 .name = "keyboard-backlight",
744 .max_brightness = 15,
745 .id = PMIC8058_ID_LED_KB_LIGHT,
746 },
747 [1] = {
748 .name = "voice:red",
749 .max_brightness = 20,
750 .id = PMIC8058_ID_LED_0,
751 },
752 [2] = {
753 .name = "wlan:green",
754 .max_brightness = 20,
755 .id = PMIC8058_ID_LED_2,
756 },
757};
758
759static struct mfd_cell pm8058_subdevs[] = {
760 { .name = "pm8058-keypad",
761 .id = -1,
762 .num_resources = ARRAY_SIZE(resources_keypad),
763 .resources = resources_keypad,
764 },
765 { .name = "pm8058-led",
766 .id = -1,
767 },
768 { .name = "pm8058-gpio",
769 .id = -1,
770 .platform_data = &pm8058_gpio_data,
771 .pdata_size = sizeof(pm8058_gpio_data),
772 },
773 { .name = "pm8058-mpp",
774 .id = -1,
775 .platform_data = &pm8058_mpp_data,
776 .pdata_size = sizeof(pm8058_mpp_data),
777 },
778 { .name = "pm8058-pwm",
779 .id = -1,
780 .platform_data = &pm8058_pwm_data,
781 .pdata_size = sizeof(pm8058_pwm_data),
782 },
783 { .name = "pm8058-nfc",
784 .id = -1,
785 },
786 { .name = "pm8058-upl",
787 .id = -1,
788 },
789};
790
791static struct pmic8058_leds_platform_data pm8058_surf_leds_data = {
792 .num_leds = ARRAY_SIZE(pmic8058_surf_leds),
793 .leds = pmic8058_surf_leds,
794};
795
796static struct pmic8058_led pmic8058_fluid_leds[] = {
797 [0] = {
798 .name = "keyboard-backlight",
799 .max_brightness = 15,
800 .id = PMIC8058_ID_LED_KB_LIGHT,
801 },
802 [1] = {
803 .name = "flash:led_0",
804 .max_brightness = 15,
805 .id = PMIC8058_ID_FLASH_LED_0,
806 },
807 [2] = {
808 .name = "flash:led_1",
809 .max_brightness = 15,
810 .id = PMIC8058_ID_FLASH_LED_1,
811 },
812};
813
814static struct pmic8058_leds_platform_data pm8058_fluid_leds_data = {
815 .num_leds = ARRAY_SIZE(pmic8058_fluid_leds),
816 .leds = pmic8058_fluid_leds,
817};
818
819static struct pm8058_platform_data pm8058_7x30_data = {
820 .irq_base = PMIC8058_IRQ_BASE,
Anirudh Ghayal9d9cdc22011-10-10 17:17:07 +0530821 .irq = MSM_GPIO_TO_INT(PMIC_GPIO_INT),
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700822
823 .num_subdevs = ARRAY_SIZE(pm8058_subdevs),
824 .sub_devices = pm8058_subdevs,
825 .irq_trigger_flags = IRQF_TRIGGER_LOW,
826};
827
Anirudh Ghayal9d9cdc22011-10-10 17:17:07 +0530828#ifdef CONFIG_MSM_SSBI
829static struct msm_ssbi_platform_data msm7x30_ssbi_pm8058_pdata = {
830 .controller_type = MSM_SBI_CTRL_SSBI2,
831 .slave = {
832 .name = "pm8058-core",
833 .platform_data = &pm8058_7x30_data,
834 },
835};
836#endif
837
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700838static struct i2c_board_info cy8info[] __initdata = {
839 {
840 I2C_BOARD_INFO(CY_I2C_NAME, 0x24),
841 .platform_data = &cyttsp_data,
842#ifndef CY_USE_TIMER
843 .irq = MSM_GPIO_TO_INT(CYTTSP_TS_GPIO_IRQ),
844#endif /* CY_USE_TIMER */
845 },
846};
847
848static struct i2c_board_info msm_camera_boardinfo[] __initdata = {
849#ifdef CONFIG_MT9D112
850 {
851 I2C_BOARD_INFO("mt9d112", 0x78 >> 1),
Dima Zavinba5499e2011-01-10 11:00:30 -0800852 },
853#endif
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700854#ifdef CONFIG_WEBCAM_OV9726
855 {
856 I2C_BOARD_INFO("ov9726", 0x10),
857 },
858#endif
859#ifdef CONFIG_S5K3E2FX
860 {
861 I2C_BOARD_INFO("s5k3e2fx", 0x20 >> 1),
862 },
863#endif
864#ifdef CONFIG_MT9P012
865 {
866 I2C_BOARD_INFO("mt9p012", 0x6C >> 1),
867 },
868#endif
869#ifdef CONFIG_VX6953
870 {
871 I2C_BOARD_INFO("vx6953", 0x20),
872 },
873#endif
874#ifdef CONFIG_MT9E013
875 {
876 I2C_BOARD_INFO("mt9e013", 0x6C >> 2),
877 },
878#endif
879#ifdef CONFIG_SN12M0PZ
880 {
881 I2C_BOARD_INFO("sn12m0pz", 0x34 >> 1),
882 },
883#endif
884#if defined(CONFIG_MT9T013) || defined(CONFIG_SENSORS_MT9T013)
885 {
886 I2C_BOARD_INFO("mt9t013", 0x6C),
887 },
888#endif
889
Dima Zavinba5499e2011-01-10 11:00:30 -0800890};
891
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700892#ifdef CONFIG_MSM_CAMERA
893#define CAM_STNDBY 143
894static uint32_t camera_off_vcm_gpio_table[] = {
895GPIO_CFG(1, 0, GPIO_CFG_OUTPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA), /* VCM */
896};
897
898static uint32_t camera_off_gpio_table[] = {
899 /* parallel CAMERA interfaces */
900 GPIO_CFG(0, 0, GPIO_CFG_OUTPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA), /* RST */
901 GPIO_CFG(2, 0, GPIO_CFG_INPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA), /* DAT2 */
902 GPIO_CFG(3, 0, GPIO_CFG_INPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA), /* DAT3 */
903 GPIO_CFG(4, 0, GPIO_CFG_INPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA), /* DAT4 */
904 GPIO_CFG(5, 0, GPIO_CFG_INPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA), /* DAT5 */
905 GPIO_CFG(6, 0, GPIO_CFG_INPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA), /* DAT6 */
906 GPIO_CFG(7, 0, GPIO_CFG_INPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA), /* DAT7 */
907 GPIO_CFG(8, 0, GPIO_CFG_INPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA), /* DAT8 */
908 GPIO_CFG(9, 0, GPIO_CFG_INPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA), /* DAT9 */
909 GPIO_CFG(10, 0, GPIO_CFG_INPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA), /* DAT10 */
910 GPIO_CFG(11, 0, GPIO_CFG_INPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA), /* DAT11 */
911 GPIO_CFG(12, 0, GPIO_CFG_INPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA), /* PCLK */
912 GPIO_CFG(13, 0, GPIO_CFG_INPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA), /* HSYNC_IN */
913 GPIO_CFG(14, 0, GPIO_CFG_INPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA), /* VSYNC_IN */
914 GPIO_CFG(15, 0, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), /* MCLK */
915};
916
917static uint32_t camera_on_vcm_gpio_table[] = {
918GPIO_CFG(1, 0, GPIO_CFG_OUTPUT, GPIO_CFG_PULL_UP, GPIO_CFG_2MA), /* VCM */
919};
920
921static uint32_t camera_on_gpio_table[] = {
922 /* parallel CAMERA interfaces */
923 GPIO_CFG(0, 0, GPIO_CFG_OUTPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA), /* RST */
924 GPIO_CFG(2, 1, GPIO_CFG_INPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA), /* DAT2 */
925 GPIO_CFG(3, 1, GPIO_CFG_INPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA), /* DAT3 */
926 GPIO_CFG(4, 1, GPIO_CFG_INPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA), /* DAT4 */
927 GPIO_CFG(5, 1, GPIO_CFG_INPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA), /* DAT5 */
928 GPIO_CFG(6, 1, GPIO_CFG_INPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA), /* DAT6 */
929 GPIO_CFG(7, 1, GPIO_CFG_INPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA), /* DAT7 */
930 GPIO_CFG(8, 1, GPIO_CFG_INPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA), /* DAT8 */
931 GPIO_CFG(9, 1, GPIO_CFG_INPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA), /* DAT9 */
932 GPIO_CFG(10, 1, GPIO_CFG_INPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA), /* DAT10 */
933 GPIO_CFG(11, 1, GPIO_CFG_INPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA), /* DAT11 */
934 GPIO_CFG(12, 1, GPIO_CFG_INPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA), /* PCLK */
935 GPIO_CFG(13, 1, GPIO_CFG_INPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA), /* HSYNC_IN */
936 GPIO_CFG(14, 1, GPIO_CFG_INPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA), /* VSYNC_IN */
937 GPIO_CFG(15, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), /* MCLK */
938};
939
940static uint32_t camera_off_gpio_fluid_table[] = {
941 /* FLUID: CAM_VGA_RST_N */
942 GPIO_CFG(31, 0, GPIO_CFG_OUTPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA),
943 /* FLUID: CAMIF_STANDBY */
944 GPIO_CFG(CAM_STNDBY, 0, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA)
945};
946
947static uint32_t camera_on_gpio_fluid_table[] = {
948 /* FLUID: CAM_VGA_RST_N */
949 GPIO_CFG(31, 0, GPIO_CFG_OUTPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA),
950 /* FLUID: CAMIF_STANDBY */
951 GPIO_CFG(CAM_STNDBY, 0, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA)
952};
953
954static void config_gpio_table(uint32_t *table, int len)
955{
956 int n, rc;
957 for (n = 0; n < len; n++) {
958 rc = gpio_tlmm_config(table[n], GPIO_CFG_ENABLE);
959 if (rc) {
960 pr_err("%s: gpio_tlmm_config(%#x)=%d\n",
961 __func__, table[n], rc);
962 break;
963 }
964 }
965}
966static int config_camera_on_gpios(void)
967{
968 config_gpio_table(camera_on_gpio_table,
969 ARRAY_SIZE(camera_on_gpio_table));
970
971 if (adie_get_detected_codec_type() != TIMPANI_ID)
972 /* GPIO1 is shared also used in Timpani RF card so
973 only configure it for non-Timpani RF card */
974 config_gpio_table(camera_on_vcm_gpio_table,
975 ARRAY_SIZE(camera_on_vcm_gpio_table));
976
977 if (machine_is_msm7x30_fluid()) {
978 config_gpio_table(camera_on_gpio_fluid_table,
979 ARRAY_SIZE(camera_on_gpio_fluid_table));
980 /* FLUID: turn on 5V booster */
981 gpio_set_value(
982 PM8058_GPIO_PM_TO_SYS(PMIC_GPIO_FLASH_BOOST_ENABLE), 1);
983 /* FLUID: drive high to put secondary sensor to STANDBY */
984 gpio_set_value(CAM_STNDBY, 1);
985 }
986 return 0;
987}
988
989static void config_camera_off_gpios(void)
990{
991 config_gpio_table(camera_off_gpio_table,
992 ARRAY_SIZE(camera_off_gpio_table));
993
994 if (adie_get_detected_codec_type() != TIMPANI_ID)
995 /* GPIO1 is shared also used in Timpani RF card so
996 only configure it for non-Timpani RF card */
997 config_gpio_table(camera_off_vcm_gpio_table,
998 ARRAY_SIZE(camera_off_vcm_gpio_table));
999
1000 if (machine_is_msm7x30_fluid()) {
1001 config_gpio_table(camera_off_gpio_fluid_table,
1002 ARRAY_SIZE(camera_off_gpio_fluid_table));
1003 /* FLUID: turn off 5V booster */
1004 gpio_set_value(
1005 PM8058_GPIO_PM_TO_SYS(PMIC_GPIO_FLASH_BOOST_ENABLE), 0);
1006 }
1007}
1008
1009struct resource msm_camera_resources[] = {
1010 {
1011 .start = 0xA6000000,
1012 .end = 0xA6000000 + SZ_1M - 1,
1013 .flags = IORESOURCE_MEM,
1014 },
1015 {
1016 .start = INT_VFE,
1017 .end = INT_VFE,
1018 .flags = IORESOURCE_IRQ,
1019 },
1020 {
1021 .flags = IORESOURCE_DMA,
1022 }
1023};
1024
1025struct msm_camera_device_platform_data msm_camera_device_data = {
1026 .camera_gpio_on = config_camera_on_gpios,
1027 .camera_gpio_off = config_camera_off_gpios,
1028 .ioext.camifpadphy = 0xAB000000,
1029 .ioext.camifpadsz = 0x00000400,
1030 .ioext.csiphy = 0xA6100000,
1031 .ioext.csisz = 0x00000400,
1032 .ioext.csiirq = INT_CSI,
1033 .ioclk.mclk_clk_rate = 24000000,
1034 .ioclk.vfe_clk_rate = 147456000,
1035};
1036
1037static struct msm_camera_sensor_flash_src msm_flash_src_pwm = {
1038 .flash_sr_type = MSM_CAMERA_FLASH_SRC_PWM,
1039 ._fsrc.pwm_src.freq = 1000,
1040 ._fsrc.pwm_src.max_load = 300,
1041 ._fsrc.pwm_src.low_load = 30,
1042 ._fsrc.pwm_src.high_load = 100,
1043 ._fsrc.pwm_src.channel = 7,
1044};
1045
1046#ifdef CONFIG_MT9D112
1047static struct msm_camera_sensor_flash_data flash_mt9d112 = {
1048 .flash_type = MSM_CAMERA_FLASH_LED,
1049 .flash_src = &msm_flash_src_pwm
1050};
1051
1052static struct msm_camera_sensor_info msm_camera_sensor_mt9d112_data = {
1053 .sensor_name = "mt9d112",
1054 .sensor_reset = 0,
1055 .sensor_pwd = 85,
1056 .vcm_pwd = 1,
1057 .vcm_enable = 0,
1058 .pdata = &msm_camera_device_data,
1059 .resource = msm_camera_resources,
1060 .num_resources = ARRAY_SIZE(msm_camera_resources),
1061 .flash_data = &flash_mt9d112,
1062 .csi_if = 0
1063};
1064
1065static struct platform_device msm_camera_sensor_mt9d112 = {
1066 .name = "msm_camera_mt9d112",
1067 .dev = {
1068 .platform_data = &msm_camera_sensor_mt9d112_data,
1069 },
1070};
1071#endif
1072
1073#ifdef CONFIG_WEBCAM_OV9726
1074
1075static struct msm_camera_sensor_platform_info ov9726_sensor_7630_info = {
1076 .mount_angle = 90
1077};
1078
1079static struct msm_camera_sensor_flash_data flash_ov9726 = {
1080 .flash_type = MSM_CAMERA_FLASH_LED,
1081 .flash_src = &msm_flash_src_pwm
1082};
1083static struct msm_camera_sensor_info msm_camera_sensor_ov9726_data = {
1084 .sensor_name = "ov9726",
1085 .sensor_reset = 0,
1086 .sensor_pwd = 85,
1087 .vcm_pwd = 1,
1088 .vcm_enable = 0,
1089 .pdata = &msm_camera_device_data,
1090 .resource = msm_camera_resources,
1091 .num_resources = ARRAY_SIZE(msm_camera_resources),
1092 .flash_data = &flash_ov9726,
1093 .sensor_platform_info = &ov9726_sensor_7630_info,
1094 .csi_if = 1
1095};
1096struct platform_device msm_camera_sensor_ov9726 = {
1097 .name = "msm_camera_ov9726",
1098 .dev = {
1099 .platform_data = &msm_camera_sensor_ov9726_data,
1100 },
1101};
1102#endif
1103
1104#ifdef CONFIG_S5K3E2FX
1105static struct msm_camera_sensor_flash_data flash_s5k3e2fx = {
1106 .flash_type = MSM_CAMERA_FLASH_LED,
1107 .flash_src = &msm_flash_src_pwm,
1108};
1109
1110static struct msm_camera_sensor_info msm_camera_sensor_s5k3e2fx_data = {
1111 .sensor_name = "s5k3e2fx",
1112 .sensor_reset = 0,
1113 .sensor_pwd = 85,
1114 .vcm_pwd = 1,
1115 .vcm_enable = 0,
1116 .pdata = &msm_camera_device_data,
1117 .resource = msm_camera_resources,
1118 .num_resources = ARRAY_SIZE(msm_camera_resources),
1119 .flash_data = &flash_s5k3e2fx,
1120 .csi_if = 0
1121};
1122
1123static struct platform_device msm_camera_sensor_s5k3e2fx = {
1124 .name = "msm_camera_s5k3e2fx",
1125 .dev = {
1126 .platform_data = &msm_camera_sensor_s5k3e2fx_data,
1127 },
1128};
1129#endif
1130
1131#ifdef CONFIG_MT9P012
1132static struct msm_camera_sensor_flash_data flash_mt9p012 = {
1133 .flash_type = MSM_CAMERA_FLASH_LED,
1134 .flash_src = &msm_flash_src_pwm
1135};
1136
1137static struct msm_camera_sensor_info msm_camera_sensor_mt9p012_data = {
1138 .sensor_name = "mt9p012",
1139 .sensor_reset = 0,
1140 .sensor_pwd = 85,
1141 .vcm_pwd = 1,
1142 .vcm_enable = 1,
1143 .pdata = &msm_camera_device_data,
1144 .resource = msm_camera_resources,
1145 .num_resources = ARRAY_SIZE(msm_camera_resources),
1146 .flash_data = &flash_mt9p012,
1147 .csi_if = 0
1148};
1149
1150static struct platform_device msm_camera_sensor_mt9p012 = {
1151 .name = "msm_camera_mt9p012",
1152 .dev = {
1153 .platform_data = &msm_camera_sensor_mt9p012_data,
1154 },
1155};
1156#endif
1157
1158#ifdef CONFIG_MT9E013
1159static struct msm_camera_sensor_platform_info mt9e013_sensor_7630_info = {
1160 .mount_angle = 0
1161};
1162
1163static struct msm_camera_sensor_flash_data flash_mt9e013 = {
1164 .flash_type = MSM_CAMERA_FLASH_LED,
1165 .flash_src = &msm_flash_src_pwm
1166};
1167
1168static struct msm_camera_sensor_info msm_camera_sensor_mt9e013_data = {
1169 .sensor_name = "mt9e013",
1170 .sensor_reset = 0,
1171 .sensor_pwd = 85,
1172 .vcm_pwd = 1,
1173 .vcm_enable = 1,
1174 .pdata = &msm_camera_device_data,
1175 .resource = msm_camera_resources,
1176 .num_resources = ARRAY_SIZE(msm_camera_resources),
1177 .flash_data = &flash_mt9e013,
1178 .sensor_platform_info = &mt9e013_sensor_7630_info,
1179 .csi_if = 1
1180};
1181
1182static struct platform_device msm_camera_sensor_mt9e013 = {
1183 .name = "msm_camera_mt9e013",
1184 .dev = {
1185 .platform_data = &msm_camera_sensor_mt9e013_data,
1186 },
1187};
1188#endif
1189
1190#ifdef CONFIG_VX6953
Jilai Wang971f97f2011-07-13 14:25:25 -04001191static struct msm_camera_sensor_platform_info vx6953_sensor_7630_info = {
1192 .mount_angle = 0
1193};
1194
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001195static struct msm_camera_sensor_flash_data flash_vx6953 = {
1196 .flash_type = MSM_CAMERA_FLASH_LED,
1197 .flash_src = &msm_flash_src_pwm
1198};
1199static struct msm_camera_sensor_info msm_camera_sensor_vx6953_data = {
1200 .sensor_name = "vx6953",
1201 .sensor_reset = 0,
1202 .sensor_pwd = 85,
1203 .vcm_pwd = 1,
1204 .vcm_enable = 0,
1205 .pdata = &msm_camera_device_data,
1206 .resource = msm_camera_resources,
1207 .num_resources = ARRAY_SIZE(msm_camera_resources),
Jilai Wang971f97f2011-07-13 14:25:25 -04001208 .sensor_platform_info = &vx6953_sensor_7630_info,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001209 .flash_data = &flash_vx6953,
1210 .csi_if = 1
1211};
1212static struct platform_device msm_camera_sensor_vx6953 = {
1213 .name = "msm_camera_vx6953",
1214 .dev = {
1215 .platform_data = &msm_camera_sensor_vx6953_data,
1216 },
1217};
1218#endif
1219
1220#ifdef CONFIG_SN12M0PZ
1221static struct msm_camera_sensor_flash_src msm_flash_src_current_driver = {
1222 .flash_sr_type = MSM_CAMERA_FLASH_SRC_CURRENT_DRIVER,
1223 ._fsrc.current_driver_src.low_current = 210,
1224 ._fsrc.current_driver_src.high_current = 700,
1225 ._fsrc.current_driver_src.driver_channel = &pm8058_fluid_leds_data,
1226};
1227
1228static struct msm_camera_sensor_flash_data flash_sn12m0pz = {
1229 .flash_type = MSM_CAMERA_FLASH_LED,
1230 .flash_src = &msm_flash_src_current_driver
1231};
1232static struct msm_camera_sensor_info msm_camera_sensor_sn12m0pz_data = {
1233 .sensor_name = "sn12m0pz",
1234 .sensor_reset = 0,
1235 .sensor_pwd = 85,
1236 .vcm_pwd = 1,
1237 .vcm_enable = 1,
1238 .pdata = &msm_camera_device_data,
1239 .flash_data = &flash_sn12m0pz,
1240 .resource = msm_camera_resources,
1241 .num_resources = ARRAY_SIZE(msm_camera_resources),
1242 .csi_if = 0
1243};
1244
1245static struct platform_device msm_camera_sensor_sn12m0pz = {
1246 .name = "msm_camera_sn12m0pz",
1247 .dev = {
1248 .platform_data = &msm_camera_sensor_sn12m0pz_data,
1249 },
1250};
1251#endif
1252
1253#ifdef CONFIG_MT9T013
1254static struct msm_camera_sensor_flash_data flash_mt9t013 = {
1255 .flash_type = MSM_CAMERA_FLASH_LED,
1256 .flash_src = &msm_flash_src_pwm
1257};
1258
1259static struct msm_camera_sensor_info msm_camera_sensor_mt9t013_data = {
1260 .sensor_name = "mt9t013",
1261 .sensor_reset = 0,
1262 .sensor_pwd = 85,
1263 .vcm_pwd = 1,
1264 .vcm_enable = 0,
1265 .pdata = &msm_camera_device_data,
1266 .resource = msm_camera_resources,
1267 .num_resources = ARRAY_SIZE(msm_camera_resources),
1268 .flash_data = &flash_mt9t013,
1269 .csi_if = 1
1270};
1271
1272static struct platform_device msm_camera_sensor_mt9t013 = {
1273 .name = "msm_camera_mt9t013",
1274 .dev = {
1275 .platform_data = &msm_camera_sensor_mt9t013_data,
1276 },
1277};
1278#endif
1279
1280#ifdef CONFIG_MSM_GEMINI
1281static struct resource msm_gemini_resources[] = {
1282 {
1283 .start = 0xA3A00000,
1284 .end = 0xA3A00000 + 0x0150 - 1,
1285 .flags = IORESOURCE_MEM,
1286 },
1287 {
1288 .start = INT_JPEG,
1289 .end = INT_JPEG,
1290 .flags = IORESOURCE_IRQ,
1291 },
1292};
1293
1294static struct platform_device msm_gemini_device = {
1295 .name = "msm_gemini",
1296 .resource = msm_gemini_resources,
1297 .num_resources = ARRAY_SIZE(msm_gemini_resources),
1298};
1299#endif
1300
1301#ifdef CONFIG_MSM_VPE
1302static struct resource msm_vpe_resources[] = {
1303 {
1304 .start = 0xAD200000,
1305 .end = 0xAD200000 + SZ_1M - 1,
1306 .flags = IORESOURCE_MEM,
1307 },
1308 {
1309 .start = INT_VPE,
1310 .end = INT_VPE,
1311 .flags = IORESOURCE_IRQ,
1312 },
1313};
1314
1315static struct platform_device msm_vpe_device = {
1316 .name = "msm_vpe",
1317 .id = 0,
1318 .num_resources = ARRAY_SIZE(msm_vpe_resources),
1319 .resource = msm_vpe_resources,
1320};
1321#endif
1322
1323#endif /*CONFIG_MSM_CAMERA*/
1324
1325#ifdef CONFIG_MSM7KV2_AUDIO
1326static uint32_t audio_pamp_gpio_config =
1327 GPIO_CFG(82, 0, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA);
1328
1329static uint32_t audio_fluid_icodec_tx_config =
1330 GPIO_CFG(85, 0, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA);
1331
1332static int __init snddev_poweramp_gpio_init(void)
1333{
1334 int rc;
1335
1336 pr_info("snddev_poweramp_gpio_init \n");
1337 rc = gpio_tlmm_config(audio_pamp_gpio_config, GPIO_CFG_ENABLE);
1338 if (rc) {
1339 printk(KERN_ERR
1340 "%s: gpio_tlmm_config(%#x)=%d\n",
1341 __func__, audio_pamp_gpio_config, rc);
1342 }
1343 return rc;
1344}
1345
1346void msm_snddev_tx_route_config(void)
1347{
1348 int rc;
1349
1350 pr_debug("%s()\n", __func__);
1351
1352 if (machine_is_msm7x30_fluid()) {
1353 rc = gpio_tlmm_config(audio_fluid_icodec_tx_config,
1354 GPIO_CFG_ENABLE);
1355 if (rc) {
1356 printk(KERN_ERR
1357 "%s: gpio_tlmm_config(%#x)=%d\n",
1358 __func__, audio_fluid_icodec_tx_config, rc);
1359 } else
1360 gpio_set_value(85, 0);
1361 }
1362}
1363
1364void msm_snddev_tx_route_deconfig(void)
1365{
1366 int rc;
1367
1368 pr_debug("%s()\n", __func__);
1369
1370 if (machine_is_msm7x30_fluid()) {
1371 rc = gpio_tlmm_config(audio_fluid_icodec_tx_config,
1372 GPIO_CFG_DISABLE);
1373 if (rc) {
1374 printk(KERN_ERR
1375 "%s: gpio_tlmm_config(%#x)=%d\n",
1376 __func__, audio_fluid_icodec_tx_config, rc);
1377 }
1378 }
1379}
1380
1381void msm_snddev_poweramp_on(void)
1382{
1383 gpio_set_value(82, 1); /* enable spkr poweramp */
1384 pr_info("%s: power on amplifier\n", __func__);
1385}
1386
1387void msm_snddev_poweramp_off(void)
1388{
1389 gpio_set_value(82, 0); /* disable spkr poweramp */
1390 pr_info("%s: power off amplifier\n", __func__);
1391}
1392
1393static struct vreg *snddev_vreg_ncp, *snddev_vreg_gp4;
1394
1395void msm_snddev_hsed_voltage_on(void)
1396{
1397 int rc;
1398
1399 snddev_vreg_gp4 = vreg_get(NULL, "gp4");
1400 if (IS_ERR(snddev_vreg_gp4)) {
1401 pr_err("%s: vreg_get(%s) failed (%ld)\n",
1402 __func__, "gp4", PTR_ERR(snddev_vreg_gp4));
1403 return;
1404 }
1405 rc = vreg_enable(snddev_vreg_gp4);
1406 if (rc)
1407 pr_err("%s: vreg_enable(gp4) failed (%d)\n", __func__, rc);
1408
1409 snddev_vreg_ncp = vreg_get(NULL, "ncp");
1410 if (IS_ERR(snddev_vreg_ncp)) {
1411 pr_err("%s: vreg_get(%s) failed (%ld)\n",
1412 __func__, "ncp", PTR_ERR(snddev_vreg_ncp));
1413 return;
1414 }
1415 rc = vreg_enable(snddev_vreg_ncp);
1416 if (rc)
1417 pr_err("%s: vreg_enable(ncp) failed (%d)\n", __func__, rc);
1418}
1419
1420void msm_snddev_hsed_voltage_off(void)
1421{
1422 int rc;
1423
1424 if (IS_ERR(snddev_vreg_ncp)) {
1425 pr_err("%s: vreg_get(%s) failed (%ld)\n",
1426 __func__, "ncp", PTR_ERR(snddev_vreg_ncp));
1427 return;
1428 }
1429 rc = vreg_disable(snddev_vreg_ncp);
1430 if (rc)
1431 pr_err("%s: vreg_disable(ncp) failed (%d)\n", __func__, rc);
1432 vreg_put(snddev_vreg_ncp);
1433
1434 if (IS_ERR(snddev_vreg_gp4)) {
1435 pr_err("%s: vreg_get(%s) failed (%ld)\n",
1436 __func__, "gp4", PTR_ERR(snddev_vreg_gp4));
1437 return;
1438 }
1439 rc = vreg_disable(snddev_vreg_gp4);
1440 if (rc)
1441 pr_err("%s: vreg_disable(gp4) failed (%d)\n", __func__, rc);
1442
1443 vreg_put(snddev_vreg_gp4);
1444
1445}
1446
1447static unsigned aux_pcm_gpio_on[] = {
1448 GPIO_CFG(138, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), /* PCM_DOUT */
1449 GPIO_CFG(139, 1, GPIO_CFG_INPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), /* PCM_DIN */
1450 GPIO_CFG(140, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), /* PCM_SYNC */
1451 GPIO_CFG(141, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), /* PCM_CLK */
1452};
1453
1454static int __init aux_pcm_gpio_init(void)
1455{
1456 int pin, rc;
1457
1458 pr_info("aux_pcm_gpio_init \n");
1459 for (pin = 0; pin < ARRAY_SIZE(aux_pcm_gpio_on); pin++) {
1460 rc = gpio_tlmm_config(aux_pcm_gpio_on[pin],
1461 GPIO_CFG_ENABLE);
1462 if (rc) {
1463 printk(KERN_ERR
1464 "%s: gpio_tlmm_config(%#x)=%d\n",
1465 __func__, aux_pcm_gpio_on[pin], rc);
1466 }
1467 }
1468 return rc;
1469}
1470
1471static struct msm_gpio mi2s_clk_gpios[] = {
1472 { GPIO_CFG(145, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA),
1473 "MI2S_SCLK"},
1474 { GPIO_CFG(144, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA),
1475 "MI2S_WS"},
1476 { GPIO_CFG(120, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA),
1477 "MI2S_MCLK_A"},
1478};
1479
1480static struct msm_gpio mi2s_rx_data_lines_gpios[] = {
1481 { GPIO_CFG(121, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA),
1482 "MI2S_DATA_SD0_A"},
1483 { GPIO_CFG(122, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA),
1484 "MI2S_DATA_SD1_A"},
1485 { GPIO_CFG(123, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA),
1486 "MI2S_DATA_SD2_A"},
1487 { GPIO_CFG(146, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA),
1488 "MI2S_DATA_SD3"},
1489};
1490
1491static struct msm_gpio mi2s_tx_data_lines_gpios[] = {
1492 { GPIO_CFG(146, 1, GPIO_CFG_INPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA),
1493 "MI2S_DATA_SD3"},
1494};
1495
1496int mi2s_config_clk_gpio(void)
1497{
1498 int rc = 0;
1499
1500 rc = msm_gpios_request_enable(mi2s_clk_gpios,
1501 ARRAY_SIZE(mi2s_clk_gpios));
1502 if (rc) {
1503 pr_err("%s: enable mi2s clk gpios failed\n",
1504 __func__);
1505 return rc;
1506 }
1507 return 0;
1508}
1509
1510int mi2s_unconfig_data_gpio(u32 direction, u8 sd_line_mask)
1511{
1512 int i, rc = 0;
1513 sd_line_mask &= MI2S_SD_LINE_MASK;
1514
1515 switch (direction) {
1516 case DIR_TX:
1517 msm_gpios_disable_free(mi2s_tx_data_lines_gpios, 1);
1518 break;
1519 case DIR_RX:
1520 i = 0;
1521 while (sd_line_mask) {
1522 if (sd_line_mask & 0x1)
1523 msm_gpios_disable_free(
1524 mi2s_rx_data_lines_gpios + i , 1);
1525 sd_line_mask = sd_line_mask >> 1;
1526 i++;
1527 }
1528 break;
1529 default:
1530 pr_err("%s: Invaild direction direction = %u\n",
1531 __func__, direction);
1532 rc = -EINVAL;
1533 break;
1534 }
1535 return rc;
1536}
1537
1538int mi2s_config_data_gpio(u32 direction, u8 sd_line_mask)
1539{
1540 int i , rc = 0;
1541 u8 sd_config_done_mask = 0;
1542
1543 sd_line_mask &= MI2S_SD_LINE_MASK;
1544
1545 switch (direction) {
1546 case DIR_TX:
1547 if ((sd_line_mask & MI2S_SD_0) || (sd_line_mask & MI2S_SD_1) ||
1548 (sd_line_mask & MI2S_SD_2) || !(sd_line_mask & MI2S_SD_3)) {
1549 pr_err("%s: can not use SD0 or SD1 or SD2 for TX"
1550 ".only can use SD3. sd_line_mask = 0x%x\n",
1551 __func__ , sd_line_mask);
1552 rc = -EINVAL;
1553 } else {
1554 rc = msm_gpios_request_enable(mi2s_tx_data_lines_gpios,
1555 1);
1556 if (rc)
1557 pr_err("%s: enable mi2s gpios for TX failed\n",
1558 __func__);
1559 }
1560 break;
1561 case DIR_RX:
1562 i = 0;
1563 while (sd_line_mask && (rc == 0)) {
1564 if (sd_line_mask & 0x1) {
1565 rc = msm_gpios_request_enable(
1566 mi2s_rx_data_lines_gpios + i , 1);
1567 if (rc) {
1568 pr_err("%s: enable mi2s gpios for"
1569 "RX failed. SD line = %s\n",
1570 __func__,
1571 (mi2s_rx_data_lines_gpios + i)->label);
1572 mi2s_unconfig_data_gpio(DIR_RX,
1573 sd_config_done_mask);
1574 } else
1575 sd_config_done_mask |= (1 << i);
1576 }
1577 sd_line_mask = sd_line_mask >> 1;
1578 i++;
1579 }
1580 break;
1581 default:
1582 pr_err("%s: Invaild direction direction = %u\n",
1583 __func__, direction);
1584 rc = -EINVAL;
1585 break;
1586 }
1587 return rc;
1588}
1589
1590int mi2s_unconfig_clk_gpio(void)
1591{
1592 msm_gpios_disable_free(mi2s_clk_gpios, ARRAY_SIZE(mi2s_clk_gpios));
1593 return 0;
1594}
1595
1596#endif /* CONFIG_MSM7KV2_AUDIO */
1597
1598static int __init buses_init(void)
1599{
1600 if (gpio_tlmm_config(GPIO_CFG(PMIC_GPIO_INT, 1, GPIO_CFG_INPUT,
1601 GPIO_CFG_NO_PULL, GPIO_CFG_2MA), GPIO_CFG_ENABLE))
1602 pr_err("%s: gpio_tlmm_config (gpio=%d) failed\n",
1603 __func__, PMIC_GPIO_INT);
1604
1605 if (machine_is_msm7x30_fluid()) {
1606 pm8058_7x30_data.sub_devices[PM8058_SUBDEV_KPD].platform_data
1607 = &fluid_keypad_data;
1608 } else {
1609 pm8058_7x30_data.sub_devices[PM8058_SUBDEV_KPD].platform_data
1610 = &surf_keypad_data;
1611 pm8058_7x30_data.sub_devices[PM8058_SUBDEV_KPD].pdata_size
1612 = sizeof(surf_keypad_data);
1613 }
1614
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001615 return 0;
1616}
1617
1618#define TIMPANI_RESET_GPIO 1
1619
1620struct bahama_config_register{
1621 u8 reg;
1622 u8 value;
1623 u8 mask;
1624};
1625
1626enum version{
1627 VER_1_0,
1628 VER_2_0,
1629 VER_UNSUPPORTED = 0xFF
1630};
1631
1632
1633static struct vreg *vreg_marimba_1;
1634static struct vreg *vreg_marimba_2;
1635static struct vreg *vreg_marimba_3;
1636
1637static struct msm_gpio timpani_reset_gpio_cfg[] = {
1638{ GPIO_CFG(TIMPANI_RESET_GPIO, 0, GPIO_CFG_OUTPUT,
1639 GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "timpani_reset"} };
1640
1641static u8 read_bahama_ver(void)
1642{
1643 int rc;
1644 struct marimba config = { .mod_id = SLAVE_ID_BAHAMA };
1645 u8 bahama_version;
1646
1647 rc = marimba_read_bit_mask(&config, 0x00, &bahama_version, 1, 0x1F);
1648 if (rc < 0) {
1649 printk(KERN_ERR
1650 "%s: version read failed: %d\n",
1651 __func__, rc);
1652 return rc;
1653 } else {
1654 printk(KERN_INFO
1655 "%s: version read got: 0x%x\n",
1656 __func__, bahama_version);
1657 }
1658
1659 switch (bahama_version) {
1660 case 0x08: /* varient of bahama v1 */
1661 case 0x10:
1662 case 0x00:
1663 return VER_1_0;
1664 case 0x09: /* variant of bahama v2 */
1665 return VER_2_0;
1666 default:
1667 return VER_UNSUPPORTED;
1668 }
1669}
1670
1671static int config_timpani_reset(void)
1672{
1673 int rc;
1674
1675 rc = msm_gpios_request_enable(timpani_reset_gpio_cfg,
1676 ARRAY_SIZE(timpani_reset_gpio_cfg));
1677 if (rc < 0) {
1678 printk(KERN_ERR
1679 "%s: msm_gpios_request_enable failed (%d)\n",
1680 __func__, rc);
1681 }
1682 return rc;
1683}
1684
1685static unsigned int msm_timpani_setup_power(void)
1686{
1687 int rc;
1688
1689 rc = config_timpani_reset();
1690 if (rc < 0)
1691 goto out;
1692
1693 rc = vreg_enable(vreg_marimba_1);
1694 if (rc) {
1695 printk(KERN_ERR "%s: vreg_enable() = %d\n",
1696 __func__, rc);
1697 goto out;
1698 }
1699 rc = vreg_enable(vreg_marimba_2);
1700 if (rc) {
1701 printk(KERN_ERR "%s: vreg_enable() = %d\n",
1702 __func__, rc);
1703 goto fail_disable_vreg_marimba_1;
1704 }
1705
1706 rc = gpio_direction_output(TIMPANI_RESET_GPIO, 1);
1707 if (rc < 0) {
1708 printk(KERN_ERR
1709 "%s: gpio_direction_output failed (%d)\n",
1710 __func__, rc);
1711 msm_gpios_free(timpani_reset_gpio_cfg,
1712 ARRAY_SIZE(timpani_reset_gpio_cfg));
1713 vreg_disable(vreg_marimba_2);
1714 } else
1715 goto out;
1716
1717
1718fail_disable_vreg_marimba_1:
1719 vreg_disable(vreg_marimba_1);
1720
1721out:
1722 return rc;
1723};
1724
1725static void msm_timpani_shutdown_power(void)
1726{
1727 int rc;
1728
1729 rc = vreg_disable(vreg_marimba_1);
1730 if (rc) {
1731 printk(KERN_ERR "%s: return val: %d\n",
1732 __func__, rc);
1733 }
1734 rc = vreg_disable(vreg_marimba_2);
1735 if (rc) {
1736 printk(KERN_ERR "%s: return val: %d\n",
1737 __func__, rc);
1738 }
1739
1740 rc = gpio_direction_output(TIMPANI_RESET_GPIO, 0);
1741 if (rc < 0) {
1742 printk(KERN_ERR
1743 "%s: gpio_direction_output failed (%d)\n",
1744 __func__, rc);
1745 }
1746
1747 msm_gpios_free(timpani_reset_gpio_cfg,
1748 ARRAY_SIZE(timpani_reset_gpio_cfg));
1749};
1750
1751static unsigned int msm_bahama_core_config(int type)
1752{
1753 int rc = 0;
1754
1755 if (type == BAHAMA_ID) {
1756
1757 int i;
1758 struct marimba config = { .mod_id = SLAVE_ID_BAHAMA };
1759
1760 const struct bahama_config_register v20_init[] = {
1761 /* reg, value, mask */
1762 { 0xF4, 0x84, 0xFF }, /* AREG */
1763 { 0xF0, 0x04, 0xFF } /* DREG */
1764 };
1765
1766 if (read_bahama_ver() == VER_2_0) {
1767 for (i = 0; i < ARRAY_SIZE(v20_init); i++) {
1768 u8 value = v20_init[i].value;
1769 rc = marimba_write_bit_mask(&config,
1770 v20_init[i].reg,
1771 &value,
1772 sizeof(v20_init[i].value),
1773 v20_init[i].mask);
1774 if (rc < 0) {
1775 printk(KERN_ERR
1776 "%s: reg %d write failed: %d\n",
1777 __func__, v20_init[i].reg, rc);
1778 return rc;
1779 }
1780 printk(KERN_INFO "%s: reg 0x%02x value 0x%02x"
1781 " mask 0x%02x\n",
1782 __func__, v20_init[i].reg,
1783 v20_init[i].value, v20_init[i].mask);
1784 }
1785 }
1786 }
1787 printk(KERN_INFO "core type: %d\n", type);
1788
1789 return rc;
1790}
1791
1792static unsigned int msm_bahama_setup_power(void)
1793{
1794 int rc;
1795
1796 rc = vreg_enable(vreg_marimba_3);
1797 if (rc) {
1798 printk(KERN_ERR "%s: vreg_enable() = %d\n",
1799 __func__, rc);
1800 }
1801
1802 return rc;
1803};
1804
1805static unsigned int msm_bahama_shutdown_power(int value)
1806{
1807 int rc = 0;
1808
1809 if (value != BAHAMA_ID) {
1810 rc = vreg_disable(vreg_marimba_3);
1811 if (rc) {
1812 printk(KERN_ERR "%s: return val: %d\n",
1813 __func__, rc);
1814 }
1815 }
1816
1817 return rc;
1818};
1819
1820static struct msm_gpio marimba_svlte_config_clock[] = {
1821 { GPIO_CFG(34, 0, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA),
1822 "MARIMBA_SVLTE_CLOCK_ENABLE" },
1823};
1824
1825static unsigned int msm_marimba_gpio_config_svlte(int gpio_cfg_marimba)
1826{
1827 if (machine_is_msm8x55_svlte_surf() ||
1828 machine_is_msm8x55_svlte_ffa()) {
1829 if (gpio_cfg_marimba)
1830 gpio_set_value(GPIO_PIN
1831 (marimba_svlte_config_clock->gpio_cfg), 1);
1832 else
1833 gpio_set_value(GPIO_PIN
1834 (marimba_svlte_config_clock->gpio_cfg), 0);
1835 }
1836
1837 return 0;
1838};
1839
1840static unsigned int msm_marimba_setup_power(void)
1841{
1842 int rc;
1843
1844 rc = vreg_enable(vreg_marimba_1);
1845 if (rc) {
1846 printk(KERN_ERR "%s: vreg_enable() = %d \n",
1847 __func__, rc);
1848 goto out;
1849 }
1850 rc = vreg_enable(vreg_marimba_2);
1851 if (rc) {
1852 printk(KERN_ERR "%s: vreg_enable() = %d \n",
1853 __func__, rc);
1854 goto out;
1855 }
1856
1857 if (machine_is_msm8x55_svlte_surf() || machine_is_msm8x55_svlte_ffa()) {
1858 rc = msm_gpios_request_enable(marimba_svlte_config_clock,
1859 ARRAY_SIZE(marimba_svlte_config_clock));
1860 if (rc < 0) {
1861 printk(KERN_ERR
1862 "%s: msm_gpios_request_enable failed (%d)\n",
1863 __func__, rc);
1864 return rc;
1865 }
1866
1867 rc = gpio_direction_output(GPIO_PIN
1868 (marimba_svlte_config_clock->gpio_cfg), 0);
1869 if (rc < 0) {
1870 printk(KERN_ERR
1871 "%s: gpio_direction_output failed (%d)\n",
1872 __func__, rc);
1873 return rc;
1874 }
1875 }
1876
1877out:
1878 return rc;
1879};
1880
1881static void msm_marimba_shutdown_power(void)
1882{
1883 int rc;
1884
1885 rc = vreg_disable(vreg_marimba_1);
1886 if (rc) {
1887 printk(KERN_ERR "%s: return val: %d\n",
1888 __func__, rc);
1889 }
1890 rc = vreg_disable(vreg_marimba_2);
1891 if (rc) {
1892 printk(KERN_ERR "%s: return val: %d \n",
1893 __func__, rc);
1894 }
1895};
1896
1897static int bahama_present(void)
1898{
1899 int id;
1900 switch (id = adie_get_detected_connectivity_type()) {
1901 case BAHAMA_ID:
1902 return 1;
1903
1904 case MARIMBA_ID:
1905 return 0;
1906
1907 case TIMPANI_ID:
1908 default:
1909 printk(KERN_ERR "%s: unexpected adie connectivity type: %d\n",
1910 __func__, id);
1911 return -ENODEV;
1912 }
1913}
1914
1915struct vreg *fm_regulator;
1916static int fm_radio_setup(struct marimba_fm_platform_data *pdata)
1917{
1918 int rc;
1919 uint32_t irqcfg;
1920 const char *id = "FMPW";
1921
1922 int bahama_not_marimba = bahama_present();
1923
1924 if (bahama_not_marimba == -1) {
1925 printk(KERN_WARNING "%s: bahama_present: %d\n",
1926 __func__, bahama_not_marimba);
1927 return -ENODEV;
1928 }
1929 if (bahama_not_marimba)
1930 fm_regulator = vreg_get(NULL, "s3");
1931 else
1932 fm_regulator = vreg_get(NULL, "s2");
1933
1934 if (IS_ERR(fm_regulator)) {
1935 printk(KERN_ERR "%s: vreg get failed (%ld)\n",
1936 __func__, PTR_ERR(fm_regulator));
1937 return -1;
1938 }
1939 if (!bahama_not_marimba) {
1940
1941 rc = pmapp_vreg_level_vote(id, PMAPP_VREG_S2, 1300);
1942
1943 if (rc < 0) {
1944 printk(KERN_ERR "%s: voltage level vote failed (%d)\n",
1945 __func__, rc);
1946 return rc;
1947 }
1948 }
1949 rc = vreg_enable(fm_regulator);
1950 if (rc) {
1951 printk(KERN_ERR "%s: vreg_enable() = %d\n",
1952 __func__, rc);
1953 return rc;
1954 }
1955
1956 rc = pmapp_clock_vote(id, PMAPP_CLOCK_ID_DO,
1957 PMAPP_CLOCK_VOTE_ON);
1958 if (rc < 0) {
1959 printk(KERN_ERR "%s: clock vote failed (%d)\n",
1960 __func__, rc);
1961 goto fm_clock_vote_fail;
1962 }
1963 /*Request the Clock Using GPIO34/AP2MDM_MRMBCK_EN in case
1964 of svlte*/
1965 if (machine_is_msm8x55_svlte_surf() ||
1966 machine_is_msm8x55_svlte_ffa()) {
1967 rc = marimba_gpio_config(1);
1968 if (rc < 0)
1969 printk(KERN_ERR "%s: clock enable for svlte : %d\n",
1970 __func__, rc);
1971 }
1972 irqcfg = GPIO_CFG(147, 0, GPIO_CFG_INPUT, GPIO_CFG_NO_PULL,
1973 GPIO_CFG_2MA);
1974 rc = gpio_tlmm_config(irqcfg, GPIO_CFG_ENABLE);
1975 if (rc) {
1976 printk(KERN_ERR "%s: gpio_tlmm_config(%#x)=%d\n",
1977 __func__, irqcfg, rc);
1978 rc = -EIO;
1979 goto fm_gpio_config_fail;
1980
1981 }
1982 return 0;
1983fm_gpio_config_fail:
1984 pmapp_clock_vote(id, PMAPP_CLOCK_ID_DO,
1985 PMAPP_CLOCK_VOTE_OFF);
1986fm_clock_vote_fail:
1987 vreg_disable(fm_regulator);
1988 return rc;
1989
1990};
1991
1992static void fm_radio_shutdown(struct marimba_fm_platform_data *pdata)
1993{
1994 int rc;
1995 const char *id = "FMPW";
1996 uint32_t irqcfg = GPIO_CFG(147, 0, GPIO_CFG_INPUT, GPIO_CFG_PULL_UP,
1997 GPIO_CFG_2MA);
1998
1999 int bahama_not_marimba = bahama_present();
2000 if (bahama_not_marimba == -1) {
2001 printk(KERN_WARNING "%s: bahama_present: %d\n",
2002 __func__, bahama_not_marimba);
2003 return;
2004 }
2005
2006 rc = gpio_tlmm_config(irqcfg, GPIO_CFG_ENABLE);
2007 if (rc) {
2008 printk(KERN_ERR "%s: gpio_tlmm_config(%#x)=%d\n",
2009 __func__, irqcfg, rc);
2010 }
2011 if (fm_regulator != NULL) {
2012 rc = vreg_disable(fm_regulator);
2013
2014 if (rc) {
2015 printk(KERN_ERR "%s: return val: %d\n",
2016 __func__, rc);
2017 }
2018 fm_regulator = NULL;
2019 }
2020 rc = pmapp_clock_vote(id, PMAPP_CLOCK_ID_DO,
2021 PMAPP_CLOCK_VOTE_OFF);
2022 if (rc < 0)
2023 printk(KERN_ERR "%s: clock_vote return val: %d\n",
2024 __func__, rc);
2025
2026 /*Disable the Clock Using GPIO34/AP2MDM_MRMBCK_EN in case
2027 of svlte*/
2028 if (machine_is_msm8x55_svlte_surf() ||
2029 machine_is_msm8x55_svlte_ffa()) {
2030 rc = marimba_gpio_config(0);
2031 if (rc < 0)
2032 printk(KERN_ERR "%s: clock disable for svlte : %d\n",
2033 __func__, rc);
2034 }
2035
2036
2037 if (!bahama_not_marimba) {
2038 rc = pmapp_vreg_level_vote(id, PMAPP_VREG_S2, 0);
2039
2040 if (rc < 0)
2041 printk(KERN_ERR "%s: vreg level vote return val: %d\n",
2042 __func__, rc);
2043 }
2044}
2045
2046static struct marimba_fm_platform_data marimba_fm_pdata = {
2047 .fm_setup = fm_radio_setup,
2048 .fm_shutdown = fm_radio_shutdown,
2049 .irq = MSM_GPIO_TO_INT(147),
2050 .vreg_s2 = NULL,
2051 .vreg_xo_out = NULL,
2052 .is_fm_soc_i2s_master = false,
2053 .config_i2s_gpio = NULL,
2054};
2055
2056
2057/* Slave id address for FM/CDC/QMEMBIST
2058 * Values can be programmed using Marimba slave id 0
2059 * should there be a conflict with other I2C devices
2060 * */
2061#define MARIMBA_SLAVE_ID_FM_ADDR 0x2A
2062#define MARIMBA_SLAVE_ID_CDC_ADDR 0x77
2063#define MARIMBA_SLAVE_ID_QMEMBIST_ADDR 0X66
2064
2065#define BAHAMA_SLAVE_ID_FM_ADDR 0x2A
2066#define BAHAMA_SLAVE_ID_QMEMBIST_ADDR 0x7B
2067
2068static const char *tsadc_id = "MADC";
2069static const char *vregs_tsadc_name[] = {
2070 "gp12",
2071 "s2",
2072};
2073static struct vreg *vregs_tsadc[ARRAY_SIZE(vregs_tsadc_name)];
2074
2075static const char *vregs_timpani_tsadc_name[] = {
2076 "s3",
2077 "gp12",
2078 "gp16"
2079};
2080static struct vreg *vregs_timpani_tsadc[ARRAY_SIZE(vregs_timpani_tsadc_name)];
2081
2082static int marimba_tsadc_power(int vreg_on)
2083{
2084 int i, rc = 0;
2085 int tsadc_adie_type = adie_get_detected_codec_type();
2086
2087 if (tsadc_adie_type == TIMPANI_ID) {
2088 for (i = 0; i < ARRAY_SIZE(vregs_timpani_tsadc_name); i++) {
2089 if (!vregs_timpani_tsadc[i]) {
2090 pr_err("%s: vreg_get %s failed(%d)\n",
2091 __func__, vregs_timpani_tsadc_name[i], rc);
2092 goto vreg_fail;
2093 }
2094
2095 rc = vreg_on ? vreg_enable(vregs_timpani_tsadc[i]) :
2096 vreg_disable(vregs_timpani_tsadc[i]);
2097 if (rc < 0) {
2098 pr_err("%s: vreg %s %s failed(%d)\n",
2099 __func__, vregs_timpani_tsadc_name[i],
2100 vreg_on ? "enable" : "disable", rc);
2101 goto vreg_fail;
2102 }
2103 }
2104 /* Vote for D0 and D1 buffer */
2105 rc = pmapp_clock_vote(tsadc_id, PMAPP_CLOCK_ID_D1,
2106 vreg_on ? PMAPP_CLOCK_VOTE_ON : PMAPP_CLOCK_VOTE_OFF);
2107 if (rc) {
2108 pr_err("%s: unable to %svote for d1 clk\n",
2109 __func__, vreg_on ? "" : "de-");
2110 goto do_vote_fail;
2111 }
2112 rc = pmapp_clock_vote(tsadc_id, PMAPP_CLOCK_ID_DO,
2113 vreg_on ? PMAPP_CLOCK_VOTE_ON : PMAPP_CLOCK_VOTE_OFF);
2114 if (rc) {
2115 pr_err("%s: unable to %svote for d1 clk\n",
2116 __func__, vreg_on ? "" : "de-");
2117 goto do_vote_fail;
2118 }
2119 } else if (tsadc_adie_type == MARIMBA_ID) {
2120 for (i = 0; i < ARRAY_SIZE(vregs_tsadc_name); i++) {
2121 if (!vregs_tsadc[i]) {
2122 pr_err("%s: vreg_get %s failed (%d)\n",
2123 __func__, vregs_tsadc_name[i], rc);
2124 goto vreg_fail;
2125 }
2126
2127 rc = vreg_on ? vreg_enable(vregs_tsadc[i]) :
2128 vreg_disable(vregs_tsadc[i]);
2129 if (rc < 0) {
2130 pr_err("%s: vreg %s %s failed (%d)\n",
2131 __func__, vregs_tsadc_name[i],
2132 vreg_on ? "enable" : "disable", rc);
2133 goto vreg_fail;
2134 }
2135 }
2136 /* If marimba vote for DO buffer */
2137 rc = pmapp_clock_vote(tsadc_id, PMAPP_CLOCK_ID_DO,
2138 vreg_on ? PMAPP_CLOCK_VOTE_ON : PMAPP_CLOCK_VOTE_OFF);
2139 if (rc) {
2140 pr_err("%s: unable to %svote for d0 clk\n",
2141 __func__, vreg_on ? "" : "de-");
2142 goto do_vote_fail;
2143 }
2144 } else {
2145 pr_err("%s:Adie %d not supported\n",
2146 __func__, tsadc_adie_type);
2147 return -ENODEV;
2148 }
2149
2150 msleep(5); /* ensure power is stable */
2151
2152 return 0;
2153
2154do_vote_fail:
2155vreg_fail:
2156 while (i) {
2157 if (vreg_on) {
2158 if (tsadc_adie_type == TIMPANI_ID)
2159 vreg_disable(vregs_timpani_tsadc[--i]);
2160 else if (tsadc_adie_type == MARIMBA_ID)
2161 vreg_disable(vregs_tsadc[--i]);
2162 } else {
2163 if (tsadc_adie_type == TIMPANI_ID)
2164 vreg_enable(vregs_timpani_tsadc[--i]);
2165 else if (tsadc_adie_type == MARIMBA_ID)
2166 vreg_enable(vregs_tsadc[--i]);
2167 }
2168 }
2169
2170 return rc;
2171}
2172
2173static int marimba_tsadc_vote(int vote_on)
2174{
2175 int rc = 0;
2176
2177 if (adie_get_detected_codec_type() == MARIMBA_ID) {
2178 int level = vote_on ? 1300 : 0;
2179 rc = pmapp_vreg_level_vote(tsadc_id, PMAPP_VREG_S2, level);
2180 if (rc < 0)
2181 pr_err("%s: vreg level %s failed (%d)\n",
2182 __func__, vote_on ? "on" : "off", rc);
2183 }
2184
2185 return rc;
2186}
2187
2188static int marimba_tsadc_init(void)
2189{
2190 int i, rc = 0;
2191 int tsadc_adie_type = adie_get_detected_codec_type();
2192
2193 if (tsadc_adie_type == TIMPANI_ID) {
2194 for (i = 0; i < ARRAY_SIZE(vregs_timpani_tsadc_name); i++) {
2195 vregs_timpani_tsadc[i] = vreg_get(NULL,
2196 vregs_timpani_tsadc_name[i]);
2197 if (IS_ERR(vregs_timpani_tsadc[i])) {
2198 pr_err("%s: vreg get %s failed (%ld)\n",
2199 __func__, vregs_timpani_tsadc_name[i],
2200 PTR_ERR(vregs_timpani_tsadc[i]));
2201 rc = PTR_ERR(vregs_timpani_tsadc[i]);
2202 goto vreg_get_fail;
2203 }
2204 }
2205 } else if (tsadc_adie_type == MARIMBA_ID) {
2206 for (i = 0; i < ARRAY_SIZE(vregs_tsadc_name); i++) {
2207 vregs_tsadc[i] = vreg_get(NULL, vregs_tsadc_name[i]);
2208 if (IS_ERR(vregs_tsadc[i])) {
2209 pr_err("%s: vreg get %s failed (%ld)\n",
2210 __func__, vregs_tsadc_name[i],
2211 PTR_ERR(vregs_tsadc[i]));
2212 rc = PTR_ERR(vregs_tsadc[i]);
2213 goto vreg_get_fail;
2214 }
2215 }
2216 } else {
2217 pr_err("%s:Adie %d not supported\n",
2218 __func__, tsadc_adie_type);
2219 return -ENODEV;
2220 }
2221
2222 return 0;
2223
2224vreg_get_fail:
2225 while (i) {
2226 if (tsadc_adie_type == TIMPANI_ID)
2227 vreg_put(vregs_timpani_tsadc[--i]);
2228 else if (tsadc_adie_type == MARIMBA_ID)
2229 vreg_put(vregs_tsadc[--i]);
2230 }
2231 return rc;
2232}
2233
2234static int marimba_tsadc_exit(void)
2235{
2236 int i, rc = 0;
2237 int tsadc_adie_type = adie_get_detected_codec_type();
2238
2239 if (tsadc_adie_type == TIMPANI_ID) {
2240 for (i = 0; i < ARRAY_SIZE(vregs_timpani_tsadc_name); i++) {
2241 if (vregs_tsadc[i])
2242 vreg_put(vregs_timpani_tsadc[i]);
2243 }
2244 } else if (tsadc_adie_type == MARIMBA_ID) {
2245 for (i = 0; i < ARRAY_SIZE(vregs_tsadc_name); i++) {
2246 if (vregs_tsadc[i])
2247 vreg_put(vregs_tsadc[i]);
2248 }
2249 rc = pmapp_vreg_level_vote(tsadc_id, PMAPP_VREG_S2, 0);
2250 if (rc < 0)
2251 pr_err("%s: vreg level off failed (%d)\n",
2252 __func__, rc);
2253 } else {
2254 pr_err("%s:Adie %d not supported\n",
2255 __func__, tsadc_adie_type);
2256 rc = -ENODEV;
2257 }
2258
2259 return rc;
2260}
2261
2262
2263static struct msm_ts_platform_data msm_ts_data = {
2264 .min_x = 0,
2265 .max_x = 4096,
2266 .min_y = 0,
2267 .max_y = 4096,
2268 .min_press = 0,
2269 .max_press = 255,
2270 .inv_x = 4096,
2271 .inv_y = 4096,
2272 .can_wakeup = false,
2273};
2274
2275static struct marimba_tsadc_platform_data marimba_tsadc_pdata = {
2276 .marimba_tsadc_power = marimba_tsadc_power,
2277 .init = marimba_tsadc_init,
2278 .exit = marimba_tsadc_exit,
2279 .level_vote = marimba_tsadc_vote,
2280 .tsadc_prechg_en = true,
2281 .can_wakeup = false,
2282 .setup = {
2283 .pen_irq_en = true,
2284 .tsadc_en = true,
2285 },
2286 .params2 = {
2287 .input_clk_khz = 2400,
2288 .sample_prd = TSADC_CLK_3,
2289 },
2290 .params3 = {
2291 .prechg_time_nsecs = 6400,
2292 .stable_time_nsecs = 6400,
2293 .tsadc_test_mode = 0,
2294 },
2295 .tssc_data = &msm_ts_data,
2296};
2297
2298static struct vreg *vreg_codec_s4;
2299static int msm_marimba_codec_power(int vreg_on)
2300{
2301 int rc = 0;
2302
2303 if (!vreg_codec_s4) {
2304
2305 vreg_codec_s4 = vreg_get(NULL, "s4");
2306
2307 if (IS_ERR(vreg_codec_s4)) {
2308 printk(KERN_ERR "%s: vreg_get() failed (%ld)\n",
2309 __func__, PTR_ERR(vreg_codec_s4));
2310 rc = PTR_ERR(vreg_codec_s4);
2311 goto vreg_codec_s4_fail;
2312 }
2313 }
2314
2315 if (vreg_on) {
2316 rc = vreg_enable(vreg_codec_s4);
2317 if (rc)
2318 printk(KERN_ERR "%s: vreg_enable() = %d \n",
2319 __func__, rc);
2320 goto vreg_codec_s4_fail;
2321 } else {
2322 rc = vreg_disable(vreg_codec_s4);
2323 if (rc)
2324 printk(KERN_ERR "%s: vreg_disable() = %d \n",
2325 __func__, rc);
2326 goto vreg_codec_s4_fail;
2327 }
2328
2329vreg_codec_s4_fail:
2330 return rc;
2331}
2332
2333static struct marimba_codec_platform_data mariba_codec_pdata = {
2334 .marimba_codec_power = msm_marimba_codec_power,
2335#ifdef CONFIG_MARIMBA_CODEC
2336 .snddev_profile_init = msm_snddev_init,
2337#endif
2338};
2339
2340static struct marimba_platform_data marimba_pdata = {
2341 .slave_id[MARIMBA_SLAVE_ID_FM] = MARIMBA_SLAVE_ID_FM_ADDR,
2342 .slave_id[MARIMBA_SLAVE_ID_CDC] = MARIMBA_SLAVE_ID_CDC_ADDR,
2343 .slave_id[MARIMBA_SLAVE_ID_QMEMBIST] = MARIMBA_SLAVE_ID_QMEMBIST_ADDR,
2344 .slave_id[SLAVE_ID_BAHAMA_FM] = BAHAMA_SLAVE_ID_FM_ADDR,
2345 .slave_id[SLAVE_ID_BAHAMA_QMEMBIST] = BAHAMA_SLAVE_ID_QMEMBIST_ADDR,
2346 .marimba_setup = msm_marimba_setup_power,
2347 .marimba_shutdown = msm_marimba_shutdown_power,
2348 .bahama_setup = msm_bahama_setup_power,
2349 .bahama_shutdown = msm_bahama_shutdown_power,
2350 .marimba_gpio_config = msm_marimba_gpio_config_svlte,
2351 .bahama_core_config = msm_bahama_core_config,
2352 .fm = &marimba_fm_pdata,
2353 .codec = &mariba_codec_pdata,
2354 .tsadc_ssbi_adap = MARIMBA_SSBI_ADAP,
2355};
2356
2357static void __init msm7x30_init_marimba(void)
2358{
2359 int rc;
2360
2361 vreg_marimba_1 = vreg_get(NULL, "s3");
2362 if (IS_ERR(vreg_marimba_1)) {
2363 printk(KERN_ERR "%s: vreg get failed (%ld)\n",
2364 __func__, PTR_ERR(vreg_marimba_1));
2365 return;
2366 }
2367 rc = vreg_set_level(vreg_marimba_1, 1800);
2368
2369 vreg_marimba_2 = vreg_get(NULL, "gp16");
2370 if (IS_ERR(vreg_marimba_1)) {
2371 printk(KERN_ERR "%s: vreg get failed (%ld)\n",
2372 __func__, PTR_ERR(vreg_marimba_1));
2373 return;
2374 }
2375 rc = vreg_set_level(vreg_marimba_2, 1200);
2376
2377 vreg_marimba_3 = vreg_get(NULL, "usb2");
2378 if (IS_ERR(vreg_marimba_3)) {
2379 printk(KERN_ERR "%s: vreg get failed (%ld)\n",
2380 __func__, PTR_ERR(vreg_marimba_3));
2381 return;
2382 }
2383 rc = vreg_set_level(vreg_marimba_3, 1800);
2384}
2385
2386static struct marimba_codec_platform_data timpani_codec_pdata = {
2387 .marimba_codec_power = msm_marimba_codec_power,
2388#ifdef CONFIG_TIMPANI_CODEC
2389 .snddev_profile_init = msm_snddev_init_timpani,
2390#endif
2391};
2392
2393static struct marimba_platform_data timpani_pdata = {
2394 .slave_id[MARIMBA_SLAVE_ID_CDC] = MARIMBA_SLAVE_ID_CDC_ADDR,
2395 .slave_id[MARIMBA_SLAVE_ID_QMEMBIST] = MARIMBA_SLAVE_ID_QMEMBIST_ADDR,
2396 .marimba_setup = msm_timpani_setup_power,
2397 .marimba_shutdown = msm_timpani_shutdown_power,
2398 .codec = &timpani_codec_pdata,
2399 .tsadc = &marimba_tsadc_pdata,
2400 .tsadc_ssbi_adap = MARIMBA_SSBI_ADAP,
2401};
2402
2403#define TIMPANI_I2C_SLAVE_ADDR 0xD
2404
2405static struct i2c_board_info msm_i2c_gsbi7_timpani_info[] = {
2406 {
2407 I2C_BOARD_INFO("timpani", TIMPANI_I2C_SLAVE_ADDR),
2408 .platform_data = &timpani_pdata,
2409 },
2410};
2411
2412#ifdef CONFIG_MSM7KV2_AUDIO
2413static struct resource msm_aictl_resources[] = {
2414 {
2415 .name = "aictl",
2416 .start = 0xa5000100,
2417 .end = 0xa5000100,
2418 .flags = IORESOURCE_MEM,
2419 }
2420};
2421
2422static struct resource msm_mi2s_resources[] = {
2423 {
2424 .name = "hdmi",
2425 .start = 0xac900000,
2426 .end = 0xac900038,
2427 .flags = IORESOURCE_MEM,
2428 },
2429 {
2430 .name = "codec_rx",
2431 .start = 0xac940040,
2432 .end = 0xac940078,
2433 .flags = IORESOURCE_MEM,
2434 },
2435 {
2436 .name = "codec_tx",
2437 .start = 0xac980080,
2438 .end = 0xac9800B8,
2439 .flags = IORESOURCE_MEM,
2440 }
2441
2442};
2443
2444static struct msm_lpa_platform_data lpa_pdata = {
2445 .obuf_hlb_size = 0x2BFF8,
2446 .dsp_proc_id = 0,
2447 .app_proc_id = 2,
2448 .nosb_config = {
2449 .llb_min_addr = 0,
2450 .llb_max_addr = 0x3ff8,
2451 .sb_min_addr = 0,
2452 .sb_max_addr = 0,
2453 },
2454 .sb_config = {
2455 .llb_min_addr = 0,
2456 .llb_max_addr = 0x37f8,
2457 .sb_min_addr = 0x3800,
2458 .sb_max_addr = 0x3ff8,
2459 }
2460};
2461
2462static struct resource msm_lpa_resources[] = {
2463 {
2464 .name = "lpa",
2465 .start = 0xa5000000,
2466 .end = 0xa50000a0,
2467 .flags = IORESOURCE_MEM,
2468 }
2469};
2470
2471static struct resource msm_aux_pcm_resources[] = {
2472
2473 {
2474 .name = "aux_codec_reg_addr",
2475 .start = 0xac9c00c0,
2476 .end = 0xac9c00c8,
2477 .flags = IORESOURCE_MEM,
2478 },
2479 {
2480 .name = "aux_pcm_dout",
2481 .start = 138,
2482 .end = 138,
2483 .flags = IORESOURCE_IO,
2484 },
2485 {
2486 .name = "aux_pcm_din",
2487 .start = 139,
2488 .end = 139,
2489 .flags = IORESOURCE_IO,
2490 },
2491 {
2492 .name = "aux_pcm_syncout",
2493 .start = 140,
2494 .end = 140,
2495 .flags = IORESOURCE_IO,
2496 },
2497 {
2498 .name = "aux_pcm_clkin_a",
2499 .start = 141,
2500 .end = 141,
2501 .flags = IORESOURCE_IO,
2502 },
2503};
2504
2505static struct platform_device msm_aux_pcm_device = {
2506 .name = "msm_aux_pcm",
2507 .id = 0,
2508 .num_resources = ARRAY_SIZE(msm_aux_pcm_resources),
2509 .resource = msm_aux_pcm_resources,
2510};
2511
2512struct platform_device msm_aictl_device = {
2513 .name = "audio_interct",
2514 .id = 0,
2515 .num_resources = ARRAY_SIZE(msm_aictl_resources),
2516 .resource = msm_aictl_resources,
2517};
2518
2519struct platform_device msm_mi2s_device = {
2520 .name = "mi2s",
2521 .id = 0,
2522 .num_resources = ARRAY_SIZE(msm_mi2s_resources),
2523 .resource = msm_mi2s_resources,
2524};
2525
2526struct platform_device msm_lpa_device = {
2527 .name = "lpa",
2528 .id = 0,
2529 .num_resources = ARRAY_SIZE(msm_lpa_resources),
2530 .resource = msm_lpa_resources,
2531 .dev = {
2532 .platform_data = &lpa_pdata,
2533 },
2534};
2535#endif /* CONFIG_MSM7KV2_AUDIO */
2536
2537#define DEC0_FORMAT ((1<<MSM_ADSP_CODEC_MP3)| \
2538 (1<<MSM_ADSP_CODEC_AAC)|(1<<MSM_ADSP_CODEC_WMA)| \
2539 (1<<MSM_ADSP_CODEC_WMAPRO)|(1<<MSM_ADSP_CODEC_AMRWB)| \
2540 (1<<MSM_ADSP_CODEC_AMRNB)|(1<<MSM_ADSP_CODEC_WAV)| \
2541 (1<<MSM_ADSP_CODEC_ADPCM)|(1<<MSM_ADSP_CODEC_YADPCM)| \
2542 (1<<MSM_ADSP_CODEC_EVRC)|(1<<MSM_ADSP_CODEC_QCELP))
2543#define DEC1_FORMAT ((1<<MSM_ADSP_CODEC_MP3)| \
2544 (1<<MSM_ADSP_CODEC_AAC)|(1<<MSM_ADSP_CODEC_WMA)| \
2545 (1<<MSM_ADSP_CODEC_WMAPRO)|(1<<MSM_ADSP_CODEC_AMRWB)| \
2546 (1<<MSM_ADSP_CODEC_AMRNB)|(1<<MSM_ADSP_CODEC_WAV)| \
2547 (1<<MSM_ADSP_CODEC_ADPCM)|(1<<MSM_ADSP_CODEC_YADPCM)| \
2548 (1<<MSM_ADSP_CODEC_EVRC)|(1<<MSM_ADSP_CODEC_QCELP))
2549 #define DEC2_FORMAT ((1<<MSM_ADSP_CODEC_MP3)| \
2550 (1<<MSM_ADSP_CODEC_AAC)|(1<<MSM_ADSP_CODEC_WMA)| \
2551 (1<<MSM_ADSP_CODEC_WMAPRO)|(1<<MSM_ADSP_CODEC_AMRWB)| \
2552 (1<<MSM_ADSP_CODEC_AMRNB)|(1<<MSM_ADSP_CODEC_WAV)| \
2553 (1<<MSM_ADSP_CODEC_ADPCM)|(1<<MSM_ADSP_CODEC_YADPCM)| \
2554 (1<<MSM_ADSP_CODEC_EVRC)|(1<<MSM_ADSP_CODEC_QCELP))
2555 #define DEC3_FORMAT ((1<<MSM_ADSP_CODEC_MP3)| \
2556 (1<<MSM_ADSP_CODEC_AAC)|(1<<MSM_ADSP_CODEC_WMA)| \
2557 (1<<MSM_ADSP_CODEC_WMAPRO)|(1<<MSM_ADSP_CODEC_AMRWB)| \
2558 (1<<MSM_ADSP_CODEC_AMRNB)|(1<<MSM_ADSP_CODEC_WAV)| \
2559 (1<<MSM_ADSP_CODEC_ADPCM)|(1<<MSM_ADSP_CODEC_YADPCM)| \
2560 (1<<MSM_ADSP_CODEC_EVRC)|(1<<MSM_ADSP_CODEC_QCELP))
2561#define DEC4_FORMAT (1<<MSM_ADSP_CODEC_MIDI)
2562
2563static unsigned int dec_concurrency_table[] = {
2564 /* Audio LP */
2565 0,
2566 (DEC3_FORMAT|(1<<MSM_ADSP_MODE_NONTUNNEL)|(1<<MSM_ADSP_OP_DM)),
2567 (DEC2_FORMAT|(1<<MSM_ADSP_MODE_NONTUNNEL)|(1<<MSM_ADSP_OP_DM)),
2568 (DEC1_FORMAT|(1<<MSM_ADSP_MODE_NONTUNNEL)|(1<<MSM_ADSP_OP_DM)),
2569 (DEC0_FORMAT|(1<<MSM_ADSP_MODE_TUNNEL)|(1<<MSM_ADSP_MODE_LP)|
2570 (1<<MSM_ADSP_OP_DM)),
2571
2572 /* Concurrency 1 */
2573 (DEC4_FORMAT),
2574 (DEC3_FORMAT|(1<<MSM_ADSP_MODE_TUNNEL)|(1<<MSM_ADSP_OP_DM)),
2575 (DEC2_FORMAT|(1<<MSM_ADSP_MODE_TUNNEL)|(1<<MSM_ADSP_OP_DM)),
2576 (DEC1_FORMAT|(1<<MSM_ADSP_MODE_TUNNEL)|(1<<MSM_ADSP_OP_DM)),
2577 (DEC0_FORMAT|(1<<MSM_ADSP_MODE_TUNNEL)|(1<<MSM_ADSP_OP_DM)),
2578
2579 /* Concurrency 2 */
2580 (DEC4_FORMAT),
2581 (DEC3_FORMAT|(1<<MSM_ADSP_MODE_TUNNEL)|(1<<MSM_ADSP_OP_DM)),
2582 (DEC2_FORMAT|(1<<MSM_ADSP_MODE_TUNNEL)|(1<<MSM_ADSP_OP_DM)),
2583 (DEC1_FORMAT|(1<<MSM_ADSP_MODE_TUNNEL)|(1<<MSM_ADSP_OP_DM)),
2584 (DEC0_FORMAT|(1<<MSM_ADSP_MODE_TUNNEL)|(1<<MSM_ADSP_OP_DM)),
2585
2586 /* Concurrency 3 */
2587 (DEC4_FORMAT),
2588 (DEC3_FORMAT|(1<<MSM_ADSP_MODE_TUNNEL)|(1<<MSM_ADSP_OP_DM)),
2589 (DEC2_FORMAT|(1<<MSM_ADSP_MODE_TUNNEL)|(1<<MSM_ADSP_OP_DM)),
2590 (DEC1_FORMAT|(1<<MSM_ADSP_MODE_TUNNEL)|(1<<MSM_ADSP_OP_DM)),
2591 (DEC0_FORMAT|(1<<MSM_ADSP_MODE_NONTUNNEL)|(1<<MSM_ADSP_OP_DM)),
2592
2593 /* Concurrency 4 */
2594 (DEC4_FORMAT),
2595 (DEC3_FORMAT|(1<<MSM_ADSP_MODE_TUNNEL)|(1<<MSM_ADSP_OP_DM)),
2596 (DEC2_FORMAT|(1<<MSM_ADSP_MODE_TUNNEL)|(1<<MSM_ADSP_OP_DM)),
2597 (DEC1_FORMAT|(1<<MSM_ADSP_MODE_NONTUNNEL)|(1<<MSM_ADSP_OP_DM)),
2598 (DEC0_FORMAT|(1<<MSM_ADSP_MODE_NONTUNNEL)|(1<<MSM_ADSP_OP_DM)),
2599
2600 /* Concurrency 5 */
2601 (DEC4_FORMAT),
2602 (DEC3_FORMAT|(1<<MSM_ADSP_MODE_TUNNEL)|(1<<MSM_ADSP_OP_DM)),
2603 (DEC2_FORMAT|(1<<MSM_ADSP_MODE_NONTUNNEL)|(1<<MSM_ADSP_OP_DM)),
2604 (DEC1_FORMAT|(1<<MSM_ADSP_MODE_NONTUNNEL)|(1<<MSM_ADSP_OP_DM)),
2605 (DEC0_FORMAT|(1<<MSM_ADSP_MODE_NONTUNNEL)|(1<<MSM_ADSP_OP_DM)),
2606
2607 /* Concurrency 6 */
2608 (DEC4_FORMAT),
2609 (DEC3_FORMAT|(1<<MSM_ADSP_MODE_NONTUNNEL)|(1<<MSM_ADSP_OP_DM)),
2610 (DEC2_FORMAT|(1<<MSM_ADSP_MODE_NONTUNNEL)|(1<<MSM_ADSP_OP_DM)),
2611 (DEC1_FORMAT|(1<<MSM_ADSP_MODE_NONTUNNEL)|(1<<MSM_ADSP_OP_DM)),
2612 (DEC0_FORMAT|(1<<MSM_ADSP_MODE_NONTUNNEL)|(1<<MSM_ADSP_OP_DM)),
2613};
2614
2615#define DEC_INFO(name, queueid, decid, nr_codec) { .module_name = name, \
2616 .module_queueid = queueid, .module_decid = decid, \
2617 .nr_codec_support = nr_codec}
2618
2619#define DEC_INSTANCE(max_instance_same, max_instance_diff) { \
2620 .max_instances_same_dec = max_instance_same, \
2621 .max_instances_diff_dec = max_instance_diff}
2622
2623static struct msm_adspdec_info dec_info_list[] = {
2624 DEC_INFO("AUDPLAY4TASK", 17, 4, 1), /* AudPlay4BitStreamCtrlQueue */
2625 DEC_INFO("AUDPLAY3TASK", 16, 3, 11), /* AudPlay3BitStreamCtrlQueue */
2626 DEC_INFO("AUDPLAY2TASK", 15, 2, 11), /* AudPlay2BitStreamCtrlQueue */
2627 DEC_INFO("AUDPLAY1TASK", 14, 1, 11), /* AudPlay1BitStreamCtrlQueue */
2628 DEC_INFO("AUDPLAY0TASK", 13, 0, 11), /* AudPlay0BitStreamCtrlQueue */
2629};
2630
2631static struct dec_instance_table dec_instance_list[][MSM_MAX_DEC_CNT] = {
2632 /* Non Turbo Mode */
2633 {
2634 DEC_INSTANCE(4, 3), /* WAV */
2635 DEC_INSTANCE(4, 3), /* ADPCM */
2636 DEC_INSTANCE(4, 2), /* MP3 */
2637 DEC_INSTANCE(0, 0), /* Real Audio */
2638 DEC_INSTANCE(4, 2), /* WMA */
2639 DEC_INSTANCE(3, 2), /* AAC */
2640 DEC_INSTANCE(0, 0), /* Reserved */
2641 DEC_INSTANCE(0, 0), /* MIDI */
2642 DEC_INSTANCE(4, 3), /* YADPCM */
2643 DEC_INSTANCE(4, 3), /* QCELP */
2644 DEC_INSTANCE(4, 3), /* AMRNB */
2645 DEC_INSTANCE(1, 1), /* AMRWB/WB+ */
2646 DEC_INSTANCE(4, 3), /* EVRC */
2647 DEC_INSTANCE(1, 1), /* WMAPRO */
2648 },
2649 /* Turbo Mode */
2650 {
2651 DEC_INSTANCE(4, 3), /* WAV */
2652 DEC_INSTANCE(4, 3), /* ADPCM */
2653 DEC_INSTANCE(4, 3), /* MP3 */
2654 DEC_INSTANCE(0, 0), /* Real Audio */
2655 DEC_INSTANCE(4, 3), /* WMA */
2656 DEC_INSTANCE(4, 3), /* AAC */
2657 DEC_INSTANCE(0, 0), /* Reserved */
2658 DEC_INSTANCE(0, 0), /* MIDI */
2659 DEC_INSTANCE(4, 3), /* YADPCM */
2660 DEC_INSTANCE(4, 3), /* QCELP */
2661 DEC_INSTANCE(4, 3), /* AMRNB */
2662 DEC_INSTANCE(2, 3), /* AMRWB/WB+ */
2663 DEC_INSTANCE(4, 3), /* EVRC */
2664 DEC_INSTANCE(1, 2), /* WMAPRO */
2665 },
2666};
2667
2668static struct msm_adspdec_database msm_device_adspdec_database = {
2669 .num_dec = ARRAY_SIZE(dec_info_list),
2670 .num_concurrency_support = (ARRAY_SIZE(dec_concurrency_table) / \
2671 ARRAY_SIZE(dec_info_list)),
2672 .dec_concurrency_table = dec_concurrency_table,
2673 .dec_info_list = dec_info_list,
2674 .dec_instance_list = &dec_instance_list[0][0],
2675};
2676
2677static struct platform_device msm_device_adspdec = {
2678 .name = "msm_adspdec",
2679 .id = -1,
2680 .dev = {
2681 .platform_data = &msm_device_adspdec_database
2682 },
2683};
2684
2685static struct resource smc91x_resources[] = {
2686 [0] = {
2687 .start = 0x8A000300,
2688 .end = 0x8A0003ff,
2689 .flags = IORESOURCE_MEM,
2690 },
2691 [1] = {
2692 .start = MSM_GPIO_TO_INT(156),
2693 .end = MSM_GPIO_TO_INT(156),
2694 .flags = IORESOURCE_IRQ,
2695 },
2696};
2697
2698static struct platform_device smc91x_device = {
2699 .name = "smc91x",
2700 .id = 0,
2701 .num_resources = ARRAY_SIZE(smc91x_resources),
2702 .resource = smc91x_resources,
2703};
2704
2705static struct smsc911x_platform_config smsc911x_config = {
2706 .phy_interface = PHY_INTERFACE_MODE_MII,
2707 .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
2708 .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL,
2709 .flags = SMSC911X_USE_32BIT,
2710};
2711
2712static struct resource smsc911x_resources[] = {
2713 [0] = {
2714 .start = 0x8D000000,
2715 .end = 0x8D000100,
2716 .flags = IORESOURCE_MEM,
2717 },
2718 [1] = {
2719 .start = MSM_GPIO_TO_INT(88),
2720 .end = MSM_GPIO_TO_INT(88),
2721 .flags = IORESOURCE_IRQ,
2722 },
2723};
2724
2725static struct platform_device smsc911x_device = {
2726 .name = "smsc911x",
2727 .id = -1,
2728 .num_resources = ARRAY_SIZE(smsc911x_resources),
2729 .resource = smsc911x_resources,
2730 .dev = {
2731 .platform_data = &smsc911x_config,
2732 },
2733};
2734
2735static struct msm_gpio smsc911x_gpios[] = {
2736 { GPIO_CFG(172, 2, GPIO_CFG_OUTPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA), "ebi2_addr6" },
2737 { GPIO_CFG(173, 2, GPIO_CFG_OUTPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA), "ebi2_addr5" },
2738 { GPIO_CFG(174, 2, GPIO_CFG_OUTPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA), "ebi2_addr4" },
2739 { GPIO_CFG(175, 2, GPIO_CFG_OUTPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA), "ebi2_addr3" },
2740 { GPIO_CFG(176, 2, GPIO_CFG_OUTPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA), "ebi2_addr2" },
2741 { GPIO_CFG(177, 2, GPIO_CFG_OUTPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA), "ebi2_addr1" },
2742 { GPIO_CFG(178, 2, GPIO_CFG_OUTPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA), "ebi2_addr0" },
2743 { GPIO_CFG(88, 2, GPIO_CFG_INPUT, GPIO_CFG_PULL_UP, GPIO_CFG_2MA), "smsc911x_irq" },
2744};
2745
2746static void msm7x30_cfg_smsc911x(void)
2747{
2748 int rc;
2749
2750 rc = msm_gpios_request_enable(smsc911x_gpios,
2751 ARRAY_SIZE(smsc911x_gpios));
2752 if (rc)
2753 pr_err("%s: unable to enable gpios\n", __func__);
2754}
2755
2756#ifdef CONFIG_USB_G_ANDROID
2757static struct android_usb_platform_data android_usb_pdata = {
2758 .update_pid_and_serial_num = usb_diag_update_pid_and_serial_num,
2759};
2760
2761static struct platform_device android_usb_device = {
2762 .name = "android_usb",
2763 .id = -1,
2764 .dev = {
2765 .platform_data = &android_usb_pdata,
2766 },
2767};
2768#endif
2769
2770static struct msm_gpio optnav_config_data[] = {
2771 { GPIO_CFG(OPTNAV_CHIP_SELECT, 0, GPIO_CFG_OUTPUT, GPIO_CFG_PULL_UP, GPIO_CFG_8MA),
2772 "optnav_chip_select" },
2773};
2774
2775static void __iomem *virtual_optnav;
2776
2777static int optnav_gpio_setup(void)
2778{
2779 int rc = -ENODEV;
2780 rc = msm_gpios_request_enable(optnav_config_data,
2781 ARRAY_SIZE(optnav_config_data));
2782
2783 /* Configure the FPGA for GPIOs */
2784 virtual_optnav = ioremap(FPGA_OPTNAV_GPIO_ADDR, 0x4);
2785 if (!virtual_optnav) {
2786 pr_err("%s:Could not ioremap region\n", __func__);
2787 return -ENOMEM;
2788 }
2789 /*
2790 * Configure the FPGA to set GPIO 19 as
2791 * normal, active(enabled), output(MSM to SURF)
2792 */
2793 writew(0x311E, virtual_optnav);
2794 return rc;
2795}
2796
2797static void optnav_gpio_release(void)
2798{
2799 msm_gpios_disable_free(optnav_config_data,
2800 ARRAY_SIZE(optnav_config_data));
2801 iounmap(virtual_optnav);
2802}
2803
2804static struct vreg *vreg_gp7;
2805static struct vreg *vreg_gp4;
2806static struct vreg *vreg_gp9;
2807static struct vreg *vreg_usb3_3;
2808
2809static int optnav_enable(void)
2810{
2811 int rc;
2812 /*
2813 * Enable the VREGs L8(gp7), L10(gp4), L12(gp9), L6(usb)
2814 * for I2C communication with keyboard.
2815 */
2816 vreg_gp7 = vreg_get(NULL, "gp7");
2817 rc = vreg_set_level(vreg_gp7, 1800);
2818 if (rc) {
2819 pr_err("%s: vreg_set_level failed \n", __func__);
2820 goto fail_vreg_gp7;
2821 }
2822
2823 rc = vreg_enable(vreg_gp7);
2824 if (rc) {
2825 pr_err("%s: vreg_enable failed \n", __func__);
2826 goto fail_vreg_gp7;
2827 }
2828
2829 vreg_gp4 = vreg_get(NULL, "gp4");
2830 rc = vreg_set_level(vreg_gp4, 2600);
2831 if (rc) {
2832 pr_err("%s: vreg_set_level failed \n", __func__);
2833 goto fail_vreg_gp4;
2834 }
2835
2836 rc = vreg_enable(vreg_gp4);
2837 if (rc) {
2838 pr_err("%s: vreg_enable failed \n", __func__);
2839 goto fail_vreg_gp4;
2840 }
2841
2842 vreg_gp9 = vreg_get(NULL, "gp9");
2843 rc = vreg_set_level(vreg_gp9, 1800);
2844 if (rc) {
2845 pr_err("%s: vreg_set_level failed \n", __func__);
2846 goto fail_vreg_gp9;
2847 }
2848
2849 rc = vreg_enable(vreg_gp9);
2850 if (rc) {
2851 pr_err("%s: vreg_enable failed \n", __func__);
2852 goto fail_vreg_gp9;
2853 }
2854
2855 vreg_usb3_3 = vreg_get(NULL, "usb");
2856 rc = vreg_set_level(vreg_usb3_3, 3300);
2857 if (rc) {
2858 pr_err("%s: vreg_set_level failed \n", __func__);
2859 goto fail_vreg_3_3;
2860 }
2861
2862 rc = vreg_enable(vreg_usb3_3);
2863 if (rc) {
2864 pr_err("%s: vreg_enable failed \n", __func__);
2865 goto fail_vreg_3_3;
2866 }
2867
2868 /* Enable the chip select GPIO */
2869 gpio_set_value(OPTNAV_CHIP_SELECT, 1);
2870 gpio_set_value(OPTNAV_CHIP_SELECT, 0);
2871
2872 return 0;
2873
2874fail_vreg_3_3:
2875 vreg_disable(vreg_gp9);
2876fail_vreg_gp9:
2877 vreg_disable(vreg_gp4);
2878fail_vreg_gp4:
2879 vreg_disable(vreg_gp7);
2880fail_vreg_gp7:
2881 return rc;
2882}
2883
2884static void optnav_disable(void)
2885{
2886 vreg_disable(vreg_usb3_3);
2887 vreg_disable(vreg_gp9);
2888 vreg_disable(vreg_gp4);
2889 vreg_disable(vreg_gp7);
2890
2891 gpio_set_value(OPTNAV_CHIP_SELECT, 1);
2892}
2893
2894static struct ofn_atlab_platform_data optnav_data = {
2895 .gpio_setup = optnav_gpio_setup,
2896 .gpio_release = optnav_gpio_release,
2897 .optnav_on = optnav_enable,
2898 .optnav_off = optnav_disable,
2899 .rotate_xy = 0,
2900 .function1 = {
2901 .no_motion1_en = true,
2902 .touch_sensor_en = true,
2903 .ofn_en = true,
2904 .clock_select_khz = 1500,
2905 .cpi_selection = 1200,
2906 },
2907 .function2 = {
2908 .invert_y = false,
2909 .invert_x = true,
2910 .swap_x_y = false,
2911 .hold_a_b_en = true,
2912 .motion_filter_en = true,
2913 },
2914};
2915
2916static int hdmi_comm_power(int on, int show);
2917static int hdmi_init_irq(void);
2918static int hdmi_enable_5v(int on);
2919static int hdmi_core_power(int on, int show);
2920static int hdmi_cec_power(int on);
2921static bool hdmi_check_hdcp_hw_support(void);
2922
2923static struct msm_hdmi_platform_data adv7520_hdmi_data = {
2924 .irq = MSM_GPIO_TO_INT(18),
2925 .comm_power = hdmi_comm_power,
2926 .init_irq = hdmi_init_irq,
2927 .enable_5v = hdmi_enable_5v,
2928 .core_power = hdmi_core_power,
2929 .cec_power = hdmi_cec_power,
2930 .check_hdcp_hw_support = hdmi_check_hdcp_hw_support,
2931};
2932
2933#ifdef CONFIG_BOSCH_BMA150
2934static struct vreg *vreg_gp6;
2935static int sensors_ldo_enable(void)
2936{
2937 int rc;
2938
2939 /*
2940 * Enable the VREGs L8(gp7), L15(gp6)
2941 * for I2C communication with sensors.
2942 */
2943 pr_info("sensors_ldo_enable called!!\n");
2944 vreg_gp7 = vreg_get(NULL, "gp7");
2945 if (IS_ERR(vreg_gp7)) {
2946 pr_err("%s: vreg_get gp7 failed\n", __func__);
2947 rc = PTR_ERR(vreg_gp7);
2948 goto fail_gp7_get;
2949 }
2950
2951 rc = vreg_set_level(vreg_gp7, 1800);
2952 if (rc) {
2953 pr_err("%s: vreg_set_level gp7 failed\n", __func__);
2954 goto fail_gp7_level;
2955 }
2956
2957 rc = vreg_enable(vreg_gp7);
2958 if (rc) {
2959 pr_err("%s: vreg_enable gp7 failed\n", __func__);
2960 goto fail_gp7_level;
2961 }
2962
2963 vreg_gp6 = vreg_get(NULL, "gp6");
2964 if (IS_ERR(vreg_gp6)) {
2965 pr_err("%s: vreg_get gp6 failed\n", __func__);
2966 rc = PTR_ERR(vreg_gp6);
2967 goto fail_gp6_get;
2968 }
2969
2970 rc = vreg_set_level(vreg_gp6, 3050);
2971 if (rc) {
2972 pr_err("%s: vreg_set_level gp6 failed\n", __func__);
2973 goto fail_gp6_level;
2974 }
2975
2976 rc = vreg_enable(vreg_gp6);
2977 if (rc) {
2978 pr_err("%s: vreg_enable gp6 failed\n", __func__);
2979 goto fail_gp6_level;
2980 }
2981
2982 return 0;
2983
2984fail_gp6_level:
2985 vreg_put(vreg_gp6);
2986fail_gp6_get:
2987 vreg_disable(vreg_gp7);
2988fail_gp7_level:
2989 vreg_put(vreg_gp7);
2990fail_gp7_get:
2991 return rc;
2992}
2993
2994static void sensors_ldo_disable(void)
2995{
2996 pr_info("sensors_ldo_disable called!!\n");
2997 vreg_disable(vreg_gp6);
2998 vreg_put(vreg_gp6);
2999 vreg_disable(vreg_gp7);
3000 vreg_put(vreg_gp7);
3001}
3002static struct bma150_platform_data bma150_data = {
3003 .power_on = sensors_ldo_enable,
3004 .power_off = sensors_ldo_disable,
3005};
3006
3007static struct i2c_board_info bma150_board_info[] __initdata = {
3008 {
3009 I2C_BOARD_INFO("bma150", 0x38),
3010 .flags = I2C_CLIENT_WAKE,
3011 .irq = MSM_GPIO_TO_INT(BMA150_GPIO_INT),
3012 .platform_data = &bma150_data,
3013 },
3014};
3015#endif
3016
3017static struct i2c_board_info msm_i2c_board_info[] = {
3018 {
3019 I2C_BOARD_INFO("m33c01", OPTNAV_I2C_SLAVE_ADDR),
3020 .irq = MSM_GPIO_TO_INT(OPTNAV_IRQ),
3021 .platform_data = &optnav_data,
3022 },
3023 {
3024 I2C_BOARD_INFO("adv7520", ADV7520_I2C_ADDR),
3025 .platform_data = &adv7520_hdmi_data,
3026 },
3027};
3028
3029static struct i2c_board_info msm_marimba_board_info[] = {
3030 {
3031 I2C_BOARD_INFO("marimba", 0xc),
3032 .platform_data = &marimba_pdata,
3033 }
3034};
3035
3036
3037static struct msm_handset_platform_data hs_platform_data = {
3038 .hs_name = "7k_handset",
3039 .pwr_key_delay_ms = 500, /* 0 will disable end key */
3040};
3041
3042static struct platform_device hs_device = {
3043 .name = "msm-handset",
3044 .id = -1,
3045 .dev = {
3046 .platform_data = &hs_platform_data,
3047 },
3048};
3049
3050static struct msm_pm_platform_data msm_pm_data[MSM_PM_SLEEP_MODE_NR] = {
3051 [MSM_PM_SLEEP_MODE_POWER_COLLAPSE] = {
3052 .idle_supported = 1,
3053 .suspend_supported = 1,
3054 .idle_enabled = 1,
3055 .suspend_enabled = 1,
3056 .latency = 8594,
3057 .residency = 23740,
3058 },
3059 [MSM_PM_SLEEP_MODE_POWER_COLLAPSE_NO_XO_SHUTDOWN] = {
3060 .idle_supported = 1,
3061 .suspend_supported = 1,
3062 .idle_enabled = 1,
3063 .suspend_enabled = 1,
3064 .latency = 4594,
3065 .residency = 23740,
3066 },
3067 [MSM_PM_SLEEP_MODE_POWER_COLLAPSE_STANDALONE] = {
3068#ifdef CONFIG_MSM_STANDALONE_POWER_COLLAPSE
3069 .idle_supported = 1,
3070 .suspend_supported = 1,
3071 .idle_enabled = 1,
3072 .suspend_enabled = 0,
3073#else /*CONFIG_MSM_STANDALONE_POWER_COLLAPSE*/
3074 .idle_supported = 0,
3075 .suspend_supported = 0,
3076 .idle_enabled = 0,
3077 .suspend_enabled = 0,
3078#endif /*CONFIG_MSM_STANDALONE_POWER_COLLAPSE*/
3079 .latency = 500,
3080 .residency = 6000,
3081 },
3082 [MSM_PM_SLEEP_MODE_RAMP_DOWN_AND_WAIT_FOR_INTERRUPT] = {
3083 .idle_supported = 1,
3084 .suspend_supported = 1,
3085 .idle_enabled = 0,
3086 .suspend_enabled = 1,
3087 .latency = 443,
3088 .residency = 1098,
3089 },
3090 [MSM_PM_SLEEP_MODE_WAIT_FOR_INTERRUPT] = {
3091 .idle_supported = 1,
3092 .suspend_supported = 1,
3093 .idle_enabled = 1,
3094 .suspend_enabled = 1,
3095 .latency = 2,
3096 .residency = 0,
3097 },
3098};
3099
3100static struct resource qsd_spi_resources[] = {
3101 {
3102 .name = "spi_irq_in",
3103 .start = INT_SPI_INPUT,
3104 .end = INT_SPI_INPUT,
3105 .flags = IORESOURCE_IRQ,
3106 },
3107 {
3108 .name = "spi_irq_out",
3109 .start = INT_SPI_OUTPUT,
3110 .end = INT_SPI_OUTPUT,
3111 .flags = IORESOURCE_IRQ,
3112 },
3113 {
3114 .name = "spi_irq_err",
3115 .start = INT_SPI_ERROR,
3116 .end = INT_SPI_ERROR,
3117 .flags = IORESOURCE_IRQ,
3118 },
3119 {
3120 .name = "spi_base",
3121 .start = 0xA8000000,
3122 .end = 0xA8000000 + SZ_4K - 1,
3123 .flags = IORESOURCE_MEM,
3124 },
3125 {
3126 .name = "spidm_channels",
3127 .flags = IORESOURCE_DMA,
3128 },
3129 {
3130 .name = "spidm_crci",
3131 .flags = IORESOURCE_DMA,
3132 },
3133};
3134
3135#define AMDH0_BASE_PHYS 0xAC200000
3136#define ADMH0_GP_CTL (ct_adm_base + 0x3D8)
3137static int msm_qsd_spi_dma_config(void)
3138{
3139 void __iomem *ct_adm_base = 0;
3140 u32 spi_mux = 0;
3141 int ret = 0;
3142
3143 ct_adm_base = ioremap(AMDH0_BASE_PHYS, PAGE_SIZE);
3144 if (!ct_adm_base) {
3145 pr_err("%s: Could not remap %x\n", __func__, AMDH0_BASE_PHYS);
3146 return -ENOMEM;
3147 }
3148
3149 spi_mux = (ioread32(ADMH0_GP_CTL) & (0x3 << 12)) >> 12;
3150
3151 qsd_spi_resources[4].start = DMOV_USB_CHAN;
3152 qsd_spi_resources[4].end = DMOV_TSIF_CHAN;
3153
3154 switch (spi_mux) {
3155 case (1):
3156 qsd_spi_resources[5].start = DMOV_HSUART1_RX_CRCI;
3157 qsd_spi_resources[5].end = DMOV_HSUART1_TX_CRCI;
3158 break;
3159 case (2):
3160 qsd_spi_resources[5].start = DMOV_HSUART2_RX_CRCI;
3161 qsd_spi_resources[5].end = DMOV_HSUART2_TX_CRCI;
3162 break;
3163 case (3):
3164 qsd_spi_resources[5].start = DMOV_CE_OUT_CRCI;
3165 qsd_spi_resources[5].end = DMOV_CE_IN_CRCI;
3166 break;
3167 default:
3168 ret = -ENOENT;
3169 }
3170
3171 iounmap(ct_adm_base);
3172
3173 return ret;
3174}
3175
3176static struct platform_device qsd_device_spi = {
3177 .name = "spi_qsd",
3178 .id = 0,
3179 .num_resources = ARRAY_SIZE(qsd_spi_resources),
3180 .resource = qsd_spi_resources,
3181};
3182
3183#ifdef CONFIG_SPI_QSD
3184static struct spi_board_info lcdc_sharp_spi_board_info[] __initdata = {
3185 {
3186 .modalias = "lcdc_sharp_ls038y7dx01",
3187 .mode = SPI_MODE_1,
3188 .bus_num = 0,
3189 .chip_select = 0,
3190 .max_speed_hz = 26331429,
3191 }
3192};
3193static struct spi_board_info lcdc_toshiba_spi_board_info[] __initdata = {
3194 {
3195 .modalias = "lcdc_toshiba_ltm030dd40",
3196 .mode = SPI_MODE_3|SPI_CS_HIGH,
3197 .bus_num = 0,
3198 .chip_select = 0,
3199 .max_speed_hz = 9963243,
3200 }
3201};
3202#endif
3203
3204static struct msm_gpio qsd_spi_gpio_config_data[] = {
3205 { GPIO_CFG(45, 1, GPIO_CFG_INPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "spi_clk" },
3206 { GPIO_CFG(46, 1, GPIO_CFG_INPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "spi_cs0" },
3207 { GPIO_CFG(47, 1, GPIO_CFG_INPUT, GPIO_CFG_NO_PULL, GPIO_CFG_8MA), "spi_mosi" },
3208 { GPIO_CFG(48, 1, GPIO_CFG_INPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "spi_miso" },
3209};
3210
3211static int msm_qsd_spi_gpio_config(void)
3212{
3213 return msm_gpios_request_enable(qsd_spi_gpio_config_data,
3214 ARRAY_SIZE(qsd_spi_gpio_config_data));
3215}
3216
3217static void msm_qsd_spi_gpio_release(void)
3218{
3219 msm_gpios_disable_free(qsd_spi_gpio_config_data,
3220 ARRAY_SIZE(qsd_spi_gpio_config_data));
3221}
3222
3223static struct msm_spi_platform_data qsd_spi_pdata = {
3224 .max_clock_speed = 26331429,
3225 .gpio_config = msm_qsd_spi_gpio_config,
3226 .gpio_release = msm_qsd_spi_gpio_release,
3227 .dma_config = msm_qsd_spi_dma_config,
3228};
3229
3230static void __init msm_qsd_spi_init(void)
3231{
3232 qsd_device_spi.dev.platform_data = &qsd_spi_pdata;
3233}
3234
3235#ifdef CONFIG_USB_EHCI_MSM_72K
3236static void msm_hsusb_vbus_power(unsigned phy_info, int on)
3237{
3238 int rc;
3239 static int vbus_is_on;
3240 struct pm8058_gpio usb_vbus = {
3241 .direction = PM_GPIO_DIR_OUT,
3242 .pull = PM_GPIO_PULL_NO,
3243 .output_buffer = PM_GPIO_OUT_BUF_CMOS,
3244 .output_value = 1,
3245 .vin_sel = 2,
3246 .out_strength = PM_GPIO_STRENGTH_MED,
3247 .function = PM_GPIO_FUNC_NORMAL,
3248 .inv_int_pol = 0,
3249 };
3250
3251 /* If VBUS is already on (or off), do nothing. */
3252 if (unlikely(on == vbus_is_on))
3253 return;
3254
3255 if (on) {
3256 rc = pm8058_gpio_config(36, &usb_vbus);
3257 if (rc) {
3258 pr_err("%s PMIC GPIO 36 write failed\n", __func__);
3259 return;
3260 }
3261 } else {
3262 gpio_set_value_cansleep(PM8058_GPIO_PM_TO_SYS(36), 0);
3263 }
3264
3265 vbus_is_on = on;
3266}
3267
3268static struct msm_usb_host_platform_data msm_usb_host_pdata = {
3269 .phy_info = (USB_PHY_INTEGRATED | USB_PHY_MODEL_45NM),
3270 .vbus_power = msm_hsusb_vbus_power,
3271 .power_budget = 180,
3272};
3273#endif
3274
3275#ifdef CONFIG_USB_MSM_OTG_72K
3276static int hsusb_rpc_connect(int connect)
3277{
3278 if (connect)
3279 return msm_hsusb_rpc_connect();
3280 else
3281 return msm_hsusb_rpc_close();
3282}
3283#endif
3284
3285#ifdef CONFIG_USB_MSM_OTG_72K
3286static struct vreg *vreg_3p3;
3287static int msm_hsusb_ldo_init(int init)
3288{
3289 uint32_t version = 0;
3290 int def_vol = 3400;
3291
3292 version = socinfo_get_version();
3293
3294 if (SOCINFO_VERSION_MAJOR(version) >= 2 &&
3295 SOCINFO_VERSION_MINOR(version) >= 1) {
3296 def_vol = 3075;
3297 pr_debug("%s: default voltage:%d\n", __func__, def_vol);
3298 }
3299
3300 if (init) {
3301 vreg_3p3 = vreg_get(NULL, "usb");
3302 if (IS_ERR(vreg_3p3))
3303 return PTR_ERR(vreg_3p3);
3304 vreg_set_level(vreg_3p3, def_vol);
3305 } else
3306 vreg_put(vreg_3p3);
3307
3308 return 0;
3309}
3310
3311static int msm_hsusb_ldo_enable(int enable)
3312{
3313 static int ldo_status;
3314
3315 if (!vreg_3p3 || IS_ERR(vreg_3p3))
3316 return -ENODEV;
3317
3318 if (ldo_status == enable)
3319 return 0;
3320
3321 ldo_status = enable;
3322
3323 if (enable)
3324 return vreg_enable(vreg_3p3);
3325
3326 return vreg_disable(vreg_3p3);
3327}
3328
3329static int msm_hsusb_ldo_set_voltage(int mV)
3330{
3331 static int cur_voltage = 3400;
3332
3333 if (!vreg_3p3 || IS_ERR(vreg_3p3))
3334 return -ENODEV;
3335
3336 if (cur_voltage == mV)
3337 return 0;
3338
3339 cur_voltage = mV;
3340
3341 pr_debug("%s: (%d)\n", __func__, mV);
3342
3343 return vreg_set_level(vreg_3p3, mV);
3344}
3345#endif
3346
3347#ifndef CONFIG_USB_EHCI_MSM_72K
3348static int msm_hsusb_pmic_notif_init(void (*callback)(int online), int init);
3349#endif
3350static struct msm_otg_platform_data msm_otg_pdata = {
3351 .rpc_connect = hsusb_rpc_connect,
3352
3353#ifndef CONFIG_USB_EHCI_MSM_72K
3354 .pmic_vbus_notif_init = msm_hsusb_pmic_notif_init,
3355#else
3356 .vbus_power = msm_hsusb_vbus_power,
3357#endif
3358 .core_clk = 1,
3359 .pemp_level = PRE_EMPHASIS_WITH_20_PERCENT,
3360 .cdr_autoreset = CDR_AUTO_RESET_DISABLE,
3361 .drv_ampl = HS_DRV_AMPLITUDE_DEFAULT,
3362 .se1_gating = SE1_GATING_DISABLE,
3363 .chg_vbus_draw = hsusb_chg_vbus_draw,
3364 .chg_connected = hsusb_chg_connected,
3365 .chg_init = hsusb_chg_init,
3366 .ldo_enable = msm_hsusb_ldo_enable,
3367 .ldo_init = msm_hsusb_ldo_init,
3368 .ldo_set_voltage = msm_hsusb_ldo_set_voltage,
3369};
3370
3371#ifdef CONFIG_USB_GADGET
3372static struct msm_hsusb_gadget_platform_data msm_gadget_pdata = {
3373 .is_phy_status_timer_on = 1,
3374};
3375#endif
3376#ifndef CONFIG_USB_EHCI_MSM_72K
3377typedef void (*notify_vbus_state) (int);
3378notify_vbus_state notify_vbus_state_func_ptr;
3379int vbus_on_irq;
3380static irqreturn_t pmic_vbus_on_irq(int irq, void *data)
3381{
3382 pr_info("%s: vbus notification from pmic\n", __func__);
3383
3384 (*notify_vbus_state_func_ptr) (1);
3385
3386 return IRQ_HANDLED;
3387}
3388static int msm_hsusb_pmic_notif_init(void (*callback)(int online), int init)
3389{
3390 int ret;
3391
3392 if (init) {
3393 if (!callback)
3394 return -ENODEV;
3395
3396 notify_vbus_state_func_ptr = callback;
3397 vbus_on_irq = platform_get_irq_byname(&msm_device_otg,
3398 "vbus_on");
3399 if (vbus_on_irq <= 0) {
3400 pr_err("%s: unable to get vbus on irq\n", __func__);
3401 return -ENODEV;
3402 }
3403
3404 ret = request_any_context_irq(vbus_on_irq, pmic_vbus_on_irq,
3405 IRQF_TRIGGER_RISING, "msm_otg_vbus_on", NULL);
3406 if (ret < 0) {
3407 pr_info("%s: request_irq for vbus_on"
3408 "interrupt failed\n", __func__);
3409 return ret;
3410 }
3411 msm_otg_pdata.pmic_vbus_irq = vbus_on_irq;
3412 return 0;
3413 } else {
3414 free_irq(vbus_on_irq, 0);
3415 notify_vbus_state_func_ptr = NULL;
3416 return 0;
3417 }
3418}
3419#endif
3420
3421static struct android_pmem_platform_data android_pmem_pdata = {
3422 .name = "pmem",
3423 .allocator_type = PMEM_ALLOCATORTYPE_ALLORNOTHING,
3424 .cached = 1,
3425 .memory_type = MEMTYPE_EBI0,
3426};
3427
3428static struct platform_device android_pmem_device = {
3429 .name = "android_pmem",
3430 .id = 0,
3431 .dev = { .platform_data = &android_pmem_pdata },
3432};
3433
3434#ifndef CONFIG_SPI_QSD
3435static int lcdc_gpio_array_num[] = {
3436 45, /* spi_clk */
3437 46, /* spi_cs */
3438 47, /* spi_mosi */
3439 48, /* spi_miso */
3440 };
3441
3442static struct msm_gpio lcdc_gpio_config_data[] = {
3443 { GPIO_CFG(45, 0, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "spi_clk" },
3444 { GPIO_CFG(46, 0, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "spi_cs0" },
3445 { GPIO_CFG(47, 0, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "spi_mosi" },
3446 { GPIO_CFG(48, 0, GPIO_CFG_INPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "spi_miso" },
3447};
3448
3449static void lcdc_config_gpios(int enable)
3450{
3451 if (enable) {
3452 msm_gpios_request_enable(lcdc_gpio_config_data,
3453 ARRAY_SIZE(
3454 lcdc_gpio_config_data));
3455 } else
3456 msm_gpios_disable_free(lcdc_gpio_config_data,
3457 ARRAY_SIZE(
3458 lcdc_gpio_config_data));
3459}
3460#endif
3461
3462static struct msm_panel_common_pdata lcdc_sharp_panel_data = {
3463#ifndef CONFIG_SPI_QSD
3464 .panel_config_gpio = lcdc_config_gpios,
3465 .gpio_num = lcdc_gpio_array_num,
3466#endif
3467 .gpio = 2, /* LPG PMIC_GPIO26 channel number */
3468};
3469
3470static struct platform_device lcdc_sharp_panel_device = {
3471 .name = "lcdc_sharp_wvga",
3472 .id = 0,
3473 .dev = {
3474 .platform_data = &lcdc_sharp_panel_data,
3475 }
3476};
3477
3478static struct msm_gpio dtv_panel_irq_gpios[] = {
3479 { GPIO_CFG(18, 0, GPIO_CFG_INPUT, GPIO_CFG_NO_PULL, GPIO_CFG_4MA),
3480 "hdmi_int" },
3481};
3482
3483static struct msm_gpio dtv_panel_gpios[] = {
3484 { GPIO_CFG(120, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_4MA), "wca_mclk" },
3485 { GPIO_CFG(121, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_4MA), "wca_sd0" },
3486 { GPIO_CFG(122, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_4MA), "wca_sd1" },
3487 { GPIO_CFG(123, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_4MA), "wca_sd2" },
3488 { GPIO_CFG(124, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_8MA), "dtv_pclk" },
3489 { GPIO_CFG(125, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_4MA), "dtv_en" },
3490 { GPIO_CFG(126, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_4MA), "dtv_vsync" },
3491 { GPIO_CFG(127, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_4MA), "dtv_hsync" },
3492 { GPIO_CFG(128, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_4MA), "dtv_data0" },
3493 { GPIO_CFG(129, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_4MA), "dtv_data1" },
3494 { GPIO_CFG(130, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_4MA), "dtv_data2" },
3495 { GPIO_CFG(131, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_4MA), "dtv_data3" },
3496 { GPIO_CFG(132, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_4MA), "dtv_data4" },
3497 { GPIO_CFG(160, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_4MA), "dtv_data5" },
3498 { GPIO_CFG(161, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_4MA), "dtv_data6" },
3499 { GPIO_CFG(162, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_4MA), "dtv_data7" },
3500 { GPIO_CFG(163, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_4MA), "dtv_data8" },
3501 { GPIO_CFG(164, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_4MA), "dtv_data9" },
3502 { GPIO_CFG(165, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_4MA), "dtv_dat10" },
3503 { GPIO_CFG(166, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_4MA), "dtv_dat11" },
3504 { GPIO_CFG(167, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_4MA), "dtv_dat12" },
3505 { GPIO_CFG(168, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_4MA), "dtv_dat13" },
3506 { GPIO_CFG(169, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_4MA), "dtv_dat14" },
3507 { GPIO_CFG(170, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_4MA), "dtv_dat15" },
3508 { GPIO_CFG(171, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_4MA), "dtv_dat16" },
3509 { GPIO_CFG(172, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_4MA), "dtv_dat17" },
3510 { GPIO_CFG(173, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_4MA), "dtv_dat18" },
3511 { GPIO_CFG(174, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_4MA), "dtv_dat19" },
3512 { GPIO_CFG(175, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_4MA), "dtv_dat20" },
3513 { GPIO_CFG(176, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_4MA), "dtv_dat21" },
3514 { GPIO_CFG(177, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_4MA), "dtv_dat22" },
3515 { GPIO_CFG(178, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_4MA), "dtv_dat23" },
3516};
3517
3518
3519#ifdef HDMI_RESET
3520static unsigned dtv_reset_gpio =
3521 GPIO_CFG(37, 0, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA);
3522#endif
3523
3524static int gpio_set(const char *label, const char *name, int level, int on)
3525{
3526 struct vreg *vreg = vreg_get(NULL, label);
3527 int rc;
3528
3529 if (IS_ERR(vreg)) {
3530 rc = PTR_ERR(vreg);
3531 pr_err("%s: vreg %s get failed (%d)\n",
3532 __func__, name, rc);
3533 return rc;
3534 }
3535
3536 rc = vreg_set_level(vreg, level);
3537 if (rc) {
3538 pr_err("%s: vreg %s set level failed (%d)\n",
3539 __func__, name, rc);
3540 return rc;
3541 }
3542
3543 if (on)
3544 rc = vreg_enable(vreg);
3545 else
3546 rc = vreg_disable(vreg);
3547 if (rc)
3548 pr_err("%s: vreg %s enable failed (%d)\n",
3549 __func__, name, rc);
3550 return rc;
3551}
3552
3553#if defined(CONFIG_FB_MSM_HDMI_ADV7520_PANEL) || defined(CONFIG_BOSCH_BMA150)
3554/* there is an i2c address conflict between adv7520 and bma150 sensor after
3555 * power up on fluid. As a solution, the default address of adv7520's packet
3556 * memory is changed as soon as possible
3557 */
3558static int __init fluid_i2c_address_fixup(void)
3559{
3560 unsigned char wBuff[16];
3561 unsigned char rBuff[16];
3562 struct i2c_msg msgs[3];
3563 int res;
3564 int rc = -EINVAL;
3565 struct vreg *vreg_ldo8;
3566 struct i2c_adapter *adapter;
3567
3568 if (machine_is_msm7x30_fluid()) {
3569 adapter = i2c_get_adapter(0);
3570 if (!adapter) {
3571 pr_err("%s: invalid i2c adapter\n", __func__);
3572 return PTR_ERR(adapter);
3573 }
3574
3575 /* turn on LDO8 */
3576 vreg_ldo8 = vreg_get(NULL, "gp7");
3577 if (!vreg_ldo8) {
3578 pr_err("%s: VREG L8 get failed\n", __func__);
3579 goto adapter_put;
3580 }
3581
3582 rc = vreg_set_level(vreg_ldo8, 1800);
3583 if (rc) {
3584 pr_err("%s: VREG L8 set failed\n", __func__);
3585 goto ldo8_put;
3586 }
3587
3588 rc = vreg_enable(vreg_ldo8);
3589 if (rc) {
3590 pr_err("%s: VREG L8 enable failed\n", __func__);
3591 goto ldo8_put;
3592 }
3593
3594 /* change packet memory address to 0x74 */
3595 wBuff[0] = 0x45;
3596 wBuff[1] = 0x74;
3597
3598 msgs[0].addr = ADV7520_I2C_ADDR;
3599 msgs[0].flags = 0;
3600 msgs[0].buf = (unsigned char *) wBuff;
3601 msgs[0].len = 2;
3602
3603 res = i2c_transfer(adapter, msgs, 1);
3604 if (res != 1) {
3605 pr_err("%s: error writing adv7520\n", __func__);
3606 goto ldo8_disable;
3607 }
3608
3609 /* powerdown adv7520 using bit 6 */
3610 /* i2c read first */
3611 wBuff[0] = 0x41;
3612
3613 msgs[0].addr = ADV7520_I2C_ADDR;
3614 msgs[0].flags = 0;
3615 msgs[0].buf = (unsigned char *) wBuff;
3616 msgs[0].len = 1;
3617
3618 msgs[1].addr = ADV7520_I2C_ADDR;
3619 msgs[1].flags = I2C_M_RD;
3620 msgs[1].buf = rBuff;
3621 msgs[1].len = 1;
3622 res = i2c_transfer(adapter, msgs, 2);
3623 if (res != 2) {
3624 pr_err("%s: error reading adv7520\n", __func__);
3625 goto ldo8_disable;
3626 }
3627
3628 /* i2c write back */
3629 wBuff[0] = 0x41;
3630 wBuff[1] = rBuff[0] | 0x40;
3631
3632 msgs[0].addr = ADV7520_I2C_ADDR;
3633 msgs[0].flags = 0;
3634 msgs[0].buf = (unsigned char *) wBuff;
3635 msgs[0].len = 2;
3636
3637 res = i2c_transfer(adapter, msgs, 1);
3638 if (res != 1) {
3639 pr_err("%s: error writing adv7520\n", __func__);
3640 goto ldo8_disable;
3641 }
3642
3643 /* for successful fixup, we release the i2c adapter */
3644 /* but leave ldo8 on so that the adv7520 is not repowered */
3645 i2c_put_adapter(adapter);
3646 pr_info("%s: fluid i2c address conflict resolved\n", __func__);
3647 }
3648 return 0;
3649
3650ldo8_disable:
3651 vreg_disable(vreg_ldo8);
3652ldo8_put:
3653 vreg_put(vreg_ldo8);
3654adapter_put:
3655 i2c_put_adapter(adapter);
3656 return rc;
3657}
3658fs_initcall_sync(fluid_i2c_address_fixup);
3659#endif
3660
3661static int hdmi_comm_power(int on, int show)
3662{
3663 int rc = gpio_set("gp7", "LDO8", 1800, on);
3664 if (rc) {
3665 pr_warning("hdmi_comm_power: LDO8 gpio failed: rc=%d\n", rc);
3666 return rc;
3667 }
3668 rc = gpio_set("gp4", "LDO10", 2600, on);
3669 if (rc)
3670 pr_warning("hdmi_comm_power: LDO10 gpio failed: rc=%d\n", rc);
3671 if (show)
3672 pr_info("%s: i2c comm: %d <LDO8+LDO10>\n", __func__, on);
3673 return rc;
3674}
3675
3676static int hdmi_init_irq(void)
3677{
3678 int rc = msm_gpios_enable(dtv_panel_irq_gpios,
3679 ARRAY_SIZE(dtv_panel_irq_gpios));
3680 if (rc < 0) {
3681 pr_err("%s: gpio enable failed: %d\n", __func__, rc);
3682 return rc;
3683 }
3684 pr_info("%s\n", __func__);
3685
3686 return 0;
3687}
3688
3689static int hdmi_enable_5v(int on)
3690{
3691 int pmic_gpio_hdmi_5v_en ;
3692
3693 if (machine_is_msm8x55_svlte_surf() || machine_is_msm8x55_svlte_ffa() ||
3694 machine_is_msm7x30_fluid())
3695 pmic_gpio_hdmi_5v_en = PMIC_GPIO_HDMI_5V_EN_V2 ;
3696 else
3697 pmic_gpio_hdmi_5v_en = PMIC_GPIO_HDMI_5V_EN_V3 ;
3698
3699 pr_info("%s: %d\n", __func__, on);
3700 if (on) {
3701 int rc;
3702 rc = gpio_request(PM8058_GPIO_PM_TO_SYS(pmic_gpio_hdmi_5v_en),
3703 "hdmi_5V_en");
3704 if (rc) {
3705 pr_err("%s PMIC_GPIO_HDMI_5V_EN gpio_request failed\n",
3706 __func__);
3707 return rc;
3708 }
3709 gpio_set_value_cansleep(
3710 PM8058_GPIO_PM_TO_SYS(pmic_gpio_hdmi_5v_en), 1);
3711 } else {
3712 gpio_set_value_cansleep(
3713 PM8058_GPIO_PM_TO_SYS(pmic_gpio_hdmi_5v_en), 0);
3714 gpio_free(PM8058_GPIO_PM_TO_SYS(pmic_gpio_hdmi_5v_en));
3715 }
3716 return 0;
3717}
3718
3719static int hdmi_core_power(int on, int show)
3720{
3721 if (show)
3722 pr_info("%s: %d <LDO8>\n", __func__, on);
3723 return gpio_set("gp7", "LDO8", 1800, on);
3724}
3725
3726static int hdmi_cec_power(int on)
3727{
3728 pr_info("%s: %d <LDO17>\n", __func__, on);
3729 return gpio_set("gp11", "LDO17", 2600, on);
3730}
3731
3732static bool hdmi_check_hdcp_hw_support(void)
3733{
3734 if (machine_is_msm7x30_fluid())
3735 return false;
3736 else
3737 return true;
3738}
3739
3740static int dtv_panel_power(int on)
3741{
3742 int flag_on = !!on;
3743 static int dtv_power_save_on;
3744 int rc;
3745
3746 if (dtv_power_save_on == flag_on)
3747 return 0;
3748
3749 dtv_power_save_on = flag_on;
3750 pr_info("%s: %d\n", __func__, on);
3751
3752#ifdef HDMI_RESET
3753 if (on) {
3754 /* reset Toshiba WeGA chip -- toggle reset pin -- gpio_180 */
3755 rc = gpio_tlmm_config(dtv_reset_gpio, GPIO_CFG_ENABLE);
3756 if (rc) {
3757 pr_err("%s: gpio_tlmm_config(%#x)=%d\n",
3758 __func__, dtv_reset_gpio, rc);
3759 return rc;
3760 }
3761
3762 /* bring reset line low to hold reset*/
3763 gpio_set_value(37, 0);
3764 }
3765#endif
3766
3767 if (on) {
3768 rc = msm_gpios_enable(dtv_panel_gpios,
3769 ARRAY_SIZE(dtv_panel_gpios));
3770 if (rc < 0) {
3771 printk(KERN_ERR "%s: gpio enable failed: %d\n",
3772 __func__, rc);
3773 return rc;
3774 }
3775 } else {
3776 rc = msm_gpios_disable(dtv_panel_gpios,
3777 ARRAY_SIZE(dtv_panel_gpios));
3778 if (rc < 0) {
3779 printk(KERN_ERR "%s: gpio disable failed: %d\n",
3780 __func__, rc);
3781 return rc;
3782 }
3783 }
3784
3785 mdelay(5); /* ensure power is stable */
3786
3787#ifdef HDMI_RESET
3788 if (on) {
3789 gpio_set_value(37, 1); /* bring reset line high */
3790 mdelay(10); /* 10 msec before IO can be accessed */
3791 }
3792#endif
3793
3794 return rc;
3795}
3796
3797static struct lcdc_platform_data dtv_pdata = {
3798 .lcdc_power_save = dtv_panel_power,
3799};
3800
3801static struct msm_serial_hs_platform_data msm_uart_dm1_pdata = {
3802 .inject_rx_on_wakeup = 1,
3803 .rx_to_inject = 0xFD,
3804};
3805
3806static struct resource msm_fb_resources[] = {
3807 {
3808 .flags = IORESOURCE_DMA,
3809 }
3810};
3811
3812static int msm_fb_detect_panel(const char *name)
3813{
3814 if (machine_is_msm7x30_fluid()) {
3815 if (!strcmp(name, "lcdc_sharp_wvga_pt"))
3816 return 0;
3817 } else {
3818 if (!strncmp(name, "mddi_toshiba_wvga_pt", 20))
3819 return -EPERM;
3820 else if (!strncmp(name, "lcdc_toshiba_wvga_pt", 20))
3821 return 0;
3822 else if (!strcmp(name, "mddi_orise"))
3823 return -EPERM;
3824 else if (!strcmp(name, "mddi_quickvx"))
3825 return -EPERM;
3826 }
3827 return -ENODEV;
3828}
3829
3830static struct msm_fb_platform_data msm_fb_pdata = {
3831 .detect_client = msm_fb_detect_panel,
3832 .mddi_prescan = 1,
3833};
3834
3835static struct platform_device msm_fb_device = {
3836 .name = "msm_fb",
3837 .id = 0,
3838 .num_resources = ARRAY_SIZE(msm_fb_resources),
3839 .resource = msm_fb_resources,
3840 .dev = {
3841 .platform_data = &msm_fb_pdata,
3842 }
3843};
3844
3845static struct platform_device msm_migrate_pages_device = {
3846 .name = "msm_migrate_pages",
3847 .id = -1,
3848};
3849
3850static struct android_pmem_platform_data android_pmem_adsp_pdata = {
3851 .name = "pmem_adsp",
3852 .allocator_type = PMEM_ALLOCATORTYPE_BITMAP,
3853 .cached = 0,
3854 .memory_type = MEMTYPE_EBI0,
3855};
3856
3857static struct android_pmem_platform_data android_pmem_audio_pdata = {
3858 .name = "pmem_audio",
3859 .allocator_type = PMEM_ALLOCATORTYPE_BITMAP,
3860 .cached = 0,
3861 .memory_type = MEMTYPE_EBI0,
3862};
3863
3864static struct platform_device android_pmem_adsp_device = {
3865 .name = "android_pmem",
3866 .id = 2,
3867 .dev = { .platform_data = &android_pmem_adsp_pdata },
3868};
3869
3870static struct platform_device android_pmem_audio_device = {
3871 .name = "android_pmem",
3872 .id = 4,
3873 .dev = { .platform_data = &android_pmem_audio_pdata },
3874};
3875
3876#if defined(CONFIG_CRYPTO_DEV_QCRYPTO) || \
3877 defined(CONFIG_CRYPTO_DEV_QCRYPTO_MODULE) || \
3878 defined(CONFIG_CRYPTO_DEV_QCEDEV) || \
3879 defined(CONFIG_CRYPTO_DEV_QCEDEV_MODULE)
3880
3881#define QCE_SIZE 0x10000
3882#define QCE_0_BASE 0xA8400000
3883
3884#define QCE_HW_KEY_SUPPORT 1
3885#define QCE_SHA_HMAC_SUPPORT 0
3886#define QCE_SHARE_CE_RESOURCE 0
3887#define QCE_CE_SHARED 0
3888
3889static struct resource qcrypto_resources[] = {
3890 [0] = {
3891 .start = QCE_0_BASE,
3892 .end = QCE_0_BASE + QCE_SIZE - 1,
3893 .flags = IORESOURCE_MEM,
3894 },
3895 [1] = {
3896 .name = "crypto_channels",
3897 .start = DMOV_CE_IN_CHAN,
3898 .end = DMOV_CE_OUT_CHAN,
3899 .flags = IORESOURCE_DMA,
3900 },
3901 [2] = {
3902 .name = "crypto_crci_in",
3903 .start = DMOV_CE_IN_CRCI,
3904 .end = DMOV_CE_IN_CRCI,
3905 .flags = IORESOURCE_DMA,
3906 },
3907 [3] = {
3908 .name = "crypto_crci_out",
3909 .start = DMOV_CE_OUT_CRCI,
3910 .end = DMOV_CE_OUT_CRCI,
3911 .flags = IORESOURCE_DMA,
3912 },
3913 [4] = {
3914 .name = "crypto_crci_hash",
3915 .start = DMOV_CE_HASH_CRCI,
3916 .end = DMOV_CE_HASH_CRCI,
3917 .flags = IORESOURCE_DMA,
3918 },
3919};
3920
3921static struct resource qcedev_resources[] = {
3922 [0] = {
3923 .start = QCE_0_BASE,
3924 .end = QCE_0_BASE + QCE_SIZE - 1,
3925 .flags = IORESOURCE_MEM,
3926 },
3927 [1] = {
3928 .name = "crypto_channels",
3929 .start = DMOV_CE_IN_CHAN,
3930 .end = DMOV_CE_OUT_CHAN,
3931 .flags = IORESOURCE_DMA,
3932 },
3933 [2] = {
3934 .name = "crypto_crci_in",
3935 .start = DMOV_CE_IN_CRCI,
3936 .end = DMOV_CE_IN_CRCI,
3937 .flags = IORESOURCE_DMA,
3938 },
3939 [3] = {
3940 .name = "crypto_crci_out",
3941 .start = DMOV_CE_OUT_CRCI,
3942 .end = DMOV_CE_OUT_CRCI,
3943 .flags = IORESOURCE_DMA,
3944 },
3945 [4] = {
3946 .name = "crypto_crci_hash",
3947 .start = DMOV_CE_HASH_CRCI,
3948 .end = DMOV_CE_HASH_CRCI,
3949 .flags = IORESOURCE_DMA,
3950 },
3951};
3952
3953#endif
3954
3955#if defined(CONFIG_CRYPTO_DEV_QCRYPTO) || \
3956 defined(CONFIG_CRYPTO_DEV_QCRYPTO_MODULE)
3957
3958static struct msm_ce_hw_support qcrypto_ce_hw_suppport = {
3959 .ce_shared = QCE_CE_SHARED,
3960 .shared_ce_resource = QCE_SHARE_CE_RESOURCE,
3961 .hw_key_support = QCE_HW_KEY_SUPPORT,
3962 .sha_hmac = QCE_SHA_HMAC_SUPPORT,
3963};
3964
3965static struct platform_device qcrypto_device = {
3966 .name = "qcrypto",
3967 .id = 0,
3968 .num_resources = ARRAY_SIZE(qcrypto_resources),
3969 .resource = qcrypto_resources,
3970 .dev = {
3971 .coherent_dma_mask = DMA_BIT_MASK(32),
3972 .platform_data = &qcrypto_ce_hw_suppport,
3973 },
3974};
3975#endif
3976
3977#if defined(CONFIG_CRYPTO_DEV_QCEDEV) || \
3978 defined(CONFIG_CRYPTO_DEV_QCEDEV_MODULE)
3979
3980static struct msm_ce_hw_support qcedev_ce_hw_suppport = {
3981 .ce_shared = QCE_CE_SHARED,
3982 .shared_ce_resource = QCE_SHARE_CE_RESOURCE,
3983 .hw_key_support = QCE_HW_KEY_SUPPORT,
3984 .sha_hmac = QCE_SHA_HMAC_SUPPORT,
3985};
3986static struct platform_device qcedev_device = {
3987 .name = "qce",
3988 .id = 0,
3989 .num_resources = ARRAY_SIZE(qcedev_resources),
3990 .resource = qcedev_resources,
3991 .dev = {
3992 .coherent_dma_mask = DMA_BIT_MASK(32),
3993 .platform_data = &qcedev_ce_hw_suppport,
3994 },
3995};
3996#endif
3997
3998static int mddi_toshiba_pmic_bl(int level)
3999{
4000 int ret = -EPERM;
4001
4002 ret = pmic_set_led_intensity(LED_LCD, level);
4003
4004 if (ret)
4005 printk(KERN_WARNING "%s: can't set lcd backlight!\n",
4006 __func__);
4007 return ret;
4008}
4009
4010static struct msm_panel_common_pdata mddi_toshiba_pdata = {
4011 .pmic_backlight = mddi_toshiba_pmic_bl,
4012};
4013
4014static struct platform_device mddi_toshiba_device = {
4015 .name = "mddi_toshiba",
4016 .id = 0,
4017 .dev = {
4018 .platform_data = &mddi_toshiba_pdata,
4019 }
4020};
4021
4022static unsigned wega_reset_gpio =
4023 GPIO_CFG(180, 0, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA);
4024
4025static struct msm_gpio fluid_vee_reset_gpio[] = {
4026 { GPIO_CFG(20, 0, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "vee_reset" },
4027};
4028
4029static unsigned char quickvx_mddi_client = 1, other_mddi_client = 1;
4030static unsigned char quickvx_ldo_enabled;
4031
4032static unsigned quickvx_vlp_gpio =
4033 GPIO_CFG(97, 0, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA);
4034
4035static struct pm8058_gpio pmic_quickvx_clk_gpio = {
4036 .direction = PM_GPIO_DIR_OUT,
4037 .output_buffer = PM_GPIO_OUT_BUF_CMOS,
4038 .output_value = 1,
4039 .pull = PM_GPIO_PULL_NO,
4040 .vin_sel = PM_GPIO_VIN_S3,
4041 .out_strength = PM_GPIO_STRENGTH_HIGH,
4042 .function = PM_GPIO_FUNC_2,
4043};
4044
4045static int display_common_power(int on)
4046{
4047 int rc = 0, flag_on = !!on;
4048 static int display_common_power_save_on;
4049 struct vreg *vreg_ldo12, *vreg_ldo15 = NULL, *vreg_ldo6;
4050 struct vreg *vreg_ldo20, *vreg_ldo16, *vreg_ldo8 = NULL;
4051
4052 if (display_common_power_save_on == flag_on)
4053 return 0;
4054
4055 display_common_power_save_on = flag_on;
4056
4057 if (on) {
4058 /* reset Toshiba WeGA chip -- toggle reset pin -- gpio_180 */
4059 rc = gpio_tlmm_config(wega_reset_gpio, GPIO_CFG_ENABLE);
4060 if (rc) {
4061 pr_err("%s: gpio_tlmm_config(%#x)=%d\n",
4062 __func__, wega_reset_gpio, rc);
4063 return rc;
4064 }
4065
4066 /* bring reset line low to hold reset*/
4067 gpio_set_value(180, 0);
4068
4069 if (quickvx_mddi_client) {
4070 /* QuickVX chip -- VLP pin -- gpio 97 */
4071 rc = gpio_tlmm_config(quickvx_vlp_gpio,
4072 GPIO_CFG_ENABLE);
4073 if (rc) {
4074 pr_err("%s: gpio_tlmm_config(%#x)=%d\n",
4075 __func__, quickvx_vlp_gpio, rc);
4076 return rc;
4077 }
4078
4079 /* bring QuickVX VLP line low */
4080 gpio_set_value(97, 0);
4081
4082 rc = pm8058_gpio_config(PMIC_GPIO_QUICKVX_CLK,
4083 &pmic_quickvx_clk_gpio);
4084 if (rc) {
4085 pr_err("%s: pm8058_gpio_config(%#x)=%d\n",
4086 __func__, PMIC_GPIO_QUICKVX_CLK + 1,
4087 rc);
4088 return rc;
4089 }
4090
4091 gpio_set_value_cansleep(PM8058_GPIO_PM_TO_SYS(
4092 PMIC_GPIO_QUICKVX_CLK), 0);
4093 }
4094 }
4095
4096 /* Toshiba WeGA power -- has 3 power source */
4097 /* 1.5V -- LDO20*/
4098 vreg_ldo20 = vreg_get(NULL, "gp13");
4099
4100 if (IS_ERR(vreg_ldo20)) {
4101 rc = PTR_ERR(vreg_ldo20);
4102 pr_err("%s: gp13 vreg get failed (%d)\n",
4103 __func__, rc);
4104 return rc;
4105 }
4106
4107 /* 1.8V -- LDO12 */
4108 vreg_ldo12 = vreg_get(NULL, "gp9");
4109
4110 if (IS_ERR(vreg_ldo12)) {
4111 rc = PTR_ERR(vreg_ldo12);
4112 pr_err("%s: gp9 vreg get failed (%d)\n",
4113 __func__, rc);
4114 return rc;
4115 }
4116
4117 /* 2.6V -- LDO16 */
4118 vreg_ldo16 = vreg_get(NULL, "gp10");
4119
4120 if (IS_ERR(vreg_ldo16)) {
4121 rc = PTR_ERR(vreg_ldo16);
4122 pr_err("%s: gp10 vreg get failed (%d)\n",
4123 __func__, rc);
4124 return rc;
4125 }
4126
4127 /* 3.075V -- LDO6 */
4128 vreg_ldo6 = vreg_get(NULL, "usb");
4129
4130 if (IS_ERR(vreg_ldo6)) {
4131 rc = PTR_ERR(vreg_ldo6);
4132 pr_err("%s: usb vreg get failed (%d)\n",
4133 __func__, rc);
4134 return rc;
4135 }
4136
4137 if (machine_is_msm7x30_fluid()) {
4138 /* 1.8V -- LDO8 */
4139 vreg_ldo8 = vreg_get(NULL, "gp7");
4140
4141 if (IS_ERR(vreg_ldo8)) {
4142 rc = PTR_ERR(vreg_ldo8);
4143 pr_err("%s: gp7 vreg get failed (%d)\n",
4144 __func__, rc);
4145 return rc;
4146 }
4147 } else {
4148 /* lcd panel power */
4149 /* 3.1V -- LDO15 */
4150 vreg_ldo15 = vreg_get(NULL, "gp6");
4151
4152 if (IS_ERR(vreg_ldo15)) {
4153 rc = PTR_ERR(vreg_ldo15);
4154 pr_err("%s: gp6 vreg get failed (%d)\n",
4155 __func__, rc);
4156 return rc;
4157 }
4158 }
4159
4160 /* For QuickLogic chip, LDO20 requires 1.8V */
4161 /* Toshiba chip requires 1.5V, but can tolerate 1.8V since max is 3V */
4162 if (quickvx_mddi_client)
4163 rc = vreg_set_level(vreg_ldo20, 1800);
4164 else
4165 rc = vreg_set_level(vreg_ldo20, 1500);
4166 if (rc) {
4167 pr_err("%s: vreg LDO20 set level failed (%d)\n",
4168 __func__, rc);
4169 return rc;
4170 }
4171
4172 rc = vreg_set_level(vreg_ldo12, 1800);
4173 if (rc) {
4174 pr_err("%s: vreg LDO12 set level failed (%d)\n",
4175 __func__, rc);
4176 return rc;
4177 }
4178
4179 if (other_mddi_client) {
4180 rc = vreg_set_level(vreg_ldo16, 2600);
4181 if (rc) {
4182 pr_err("%s: vreg LDO16 set level failed (%d)\n",
4183 __func__, rc);
4184 return rc;
4185 }
4186 }
4187
4188 if (quickvx_mddi_client) {
4189 rc = vreg_set_level(vreg_ldo6, 3075);
4190 if (rc) {
4191 pr_err("%s: vreg LDO6 set level failed (%d)\n",
4192 __func__, rc);
4193 return rc;
4194 }
4195 }
4196
4197 if (machine_is_msm7x30_fluid()) {
4198 rc = vreg_set_level(vreg_ldo8, 1800);
4199 if (rc) {
4200 pr_err("%s: vreg LDO8 set level failed (%d)\n",
4201 __func__, rc);
4202 return rc;
4203 }
4204 } else {
4205 rc = vreg_set_level(vreg_ldo15, 3100);
4206 if (rc) {
4207 pr_err("%s: vreg LDO15 set level failed (%d)\n",
4208 __func__, rc);
4209 return rc;
4210 }
4211 }
4212
4213 if (on) {
4214 rc = vreg_enable(vreg_ldo20);
4215 if (rc) {
4216 pr_err("%s: LDO20 vreg enable failed (%d)\n",
4217 __func__, rc);
4218 return rc;
4219 }
4220
4221 rc = vreg_enable(vreg_ldo12);
4222 if (rc) {
4223 pr_err("%s: LDO12 vreg enable failed (%d)\n",
4224 __func__, rc);
4225 return rc;
4226 }
4227
4228 if (other_mddi_client) {
4229 rc = vreg_enable(vreg_ldo16);
4230 if (rc) {
4231 pr_err("%s: LDO16 vreg enable failed (%d)\n",
4232 __func__, rc);
4233 return rc;
4234 }
4235 }
4236
4237 if (quickvx_mddi_client && quickvx_ldo_enabled) {
4238 /* Disable LDO6 during display ON */
4239 rc = vreg_disable(vreg_ldo6);
4240 if (rc) {
4241 pr_err("%s: LDO6 vreg disable failed (%d)\n",
4242 __func__, rc);
4243 return rc;
4244 }
4245 quickvx_ldo_enabled = 0;
4246 }
4247
4248 if (machine_is_msm7x30_fluid()) {
4249 rc = vreg_enable(vreg_ldo8);
4250 if (rc) {
4251 pr_err("%s: LDO8 vreg enable failed (%d)\n",
4252 __func__, rc);
4253 return rc;
4254 }
4255 } else {
4256 rc = vreg_enable(vreg_ldo15);
4257 if (rc) {
4258 pr_err("%s: LDO15 vreg enable failed (%d)\n",
4259 __func__, rc);
4260 return rc;
4261 }
4262 }
4263
4264 mdelay(5); /* ensure power is stable */
4265
4266 if (machine_is_msm7x30_fluid()) {
4267 rc = msm_gpios_request_enable(fluid_vee_reset_gpio,
4268 ARRAY_SIZE(fluid_vee_reset_gpio));
4269 if (rc)
4270 pr_err("%s gpio_request_enable failed rc=%d\n",
4271 __func__, rc);
4272 else {
4273 /* assert vee reset_n */
4274 gpio_set_value(20, 1);
4275 gpio_set_value(20, 0);
4276 mdelay(1);
4277 gpio_set_value(20, 1);
4278 }
4279 }
4280
4281 gpio_set_value(180, 1); /* bring reset line high */
4282 mdelay(10); /* 10 msec before IO can be accessed */
4283
4284 if (quickvx_mddi_client) {
4285 gpio_set_value(97, 1);
4286 msleep(2);
4287 gpio_set_value_cansleep(PM8058_GPIO_PM_TO_SYS(
4288 PMIC_GPIO_QUICKVX_CLK), 1);
4289 msleep(2);
4290 }
4291
4292 rc = pmapp_display_clock_config(1);
4293 if (rc) {
4294 pr_err("%s pmapp_display_clock_config rc=%d\n",
4295 __func__, rc);
4296 return rc;
4297 }
4298
4299 } else {
4300 rc = vreg_disable(vreg_ldo20);
4301 if (rc) {
4302 pr_err("%s: LDO20 vreg disable failed (%d)\n",
4303 __func__, rc);
4304 return rc;
4305 }
4306
4307
4308 if (other_mddi_client) {
4309 rc = vreg_disable(vreg_ldo16);
4310 if (rc) {
4311 pr_err("%s: LDO16 vreg disable failed (%d)\n",
4312 __func__, rc);
4313 return rc;
4314 }
4315 }
4316
4317 if (quickvx_mddi_client && !quickvx_ldo_enabled) {
4318 /* Enable LDO6 during display OFF for
4319 Quicklogic chip to sleep with data retention */
4320 rc = vreg_enable(vreg_ldo6);
4321 if (rc) {
4322 pr_err("%s: LDO6 vreg enable failed (%d)\n",
4323 __func__, rc);
4324 return rc;
4325 }
4326 quickvx_ldo_enabled = 1;
4327 }
4328
4329 gpio_set_value(180, 0); /* bring reset line low */
4330
4331 if (quickvx_mddi_client) {
4332 gpio_set_value(97, 0);
4333 gpio_set_value_cansleep(PM8058_GPIO_PM_TO_SYS(
4334 PMIC_GPIO_QUICKVX_CLK), 0);
4335 }
4336
4337 if (machine_is_msm7x30_fluid()) {
4338 rc = vreg_disable(vreg_ldo8);
4339 if (rc) {
4340 pr_err("%s: LDO8 vreg disable failed (%d)\n",
4341 __func__, rc);
4342 return rc;
4343 }
4344 } else {
4345 rc = vreg_disable(vreg_ldo15);
4346 if (rc) {
4347 pr_err("%s: LDO15 vreg disable failed (%d)\n",
4348 __func__, rc);
4349 return rc;
4350 }
4351 }
4352
4353 mdelay(5); /* ensure power is stable */
4354
4355 rc = vreg_disable(vreg_ldo12);
4356 if (rc) {
4357 pr_err("%s: LDO12 vreg disable failed (%d)\n",
4358 __func__, rc);
4359 return rc;
4360 }
4361
4362 if (machine_is_msm7x30_fluid()) {
4363 msm_gpios_disable_free(fluid_vee_reset_gpio,
4364 ARRAY_SIZE(fluid_vee_reset_gpio));
4365 }
4366
4367 rc = pmapp_display_clock_config(0);
4368 if (rc) {
4369 pr_err("%s pmapp_display_clock_config rc=%d\n",
4370 __func__, rc);
4371 return rc;
4372 }
4373 }
4374
4375 return rc;
4376}
4377
4378static int msm_fb_mddi_sel_clk(u32 *clk_rate)
4379{
4380 *clk_rate *= 2;
4381 return 0;
4382}
4383
4384static int msm_fb_mddi_client_power(u32 client_id)
4385{
4386 struct vreg *vreg_ldo20, *vreg_ldo16;
4387 int rc;
4388
4389 printk(KERN_NOTICE "\n client_id = 0x%x", client_id);
4390 /* Check if it is Quicklogic client */
4391 if (client_id == 0xc5835800) {
4392 printk(KERN_NOTICE "\n Quicklogic MDDI client");
4393 other_mddi_client = 0;
4394 vreg_ldo16 = vreg_get(NULL, "gp10");
4395
4396 if (IS_ERR(vreg_ldo16)) {
4397 rc = PTR_ERR(vreg_ldo16);
4398 pr_err("%s: gp10 vreg get failed (%d)\n",
4399 __func__, rc);
4400 return rc;
4401 }
4402
4403 rc = vreg_disable(vreg_ldo16);
4404 if (rc) {
4405 pr_err("%s: LDO16 vreg enable failed (%d)\n",
4406 __func__, rc);
4407 return rc;
4408 }
4409 } else {
4410 printk(KERN_NOTICE "\n Non-Quicklogic MDDI client");
4411 quickvx_mddi_client = 0;
4412 gpio_set_value(97, 0);
4413 gpio_set_value_cansleep(PM8058_GPIO_PM_TO_SYS(
4414 PMIC_GPIO_QUICKVX_CLK), 0);
4415
4416 vreg_ldo20 = vreg_get(NULL, "gp13");
4417
4418 if (IS_ERR(vreg_ldo20)) {
4419 rc = PTR_ERR(vreg_ldo20);
4420 pr_err("%s: gp13 vreg get failed (%d)\n",
4421 __func__, rc);
4422 return rc;
4423 }
4424 rc = vreg_set_level(vreg_ldo20, 1500);
4425 if (rc) {
4426 pr_err("%s: vreg LDO20 set level failed (%d)\n",
4427 __func__, rc);
4428 return rc;
4429 }
4430 }
4431 return 0;
4432}
4433
4434static struct mddi_platform_data mddi_pdata = {
4435 .mddi_power_save = display_common_power,
4436 .mddi_sel_clk = msm_fb_mddi_sel_clk,
4437 .mddi_client_power = msm_fb_mddi_client_power,
4438};
4439
4440int mdp_core_clk_rate_table[] = {
4441 122880000,
4442 122880000,
Pradeep Jilagam3cc12f92011-07-26 22:25:18 +05304443 192000000,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004444 192000000,
4445};
4446
4447static struct msm_panel_common_pdata mdp_pdata = {
4448 .hw_revision_addr = 0xac001270,
4449 .gpio = 30,
4450 .mdp_core_clk_rate = 122880000,
4451 .mdp_core_clk_table = mdp_core_clk_rate_table,
4452 .num_mdp_clk = ARRAY_SIZE(mdp_core_clk_rate_table),
Ravishangar Kalyanam07ef7882011-08-09 15:50:48 -07004453 .mdp_rev = MDP_REV_40,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07004454};
4455
4456static int lcd_panel_spi_gpio_num[] = {
4457 45, /* spi_clk */
4458 46, /* spi_cs */
4459 47, /* spi_mosi */
4460 48, /* spi_miso */
4461 };
4462
4463static struct msm_gpio lcd_panel_gpios[] = {
4464/* Workaround, since HDMI_INT is using the same GPIO line (18), and is used as
4465 * input. if there is a hardware revision; we should reassign this GPIO to a
4466 * new open line; and removing it will just ensure that this will be missed in
4467 * the future.
4468 { GPIO_CFG(18, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "lcdc_grn0" },
4469 */
4470 { GPIO_CFG(19, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "lcdc_grn1" },
4471 { GPIO_CFG(20, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "lcdc_blu0" },
4472 { GPIO_CFG(21, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "lcdc_blu1" },
4473 { GPIO_CFG(22, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "lcdc_blu2" },
4474 { GPIO_CFG(23, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "lcdc_red0" },
4475 { GPIO_CFG(24, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "lcdc_red1" },
4476 { GPIO_CFG(25, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "lcdc_red2" },
4477#ifndef CONFIG_SPI_QSD
4478 { GPIO_CFG(45, 0, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "spi_clk" },
4479 { GPIO_CFG(46, 0, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "spi_cs0" },
4480 { GPIO_CFG(47, 0, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "spi_mosi" },
4481 { GPIO_CFG(48, 0, GPIO_CFG_INPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "spi_miso" },
4482#endif
4483 { GPIO_CFG(90, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "lcdc_pclk" },
4484 { GPIO_CFG(91, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "lcdc_en" },
4485 { GPIO_CFG(92, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "lcdc_vsync" },
4486 { GPIO_CFG(93, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "lcdc_hsync" },
4487 { GPIO_CFG(94, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "lcdc_grn2" },
4488 { GPIO_CFG(95, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "lcdc_grn3" },
4489 { GPIO_CFG(96, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "lcdc_grn4" },
4490 { GPIO_CFG(97, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "lcdc_grn5" },
4491 { GPIO_CFG(98, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "lcdc_grn6" },
4492 { GPIO_CFG(99, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "lcdc_grn7" },
4493 { GPIO_CFG(100, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "lcdc_blu3" },
4494 { GPIO_CFG(101, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "lcdc_blu4" },
4495 { GPIO_CFG(102, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "lcdc_blu5" },
4496 { GPIO_CFG(103, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "lcdc_blu6" },
4497 { GPIO_CFG(104, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "lcdc_blu7" },
4498 { GPIO_CFG(105, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "lcdc_red3" },
4499 { GPIO_CFG(106, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "lcdc_red4" },
4500 { GPIO_CFG(107, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "lcdc_red5" },
4501 { GPIO_CFG(108, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "lcdc_red6" },
4502 { GPIO_CFG(109, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "lcdc_red7" },
4503};
4504
4505static struct msm_gpio lcd_sharp_panel_gpios[] = {
4506 { GPIO_CFG(22, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "lcdc_blu2" },
4507 { GPIO_CFG(25, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "lcdc_red2" },
4508 { GPIO_CFG(90, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "lcdc_pclk" },
4509 { GPIO_CFG(91, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "lcdc_en" },
4510 { GPIO_CFG(92, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "lcdc_vsync" },
4511 { GPIO_CFG(93, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "lcdc_hsync" },
4512 { GPIO_CFG(94, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "lcdc_grn2" },
4513 { GPIO_CFG(95, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "lcdc_grn3" },
4514 { GPIO_CFG(96, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "lcdc_grn4" },
4515 { GPIO_CFG(97, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "lcdc_grn5" },
4516 { GPIO_CFG(98, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "lcdc_grn6" },
4517 { GPIO_CFG(99, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "lcdc_grn7" },
4518 { GPIO_CFG(100, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "lcdc_blu3" },
4519 { GPIO_CFG(101, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "lcdc_blu4" },
4520 { GPIO_CFG(102, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "lcdc_blu5" },
4521 { GPIO_CFG(103, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "lcdc_blu6" },
4522 { GPIO_CFG(104, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "lcdc_blu7" },
4523 { GPIO_CFG(105, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "lcdc_red3" },
4524 { GPIO_CFG(106, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "lcdc_red4" },
4525 { GPIO_CFG(107, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "lcdc_red5" },
4526 { GPIO_CFG(108, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "lcdc_red6" },
4527 { GPIO_CFG(109, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "lcdc_red7" },
4528};
4529
4530static int lcdc_toshiba_panel_power(int on)
4531{
4532 int rc, i;
4533 struct msm_gpio *gp;
4534
4535 rc = display_common_power(on);
4536 if (rc < 0) {
4537 printk(KERN_ERR "%s display_common_power failed: %d\n",
4538 __func__, rc);
4539 return rc;
4540 }
4541
4542 if (on) {
4543 rc = msm_gpios_enable(lcd_panel_gpios,
4544 ARRAY_SIZE(lcd_panel_gpios));
4545 if (rc < 0) {
4546 printk(KERN_ERR "%s: gpio enable failed: %d\n",
4547 __func__, rc);
4548 }
4549 } else { /* off */
4550 gp = lcd_panel_gpios;
4551 for (i = 0; i < ARRAY_SIZE(lcd_panel_gpios); i++) {
4552 /* ouput low */
4553 gpio_set_value(GPIO_PIN(gp->gpio_cfg), 0);
4554 gp++;
4555 }
4556 }
4557
4558 return rc;
4559}
4560
4561static int lcdc_sharp_panel_power(int on)
4562{
4563 int rc, i;
4564 struct msm_gpio *gp;
4565
4566 rc = display_common_power(on);
4567 if (rc < 0) {
4568 printk(KERN_ERR "%s display_common_power failed: %d\n",
4569 __func__, rc);
4570 return rc;
4571 }
4572
4573 if (on) {
4574 rc = msm_gpios_enable(lcd_sharp_panel_gpios,
4575 ARRAY_SIZE(lcd_sharp_panel_gpios));
4576 if (rc < 0) {
4577 printk(KERN_ERR "%s: gpio enable failed: %d\n",
4578 __func__, rc);
4579 }
4580 } else { /* off */
4581 gp = lcd_sharp_panel_gpios;
4582 for (i = 0; i < ARRAY_SIZE(lcd_sharp_panel_gpios); i++) {
4583 /* ouput low */
4584 gpio_set_value(GPIO_PIN(gp->gpio_cfg), 0);
4585 gp++;
4586 }
4587 }
4588
4589 return rc;
4590}
4591
4592static int lcdc_panel_power(int on)
4593{
4594 int flag_on = !!on;
4595 static int lcdc_power_save_on;
4596
4597 if (lcdc_power_save_on == flag_on)
4598 return 0;
4599
4600 lcdc_power_save_on = flag_on;
4601 quickvx_mddi_client = 0;
4602
4603 if (machine_is_msm7x30_fluid())
4604 return lcdc_sharp_panel_power(on);
4605 else
4606 return lcdc_toshiba_panel_power(on);
4607}
4608
4609static struct lcdc_platform_data lcdc_pdata = {
4610 .lcdc_power_save = lcdc_panel_power,
4611};
4612
4613static int atv_dac_power(int on)
4614{
4615 int rc = 0;
4616 struct vreg *vreg_s4, *vreg_ldo9;
4617
4618 vreg_s4 = vreg_get(NULL, "s4");
4619 if (IS_ERR(vreg_s4)) {
4620 rc = PTR_ERR(vreg_s4);
4621 pr_err("%s: s4 vreg get failed (%d)\n",
4622 __func__, rc);
4623 return -1;
4624 }
4625 vreg_ldo9 = vreg_get(NULL, "gp1");
4626 if (IS_ERR(vreg_ldo9)) {
4627 rc = PTR_ERR(vreg_ldo9);
4628 pr_err("%s: ldo9 vreg get failed (%d)\n",
4629 __func__, rc);
4630 return rc;
4631 }
4632
4633 if (on) {
4634 rc = vreg_enable(vreg_s4);
4635 if (rc) {
4636 pr_err("%s: s4 vreg enable failed (%d)\n",
4637 __func__, rc);
4638 return rc;
4639 }
4640 rc = vreg_enable(vreg_ldo9);
4641 if (rc) {
4642 pr_err("%s: ldo9 vreg enable failed (%d)\n",
4643 __func__, rc);
4644 return rc;
4645 }
4646 } else {
4647 rc = vreg_disable(vreg_ldo9);
4648 if (rc) {
4649 pr_err("%s: ldo9 vreg disable failed (%d)\n",
4650 __func__, rc);
4651 return rc;
4652 }
4653 rc = vreg_disable(vreg_s4);
4654 if (rc) {
4655 pr_err("%s: s4 vreg disable failed (%d)\n",
4656 __func__, rc);
4657 return rc;
4658 }
4659 }
4660 return rc;
4661}
4662
4663static struct tvenc_platform_data atv_pdata = {
4664 .poll = 1,
4665 .pm_vid_en = atv_dac_power,
4666};
4667
4668static void __init msm_fb_add_devices(void)
4669{
4670 msm_fb_register_device("mdp", &mdp_pdata);
4671 msm_fb_register_device("pmdh", &mddi_pdata);
4672 msm_fb_register_device("lcdc", &lcdc_pdata);
4673 msm_fb_register_device("dtv", &dtv_pdata);
4674 msm_fb_register_device("tvenc", &atv_pdata);
4675#ifdef CONFIG_FB_MSM_TVOUT
4676 msm_fb_register_device("tvout_device", NULL);
4677#endif
4678}
4679
4680static struct msm_panel_common_pdata lcdc_toshiba_panel_data = {
4681 .gpio_num = lcd_panel_spi_gpio_num,
4682};
4683
4684static struct platform_device lcdc_toshiba_panel_device = {
4685 .name = "lcdc_toshiba_wvga",
4686 .id = 0,
4687 .dev = {
4688 .platform_data = &lcdc_toshiba_panel_data,
4689 }
4690};
4691
4692#if defined(CONFIG_MARIMBA_CORE) && \
4693 (defined(CONFIG_MSM_BT_POWER) || defined(CONFIG_MSM_BT_POWER_MODULE))
4694static struct platform_device msm_bt_power_device = {
4695 .name = "bt_power",
4696 .id = -1
4697};
4698
4699enum {
4700 BT_RFR,
4701 BT_CTS,
4702 BT_RX,
4703 BT_TX,
4704};
4705
4706static struct msm_gpio bt_config_power_on[] = {
4707 { GPIO_CFG(134, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA),
4708 "UART1DM_RFR" },
4709 { GPIO_CFG(135, 1, GPIO_CFG_INPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA),
4710 "UART1DM_CTS" },
4711 { GPIO_CFG(136, 1, GPIO_CFG_INPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA),
4712 "UART1DM_Rx" },
4713 { GPIO_CFG(137, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA),
4714 "UART1DM_Tx" }
4715};
4716
4717static struct msm_gpio bt_config_power_off[] = {
4718 { GPIO_CFG(134, 0, GPIO_CFG_INPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA),
4719 "UART1DM_RFR" },
4720 { GPIO_CFG(135, 0, GPIO_CFG_INPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA),
4721 "UART1DM_CTS" },
4722 { GPIO_CFG(136, 0, GPIO_CFG_INPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA),
4723 "UART1DM_Rx" },
4724 { GPIO_CFG(137, 0, GPIO_CFG_INPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA),
4725 "UART1DM_Tx" }
4726};
4727
4728static const char *vregs_bt_marimba_name[] = {
4729 "s3",
4730 "s2",
4731 "gp16",
4732 "wlan"
4733};
4734static struct vreg *vregs_bt_marimba[ARRAY_SIZE(vregs_bt_marimba_name)];
4735
4736static const char *vregs_bt_bahama_name[] = {
4737 "s3",
4738 "usb2",
4739 "s2",
4740 "wlan"
4741};
4742static struct vreg *vregs_bt_bahama[ARRAY_SIZE(vregs_bt_bahama_name)];
4743
4744static u8 bahama_version;
4745
4746static int marimba_bt(int on)
4747{
4748 int rc;
4749 int i;
4750 struct marimba config = { .mod_id = MARIMBA_SLAVE_ID_MARIMBA };
4751
4752 struct marimba_config_register {
4753 u8 reg;
4754 u8 value;
4755 u8 mask;
4756 };
4757
4758 struct marimba_variant_register {
4759 const size_t size;
4760 const struct marimba_config_register *set;
4761 };
4762
4763 const struct marimba_config_register *p;
4764
4765 u8 version;
4766
4767 const struct marimba_config_register v10_bt_on[] = {
4768 { 0xE5, 0x0B, 0x0F },
4769 { 0x05, 0x02, 0x07 },
4770 { 0x06, 0x88, 0xFF },
4771 { 0xE7, 0x21, 0x21 },
4772 { 0xE3, 0x38, 0xFF },
4773 { 0xE4, 0x06, 0xFF },
4774 };
4775
4776 const struct marimba_config_register v10_bt_off[] = {
4777 { 0xE5, 0x0B, 0x0F },
4778 { 0x05, 0x08, 0x0F },
4779 { 0x06, 0x88, 0xFF },
4780 { 0xE7, 0x00, 0x21 },
4781 { 0xE3, 0x00, 0xFF },
4782 { 0xE4, 0x00, 0xFF },
4783 };
4784
4785 const struct marimba_config_register v201_bt_on[] = {
4786 { 0x05, 0x08, 0x07 },
4787 { 0x06, 0x88, 0xFF },
4788 { 0xE7, 0x21, 0x21 },
4789 { 0xE3, 0x38, 0xFF },
4790 { 0xE4, 0x06, 0xFF },
4791 };
4792
4793 const struct marimba_config_register v201_bt_off[] = {
4794 { 0x05, 0x08, 0x07 },
4795 { 0x06, 0x88, 0xFF },
4796 { 0xE7, 0x00, 0x21 },
4797 { 0xE3, 0x00, 0xFF },
4798 { 0xE4, 0x00, 0xFF },
4799 };
4800
4801 const struct marimba_config_register v210_bt_on[] = {
4802 { 0xE9, 0x01, 0x01 },
4803 { 0x06, 0x88, 0xFF },
4804 { 0xE7, 0x21, 0x21 },
4805 { 0xE3, 0x38, 0xFF },
4806 { 0xE4, 0x06, 0xFF },
4807 };
4808
4809 const struct marimba_config_register v210_bt_off[] = {
4810 { 0x06, 0x88, 0xFF },
4811 { 0xE7, 0x00, 0x21 },
4812 { 0xE9, 0x00, 0x01 },
4813 { 0xE3, 0x00, 0xFF },
4814 { 0xE4, 0x00, 0xFF },
4815 };
4816
4817 const struct marimba_variant_register bt_marimba[2][4] = {
4818 {
4819 { ARRAY_SIZE(v10_bt_off), v10_bt_off },
4820 { 0, NULL },
4821 { ARRAY_SIZE(v201_bt_off), v201_bt_off },
4822 { ARRAY_SIZE(v210_bt_off), v210_bt_off }
4823 },
4824 {
4825 { ARRAY_SIZE(v10_bt_on), v10_bt_on },
4826 { 0, NULL },
4827 { ARRAY_SIZE(v201_bt_on), v201_bt_on },
4828 { ARRAY_SIZE(v210_bt_on), v210_bt_on }
4829 }
4830 };
4831
4832 on = on ? 1 : 0;
4833
4834 rc = marimba_read_bit_mask(&config, 0x11, &version, 1, 0x1F);
4835 if (rc < 0) {
4836 printk(KERN_ERR
4837 "%s: version read failed: %d\n",
4838 __func__, rc);
4839 return rc;
4840 }
4841
4842 if ((version >= ARRAY_SIZE(bt_marimba[on])) ||
4843 (bt_marimba[on][version].size == 0)) {
4844 printk(KERN_ERR
4845 "%s: unsupported version\n",
4846 __func__);
4847 return -EIO;
4848 }
4849
4850 p = bt_marimba[on][version].set;
4851
4852 printk(KERN_INFO "%s: found version %d\n", __func__, version);
4853
4854 for (i = 0; i < bt_marimba[on][version].size; i++) {
4855 u8 value = (p+i)->value;
4856 rc = marimba_write_bit_mask(&config,
4857 (p+i)->reg,
4858 &value,
4859 sizeof((p+i)->value),
4860 (p+i)->mask);
4861 if (rc < 0) {
4862 printk(KERN_ERR
4863 "%s: reg %d write failed: %d\n",
4864 __func__, (p+i)->reg, rc);
4865 return rc;
4866 }
4867 printk(KERN_INFO "%s: reg 0x%02x value 0x%02x mask 0x%02x\n",
4868 __func__, (p+i)->reg,
4869 value, (p+i)->mask);
4870 }
4871 return 0;
4872}
4873
4874static int bahama_bt(int on)
4875{
4876 int rc;
4877 int i;
4878 struct marimba config = { .mod_id = SLAVE_ID_BAHAMA };
4879
4880 struct bahama_variant_register {
4881 const size_t size;
4882 const struct bahama_config_register *set;
4883 };
4884
4885 const struct bahama_config_register *p;
4886
4887
4888 const struct bahama_config_register v10_bt_on[] = {
4889 { 0xE9, 0x00, 0xFF },
4890 { 0xF4, 0x80, 0xFF },
4891 { 0xF0, 0x06, 0xFF },
4892 { 0xE4, 0x00, 0xFF },
4893 { 0xE5, 0x00, 0x0F },
4894#ifdef CONFIG_WLAN
4895 { 0xE6, 0x38, 0x7F },
4896 { 0xE7, 0x06, 0xFF },
4897#endif
4898 { 0x11, 0x13, 0xFF },
4899 { 0xE9, 0x21, 0xFF },
4900 { 0x01, 0x0C, 0x1F },
4901 { 0x01, 0x08, 0x1F },
4902 };
4903
4904 const struct bahama_config_register v20_bt_on_fm_off[] = {
4905 { 0x11, 0x0C, 0xFF },
4906 { 0x13, 0x01, 0xFF },
4907 { 0xF4, 0x80, 0xFF },
4908 { 0xF0, 0x00, 0xFF },
4909 { 0xE9, 0x00, 0xFF },
4910#ifdef CONFIG_WLAN
4911 { 0x81, 0x00, 0xFF },
4912 { 0x82, 0x00, 0xFF },
4913 { 0xE6, 0x38, 0x7F },
4914 { 0xE7, 0x06, 0xFF },
4915#endif
4916 { 0xE9, 0x21, 0xFF }
4917 };
4918
4919 const struct bahama_config_register v20_bt_on_fm_on[] = {
4920 { 0x11, 0x0C, 0xFF },
4921 { 0x13, 0x01, 0xFF },
4922 { 0xF4, 0x86, 0xFF },
4923 { 0xF0, 0x06, 0xFF },
4924 { 0xE9, 0x00, 0xFF },
4925#ifdef CONFIG_WLAN
4926 { 0x81, 0x00, 0xFF },
4927 { 0x82, 0x00, 0xFF },
4928 { 0xE6, 0x38, 0x7F },
4929 { 0xE7, 0x06, 0xFF },
4930#endif
4931 { 0xE9, 0x21, 0xFF }
4932 };
4933
4934 const struct bahama_config_register v10_bt_off[] = {
4935 { 0xE9, 0x00, 0xFF },
4936 };
4937
4938 const struct bahama_config_register v20_bt_off_fm_off[] = {
4939 { 0xF4, 0x84, 0xFF },
4940 { 0xF0, 0x04, 0xFF },
4941 { 0xE9, 0x00, 0xFF }
4942 };
4943
4944 const struct bahama_config_register v20_bt_off_fm_on[] = {
4945 { 0xF4, 0x86, 0xFF },
4946 { 0xF0, 0x06, 0xFF },
4947 { 0xE9, 0x00, 0xFF }
4948 };
4949
4950 const struct bahama_variant_register bt_bahama[2][3] = {
4951 {
4952 { ARRAY_SIZE(v10_bt_off), v10_bt_off },
4953 { ARRAY_SIZE(v20_bt_off_fm_off), v20_bt_off_fm_off },
4954 { ARRAY_SIZE(v20_bt_off_fm_on), v20_bt_off_fm_on }
4955 },
4956 {
4957 { ARRAY_SIZE(v10_bt_on), v10_bt_on },
4958 { ARRAY_SIZE(v20_bt_on_fm_off), v20_bt_on_fm_off },
4959 { ARRAY_SIZE(v20_bt_on_fm_on), v20_bt_on_fm_on }
4960 }
4961 };
4962
4963 u8 offset = 0; /* index into bahama configs */
4964
4965 on = on ? 1 : 0;
4966
4967 bahama_version = read_bahama_ver();
4968
4969 if (((int)bahama_version) < 0 ||
4970 bahama_version == VER_UNSUPPORTED) {
4971 dev_err(&msm_bt_power_device.dev,
4972 "%s: i2c failure or unsupported version: %d\n",
4973 __func__, bahama_version);
4974 return -EIO;
4975 }
4976
4977 if (bahama_version == VER_2_0) {
4978 if (marimba_get_fm_status(&config))
4979 offset = 0x01;
4980 }
4981
4982 p = bt_bahama[on][bahama_version + offset].set;
4983
4984 dev_info(&msm_bt_power_device.dev,
4985 "%s: found version %d\n", __func__, bahama_version);
4986
4987 for (i = 0; i < bt_bahama[on][bahama_version + offset].size; i++) {
4988 u8 value = (p+i)->value;
4989 rc = marimba_write_bit_mask(&config,
4990 (p+i)->reg,
4991 &value,
4992 sizeof((p+i)->value),
4993 (p+i)->mask);
4994 if (rc < 0) {
4995 dev_err(&msm_bt_power_device.dev,
4996 "%s: reg %d write failed: %d\n",
4997 __func__, (p+i)->reg, rc);
4998 return rc;
4999 }
5000 dev_info(&msm_bt_power_device.dev,
5001 "%s: reg 0x%02x write value 0x%02x mask 0x%02x\n",
5002 __func__, (p+i)->reg,
5003 value, (p+i)->mask);
5004 }
5005 /* Update BT status */
5006 if (on)
5007 marimba_set_bt_status(&config, true);
5008 else
5009 marimba_set_bt_status(&config, false);
5010
5011 if (bahama_version == VER_2_0 && on) { /* variant of bahama v2 */
5012 /* Disable s2 as bahama v2 uses internal LDO regulator */
5013 for (i = 0; i < ARRAY_SIZE(vregs_bt_bahama_name); i++) {
5014 if (!strcmp(vregs_bt_bahama_name[i], "s2")) {
5015 rc = vreg_disable(vregs_bt_bahama[i]);
5016 if (rc < 0) {
5017 printk(KERN_ERR
5018 "%s: vreg %s disable "
5019 "failed (%d)\n",
5020 __func__,
5021 vregs_bt_bahama_name[i], rc);
5022 return -EIO;
5023 }
5024 rc = pmapp_vreg_level_vote("BTPW",
5025 PMAPP_VREG_S2,
5026 0);
5027 if (rc < 0) {
5028 printk(KERN_ERR "%s: vreg "
5029 "level off failed (%d)\n",
5030 __func__, rc);
5031 return -EIO;
5032 }
5033 printk(KERN_INFO "%s: vreg disable & "
5034 "level off successful (%d)\n",
5035 __func__, rc);
5036 }
5037 }
5038 }
5039
5040 return 0;
5041}
5042
5043static int bluetooth_power_regulators(int on, int bahama_not_marimba)
5044{
5045 int i, rc;
5046 const char **vregs_name;
5047 struct vreg **vregs;
5048 int vregs_size;
5049
5050 if (bahama_not_marimba) {
5051 vregs_name = vregs_bt_bahama_name;
5052 vregs = vregs_bt_bahama;
5053 vregs_size = ARRAY_SIZE(vregs_bt_bahama_name);
5054 } else {
5055 vregs_name = vregs_bt_marimba_name;
5056 vregs = vregs_bt_marimba;
5057 vregs_size = ARRAY_SIZE(vregs_bt_marimba_name);
5058 }
5059
5060 for (i = 0; i < vregs_size; i++) {
5061 if (bahama_not_marimba && (bahama_version == VER_2_0) &&
5062 !on && !strcmp(vregs_bt_bahama_name[i], "s2"))
5063 continue;
5064 rc = on ? vreg_enable(vregs[i]) :
5065 vreg_disable(vregs[i]);
5066 if (rc < 0) {
5067 printk(KERN_ERR "%s: vreg %s %s failed (%d)\n",
5068 __func__, vregs_name[i],
5069 on ? "enable" : "disable", rc);
5070 return -EIO;
5071 }
5072 }
5073 return 0;
5074}
5075
5076static int bluetooth_power(int on)
5077{
5078 int rc;
5079 const char *id = "BTPW";
5080
5081 int bahama_not_marimba = bahama_present();
5082
5083 if (bahama_not_marimba == -1) {
5084 printk(KERN_WARNING "%s: bahama_present: %d\n",
5085 __func__, bahama_not_marimba);
5086 return -ENODEV;
5087 }
5088
5089 if (on) {
5090 rc = pmapp_vreg_level_vote(id, PMAPP_VREG_S2, 1300);
5091 if (rc < 0) {
5092 printk(KERN_ERR "%s: vreg level on failed (%d)\n",
5093 __func__, rc);
5094 return rc;
5095 }
5096
5097 rc = bluetooth_power_regulators(on, bahama_not_marimba);
5098 if (rc < 0)
5099 return -EIO;
5100
5101 rc = pmapp_clock_vote(id, PMAPP_CLOCK_ID_DO,
5102 PMAPP_CLOCK_VOTE_ON);
5103 if (rc < 0)
5104 return -EIO;
5105
5106 if (machine_is_msm8x55_svlte_surf() ||
5107 machine_is_msm8x55_svlte_ffa()) {
5108 rc = marimba_gpio_config(1);
5109 if (rc < 0)
5110 return -EIO;
5111 }
5112
5113 rc = (bahama_not_marimba ? bahama_bt(on) : marimba_bt(on));
5114 if (rc < 0)
5115 return -EIO;
5116
5117 msleep(10);
5118
5119 rc = pmapp_clock_vote(id, PMAPP_CLOCK_ID_DO,
5120 PMAPP_CLOCK_VOTE_PIN_CTRL);
5121 if (rc < 0)
5122 return -EIO;
5123
5124 if (machine_is_msm8x55_svlte_surf() ||
5125 machine_is_msm8x55_svlte_ffa()) {
5126 rc = marimba_gpio_config(0);
5127 if (rc < 0)
5128 return -EIO;
5129 }
5130
5131 rc = msm_gpios_enable(bt_config_power_on,
5132 ARRAY_SIZE(bt_config_power_on));
5133
5134 if (rc < 0)
5135 return rc;
5136
5137 } else {
5138 rc = msm_gpios_enable(bt_config_power_off,
5139 ARRAY_SIZE(bt_config_power_off));
5140 if (rc < 0)
5141 return rc;
5142
5143 /* check for initial RFKILL block (power off) */
5144 if (platform_get_drvdata(&msm_bt_power_device) == NULL)
5145 goto out;
5146
5147 rc = (bahama_not_marimba ? bahama_bt(on) : marimba_bt(on));
5148 if (rc < 0)
5149 return -EIO;
5150
5151 rc = pmapp_clock_vote(id, PMAPP_CLOCK_ID_DO,
5152 PMAPP_CLOCK_VOTE_OFF);
5153 if (rc < 0)
5154 return -EIO;
5155
5156 rc = bluetooth_power_regulators(on, bahama_not_marimba);
5157 if (rc < 0)
5158 return -EIO;
5159
5160 if (bahama_version == VER_1_0) {
5161 rc = pmapp_vreg_level_vote(id, PMAPP_VREG_S2, 0);
5162 if (rc < 0) {
5163 printk(KERN_ERR "%s: vreg level off failed "
5164 "(%d)\n", __func__, rc);
5165 return -EIO;
5166 }
5167 }
5168 }
5169
5170out:
5171 printk(KERN_DEBUG "Bluetooth power switch: %d\n", on);
5172
5173 return 0;
5174}
5175
5176static void __init bt_power_init(void)
5177{
5178 int i;
5179
5180 for (i = 0; i < ARRAY_SIZE(vregs_bt_marimba_name); i++) {
5181 vregs_bt_marimba[i] = vreg_get(NULL, vregs_bt_marimba_name[i]);
5182 if (IS_ERR(vregs_bt_marimba[i])) {
5183 printk(KERN_ERR "%s: vreg get %s failed (%ld)\n",
5184 __func__, vregs_bt_marimba_name[i],
5185 PTR_ERR(vregs_bt_marimba[i]));
5186 return;
5187 }
5188 }
5189
5190 for (i = 0; i < ARRAY_SIZE(vregs_bt_bahama_name); i++) {
5191 vregs_bt_bahama[i] = vreg_get(NULL, vregs_bt_bahama_name[i]);
5192 if (IS_ERR(vregs_bt_bahama[i])) {
5193 printk(KERN_ERR "%s: vreg get %s failed (%ld)\n",
5194 __func__, vregs_bt_bahama_name[i],
5195 PTR_ERR(vregs_bt_bahama[i]));
5196 return;
5197 }
5198 }
5199
5200 msm_bt_power_device.dev.platform_data = &bluetooth_power;
5201}
5202#else
5203#define bt_power_init(x) do {} while (0)
5204#endif
5205
5206static struct msm_psy_batt_pdata msm_psy_batt_data = {
5207 .voltage_min_design = 2800,
5208 .voltage_max_design = 4300,
5209 .avail_chg_sources = AC_CHG | USB_CHG ,
5210 .batt_technology = POWER_SUPPLY_TECHNOLOGY_LION,
5211};
5212
5213static struct platform_device msm_batt_device = {
5214 .name = "msm-battery",
5215 .id = -1,
5216 .dev.platform_data = &msm_psy_batt_data,
5217};
5218
5219static char *msm_adc_fluid_device_names[] = {
5220 "LTC_ADC1",
5221 "LTC_ADC2",
5222 "LTC_ADC3",
5223};
5224
5225static char *msm_adc_surf_device_names[] = {
5226 "XO_ADC",
5227};
5228
5229static struct msm_adc_platform_data msm_adc_pdata;
5230
5231static struct platform_device msm_adc_device = {
5232 .name = "msm_adc",
5233 .id = -1,
5234 .dev = {
5235 .platform_data = &msm_adc_pdata,
5236 },
5237};
5238
5239#ifdef CONFIG_MSM_SDIO_AL
5240static struct msm_gpio mdm2ap_status = {
5241 GPIO_CFG(77, 0, GPIO_CFG_INPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA),
5242 "mdm2ap_status"
5243};
5244
5245
5246static int configure_mdm2ap_status(int on)
5247{
5248 if (on)
5249 return msm_gpios_request_enable(&mdm2ap_status, 1);
5250 else {
5251 msm_gpios_disable_free(&mdm2ap_status, 1);
5252 return 0;
5253 }
5254}
5255
5256static int get_mdm2ap_status(void)
5257{
5258 return gpio_get_value(GPIO_PIN(mdm2ap_status.gpio_cfg));
5259}
5260
5261static struct sdio_al_platform_data sdio_al_pdata = {
5262 .config_mdm2ap_status = configure_mdm2ap_status,
5263 .get_mdm2ap_status = get_mdm2ap_status,
5264 .allow_sdioc_version_major_2 = 1,
5265 .peer_sdioc_version_minor = 0x0001,
5266 .peer_sdioc_version_major = 0x0003,
5267 .peer_sdioc_boot_version_minor = 0x0001,
5268 .peer_sdioc_boot_version_major = 0x0003,
5269};
5270
5271struct platform_device msm_device_sdio_al = {
5272 .name = "msm_sdio_al",
5273 .id = -1,
5274 .dev = {
5275 .platform_data = &sdio_al_pdata,
5276 },
5277};
5278
5279#endif /* CONFIG_MSM_SDIO_AL */
5280
Daniel Walker8d747cd2010-02-25 11:37:43 -08005281static struct platform_device *devices[] __initdata = {
Daniel Walker90e37c52010-05-12 14:24:15 -07005282#if defined(CONFIG_SERIAL_MSM) || defined(CONFIG_MSM_SERIAL_DEBUGGER)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005283 &msm_device_uart2,
5284#endif
Justin Paupore637a25d2011-07-14 17:11:04 -07005285#ifdef CONFIG_MSM_PROC_COMM_REGULATOR
5286 &msm_proccomm_regulator_dev,
5287#endif
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005288 &asoc_msm_pcm,
5289 &asoc_msm_dai0,
5290 &asoc_msm_dai1,
5291#if defined (CONFIG_SND_MSM_MVS_DAI_SOC)
5292 &asoc_msm_mvs,
5293 &asoc_mvs_dai0,
5294 &asoc_mvs_dai1,
Daniel Walker90e37c52010-05-12 14:24:15 -07005295#endif
Niranjana Vishwanathapuraa8855e92010-10-06 13:52:10 -07005296 &msm_device_smd,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005297 &msm_device_dmov,
5298 &smc91x_device,
5299 &smsc911x_device,
5300 &msm_device_nand,
5301#ifdef CONFIG_USB_MSM_OTG_72K
Pavankumar Kondeti5155e2c2010-12-08 13:37:08 +05305302 &msm_device_otg,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005303#ifdef CONFIG_USB_GADGET
5304 &msm_device_gadget_peripheral,
5305#endif
5306#endif
5307#ifdef CONFIG_USB_G_ANDROID
5308 &android_usb_device,
5309#endif
5310 &qsd_device_spi,
Anirudh Ghayal9d9cdc22011-10-10 17:17:07 +05305311
5312#ifdef CONFIG_MSM_SSBI
5313 &msm_device_ssbi_pmic1,
5314#endif
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005315#ifdef CONFIG_I2C_SSBI
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005316 &msm_device_ssbi7,
5317#endif
5318 &android_pmem_device,
5319 &msm_fb_device,
5320 &msm_migrate_pages_device,
5321 &mddi_toshiba_device,
5322 &lcdc_toshiba_panel_device,
5323#ifdef CONFIG_MSM_ROTATOR
5324 &msm_rotator_device,
5325#endif
5326 &lcdc_sharp_panel_device,
5327 &android_pmem_adsp_device,
5328 &android_pmem_audio_device,
5329 &msm_device_i2c,
5330 &msm_device_i2c_2,
5331 &msm_device_uart_dm1,
5332 &hs_device,
5333#ifdef CONFIG_MSM7KV2_AUDIO
5334 &msm_aictl_device,
5335 &msm_mi2s_device,
5336 &msm_lpa_device,
5337 &msm_aux_pcm_device,
5338#endif
5339 &msm_device_adspdec,
5340 &qup_device_i2c,
5341#if defined(CONFIG_MARIMBA_CORE) && \
5342 (defined(CONFIG_MSM_BT_POWER) || defined(CONFIG_MSM_BT_POWER_MODULE))
5343 &msm_bt_power_device,
5344#endif
5345 &msm_kgsl_3d0,
5346 &msm_kgsl_2d0,
5347#ifdef CONFIG_MT9T013
5348 &msm_camera_sensor_mt9t013,
5349#endif
5350#ifdef CONFIG_MT9D112
5351 &msm_camera_sensor_mt9d112,
5352#endif
5353#ifdef CONFIG_WEBCAM_OV9726
5354 &msm_camera_sensor_ov9726,
5355#endif
5356#ifdef CONFIG_S5K3E2FX
5357 &msm_camera_sensor_s5k3e2fx,
5358#endif
5359#ifdef CONFIG_MT9P012
5360 &msm_camera_sensor_mt9p012,
5361#endif
5362#ifdef CONFIG_MT9E013
5363 &msm_camera_sensor_mt9e013,
5364#endif
5365#ifdef CONFIG_VX6953
5366 &msm_camera_sensor_vx6953,
5367#endif
5368#ifdef CONFIG_SN12M0PZ
5369 &msm_camera_sensor_sn12m0pz,
5370#endif
5371 &msm_device_vidc_720p,
5372#ifdef CONFIG_MSM_GEMINI
5373 &msm_gemini_device,
5374#endif
5375#ifdef CONFIG_MSM_VPE
5376 &msm_vpe_device,
5377#endif
5378#if defined(CONFIG_TSIF) || defined(CONFIG_TSIF_MODULE)
5379 &msm_device_tsif,
5380#endif
5381#ifdef CONFIG_MSM_SDIO_AL
5382 &msm_device_sdio_al,
5383#endif
5384
5385#if defined(CONFIG_CRYPTO_DEV_QCRYPTO) || \
5386 defined(CONFIG_CRYPTO_DEV_QCRYPTO_MODULE)
5387 &qcrypto_device,
5388#endif
5389
5390#if defined(CONFIG_CRYPTO_DEV_QCEDEV) || \
5391 defined(CONFIG_CRYPTO_DEV_QCEDEV_MODULE)
5392 &qcedev_device,
5393#endif
5394
5395 &msm_batt_device,
5396 &msm_adc_device,
5397 &msm_ebi0_thermal,
5398 &msm_ebi1_thermal
5399};
5400
5401static struct msm_gpio msm_i2c_gpios_hw[] = {
5402 { GPIO_CFG(70, 1, GPIO_CFG_INPUT, GPIO_CFG_NO_PULL, GPIO_CFG_16MA), "i2c_scl" },
5403 { GPIO_CFG(71, 1, GPIO_CFG_INPUT, GPIO_CFG_NO_PULL, GPIO_CFG_16MA), "i2c_sda" },
5404};
5405
5406static struct msm_gpio msm_i2c_gpios_io[] = {
5407 { GPIO_CFG(70, 0, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_16MA), "i2c_scl" },
5408 { GPIO_CFG(71, 0, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_16MA), "i2c_sda" },
5409};
5410
5411static struct msm_gpio qup_i2c_gpios_io[] = {
5412 { GPIO_CFG(16, 0, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_16MA), "qup_scl" },
5413 { GPIO_CFG(17, 0, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_16MA), "qup_sda" },
5414};
5415static struct msm_gpio qup_i2c_gpios_hw[] = {
5416 { GPIO_CFG(16, 2, GPIO_CFG_INPUT, GPIO_CFG_NO_PULL, GPIO_CFG_16MA), "qup_scl" },
5417 { GPIO_CFG(17, 2, GPIO_CFG_INPUT, GPIO_CFG_NO_PULL, GPIO_CFG_16MA), "qup_sda" },
5418};
5419
5420static void
5421msm_i2c_gpio_config(int adap_id, int config_type)
5422{
5423 struct msm_gpio *msm_i2c_table;
5424
5425 /* Each adapter gets 2 lines from the table */
5426 if (adap_id > 0)
5427 return;
5428 if (config_type)
5429 msm_i2c_table = &msm_i2c_gpios_hw[adap_id*2];
5430 else
5431 msm_i2c_table = &msm_i2c_gpios_io[adap_id*2];
5432 msm_gpios_enable(msm_i2c_table, 2);
5433}
5434/*This needs to be enabled only for OEMS*/
5435#ifndef CONFIG_QUP_EXCLUSIVE_TO_CAMERA
5436static struct vreg *qup_vreg;
5437#endif
5438static void
5439qup_i2c_gpio_config(int adap_id, int config_type)
5440{
5441 int rc = 0;
5442 struct msm_gpio *qup_i2c_table;
5443 /* Each adapter gets 2 lines from the table */
5444 if (adap_id != 4)
5445 return;
5446 if (config_type)
5447 qup_i2c_table = qup_i2c_gpios_hw;
5448 else
5449 qup_i2c_table = qup_i2c_gpios_io;
5450 rc = msm_gpios_enable(qup_i2c_table, 2);
5451 if (rc < 0)
5452 printk(KERN_ERR "QUP GPIO enable failed: %d\n", rc);
5453 /*This needs to be enabled only for OEMS*/
5454#ifndef CONFIG_QUP_EXCLUSIVE_TO_CAMERA
5455 if (qup_vreg) {
5456 int rc = vreg_set_level(qup_vreg, 1800);
5457 if (rc) {
5458 pr_err("%s: vreg LVS1 set level failed (%d)\n",
5459 __func__, rc);
5460 }
5461 rc = vreg_enable(qup_vreg);
5462 if (rc) {
5463 pr_err("%s: vreg_enable() = %d \n",
5464 __func__, rc);
5465 }
5466 }
5467#endif
5468}
5469
5470static struct msm_i2c_platform_data msm_i2c_pdata = {
5471 .clk_freq = 100000,
5472 .pri_clk = 70,
5473 .pri_dat = 71,
5474 .rmutex = 1,
5475 .rsl_id = "D:I2C02000021",
5476 .msm_i2c_config_gpio = msm_i2c_gpio_config,
5477};
5478
5479static void __init msm_device_i2c_init(void)
5480{
5481 if (msm_gpios_request(msm_i2c_gpios_hw, ARRAY_SIZE(msm_i2c_gpios_hw)))
5482 pr_err("failed to request I2C gpios\n");
5483
5484 msm_device_i2c.dev.platform_data = &msm_i2c_pdata;
5485}
5486
5487static struct msm_i2c_platform_data msm_i2c_2_pdata = {
5488 .clk_freq = 100000,
5489 .rmutex = 1,
5490 .rsl_id = "D:I2C02000022",
5491 .msm_i2c_config_gpio = msm_i2c_gpio_config,
5492};
5493
5494static void __init msm_device_i2c_2_init(void)
5495{
5496 msm_device_i2c_2.dev.platform_data = &msm_i2c_2_pdata;
5497}
5498
5499static struct msm_i2c_platform_data qup_i2c_pdata = {
5500 .clk_freq = 384000,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005501 .msm_i2c_config_gpio = qup_i2c_gpio_config,
5502};
5503
5504static void __init qup_device_i2c_init(void)
5505{
5506 if (msm_gpios_request(qup_i2c_gpios_hw, ARRAY_SIZE(qup_i2c_gpios_hw)))
5507 pr_err("failed to request I2C gpios\n");
5508
5509 qup_device_i2c.dev.platform_data = &qup_i2c_pdata;
5510 /*This needs to be enabled only for OEMS*/
5511#ifndef CONFIG_QUP_EXCLUSIVE_TO_CAMERA
5512 qup_vreg = vreg_get(NULL, "lvsw1");
5513 if (IS_ERR(qup_vreg)) {
5514 printk(KERN_ERR "%s: vreg get failed (%ld)\n",
5515 __func__, PTR_ERR(qup_vreg));
5516 }
5517#endif
5518}
5519
5520#ifdef CONFIG_I2C_SSBI
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005521static struct msm_i2c_ssbi_platform_data msm_i2c_ssbi7_pdata = {
5522 .rsl_id = "D:CODEC_SSBI",
5523 .controller_type = MSM_SBI_CTRL_SSBI,
5524};
5525#endif
5526
Daniel Walker8d747cd2010-02-25 11:37:43 -08005527static void __init msm7x30_init_irq(void)
5528{
5529 msm_init_irq();
5530}
5531
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005532static struct msm_gpio msm_nand_ebi2_cfg_data[] = {
5533 {GPIO_CFG(86, 1, GPIO_CFG_OUTPUT, GPIO_CFG_PULL_UP, GPIO_CFG_8MA), "ebi2_cs1"},
5534 {GPIO_CFG(115, 2, GPIO_CFG_OUTPUT, GPIO_CFG_PULL_UP, GPIO_CFG_8MA), "ebi2_busy1"},
5535};
5536
5537struct vreg *vreg_s3;
5538struct vreg *vreg_mmc;
5539
5540#if (defined(CONFIG_MMC_MSM_SDC1_SUPPORT)\
5541 || defined(CONFIG_MMC_MSM_SDC2_SUPPORT)\
5542 || defined(CONFIG_MMC_MSM_SDC3_SUPPORT)\
5543 || defined(CONFIG_MMC_MSM_SDC4_SUPPORT))
5544
5545struct sdcc_gpio {
5546 struct msm_gpio *cfg_data;
5547 uint32_t size;
5548 struct msm_gpio *sleep_cfg_data;
5549};
5550#if defined(CONFIG_MMC_MSM_SDC1_SUPPORT)
5551static struct msm_gpio sdc1_lvlshft_cfg_data[] = {
5552 {GPIO_CFG(35, 1, GPIO_CFG_OUTPUT, GPIO_CFG_PULL_UP, GPIO_CFG_16MA), "sdc1_lvlshft"},
5553};
5554#endif
5555static struct msm_gpio sdc1_cfg_data[] = {
5556 {GPIO_CFG(38, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_16MA), "sdc1_clk"},
5557 {GPIO_CFG(39, 1, GPIO_CFG_OUTPUT, GPIO_CFG_PULL_UP, GPIO_CFG_8MA), "sdc1_cmd"},
5558 {GPIO_CFG(40, 1, GPIO_CFG_OUTPUT, GPIO_CFG_PULL_UP, GPIO_CFG_8MA), "sdc1_dat_3"},
5559 {GPIO_CFG(41, 1, GPIO_CFG_OUTPUT, GPIO_CFG_PULL_UP, GPIO_CFG_8MA), "sdc1_dat_2"},
5560 {GPIO_CFG(42, 1, GPIO_CFG_OUTPUT, GPIO_CFG_PULL_UP, GPIO_CFG_8MA), "sdc1_dat_1"},
5561 {GPIO_CFG(43, 1, GPIO_CFG_OUTPUT, GPIO_CFG_PULL_UP, GPIO_CFG_8MA), "sdc1_dat_0"},
5562};
5563
5564static struct msm_gpio sdc2_cfg_data[] = {
5565 {GPIO_CFG(64, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_16MA), "sdc2_clk"},
5566 {GPIO_CFG(65, 1, GPIO_CFG_OUTPUT, GPIO_CFG_PULL_UP, GPIO_CFG_8MA), "sdc2_cmd"},
5567 {GPIO_CFG(66, 1, GPIO_CFG_OUTPUT, GPIO_CFG_PULL_UP, GPIO_CFG_8MA), "sdc2_dat_3"},
5568 {GPIO_CFG(67, 1, GPIO_CFG_OUTPUT, GPIO_CFG_PULL_UP, GPIO_CFG_8MA), "sdc2_dat_2"},
5569 {GPIO_CFG(68, 1, GPIO_CFG_OUTPUT, GPIO_CFG_PULL_UP, GPIO_CFG_8MA), "sdc2_dat_1"},
5570 {GPIO_CFG(69, 1, GPIO_CFG_OUTPUT, GPIO_CFG_PULL_UP, GPIO_CFG_8MA), "sdc2_dat_0"},
5571
5572#ifdef CONFIG_MMC_MSM_SDC2_8_BIT_SUPPORT
5573 {GPIO_CFG(115, 1, GPIO_CFG_OUTPUT, GPIO_CFG_PULL_UP, GPIO_CFG_8MA), "sdc2_dat_4"},
5574 {GPIO_CFG(114, 1, GPIO_CFG_OUTPUT, GPIO_CFG_PULL_UP, GPIO_CFG_8MA), "sdc2_dat_5"},
5575 {GPIO_CFG(113, 1, GPIO_CFG_OUTPUT, GPIO_CFG_PULL_UP, GPIO_CFG_8MA), "sdc2_dat_6"},
5576 {GPIO_CFG(112, 1, GPIO_CFG_OUTPUT, GPIO_CFG_PULL_UP, GPIO_CFG_8MA), "sdc2_dat_7"},
5577#endif
5578};
5579
5580static struct msm_gpio sdc3_cfg_data[] = {
5581 {GPIO_CFG(110, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_16MA), "sdc3_clk"},
5582 {GPIO_CFG(111, 1, GPIO_CFG_OUTPUT, GPIO_CFG_PULL_UP, GPIO_CFG_8MA), "sdc3_cmd"},
5583 {GPIO_CFG(116, 1, GPIO_CFG_OUTPUT, GPIO_CFG_PULL_UP, GPIO_CFG_8MA), "sdc3_dat_3"},
5584 {GPIO_CFG(117, 1, GPIO_CFG_OUTPUT, GPIO_CFG_PULL_UP, GPIO_CFG_8MA), "sdc3_dat_2"},
5585 {GPIO_CFG(118, 1, GPIO_CFG_OUTPUT, GPIO_CFG_PULL_UP, GPIO_CFG_8MA), "sdc3_dat_1"},
5586 {GPIO_CFG(119, 1, GPIO_CFG_OUTPUT, GPIO_CFG_PULL_UP, GPIO_CFG_8MA), "sdc3_dat_0"},
5587};
5588
5589static struct msm_gpio sdc3_sleep_cfg_data[] = {
5590 {GPIO_CFG(110, 0, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA),
5591 "sdc3_clk"},
5592 {GPIO_CFG(111, 0, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA),
5593 "sdc3_cmd"},
5594 {GPIO_CFG(116, 0, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA),
5595 "sdc3_dat_3"},
5596 {GPIO_CFG(117, 0, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA),
5597 "sdc3_dat_2"},
5598 {GPIO_CFG(118, 0, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA),
5599 "sdc3_dat_1"},
5600 {GPIO_CFG(119, 0, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA),
5601 "sdc3_dat_0"},
5602};
5603
5604static struct msm_gpio sdc4_cfg_data[] = {
5605 {GPIO_CFG(58, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_16MA), "sdc4_clk"},
5606 {GPIO_CFG(59, 1, GPIO_CFG_OUTPUT, GPIO_CFG_PULL_UP, GPIO_CFG_8MA), "sdc4_cmd"},
5607 {GPIO_CFG(60, 1, GPIO_CFG_OUTPUT, GPIO_CFG_PULL_UP, GPIO_CFG_8MA), "sdc4_dat_3"},
5608 {GPIO_CFG(61, 1, GPIO_CFG_OUTPUT, GPIO_CFG_PULL_UP, GPIO_CFG_8MA), "sdc4_dat_2"},
5609 {GPIO_CFG(62, 1, GPIO_CFG_OUTPUT, GPIO_CFG_PULL_UP, GPIO_CFG_8MA), "sdc4_dat_1"},
5610 {GPIO_CFG(63, 1, GPIO_CFG_OUTPUT, GPIO_CFG_PULL_UP, GPIO_CFG_8MA), "sdc4_dat_0"},
5611};
5612
5613static struct sdcc_gpio sdcc_cfg_data[] = {
5614 {
5615 .cfg_data = sdc1_cfg_data,
5616 .size = ARRAY_SIZE(sdc1_cfg_data),
5617 .sleep_cfg_data = NULL,
5618 },
5619 {
5620 .cfg_data = sdc2_cfg_data,
5621 .size = ARRAY_SIZE(sdc2_cfg_data),
5622 .sleep_cfg_data = NULL,
5623 },
5624 {
5625 .cfg_data = sdc3_cfg_data,
5626 .size = ARRAY_SIZE(sdc3_cfg_data),
5627 .sleep_cfg_data = sdc3_sleep_cfg_data,
5628 },
5629 {
5630 .cfg_data = sdc4_cfg_data,
5631 .size = ARRAY_SIZE(sdc4_cfg_data),
5632 .sleep_cfg_data = NULL,
5633 },
5634};
5635
5636struct sdcc_vreg {
5637 struct vreg *vreg_data;
5638 unsigned level;
5639};
5640
5641static struct sdcc_vreg sdcc_vreg_data[4];
5642
5643static unsigned long vreg_sts, gpio_sts;
5644
5645static uint32_t msm_sdcc_setup_gpio(int dev_id, unsigned int enable)
5646{
5647 int rc = 0;
5648 struct sdcc_gpio *curr;
5649
5650 curr = &sdcc_cfg_data[dev_id - 1];
5651
5652 if (!(test_bit(dev_id, &gpio_sts)^enable))
5653 return rc;
5654
5655 if (enable) {
5656 set_bit(dev_id, &gpio_sts);
5657 rc = msm_gpios_request_enable(curr->cfg_data, curr->size);
5658 if (rc)
5659 printk(KERN_ERR "%s: Failed to turn on GPIOs for slot %d\n",
5660 __func__, dev_id);
5661 } else {
5662 clear_bit(dev_id, &gpio_sts);
5663 if (curr->sleep_cfg_data) {
5664 msm_gpios_enable(curr->sleep_cfg_data, curr->size);
5665 msm_gpios_free(curr->sleep_cfg_data, curr->size);
5666 } else {
5667 msm_gpios_disable_free(curr->cfg_data, curr->size);
5668 }
5669 }
5670
5671 return rc;
5672}
5673
5674static uint32_t msm_sdcc_setup_vreg(int dev_id, unsigned int enable)
5675{
5676 int rc = 0;
5677 struct sdcc_vreg *curr;
5678 static int enabled_once[] = {0, 0, 0, 0};
5679
5680 curr = &sdcc_vreg_data[dev_id - 1];
5681
5682 if (!(test_bit(dev_id, &vreg_sts)^enable))
5683 return rc;
5684
5685 if (!enable || enabled_once[dev_id - 1])
5686 return 0;
5687
5688 if (enable) {
5689 set_bit(dev_id, &vreg_sts);
5690 rc = vreg_set_level(curr->vreg_data, curr->level);
5691 if (rc) {
5692 printk(KERN_ERR "%s: vreg_set_level() = %d \n",
5693 __func__, rc);
5694 }
5695 rc = vreg_enable(curr->vreg_data);
5696 if (rc) {
5697 printk(KERN_ERR "%s: vreg_enable() = %d \n",
5698 __func__, rc);
5699 }
5700 enabled_once[dev_id - 1] = 1;
5701 } else {
5702 clear_bit(dev_id, &vreg_sts);
5703 rc = vreg_disable(curr->vreg_data);
5704 if (rc) {
5705 printk(KERN_ERR "%s: vreg_disable() = %d \n",
5706 __func__, rc);
5707 }
5708 }
5709 return rc;
5710}
5711
5712static uint32_t msm_sdcc_setup_power(struct device *dv, unsigned int vdd)
5713{
5714 int rc = 0;
5715 struct platform_device *pdev;
5716
5717 pdev = container_of(dv, struct platform_device, dev);
5718 rc = msm_sdcc_setup_gpio(pdev->id, (vdd ? 1 : 0));
5719 if (rc)
5720 goto out;
5721
5722 if (pdev->id == 4) /* S3 is always ON and cannot be disabled */
5723 rc = msm_sdcc_setup_vreg(pdev->id, (vdd ? 1 : 0));
5724out:
5725 return rc;
5726}
5727
5728#if defined(CONFIG_MMC_MSM_SDC1_SUPPORT) && \
5729 defined(CONFIG_CSDIO_VENDOR_ID) && \
5730 defined(CONFIG_CSDIO_DEVICE_ID) && \
5731 (CONFIG_CSDIO_VENDOR_ID == 0x70 && CONFIG_CSDIO_DEVICE_ID == 0x1117)
5732
5733#define MBP_ON 1
5734#define MBP_OFF 0
5735
5736#define MBP_RESET_N \
5737 GPIO_CFG(44, 0, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_8MA)
5738#define MBP_INT0 \
5739 GPIO_CFG(46, 0, GPIO_CFG_INPUT, GPIO_CFG_PULL_UP, GPIO_CFG_8MA)
5740
5741#define MBP_MODE_CTRL_0 \
5742 GPIO_CFG(35, 0, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA)
5743#define MBP_MODE_CTRL_1 \
5744 GPIO_CFG(36, 0, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA)
5745#define MBP_MODE_CTRL_2 \
5746 GPIO_CFG(34, 0, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA)
5747#define TSIF_EN \
5748 GPIO_CFG(35, 1, GPIO_CFG_INPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA)
5749#define TSIF_DATA \
5750 GPIO_CFG(36, 1, GPIO_CFG_INPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA)
5751#define TSIF_CLK \
5752 GPIO_CFG(34, 1, GPIO_CFG_INPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA)
5753
5754static struct msm_gpio mbp_cfg_data[] = {
5755 {GPIO_CFG(44, 0, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_16MA),
5756 "mbp_reset"},
5757 {GPIO_CFG(85, 0, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_16MA),
5758 "mbp_io_voltage"},
5759};
5760
5761static int mbp_config_gpios_pre_init(int enable)
5762{
5763 int rc = 0;
5764
5765 if (enable) {
5766 rc = msm_gpios_request_enable(mbp_cfg_data,
5767 ARRAY_SIZE(mbp_cfg_data));
5768 if (rc) {
5769 printk(KERN_ERR
5770 "%s: Failed to turnon GPIOs for mbp chip(%d)\n",
5771 __func__, rc);
5772 }
5773 } else
5774 msm_gpios_disable_free(mbp_cfg_data, ARRAY_SIZE(mbp_cfg_data));
5775 return rc;
5776}
5777
5778static int mbp_setup_rf_vregs(int state)
5779{
5780 struct vreg *vreg_rf = NULL;
5781 struct vreg *vreg_rf_switch = NULL;
5782 int rc;
5783
5784 vreg_rf = vreg_get(NULL, "s2");
5785 if (IS_ERR(vreg_rf)) {
5786 pr_err("%s: s2 vreg get failed (%ld)",
5787 __func__, PTR_ERR(vreg_rf));
5788 return -EFAULT;
5789 }
5790 vreg_rf_switch = vreg_get(NULL, "rf");
5791 if (IS_ERR(vreg_rf_switch)) {
5792 pr_err("%s: rf vreg get failed (%ld)",
5793 __func__, PTR_ERR(vreg_rf_switch));
5794 return -EFAULT;
5795 }
5796
5797 if (state) {
5798 rc = vreg_set_level(vreg_rf, 1300);
5799 if (rc) {
5800 pr_err("%s: vreg s2 set level failed (%d)\n",
5801 __func__, rc);
5802 return rc;
5803 }
5804
5805 rc = vreg_enable(vreg_rf);
5806 if (rc) {
5807 printk(KERN_ERR "%s: vreg_enable(s2) = %d\n",
5808 __func__, rc);
5809 }
5810
5811 rc = vreg_set_level(vreg_rf_switch, 2600);
5812 if (rc) {
5813 pr_err("%s: vreg rf switch set level failed (%d)\n",
5814 __func__, rc);
5815 return rc;
5816 }
5817 rc = vreg_enable(vreg_rf_switch);
5818 if (rc) {
5819 printk(KERN_ERR "%s: vreg_enable(rf) = %d\n",
5820 __func__, rc);
5821 }
5822 } else {
5823 (void) vreg_disable(vreg_rf);
5824 (void) vreg_disable(vreg_rf_switch);
5825 }
5826 return 0;
5827}
5828
5829static int mbp_setup_vregs(int state)
5830{
5831 struct vreg *vreg_analog = NULL;
5832 struct vreg *vreg_io = NULL;
5833 int rc;
5834
5835 vreg_analog = vreg_get(NULL, "gp4");
5836 if (IS_ERR(vreg_analog)) {
5837 pr_err("%s: gp4 vreg get failed (%ld)",
5838 __func__, PTR_ERR(vreg_analog));
5839 return -EFAULT;
5840 }
5841 vreg_io = vreg_get(NULL, "s3");
5842 if (IS_ERR(vreg_io)) {
5843 pr_err("%s: s3 vreg get failed (%ld)",
5844 __func__, PTR_ERR(vreg_io));
5845 return -EFAULT;
5846 }
5847 if (state) {
5848 rc = vreg_set_level(vreg_analog, 2600);
5849 if (rc) {
5850 pr_err("%s: vreg_set_level failed (%d)",
5851 __func__, rc);
5852 }
5853 rc = vreg_enable(vreg_analog);
5854 if (rc) {
5855 pr_err("%s: analog vreg enable failed (%d)",
5856 __func__, rc);
5857 }
5858 rc = vreg_set_level(vreg_io, 1800);
5859 if (rc) {
5860 pr_err("%s: vreg_set_level failed (%d)",
5861 __func__, rc);
5862 }
5863 rc = vreg_enable(vreg_io);
5864 if (rc) {
5865 pr_err("%s: io vreg enable failed (%d)",
5866 __func__, rc);
5867 }
5868 } else {
5869 rc = vreg_disable(vreg_analog);
5870 if (rc) {
5871 pr_err("%s: analog vreg disable failed (%d)",
5872 __func__, rc);
5873 }
5874 rc = vreg_disable(vreg_io);
5875 if (rc) {
5876 pr_err("%s: io vreg disable failed (%d)",
5877 __func__, rc);
5878 }
5879 }
5880 return rc;
5881}
5882
5883static int mbp_set_tcxo_en(int enable)
5884{
5885 int rc;
5886 const char *id = "UBMC";
5887 struct vreg *vreg_analog = NULL;
5888
5889 rc = pmapp_clock_vote(id, PMAPP_CLOCK_ID_A1,
5890 enable ? PMAPP_CLOCK_VOTE_ON : PMAPP_CLOCK_VOTE_OFF);
5891 if (rc < 0) {
5892 printk(KERN_ERR "%s: unable to %svote for a1 clk\n",
5893 __func__, enable ? "" : "de-");
5894 return -EIO;
5895 }
5896 if (!enable) {
5897 vreg_analog = vreg_get(NULL, "gp4");
5898 if (IS_ERR(vreg_analog)) {
5899 pr_err("%s: gp4 vreg get failed (%ld)",
5900 __func__, PTR_ERR(vreg_analog));
5901 return -EFAULT;
5902 }
5903
5904 (void) vreg_disable(vreg_analog);
5905 }
5906 return rc;
5907}
5908
5909static void mbp_set_freeze_io(int state)
5910{
5911 if (state)
5912 gpio_set_value(85, 0);
5913 else
5914 gpio_set_value(85, 1);
5915}
5916
5917static int mbp_set_core_voltage_en(int enable)
5918{
5919 int rc;
5920 struct vreg *vreg_core1p2 = NULL;
5921
5922 vreg_core1p2 = vreg_get(NULL, "gp16");
5923 if (IS_ERR(vreg_core1p2)) {
5924 pr_err("%s: gp16 vreg get failed (%ld)",
5925 __func__, PTR_ERR(vreg_core1p2));
5926 return -EFAULT;
5927 }
5928 if (enable) {
5929 rc = vreg_set_level(vreg_core1p2, 1200);
5930 if (rc) {
5931 pr_err("%s: vreg_set_level failed (%d)",
5932 __func__, rc);
5933 }
5934 (void) vreg_enable(vreg_core1p2);
5935
5936 return 80;
5937 } else {
5938 gpio_set_value(85, 1);
5939 return 0;
5940 }
5941 return rc;
5942}
5943
5944static void mbp_set_reset(int state)
5945{
5946 if (state)
5947 gpio_set_value(GPIO_PIN(MBP_RESET_N), 0);
5948 else
5949 gpio_set_value(GPIO_PIN(MBP_RESET_N), 1);
5950}
5951
5952static int mbp_config_interface_mode(int state)
5953{
5954 if (state) {
5955 gpio_tlmm_config(MBP_MODE_CTRL_0, GPIO_CFG_ENABLE);
5956 gpio_tlmm_config(MBP_MODE_CTRL_1, GPIO_CFG_ENABLE);
5957 gpio_tlmm_config(MBP_MODE_CTRL_2, GPIO_CFG_ENABLE);
5958 gpio_set_value(GPIO_PIN(MBP_MODE_CTRL_0), 0);
5959 gpio_set_value(GPIO_PIN(MBP_MODE_CTRL_1), 1);
5960 gpio_set_value(GPIO_PIN(MBP_MODE_CTRL_2), 0);
5961 } else {
5962 gpio_tlmm_config(MBP_MODE_CTRL_0, GPIO_CFG_DISABLE);
5963 gpio_tlmm_config(MBP_MODE_CTRL_1, GPIO_CFG_DISABLE);
5964 gpio_tlmm_config(MBP_MODE_CTRL_2, GPIO_CFG_DISABLE);
5965 }
5966 return 0;
5967}
5968
5969static int mbp_setup_adc_vregs(int state)
5970{
5971 struct vreg *vreg_adc = NULL;
5972 int rc;
5973
5974 vreg_adc = vreg_get(NULL, "s4");
5975 if (IS_ERR(vreg_adc)) {
5976 pr_err("%s: s4 vreg get failed (%ld)",
5977 __func__, PTR_ERR(vreg_adc));
5978 return -EFAULT;
5979 }
5980 if (state) {
5981 rc = vreg_set_level(vreg_adc, 2200);
5982 if (rc) {
5983 pr_err("%s: vreg_set_level failed (%d)",
5984 __func__, rc);
5985 }
5986 rc = vreg_enable(vreg_adc);
5987 if (rc) {
5988 pr_err("%s: enable vreg adc failed (%d)",
5989 __func__, rc);
5990 }
5991 } else {
5992 rc = vreg_disable(vreg_adc);
5993 if (rc) {
5994 pr_err("%s: disable vreg adc failed (%d)",
5995 __func__, rc);
5996 }
5997 }
5998 return rc;
5999}
6000
6001static int mbp_power_up(void)
6002{
6003 int rc;
6004
6005 rc = mbp_config_gpios_pre_init(MBP_ON);
6006 if (rc)
6007 goto exit;
6008 pr_debug("%s: mbp_config_gpios_pre_init() done\n", __func__);
6009
6010 rc = mbp_setup_vregs(MBP_ON);
6011 if (rc)
6012 goto exit;
6013 pr_debug("%s: gp4 (2.6) and s3 (1.8) done\n", __func__);
6014
6015 rc = mbp_set_tcxo_en(MBP_ON);
6016 if (rc)
6017 goto exit;
6018 pr_debug("%s: tcxo clock done\n", __func__);
6019
6020 mbp_set_freeze_io(MBP_OFF);
6021 pr_debug("%s: set gpio 85 to 1 done\n", __func__);
6022
6023 udelay(100);
6024 mbp_set_reset(MBP_ON);
6025
6026 udelay(300);
6027 rc = mbp_config_interface_mode(MBP_ON);
6028 if (rc)
6029 goto exit;
6030 pr_debug("%s: mbp_config_interface_mode() done\n", __func__);
6031
6032 udelay(100 + mbp_set_core_voltage_en(MBP_ON));
6033 pr_debug("%s: power gp16 1.2V done\n", __func__);
6034
6035 mbp_set_freeze_io(MBP_ON);
6036 pr_debug("%s: set gpio 85 to 0 done\n", __func__);
6037
6038 udelay(100);
6039
6040 rc = mbp_setup_rf_vregs(MBP_ON);
6041 if (rc)
6042 goto exit;
6043 pr_debug("%s: s2 1.3V and rf 2.6V done\n", __func__);
6044
6045 rc = mbp_setup_adc_vregs(MBP_ON);
6046 if (rc)
6047 goto exit;
6048 pr_debug("%s: s4 2.2V done\n", __func__);
6049
6050 udelay(200);
6051
6052 mbp_set_reset(MBP_OFF);
6053 pr_debug("%s: close gpio 44 done\n", __func__);
6054
6055 msleep(20);
6056exit:
6057 return rc;
6058}
6059
6060static int mbp_power_down(void)
6061{
6062 int rc;
6063 struct vreg *vreg_adc = NULL;
6064
6065 vreg_adc = vreg_get(NULL, "s4");
6066 if (IS_ERR(vreg_adc)) {
6067 pr_err("%s: s4 vreg get failed (%ld)",
6068 __func__, PTR_ERR(vreg_adc));
6069 return -EFAULT;
6070 }
6071
6072 mbp_set_reset(MBP_ON);
6073 pr_debug("%s: mbp_set_reset(MBP_ON) done\n", __func__);
6074
6075 udelay(100);
6076
6077 rc = mbp_setup_adc_vregs(MBP_OFF);
6078 if (rc)
6079 goto exit;
6080 pr_debug("%s: vreg_disable(vreg_adc) done\n", __func__);
6081
6082 udelay(5);
6083
6084 rc = mbp_setup_rf_vregs(MBP_OFF);
6085 if (rc)
6086 goto exit;
6087 pr_debug("%s: mbp_setup_rf_vregs(MBP_OFF) done\n", __func__);
6088
6089 udelay(5);
6090
6091 mbp_set_freeze_io(MBP_OFF);
6092 pr_debug("%s: mbp_set_freeze_io(MBP_OFF) done\n", __func__);
6093
6094 udelay(100);
6095 rc = mbp_set_core_voltage_en(MBP_OFF);
6096 if (rc)
6097 goto exit;
6098 pr_debug("%s: mbp_set_core_voltage_en(MBP_OFF) done\n", __func__);
6099
6100 gpio_set_value(85, 1);
6101
6102 rc = mbp_set_tcxo_en(MBP_OFF);
6103 if (rc)
6104 goto exit;
6105 pr_debug("%s: mbp_set_tcxo_en(MBP_OFF) done\n", __func__);
6106
6107 rc = mbp_config_gpios_pre_init(MBP_OFF);
6108 if (rc)
6109 goto exit;
6110exit:
6111 return rc;
6112}
6113
6114static void (*mbp_status_notify_cb)(int card_present, void *dev_id);
6115static void *mbp_status_notify_cb_devid;
6116static int mbp_power_status;
6117static int mbp_power_init_done;
6118
6119static uint32_t mbp_setup_power(struct device *dv,
6120 unsigned int power_status)
6121{
6122 int rc = 0;
6123 struct platform_device *pdev;
6124
6125 pdev = container_of(dv, struct platform_device, dev);
6126
6127 if (power_status == mbp_power_status)
6128 goto exit;
6129 if (power_status) {
6130 pr_debug("turn on power of mbp slot");
6131 rc = mbp_power_up();
6132 mbp_power_status = 1;
6133 } else {
6134 pr_debug("turn off power of mbp slot");
6135 rc = mbp_power_down();
6136 mbp_power_status = 0;
6137 }
6138exit:
6139 return rc;
6140};
6141
6142int mbp_register_status_notify(void (*callback)(int, void *),
6143 void *dev_id)
6144{
6145 mbp_status_notify_cb = callback;
6146 mbp_status_notify_cb_devid = dev_id;
6147 return 0;
6148}
6149
6150static unsigned int mbp_status(struct device *dev)
6151{
6152 return mbp_power_status;
6153}
6154
6155static uint32_t msm_sdcc_setup_power_mbp(struct device *dv, unsigned int vdd)
6156{
6157 struct platform_device *pdev;
6158 uint32_t rc = 0;
6159
6160 pdev = container_of(dv, struct platform_device, dev);
6161 rc = msm_sdcc_setup_power(dv, vdd);
6162 if (rc) {
6163 pr_err("%s: Failed to setup power (%d)\n",
6164 __func__, rc);
6165 goto out;
6166 }
6167 if (!mbp_power_init_done) {
6168 mbp_setup_power(dv, 1);
6169 mbp_setup_power(dv, 0);
6170 mbp_power_init_done = 1;
6171 }
6172 if (vdd >= 0x8000) {
6173 rc = mbp_setup_power(dv, (0x8000 == vdd) ? 0 : 1);
6174 if (rc) {
6175 pr_err("%s: Failed to config mbp chip power (%d)\n",
6176 __func__, rc);
6177 goto out;
6178 }
6179 if (mbp_status_notify_cb) {
6180 mbp_status_notify_cb(mbp_power_status,
6181 mbp_status_notify_cb_devid);
6182 }
6183 }
6184out:
6185 /* should return 0 only */
6186 return 0;
6187}
6188
6189#endif
6190
6191#endif
6192
6193#ifdef CONFIG_MMC_MSM_SDC4_SUPPORT
6194#ifdef CONFIG_MMC_MSM_CARD_HW_DETECTION
6195static unsigned int msm7x30_sdcc_slot_status(struct device *dev)
6196{
6197 return (unsigned int)
6198 gpio_get_value_cansleep(
6199 PM8058_GPIO_PM_TO_SYS(PMIC_GPIO_SD_DET - 1));
6200}
6201#endif
6202
6203static int msm_sdcc_get_wpswitch(struct device *dv)
6204{
6205 void __iomem *wp_addr = 0;
6206 uint32_t ret = 0;
6207 struct platform_device *pdev;
6208
6209 if (!(machine_is_msm7x30_surf()))
6210 return -1;
6211 pdev = container_of(dv, struct platform_device, dev);
6212
6213 wp_addr = ioremap(FPGA_SDCC_STATUS, 4);
6214 if (!wp_addr) {
6215 pr_err("%s: Could not remap %x\n", __func__, FPGA_SDCC_STATUS);
6216 return -ENOMEM;
6217 }
6218
6219 ret = (((readl(wp_addr) >> 4) >> (pdev->id-1)) & 0x01);
6220 pr_info("%s: WP Status for Slot %d = 0x%x \n", __func__,
6221 pdev->id, ret);
6222 iounmap(wp_addr);
6223
6224 return ret;
6225}
6226#endif
6227
6228#if defined(CONFIG_MMC_MSM_SDC1_SUPPORT)
6229#if defined(CONFIG_CSDIO_VENDOR_ID) && \
6230 defined(CONFIG_CSDIO_DEVICE_ID) && \
6231 (CONFIG_CSDIO_VENDOR_ID == 0x70 && CONFIG_CSDIO_DEVICE_ID == 0x1117)
6232static struct mmc_platform_data msm7x30_sdc1_data = {
6233 .ocr_mask = MMC_VDD_165_195 | MMC_VDD_27_28 | MMC_VDD_28_29,
6234 .translate_vdd = msm_sdcc_setup_power_mbp,
6235 .mmc_bus_width = MMC_CAP_4_BIT_DATA,
6236 .status = mbp_status,
6237 .register_status_notify = mbp_register_status_notify,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07006238 .msmsdcc_fmin = 144000,
6239 .msmsdcc_fmid = 24576000,
6240 .msmsdcc_fmax = 24576000,
6241 .nonremovable = 0,
6242};
6243#else
6244static struct mmc_platform_data msm7x30_sdc1_data = {
6245 .ocr_mask = MMC_VDD_165_195,
6246 .translate_vdd = msm_sdcc_setup_power,
6247 .mmc_bus_width = MMC_CAP_4_BIT_DATA,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07006248 .msmsdcc_fmin = 144000,
6249 .msmsdcc_fmid = 24576000,
6250 .msmsdcc_fmax = 49152000,
6251 .nonremovable = 0,
6252};
6253#endif
6254#endif
6255
6256#ifdef CONFIG_MMC_MSM_SDC2_SUPPORT
6257static struct mmc_platform_data msm7x30_sdc2_data = {
6258 .ocr_mask = MMC_VDD_165_195 | MMC_VDD_27_28,
6259 .translate_vdd = msm_sdcc_setup_power,
6260#ifdef CONFIG_MMC_MSM_SDC2_8_BIT_SUPPORT
6261 .mmc_bus_width = MMC_CAP_8_BIT_DATA,
6262#else
6263 .mmc_bus_width = MMC_CAP_4_BIT_DATA,
6264#endif
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07006265 .msmsdcc_fmin = 144000,
6266 .msmsdcc_fmid = 24576000,
6267 .msmsdcc_fmax = 49152000,
6268 .nonremovable = 1,
6269};
6270#endif
6271
6272#ifdef CONFIG_MMC_MSM_SDC3_SUPPORT
6273static struct mmc_platform_data msm7x30_sdc3_data = {
6274 .ocr_mask = MMC_VDD_27_28 | MMC_VDD_28_29,
6275 .translate_vdd = msm_sdcc_setup_power,
6276 .mmc_bus_width = MMC_CAP_4_BIT_DATA,
6277#ifdef CONFIG_MMC_MSM_SDIO_SUPPORT
6278 .sdiowakeup_irq = MSM_GPIO_TO_INT(118),
6279#endif
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07006280 .msmsdcc_fmin = 144000,
6281 .msmsdcc_fmid = 24576000,
6282 .msmsdcc_fmax = 49152000,
6283 .nonremovable = 0,
6284};
6285#endif
6286
6287#ifdef CONFIG_MMC_MSM_SDC4_SUPPORT
6288static struct mmc_platform_data msm7x30_sdc4_data = {
6289 .ocr_mask = MMC_VDD_27_28 | MMC_VDD_28_29,
6290 .translate_vdd = msm_sdcc_setup_power,
6291 .mmc_bus_width = MMC_CAP_4_BIT_DATA,
6292#ifdef CONFIG_MMC_MSM_CARD_HW_DETECTION
6293 .status = msm7x30_sdcc_slot_status,
6294 .status_irq = PM8058_GPIO_IRQ(PMIC8058_IRQ_BASE, PMIC_GPIO_SD_DET - 1),
6295 .irq_flags = IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING,
6296#endif
6297 .wpswitch = msm_sdcc_get_wpswitch,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07006298 .msmsdcc_fmin = 144000,
6299 .msmsdcc_fmid = 24576000,
6300 .msmsdcc_fmax = 49152000,
6301 .nonremovable = 0,
6302};
6303#endif
6304
6305#ifdef CONFIG_MMC_MSM_SDC1_SUPPORT
6306static void msm_sdc1_lvlshft_enable(void)
6307{
6308 int rc;
6309
6310 /* Enable LDO5, an input to the FET that powers slot 1 */
6311 rc = vreg_set_level(vreg_mmc, 2850);
6312 if (rc)
6313 printk(KERN_ERR "%s: vreg_set_level() = %d \n", __func__, rc);
6314
6315 rc = vreg_enable(vreg_mmc);
6316 if (rc)
6317 printk(KERN_ERR "%s: vreg_enable() = %d \n", __func__, rc);
6318
6319 /* Enable GPIO 35, to turn on the FET that powers slot 1 */
6320 rc = msm_gpios_request_enable(sdc1_lvlshft_cfg_data,
6321 ARRAY_SIZE(sdc1_lvlshft_cfg_data));
6322 if (rc)
6323 printk(KERN_ERR "%s: Failed to enable GPIO 35\n", __func__);
6324
6325 rc = gpio_direction_output(GPIO_PIN(sdc1_lvlshft_cfg_data[0].gpio_cfg),
6326 1);
6327 if (rc)
6328 printk(KERN_ERR "%s: Failed to turn on GPIO 35\n", __func__);
6329}
6330#endif
6331
6332static void __init msm7x30_init_mmc(void)
6333{
6334 vreg_s3 = vreg_get(NULL, "s3");
6335 if (IS_ERR(vreg_s3)) {
6336 printk(KERN_ERR "%s: vreg get failed (%ld)\n",
6337 __func__, PTR_ERR(vreg_s3));
6338 return;
6339 }
6340
6341 vreg_mmc = vreg_get(NULL, "mmc");
6342 if (IS_ERR(vreg_mmc)) {
6343 printk(KERN_ERR "%s: vreg get failed (%ld)\n",
6344 __func__, PTR_ERR(vreg_mmc));
6345 return;
6346 }
6347
6348#ifdef CONFIG_MMC_MSM_SDC1_SUPPORT
6349 if (machine_is_msm7x30_fluid()) {
6350 msm7x30_sdc1_data.ocr_mask = MMC_VDD_27_28 | MMC_VDD_28_29;
6351 msm_sdc1_lvlshft_enable();
6352 }
6353 sdcc_vreg_data[0].vreg_data = vreg_s3;
6354 sdcc_vreg_data[0].level = 1800;
6355 msm_add_sdcc(1, &msm7x30_sdc1_data);
6356#endif
6357#ifdef CONFIG_MMC_MSM_SDC2_SUPPORT
6358 if (machine_is_msm8x55_svlte_surf())
6359 msm7x30_sdc2_data.msmsdcc_fmax = 24576000;
6360 sdcc_vreg_data[1].vreg_data = vreg_s3;
6361 sdcc_vreg_data[1].level = 1800;
6362 msm_add_sdcc(2, &msm7x30_sdc2_data);
6363#endif
6364#ifdef CONFIG_MMC_MSM_SDC3_SUPPORT
6365 sdcc_vreg_data[2].vreg_data = vreg_s3;
6366 sdcc_vreg_data[2].level = 1800;
6367 msm_sdcc_setup_gpio(3, 1);
6368 msm_add_sdcc(3, &msm7x30_sdc3_data);
6369#endif
6370#ifdef CONFIG_MMC_MSM_SDC4_SUPPORT
6371 sdcc_vreg_data[3].vreg_data = vreg_mmc;
6372 sdcc_vreg_data[3].level = 2850;
6373 msm_add_sdcc(4, &msm7x30_sdc4_data);
6374#endif
6375
6376}
6377
6378static void __init msm7x30_init_nand(void)
6379{
6380 char *build_id;
6381 struct flash_platform_data *plat_data;
6382
6383 build_id = socinfo_get_build_id();
6384 if (build_id == NULL) {
6385 pr_err("%s: Build ID not available from socinfo\n", __func__);
6386 return;
6387 }
6388
6389 if (build_id[8] == 'C' &&
6390 !msm_gpios_request_enable(msm_nand_ebi2_cfg_data,
6391 ARRAY_SIZE(msm_nand_ebi2_cfg_data))) {
6392 plat_data = msm_device_nand.dev.platform_data;
6393 plat_data->interleave = 1;
6394 printk(KERN_INFO "%s: Interleave mode Build ID found\n",
6395 __func__);
6396 }
6397}
6398
6399#ifdef CONFIG_SERIAL_MSM_CONSOLE
6400static struct msm_gpio uart2_config_data[] = {
6401 { GPIO_CFG(49, 2, GPIO_CFG_OUTPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA), "UART2_RFR"},
6402 { GPIO_CFG(50, 2, GPIO_CFG_INPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA), "UART2_CTS"},
6403 { GPIO_CFG(51, 2, GPIO_CFG_INPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA), "UART2_Rx"},
6404 { GPIO_CFG(52, 2, GPIO_CFG_OUTPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA), "UART2_Tx"},
6405};
6406
6407static void msm7x30_init_uart2(void)
6408{
6409 msm_gpios_request_enable(uart2_config_data,
6410 ARRAY_SIZE(uart2_config_data));
6411
6412}
6413#endif
6414
6415/* TSIF begin */
6416#if defined(CONFIG_TSIF) || defined(CONFIG_TSIF_MODULE)
6417
6418#define TSIF_B_SYNC GPIO_CFG(37, 1, GPIO_CFG_INPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA)
6419#define TSIF_B_DATA GPIO_CFG(36, 1, GPIO_CFG_INPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA)
6420#define TSIF_B_EN GPIO_CFG(35, 1, GPIO_CFG_INPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA)
6421#define TSIF_B_CLK GPIO_CFG(34, 1, GPIO_CFG_INPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA)
6422
6423static const struct msm_gpio tsif_gpios[] = {
6424 { .gpio_cfg = TSIF_B_CLK, .label = "tsif_clk", },
6425 { .gpio_cfg = TSIF_B_EN, .label = "tsif_en", },
6426 { .gpio_cfg = TSIF_B_DATA, .label = "tsif_data", },
6427 { .gpio_cfg = TSIF_B_SYNC, .label = "tsif_sync", },
6428};
6429
6430static struct msm_tsif_platform_data tsif_platform_data = {
6431 .num_gpios = ARRAY_SIZE(tsif_gpios),
6432 .gpios = tsif_gpios,
Matt Wagantall640e5fd2011-08-17 16:08:53 -07006433 .tsif_pclk = "iface_clk",
6434 .tsif_ref_clk = "ref_clk",
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07006435};
6436#endif /* defined(CONFIG_TSIF) || defined(CONFIG_TSIF_MODULE) */
6437/* TSIF end */
6438
6439static void __init pmic8058_leds_init(void)
6440{
6441 if (machine_is_msm7x30_surf()) {
6442 pm8058_7x30_data.sub_devices[PM8058_SUBDEV_LED].platform_data
6443 = &pm8058_surf_leds_data;
6444 } else if (!machine_is_msm7x30_fluid()) {
6445 pm8058_7x30_data.sub_devices[PM8058_SUBDEV_LED].platform_data
6446 = &pm8058_ffa_leds_data;
6447 } else if (machine_is_msm7x30_fluid()) {
6448 pm8058_7x30_data.sub_devices[PM8058_SUBDEV_LED].platform_data
6449 = &pm8058_fluid_leds_data;
6450 }
6451}
6452
6453static struct msm_spm_platform_data msm_spm_data __initdata = {
6454 .reg_base_addr = MSM_SAW_BASE,
6455
6456 .reg_init_values[MSM_SPM_REG_SAW_CFG] = 0x05,
6457 .reg_init_values[MSM_SPM_REG_SAW_SPM_CTL] = 0x18,
6458 .reg_init_values[MSM_SPM_REG_SAW_SPM_SLP_TMR_DLY] = 0x00006666,
6459 .reg_init_values[MSM_SPM_REG_SAW_SPM_WAKE_TMR_DLY] = 0xFF000666,
6460
6461 .reg_init_values[MSM_SPM_REG_SAW_SLP_CLK_EN] = 0x01,
6462 .reg_init_values[MSM_SPM_REG_SAW_SLP_HSFS_PRECLMP_EN] = 0x03,
6463 .reg_init_values[MSM_SPM_REG_SAW_SLP_HSFS_POSTCLMP_EN] = 0x00,
6464
6465 .reg_init_values[MSM_SPM_REG_SAW_SLP_CLMP_EN] = 0x01,
6466 .reg_init_values[MSM_SPM_REG_SAW_SLP_RST_EN] = 0x00,
6467 .reg_init_values[MSM_SPM_REG_SAW_SPM_MPM_CFG] = 0x00,
6468
6469 .awake_vlevel = 0xF2,
6470 .retention_vlevel = 0xE0,
6471 .collapse_vlevel = 0x72,
6472 .retention_mid_vlevel = 0xE0,
6473 .collapse_mid_vlevel = 0xE0,
6474
6475 .vctl_timeout_us = 50,
6476};
6477
6478#if defined(CONFIG_TOUCHSCREEN_TSC2007) || \
6479 defined(CONFIG_TOUCHSCREEN_TSC2007_MODULE)
6480
6481#define TSC2007_TS_PEN_INT 20
6482
6483static struct msm_gpio tsc2007_config_data[] = {
6484 { GPIO_CFG(TSC2007_TS_PEN_INT, 0, GPIO_CFG_INPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA),
6485 "tsc2007_irq" },
6486};
6487
6488static struct vreg *vreg_tsc_s3;
6489static struct vreg *vreg_tsc_s2;
6490
6491static int tsc2007_init(void)
6492{
6493 int rc;
6494
6495 vreg_tsc_s3 = vreg_get(NULL, "s3");
6496 if (IS_ERR(vreg_tsc_s3)) {
6497 printk(KERN_ERR "%s: vreg get failed (%ld)\n",
6498 __func__, PTR_ERR(vreg_tsc_s3));
6499 return -ENODEV;
6500 }
6501
6502 rc = vreg_set_level(vreg_tsc_s3, 1800);
6503 if (rc) {
6504 pr_err("%s: vreg_set_level failed \n", __func__);
6505 goto fail_vreg_set_level;
6506 }
6507
6508 rc = vreg_enable(vreg_tsc_s3);
6509 if (rc) {
6510 pr_err("%s: vreg_enable failed \n", __func__);
6511 goto fail_vreg_set_level;
6512 }
6513
6514 vreg_tsc_s2 = vreg_get(NULL, "s2");
6515 if (IS_ERR(vreg_tsc_s2)) {
6516 printk(KERN_ERR "%s: vreg get failed (%ld)\n",
6517 __func__, PTR_ERR(vreg_tsc_s2));
6518 goto fail_vreg_get;
6519 }
6520
6521 rc = vreg_set_level(vreg_tsc_s2, 1300);
6522 if (rc) {
6523 pr_err("%s: vreg_set_level failed \n", __func__);
6524 goto fail_vreg_s2_level;
6525 }
6526
6527 rc = vreg_enable(vreg_tsc_s2);
6528 if (rc) {
6529 pr_err("%s: vreg_enable failed \n", __func__);
6530 goto fail_vreg_s2_level;
6531 }
6532
6533 rc = msm_gpios_request_enable(tsc2007_config_data,
6534 ARRAY_SIZE(tsc2007_config_data));
6535 if (rc) {
6536 pr_err("%s: Unable to request gpios\n", __func__);
6537 goto fail_gpio_req;
6538 }
6539
6540 return 0;
6541
6542fail_gpio_req:
6543 vreg_disable(vreg_tsc_s2);
6544fail_vreg_s2_level:
6545 vreg_put(vreg_tsc_s2);
6546fail_vreg_get:
6547 vreg_disable(vreg_tsc_s3);
6548fail_vreg_set_level:
6549 vreg_put(vreg_tsc_s3);
6550 return rc;
6551}
6552
6553static int tsc2007_get_pendown_state(void)
6554{
6555 int rc;
6556
6557 rc = gpio_get_value(TSC2007_TS_PEN_INT);
6558 if (rc < 0) {
6559 pr_err("%s: MSM GPIO %d read failed\n", __func__,
6560 TSC2007_TS_PEN_INT);
6561 return rc;
6562 }
6563
6564 return (rc == 0 ? 1 : 0);
6565}
6566
6567static void tsc2007_exit(void)
6568{
6569 vreg_disable(vreg_tsc_s3);
6570 vreg_put(vreg_tsc_s3);
6571 vreg_disable(vreg_tsc_s2);
6572 vreg_put(vreg_tsc_s2);
6573
6574 msm_gpios_disable_free(tsc2007_config_data,
6575 ARRAY_SIZE(tsc2007_config_data));
6576}
6577
6578static int tsc2007_power_shutdown(bool enable)
6579{
6580 int rc;
6581
6582 if (enable == false) {
6583 rc = vreg_enable(vreg_tsc_s2);
6584 if (rc) {
6585 pr_err("%s: vreg_enable failed\n", __func__);
6586 return rc;
6587 }
6588 rc = vreg_enable(vreg_tsc_s3);
6589 if (rc) {
6590 pr_err("%s: vreg_enable failed\n", __func__);
6591 vreg_disable(vreg_tsc_s2);
6592 return rc;
6593 }
6594 /* Voltage settling delay */
6595 msleep(20);
6596 } else {
6597 rc = vreg_disable(vreg_tsc_s2);
6598 if (rc) {
6599 pr_err("%s: vreg_disable failed\n", __func__);
6600 return rc;
6601 }
6602 rc = vreg_disable(vreg_tsc_s3);
6603 if (rc) {
6604 pr_err("%s: vreg_disable failed\n", __func__);
6605 vreg_enable(vreg_tsc_s2);
6606 return rc;
6607 }
6608 }
6609
6610 return rc;
6611}
6612
6613static struct tsc2007_platform_data tsc2007_ts_data = {
6614 .model = 2007,
6615 .x_plate_ohms = 300,
6616 .irq_flags = IRQF_TRIGGER_LOW,
6617 .init_platform_hw = tsc2007_init,
6618 .exit_platform_hw = tsc2007_exit,
6619 .power_shutdown = tsc2007_power_shutdown,
6620 .invert_x = true,
6621 .invert_y = true,
6622 /* REVISIT: Temporary fix for reversed pressure */
6623 .invert_z1 = true,
6624 .invert_z2 = true,
6625 .get_pendown_state = tsc2007_get_pendown_state,
6626};
6627
6628static struct i2c_board_info tsc_i2c_board_info[] = {
6629 {
6630 I2C_BOARD_INFO("tsc2007", 0x48),
6631 .irq = MSM_GPIO_TO_INT(TSC2007_TS_PEN_INT),
6632 .platform_data = &tsc2007_ts_data,
6633 },
6634};
6635#endif
6636
6637static const char *vregs_isa1200_name[] = {
6638 "gp7",
6639 "gp10",
6640};
6641
6642static const int vregs_isa1200_val[] = {
6643 1800,
6644 2600,
6645};
6646static struct vreg *vregs_isa1200[ARRAY_SIZE(vregs_isa1200_name)];
6647
6648static int isa1200_power(int vreg_on)
6649{
6650 int i, rc = 0;
6651
6652 for (i = 0; i < ARRAY_SIZE(vregs_isa1200_name); i++) {
6653 if (!vregs_isa1200[i]) {
6654 pr_err("%s: vreg_get %s failed (%d)\n",
6655 __func__, vregs_isa1200_name[i], rc);
6656 goto vreg_fail;
6657 }
6658
6659 rc = vreg_on ? vreg_enable(vregs_isa1200[i]) :
6660 vreg_disable(vregs_isa1200[i]);
6661 if (rc < 0) {
6662 pr_err("%s: vreg %s %s failed (%d)\n",
6663 __func__, vregs_isa1200_name[i],
6664 vreg_on ? "enable" : "disable", rc);
6665 goto vreg_fail;
6666 }
6667 }
6668
6669 /* vote for DO buffer */
6670 rc = pmapp_clock_vote("VIBR", PMAPP_CLOCK_ID_DO,
6671 vreg_on ? PMAPP_CLOCK_VOTE_ON : PMAPP_CLOCK_VOTE_OFF);
6672 if (rc) {
6673 pr_err("%s: unable to %svote for d0 clk\n",
6674 __func__, vreg_on ? "" : "de-");
6675 goto vreg_fail;
6676 }
6677
6678 return 0;
6679
6680vreg_fail:
6681 while (i)
6682 vreg_disable(vregs_isa1200[--i]);
6683 return rc;
6684}
6685
6686static int isa1200_dev_setup(bool enable)
6687{
6688 int i, rc;
6689
6690 if (enable == true) {
6691 for (i = 0; i < ARRAY_SIZE(vregs_isa1200_name); i++) {
6692 vregs_isa1200[i] = vreg_get(NULL,
6693 vregs_isa1200_name[i]);
6694 if (IS_ERR(vregs_isa1200[i])) {
6695 pr_err("%s: vreg get %s failed (%ld)\n",
6696 __func__, vregs_isa1200_name[i],
6697 PTR_ERR(vregs_isa1200[i]));
6698 rc = PTR_ERR(vregs_isa1200[i]);
6699 goto vreg_get_fail;
6700 }
6701 rc = vreg_set_level(vregs_isa1200[i],
6702 vregs_isa1200_val[i]);
6703 if (rc) {
6704 pr_err("%s: vreg_set_level() = %d\n",
6705 __func__, rc);
6706 goto vreg_get_fail;
6707 }
6708 }
6709
6710 rc = gpio_tlmm_config(GPIO_CFG(HAP_LVL_SHFT_MSM_GPIO, 0,
6711 GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL,
6712 GPIO_CFG_2MA), GPIO_CFG_ENABLE);
6713 if (rc) {
6714 pr_err("%s: Could not configure gpio %d\n",
6715 __func__, HAP_LVL_SHFT_MSM_GPIO);
6716 goto vreg_get_fail;
6717 }
6718
6719 rc = gpio_request(HAP_LVL_SHFT_MSM_GPIO, "haptics_shft_lvl_oe");
6720 if (rc) {
6721 pr_err("%s: unable to request gpio %d (%d)\n",
6722 __func__, HAP_LVL_SHFT_MSM_GPIO, rc);
6723 goto vreg_get_fail;
6724 }
6725
6726 gpio_set_value(HAP_LVL_SHFT_MSM_GPIO, 1);
6727 } else {
6728 for (i = 0; i < ARRAY_SIZE(vregs_isa1200_name); i++)
6729 vreg_put(vregs_isa1200[i]);
6730
6731 gpio_free(HAP_LVL_SHFT_MSM_GPIO);
6732 }
6733
6734 return 0;
6735vreg_get_fail:
6736 while (i)
6737 vreg_put(vregs_isa1200[--i]);
6738 return rc;
6739}
6740static struct isa1200_platform_data isa1200_1_pdata = {
6741 .name = "vibrator",
6742 .power_on = isa1200_power,
6743 .dev_setup = isa1200_dev_setup,
6744 .pwm_ch_id = 1, /*channel id*/
6745 /*gpio to enable haptic*/
6746 .hap_en_gpio = PM8058_GPIO_PM_TO_SYS(PMIC_GPIO_HAP_ENABLE),
6747 .max_timeout = 15000,
6748 .mode_ctrl = PWM_GEN_MODE,
6749 .pwm_fd = {
6750 .pwm_div = 256,
6751 },
6752 .is_erm = false,
6753 .smart_en = true,
6754 .ext_clk_en = true,
6755 .chip_en = 1,
6756};
6757
6758static struct i2c_board_info msm_isa1200_board_info[] = {
6759 {
6760 I2C_BOARD_INFO("isa1200_1", 0x90>>1),
6761 .platform_data = &isa1200_1_pdata,
6762 },
6763};
6764
6765
6766static int kp_flip_mpp_config(void)
6767{
6768 return pm8058_mpp_config_digital_in(PM_FLIP_MPP,
6769 PM8058_MPP_DIG_LEVEL_S3, PM_MPP_DIN_TO_INT);
6770}
6771
6772static struct flip_switch_pdata flip_switch_data = {
6773 .name = "kp_flip_switch",
6774 .flip_gpio = PM8058_GPIO_PM_TO_SYS(PM8058_GPIOS) + PM_FLIP_MPP,
6775 .left_key = KEY_OPEN,
6776 .right_key = KEY_CLOSE,
6777 .active_low = 0,
6778 .wakeup = 1,
6779 .flip_mpp_config = kp_flip_mpp_config,
6780};
6781
6782static struct platform_device flip_switch_device = {
6783 .name = "kp_flip_switch",
6784 .id = -1,
6785 .dev = {
6786 .platform_data = &flip_switch_data,
6787 }
6788};
6789
6790static const char *vregs_tma300_name[] = {
6791 "gp6",
6792 "gp7",
6793};
6794
6795static const int vregs_tma300_val[] = {
6796 3050,
6797 1800,
6798};
6799static struct vreg *vregs_tma300[ARRAY_SIZE(vregs_tma300_name)];
6800
6801static int tma300_power(int vreg_on)
6802{
6803 int i, rc = -EINVAL;
6804
6805 for (i = 0; i < ARRAY_SIZE(vregs_tma300_name); i++) {
6806 /* Never disable gp6 for fluid as lcd has a problem with it */
6807 if (!i && !vreg_on)
6808 continue;
6809 if (!vregs_tma300[i]) {
6810 printk(KERN_ERR "%s: vreg_get %s failed (%d)\n",
6811 __func__, vregs_tma300_name[i], rc);
6812 return rc;
6813 }
6814
6815 rc = vreg_on ? vreg_enable(vregs_tma300[i]) :
6816 vreg_disable(vregs_tma300[i]);
6817 if (rc < 0) {
6818 printk(KERN_ERR "%s: vreg %s %s failed (%d)\n",
6819 __func__, vregs_tma300_name[i],
6820 vreg_on ? "enable" : "disable", rc);
6821 return rc;
6822 }
6823 }
6824
6825 return 0;
6826}
6827
6828#define TS_GPIO_IRQ 150
6829
6830static int tma300_dev_setup(bool enable)
6831{
6832 int i, rc;
6833
6834 if (enable) {
6835 /* get voltage sources */
6836 for (i = 0; i < ARRAY_SIZE(vregs_tma300_name); i++) {
6837 vregs_tma300[i] = vreg_get(NULL, vregs_tma300_name[i]);
6838 if (IS_ERR(vregs_tma300[i])) {
6839 pr_err("%s: vreg get %s failed (%ld)\n",
6840 __func__, vregs_tma300_name[i],
6841 PTR_ERR(vregs_tma300[i]));
6842 rc = PTR_ERR(vregs_tma300[i]);
6843 goto vreg_get_fail;
6844 }
6845 rc = vreg_set_level(vregs_tma300[i],
6846 vregs_tma300_val[i]);
6847 if (rc) {
6848 pr_err("%s: vreg_set_level() = %d\n",
6849 __func__, rc);
6850 i++;
6851 goto vreg_get_fail;
6852 }
6853 }
6854
6855 /* enable interrupt gpio */
6856 rc = gpio_tlmm_config(GPIO_CFG(TS_GPIO_IRQ, 0, GPIO_CFG_INPUT,
6857 GPIO_CFG_PULL_UP, GPIO_CFG_6MA), GPIO_CFG_ENABLE);
6858 if (rc) {
6859 pr_err("%s: Could not configure gpio %d\n",
6860 __func__, TS_GPIO_IRQ);
6861 goto vreg_get_fail;
6862 }
6863
6864 /* virtual keys */
6865 tma300_vkeys_attr.attr.name = "virtualkeys.msm_tma300_ts";
6866 properties_kobj = kobject_create_and_add("board_properties",
6867 NULL);
6868 if (!properties_kobj) {
6869 pr_err("%s: failed to create a kobject"
6870 "for board_properites\n", __func__);
6871 rc = -ENOMEM;
6872 goto vreg_get_fail;
6873 }
6874 rc = sysfs_create_group(properties_kobj,
6875 &tma300_properties_attr_group);
6876 if (rc) {
6877 pr_err("%s: failed to create a sysfs entry %s\n",
6878 __func__, tma300_vkeys_attr.attr.name);
6879 kobject_put(properties_kobj);
6880 goto vreg_get_fail;
6881 }
6882 } else {
6883 /* put voltage sources */
6884 for (i = 0; i < ARRAY_SIZE(vregs_tma300_name); i++)
6885 vreg_put(vregs_tma300[i]);
6886 /* destroy virtual keys */
6887 if (properties_kobj) {
6888 sysfs_remove_group(properties_kobj,
6889 &tma300_properties_attr_group);
6890 kobject_put(properties_kobj);
6891 }
6892 }
6893 return 0;
6894
6895vreg_get_fail:
6896 while (i)
6897 vreg_put(vregs_tma300[--i]);
6898 return rc;
6899}
6900
6901static struct cy8c_ts_platform_data cy8ctma300_pdata = {
6902 .power_on = tma300_power,
6903 .dev_setup = tma300_dev_setup,
6904 .ts_name = "msm_tma300_ts",
6905 .dis_min_x = 0,
6906 .dis_max_x = 479,
6907 .dis_min_y = 0,
6908 .dis_max_y = 799,
6909 .res_x = 479,
6910 .res_y = 1009,
6911 .min_tid = 1,
6912 .max_tid = 255,
6913 .min_touch = 0,
6914 .max_touch = 255,
6915 .min_width = 0,
6916 .max_width = 255,
6917 .invert_y = 1,
6918 .nfingers = 4,
6919 .irq_gpio = TS_GPIO_IRQ,
6920 .resout_gpio = -1,
6921};
6922
6923static struct i2c_board_info cy8ctma300_board_info[] = {
6924 {
6925 I2C_BOARD_INFO("cy8ctma300", 0x2),
6926 .platform_data = &cy8ctma300_pdata,
6927 }
6928};
6929
Daniel Walker8d747cd2010-02-25 11:37:43 -08006930static void __init msm7x30_init(void)
6931{
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07006932 int rc;
6933 unsigned smem_size;
6934 uint32_t usb_hub_gpio_cfg_value = GPIO_CFG(56,
6935 0,
6936 GPIO_CFG_OUTPUT,
6937 GPIO_CFG_NO_PULL,
6938 GPIO_CFG_2MA);
6939 uint32_t soc_version = 0;
Pavankumar Kondeti5155e2c2010-12-08 13:37:08 +05306940
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07006941 soc_version = socinfo_get_version();
6942
Stephen Boydbb600ae2011-08-02 20:11:40 -07006943 msm_clock_init(&msm7x30_clock_init_data);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07006944#ifdef CONFIG_SERIAL_MSM_CONSOLE
6945 msm7x30_init_uart2();
6946#endif
6947 msm_spm_init(&msm_spm_data, 1);
Matt Wagantallec57f062011-08-16 23:54:46 -07006948 acpuclk_init(&acpuclk_7x30_soc_data);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07006949 if (machine_is_msm7x30_surf() || machine_is_msm7x30_fluid())
6950 msm7x30_cfg_smsc911x();
6951
6952#ifdef CONFIG_USB_MSM_OTG_72K
6953 if (SOCINFO_VERSION_MAJOR(soc_version) >= 2 &&
6954 SOCINFO_VERSION_MINOR(soc_version) >= 1) {
6955 pr_debug("%s: SOC Version:2.(1 or more)\n", __func__);
6956 msm_otg_pdata.ldo_set_voltage = 0;
6957 }
6958
6959 msm_device_otg.dev.platform_data = &msm_otg_pdata;
6960#ifdef CONFIG_USB_GADGET
6961 msm_otg_pdata.swfi_latency =
6962 msm_pm_data
6963 [MSM_PM_SLEEP_MODE_RAMP_DOWN_AND_WAIT_FOR_INTERRUPT].latency;
6964 msm_device_gadget_peripheral.dev.platform_data = &msm_gadget_pdata;
6965#endif
6966#endif
6967 msm_uart_dm1_pdata.wakeup_irq = gpio_to_irq(136);
6968 msm_device_uart_dm1.dev.platform_data = &msm_uart_dm1_pdata;
6969#if defined(CONFIG_TSIF) || defined(CONFIG_TSIF_MODULE)
6970 msm_device_tsif.dev.platform_data = &tsif_platform_data;
6971#endif
6972 if (machine_is_msm7x30_fluid()) {
6973 msm_adc_pdata.dev_names = msm_adc_fluid_device_names;
6974 msm_adc_pdata.num_adc = ARRAY_SIZE(msm_adc_fluid_device_names);
6975 } else {
6976 msm_adc_pdata.dev_names = msm_adc_surf_device_names;
6977 msm_adc_pdata.num_adc = ARRAY_SIZE(msm_adc_surf_device_names);
6978 }
6979
Anirudh Ghayal9d9cdc22011-10-10 17:17:07 +05306980#ifdef CONFIG_MSM_SSBI
6981 msm_device_ssbi_pmic1.dev.platform_data =
6982 &msm7x30_ssbi_pm8058_pdata;
6983#endif
6984
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07006985 platform_add_devices(msm_footswitch_devices,
6986 msm_num_footswitch_devices);
Daniel Walker8d747cd2010-02-25 11:37:43 -08006987 platform_add_devices(devices, ARRAY_SIZE(devices));
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07006988#ifdef CONFIG_USB_EHCI_MSM_72K
6989 msm_add_host(0, &msm_usb_host_pdata);
6990#endif
6991 msm7x30_init_mmc();
6992 msm7x30_init_nand();
6993 msm_qsd_spi_init();
6994
6995#ifdef CONFIG_SPI_QSD
6996 if (machine_is_msm7x30_fluid())
6997 spi_register_board_info(lcdc_sharp_spi_board_info,
6998 ARRAY_SIZE(lcdc_sharp_spi_board_info));
6999 else
7000 spi_register_board_info(lcdc_toshiba_spi_board_info,
7001 ARRAY_SIZE(lcdc_toshiba_spi_board_info));
7002#endif
7003
7004 msm_fb_add_devices();
7005 msm_pm_set_platform_data(msm_pm_data, ARRAY_SIZE(msm_pm_data));
Maheshkumar Sivasubramanian8ccc16e2011-10-25 15:59:57 -06007006 BUG_ON(msm_pm_boot_init(MSM_PM_BOOT_CONFIG_RESET_VECTOR,
7007 (uint32_t *)PAGE_OFFSET));
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07007008 msm_device_i2c_init();
7009 msm_device_i2c_2_init();
7010 qup_device_i2c_init();
7011 buses_init();
7012 msm7x30_init_marimba();
7013#ifdef CONFIG_MSM7KV2_AUDIO
7014 snddev_poweramp_gpio_init();
7015 aux_pcm_gpio_init();
7016#endif
7017
7018 i2c_register_board_info(0, msm_i2c_board_info,
7019 ARRAY_SIZE(msm_i2c_board_info));
7020
7021 if (!machine_is_msm8x55_svlte_ffa() && !machine_is_msm7x30_fluid())
7022 marimba_pdata.tsadc = &marimba_tsadc_pdata;
7023
7024 if (machine_is_msm7x30_fluid())
7025 i2c_register_board_info(0, cy8info,
7026 ARRAY_SIZE(cy8info));
7027#ifdef CONFIG_BOSCH_BMA150
7028 if (machine_is_msm7x30_fluid())
7029 i2c_register_board_info(0, bma150_board_info,
7030 ARRAY_SIZE(bma150_board_info));
7031#endif
7032
7033 i2c_register_board_info(2, msm_marimba_board_info,
7034 ARRAY_SIZE(msm_marimba_board_info));
7035
7036 i2c_register_board_info(2, msm_i2c_gsbi7_timpani_info,
7037 ARRAY_SIZE(msm_i2c_gsbi7_timpani_info));
7038
7039 i2c_register_board_info(4 /* QUP ID */, msm_camera_boardinfo,
7040 ARRAY_SIZE(msm_camera_boardinfo));
7041
7042 bt_power_init();
7043#ifdef CONFIG_I2C_SSBI
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07007044 msm_device_ssbi7.dev.platform_data = &msm_i2c_ssbi7_pdata;
7045#endif
7046 if (machine_is_msm7x30_fluid())
7047 i2c_register_board_info(0, msm_isa1200_board_info,
7048 ARRAY_SIZE(msm_isa1200_board_info));
7049
7050#if defined(CONFIG_TOUCHSCREEN_TSC2007) || \
7051 defined(CONFIG_TOUCHSCREEN_TSC2007_MODULE)
7052 if (machine_is_msm8x55_svlte_ffa())
7053 i2c_register_board_info(2, tsc_i2c_board_info,
7054 ARRAY_SIZE(tsc_i2c_board_info));
7055#endif
7056
7057 if (machine_is_msm7x30_surf())
7058 platform_device_register(&flip_switch_device);
7059 pmic8058_leds_init();
7060
7061 if (machine_is_msm7x30_fluid()) {
7062 /* Initialize platform data for fluid v2 hardware */
7063 if (SOCINFO_VERSION_MAJOR(
7064 socinfo_get_platform_version()) == 2) {
7065 cy8ctma300_pdata.res_y = 920;
7066 cy8ctma300_pdata.invert_y = 0;
7067 }
7068 i2c_register_board_info(0, cy8ctma300_board_info,
7069 ARRAY_SIZE(cy8ctma300_board_info));
7070 }
7071
7072 if (machine_is_msm8x55_svlte_surf() || machine_is_msm8x55_svlte_ffa()) {
7073 rc = gpio_tlmm_config(usb_hub_gpio_cfg_value, GPIO_CFG_ENABLE);
7074 if (rc)
7075 pr_err("%s: gpio_tlmm_config(%#x)=%d\n",
7076 __func__, usb_hub_gpio_cfg_value, rc);
7077 }
7078
7079 boot_reason = *(unsigned int *)
7080 (smem_get_entry(SMEM_POWER_ON_STATUS_INFO, &smem_size));
7081 printk(KERN_NOTICE "Boot Reason = 0x%02x\n", boot_reason);
7082}
7083
7084static unsigned pmem_sf_size = MSM_PMEM_SF_SIZE;
7085static int __init pmem_sf_size_setup(char *p)
7086{
7087 pmem_sf_size = memparse(p, NULL);
7088 return 0;
7089}
7090early_param("pmem_sf_size", pmem_sf_size_setup);
7091
7092static unsigned fb_size = MSM_FB_SIZE;
7093static int __init fb_size_setup(char *p)
7094{
7095 fb_size = memparse(p, NULL);
7096 return 0;
7097}
7098early_param("fb_size", fb_size_setup);
7099
7100static unsigned pmem_adsp_size = MSM_PMEM_ADSP_SIZE;
7101static int __init pmem_adsp_size_setup(char *p)
7102{
7103 pmem_adsp_size = memparse(p, NULL);
7104 return 0;
7105}
7106early_param("pmem_adsp_size", pmem_adsp_size_setup);
7107
7108static unsigned fluid_pmem_adsp_size = MSM_FLUID_PMEM_ADSP_SIZE;
7109static int __init fluid_pmem_adsp_size_setup(char *p)
7110{
7111 fluid_pmem_adsp_size = memparse(p, NULL);
7112 return 0;
7113}
7114early_param("fluid_pmem_adsp_size", fluid_pmem_adsp_size_setup);
7115
7116static unsigned pmem_audio_size = MSM_PMEM_AUDIO_SIZE;
7117static int __init pmem_audio_size_setup(char *p)
7118{
7119 pmem_audio_size = memparse(p, NULL);
7120 return 0;
7121}
7122early_param("pmem_audio_size", pmem_audio_size_setup);
7123
7124static unsigned pmem_kernel_ebi0_size = PMEM_KERNEL_EBI0_SIZE;
7125static int __init pmem_kernel_ebi0_size_setup(char *p)
7126{
7127 pmem_kernel_ebi0_size = memparse(p, NULL);
7128 return 0;
7129}
7130early_param("pmem_kernel_ebi0_size", pmem_kernel_ebi0_size_setup);
7131
7132static struct memtype_reserve msm7x30_reserve_table[] __initdata = {
7133 [MEMTYPE_SMI] = {
7134 },
7135 [MEMTYPE_EBI0] = {
7136 .flags = MEMTYPE_FLAGS_1M_ALIGN,
7137 },
7138 [MEMTYPE_EBI1] = {
7139 .flags = MEMTYPE_FLAGS_1M_ALIGN,
7140 },
7141};
7142
7143static void __init size_pmem_devices(void)
7144{
7145#ifdef CONFIG_ANDROID_PMEM
7146 unsigned long size;
7147
7148 if machine_is_msm7x30_fluid()
7149 size = fluid_pmem_adsp_size;
7150 else
7151 size = pmem_adsp_size;
7152 android_pmem_adsp_pdata.size = size;
7153 android_pmem_audio_pdata.size = pmem_audio_size;
7154 android_pmem_pdata.size = pmem_sf_size;
7155#endif
7156}
7157
7158static void __init reserve_memory_for(struct android_pmem_platform_data *p)
7159{
7160 msm7x30_reserve_table[p->memory_type].size += p->size;
7161}
7162
7163static void __init reserve_pmem_memory(void)
7164{
7165#ifdef CONFIG_ANDROID_PMEM
7166 reserve_memory_for(&android_pmem_adsp_pdata);
7167 reserve_memory_for(&android_pmem_audio_pdata);
7168 reserve_memory_for(&android_pmem_pdata);
7169 msm7x30_reserve_table[MEMTYPE_EBI0].size += pmem_kernel_ebi0_size;
7170#endif
7171}
7172
7173static void __init msm7x30_calculate_reserve_sizes(void)
7174{
7175 size_pmem_devices();
7176 reserve_pmem_memory();
7177}
7178
7179static int msm7x30_paddr_to_memtype(unsigned int paddr)
7180{
7181 if (paddr < 0x40000000)
7182 return MEMTYPE_EBI0;
7183 if (paddr >= 0x40000000 && paddr < 0x80000000)
7184 return MEMTYPE_EBI1;
7185 return MEMTYPE_NONE;
7186}
7187
7188static struct reserve_info msm7x30_reserve_info __initdata = {
7189 .memtype_reserve_table = msm7x30_reserve_table,
7190 .calculate_reserve_sizes = msm7x30_calculate_reserve_sizes,
7191 .paddr_to_memtype = msm7x30_paddr_to_memtype,
7192};
7193
7194static void __init msm7x30_reserve(void)
7195{
7196 reserve_info = &msm7x30_reserve_info;
7197 msm_reserve();
7198}
7199
7200static void __init msm7x30_allocate_memory_regions(void)
7201{
7202 void *addr;
7203 unsigned long size;
7204
7205 size = fb_size ? : MSM_FB_SIZE;
7206 addr = alloc_bootmem_align(size, 0x1000);
7207 msm_fb_resources[0].start = __pa(addr);
7208 msm_fb_resources[0].end = msm_fb_resources[0].start + size - 1;
7209 pr_info("allocating %lu bytes at %p (%lx physical) for fb\n",
7210 size, addr, __pa(addr));
Daniel Walker8d747cd2010-02-25 11:37:43 -08007211}
7212
7213static void __init msm7x30_map_io(void)
7214{
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07007215 msm_shared_ram_phys = 0x00100000;
Daniel Walker8d747cd2010-02-25 11:37:43 -08007216 msm_map_msm7x30_io();
Jeff Ohlstein3a77f9f2011-09-06 14:50:20 -07007217 if (socinfo_init() < 0)
7218 printk(KERN_ERR "%s: socinfo_init() failed!\n",
7219 __func__);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07007220}
7221
7222static void __init msm7x30_init_early(void)
7223{
7224 msm7x30_allocate_memory_regions();
Daniel Walker8d747cd2010-02-25 11:37:43 -08007225}
7226
7227MACHINE_START(MSM7X30_SURF, "QCT MSM7X30 SURF")
Russell Kingb75c1782011-01-04 19:03:16 +00007228 .boot_params = PLAT_PHYS_OFFSET + 0x100,
Daniel Walker8d747cd2010-02-25 11:37:43 -08007229 .map_io = msm7x30_map_io,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07007230 .reserve = msm7x30_reserve,
Daniel Walker8d747cd2010-02-25 11:37:43 -08007231 .init_irq = msm7x30_init_irq,
7232 .init_machine = msm7x30_init,
7233 .timer = &msm_timer,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07007234 .init_early = msm7x30_init_early,
Taniya Dasbae99fb2011-10-12 09:55:13 +05307235 .handle_irq = vic_handle_irq,
Daniel Walker8d747cd2010-02-25 11:37:43 -08007236MACHINE_END
7237
7238MACHINE_START(MSM7X30_FFA, "QCT MSM7X30 FFA")
Russell Kingb75c1782011-01-04 19:03:16 +00007239 .boot_params = PLAT_PHYS_OFFSET + 0x100,
Daniel Walker8d747cd2010-02-25 11:37:43 -08007240 .map_io = msm7x30_map_io,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07007241 .reserve = msm7x30_reserve,
Daniel Walker8d747cd2010-02-25 11:37:43 -08007242 .init_irq = msm7x30_init_irq,
7243 .init_machine = msm7x30_init,
7244 .timer = &msm_timer,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07007245 .init_early = msm7x30_init_early,
Taniya Dasbae99fb2011-10-12 09:55:13 +05307246 .handle_irq = vic_handle_irq,
Daniel Walker8d747cd2010-02-25 11:37:43 -08007247MACHINE_END
7248
7249MACHINE_START(MSM7X30_FLUID, "QCT MSM7X30 FLUID")
Russell Kingb75c1782011-01-04 19:03:16 +00007250 .boot_params = PLAT_PHYS_OFFSET + 0x100,
Daniel Walker8d747cd2010-02-25 11:37:43 -08007251 .map_io = msm7x30_map_io,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07007252 .reserve = msm7x30_reserve,
Daniel Walker8d747cd2010-02-25 11:37:43 -08007253 .init_irq = msm7x30_init_irq,
7254 .init_machine = msm7x30_init,
7255 .timer = &msm_timer,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07007256 .init_early = msm7x30_init_early,
Taniya Dasbae99fb2011-10-12 09:55:13 +05307257 .handle_irq = vic_handle_irq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07007258MACHINE_END
7259
7260MACHINE_START(MSM8X55_SURF, "QCT MSM8X55 SURF")
7261 .boot_params = PHYS_OFFSET + 0x100,
7262 .map_io = msm7x30_map_io,
7263 .reserve = msm7x30_reserve,
7264 .init_irq = msm7x30_init_irq,
7265 .init_machine = msm7x30_init,
7266 .timer = &msm_timer,
7267 .init_early = msm7x30_init_early,
Taniya Dasbae99fb2011-10-12 09:55:13 +05307268 .handle_irq = vic_handle_irq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07007269MACHINE_END
7270
7271MACHINE_START(MSM8X55_FFA, "QCT MSM8X55 FFA")
7272 .boot_params = PHYS_OFFSET + 0x100,
7273 .map_io = msm7x30_map_io,
7274 .reserve = msm7x30_reserve,
7275 .init_irq = msm7x30_init_irq,
7276 .init_machine = msm7x30_init,
7277 .timer = &msm_timer,
7278 .init_early = msm7x30_init_early,
Taniya Dasbae99fb2011-10-12 09:55:13 +05307279 .handle_irq = vic_handle_irq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07007280MACHINE_END
7281MACHINE_START(MSM8X55_SVLTE_SURF, "QCT MSM8X55 SVLTE SURF")
7282 .boot_params = PHYS_OFFSET + 0x100,
7283 .map_io = msm7x30_map_io,
7284 .reserve = msm7x30_reserve,
7285 .init_irq = msm7x30_init_irq,
7286 .init_machine = msm7x30_init,
7287 .timer = &msm_timer,
7288 .init_early = msm7x30_init_early,
Taniya Dasbae99fb2011-10-12 09:55:13 +05307289 .handle_irq = vic_handle_irq,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07007290MACHINE_END
7291MACHINE_START(MSM8X55_SVLTE_FFA, "QCT MSM8X55 SVLTE FFA")
7292 .boot_params = PHYS_OFFSET + 0x100,
7293 .map_io = msm7x30_map_io,
7294 .reserve = msm7x30_reserve,
7295 .init_irq = msm7x30_init_irq,
7296 .init_machine = msm7x30_init,
7297 .timer = &msm_timer,
7298 .init_early = msm7x30_init_early,
Taniya Dasbae99fb2011-10-12 09:55:13 +05307299 .handle_irq = vic_handle_irq,
Daniel Walker8d747cd2010-02-25 11:37:43 -08007300MACHINE_END