blob: af526ab9ec04205239f5d580aec7ce30323dc9e2 [file] [log] [blame]
Linus Torvalds1da177e2005-04-16 15:20:36 -07001#ifndef _I8042_H
2#define _I8042_H
3
Linus Torvalds1da177e2005-04-16 15:20:36 -07004
5/*
6 * Copyright (c) 1999-2002 Vojtech Pavlik
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License version 2 as published by
10 * the Free Software Foundation.
11 */
12
13/*
14 * Arch-dependent inline functions and defines.
15 */
16
17#if defined(CONFIG_MACH_JAZZ)
18#include "i8042-jazzio.h"
19#elif defined(CONFIG_SGI_IP22)
20#include "i8042-ip22io.h"
21#elif defined(CONFIG_PPC)
22#include "i8042-ppcio.h"
Adrian Bunk0b57ee92005-12-22 21:03:47 -080023#elif defined(CONFIG_SPARC)
Linus Torvalds1da177e2005-04-16 15:20:36 -070024#include "i8042-sparcio.h"
25#elif defined(CONFIG_X86) || defined(CONFIG_IA64)
26#include "i8042-x86ia64io.h"
27#else
28#include "i8042-io.h"
29#endif
30
31/*
32 * This is in 50us units, the time we wait for the i8042 to react. This
33 * has to be long enough for the i8042 itself to timeout on sending a byte
34 * to a non-existent mouse.
35 */
36
37#define I8042_CTL_TIMEOUT 10000
38
39/*
40 * When the device isn't opened and it's interrupts aren't used, we poll it at
41 * regular intervals to see if any characters arrived. If yes, we can start
42 * probing for any mouse / keyboard connected. This is the period of the
43 * polling.
44 */
45
46#define I8042_POLL_PERIOD HZ/20
47
48/*
49 * Status register bits.
50 */
51
52#define I8042_STR_PARITY 0x80
53#define I8042_STR_TIMEOUT 0x40
54#define I8042_STR_AUXDATA 0x20
55#define I8042_STR_KEYLOCK 0x10
56#define I8042_STR_CMDDAT 0x08
57#define I8042_STR_MUXERR 0x04
58#define I8042_STR_IBF 0x02
59#define I8042_STR_OBF 0x01
60
61/*
62 * Control register bits.
63 */
64
65#define I8042_CTR_KBDINT 0x01
66#define I8042_CTR_AUXINT 0x02
67#define I8042_CTR_IGNKEYLOCK 0x08
68#define I8042_CTR_KBDDIS 0x10
69#define I8042_CTR_AUXDIS 0x20
70#define I8042_CTR_XLATE 0x40
71
72/*
73 * Commands.
74 */
75
76#define I8042_CMD_CTL_RCTR 0x0120
77#define I8042_CMD_CTL_WCTR 0x1060
78#define I8042_CMD_CTL_TEST 0x01aa
79
80#define I8042_CMD_KBD_DISABLE 0x00ad
81#define I8042_CMD_KBD_ENABLE 0x00ae
82#define I8042_CMD_KBD_TEST 0x01ab
83#define I8042_CMD_KBD_LOOP 0x11d2
84
85#define I8042_CMD_AUX_DISABLE 0x00a7
86#define I8042_CMD_AUX_ENABLE 0x00a8
87#define I8042_CMD_AUX_TEST 0x01a9
88#define I8042_CMD_AUX_SEND 0x10d4
89#define I8042_CMD_AUX_LOOP 0x11d3
90
91#define I8042_CMD_MUX_PFX 0x0090
92#define I8042_CMD_MUX_SEND 0x1090
93
94/*
95 * Return codes.
96 */
97
98#define I8042_RET_CTL_TEST 0x55
99
100/*
101 * Expected maximum internal i8042 buffer size. This is used for flushing
102 * the i8042 buffers.
103 */
104
105#define I8042_BUFFER_SIZE 16
106
107/*
108 * Number of AUX ports on controllers supporting active multiplexing
109 * specification
110 */
111
112#define I8042_NUM_MUX_PORTS 4
113
114/*
115 * Debug.
116 */
117
118#ifdef DEBUG
119static unsigned long i8042_start_time;
120#define dbg_init() do { i8042_start_time = jiffies; } while (0)
121#define dbg(format, arg...) \
122 do { \
123 if (i8042_debug) \
124 printk(KERN_DEBUG __FILE__ ": " format " [%d]\n" , \
125 ## arg, (int) (jiffies - i8042_start_time)); \
126 } while (0)
127#else
128#define dbg_init() do { } while (0)
129#define dbg(format, arg...) do {} while (0)
130#endif
131
132#endif /* _I8042_H */