blob: 85785fc5992e669aab0eef098ef893e87632527b [file] [log] [blame]
Terence Hampson2e1705f2012-04-11 19:55:29 -04001/* Copyright (c) 2011-2012, Code Aurora Forum. All rights reserved.
Stepan Moskovchenko0c547bb2011-11-30 13:29:12 -08002 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 *
12 */
13
14#include <linux/init.h>
15#include <linux/ioport.h>
16#include <linux/platform_device.h>
17#include <linux/bootmem.h>
Steve Mucklef132c6c2012-06-06 18:30:57 -070018#include <linux/gpio.h>
Stepan Moskovchenko0c547bb2011-11-30 13:29:12 -080019#include <asm/mach-types.h>
20#include <asm/mach/mmc.h>
Stepan Moskovchenko0c547bb2011-11-30 13:29:12 -080021#include <mach/board.h>
Stepan Moskovchenko0c547bb2011-11-30 13:29:12 -080022#include <mach/gpiomux.h>
23#include "devices.h"
Stepan Moskovchenko5a83dba2011-12-05 17:30:17 -080024#include "board-8960.h"
Subhash Jadavanibcd435f2012-04-24 18:26:49 +053025#include "board-storage-common-a.h"
Stepan Moskovchenko0c547bb2011-11-30 13:29:12 -080026
27/* MSM8960 has 5 SDCC controllers */
28enum sdcc_controllers {
29 SDCC1,
30 SDCC2,
31 SDCC3,
32 SDCC4,
33 SDCC5,
34 MAX_SDCC_CONTROLLER
35};
36
37/* All SDCC controllers require VDD/VCC voltage */
38static struct msm_mmc_reg_data mmc_vdd_reg_data[MAX_SDCC_CONTROLLER] = {
39 /* SDCC1 : eMMC card connected */
40 [SDCC1] = {
41 .name = "sdc_vdd",
42 .high_vol_level = 2950000,
43 .low_vol_level = 2950000,
44 .always_on = 1,
45 .lpm_sup = 1,
46 .lpm_uA = 9000,
47 .hpm_uA = 200000, /* 200mA */
48 },
Pratibhasagar V57c808e2012-01-12 13:47:30 +053049 /* SDCC2 : SDIO slot connected */
50 [SDCC2] = {
51 .name = "sdc_vdd",
52 .high_vol_level = 1800000,
53 .low_vol_level = 1800000,
54 .always_on = 1,
55 .lpm_sup = 1,
56 .lpm_uA = 9000,
57 .hpm_uA = 200000, /* 200mA */
58 },
Stepan Moskovchenko0c547bb2011-11-30 13:29:12 -080059 /* SDCC3 : External card slot connected */
60 [SDCC3] = {
61 .name = "sdc_vdd",
62 .high_vol_level = 2950000,
63 .low_vol_level = 2950000,
64 .hpm_uA = 600000, /* 600mA */
65 }
66};
67
Subhash Jadavani937c7502012-06-01 15:34:46 +053068/* SDCC controllers may require voting for IO operating voltage */
69static struct msm_mmc_reg_data mmc_vdd_io_reg_data[MAX_SDCC_CONTROLLER] = {
Stepan Moskovchenko0c547bb2011-11-30 13:29:12 -080070 /* SDCC1 : eMMC card connected */
71 [SDCC1] = {
Subhash Jadavani937c7502012-06-01 15:34:46 +053072 .name = "sdc_vdd_io",
Stepan Moskovchenko0c547bb2011-11-30 13:29:12 -080073 .always_on = 1,
74 .high_vol_level = 1800000,
75 .low_vol_level = 1800000,
76 .hpm_uA = 200000, /* 200mA */
Subhash Jadavani937c7502012-06-01 15:34:46 +053077 },
Stepan Moskovchenko0c547bb2011-11-30 13:29:12 -080078 /* SDCC3 : External card slot connected */
79 [SDCC3] = {
Subhash Jadavani937c7502012-06-01 15:34:46 +053080 .name = "sdc_vdd_io",
Stepan Moskovchenko0c547bb2011-11-30 13:29:12 -080081 .high_vol_level = 2950000,
82 .low_vol_level = 1850000,
83 .always_on = 1,
84 .lpm_sup = 1,
85 /* Max. Active current required is 16 mA */
86 .hpm_uA = 16000,
87 /*
88 * Sleep current required is ~300 uA. But min. vote can be
89 * in terms of mA (min. 1 mA). So let's vote for 2 mA
90 * during sleep.
91 */
92 .lpm_uA = 2000,
Pratibhasagar V26cf2652012-01-12 17:31:21 +053093 },
94 /* SDCC4 : SDIO slot connected */
95 [SDCC4] = {
Subhash Jadavani937c7502012-06-01 15:34:46 +053096 .name = "sdc_vdd_io",
Pratibhasagar V26cf2652012-01-12 17:31:21 +053097 .high_vol_level = 1800000,
98 .low_vol_level = 1800000,
99 .always_on = 1,
100 .lpm_sup = 1,
101 .hpm_uA = 200000, /* 200mA */
102 .lpm_uA = 2000,
103 },
Stepan Moskovchenko0c547bb2011-11-30 13:29:12 -0800104};
105
106static struct msm_mmc_slot_reg_data mmc_slot_vreg_data[MAX_SDCC_CONTROLLER] = {
107 /* SDCC1 : eMMC card connected */
108 [SDCC1] = {
109 .vdd_data = &mmc_vdd_reg_data[SDCC1],
Subhash Jadavani937c7502012-06-01 15:34:46 +0530110 .vdd_io_data = &mmc_vdd_io_reg_data[SDCC1],
Stepan Moskovchenko0c547bb2011-11-30 13:29:12 -0800111 },
Pratibhasagar V57c808e2012-01-12 13:47:30 +0530112 /* SDCC2 : SDIO card slot connected */
113 [SDCC2] = {
114 .vdd_data = &mmc_vdd_reg_data[SDCC2],
115 },
Stepan Moskovchenko0c547bb2011-11-30 13:29:12 -0800116 /* SDCC3 : External card slot connected */
117 [SDCC3] = {
118 .vdd_data = &mmc_vdd_reg_data[SDCC3],
Subhash Jadavani937c7502012-06-01 15:34:46 +0530119 .vdd_io_data = &mmc_vdd_io_reg_data[SDCC3],
Pratibhasagar V26cf2652012-01-12 17:31:21 +0530120 },
121 /* SDCC4 : SDIO card slot connected */
122 [SDCC4] = {
Subhash Jadavani937c7502012-06-01 15:34:46 +0530123 .vdd_io_data = &mmc_vdd_io_reg_data[SDCC4],
Pratibhasagar V26cf2652012-01-12 17:31:21 +0530124 },
Stepan Moskovchenko0c547bb2011-11-30 13:29:12 -0800125};
126
127/* SDC1 pad data */
128static struct msm_mmc_pad_drv sdc1_pad_drv_on_cfg[] = {
129 {TLMM_HDRV_SDC1_CLK, GPIO_CFG_16MA},
130 {TLMM_HDRV_SDC1_CMD, GPIO_CFG_10MA},
131 {TLMM_HDRV_SDC1_DATA, GPIO_CFG_10MA}
132};
133
134static struct msm_mmc_pad_drv sdc1_pad_drv_off_cfg[] = {
135 {TLMM_HDRV_SDC1_CLK, GPIO_CFG_2MA},
136 {TLMM_HDRV_SDC1_CMD, GPIO_CFG_2MA},
137 {TLMM_HDRV_SDC1_DATA, GPIO_CFG_2MA}
138};
139
140static struct msm_mmc_pad_pull sdc1_pad_pull_on_cfg[] = {
141 {TLMM_PULL_SDC1_CLK, GPIO_CFG_NO_PULL},
142 {TLMM_PULL_SDC1_CMD, GPIO_CFG_PULL_UP},
143 {TLMM_PULL_SDC1_DATA, GPIO_CFG_PULL_UP}
144};
145
146static struct msm_mmc_pad_pull sdc1_pad_pull_off_cfg[] = {
147 {TLMM_PULL_SDC1_CLK, GPIO_CFG_NO_PULL},
Subhash Jadavani32a43982012-01-20 16:51:06 +0530148 {TLMM_PULL_SDC1_CMD, GPIO_CFG_PULL_UP},
149 {TLMM_PULL_SDC1_DATA, GPIO_CFG_PULL_UP}
Stepan Moskovchenko0c547bb2011-11-30 13:29:12 -0800150};
151
152/* SDC3 pad data */
153static struct msm_mmc_pad_drv sdc3_pad_drv_on_cfg[] = {
154 {TLMM_HDRV_SDC3_CLK, GPIO_CFG_8MA},
155 {TLMM_HDRV_SDC3_CMD, GPIO_CFG_8MA},
156 {TLMM_HDRV_SDC3_DATA, GPIO_CFG_8MA}
157};
158
159static struct msm_mmc_pad_drv sdc3_pad_drv_off_cfg[] = {
160 {TLMM_HDRV_SDC3_CLK, GPIO_CFG_2MA},
161 {TLMM_HDRV_SDC3_CMD, GPIO_CFG_2MA},
162 {TLMM_HDRV_SDC3_DATA, GPIO_CFG_2MA}
163};
164
165static struct msm_mmc_pad_pull sdc3_pad_pull_on_cfg[] = {
166 {TLMM_PULL_SDC3_CLK, GPIO_CFG_NO_PULL},
167 {TLMM_PULL_SDC3_CMD, GPIO_CFG_PULL_UP},
168 {TLMM_PULL_SDC3_DATA, GPIO_CFG_PULL_UP}
169};
170
171static struct msm_mmc_pad_pull sdc3_pad_pull_off_cfg[] = {
172 {TLMM_PULL_SDC3_CLK, GPIO_CFG_NO_PULL},
173 /*
174 * SDC3 CMD line should be PULLed UP otherwise fluid platform will
175 * see transitions (1 -> 0 and 0 -> 1) on card detection line,
176 * which would result in false card detection interrupts.
177 */
178 {TLMM_PULL_SDC3_CMD, GPIO_CFG_PULL_UP},
179 /*
180 * Keeping DATA lines status to PULL UP will make sure that
181 * there is no current leak during sleep if external pull up
182 * is connected to DATA lines.
183 */
184 {TLMM_PULL_SDC3_DATA, GPIO_CFG_PULL_UP}
185};
186
187static struct msm_mmc_pad_pull_data mmc_pad_pull_data[MAX_SDCC_CONTROLLER] = {
188 [SDCC1] = {
189 .on = sdc1_pad_pull_on_cfg,
190 .off = sdc1_pad_pull_off_cfg,
191 .size = ARRAY_SIZE(sdc1_pad_pull_on_cfg)
192 },
193 [SDCC3] = {
194 .on = sdc3_pad_pull_on_cfg,
195 .off = sdc3_pad_pull_off_cfg,
196 .size = ARRAY_SIZE(sdc3_pad_pull_on_cfg)
197 },
198};
199
200static struct msm_mmc_pad_drv_data mmc_pad_drv_data[MAX_SDCC_CONTROLLER] = {
201 [SDCC1] = {
202 .on = sdc1_pad_drv_on_cfg,
203 .off = sdc1_pad_drv_off_cfg,
204 .size = ARRAY_SIZE(sdc1_pad_drv_on_cfg)
205 },
206 [SDCC3] = {
207 .on = sdc3_pad_drv_on_cfg,
208 .off = sdc3_pad_drv_off_cfg,
209 .size = ARRAY_SIZE(sdc3_pad_drv_on_cfg)
210 },
211};
212
Pratibhasagar V57c808e2012-01-12 13:47:30 +0530213struct msm_mmc_gpio sdc2_gpio[] = {
214 {92, "sdc2_dat_3"},
215 {91, "sdc2_dat_2"},
216 {90, "sdc2_dat_1"},
217 {89, "sdc2_dat_0"},
218 {97, "sdc2_cmd"},
219 {98, "sdc2_clk"}
220};
221
Pratibhasagar V26cf2652012-01-12 17:31:21 +0530222struct msm_mmc_gpio sdc4_gpio[] = {
223 {83, "sdc4_dat_3"},
224 {84, "sdc4_dat_2"},
225 {85, "sdc4_dat_1"},
226 {86, "sdc4_dat_0"},
227 {87, "sdc4_cmd"},
228 {88, "sdc4_clk"}
229};
230
Pratibhasagar V57c808e2012-01-12 13:47:30 +0530231struct msm_mmc_gpio_data mmc_gpio_data[MAX_SDCC_CONTROLLER] = {
232 [SDCC2] = {
233 .gpio = sdc2_gpio,
234 .size = ARRAY_SIZE(sdc2_gpio),
Pratibhasagar V26cf2652012-01-12 17:31:21 +0530235 },
236 [SDCC4] = {
237 .gpio = sdc4_gpio,
238 .size = ARRAY_SIZE(sdc4_gpio),
239 },
Pratibhasagar V57c808e2012-01-12 13:47:30 +0530240};
241
Stepan Moskovchenko0c547bb2011-11-30 13:29:12 -0800242static struct msm_mmc_pad_data mmc_pad_data[MAX_SDCC_CONTROLLER] = {
243 [SDCC1] = {
244 .pull = &mmc_pad_pull_data[SDCC1],
245 .drv = &mmc_pad_drv_data[SDCC1]
246 },
247 [SDCC3] = {
248 .pull = &mmc_pad_pull_data[SDCC3],
249 .drv = &mmc_pad_drv_data[SDCC3]
250 },
251};
252
253static struct msm_mmc_pin_data mmc_slot_pin_data[MAX_SDCC_CONTROLLER] = {
254 [SDCC1] = {
255 .pad_data = &mmc_pad_data[SDCC1],
256 },
Pratibhasagar V57c808e2012-01-12 13:47:30 +0530257 [SDCC2] = {
258 .is_gpio = 1,
259 .gpio_data = &mmc_gpio_data[SDCC2],
260 },
Stepan Moskovchenko0c547bb2011-11-30 13:29:12 -0800261 [SDCC3] = {
262 .pad_data = &mmc_pad_data[SDCC3],
263 },
Pratibhasagar V26cf2652012-01-12 17:31:21 +0530264 [SDCC4] = {
265 .is_gpio = 1,
266 .gpio_data = &mmc_gpio_data[SDCC4],
267 },
Stepan Moskovchenko0c547bb2011-11-30 13:29:12 -0800268};
269
Subhash Jadavani55e188e2012-04-13 11:31:08 +0530270#define MSM_MPM_PIN_SDC1_DAT1 17
271#define MSM_MPM_PIN_SDC3_DAT1 21
272
Stepan Moskovchenko0c547bb2011-11-30 13:29:12 -0800273static unsigned int sdc1_sup_clk_rates[] = {
274 400000, 24000000, 48000000
275};
276
Terence Hampson2e1705f2012-04-11 19:55:29 -0400277#ifdef CONFIG_MMC_MSM_SDC3_SUPPORT
Stepan Moskovchenko0c547bb2011-11-30 13:29:12 -0800278static unsigned int sdc3_sup_clk_rates[] = {
Subhash Jadavani2f64f5a2011-12-06 17:17:23 +0530279 400000, 24000000, 48000000, 96000000, 192000000
Stepan Moskovchenko0c547bb2011-11-30 13:29:12 -0800280};
Terence Hampson2e1705f2012-04-11 19:55:29 -0400281#endif
Stepan Moskovchenko0c547bb2011-11-30 13:29:12 -0800282
283#ifdef CONFIG_MMC_MSM_SDC1_SUPPORT
284static struct mmc_platform_data msm8960_sdc1_data = {
285 .ocr_mask = MMC_VDD_27_28 | MMC_VDD_28_29,
286#ifdef CONFIG_MMC_MSM_SDC1_8_BIT_SUPPORT
287 .mmc_bus_width = MMC_CAP_8_BIT_DATA,
288#else
289 .mmc_bus_width = MMC_CAP_4_BIT_DATA,
290#endif
291 .sup_clk_table = sdc1_sup_clk_rates,
292 .sup_clk_cnt = ARRAY_SIZE(sdc1_sup_clk_rates),
293 .pclk_src_dfab = 1,
294 .nonremovable = 1,
295 .vreg_data = &mmc_slot_vreg_data[SDCC1],
Subhash Jadavani933e6a62011-12-26 18:05:04 +0530296 .pin_data = &mmc_slot_pin_data[SDCC1],
Subhash Jadavani55e188e2012-04-13 11:31:08 +0530297 .mpm_sdiowakeup_int = MSM_MPM_PIN_SDC1_DAT1,
Subhash Jadavanibcd435f2012-04-24 18:26:49 +0530298 .msm_bus_voting_data = &sps_to_ddr_bus_voting_data,
Stepan Moskovchenko0c547bb2011-11-30 13:29:12 -0800299};
300#endif
301
Pratibhasagar V57c808e2012-01-12 13:47:30 +0530302#ifdef CONFIG_MMC_MSM_SDC2_SUPPORT
303static unsigned int sdc2_sup_clk_rates[] = {
304 400000, 24000000, 48000000
305};
306
307static struct mmc_platform_data msm8960_sdc2_data = {
308 .ocr_mask = MMC_VDD_165_195,
309 .mmc_bus_width = MMC_CAP_4_BIT_DATA,
310 .sup_clk_table = sdc2_sup_clk_rates,
311 .sup_clk_cnt = ARRAY_SIZE(sdc2_sup_clk_rates),
312 .pclk_src_dfab = 1,
313 .vreg_data = &mmc_slot_vreg_data[SDCC2],
314 .pin_data = &mmc_slot_pin_data[SDCC2],
315 .sdiowakeup_irq = MSM_GPIO_TO_INT(90),
Subhash Jadavanibcd435f2012-04-24 18:26:49 +0530316 .msm_bus_voting_data = &sps_to_ddr_bus_voting_data,
Pratibhasagar V57c808e2012-01-12 13:47:30 +0530317};
318#endif
319
Stepan Moskovchenko0c547bb2011-11-30 13:29:12 -0800320#ifdef CONFIG_MMC_MSM_SDC3_SUPPORT
321static struct mmc_platform_data msm8960_sdc3_data = {
322 .ocr_mask = MMC_VDD_27_28 | MMC_VDD_28_29,
323 .mmc_bus_width = MMC_CAP_4_BIT_DATA,
324 .sup_clk_table = sdc3_sup_clk_rates,
325 .sup_clk_cnt = ARRAY_SIZE(sdc3_sup_clk_rates),
326 .pclk_src_dfab = 1,
327#ifdef CONFIG_MMC_MSM_SDC3_WP_SUPPORT
328 .wpswitch_gpio = PM8921_GPIO_PM_TO_SYS(16),
329#endif
330 .vreg_data = &mmc_slot_vreg_data[SDCC3],
331 .pin_data = &mmc_slot_pin_data[SDCC3],
332#ifdef CONFIG_MMC_MSM_CARD_HW_DETECTION
333 .status_gpio = PM8921_GPIO_PM_TO_SYS(26),
334 .status_irq = PM8921_GPIO_IRQ(PM8921_IRQ_BASE, 26),
335 .irq_flags = IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING,
Krishna Konda360aa422011-12-06 18:27:41 -0800336 .is_status_gpio_active_low = true,
Stepan Moskovchenko0c547bb2011-11-30 13:29:12 -0800337#endif
338 .xpc_cap = 1,
339 .uhs_caps = (MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25 |
340 MMC_CAP_UHS_SDR50 | MMC_CAP_UHS_DDR50 |
Subhash Jadavani2f64f5a2011-12-06 17:17:23 +0530341 MMC_CAP_UHS_SDR104 | MMC_CAP_MAX_CURRENT_600),
Subhash Jadavani55e188e2012-04-13 11:31:08 +0530342 .mpm_sdiowakeup_int = MSM_MPM_PIN_SDC3_DAT1,
Subhash Jadavanibcd435f2012-04-24 18:26:49 +0530343 .msm_bus_voting_data = &sps_to_ddr_bus_voting_data,
Stepan Moskovchenko0c547bb2011-11-30 13:29:12 -0800344};
345#endif
346
Pratibhasagar V26cf2652012-01-12 17:31:21 +0530347#ifdef CONFIG_MMC_MSM_SDC4_SUPPORT
348static unsigned int sdc4_sup_clk_rates[] = {
349 400000, 24000000, 48000000
350};
351
352static struct mmc_platform_data msm8960_sdc4_data = {
353 .ocr_mask = MMC_VDD_165_195,
354 .mmc_bus_width = MMC_CAP_4_BIT_DATA,
355 .sup_clk_table = sdc4_sup_clk_rates,
356 .sup_clk_cnt = ARRAY_SIZE(sdc4_sup_clk_rates),
357 .pclk_src_dfab = 1,
358 .vreg_data = &mmc_slot_vreg_data[SDCC4],
359 .pin_data = &mmc_slot_pin_data[SDCC4],
360 .sdiowakeup_irq = MSM_GPIO_TO_INT(85),
Subhash Jadavanibcd435f2012-04-24 18:26:49 +0530361 .msm_bus_voting_data = &sps_to_ddr_bus_voting_data,
Pratibhasagar V26cf2652012-01-12 17:31:21 +0530362};
363#endif
364
Stepan Moskovchenko0c547bb2011-11-30 13:29:12 -0800365void __init msm8960_init_mmc(void)
366{
367#ifdef CONFIG_MMC_MSM_SDC1_SUPPORT
368 /* SDC1 : eMMC card connected */
369 msm_add_sdcc(1, &msm8960_sdc1_data);
370#endif
Pratibhasagar V57c808e2012-01-12 13:47:30 +0530371#ifdef CONFIG_MMC_MSM_SDC2_SUPPORT
372 /* SDC2: SDIO slot for WLAN*/
373 msm_add_sdcc(2, &msm8960_sdc2_data);
374#endif
Stepan Moskovchenko0c547bb2011-11-30 13:29:12 -0800375#ifdef CONFIG_MMC_MSM_SDC3_SUPPORT
Stepan Moskovchenko0c547bb2011-11-30 13:29:12 -0800376 /* SDC3: External card slot */
377 msm_add_sdcc(3, &msm8960_sdc3_data);
378#endif
Pratibhasagar V26cf2652012-01-12 17:31:21 +0530379#ifdef CONFIG_MMC_MSM_SDC4_SUPPORT
380 /* SDC4: SDIO slot for WLAN */
381 msm_add_sdcc(4, &msm8960_sdc4_data);
382#endif
Stepan Moskovchenko0c547bb2011-11-30 13:29:12 -0800383}