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review.evervolv.com / android_kernel_htc_msm8960 / 94455a4f099cc13b899ada59f71e6e88c6980514 / . / arch / arm / boot / dts / msm8974.dtsi
blob: 8426b5221b67633fcaa0fb6df46c38eed46d1c32 [file] [log] [blame]
Sathish Ambley9d69ac32012-03-21 10:28:26 -0700[diff] [blame]1/* Copyright (c) 2012, Code Aurora Forum. All rights reserved.
2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 */
Sathish Ambley4df614c2011-10-07 16:30:46 -0700[diff] [blame]12
13/include/ "skeleton.dtsi"
Abhimanyu Kapur90ced6e2012-06-26 17:41:25 -0700[diff] [blame]14/include/ "msm8974_pm.dtsi"
Abhimanyu Kapur90ced6e2012-06-26 17:41:25 -0700[diff] [blame]15/include/ "msm8974-iommu.dtsi"
Matt Wagantallfc727212012-01-06 18:18:25 -0800[diff] [blame]16/include/ "msm-gdsc.dtsi"
Sathish Ambley4df614c2011-10-07 16:30:46 -0700[diff] [blame]17
18/ {
Abhimanyu Kapur90ced6e2012-06-26 17:41:25 -0700[diff] [blame]19 model = "Qualcomm MSM 8974";
20 compatible = "qcom,msm8974";
Sathish Ambley4df614c2011-10-07 16:30:46 -0700[diff] [blame]21 interrupt-parent = <&intc>;
22
23 intc: interrupt-controller@F9000000 {
24 compatible = "qcom,msm-qgic2";
25 interrupt-controller;
Michael Bohanc7224532012-01-06 16:02:52 -0800[diff] [blame]26 #interrupt-cells = <3>;
Sathish Ambley4df614c2011-10-07 16:30:46 -0700[diff] [blame]27 reg = <0xF9000000 0x1000>,
28 <0xF9002000 0x1000>;
29 };
Sathish Ambley3d50c762011-10-25 15:26:00 -0700[diff] [blame]30
Sathish Ambleye046b242012-04-09 12:38:05 -0700[diff] [blame]31 msmgpio: gpio@fd510000 {
Michael Bohan0425f6f2012-01-17 14:36:39 -0800[diff] [blame]32 compatible = "qcom,msm-gpio";
33 interrupt-controller;
34 #interrupt-cells = <2>;
Sathish Ambleye046b242012-04-09 12:38:05 -0700[diff] [blame]35 reg = <0xfd510000 0x4000>;
36 #gpio-cells = <2>;
Michael Bohan0425f6f2012-01-17 14:36:39 -0800[diff] [blame]37 };
38
Sathish Ambley098f9bd2011-11-09 16:32:53 -0800[diff] [blame]39 timer {
Sathish Ambley2f27a172012-03-16 10:46:28 -0700[diff] [blame]40 compatible = "qcom,msm-qtimer", "arm,armv7-timer";
Sathish Ambleyddd099e2012-04-25 13:24:47 -0700[diff] [blame]41 interrupts = <1 2 0 1 3 0>;
Sathish Ambley2f27a172012-03-16 10:46:28 -0700[diff] [blame]42 clock-frequency = <19200000>;
Sathish Ambley098f9bd2011-11-09 16:32:53 -0800[diff] [blame]43 };
44
Praneeth Paladugu4b73ec82012-02-08 12:55:59 -0800[diff] [blame]45 qcom,vidc@fdc00000 {
46 compatible = "qcom,msm-vidc";
47 reg = <0xfdc00000 0xff000>;
48 interrupts = <0 44 0>;
49 };
50
David Brown225abee2012-02-09 22:28:50 -0800[diff] [blame]51 serial@f991f000 {
Sathish Ambley3d50c762011-10-25 15:26:00 -0700[diff] [blame]52 compatible = "qcom,msm-lsuart-v14";
David Brown225abee2012-02-09 22:28:50 -0800[diff] [blame]53 reg = <0xf991f000 0x1000>;
Michael Bohanc7224532012-01-06 16:02:52 -0800[diff] [blame]54 interrupts = <0 109 0>;
Sathish Ambley3d50c762011-10-25 15:26:00 -0700[diff] [blame]55 };
Pavankumar Kondetieaea7fe2011-10-27 14:46:45 +0530[diff] [blame]56
Sathish Ambley9d69ac32012-03-21 10:28:26 -0700[diff] [blame]57 serial@f995e000 {
58 compatible = "qcom,msm-lsuart-v14";
59 reg = <0xf995e000 0x1000>;
60 interrupts = <0 114 0>;
61 };
62
David Brown225abee2012-02-09 22:28:50 -0800[diff] [blame]63 usb@f9a55000 {
Pavankumar Kondetieaea7fe2011-10-27 14:46:45 +0530[diff] [blame]64 compatible = "qcom,hsusb-otg";
David Brown225abee2012-02-09 22:28:50 -0800[diff] [blame]65 reg = <0xf9a55000 0x400>;
Michael Bohanc7224532012-01-06 16:02:52 -0800[diff] [blame]66 interrupts = <0 134 0>;
Michael Bohane66a3a92012-03-26 12:47:28 -0700[diff] [blame]67 HSUSB_VDDCX-supply = <&pm8841_s2>;
68 HSUSB_1p8-supply = <&pm8941_l6>;
69 HSUSB_3p3-supply = <&pm8941_l24>;
Pavankumar Kondetieaea7fe2011-10-27 14:46:45 +0530[diff] [blame]70
71 qcom,hsusb-otg-phy-type = <2>;
72 qcom,hsusb-otg-mode = <1>;
73 qcom,hsusb-otg-otg-control = <1>;
74 };
Sujit Reddy Thumma7285c2e2011-11-04 10:18:15 +0530[diff] [blame]75
Sujit Reddy Thumma85fc52c2012-05-02 12:53:45 +0530[diff] [blame]76 qcom,sdcc@f9824000 {
Sujit Reddy Thumma7285c2e2011-11-04 10:18:15 +0530[diff] [blame]77 cell-index = <1>;
78 compatible = "qcom,msm-sdcc";
Sujit Reddy Thumma85fc52c2012-05-02 12:53:45 +0530[diff] [blame]79 reg = <0xf9824000 0x1000>;
Michael Bohanc7224532012-01-06 16:02:52 -0800[diff] [blame]80 interrupts = <0 123 0>;
Sujit Reddy Thummab9ff7f02012-05-04 09:57:49 +0530[diff] [blame]81 vdd-supply = <&pm8941_l20>;
82 vdd-io-supply = <&pm8941_s3>;
83
84 qcom,sdcc-vdd-voltage_level = <2950000 2950000>;
85 qcom,sdcc-vdd-current_level = <800 500000>;
86
87 qcom,sdcc-vdd-io-always_on;
88 qcom,sdcc-vdd-io-voltage_level = <1800000 1800000>;
89 qcom,sdcc-vdd-io-current_level = <250 154000>;
Sujit Reddy Thumma7285c2e2011-11-04 10:18:15 +0530[diff] [blame]90
Sujit Reddy Thumma85fc52c2012-05-02 12:53:45 +0530[diff] [blame]91 qcom,sdcc-clk-rates = <400000 25000000 50000000 100000000 200000000>;
92 qcom,sdcc-sup-voltages = <2950 2950>;
Sujit Reddy Thumma7285c2e2011-11-04 10:18:15 +0530[diff] [blame]93 qcom,sdcc-bus-width = <8>;
94 qcom,sdcc-nonremovable;
Sujit Reddy Thumma824b7522012-05-30 13:04:34 +0530[diff] [blame]95 qcom,sdcc-bus-speed-mode = "HS200_1p8v", "DDR_1p8v";
Sujit Reddy Thumma7285c2e2011-11-04 10:18:15 +0530[diff] [blame]96 };
97
Sujit Reddy Thumma85fc52c2012-05-02 12:53:45 +0530[diff] [blame]98 qcom,sdcc@f98a4000 {
99 cell-index = <2>;
100 compatible = "qcom,msm-sdcc";
101 reg = <0xf98a4000 0x1000>;
102 interrupts = <0 125 0>;
Sujit Reddy Thummab9ff7f02012-05-04 09:57:49 +0530[diff] [blame]103 vdd-supply = <&pm8941_l21>;
104 vdd-io-supply = <&pm8941_l13>;
105
106 qcom,sdcc-vdd-voltage_level = <2950000 2950000>;
107 qcom,sdcc-vdd-current_level = <9000 800000>;
108
109 qcom,sdcc-vdd-io-always_on;
110 qcom,sdcc-vdd-io-lpm_sup;
111 qcom,sdcc-vdd-io-voltage_level = <1800000 2950000>;
112 qcom,sdcc-vdd-io-current_level = <6 22000>;
Sujit Reddy Thumma85fc52c2012-05-02 12:53:45 +0530[diff] [blame]113
114 qcom,sdcc-clk-rates = <400000 25000000 50000000 100000000 200000000>;
115 qcom,sdcc-sup-voltages = <2950 2950>;
116 qcom,sdcc-bus-width = <4>;
Sujit Reddy Thumma824b7522012-05-30 13:04:34 +0530[diff] [blame]117 qcom,sdcc-xpc;
118 qcom,sdcc-bus-speed-mode = "SDR12", "SDR25", "SDR50", "DDR50", "SDR104";
119 qcom,sdcc-current-limit = <800>;
Sujit Reddy Thumma85fc52c2012-05-02 12:53:45 +0530[diff] [blame]120 };
121
122 qcom,sdcc@f9864000 {
Sujit Reddy Thumma7285c2e2011-11-04 10:18:15 +0530[diff] [blame]123 cell-index = <3>;
124 compatible = "qcom,msm-sdcc";
Sujit Reddy Thumma85fc52c2012-05-02 12:53:45 +0530[diff] [blame]125 reg = <0xf9864000 0x1000>;
Michael Bohanc7224532012-01-06 16:02:52 -0800[diff] [blame]126 interrupts = <0 127 0>;
Sujit Reddy Thumma7285c2e2011-11-04 10:18:15 +0530[diff] [blame]127
Sujit Reddy Thumma85fc52c2012-05-02 12:53:45 +0530[diff] [blame]128 qcom,sdcc-clk-rates = <400000 25000000 50000000 100000000>;
129 qcom,sdcc-sup-voltages = <1800 1800>;
Sujit Reddy Thumma7285c2e2011-11-04 10:18:15 +0530[diff] [blame]130 qcom,sdcc-bus-width = <4>;
Sujit Reddy Thumma824b7522012-05-30 13:04:34 +0530[diff] [blame]131 qcom,sdcc-bus-speed-mode = "SDR12", "SDR25", "SDR50", "DDR50";
Sujit Reddy Thumma7138b3e2012-06-04 09:10:11 +0530[diff] [blame]132 status = "disable";
Sujit Reddy Thumma85fc52c2012-05-02 12:53:45 +0530[diff] [blame]133 };
134
135 qcom,sdcc@f98e4000 {
136 cell-index = <4>;
137 compatible = "qcom,msm-sdcc";
138 reg = <0xf98e4000 0x1000>;
139 interrupts = <0 129 0>;
140
141 qcom,sdcc-clk-rates = <400000 25000000 50000000 100000000>;
142 qcom,sdcc-sup-voltages = <1800 1800>;
143 qcom,sdcc-bus-width = <4>;
Sujit Reddy Thumma824b7522012-05-30 13:04:34 +0530[diff] [blame]144 qcom,sdcc-bus-speed-mode = "SDR12", "SDR25", "SDR50", "DDR50";
Sujit Reddy Thumma7138b3e2012-06-04 09:10:11 +0530[diff] [blame]145 status = "disable";
Sujit Reddy Thumma7285c2e2011-11-04 10:18:15 +0530[diff] [blame]146 };
Yan He1466daa2011-11-30 17:25:38 -0800[diff] [blame]147
David Brown225abee2012-02-09 22:28:50 -0800[diff] [blame]148 qcom,sps@f9980000 {
Yan He1466daa2011-11-30 17:25:38 -0800[diff] [blame]149 compatible = "qcom,msm_sps";
David Brown225abee2012-02-09 22:28:50 -0800[diff] [blame]150 reg = <0xf9984000 0x15000>,
151 <0xf9999000 0xb000>;
Michael Bohanc7224532012-01-06 16:02:52 -0800[diff] [blame]152 interrupts = <0 94 0>;
Yan He1466daa2011-11-30 17:25:38 -0800[diff] [blame]153
154 qcom,bam-dma-res-pipes = <6>;
155 };
156
Hariprasad Dhalinarasimhade991f02012-05-31 13:15:51 -0700[diff] [blame]157
Harini Jayaraman5f98dbb2011-12-20 13:38:19 -0700[diff] [blame]158 spi@f9924000 {
159 compatible = "qcom,spi-qup-v2";
160 reg = <0xf9924000 0x1000>;
Michael Bohan857c8ac2012-01-23 16:57:34 -0800[diff] [blame]161 interrupts = <0 96 0>;
Vikram Mulukutla703e5722012-05-24 21:53:40 -0700[diff] [blame]162 spi-max-frequency = <25000000>;
Harini Jayaraman5f98dbb2011-12-20 13:38:19 -0700[diff] [blame]163 };
Kenneth Heitkef3c829c2012-01-13 17:02:43 -0700[diff] [blame]164
Sagar Dhariaa316a962012-03-21 16:13:22 -0600[diff] [blame]165 slim@fe12f000 {
166 cell-index = <1>;
167 compatible = "qcom,slim-msm";
168 reg = <0xfe12f000 0x35000>,
169 <0xfe104000 0x20000>;
170 reg-names = "slimbus_physical", "slimbus_bam_physical";
171 interrupts = <0 163 0 0 164 0>;
172 interrupt-names = "slimbus_irq", "slimbus_bam_irq";
173 qcom,min-clk-gear = <10>;
174 };
175
Varad Deshmukh18057ed2012-07-03 16:34:53 -0700[diff] [blame]176 spmi_bus: qcom,spmi@fc4c0000 {
Kenneth Heitkef3c829c2012-01-13 17:02:43 -0700[diff] [blame]177 cell-index = <0>;
178 compatible = "qcom,spmi-pmic-arb";
179 reg = <0xfc4cf000 0x1000>,
180 <0Xfc4cb000 0x1000>;
181 /* 190,ee0_krait_hlos_spmi_periph_irq */
182 /* 187,channel_0_krait_hlos_trans_done_irq */
183 interrupts = <0 190 0 0 187 0>;
184 qcom,pmic-arb-ee = <0>;
185 qcom,pmic-arb-channel = <0>;
Gilad Avidova11c0b52012-02-15 15:30:49 -0700[diff] [blame]186 qcom,pmic-arb-ppid-map = <0x13000000>, /* PM8941_LDO1 */
187 <0x13100001>, /* PM8941_LDO2 */
188 <0x13200002>, /* PM8941_LDO3 */
189 <0x13300003>, /* PM8941_LDO4 */
190 <0x13400004>, /* PM8941_LDO5 */
191 <0x13500005>, /* PM8941_LDO6 */
192 <0x13600006>, /* PM8941_LDO7 */
193 <0x13700007>, /* PM8941_LDO8 */
194 <0x13800008>, /* PM8941_LDO9 */
195 <0x13900009>, /* PM8941_LDO10 */
196 <0x13a0000a>, /* PM8941_LDO11 */
197 <0x13b0000b>, /* PM8941_LDO12 */
198 <0x13c0000c>, /* PM8941_LDO13 */
199 <0x13d0000d>, /* PM8941_LDO14 */
200 <0x13e0000e>, /* PM8941_LDO15 */
201 <0x13f0000f>, /* PM8941_LDO16 */
202 <0x14000010>, /* PM8941_LDO17 */
203 <0x14100011>, /* PM8941_LDO18 */
204 <0x14200012>, /* PM8941_LDO19 */
205 <0x14300013>, /* PM8941_LDO20 */
206 <0x14400014>, /* PM8941_LDO21 */
207 <0x14500015>, /* PM8941_LDO22 */
208 <0x14600016>, /* PM8941_LDO23 */
209 <0x14700017>, /* PM8941_LDO24 */
210 <0x14800018>, /* PM8941_LDO25 */
211 <0x14900019>, /* PM8941_LDO26 */
212 <0x0c00001a>, /* PM8941_GPIO1 */
213 <0x0c10001b>, /* PM8941_GPIO2 */
214 <0x0c20001c>, /* PM8941_GPIO3 */
215 <0x0c30001d>, /* PM8941_GPIO4 */
216 <0x0c40001e>, /* PM8941_GPIO5 */
217 <0x0c50001f>, /* PM8941_GPIO6 */
218 <0x0c600020>, /* PM8941_GPIO7 */
219 <0x0c700021>, /* PM8941_GPIO8 */
220 <0x0c800022>, /* PM8941_GPIO9 */
221 <0x0c900023>, /* PM8941_GPIO10 */
222 <0x0ca00024>, /* PM8941_GPIO11 */
223 <0x0cb00025>, /* PM8941_GPIO12 */
224 <0x0cc00026>, /* PM8941_GPIO13 */
225 <0x0cd00027>, /* PM8941_GPIO14 */
226 <0x0ce00028>, /* PM8941_GPIO15 */
227 <0x0cf00029>, /* PM8941_GPIO16 */
228 <0x0d00002a>, /* PM8941_GPIO17 */
229 <0x0d10002b>, /* PM8941_GPIO18 */
230 <0x0d20002c>, /* PM8941_GPIO19 */
231 <0x0d30002d>, /* PM8941_GPIO20 */
232 <0x0d40002e>, /* PM8941_GPIO21 */
233 <0x0d50002f>, /* PM8941_GPIO22 */
234 <0x0d600030>, /* PM8941_GPIO23 */
235 <0x0d700031>, /* PM8941_GPIO24 */
236 <0x0d800032>, /* PM8941_GPIO25 */
237 <0x0d900033>, /* PM8941_GPIO26 */
238 <0x0da00034>, /* PM8941_GPIO27 */
239 <0x0db00035>, /* PM8941_GPIO28 */
240 <0x0dc00036>, /* PM8941_GPIO29 */
241 <0x0dd00037>, /* PM8941_GPIO30 */
242 <0x0de00038>, /* PM8941_GPIO31 */
243 <0x0df00039>, /* PM8941_GPIO32 */
244 <0x0e00003a>, /* PM8941_GPIO33 */
245 <0x0e10003b>, /* PM8941_GPIO34 */
246 <0x0e20003c>, /* PM8941_GPIO35 */
247 <0x0e30003d>, /* PM8941_GPIO36 */
248 <0x0280003e>, /* COINCELL */
249 <0x0100003f>, /* SMBC_OVP */
250 <0x01100040>, /* SMBC_CHG */
251 <0x01200041>, /* SMBC_BIF */
252 <0x00500042>, /* INTERRUPT */
253 <0x00100043>, /* PM8941_0 */
254 <0x20100044>, /* PM8841_0 */
255 <0x10100045>, /* PM8941_1 */
256 <0x30100046>, /* PM8841_1 */
257 <0x00800047>, /* PON0 */
258 <0x20800048>, /* PON1 */
259 <0x11000049>, /* PM8941_SMPS1 */
260 <0x1110004a>, /* PM8941_SMPS2 */
261 <0x1120004b>, /* PM8941_SMPS3 */
262 <0x3100004c>, /* PM8841_SMPS1 */
263 <0x3110004d>, /* PM8841_SMPS2 */
264 <0x3120004e>, /* PM8841_SMPS3 */
265 <0x3130004f>, /* PM8841_SMPS4 */
266 <0x31400050>, /* PM8841_SMPS5 */
267 <0x31500051>, /* PM8841_SMPS6 */
268 <0x31600052>, /* PM8841_SMPS7 */
269 <0x31700053>, /* PM8841_SMPS8 */
270 <0x05000054>, /* SHARED_XO */
271 <0x05100055>, /* BB_CLK1 */
272 <0x05200056>, /* BB_CLK2 */
273 <0x05900057>, /* SLEEP_CLK */
274 <0x07000058>, /* PBS_CORE */
275 <0x07100059>, /* PBS_CLIENT1 */
276 <0x0720005a>; /* PBS_CLIENT2 */
Kenneth Heitkef3c829c2012-01-13 17:02:43 -0700[diff] [blame]277 };
Sagar Dharia218edb92012-01-15 18:03:01 -0700[diff] [blame]278
279 i2c@f9966000 {
280 cell-index = <0>;
281 compatible = "qcom,i2c-qup";
282 reg = <0Xf9966000 0x1000>;
283 reg-names = "qup_phys_addr";
284 interrupts = <0 104 0>;
285 interrupt-names = "qup_err_intr";
286 qcom,i2c-bus-freq = <100000>;
287 qcom,i2c-src-freq = <24000000>;
288 };
Matt Wagantalle9b715a2012-01-04 18:16:14 -0800[diff] [blame]289
Matt Wagantall48523022012-04-23 13:28:42 -0700[diff] [blame]290 qcom,acpuclk@f9000000 {
Abhimanyu Kapur90ced6e2012-06-26 17:41:25 -0700[diff] [blame]291 compatible = "qcom,acpuclk-8974";
Matt Wagantallbf9eb2c2012-05-31 09:44:22 -0700[diff] [blame]292 krait0-supply = <&krait0_vreg>;
293 krait1-supply = <&krait1_vreg>;
294 krait2-supply = <&krait2_vreg>;
295 krait3-supply = <&krait3_vreg>;
David Collins1c91ea72012-05-03 16:17:35 -0700[diff] [blame]296 krait0_mem-supply = <&pm8841_s1_ao>;
297 krait1_mem-supply = <&pm8841_s1_ao>;
298 krait2_mem-supply = <&pm8841_s1_ao>;
299 krait3_mem-supply = <&pm8841_s1_ao>;
300 krait0_dig-supply = <&pm8841_s2_corner_ao>;
301 krait1_dig-supply = <&pm8841_s2_corner_ao>;
302 krait2_dig-supply = <&pm8841_s2_corner_ao>;
303 krait3_dig-supply = <&pm8841_s2_corner_ao>;
Matt Wagantall337cdb72012-06-29 12:07:27 -0700[diff] [blame]304 krait0_hfpll_a-supply = <&pm8941_s2_ao>;
305 krait1_hfpll_a-supply = <&pm8941_s2_ao>;
306 krait2_hfpll_a-supply = <&pm8941_s2_ao>;
307 krait3_hfpll_a-supply = <&pm8941_s2_ao>;
308 l2_hfpll_a-supply = <&pm8941_s2_ao>;
309 krait0_hfpll_b-supply = <&pm8941_l12_ao>;
310 krait1_hfpll_b-supply = <&pm8941_l12_ao>;
311 krait2_hfpll_b-supply = <&pm8941_l12_ao>;
312 krait3_hfpll_b-supply = <&pm8941_l12_ao>;
313 l2_hfpll_b-supply = <&pm8941_l12_ao>;
Matt Wagantalle9b715a2012-01-04 18:16:14 -0800[diff] [blame]314 };
Ido Shayevitzef72ddd2012-03-28 18:55:55 +0200[diff] [blame]315
316 qcom,ssusb@F9200000 {
317 compatible = "qcom,dwc-usb3-msm";
Manu Gautam8c642812012-06-07 10:35:10 +0530[diff] [blame]318 reg = <0xF9200000 0xFA000>;
Manu Gautam17206c22012-06-21 10:17:53 +0530[diff] [blame]319 interrupts = <0 131 0 0 179 0>;
320 interrupt-names = "irq", "otg_irq";
Manu Gautam60e01352012-05-29 09:00:34 +0530[diff] [blame]321 SSUSB_VDDCX-supply = <&pm8841_s2>;
322 SSUSB_1p8-supply = <&pm8941_l6>;
323 HSUSB_VDDCX-supply = <&pm8841_s2>;
324 HSUSB_1p8-supply = <&pm8941_l6>;
325 HSUSB_3p3-supply = <&pm8941_l24>;
Ido Shayevitzef72ddd2012-03-28 18:55:55 +0200[diff] [blame]326 qcom,dwc-usb3-msm-dbm-eps = <4>;
327 };
Matt Wagantallc2bbdc32012-03-21 19:44:50 -0700[diff] [blame]328
Matt Wagantallfc727212012-01-06 18:18:25 -0800[diff] [blame]329 gdsc_oxili_gx: qcom,gdsc@fd8c4024 {
330 parent-supply = <&pm8841_s4>;
331 };
332
Matt Wagantallc2bbdc32012-03-21 19:44:50 -0700[diff] [blame]333 qcom,lpass@fe200000 {
334 compatible = "qcom,pil-q6v5-lpass";
335 reg = <0xfe200000 0x00100>,
Matt Wagantallc2bbdc32012-03-21 19:44:50 -0700[diff] [blame]336 <0xfd485100 0x00010>;
337
Matt Wagantall6e6b8cd2012-05-24 12:42:24 -0700[diff] [blame]338 qcom,firmware-name = "adsp";
Matt Wagantallc2bbdc32012-03-21 19:44:50 -0700[diff] [blame]339 };
Tianyi Gouc1e049f82011-11-23 14:20:16 -0800[diff] [blame]340
Phani Kumar Uppalapati87841c82012-06-14 21:28:43 -0700[diff] [blame]341 qcom,msm-pcm {
342 compatible = "qcom,msm-pcm-dsp";
343 };
Phani Kumar Uppalapatic6651692012-06-14 20:33:09 -0700[diff] [blame]344
Phani Kumar Uppalapati87841c82012-06-14 21:28:43 -0700[diff] [blame]345 qcom,msm-pcm-routing {
346 compatible = "qcom,msm-pcm-routing";
347 };
Phani Kumar Uppalapatic6651692012-06-14 20:33:09 -0700[diff] [blame]348
Phani Kumar Uppalapati87841c82012-06-14 21:28:43 -0700[diff] [blame]349 qcom,msm-pcm-lpa {
350 compatible = "qcom,msm-pcm-lpa";
351 };
Phani Kumar Uppalapatic6651692012-06-14 20:33:09 -0700[diff] [blame]352
Phani Kumar Uppalapati87841c82012-06-14 21:28:43 -0700[diff] [blame]353 qcom,msm-voip-dsp {
354 compatible = "qcom,msm-voip-dsp";
355 };
Phani Kumar Uppalapatic6651692012-06-14 20:33:09 -0700[diff] [blame]356
Phani Kumar Uppalapati87841c82012-06-14 21:28:43 -0700[diff] [blame]357 qcom,msm-stub-codec {
358 compatible = "qcom,msm-stub-codec";
359 };
Phani Kumar Uppalapatic6651692012-06-14 20:33:09 -0700[diff] [blame]360
Phani Kumar Uppalapati87841c82012-06-14 21:28:43 -0700[diff] [blame]361 qcom,msm-dai-fe {
362 compatible = "qcom,msm-dai-fe";
363 };
Phani Kumar Uppalapatic6651692012-06-14 20:33:09 -0700[diff] [blame]364
Phani Kumar Uppalapati87841c82012-06-14 21:28:43 -0700[diff] [blame]365 qcom,msm-auxpcm {
366 compatible = "qcom,msm-auxpcm-resource";
367 qcom,msm-cpudai-auxpcm-clk = "pcm_clk";
368 qcom,msm-cpudai-auxpcm-mode = <0>;
369 qcom,msm-cpudai-auxpcm-sync = <1>;
370 qcom,msm-cpudai-auxpcm-frame = <5>;
371 qcom,msm-cpudai-auxpcm-quant = <2>;
372 qcom,msm-cpudai-auxpcm-slot = <1>;
373 qcom,msm-cpudai-auxpcm-data = <0>;
374 qcom,msm-cpudai-auxpcm-pcm-clk-rate = <2048000>;
Phani Kumar Uppalapatic6651692012-06-14 20:33:09 -0700[diff] [blame]375
Phani Kumar Uppalapati87841c82012-06-14 21:28:43 -0700[diff] [blame]376 qcom,msm-auxpcm-rx {
377 qcom,msm-auxpcm-dev-id = <4106>;
378 compatible = "qcom,msm-auxpcm-dev";
379 };
Phani Kumar Uppalapatic6651692012-06-14 20:33:09 -0700[diff] [blame]380
Phani Kumar Uppalapati87841c82012-06-14 21:28:43 -0700[diff] [blame]381 qcom,msm-auxpcm-tx {
382 qcom,msm-auxpcm-dev-id = <4107>;
383 compatible = "qcom,msm-auxpcm-dev";
384 };
385 };
386
387 qcom,msm-pcm-hostless {
388 compatible = "qcom,msm-pcm-hostless";
389 };
Phani Kumar Uppalapatic6651692012-06-14 20:33:09 -0700[diff] [blame]390
Matt Wagantall4e2599e2012-03-21 22:31:35 -0700[diff] [blame]391 qcom,mss@fc880000 {
392 compatible = "qcom,pil-q6v5-mss";
393 reg = <0xfc880000 0x100>,
394 <0xfd485000 0x400>,
395 <0xfc820000 0x020>,
396 <0xfc401680 0x004>;
397 vdd_mss-supply = <&pm8841_s3>;
398
399 qcom,firmware-name = "mba";
400 qcom,pil-self-auth = <1>;
401 };
402
Matt Wagantalle6e00d52012-03-08 17:39:07 -0800[diff] [blame]403 qcom,mba@fc820000 {
404 compatible = "qcom,pil-mba";
405 reg = <0xfc820000 0x0020>,
406 <0x0d1fc000 0x4000>;
407
408 qcom,firmware-name = "modem";
409 qcom,depends-on = "mba";
410 };
411
Tianyi Gouc1e049f82011-11-23 14:20:16 -0800[diff] [blame]412 qcom,pronto@fb21b000 {
413 compatible = "qcom,pil-pronto";
414 reg = <0xfb21b000 0x3000>,
415 <0xfc401700 0x4>,
416 <0xfd485300 0xc>;
417 vdd_pronto_pll-supply = <&pm8941_l12>;
418
419 qcom,firmware-name = "wcnss";
420 };
Naveen Ramaraj51f5e8b2012-04-09 15:58:40 -0700[diff] [blame]421
422 qcom,ocmem@fdd00000 {
Naveen Ramaraj94455a42012-07-05 16:01:40 -0700[diff] [blame^]423 compatible = "qcom,msm-ocmem";
424 reg = <0xfdd00000 0x2000>,
425 <0xfdd02000 0x2000>,
426 <0xfe039000 0x400>,
427 <0xfec00000 0x180000>;
428 reg-names = "ocmem_ctrl_physical", "dm_ctrl_physical", "br_ctrl_physical", "ocmem_physical";
429 interrupts = <0 76 0 0 77 0>;
430 interrupt-names = "ocmem_irq", "dm_irq";
431 qcom,ocmem-num-regions = <0x3>;
432 #address-cells = <1>;
433 #size-cells = <1>;
434 ranges = <0x0 0xfec00000 0x180000>;
435
436 partition@0 {
437 reg = <0x0 0x100000>;
438 qcom,ocmem-part-name = "graphics";
439 qcom,ocmem-part-min = <0x80000>;
440 };
441
442 partition@80000 {
443 reg = <0x80000 0xA0000>;
444 qcom,ocmem-part-name = "lp_audio";
445 qcom,ocmem-part-min = <0xA0000>;
446 };
447
448 partition@E0000 {
449 reg = <0x120000 0x20000>;
450 qcom,ocmem-part-name = "blast";
451 qcom,ocmem-part-min = <0x20000>;
452 };
453
454 partition@100000 {
455 reg = <0x100000 0x80000>;
456 qcom,ocmem-part-name = "video";
457 qcom,ocmem-part-min = <0x55000>;
458 };
459
460 partition@140000 {
461 reg = <0x140000 0x40000>;
462 qcom,ocmem-part-name = "sensors";
463 qcom,ocmem-part-min = <0x40000>;
464 };
Naveen Ramaraj51f5e8b2012-04-09 15:58:40 -0700[diff] [blame]465 };
Mahesh Sivasubramanian3f0d0c72012-05-04 17:35:55 -0600[diff] [blame]466
Varad Deshmukh18057ed2012-07-03 16:34:53 -0700[diff] [blame]467 rpm_bus: qcom,rpm-smd {
Mahesh Sivasubramanian3f0d0c72012-05-04 17:35:55 -0600[diff] [blame]468 compatible = "qcom,rpm-smd";
469 rpm-channel-name = "rpm_requests";
470 rpm-channel-type = <15>; /* SMD_APPS_RPM */
471 };
Hariprasad Dhalinarasimhade991f02012-05-31 13:15:51 -0700[diff] [blame]472
473 qcom,msm-rng@f9bff000 {
474 compatible = "qcom,msm-rng";
475 reg = <0xf9bff000 0x200>;
476 };
Ramesh Masavarapufb1f01e2012-06-14 09:40:40 -0700[diff] [blame]477
478 qcom,qseecom@fe806000 {
479 compatible = "qcom,qseecom";
480 };
Adrian Salido-Moreno5ef3ac02012-05-14 18:40:47 -0700[diff] [blame]481
482 qcom,mdss_mdp@fd900000 {
483 cell-index = <0>;
484 compatible = "qcom,mdss_mdp";
485 reg = <0xfd900000 0x22100>;
486 interrupts = <0 72 0>;
Matt Wagantall37320fb2012-06-26 14:50:28 -0700[diff] [blame]487 vdd-supply = <&gdsc_mdss>;
Adrian Salido-Moreno5ef3ac02012-05-14 18:40:47 -0700[diff] [blame]488 };
489
490 qcom,mdss_wb_panel {
491 cell-index = <1>;
492 compatible = "qcom,mdss_wb";
493 qcom,mdss_pan_res = <640 480>;
494 qcom,mdss_pan_bpp = <24>;
495 };
Hanumant72aec702012-06-25 11:51:07 -0700[diff] [blame]496
497 qcom,wdt@f9017000 {
498 compatible = "qcom,msm-watchdog";
499 reg = <0xf9017000 0x1000>;
500 interrupts = <0 3 0 0 4 0>;
501 qcom,bark-time = <11000>;
502 qcom,pet-time = <10000>;
503 qcom,ipi-ping = <1>;
504 };
Hariprasad Dhalinarasimha0fc258f2012-07-05 13:01:29 -0700[diff] [blame]505
506 qcom,tz-log@fe805720 {
507 compatible = "qcom,tz-log";
508 reg = <0xfe805720 0x1000>;
509 };
Tianyi Gou828798d2012-05-02 21:12:38 -0700[diff] [blame]510
511 qcom,venus@fdce0000 {
512 compatible = "qcom,pil-venus";
513 reg = <0xfdce0000 0x4000>,
514 <0xfdc80208 0x8>;
515 vdd-supply = <&gdsc_venus>;
516
517 qcom,firmware-name = "venus";
518 qcom,firmware-min-paddr = <0xF500000>;
519 qcom,firmware-max-paddr = <0xFA00000>;
520 };
Siddartha Mohanadoss05a6e382012-05-14 15:13:37 -0700[diff] [blame]521
522 tsens@fc4a8000 {
523 compatible = "qcom,msm-tsens";
524 reg = <0xfc4a8000 0x2000>,
525 <0xfc4b80d0 0x5>;
526 reg-names = "tsens_physical", "tsens_eeprom_physical";
527 interrupts = <0 184 0>;
528 qcom,sensors = <11>;
529 qcom,slope = <1134 1122 1142 1123 1176 1176 1176 1186 1176
530 1176 1176>;
531 };
Sathish Ambley4df614c2011-10-07 16:30:46 -0700[diff] [blame]532};
Varad Deshmukh18057ed2012-07-03 16:34:53 -0700[diff] [blame]533
534/include/ "msm-pm8x41-rpm-regulator.dtsi"
535/include/ "msm-pm8841.dtsi"
536/include/ "msm-pm8941.dtsi"
537/include/ "msm8974-regulator.dtsi"
538/include/ "msm8974-gpio.dtsi"