blob: e003243dfa88d30c37494f2f7d37a74948c23e33 [file] [log] [blame]
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001/* Copyright (c) 2009-2011, Code Aurora Forum. All rights reserved.
2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 *
12 */
13
14#include <linux/module.h>
15#include <linux/kernel.h>
16#include <linux/sched.h>
17#include <linux/time.h>
18#include <linux/init.h>
19#include <linux/interrupt.h>
20#include <linux/spinlock.h>
21#include <linux/hrtimer.h>
22#include <linux/clk.h>
23#include <mach/hardware.h>
24#include <linux/io.h>
25#include <linux/debugfs.h>
26#include <linux/fb.h>
27#include <linux/msm_mdp.h>
28#include <linux/file.h>
29#include <linux/android_pmem.h>
30#include <linux/major.h>
31#include <asm/system.h>
32#include <asm/mach-types.h>
33#include <linux/semaphore.h>
34#include <linux/uaccess.h>
35#include <linux/mutex.h>
36#include <linux/msm_kgsl.h>
37#include "mdp.h"
38#include "msm_fb.h"
39#include "mdp4.h"
40
41#define VERSION_KEY_MASK 0xFFFFFF00
42
43struct mdp4_overlay_ctrl {
44 struct mdp4_pipe_desc ov_pipe[OVERLAY_PIPE_MAX];/* 4 */
45 struct mdp4_overlay_pipe plist[MDP4_MAX_PIPE]; /* 4 + 2 */
kuogee hsieh405dc302011-07-21 15:06:59 -070046 struct mdp4_overlay_pipe *stage[MDP4_MAX_MIXER][MDP4_MIXER_STAGE_MAX];
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070047 uint32 panel_3d;
48 uint32 panel_mode;
49 uint32 mixer0_played;
50 uint32 mixer1_played;
51} mdp4_overlay_db = {
52 .ov_pipe = {
53 {
54 .share = 0, /* RGB 1 */
55 },
56 {
57 .share = 0, /* RGB 2 */
58 },
59 {
60 .share = 1, /* VG 1 */
61 },
62 {
63 .share = 1, /* VG 2 */
64 },
65 },
66 .plist = {
67 {
68 .pipe_type = OVERLAY_TYPE_RGB,
69 .pipe_num = OVERLAY_PIPE_RGB1,
70 .pipe_ndx = 1,
71 },
72 {
73 .pipe_type = OVERLAY_TYPE_RGB,
74 .pipe_num = OVERLAY_PIPE_RGB2,
75 .pipe_ndx = 2,
76 },
77 {
78 .pipe_type = OVERLAY_TYPE_RGB, /* shared */
79 .pipe_num = OVERLAY_PIPE_VG1,
80 .pipe_ndx = 3,
81 },
82 {
83 .pipe_type = OVERLAY_TYPE_RGB, /* shared */
84 .pipe_num = OVERLAY_PIPE_VG2,
85 .pipe_ndx = 4,
86 },
87 {
88 .pipe_type = OVERLAY_TYPE_VIDEO, /* shared */
89 .pipe_num = OVERLAY_PIPE_VG1,
90 .pipe_ndx = 5,
91 },
92 {
93 .pipe_type = OVERLAY_TYPE_VIDEO, /* shared */
94 .pipe_num = OVERLAY_PIPE_VG2,
95 .pipe_ndx = 6,
96 },
97 },
98};
99
100static struct mdp4_overlay_ctrl *ctrl = &mdp4_overlay_db;
kuogee hsieh9452ecb2011-08-01 18:26:23 -0700101static int new_perf_level;
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700102/* static array with index 0 for unset status and 1 for set status */
103static bool overlay_status[MDP4_OVERLAY_TYPE_MAX];
104
105void mdp4_overlay_status_write(enum mdp4_overlay_status type, bool val)
106{
107 overlay_status[type] = val;
108}
109
110bool mdp4_overlay_status_read(enum mdp4_overlay_status type)
111{
112 return overlay_status[type];
113}
114
115int mdp4_overlay_mixer_play(int mixer_num)
116{
117 if (mixer_num == MDP4_MIXER1)
118 return ctrl->mixer1_played;
119 else
120 return ctrl->mixer0_played;
121}
122
123void mdp4_overlay_panel_3d(int mixer_num, uint32 panel_3d)
124{
125 ctrl->panel_3d = panel_3d;
126}
127
128void mdp4_overlay_panel_mode(int mixer_num, uint32 mode)
129{
130 ctrl->panel_mode |= mode;
131}
132
133uint32 mdp4_overlay_panel_list(void)
134{
135 return ctrl->panel_mode;
136}
137
138void mdp4_overlay_dmae_cfg(struct msm_fb_data_type *mfd, int atv)
139{
140 uint32 dmae_cfg_reg;
141
142 if (atv)
143 dmae_cfg_reg = DMA_DEFLKR_EN;
144 else
145 dmae_cfg_reg = 0;
146
147 if (mfd->fb_imgType == MDP_BGR_565)
148 dmae_cfg_reg |= DMA_PACK_PATTERN_BGR;
149 else
150 dmae_cfg_reg |= DMA_PACK_PATTERN_RGB;
151
152
153 if (mfd->panel_info.bpp == 18) {
154 dmae_cfg_reg |= DMA_DSTC0G_6BITS | /* 666 18BPP */
155 DMA_DSTC1B_6BITS | DMA_DSTC2R_6BITS;
156 } else if (mfd->panel_info.bpp == 16) {
157 dmae_cfg_reg |= DMA_DSTC0G_6BITS | /* 565 16BPP */
158 DMA_DSTC1B_5BITS | DMA_DSTC2R_5BITS;
159 } else {
160 dmae_cfg_reg |= DMA_DSTC0G_8BITS | /* 888 16BPP */
161 DMA_DSTC1B_8BITS | DMA_DSTC2R_8BITS;
162 }
163
164 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
165
166 /* dma2 config register */
167 MDP_OUTP(MDP_BASE + 0xb0000, dmae_cfg_reg);
168 if (atv) {
169 MDP_OUTP(MDP_BASE + 0xb0070, 0xeb0010);
170 MDP_OUTP(MDP_BASE + 0xb0074, 0xf00010);
171 MDP_OUTP(MDP_BASE + 0xb0078, 0xf00010);
172 MDP_OUTP(MDP_BASE + 0xb3000, 0x80);
173 MDP_OUTP(MDP_BASE + 0xb3010, 0x1800040);
174 MDP_OUTP(MDP_BASE + 0xb3014, 0x1000080);
175 MDP_OUTP(MDP_BASE + 0xb4004, 0x67686970);
176 } else {
177 MDP_OUTP(MDP_BASE + 0xb0070, 0xff0000);
178 MDP_OUTP(MDP_BASE + 0xb0074, 0xff0000);
179 MDP_OUTP(MDP_BASE + 0xb0078, 0xff0000);
180 }
181
182 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
183}
184
Manoj Raob91fa712011-06-29 09:07:55 -0700185#ifdef CONFIG_FB_MSM_HDMI_3D
186void unfill_black_screen(void) { return; }
187#else
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700188void unfill_black_screen(void)
189{
190 uint32 temp_src_format;
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700191 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
192 /*
193 * VG2 Constant Color
194 */
195 temp_src_format = inpdw(MDP_BASE + 0x30050);
196 MDP_OUTP(MDP_BASE + 0x30050, temp_src_format&(~BIT(22)));
197 /*
198 * MDP_OVERLAY_REG_FLUSH
199 */
200 MDP_OUTP(MDP_BASE + 0x18000, BIT(3));
201 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
Manoj Raob91fa712011-06-29 09:07:55 -0700202 return;
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700203}
Manoj Raob91fa712011-06-29 09:07:55 -0700204#endif
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700205
Manoj Raob91fa712011-06-29 09:07:55 -0700206#ifdef CONFIG_FB_MSM_HDMI_3D
207void fill_black_screen(void) { return; }
208#else
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700209void fill_black_screen(void)
210{
211 /*Black color*/
212 uint32 color = 0x00000000;
213 uint32 temp_src_format;
214 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
215 /*
216 * VG2 Constant Color
217 */
218 MDP_OUTP(MDP_BASE + 0x31008, color);
219 /*
220 * MDP_VG2_SRC_FORMAT
221 */
222 temp_src_format = inpdw(MDP_BASE + 0x30050);
223 MDP_OUTP(MDP_BASE + 0x30050, temp_src_format | BIT(22));
224 /*
225 * MDP_OVERLAY_REG_FLUSH
226 */
227 MDP_OUTP(MDP_BASE + 0x18000, BIT(3));
228 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
Manoj Raob91fa712011-06-29 09:07:55 -0700229 return;
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700230}
Manoj Raob91fa712011-06-29 09:07:55 -0700231#endif
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700232
233void mdp4_overlay_dmae_xy(struct mdp4_overlay_pipe *pipe)
234{
235
236 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
237
238 /* dma_p source */
239 MDP_OUTP(MDP_BASE + 0xb0004,
240 (pipe->src_height << 16 | pipe->src_width));
241 MDP_OUTP(MDP_BASE + 0xb0008, pipe->srcp0_addr);
242 MDP_OUTP(MDP_BASE + 0xb000c, pipe->srcp0_ystride);
243
244 /* dma_p dest */
245 MDP_OUTP(MDP_BASE + 0xb0010, (pipe->dst_y << 16 | pipe->dst_x));
246
247 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
248}
249
250void mdp4_overlay_dmap_cfg(struct msm_fb_data_type *mfd, int lcdc)
251{
252 uint32 dma2_cfg_reg;
253
254 dma2_cfg_reg = DMA_DITHER_EN;
255#ifdef BLT_RGB565
256 /* RGB888 is 0 */
257 dma2_cfg_reg |= DMA_BUF_FORMAT_RGB565; /* blt only */
258#endif
259
260 if (mfd->fb_imgType == MDP_BGR_565)
261 dma2_cfg_reg |= DMA_PACK_PATTERN_BGR;
262 else
263 dma2_cfg_reg |= DMA_PACK_PATTERN_RGB;
264
265
266 if (mfd->panel_info.bpp == 18) {
267 dma2_cfg_reg |= DMA_DSTC0G_6BITS | /* 666 18BPP */
268 DMA_DSTC1B_6BITS | DMA_DSTC2R_6BITS;
269 } else if (mfd->panel_info.bpp == 16) {
270 dma2_cfg_reg |= DMA_DSTC0G_6BITS | /* 565 16BPP */
271 DMA_DSTC1B_5BITS | DMA_DSTC2R_5BITS;
272 } else {
273 dma2_cfg_reg |= DMA_DSTC0G_8BITS | /* 888 16BPP */
274 DMA_DSTC1B_8BITS | DMA_DSTC2R_8BITS;
275 }
276
277 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
278
279#ifndef CONFIG_FB_MSM_LCDC_CHIMEI_WXGA_PANEL
280 if (lcdc)
281 dma2_cfg_reg |= DMA_PACK_ALIGN_MSB;
282#endif
283
284 /* dma2 config register */
285 MDP_OUTP(MDP_BASE + 0x90000, dma2_cfg_reg);
286
287 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
288}
289
290/*
291 * mdp4_overlay_dmap_xy: called form baselayer only
292 */
293void mdp4_overlay_dmap_xy(struct mdp4_overlay_pipe *pipe)
294{
295 uint32 off, bpp;
296
297 if (mdp_is_in_isr == FALSE)
298 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
299
300 /* dma_p source */
301 MDP_OUTP(MDP_BASE + 0x90004,
302 (pipe->src_height << 16 | pipe->src_width));
303 if (pipe->blt_addr) {
304#ifdef BLT_RGB565
305 bpp = 2; /* overlay ouput is RGB565 */
306#else
307 bpp = 3; /* overlay ouput is RGB888 */
308#endif
309 off = 0;
310 if (pipe->dmap_cnt & 0x01)
311 off = pipe->src_height * pipe->src_width * bpp;
312 MDP_OUTP(MDP_BASE + 0x90008, pipe->blt_addr + off);
313 /* RGB888, output of overlay blending */
314 MDP_OUTP(MDP_BASE + 0x9000c, pipe->src_width * bpp);
315 } else {
316 MDP_OUTP(MDP_BASE + 0x90008, pipe->srcp0_addr);
317 MDP_OUTP(MDP_BASE + 0x9000c, pipe->srcp0_ystride);
318 }
319
320 /* dma_p dest */
321 MDP_OUTP(MDP_BASE + 0x90010, (pipe->dst_y << 16 | pipe->dst_x));
322
323 if (mdp_is_in_isr == FALSE)
324 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
325}
326
327#define MDP4_VG_PHASE_STEP_DEFAULT 0x20000000
328#define MDP4_VG_PHASE_STEP_SHIFT 29
329
330static int mdp4_leading_0(uint32 num)
331{
332 uint32 bit = 0x80000000;
333 int i;
334
335 for (i = 0; i < 32; i++) {
336 if (bit & num)
337 return i;
338 bit >>= 1;
339 }
340
341 return i;
342}
343
344static uint32 mdp4_scale_phase_step(int f_num, uint32 src, uint32 dst)
345{
346 uint32 val;
347 int n;
348
349 n = mdp4_leading_0(src);
350 if (n > f_num)
351 n = f_num;
352 val = src << n; /* maximum to reduce lose of resolution */
353 val /= dst;
354 if (n < f_num) {
355 n = f_num - n;
356 val <<= n;
357 }
358
359 return val;
360}
361
362static void mdp4_scale_setup(struct mdp4_overlay_pipe *pipe)
363{
364 int ptype;
365
366 pipe->phasex_step = MDP4_VG_PHASE_STEP_DEFAULT;
367 pipe->phasey_step = MDP4_VG_PHASE_STEP_DEFAULT;
368 ptype = mdp4_overlay_format2type(pipe->src_format);
369
370 if (pipe->dst_h && pipe->src_h != pipe->dst_h) {
371 if (pipe->dst_h > pipe->src_h * 8) /* too much */
372 return;
373 pipe->op_mode |= MDP4_OP_SCALEY_EN;
374
375 if (pipe->pipe_num >= OVERLAY_PIPE_VG1) {
376 if (pipe->dst_h <= (pipe->src_h / 4))
377 pipe->op_mode |= MDP4_OP_SCALEY_MN_PHASE;
378 else
379 pipe->op_mode |= MDP4_OP_SCALEY_FIR;
380 }
381
382 pipe->phasey_step = mdp4_scale_phase_step(29,
383 pipe->src_h, pipe->dst_h);
384 }
385
386 if (pipe->dst_w && pipe->src_w != pipe->dst_w) {
387 if (pipe->dst_w > pipe->src_w * 8) /* too much */
388 return;
389 pipe->op_mode |= MDP4_OP_SCALEX_EN;
390
391 if (pipe->pipe_num >= OVERLAY_PIPE_VG1) {
392 if (pipe->dst_w <= (pipe->src_w / 4))
393 pipe->op_mode |= MDP4_OP_SCALEX_MN_PHASE;
394 else
395 pipe->op_mode |= MDP4_OP_SCALEX_FIR;
396 }
397
398 pipe->phasex_step = mdp4_scale_phase_step(29,
399 pipe->src_w, pipe->dst_w);
400 }
401}
402
403void mdp4_overlay_rgb_setup(struct mdp4_overlay_pipe *pipe)
404{
405 char *rgb_base;
406 uint32 src_size, src_xy, dst_size, dst_xy;
407 uint32 format, pattern;
408
409 rgb_base = MDP_BASE + MDP4_RGB_BASE;
410 rgb_base += (MDP4_RGB_OFF * pipe->pipe_num);
411
412 src_size = ((pipe->src_h << 16) | pipe->src_w);
413 src_xy = ((pipe->src_y << 16) | pipe->src_x);
414 dst_size = ((pipe->dst_h << 16) | pipe->dst_w);
415 dst_xy = ((pipe->dst_y << 16) | pipe->dst_x);
416
417 format = mdp4_overlay_format(pipe);
418 pattern = mdp4_overlay_unpack_pattern(pipe);
419
420#ifdef MDP4_IGC_LUT_ENABLE
421 pipe->op_mode |= MDP4_OP_IGC_LUT_EN;
422#endif
423
424 mdp4_scale_setup(pipe);
425
426 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
427
428 outpdw(rgb_base + 0x0000, src_size); /* MDP_RGB_SRC_SIZE */
429 outpdw(rgb_base + 0x0004, src_xy); /* MDP_RGB_SRC_XY */
430 outpdw(rgb_base + 0x0008, dst_size); /* MDP_RGB_DST_SIZE */
431 outpdw(rgb_base + 0x000c, dst_xy); /* MDP_RGB_DST_XY */
432
433 outpdw(rgb_base + 0x0010, pipe->srcp0_addr);
434 outpdw(rgb_base + 0x0040, pipe->srcp0_ystride);
435
436 outpdw(rgb_base + 0x0050, format);/* MDP_RGB_SRC_FORMAT */
437 outpdw(rgb_base + 0x0054, pattern);/* MDP_RGB_SRC_UNPACK_PATTERN */
438 outpdw(rgb_base + 0x0058, pipe->op_mode);/* MDP_RGB_OP_MODE */
439 outpdw(rgb_base + 0x005c, pipe->phasex_step);
440 outpdw(rgb_base + 0x0060, pipe->phasey_step);
441
442 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
443
444 mdp4_stat.pipe[pipe->pipe_num]++;
445}
446
Ravishangar Kalyanam01d68282011-07-18 18:45:06 -0700447
448static void mdp4_overlay_vg_get_src_offset(struct mdp4_overlay_pipe *pipe,
449 char *vg_base, uint32 *luma_off, uint32 *chroma_off)
450{
451 uint32 src_xy;
452 *luma_off = 0;
453 *chroma_off = 0;
454
455 if (pipe->src_x) {
456 src_xy = (pipe->src_y << 16) | pipe->src_x;
457 src_xy &= 0xffff0000;
458 outpdw(vg_base + 0x0004, src_xy); /* MDP_RGB_SRC_XY */
459
460 switch (pipe->src_format) {
461 case MDP_Y_CR_CB_H2V2:
462 case MDP_Y_CB_CR_H2V2:
463 *luma_off = pipe->src_x;
464 *chroma_off = pipe->src_x/2;
465 break;
466
467 case MDP_Y_CBCR_H2V2_TILE:
468 case MDP_Y_CRCB_H2V2_TILE:
469 case MDP_Y_CBCR_H2V2:
470 case MDP_Y_CRCB_H2V2:
471 case MDP_Y_CRCB_H1V1:
472 case MDP_Y_CBCR_H1V1:
473 case MDP_Y_CRCB_H2V1:
474 case MDP_Y_CBCR_H2V1:
475 *luma_off = pipe->src_x;
476 *chroma_off = pipe->src_x;
477 break;
478
479 case MDP_YCRYCB_H2V1:
480 if (pipe->src_x & 0x1)
481 pipe->src_x += 1;
482 *luma_off += pipe->src_x * 2;
483 break;
484
485 case MDP_ARGB_8888:
486 case MDP_RGBA_8888:
487 case MDP_BGRA_8888:
488 case MDP_RGBX_8888:
489 case MDP_RGB_565:
490 case MDP_BGR_565:
491 case MDP_XRGB_8888:
492 case MDP_RGB_888:
493 *luma_off = pipe->src_x * pipe->bpp;
494 break;
495
496 default:
497 pr_err("Source format %u not supported for x offset adjustment\n",
498 pipe->src_format);
499 break;
500 }
501 }
502}
503
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700504void mdp4_overlay_vg_setup(struct mdp4_overlay_pipe *pipe)
505{
506 char *vg_base;
507 uint32 frame_size, src_size, src_xy, dst_size, dst_xy;
Ravishangar Kalyanam01d68282011-07-18 18:45:06 -0700508 uint32 format, pattern, luma_offset, chroma_offset;
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700509 int pnum;
510
511 pnum = pipe->pipe_num - OVERLAY_PIPE_VG1; /* start from 0 */
512 vg_base = MDP_BASE + MDP4_VIDEO_BASE;
513 vg_base += (MDP4_VIDEO_OFF * pnum);
514
515 frame_size = ((pipe->src_height << 16) | pipe->src_width);
516 src_size = ((pipe->src_h << 16) | pipe->src_w);
517 src_xy = ((pipe->src_y << 16) | pipe->src_x);
518 dst_size = ((pipe->dst_h << 16) | pipe->dst_w);
519 dst_xy = ((pipe->dst_y << 16) | pipe->dst_x);
520
521 format = mdp4_overlay_format(pipe);
522 pattern = mdp4_overlay_unpack_pattern(pipe);
523
524 /* not RGB use VG pipe, pure VG pipe */
525 if (pipe->pipe_type != OVERLAY_TYPE_RGB)
526#ifdef MDP4_IGC_LUT_ENABLE
527 pipe->op_mode |= (MDP4_OP_CSC_EN | MDP4_OP_SRC_DATA_YCBCR |
528 MDP4_OP_IGC_LUT_EN);
529#else
530 pipe->op_mode |= (MDP4_OP_CSC_EN | MDP4_OP_SRC_DATA_YCBCR);
531#endif
532
533 mdp4_scale_setup(pipe);
534
535 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
536
537 outpdw(vg_base + 0x0000, src_size); /* MDP_RGB_SRC_SIZE */
538 outpdw(vg_base + 0x0004, src_xy); /* MDP_RGB_SRC_XY */
539 outpdw(vg_base + 0x0008, dst_size); /* MDP_RGB_DST_SIZE */
540 outpdw(vg_base + 0x000c, dst_xy); /* MDP_RGB_DST_XY */
541 outpdw(vg_base + 0x0048, frame_size); /* TILE frame size */
542
Ravishangar Kalyanam01d68282011-07-18 18:45:06 -0700543 /*
544 * Adjust src X offset to avoid MDP from overfetching pixels
545 * present before the offset. This is required for video
546 * frames coming with unused green pixels along the left margin
547 */
548 mdp4_overlay_vg_get_src_offset(pipe, vg_base, &luma_offset,
549 &chroma_offset);
550
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700551 /* luma component plane */
Ravishangar Kalyanam01d68282011-07-18 18:45:06 -0700552 outpdw(vg_base + 0x0010, pipe->srcp0_addr + luma_offset);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700553
554 /* chroma component plane or planar color 1 */
Ravishangar Kalyanam01d68282011-07-18 18:45:06 -0700555 outpdw(vg_base + 0x0014, pipe->srcp1_addr + chroma_offset);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700556
557 /* planar color 2 */
Ravishangar Kalyanam01d68282011-07-18 18:45:06 -0700558 outpdw(vg_base + 0x0018, pipe->srcp2_addr + chroma_offset);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700559
560 outpdw(vg_base + 0x0040,
561 pipe->srcp1_ystride << 16 | pipe->srcp0_ystride);
562
563 outpdw(vg_base + 0x0044,
564 pipe->srcp3_ystride << 16 | pipe->srcp2_ystride);
565
566 outpdw(vg_base + 0x0050, format); /* MDP_RGB_SRC_FORMAT */
567 outpdw(vg_base + 0x0054, pattern); /* MDP_RGB_SRC_UNPACK_PATTERN */
568 outpdw(vg_base + 0x0058, pipe->op_mode);/* MDP_RGB_OP_MODE */
569 outpdw(vg_base + 0x005c, pipe->phasex_step);
570 outpdw(vg_base + 0x0060, pipe->phasey_step);
571
572 if (pipe->op_mode & MDP4_OP_DITHER_EN) {
573 outpdw(vg_base + 0x0068,
574 pipe->r_bit << 4 | pipe->b_bit << 2 | pipe->g_bit);
575 }
576
577 if (pipe->flags & MDP_SHARPENING) {
578 outpdw(vg_base + 0x8200,
579 mdp4_ss_table_value(pipe->req_data.dpp.sharp_strength,
580 0));
581 outpdw(vg_base + 0x8204,
582 mdp4_ss_table_value(pipe->req_data.dpp.sharp_strength,
583 1));
584 }
585
586 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
587
588 mdp4_stat.pipe[pipe->pipe_num]++;
589}
590
591int mdp4_overlay_format2type(uint32 format)
592{
593 switch (format) {
594 case MDP_RGB_565:
595 case MDP_RGB_888:
596 case MDP_BGR_565:
597 case MDP_XRGB_8888:
598 case MDP_ARGB_8888:
599 case MDP_RGBA_8888:
600 case MDP_BGRA_8888:
601 case MDP_RGBX_8888:
602 return OVERLAY_TYPE_RGB;
603 case MDP_YCRYCB_H2V1:
604 case MDP_Y_CRCB_H2V1:
605 case MDP_Y_CBCR_H2V1:
606 case MDP_Y_CRCB_H2V2:
607 case MDP_Y_CBCR_H2V2:
608 case MDP_Y_CBCR_H2V2_TILE:
609 case MDP_Y_CRCB_H2V2_TILE:
610 case MDP_Y_CR_CB_H2V2:
611 case MDP_Y_CB_CR_H2V2:
612 case MDP_Y_CRCB_H1V1:
613 case MDP_Y_CBCR_H1V1:
614 return OVERLAY_TYPE_VIDEO;
615 default:
616 mdp4_stat.err_format++;
617 return -ERANGE;
618 }
619
620}
621
622#define C3_ALPHA 3 /* alpha */
623#define C2_R_Cr 2 /* R/Cr */
624#define C1_B_Cb 1 /* B/Cb */
625#define C0_G_Y 0 /* G/luma */
626#define YUV_444_MAX_WIDTH 1280 /* Max width for YUV 444*/
627
628int mdp4_overlay_format2pipe(struct mdp4_overlay_pipe *pipe)
629{
630 switch (pipe->src_format) {
631 case MDP_RGB_565:
632 pipe->frame_format = MDP4_FRAME_FORMAT_LINEAR;
633 pipe->fetch_plane = OVERLAY_PLANE_INTERLEAVED;
634 pipe->a_bit = 0;
635 pipe->r_bit = 1; /* R, 5 bits */
636 pipe->b_bit = 1; /* B, 5 bits */
637 pipe->g_bit = 2; /* G, 6 bits */
638 pipe->alpha_enable = 0;
639 pipe->unpack_tight = 1;
640 pipe->unpack_align_msb = 0;
641 pipe->unpack_count = 2;
642 pipe->element2 = C2_R_Cr; /* R */
643 pipe->element1 = C0_G_Y; /* G */
644 pipe->element0 = C1_B_Cb; /* B */
645 pipe->bpp = 2; /* 2 bpp */
646 break;
647 case MDP_RGB_888:
648 pipe->frame_format = MDP4_FRAME_FORMAT_LINEAR;
649 pipe->fetch_plane = OVERLAY_PLANE_INTERLEAVED;
650 pipe->a_bit = 0;
651 pipe->r_bit = 3; /* R, 8 bits */
652 pipe->b_bit = 3; /* B, 8 bits */
653 pipe->g_bit = 3; /* G, 8 bits */
654 pipe->alpha_enable = 0;
655 pipe->unpack_tight = 1;
656 pipe->unpack_align_msb = 0;
657 pipe->unpack_count = 2;
658 pipe->element2 = C2_R_Cr; /* R */
659 pipe->element1 = C0_G_Y; /* G */
660 pipe->element0 = C1_B_Cb; /* B */
661 pipe->bpp = 3; /* 3 bpp */
662 break;
663 case MDP_BGR_565:
664 pipe->frame_format = MDP4_FRAME_FORMAT_LINEAR;
665 pipe->fetch_plane = OVERLAY_PLANE_INTERLEAVED;
666 pipe->a_bit = 0;
667 pipe->r_bit = 1; /* R, 5 bits */
668 pipe->b_bit = 1; /* B, 5 bits */
669 pipe->g_bit = 2; /* G, 6 bits */
670 pipe->alpha_enable = 0;
671 pipe->unpack_tight = 1;
672 pipe->unpack_align_msb = 0;
673 pipe->unpack_count = 2;
674 pipe->element2 = C1_B_Cb; /* B */
675 pipe->element1 = C0_G_Y; /* G */
676 pipe->element0 = C2_R_Cr; /* R */
677 pipe->bpp = 2; /* 2 bpp */
678 break;
679 case MDP_XRGB_8888:
680 pipe->frame_format = MDP4_FRAME_FORMAT_LINEAR;
681 pipe->fetch_plane = OVERLAY_PLANE_INTERLEAVED;
682 pipe->a_bit = 3; /* alpha, 4 bits */
683 pipe->r_bit = 3; /* R, 8 bits */
684 pipe->b_bit = 3; /* B, 8 bits */
685 pipe->g_bit = 3; /* G, 8 bits */
686 pipe->alpha_enable = 0;
687 pipe->unpack_tight = 1;
688 pipe->unpack_align_msb = 0;
689 pipe->unpack_count = 3;
690 pipe->element3 = C3_ALPHA; /* alpha */
691 pipe->element2 = C2_R_Cr; /* R */
692 pipe->element1 = C0_G_Y; /* G */
693 pipe->element0 = C1_B_Cb; /* B */
694 pipe->bpp = 4; /* 4 bpp */
695 break;
696 case MDP_ARGB_8888:
697 pipe->frame_format = MDP4_FRAME_FORMAT_LINEAR;
698 pipe->fetch_plane = OVERLAY_PLANE_INTERLEAVED;
699 pipe->a_bit = 3; /* alpha, 4 bits */
700 pipe->r_bit = 3; /* R, 8 bits */
701 pipe->b_bit = 3; /* B, 8 bits */
702 pipe->g_bit = 3; /* G, 8 bits */
703 pipe->alpha_enable = 1;
704 pipe->unpack_tight = 1;
705 pipe->unpack_align_msb = 0;
706 pipe->unpack_count = 3;
707 pipe->element3 = C3_ALPHA; /* alpha */
708 pipe->element2 = C2_R_Cr; /* R */
709 pipe->element1 = C0_G_Y; /* G */
710 pipe->element0 = C1_B_Cb; /* B */
711 pipe->bpp = 4; /* 4 bpp */
712 break;
713 case MDP_RGBA_8888:
714 pipe->frame_format = MDP4_FRAME_FORMAT_LINEAR;
715 pipe->fetch_plane = OVERLAY_PLANE_INTERLEAVED;
716 pipe->a_bit = 3; /* alpha, 4 bits */
717 pipe->r_bit = 3; /* R, 8 bits */
718 pipe->b_bit = 3; /* B, 8 bits */
719 pipe->g_bit = 3; /* G, 8 bits */
720 pipe->alpha_enable = 1;
721 pipe->unpack_tight = 1;
722 pipe->unpack_align_msb = 0;
723 pipe->unpack_count = 3;
724 pipe->element3 = C3_ALPHA; /* alpha */
725 pipe->element2 = C1_B_Cb; /* B */
726 pipe->element1 = C0_G_Y; /* G */
727 pipe->element0 = C2_R_Cr; /* R */
728 pipe->bpp = 4; /* 4 bpp */
729 break;
730 case MDP_RGBX_8888:
731 pipe->frame_format = MDP4_FRAME_FORMAT_LINEAR;
732 pipe->fetch_plane = OVERLAY_PLANE_INTERLEAVED;
733 pipe->a_bit = 3;
734 pipe->r_bit = 3; /* R, 8 bits */
735 pipe->b_bit = 3; /* B, 8 bits */
736 pipe->g_bit = 3; /* G, 8 bits */
737 pipe->alpha_enable = 0;
738 pipe->unpack_tight = 1;
739 pipe->unpack_align_msb = 0;
740 pipe->unpack_count = 3;
741 pipe->element3 = C3_ALPHA; /* alpha */
742 pipe->element2 = C1_B_Cb; /* B */
743 pipe->element1 = C0_G_Y; /* G */
744 pipe->element0 = C2_R_Cr; /* R */
745 pipe->bpp = 4; /* 4 bpp */
746 break;
747 case MDP_BGRA_8888:
748 pipe->frame_format = MDP4_FRAME_FORMAT_LINEAR;
749 pipe->fetch_plane = OVERLAY_PLANE_INTERLEAVED;
750 pipe->a_bit = 3; /* alpha, 4 bits */
751 pipe->r_bit = 3; /* R, 8 bits */
752 pipe->b_bit = 3; /* B, 8 bits */
753 pipe->g_bit = 3; /* G, 8 bits */
754 pipe->alpha_enable = 1;
755 pipe->unpack_tight = 1;
756 pipe->unpack_align_msb = 0;
757 pipe->unpack_count = 3;
758 pipe->element3 = C3_ALPHA; /* alpha */
759 pipe->element2 = C2_R_Cr; /* R */
760 pipe->element1 = C0_G_Y; /* G */
761 pipe->element0 = C1_B_Cb; /* B */
762 pipe->bpp = 4; /* 4 bpp */
763 break;
764 case MDP_YCRYCB_H2V1:
765 pipe->frame_format = MDP4_FRAME_FORMAT_LINEAR;
766 pipe->fetch_plane = OVERLAY_PLANE_INTERLEAVED;
767 pipe->a_bit = 0; /* alpha, 4 bits */
768 pipe->r_bit = 3; /* R, 8 bits */
769 pipe->b_bit = 3; /* B, 8 bits */
770 pipe->g_bit = 3; /* G, 8 bits */
771 pipe->alpha_enable = 0;
772 pipe->unpack_tight = 1;
773 pipe->unpack_align_msb = 0;
774 pipe->unpack_count = 3;
775 pipe->element3 = C0_G_Y; /* G */
776 pipe->element2 = C2_R_Cr; /* R */
777 pipe->element1 = C0_G_Y; /* G */
778 pipe->element0 = C1_B_Cb; /* B */
779 pipe->bpp = 2; /* 2 bpp */
780 pipe->chroma_sample = MDP4_CHROMA_H2V1;
781 break;
782 case MDP_Y_CRCB_H2V1:
783 case MDP_Y_CBCR_H2V1:
784 case MDP_Y_CRCB_H2V2:
785 case MDP_Y_CBCR_H2V2:
786 case MDP_Y_CRCB_H1V1:
787 case MDP_Y_CBCR_H1V1:
788 pipe->frame_format = MDP4_FRAME_FORMAT_LINEAR;
789 pipe->fetch_plane = OVERLAY_PLANE_PSEUDO_PLANAR;
790 pipe->a_bit = 0;
791 pipe->r_bit = 3; /* R, 8 bits */
792 pipe->b_bit = 3; /* B, 8 bits */
793 pipe->g_bit = 3; /* G, 8 bits */
794 pipe->alpha_enable = 0;
795 pipe->unpack_tight = 1;
796 pipe->unpack_align_msb = 0;
797 pipe->unpack_count = 1; /* 2 */
798 pipe->element3 = C0_G_Y; /* not used */
799 pipe->element2 = C0_G_Y; /* not used */
800 if (pipe->src_format == MDP_Y_CRCB_H2V1) {
801 pipe->element1 = C2_R_Cr; /* R */
802 pipe->element0 = C1_B_Cb; /* B */
803 pipe->chroma_sample = MDP4_CHROMA_H2V1;
804 } else if (pipe->src_format == MDP_Y_CRCB_H1V1) {
805 pipe->element1 = C2_R_Cr; /* R */
806 pipe->element0 = C1_B_Cb; /* B */
807 if (pipe->src_width > YUV_444_MAX_WIDTH)
808 pipe->chroma_sample = MDP4_CHROMA_H1V2;
809 else
810 pipe->chroma_sample = MDP4_CHROMA_RGB;
811 } else if (pipe->src_format == MDP_Y_CBCR_H2V1) {
812 pipe->element1 = C1_B_Cb; /* B */
813 pipe->element0 = C2_R_Cr; /* R */
814 pipe->chroma_sample = MDP4_CHROMA_H2V1;
815 } else if (pipe->src_format == MDP_Y_CBCR_H1V1) {
816 pipe->element1 = C1_B_Cb; /* B */
817 pipe->element0 = C2_R_Cr; /* R */
818 if (pipe->src_width > YUV_444_MAX_WIDTH)
819 pipe->chroma_sample = MDP4_CHROMA_H1V2;
820 else
821 pipe->chroma_sample = MDP4_CHROMA_RGB;
822 } else if (pipe->src_format == MDP_Y_CRCB_H2V2) {
823 pipe->element1 = C2_R_Cr; /* R */
824 pipe->element0 = C1_B_Cb; /* B */
825 pipe->chroma_sample = MDP4_CHROMA_420;
826 } else if (pipe->src_format == MDP_Y_CBCR_H2V2) {
827 pipe->element1 = C1_B_Cb; /* B */
828 pipe->element0 = C2_R_Cr; /* R */
829 pipe->chroma_sample = MDP4_CHROMA_420;
830 }
831 pipe->bpp = 2; /* 2 bpp */
832 break;
833 case MDP_Y_CBCR_H2V2_TILE:
834 case MDP_Y_CRCB_H2V2_TILE:
835 pipe->frame_format = MDP4_FRAME_FORMAT_VIDEO_SUPERTILE;
836 pipe->fetch_plane = OVERLAY_PLANE_PSEUDO_PLANAR;
837 pipe->a_bit = 0;
838 pipe->r_bit = 3; /* R, 8 bits */
839 pipe->b_bit = 3; /* B, 8 bits */
840 pipe->g_bit = 3; /* G, 8 bits */
841 pipe->alpha_enable = 0;
842 pipe->unpack_tight = 1;
843 pipe->unpack_align_msb = 0;
844 pipe->unpack_count = 1; /* 2 */
845 pipe->element3 = C0_G_Y; /* not used */
846 pipe->element2 = C0_G_Y; /* not used */
847 if (pipe->src_format == MDP_Y_CRCB_H2V2_TILE) {
848 pipe->element1 = C2_R_Cr; /* R */
849 pipe->element0 = C1_B_Cb; /* B */
850 pipe->chroma_sample = MDP4_CHROMA_420;
851 } else if (pipe->src_format == MDP_Y_CBCR_H2V2_TILE) {
852 pipe->element1 = C1_B_Cb; /* B */
853 pipe->element0 = C2_R_Cr; /* R */
854 pipe->chroma_sample = MDP4_CHROMA_420;
855 }
856 pipe->bpp = 2; /* 2 bpp */
857 break;
858 case MDP_Y_CR_CB_H2V2:
859 case MDP_Y_CB_CR_H2V2:
860 pipe->frame_format = MDP4_FRAME_FORMAT_LINEAR;
861 pipe->fetch_plane = OVERLAY_PLANE_PLANAR;
862 pipe->a_bit = 0;
863 pipe->r_bit = 3; /* R, 8 bits */
864 pipe->b_bit = 3; /* B, 8 bits */
865 pipe->g_bit = 3; /* G, 8 bits */
866 pipe->alpha_enable = 0;
867 pipe->unpack_tight = 1;
868 pipe->unpack_align_msb = 0;
869 pipe->unpack_count = 1; /* 2 */
870 pipe->element3 = C0_G_Y; /* not used */
871 pipe->element2 = C0_G_Y; /* not used */
872 if (pipe->src_format == MDP_Y_CR_CB_H2V2) {
873 pipe->element1 = C2_R_Cr; /* R */
874 pipe->element0 = C1_B_Cb; /* B */
875 pipe->chroma_sample = MDP4_CHROMA_420;
876 } else if (pipe->src_format == MDP_Y_CB_CR_H2V2) {
877 pipe->element1 = C1_B_Cb; /* B */
878 pipe->element0 = C2_R_Cr; /* R */
879 pipe->chroma_sample = MDP4_CHROMA_420;
880 }
881 pipe->bpp = 2; /* 2 bpp */
882 break;
883 default:
884 /* not likely */
885 mdp4_stat.err_format++;
886 return -ERANGE;
887 }
888
889 return 0;
890}
891
892/*
893 * color_key_convert: output with 12 bits color key
894 */
895static uint32 color_key_convert(int start, int num, uint32 color)
896{
897 uint32 data;
898
899 data = (color >> start) & ((1 << num) - 1);
900
901 /* convert to 8 bits */
902 if (num == 5)
903 data = ((data << 3) | (data >> 2));
904 else if (num == 6)
905 data = ((data << 2) | (data >> 4));
906
907 /* convert 8 bits to 12 bits */
908 data = (data << 4) | (data >> 4);
909
910 return data;
911}
912
913void transp_color_key(int format, uint32 transp,
914 uint32 *c0, uint32 *c1, uint32 *c2)
915{
916 int b_start, g_start, r_start;
917 int b_num, g_num, r_num;
918
919 switch (format) {
920 case MDP_RGB_565:
921 b_start = 0;
922 g_start = 5;
923 r_start = 11;
924 r_num = 5;
925 g_num = 6;
926 b_num = 5;
927 break;
928 case MDP_RGB_888:
929 case MDP_XRGB_8888:
930 case MDP_ARGB_8888:
931 case MDP_BGRA_8888:
932 b_start = 0;
933 g_start = 8;
934 r_start = 16;
935 r_num = 8;
936 g_num = 8;
937 b_num = 8;
938 break;
939 case MDP_RGBA_8888:
940 case MDP_RGBX_8888:
941 b_start = 16;
942 g_start = 8;
943 r_start = 0;
944 r_num = 8;
945 g_num = 8;
946 b_num = 8;
947 break;
948 case MDP_BGR_565:
949 b_start = 11;
950 g_start = 5;
951 r_start = 0;
952 r_num = 5;
953 g_num = 6;
954 b_num = 5;
955 break;
956 case MDP_Y_CB_CR_H2V2:
957 case MDP_Y_CBCR_H2V2:
958 case MDP_Y_CBCR_H2V1:
959 b_start = 8;
960 g_start = 16;
961 r_start = 0;
962 r_num = 8;
963 g_num = 8;
964 b_num = 8;
965 break;
966 case MDP_Y_CR_CB_H2V2:
967 case MDP_Y_CRCB_H2V2:
968 case MDP_Y_CRCB_H2V1:
969 case MDP_Y_CRCB_H1V1:
970 case MDP_Y_CBCR_H1V1:
971 b_start = 0;
972 g_start = 16;
973 r_start = 8;
974 r_num = 8;
975 g_num = 8;
976 b_num = 8;
977 break;
978 default:
979 b_start = 0;
980 g_start = 8;
981 r_start = 16;
982 r_num = 8;
983 g_num = 8;
984 b_num = 8;
985 break;
986 }
987
988 *c0 = color_key_convert(g_start, g_num, transp);
989 *c1 = color_key_convert(b_start, b_num, transp);
990 *c2 = color_key_convert(r_start, r_num, transp);
991}
992
993uint32 mdp4_overlay_format(struct mdp4_overlay_pipe *pipe)
994{
995 uint32 format;
996
997 format = 0;
998
999 if (pipe->solid_fill)
1000 format |= MDP4_FORMAT_SOLID_FILL;
1001
1002 if (pipe->unpack_align_msb)
1003 format |= MDP4_FORMAT_UNPACK_ALIGN_MSB;
1004
1005 if (pipe->unpack_tight)
1006 format |= MDP4_FORMAT_UNPACK_TIGHT;
1007
1008 if (pipe->alpha_enable)
1009 format |= MDP4_FORMAT_ALPHA_ENABLE;
1010
1011 if (pipe->flags & MDP_SOURCE_ROTATED_90)
1012 format |= MDP4_FORMAT_90_ROTATED;
1013 format |= (pipe->unpack_count << 13);
1014 format |= ((pipe->bpp - 1) << 9);
1015 format |= (pipe->a_bit << 6);
1016 format |= (pipe->r_bit << 4);
1017 format |= (pipe->b_bit << 2);
1018 format |= pipe->g_bit;
1019
1020 format |= (pipe->frame_format << 29);
1021
1022 if (pipe->fetch_plane == OVERLAY_PLANE_PSEUDO_PLANAR ||
1023 pipe->fetch_plane == OVERLAY_PLANE_PLANAR) {
1024 /* video/graphic */
1025 format |= (pipe->fetch_plane << 19);
1026 format |= (pipe->chroma_site << 28);
1027 format |= (pipe->chroma_sample << 26);
1028 }
1029
1030 return format;
1031}
1032
1033uint32 mdp4_overlay_unpack_pattern(struct mdp4_overlay_pipe *pipe)
1034{
1035 return (pipe->element3 << 24) | (pipe->element2 << 16) |
1036 (pipe->element1 << 8) | pipe->element0;
1037}
1038
1039/*
1040 * mdp4_overlayproc_cfg: only be called from base layer
1041 */
1042void mdp4_overlayproc_cfg(struct mdp4_overlay_pipe *pipe)
1043{
1044 uint32 data, intf;
1045 char *overlay_base;
1046
1047 intf = 0;
1048 if (pipe->mixer_num == MDP4_MIXER1) {
1049 overlay_base = MDP_BASE + MDP4_OVERLAYPROC1_BASE;/* 0x18000 */
1050 intf = inpdw(MDP_BASE + 0x0038); /* MDP_DISP_INTF_SEL */
1051 intf >>= 4;
1052 intf &= 0x03;
1053 } else
1054 overlay_base = MDP_BASE + MDP4_OVERLAYPROC0_BASE;/* 0x10000 */
1055
1056 if (mdp_is_in_isr == FALSE)
1057 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
1058
1059 /*
1060 * BLT only siupport at primary display
1061 */
1062 if (pipe->mixer_num == MDP4_MIXER0 && pipe->blt_addr) {
1063 int off, bpp;
1064#ifdef BLT_RGB565
1065 bpp = 2; /* overlay ouput is RGB565 */
1066#else
1067 bpp = 3; /* overlay ouput is RGB888 */
1068#endif
1069 data = pipe->src_height;
1070 data <<= 16;
1071 data |= pipe->src_width;
1072 outpdw(overlay_base + 0x0008, data); /* ROI, height + width */
1073 if (ctrl->panel_mode & MDP4_PANEL_LCDC ||
1074 ctrl->panel_mode & MDP4_PANEL_DSI_VIDEO) {
1075 outpdw(overlay_base + 0x000c, pipe->blt_addr);
1076 outpdw(overlay_base + 0x0010, pipe->src_width * bpp);
1077 off = pipe->src_height * pipe->src_width * bpp;
1078 outpdw(overlay_base + 0x001c, pipe->blt_addr + off);
1079 /* LCDC - FRAME BUFFER + vsync rate */
1080 outpdw(overlay_base + 0x0004, 0x02);
1081 } else { /* MDDI */
1082 off = 0;
1083 if (pipe->ov_cnt & 0x01)
1084 off = pipe->src_height * pipe->src_width * bpp;
1085
1086 outpdw(overlay_base + 0x000c, pipe->blt_addr + off);
1087 /* overlay ouput is RGB888 */
1088 outpdw(overlay_base + 0x0010, pipe->src_width * bpp);
1089 outpdw(overlay_base + 0x001c, pipe->blt_addr + off);
1090 /* MDDI - BLT + on demand */
1091 outpdw(overlay_base + 0x0004, 0x08);
1092 }
1093#ifdef BLT_RGB565
1094 outpdw(overlay_base + 0x0014, 0x1); /* RGB565 */
1095#else
1096 outpdw(overlay_base + 0x0014, 0x0); /* RGB888 */
1097#endif
1098 } else {
1099 data = pipe->src_height;
1100 data <<= 16;
1101 data |= pipe->src_width;
1102 outpdw(overlay_base + 0x0008, data); /* ROI, height + width */
1103 outpdw(overlay_base + 0x000c, pipe->srcp0_addr);
1104 outpdw(overlay_base + 0x0010, pipe->srcp0_ystride);
1105 outpdw(overlay_base + 0x0004, 0x01); /* directout */
1106 }
1107
1108 if (pipe->mixer_num == MDP4_MIXER1) {
1109 if (intf == TV_INTF) {
1110 outpdw(overlay_base + 0x0014, 0x02); /* yuv422 */
1111 /* overlay1 CSC config */
1112 outpdw(overlay_base + 0x0200, 0x05); /* rgb->yuv */
1113 }
1114 }
1115
1116#ifdef MDP4_IGC_LUT_ENABLE
1117 outpdw(overlay_base + 0x0014, 0x4); /* GC_LUT_EN, 888 */
1118#endif
1119
1120 if (mdp_is_in_isr == FALSE)
1121 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
1122}
1123
1124int mdp4_overlay_pipe_staged(int mixer)
1125{
1126 uint32 data, mask, i;
1127 int p1, p2;
1128
1129 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
1130 data = inpdw(MDP_BASE + 0x10100);
1131 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
1132 p1 = 0;
1133 p2 = 0;
1134 for (i = 0; i < 8; i++) {
1135 mask = data & 0x0f;
1136 if (mask) {
1137 if (mask <= 4)
1138 p1++;
1139 else
1140 p2++;
1141 }
1142 data >>= 4;
1143 }
1144
1145 if (mixer)
1146 return p2;
1147 else
1148 return p1;
1149}
1150
kuogee hsieh405dc302011-07-21 15:06:59 -07001151int mdp4_mixer_info(int mixer_num, struct mdp_mixer_info *info)
1152{
1153
1154 int ndx, cnt;
1155 struct mdp4_overlay_pipe *pipe;
1156
1157 if (mixer_num > MDP4_MIXER_MAX)
1158 return -ENODEV;
1159
1160 cnt = 0;
1161 ndx = 1; /* ndx 0 if not used */
1162
1163 for ( ; ndx < MDP4_MIXER_STAGE_MAX; ndx++) {
1164 pipe = ctrl->stage[mixer_num][ndx];
1165 if (pipe == NULL)
1166 continue;
1167 info->z_order = pipe->mixer_stage - MDP4_MIXER_STAGE0;
1168 info->ptype = pipe->pipe_type;
1169 info->pnum = pipe->pipe_num;
1170 info->pndx = pipe->pipe_ndx;
1171 info->mixer_num = pipe->mixer_num;
1172 info++;
1173 cnt++;
1174 }
1175 return cnt;
1176}
1177
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001178void mdp4_mixer_stage_up(struct mdp4_overlay_pipe *pipe)
1179{
1180 uint32 data, mask, snum, stage, mixer, pnum;
1181
1182 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
1183
1184 stage = pipe->mixer_stage;
1185 mixer = pipe->mixer_num;
1186 pnum = pipe->pipe_num;
1187
1188 /* MDP_LAYERMIXER_IN_CFG, shard by both mixer 0 and 1 */
1189 data = inpdw(MDP_BASE + 0x10100);
1190
1191 if (mixer == MDP4_MIXER1)
1192 stage += 8;
1193
1194 if (pipe->pipe_num >= OVERLAY_PIPE_VG1) {/* VG1 and VG2 */
1195 pnum -= OVERLAY_PIPE_VG1; /* start from 0 */
1196 snum = 0;
1197 snum += (4 * pnum);
1198 } else {
1199 snum = 8;
1200 snum += (4 * pnum); /* RGB1 and RGB2 */
1201 }
1202
1203 mask = 0x0f;
1204 mask <<= snum;
1205 stage <<= snum;
1206 data &= ~mask; /* clear old bits */
1207
1208 data |= stage;
1209
1210 outpdw(MDP_BASE + 0x10100, data); /* MDP_LAYERMIXER_IN_CFG */
1211
1212 data = inpdw(MDP_BASE + 0x10100);
1213
1214 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
1215
1216 ctrl->stage[pipe->mixer_num][pipe->mixer_stage] = pipe; /* keep it */
1217}
1218
1219void mdp4_mixer_stage_down(struct mdp4_overlay_pipe *pipe)
1220{
1221 uint32 data, mask, snum, stage, mixer, pnum;
1222
1223 stage = pipe->mixer_stage;
1224 mixer = pipe->mixer_num;
1225 pnum = pipe->pipe_num;
1226
1227 if (pipe != ctrl->stage[mixer][stage]) /* not runing */
1228 return;
1229
1230 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
1231
1232 /* MDP_LAYERMIXER_IN_CFG, shard by both mixer 0 and 1 */
1233 data = inpdw(MDP_BASE + 0x10100);
1234
1235 if (mixer == MDP4_MIXER1)
1236 stage += 8;
1237
1238 if (pipe->pipe_num >= OVERLAY_PIPE_VG1) {/* VG1 and VG2 */
1239 pnum -= OVERLAY_PIPE_VG1; /* start from 0 */
1240 snum = 0;
1241 snum += (4 * pnum);
1242 } else {
1243 snum = 8;
1244 snum += (4 * pnum); /* RGB1 and RGB2 */
1245 }
1246
1247 mask = 0x0f;
1248 mask <<= snum;
1249 data &= ~mask; /* clear old bits */
1250
1251 outpdw(MDP_BASE + 0x10100, data); /* MDP_LAYERMIXER_IN_CFG */
1252
1253 data = inpdw(MDP_BASE + 0x10100);
1254
1255 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
1256
1257 ctrl->stage[pipe->mixer_num][pipe->mixer_stage] = NULL; /* clear it */
1258}
1259
1260void mdp4_mixer_blend_setup(struct mdp4_overlay_pipe *pipe)
1261{
1262 struct mdp4_overlay_pipe *bg_pipe;
1263 unsigned char *overlay_base, *rgb_base;
1264 uint32 c0, c1, c2, blend_op, constant_color = 0, rgb_src_format;
1265 int off;
1266
1267 if (pipe->mixer_num) /* mixer number, /dev/fb0, /dev/fb1 */
1268 overlay_base = MDP_BASE + MDP4_OVERLAYPROC1_BASE;/* 0x18000 */
1269 else
1270 overlay_base = MDP_BASE + MDP4_OVERLAYPROC0_BASE;/* 0x10000 */
1271
1272 /* stage 0 to stage 2 */
1273 off = 0x20 * (pipe->mixer_stage - MDP4_MIXER_STAGE0);
1274
1275 bg_pipe = mdp4_overlay_stage_pipe(pipe->mixer_num,
1276 MDP4_MIXER_STAGE_BASE);
1277 if (bg_pipe == NULL) {
1278 pr_err("%s: Error: no bg_pipe\n", __func__);
1279 return;
1280 }
1281
1282 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
1283
1284 blend_op = 0;
1285
1286 if (pipe->is_fg) {
1287 blend_op |= (MDP4_BLEND_FG_ALPHA_FG_CONST |
1288 MDP4_BLEND_BG_ALPHA_BG_CONST);
1289 outpdw(overlay_base + off + 0x108, pipe->alpha);
1290 outpdw(overlay_base + off + 0x10c, 0xff - pipe->alpha);
1291 if (pipe->alpha == 0xff) {
1292 rgb_base = MDP_BASE + MDP4_RGB_BASE;
1293 rgb_base += MDP4_RGB_OFF * bg_pipe->pipe_num;
1294 rgb_src_format = inpdw(rgb_base + 0x50);
1295 rgb_src_format |= MDP4_FORMAT_SOLID_FILL;
1296 outpdw(rgb_base + 0x50, rgb_src_format);
1297 outpdw(rgb_base + 0x1008, constant_color);
1298 }
1299 } else {
1300 if (bg_pipe->alpha_enable && pipe->alpha_enable) {
1301 /* both pipe have alpha */
1302 blend_op |= (MDP4_BLEND_FG_ALPHA_BG_PIXEL |
1303 MDP4_BLEND_FG_INV_ALPHA |
1304 MDP4_BLEND_BG_ALPHA_BG_PIXEL);
1305 } else if (bg_pipe->alpha_enable && pipe->alpha_enable == 0) {
1306 /* no alpha on both pipe */
1307 blend_op = (MDP4_BLEND_BG_ALPHA_BG_PIXEL |
1308 MDP4_BLEND_FG_ALPHA_BG_PIXEL |
1309 MDP4_BLEND_FG_INV_ALPHA);
1310 }
1311 }
1312
1313
1314 if (pipe->transp != MDP_TRANSP_NOP) {
1315 if (pipe->is_fg) {
1316 transp_color_key(pipe->src_format, pipe->transp,
1317 &c0, &c1, &c2);
1318 /* Fg blocked */
1319 blend_op |= MDP4_BLEND_FG_TRANSP_EN;
1320 /* lower limit */
1321 outpdw(overlay_base + off + 0x110,
1322 (c1 << 16 | c0));/* low */
1323 outpdw(overlay_base + off + 0x114, c2);/* low */
1324 /* upper limit */
1325 outpdw(overlay_base + off + 0x118,
1326 (c1 << 16 | c0));
1327 outpdw(overlay_base + off + 0x11c, c2);
1328 } else {
1329 transp_color_key(bg_pipe->src_format,
1330 pipe->transp, &c0, &c1, &c2);
1331 /* bg blocked */
1332 blend_op |= MDP4_BLEND_BG_TRANSP_EN;
1333 /* lower limit */
1334 outpdw(overlay_base + 0x180,
1335 (c1 << 16 | c0));/* low */
1336 outpdw(overlay_base + 0x184, c2);/* low */
1337 /* upper limit */
1338 outpdw(overlay_base + 0x188,
1339 (c1 << 16 | c0));/* high */
1340 outpdw(overlay_base + 0x18c, c2);/* high */
1341 }
1342 }
1343
1344 outpdw(overlay_base + off + 0x104, blend_op);
1345
1346 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
1347}
1348
1349void mdp4_overlay_reg_flush(struct mdp4_overlay_pipe *pipe, int all)
1350{
1351 struct mdp4_overlay_pipe *bg_pipe;
1352 uint32 bits = 0;
1353
1354 if (pipe->mixer_num == MDP4_MIXER1)
1355 bits |= 0x02;
1356 else
1357 bits |= 0x01;
1358
1359 if (all) {
1360 if (pipe->pipe_num <= OVERLAY_PIPE_RGB2) {
1361 if (pipe->pipe_num == OVERLAY_PIPE_RGB2)
1362 bits |= 0x20;
1363 else
1364 bits |= 0x10;
1365 } else {
1366 if (pipe->is_fg && pipe->alpha == 0xFF) {
1367 bg_pipe = mdp4_overlay_stage_pipe(
1368 pipe->mixer_num,
1369 MDP4_MIXER_STAGE_BASE);
1370 if (bg_pipe->pipe_num <= OVERLAY_PIPE_RGB2) {
1371 if (bg_pipe->pipe_num ==
1372 OVERLAY_PIPE_RGB2)
1373 bits |= 0x20;
1374 else
1375 bits |= 0x10;
1376 }
1377 }
1378 if (pipe->pipe_num == OVERLAY_PIPE_VG2)
1379 bits |= 0x08;
1380 else
1381 bits |= 0x04;
1382 }
1383 }
1384
1385 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
1386 outpdw(MDP_BASE + 0x18000, bits); /* MDP_OVERLAY_REG_FLUSH */
1387 mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
1388}
1389
1390struct mdp4_overlay_pipe *mdp4_overlay_stage_pipe(int mixer, int stage)
1391{
1392 return ctrl->stage[mixer][stage];
1393}
1394
1395struct mdp4_overlay_pipe *mdp4_overlay_ndx2pipe(int ndx)
1396{
1397 struct mdp4_overlay_pipe *pipe;
1398
1399 if (ndx <= 0 || ndx > MDP4_MAX_PIPE)
1400 return NULL;
1401
1402 pipe = &ctrl->plist[ndx - 1]; /* ndx start from 1 */
1403
1404 if (pipe->pipe_used == 0)
1405 return NULL;
1406
1407 return pipe;
1408}
1409
1410struct mdp4_overlay_pipe *mdp4_overlay_pipe_alloc(
1411 int ptype, int mixer, int req_share)
1412{
1413 int i, j, ndx, found;
1414 struct mdp4_overlay_pipe *pipe, *opipe;
1415 struct mdp4_pipe_desc *pd;
1416
1417 found = 0;
1418 pipe = &ctrl->plist[0];
1419
1420 for (i = 0; i < MDP4_MAX_PIPE; i++) {
1421 if (pipe->pipe_type == ptype && pipe->pipe_used == 0) {
1422 pd = &ctrl->ov_pipe[pipe->pipe_num];
1423 if (pd->share) { /* pipe can be shared */
1424 if (pd->ref_cnt == 0) {
1425 /* not yet been used */
1426 found++;
1427 break;
1428 }
1429 /* pipe occupied already */
1430 if (req_share && pd->ref_cnt < MDP4_MAX_SHARE) {
1431 for (j = 0; j < MDP4_MAX_SHARE; j++) {
1432 ndx = pd->ndx_list[j];
1433 if (ndx != 0)
1434 break;
1435 }
1436 /* ndx satrt from 1 */
1437 opipe = &ctrl->plist[ndx - 1];
1438 /*
1439 * occupied pipe willing to share and
1440 * same mixer
1441 */
1442 if (opipe->pipe_share &&
1443 opipe->mixer_num == mixer) {
1444 found++;
1445 break;
1446 }
1447 }
1448 } else { /* not a shared pipe */
1449 if (req_share == 0 && pd->ref_cnt == 0) {
1450 found++;
1451 break;
1452 }
1453 }
1454 }
1455 pipe++;
1456 }
1457
1458 if (found) {
1459 init_completion(&pipe->comp);
1460 init_completion(&pipe->dmas_comp);
1461 pr_info("%s: pipe=%x ndx=%d num=%d share=%d cnt=%d\n",
1462 __func__, (int)pipe, pipe->pipe_ndx, pipe->pipe_num,
1463 pd->share, pd->ref_cnt);
1464 return pipe;
1465 }
1466
1467 pr_debug("%s: ptype=%d mixer=%d req_share=%d FAILED\n",
1468 __func__, ptype, mixer, req_share);
1469
1470 return NULL;
1471}
1472
1473
1474void mdp4_overlay_pipe_free(struct mdp4_overlay_pipe *pipe)
1475{
1476 int i;
1477 uint32 ptype, num, ndx;
1478 struct mdp4_pipe_desc *pd;
1479
1480 pr_debug("%s: pipe=%x ndx=%d\n", __func__,
1481 (int)pipe, pipe->pipe_ndx);
1482 pd = &ctrl->ov_pipe[pipe->pipe_num];
1483 if (pd->ref_cnt) {
1484 pd->ref_cnt--;
1485 for (i = 0; i < MDP4_MAX_SHARE; i++) {
1486 if (pd->ndx_list[i] == pipe->pipe_ndx) {
1487 pd->ndx_list[i] = 0;
1488 break;
1489 }
1490 }
1491 }
1492
1493 pd->player = NULL;
1494
1495 ptype = pipe->pipe_type;
1496 num = pipe->pipe_num;
1497 ndx = pipe->pipe_ndx;
1498
1499 memset(pipe, 0, sizeof(*pipe));
1500
1501 pipe->pipe_type = ptype;
1502 pipe->pipe_num = num;
1503 pipe->pipe_ndx = ndx;
1504}
1505
1506int mdp4_overlay_req_check(uint32 id, uint32 z_order, uint32 mixer)
1507{
1508 struct mdp4_overlay_pipe *pipe;
1509
1510 pipe = ctrl->stage[mixer][z_order];
1511
1512 if (pipe == NULL)
1513 return 0;
1514
1515 if (pipe->pipe_ndx == id) /* same req, recycle */
1516 return 0;
1517
1518 if (id == MSMFB_NEW_REQUEST) { /* new request */
1519 if (pipe->pipe_num >= OVERLAY_PIPE_VG1) /* share pipe */
1520 return 0;
1521 }
1522
1523 return -EPERM;
1524}
1525
1526static int mdp4_overlay_validate_downscale(struct mdp_overlay *req,
1527 struct msm_fb_data_type *mfd, uint32 perf_level, uint32 pclk_rate)
1528{
1529 __u32 panel_clk_khz, mdp_clk_khz;
1530 __u32 num_hsync_pix_clks, mdp_clks_per_hsync, src_wh;
1531 __u32 hsync_period_ps, mdp_period_ps, total_hsync_period_ps;
1532 unsigned long fill_rate_y_dir, fill_rate_x_dir;
1533 unsigned long fillratex100, mdp_pixels_produced;
1534 unsigned long mdp_clk_hz;
1535
1536 pr_debug("%s: LCDC Mode Downscale validation with MDP Core"
1537 " Clk rate\n", __func__);
1538 pr_debug("src_w %u, src_h %u, dst_w %u, dst_h %u\n",
1539 req->src_rect.w, req->src_rect.h, req->dst_rect.w,
1540 req->dst_rect.h);
1541
1542
1543 panel_clk_khz = pclk_rate/1000;
1544 mdp_clk_hz = mdp_perf_level2clk_rate(perf_level);
1545
1546 if (!mdp_clk_hz) {
1547 pr_debug("mdp_perf_level2clk_rate returned 0,"
1548 "Downscale Validation incomplete\n");
1549 return 0;
1550 }
1551
1552 mdp_clk_khz = mdp_clk_hz/1000;
1553
1554 num_hsync_pix_clks = mfd->panel_info.lcdc.h_back_porch +
1555 mfd->panel_info.lcdc.h_front_porch +
1556 mfd->panel_info.lcdc.h_pulse_width +
1557 mfd->panel_info.xres;
1558
1559 hsync_period_ps = 1000000000/panel_clk_khz;
1560 mdp_period_ps = 1000000000/mdp_clk_khz;
1561
1562 total_hsync_period_ps = num_hsync_pix_clks * hsync_period_ps;
1563 mdp_clks_per_hsync = total_hsync_period_ps/mdp_period_ps;
1564
1565 pr_debug("hsync_period_ps %u, mdp_period_ps %u,"
1566 "total_hsync_period_ps %u\n", hsync_period_ps,
1567 mdp_period_ps, total_hsync_period_ps);
1568
1569 src_wh = req->src_rect.w * req->src_rect.h;
1570 if (src_wh % req->dst_rect.h)
1571 fill_rate_y_dir = (src_wh / req->dst_rect.h) + 1;
1572 else
1573 fill_rate_y_dir = (src_wh / req->dst_rect.h);
1574
1575 fill_rate_x_dir = (mfd->panel_info.xres - req->dst_rect.w)
1576 + req->src_rect.w;
1577
1578 if (fill_rate_y_dir >= fill_rate_x_dir)
1579 fillratex100 = 100 * fill_rate_y_dir / mfd->panel_info.xres;
1580 else
1581 fillratex100 = 100 * fill_rate_x_dir / mfd->panel_info.xres;
1582
1583 pr_debug("mdp_clks_per_hsync %u, fill_rate_y_dir %lu,"
1584 "fill_rate_x_dir %lu\n", mdp_clks_per_hsync,
1585 fill_rate_y_dir, fill_rate_x_dir);
1586
1587 mdp_pixels_produced = 100 * mdp_clks_per_hsync/fillratex100;
1588 pr_debug("fillratex100 %lu, mdp_pixels_produced %lu\n",
1589 fillratex100, mdp_pixels_produced);
1590 if (mdp_pixels_produced <= mfd->panel_info.xres) {
1591 pr_err("%s(): LCDC underflow detected during downscale\n",
1592 __func__);
1593 return -ERANGE;
1594 }
1595
1596 return 0;
1597}
1598
1599static int mdp4_overlay_req2pipe(struct mdp_overlay *req, int mixer,
1600 struct mdp4_overlay_pipe **ppipe,
1601 struct msm_fb_data_type *mfd)
1602{
1603 struct mdp4_overlay_pipe *pipe;
1604 struct mdp4_pipe_desc *pd;
1605 int ret, ptype, req_share;
1606 int j;
1607
1608 if (mfd == NULL) {
1609 pr_err("%s: mfd == NULL, -ENODEV\n", __func__);
1610 return -ENODEV;
1611 }
1612
1613 if (mixer >= MDP4_MAX_MIXER) {
1614 pr_err("%s: mixer out of range!\n", __func__);
1615 mdp4_stat.err_mixer++;
1616 return -ERANGE;
1617 }
1618
1619 if (req->z_order < 0 || req->z_order > 2) {
1620 pr_err("%s: z_order=%d out of range!\n", __func__,
1621 req->z_order);
1622 mdp4_stat.err_zorder++;
1623 return -ERANGE;
1624 }
1625
1626 if (req->src_rect.h == 0 || req->src_rect.w == 0) {
1627 pr_err("%s: src img of zero size!\n", __func__);
1628 mdp4_stat.err_size++;
1629 return -EINVAL;
1630 }
1631
1632
1633 if (req->dst_rect.h > (req->src_rect.h * 8)) { /* too much */
1634 mdp4_stat.err_scale++;
1635 pr_err("%s: scale up, too much (h)!\n", __func__);
1636 return -ERANGE;
1637 }
1638
1639 if (req->src_rect.h > (req->dst_rect.h * 8)) { /* too little */
1640 mdp4_stat.err_scale++;
1641 pr_err("%s: scale down, too little (h)!\n", __func__);
1642 return -ERANGE;
1643 }
1644
1645 if (req->dst_rect.w > (req->src_rect.w * 8)) { /* too much */
1646 mdp4_stat.err_scale++;
1647 pr_err("%s: scale up, too much (w)!\n", __func__);
1648 return -ERANGE;
1649 }
1650
1651 if (req->src_rect.w > (req->dst_rect.w * 8)) { /* too little */
1652 mdp4_stat.err_scale++;
1653 pr_err("%s: scale down, too little (w)!\n", __func__);
1654 return -ERANGE;
1655 }
1656
1657 if (mdp_hw_revision == MDP4_REVISION_V1) {
1658 /* non integer down saceling ratio smaller than 1/4
1659 * is not supportted
1660 */
1661 if (req->src_rect.h > (req->dst_rect.h * 4)) {
1662 if (req->src_rect.h % req->dst_rect.h) {
1663 mdp4_stat.err_scale++;
1664 pr_err("%s: need integer (h)!\n", __func__);
1665 return -ERANGE;
1666 }
1667 }
1668
1669 if (req->src_rect.w > (req->dst_rect.w * 4)) {
1670 if (req->src_rect.w % req->dst_rect.w) {
1671 mdp4_stat.err_scale++;
1672 pr_err("%s: need integer (w)!\n", __func__);
1673 return -ERANGE;
1674 }
1675 }
1676 }
1677
1678 if (((req->src_rect.x + req->src_rect.w) > req->src.width) ||
1679 ((req->src_rect.y + req->src_rect.h) > req->src.height)) {
1680 mdp4_stat.err_size++;
1681 pr_err("%s invalid src rectangle\n", __func__);
1682 return -ERANGE;
1683 }
1684
1685 if (ctrl->panel_3d != MDP4_3D_SIDE_BY_SIDE) {
1686 int xres;
1687 int yres;
1688
1689 xres = mfd->panel_info.xres;
1690 yres = mfd->panel_info.yres;
1691
1692 if (((req->dst_rect.x + req->dst_rect.w) > xres) ||
1693 ((req->dst_rect.y + req->dst_rect.h) > yres)) {
1694 mdp4_stat.err_size++;
1695 pr_err("%s invalid dst rectangle\n", __func__);
1696 return -ERANGE;
1697 }
1698 }
1699
1700 ptype = mdp4_overlay_format2type(req->src.format);
1701 if (ptype < 0) {
1702 pr_err("%s: mdp4_overlay_format2type!\n", __func__);
1703 return ptype;
1704 }
1705
1706 req_share = (req->flags & MDP_OV_PIPE_SHARE);
1707
1708 if (req->id == MSMFB_NEW_REQUEST) /* new request */
1709 pipe = mdp4_overlay_pipe_alloc(ptype, mixer, req_share);
1710 else
1711 pipe = mdp4_overlay_ndx2pipe(req->id);
1712
1713 if (pipe == NULL) {
1714 pr_err("%s: pipe == NULL!\n", __func__);
1715 return -ENOMEM;
1716 }
1717
1718 /* no down scale at rgb pipe */
1719 if (pipe->pipe_num <= OVERLAY_PIPE_RGB2) {
1720 if ((req->src_rect.h > req->dst_rect.h) ||
1721 (req->src_rect.w > req->dst_rect.w)) {
1722 pr_err("%s: h>h || w>w!\n", __func__);
1723 return -ERANGE;
1724 }
1725 }
1726
1727 pipe->src_format = req->src.format;
1728 ret = mdp4_overlay_format2pipe(pipe);
1729 if (ret < 0) {
1730 pr_err("%s: mdp4_overlay_format2pipe!\n", __func__);
1731 return ret;
1732 }
1733
1734 /*
1735 * base layer == 1, reserved for frame buffer
1736 * zorder 0 == stage 0 == 2
1737 * zorder 1 == stage 1 == 3
1738 * zorder 2 == stage 2 == 4
1739 */
1740 if (req->id == MSMFB_NEW_REQUEST) { /* new request */
1741 pd = &ctrl->ov_pipe[pipe->pipe_num];
1742 for (j = 0; j < MDP4_MAX_SHARE; j++) {
1743 if (pd->ndx_list[j] == 0) {
1744 pd->ndx_list[j] = pipe->pipe_ndx;
1745 break;
1746 }
1747 }
1748 pipe->pipe_share = req_share;
1749 pd->ref_cnt++;
1750 pipe->pipe_used++;
1751 pipe->mixer_num = mixer;
1752 pipe->mixer_stage = req->z_order + MDP4_MIXER_STAGE0;
1753 pr_debug("%s: zorder=%d pipe ndx=%d num=%d\n", __func__,
1754 req->z_order, pipe->pipe_ndx, pipe->pipe_num);
1755
1756 }
1757
1758 pipe->src_width = req->src.width & 0x07ff; /* source img width */
1759 pipe->src_height = req->src.height & 0x07ff; /* source img height */
1760 pipe->src_h = req->src_rect.h & 0x07ff;
1761 pipe->src_w = req->src_rect.w & 0x07ff;
1762 pipe->src_y = req->src_rect.y & 0x07ff;
1763 pipe->src_x = req->src_rect.x & 0x07ff;
1764 pipe->dst_h = req->dst_rect.h & 0x07ff;
1765 pipe->dst_w = req->dst_rect.w & 0x07ff;
1766 pipe->dst_y = req->dst_rect.y & 0x07ff;
1767 pipe->dst_x = req->dst_rect.x & 0x07ff;
1768
1769 pipe->op_mode = 0;
1770
1771 if (req->flags & MDP_FLIP_LR)
1772 pipe->op_mode |= MDP4_OP_FLIP_LR;
1773
1774 if (req->flags & MDP_FLIP_UD)
1775 pipe->op_mode |= MDP4_OP_FLIP_UD;
1776
1777 if (req->flags & MDP_DITHER)
1778 pipe->op_mode |= MDP4_OP_DITHER_EN;
1779
1780 if (req->flags & MDP_DEINTERLACE)
1781 pipe->op_mode |= MDP4_OP_DEINT_EN;
1782
1783 if (req->flags & MDP_DEINTERLACE_ODD)
1784 pipe->op_mode |= MDP4_OP_DEINT_ODD_REF;
1785
1786 pipe->is_fg = req->is_fg;/* control alpha and color key */
1787
1788 pipe->alpha = req->alpha & 0x0ff;
1789
1790 pipe->transp = req->transp_mask;
1791
1792 *ppipe = pipe;
1793
1794 return 0;
1795}
1796
1797static int get_img(struct msmfb_data *img, struct fb_info *info,
1798 unsigned long *start, unsigned long *len, struct file **pp_file)
1799{
1800 int put_needed, ret = 0, fb_num;
1801 struct file *file;
1802#ifdef CONFIG_ANDROID_PMEM
1803 unsigned long vstart;
1804#endif
1805
1806 if (img->flags & MDP_BLIT_SRC_GEM) {
1807 *pp_file = NULL;
1808 return kgsl_gem_obj_addr(img->memory_id, (int) img->priv,
1809 start, len);
1810 }
1811
1812#ifdef CONFIG_ANDROID_PMEM
1813 if (!get_pmem_file(img->memory_id, start, &vstart, len, pp_file))
1814 return 0;
1815#endif
1816 file = fget_light(img->memory_id, &put_needed);
1817 if (file == NULL)
1818 return -1;
1819
1820 if (MAJOR(file->f_dentry->d_inode->i_rdev) == FB_MAJOR) {
1821 fb_num = MINOR(file->f_dentry->d_inode->i_rdev);
1822 if (get_fb_phys_info(start, len, fb_num))
1823 ret = -1;
1824 else
1825 *pp_file = file;
1826 } else
1827 ret = -1;
1828 if (ret)
1829 fput_light(file, put_needed);
1830 return ret;
1831}
1832
kuogee hsieh4aea2742011-07-06 11:05:05 -07001833#ifdef CONFIG_FB_MSM_MIPI_DSI
1834int mdp4_overlay_3d_sbys(struct fb_info *info, struct msmfb_overlay_3d *req)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001835{
1836 struct msm_fb_data_type *mfd = (struct msm_fb_data_type *)info->par;
1837 int ret = -EPERM;
1838
1839 if (mutex_lock_interruptible(&mfd->dma->ov_mutex))
1840 return -EINTR;
1841
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001842 if (ctrl->panel_mode & MDP4_PANEL_DSI_CMD) {
kuogee hsieh4aea2742011-07-06 11:05:05 -07001843 mdp4_dsi_cmd_3d_sbys(mfd, req);
1844 ret = 0;
1845 } else if (ctrl->panel_mode & MDP4_PANEL_DSI_VIDEO) {
1846 mdp4_dsi_video_3d_sbys(mfd, req);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001847 ret = 0;
1848 }
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001849 mutex_unlock(&mfd->dma->ov_mutex);
1850
1851 return ret;
1852}
kuogee hsieh4aea2742011-07-06 11:05:05 -07001853#else
1854int mdp4_overlay_3d_sbys(struct fb_info *info, struct msmfb_overlay_3d *req)
1855{
1856 /* do nothing */
1857 return -EPERM;
1858}
1859#endif
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001860
1861#ifdef CONFIG_FB_MSM_OVERLAY_WRITEBACK
1862int mdp4_overlay_blt(struct fb_info *info, struct msmfb_overlay_blt *req)
1863{
1864 struct msm_fb_data_type *mfd = (struct msm_fb_data_type *)info->par;
1865
1866 if (mfd == NULL)
1867 return -ENODEV;
1868
1869 if (mutex_lock_interruptible(&mfd->dma->ov_mutex))
1870 return -EINTR;
1871
1872 if (ctrl->panel_mode & MDP4_PANEL_DSI_CMD)
1873 mdp4_dsi_overlay_blt(mfd, req);
1874 else if (ctrl->panel_mode & MDP4_PANEL_DSI_VIDEO)
1875 mdp4_dsi_video_overlay_blt(mfd, req);
1876 else if (ctrl->panel_mode & MDP4_PANEL_LCDC)
1877 mdp4_lcdc_overlay_blt(mfd, req);
1878
1879 mutex_unlock(&mfd->dma->ov_mutex);
1880
1881 return 0;
1882}
1883
1884int mdp4_overlay_blt_offset(struct fb_info *info, struct msmfb_overlay_blt *req)
1885{
1886 int ret = 0;
1887
1888 struct msm_fb_data_type *mfd = (struct msm_fb_data_type *)info->par;
1889
1890 if (mutex_lock_interruptible(&mfd->dma->ov_mutex))
1891 return -EINTR;
1892
1893 if (ctrl->panel_mode & MDP4_PANEL_DSI_CMD)
1894 ret = mdp4_dsi_overlay_blt_offset(mfd, req);
1895 else if (ctrl->panel_mode & MDP4_PANEL_DSI_VIDEO)
1896 ret = mdp4_dsi_video_overlay_blt_offset(mfd, req);
1897 else if (ctrl->panel_mode & MDP4_PANEL_LCDC)
1898 ret = mdp4_lcdc_overlay_blt_offset(mfd, req);
1899
1900 mutex_unlock(&mfd->dma->ov_mutex);
1901
1902 return ret;
1903}
1904#endif
1905
1906int mdp4_overlay_get(struct fb_info *info, struct mdp_overlay *req)
1907{
1908 struct mdp4_overlay_pipe *pipe;
1909
1910 pipe = mdp4_overlay_ndx2pipe(req->id);
1911 if (pipe == NULL)
1912 return -ENODEV;
1913
1914 *req = pipe->req_data;
1915
1916 return 0;
1917}
1918
1919#define OVERLAY_VGA_SIZE 0x04B000
1920#define OVERLAY_720P_TILE_SIZE 0x0E6000
1921#define OVERLAY_WSVGA_SIZE 0x98000 /* 1024x608, align 600 to 32bit */
1922#define OVERLAY_PERF_LEVEL1 1
1923#define OVERLAY_PERF_LEVEL2 2
1924#define OVERLAY_PERF_LEVEL3 3
1925#define OVERLAY_PERF_LEVEL4 4
1926
1927#ifdef CONFIG_MSM_BUS_SCALING
1928#define OVERLAY_BUS_SCALE_TABLE_BASE 6
1929#endif
1930
1931static int mdp4_overlay_is_rgb_type(int format)
1932{
1933 switch (format) {
1934 case MDP_RGB_565:
1935 case MDP_RGB_888:
1936 case MDP_BGR_565:
1937 case MDP_XRGB_8888:
1938 case MDP_ARGB_8888:
1939 case MDP_RGBA_8888:
1940 case MDP_BGRA_8888:
1941 case MDP_RGBX_8888:
1942 return 1;
1943 default:
1944 return 0;
1945 }
1946}
1947
1948static uint32 mdp4_overlay_get_perf_level(struct mdp_overlay *req)
1949{
1950 int is_fg;
1951
1952 if (req->is_fg && ((req->alpha & 0x0ff) == 0xff))
1953 is_fg = 1;
1954
1955 if (req->flags & MDP_DEINTERLACE)
1956 return OVERLAY_PERF_LEVEL1;
1957
1958 if (mdp4_overlay_is_rgb_type(req->src.format) && is_fg &&
1959 ((req->src.width * req->src.height) <= OVERLAY_WSVGA_SIZE))
1960 return OVERLAY_PERF_LEVEL4;
1961 else if (mdp4_overlay_is_rgb_type(req->src.format))
1962 return OVERLAY_PERF_LEVEL1;
1963
1964 if (ctrl->ov_pipe[OVERLAY_PIPE_VG1].ref_cnt &&
1965 ctrl->ov_pipe[OVERLAY_PIPE_VG2].ref_cnt)
1966 return OVERLAY_PERF_LEVEL1;
1967
1968 if (req->src.width*req->src.height <= OVERLAY_VGA_SIZE)
1969 return OVERLAY_PERF_LEVEL3;
1970 else if (req->src.width*req->src.height <= OVERLAY_720P_TILE_SIZE)
1971 return OVERLAY_PERF_LEVEL2;
1972 else
1973 return OVERLAY_PERF_LEVEL1;
1974}
1975
kuogee hsiehc4b8b2f2011-07-12 13:32:14 -07001976void mdp4_set_perf_level(void)
1977{
1978 static int old_perf_level;
1979
1980 if (old_perf_level != new_perf_level) {
1981 mdp_set_core_clk(new_perf_level);
1982 old_perf_level = new_perf_level;
1983 }
1984}
1985
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001986int mdp4_overlay_set(struct fb_info *info, struct mdp_overlay *req)
1987{
1988 struct msm_fb_data_type *mfd = (struct msm_fb_data_type *)info->par;
kuogee hsiehc4b8b2f2011-07-12 13:32:14 -07001989 int ret, mixer, perf_level;
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001990 struct mdp4_overlay_pipe *pipe;
kuogee hsieh9452ecb2011-08-01 18:26:23 -07001991 uint32 flags;
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001992
1993 if (mfd == NULL) {
1994 pr_err("%s: mfd == NULL, -ENODEV\n", __func__);
1995 return -ENODEV;
1996 }
1997
1998 if (!mfd->panel_power_on) /* suspended */
1999 return -EPERM;
2000
2001 if (req->src.format == MDP_FB_FORMAT)
2002 req->src.format = mfd->fb_imgType;
2003
2004 if (mutex_lock_interruptible(&mfd->dma->ov_mutex)) {
2005 pr_err("%s: mutex_lock_interruptible, -EINTR\n", __func__);
2006 return -EINTR;
2007 }
2008
2009 perf_level = mdp4_overlay_get_perf_level(req);
2010
2011 if ((mfd->panel_info.type == LCDC_PANEL) &&
2012 (req->src_rect.h >
2013 req->dst_rect.h || req->src_rect.w > req->dst_rect.w)) {
2014 if (mdp4_overlay_validate_downscale(req, mfd,
2015 perf_level, mfd->panel_info.clk_rate)) {
2016 mutex_unlock(&mfd->dma->ov_mutex);
2017 return -ERANGE;
2018 }
2019 }
2020 if ((mfd->panel_info.type == MIPI_VIDEO_PANEL) &&
2021 (req->src_rect.h >
2022 req->dst_rect.h || req->src_rect.w > req->dst_rect.w)) {
2023 if (mdp4_overlay_validate_downscale(req, mfd,
2024 perf_level, (&mfd->panel_info.mipi)->dsi_pclk_rate)) {
2025 mutex_unlock(&mfd->dma->ov_mutex);
2026 return -ERANGE;
2027 }
2028 }
2029 mixer = mfd->panel_info.pdest; /* DISPLAY_1 or DISPLAY_2 */
2030
2031 ret = mdp4_overlay_req2pipe(req, mixer, &pipe, mfd);
2032 if (ret < 0) {
2033 mutex_unlock(&mfd->dma->ov_mutex);
2034 pr_err("%s: mdp4_overlay_req2pipe, ret=%d\n", __func__, ret);
2035 return ret;
2036 }
2037
2038#ifdef CONFIG_FB_MSM_MIPI_DSI
2039 /*
2040 * writeback (blt) mode to provide work around for
2041 * dsi cmd mode interface hardware bug.
2042 */
2043 if (ctrl->panel_mode & MDP4_PANEL_DSI_CMD) {
2044 if (mixer == MDP4_MIXER0 && req->dst_rect.x != 0) {
2045 mdp4_dsi_blt_dmap_busy_wait(mfd);
2046 mdp4_dsi_overlay_blt_start(mfd);
2047 }
2048 }
2049#endif
2050
2051 /* return id back to user */
2052 req->id = pipe->pipe_ndx; /* pipe_ndx start from 1 */
2053 pipe->req_data = *req; /* keep original req */
2054
2055 pipe->flags = req->flags;
2056
2057 if (pipe->flags & MDP_SHARPENING) {
2058 bool test = ((pipe->req_data.dpp.sharp_strength > 0) &&
2059 ((req->src_rect.w > req->dst_rect.w) &&
2060 (req->src_rect.h > req->dst_rect.h)));
2061 if (test) {
2062 pr_warn("%s: No sharpening while downscaling.\n",
2063 __func__);
2064 pipe->flags &= ~MDP_SHARPENING;
2065 }
2066 }
2067
2068 mdp4_stat.overlay_set[pipe->mixer_num]++;
2069
2070 if (ctrl->panel_mode & MDP4_PANEL_MDDI) {
2071 if (mdp_hw_revision == MDP4_REVISION_V2_1 &&
2072 pipe->mixer_num == MDP4_MIXER0)
2073 mdp4_overlay_status_write(MDP4_OVERLAY_TYPE_SET, true);
2074 }
2075
kuogee hsiehc4b8b2f2011-07-12 13:32:14 -07002076
2077 new_perf_level = perf_level;
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002078
kuogee hsieh9452ecb2011-08-01 18:26:23 -07002079 /* change clck base on perf level */
2080 flags = pipe->flags;
2081 pipe->flags &= ~MDP_OV_PLAY_NOWAIT;
2082 if (pipe->mixer_num == MDP4_MIXER0) {
2083 if (ctrl->panel_mode & MDP4_PANEL_DSI_VIDEO) {
2084 mdp4_overlay_dsi_video_vsync_push(mfd, pipe);
2085 } else if (ctrl->panel_mode & MDP4_PANEL_DSI_CMD) {
2086 mdp4_dsi_cmd_dma_busy_wait(mfd);
2087 mdp4_dsi_blt_dmap_busy_wait(mfd);
2088 mdp4_set_perf_level();
2089 } else if (ctrl->panel_mode & MDP4_PANEL_LCDC) {
2090 mdp4_overlay_lcdc_vsync_push(mfd, pipe);
2091 } else if (ctrl->panel_mode & MDP4_PANEL_MDDI) {
2092 mdp4_mddi_dma_busy_wait(mfd);
2093 mdp4_set_perf_level();
2094 }
2095 } else {
2096 if (ctrl->panel_mode & MDP4_PANEL_DTV)
2097 mdp4_overlay_dtv_vsync_push(mfd, pipe);
2098 }
2099 pipe->flags = flags;
2100
2101 mutex_unlock(&mfd->dma->ov_mutex);
2102
2103
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002104#ifdef CONFIG_MSM_BUS_SCALING
2105 if (pipe->mixer_num == MDP4_MIXER0) {
2106 mdp_bus_scale_update_request(OVERLAY_BUS_SCALE_TABLE_BASE
2107 - perf_level);
2108 }
2109#endif
2110
2111 return 0;
2112}
2113
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002114int mdp4_overlay_unset(struct fb_info *info, int ndx)
2115{
2116 struct msm_fb_data_type *mfd = (struct msm_fb_data_type *)info->par;
2117 struct mdp4_overlay_pipe *pipe;
2118 uint32 flags;
2119
2120 if (mfd == NULL)
2121 return -ENODEV;
2122
2123 if (mutex_lock_interruptible(&mfd->dma->ov_mutex))
2124 return -EINTR;
2125
2126 pipe = mdp4_overlay_ndx2pipe(ndx);
2127
2128 if (pipe == NULL) {
2129 mutex_unlock(&mfd->dma->ov_mutex);
2130 return -ENODEV;
2131 }
2132
2133 if (pipe->mixer_num == MDP4_MIXER1)
2134 ctrl->mixer1_played = 0;
2135 else {
2136 /* mixer 0 */
2137 ctrl->mixer0_played = 0;
2138#ifdef CONFIG_FB_MSM_MIPI_DSI
2139 if (ctrl->panel_mode & MDP4_PANEL_DSI_CMD) {
2140 if (mfd->panel_power_on) {
2141 mdp4_dsi_blt_dmap_busy_wait(mfd);
2142 }
2143 }
2144#else
2145 if (ctrl->panel_mode & MDP4_PANEL_MDDI) {
2146 if (mfd->panel_power_on)
2147 mdp4_mddi_dma_busy_wait(mfd);
2148 }
2149#endif
2150 }
2151
2152 mdp4_mixer_stage_down(pipe);
2153
2154 if (pipe->mixer_num == MDP4_MIXER0) {
2155#ifdef CONFIG_FB_MSM_MIPI_DSI
2156 if (ctrl->panel_mode & MDP4_PANEL_DSI_CMD) {
2157 if (mfd->panel_power_on)
2158 if (mdp4_dsi_overlay_blt_stop(mfd) == 0)
2159 mdp4_dsi_cmd_overlay_restore();
2160 } else if (ctrl->panel_mode & MDP4_PANEL_DSI_VIDEO) {
2161 flags = pipe->flags;
2162 pipe->flags &= ~MDP_OV_PLAY_NOWAIT;
kuogee hsiehebca0c72011-07-14 13:30:33 -07002163 mdp4_overlay_reg_flush(pipe, 1);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002164 mdp4_overlay_dsi_video_vsync_push(mfd, pipe);
2165 pipe->flags = flags;
2166 }
2167#else
2168 if (ctrl->panel_mode & MDP4_PANEL_MDDI) {
2169 if (mdp_hw_revision == MDP4_REVISION_V2_1)
2170 mdp4_overlay_status_write(
2171 MDP4_OVERLAY_TYPE_UNSET, true);
2172 if (mfd->panel_power_on)
2173 mdp4_mddi_overlay_restore();
2174 }
2175#endif
2176 else if (ctrl->panel_mode & MDP4_PANEL_LCDC) {
2177 flags = pipe->flags;
2178 pipe->flags &= ~MDP_OV_PLAY_NOWAIT;
kuogee hsiehebca0c72011-07-14 13:30:33 -07002179 mdp4_overlay_reg_flush(pipe, 1);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002180 mdp4_overlay_lcdc_vsync_push(mfd, pipe);
2181 pipe->flags = flags;
2182 }
2183 }
2184#ifdef CONFIG_FB_MSM_DTV
2185 else { /* mixer1, DTV, ATV */
kuogee hsieh9452ecb2011-08-01 18:26:23 -07002186 if (ctrl->panel_mode & MDP4_PANEL_DTV) {
2187 flags = pipe->flags;
2188 pipe->flags &= ~MDP_OV_PLAY_NOWAIT;
2189 mdp4_overlay_dtv_vsync_push(mfd, pipe);
2190 pipe->flags = flags;
2191 }
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002192 }
2193#endif
2194
2195 mdp4_stat.overlay_unset[pipe->mixer_num]++;
2196
2197 mdp4_overlay_pipe_free(pipe);
2198
2199 if (!(ctrl->ov_pipe[OVERLAY_PIPE_VG1].ref_cnt +
2200 ctrl->ov_pipe[OVERLAY_PIPE_VG2].ref_cnt))
kuogee hsiehc4b8b2f2011-07-12 13:32:14 -07002201 new_perf_level = OVERLAY_PERF_LEVEL4;
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002202
2203 mutex_unlock(&mfd->dma->ov_mutex);
2204
2205#ifdef CONFIG_MSM_BUS_SCALING
2206 if (pipe->mixer_num == MDP4_MIXER0)
2207 if (mfd->panel_power_on)
2208 mdp_bus_scale_update_request(2);
2209#endif
2210 return 0;
2211}
2212
2213struct tile_desc {
2214 uint32 width; /* tile's width */
2215 uint32 height; /* tile's height */
2216 uint32 row_tile_w; /* tiles per row's width */
2217 uint32 row_tile_h; /* tiles per row's height */
2218};
2219
2220void tile_samsung(struct tile_desc *tp)
2221{
2222 /*
2223 * each row of samsung tile consists of two tiles in height
2224 * and two tiles in width which means width should align to
2225 * 64 x 2 bytes and height should align to 32 x 2 bytes.
2226 * video decoder generate two tiles in width and one tile
2227 * in height which ends up height align to 32 X 1 bytes.
2228 */
2229 tp->width = 64; /* 64 bytes */
2230 tp->row_tile_w = 2; /* 2 tiles per row's width */
2231 tp->height = 32; /* 32 bytes */
2232 tp->row_tile_h = 1; /* 1 tiles per row's height */
2233}
2234
2235uint32 tile_mem_size(struct mdp4_overlay_pipe *pipe, struct tile_desc *tp)
2236{
2237 uint32 tile_w, tile_h;
2238 uint32 row_num_w, row_num_h;
2239
2240
2241 tile_w = tp->width * tp->row_tile_w;
2242 tile_h = tp->height * tp->row_tile_h;
2243
2244 row_num_w = (pipe->src_width + tile_w - 1) / tile_w;
2245 row_num_h = (pipe->src_height + tile_h - 1) / tile_h;
2246 return ((row_num_w * row_num_h * tile_w * tile_h) + 8191) & ~8191;
2247}
2248
2249int mdp4_overlay_play(struct fb_info *info, struct msmfb_overlay_data *req,
2250 struct file **pp_src_file, struct file **pp_src_plane1_file,
2251 struct file **pp_src_plane2_file)
2252{
2253 struct msm_fb_data_type *mfd = (struct msm_fb_data_type *)info->par;
2254 struct msmfb_data *img;
2255 struct mdp4_overlay_pipe *pipe;
2256 struct mdp4_pipe_desc *pd;
2257 ulong start, addr;
2258 ulong len = 0;
2259 struct file *p_src_file = 0;
2260 struct file *p_src_plane1_file = 0, *p_src_plane2_file = 0;
2261 uint32_t overlay_version = 0;
2262
2263 if (mfd == NULL)
2264 return -ENODEV;
2265
2266 if (!mfd->panel_power_on) /* suspended */
2267 return -EPERM;
2268
2269 pipe = mdp4_overlay_ndx2pipe(req->id);
2270 if (pipe == NULL) {
2271 pr_err("%s: req_id=%d Error\n", __func__, req->id);
2272 return -ENODEV;
2273 }
2274
2275 if (mutex_lock_interruptible(&mfd->dma->ov_mutex))
2276 return -EINTR;
2277
2278 pd = &ctrl->ov_pipe[pipe->pipe_num];
2279 if (pd->player && pipe != pd->player) {
2280 if (pipe->pipe_type == OVERLAY_TYPE_RGB) {
2281 mutex_unlock(&mfd->dma->ov_mutex);
2282 return 0; /* ignore it, kicked out already */
2283 }
2284 }
2285
2286 pd->player = pipe; /* keep */
2287
2288 img = &req->data;
2289 get_img(img, info, &start, &len, &p_src_file);
2290 if (len == 0) {
2291 mutex_unlock(&mfd->dma->ov_mutex);
2292 pr_err("%s: pmem Error\n", __func__);
2293 return -1;
2294 }
2295 *pp_src_file = p_src_file;
2296
2297 addr = start + img->offset;
2298 pipe->srcp0_addr = addr;
2299 pipe->srcp0_ystride = pipe->src_width * pipe->bpp;
2300
2301 if ((req->version_key & VERSION_KEY_MASK) == 0xF9E8D700)
2302 overlay_version = (req->version_key & ~VERSION_KEY_MASK);
2303
2304 if (pipe->fetch_plane == OVERLAY_PLANE_PSEUDO_PLANAR) {
2305 if (overlay_version > 0) {
2306 img = &req->plane1_data;
2307 get_img(img, info, &start, &len, &p_src_plane1_file);
2308 if (len == 0) {
2309 mutex_unlock(&mfd->dma->ov_mutex);
2310 pr_err("%s: Error to get plane1\n", __func__);
2311 return -EINVAL;
2312 }
2313 pipe->srcp1_addr = start + img->offset;
2314 *pp_src_plane1_file = p_src_plane1_file;
2315 } else if (pipe->frame_format ==
2316 MDP4_FRAME_FORMAT_VIDEO_SUPERTILE) {
2317 struct tile_desc tile;
2318
2319 tile_samsung(&tile);
2320 pipe->srcp1_addr = addr + tile_mem_size(pipe, &tile);
2321 } else {
2322 pipe->srcp1_addr = addr + (pipe->src_width *
2323 pipe->src_height);
2324 }
2325 pipe->srcp0_ystride = pipe->src_width;
2326 if ((pipe->src_format == MDP_Y_CRCB_H1V1) ||
2327 (pipe->src_format == MDP_Y_CBCR_H1V1)) {
2328 if (pipe->src_width > YUV_444_MAX_WIDTH)
2329 pipe->srcp1_ystride = pipe->src_width << 2;
2330 else
2331 pipe->srcp1_ystride = pipe->src_width << 1;
2332 } else
2333 pipe->srcp1_ystride = pipe->src_width;
2334
2335 } else if (pipe->fetch_plane == OVERLAY_PLANE_PLANAR) {
2336 if (overlay_version > 0) {
2337 img = &req->plane1_data;
2338 get_img(img, info, &start, &len, &p_src_plane1_file);
2339 if (len == 0) {
2340 mutex_unlock(&mfd->dma->ov_mutex);
2341 pr_err("%s: Error to get plane1\n", __func__);
2342 return -EINVAL;
2343 }
2344 pipe->srcp1_addr = start + img->offset;
2345 *pp_src_plane1_file = p_src_plane1_file;
2346
2347 img = &req->plane2_data;
2348 get_img(img, info, &start, &len, &p_src_plane2_file);
2349 if (len == 0) {
2350 mutex_unlock(&mfd->dma->ov_mutex);
2351 pr_err("%s: Error to get plane2\n", __func__);
2352 return -EINVAL;
2353 }
2354 pipe->srcp2_addr = start + img->offset;
2355 *pp_src_plane2_file = p_src_plane2_file;
2356 } else {
2357 addr += (pipe->src_width * pipe->src_height);
2358 pipe->srcp1_addr = addr;
2359 addr += ((pipe->src_width / 2) *
2360 (pipe->src_height / 2));
2361 pipe->srcp2_addr = addr;
2362 }
2363 pipe->srcp0_ystride = pipe->src_width;
2364 pipe->srcp1_ystride = pipe->src_width / 2;
2365 pipe->srcp2_ystride = pipe->src_width / 2;
2366 }
2367
2368 if (pipe->pipe_num >= OVERLAY_PIPE_VG1)
2369 mdp4_overlay_vg_setup(pipe); /* video/graphic pipe */
2370 else {
2371 if (pipe->flags & MDP_SHARPENING) {
2372 pr_warn(
2373 "%s: Sharpening/Smoothing not supported on RGB pipe\n",
2374 __func__);
2375 pipe->flags &= ~MDP_SHARPENING;
2376 }
2377 mdp4_overlay_rgb_setup(pipe); /* rgb pipe */
2378 }
2379
2380 mdp4_mixer_blend_setup(pipe);
2381 mdp4_mixer_stage_up(pipe);
2382
2383 if (pipe->mixer_num == MDP4_MIXER1) {
2384 ctrl->mixer1_played++;
2385 /* enternal interface */
2386 if (ctrl->panel_mode & MDP4_PANEL_DTV)
2387#ifdef CONFIG_FB_MSM_DTV
2388 mdp4_overlay_dtv_ov_done_push(mfd, pipe);
2389#else
2390 mdp4_overlay_reg_flush(pipe, 1);
2391#endif
2392 else if (ctrl->panel_mode & MDP4_PANEL_ATV)
2393 mdp4_overlay_reg_flush(pipe, 1);
2394 } else {
2395 /* primary interface */
2396 ctrl->mixer0_played++;
kuogee hsieh3de11f32011-07-08 14:09:11 -07002397 if (ctrl->panel_mode & MDP4_PANEL_LCDC) {
2398 mdp4_overlay_reg_flush(pipe, 1);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002399 mdp4_overlay_lcdc_vsync_push(mfd, pipe);
kuogee hsieh3de11f32011-07-08 14:09:11 -07002400 }
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002401#ifdef CONFIG_FB_MSM_MIPI_DSI
kuogee hsieh3de11f32011-07-08 14:09:11 -07002402 else if (ctrl->panel_mode & MDP4_PANEL_DSI_VIDEO) {
2403 mdp4_overlay_reg_flush(pipe, 1);
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002404 mdp4_overlay_dsi_video_vsync_push(mfd, pipe);
kuogee hsieh3de11f32011-07-08 14:09:11 -07002405 }
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07002406#endif
2407 else {
2408 /* mddi & mipi dsi cmd mode */
2409 if (pipe->flags & MDP_OV_PLAY_NOWAIT) {
2410 mdp4_stat.overlay_play[pipe->mixer_num]++;
2411 mutex_unlock(&mfd->dma->ov_mutex);
2412 return 0;
2413 }
2414#ifdef CONFIG_FB_MSM_MIPI_DSI
2415 if (ctrl->panel_mode & MDP4_PANEL_DSI_CMD) {
2416 mdp4_dsi_cmd_dma_busy_wait(mfd);
2417 mdp4_dsi_cmd_kickoff_video(mfd, pipe);
2418 }
2419#else
2420 if (ctrl->panel_mode & MDP4_PANEL_MDDI) {
2421 mdp4_mddi_dma_busy_wait(mfd);
2422 mdp4_mddi_kickoff_video(mfd, pipe);
2423 }
2424#endif
2425 }
2426 }
2427
2428 mdp4_stat.overlay_play[pipe->mixer_num]++;
2429
2430 mutex_unlock(&mfd->dma->ov_mutex);
2431
2432 return 0;
2433}