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review.evervolv.com / android_kernel_htc_msm8960 / 95b6847e8335dff39428f711db7d6b6f497d4015 / . / drivers / gpu / msm / kgsl_iommu.h
blob: efc3d9cf1de10c7c97cb2b4abc701f21189c2a27 [file] [log] [blame]
Shubhraprakash Daseb6df1d2012-05-01 00:55:35 -0600[diff] [blame]1/* Copyright (c) 2012, Code Aurora Forum. All rights reserved.
2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 *
12 */
13#ifndef __KGSL_IOMMU_H
14#define __KGSL_IOMMU_H
15
16#include <mach/iommu.h>
17
Shubhraprakash Das2b8716b2012-05-04 16:58:40 -0600[diff] [blame]18/* IOMMU registers and masks */
19#define KGSL_IOMMU_TTBR0 0x10
20#define KGSL_IOMMU_TTBR1 0x14
Jordan Crouse95b68472012-05-25 10:25:01 -0600[diff] [blame^]21#define KGSL_IOMMU_FSR 0x20
22
Shubhraprakash Das2b8716b2012-05-04 16:58:40 -0600[diff] [blame]23#define KGSL_IOMMU_TTBR0_PA_MASK 0x0003FFFF
24#define KGSL_IOMMU_TTBR0_PA_SHIFT 14
25#define KGSL_IOMMU_CTX_TLBIALL 0x800
26#define KGSL_IOMMU_CONTEXTIDR 0x8
27#define KGSL_IOMMU_CONTEXTIDR_ASID_MASK 0xFF
28#define KGSL_IOMMU_CONTEXTIDR_ASID_SHIFT 0
29#define KGSL_IOMMU_CTX_TLBIASID 0x804
30#define KGSL_IOMMU_CTX_SHIFT 12
Shubhraprakash Dasd3f937c2012-05-07 12:44:40 -0600[diff] [blame]31
32#define KGSL_IOMMU_MAX_ASIDS 256
33#define KGSL_IOMMU_ASID_REUSE 2
34
Shubhraprakash Daseb6df1d2012-05-01 00:55:35 -0600[diff] [blame]35/*
36 * Max number of iommu units that the gpu core can have
37 * On APQ8064, KGSL can control a maximum of 2 IOMMU units.
38 */
39#define KGSL_IOMMU_MAX_UNITS 2
40
41/* Max number of iommu contexts per IOMMU unit */
42#define KGSL_IOMMU_MAX_DEVS_PER_UNIT 2
43
Shubhraprakash Dasd8cbcd12012-05-07 16:11:32 -0600[diff] [blame]44/* Macros to read/write IOMMU registers */
45#define KGSL_IOMMU_SET_IOMMU_REG(base_addr, ctx, REG, val) \
46 writel_relaxed(val, base_addr + \
47 (ctx << KGSL_IOMMU_CTX_SHIFT) + \
48 KGSL_IOMMU_##REG)
49
50#define KGSL_IOMMU_GET_IOMMU_REG(base_addr, ctx, REG) \
51 readl_relaxed(base_addr + \
52 (ctx << KGSL_IOMMU_CTX_SHIFT) + \
53 KGSL_IOMMU_##REG)
54
55/* Gets the lsb value of pagetable */
56#define KGSL_IOMMMU_PT_LSB(pt_val) \
57 (pt_val & ~(KGSL_IOMMU_TTBR0_PA_MASK << \
58 KGSL_IOMMU_TTBR0_PA_SHIFT))
59
Shubhraprakash Dase9541a32012-05-09 22:25:55 -0600[diff] [blame]60/* offset at which a nop command is placed in setstate_memory */
61#define KGSL_IOMMU_SETSTATE_NOP_OFFSET 1024
62
Shubhraprakash Daseb6df1d2012-05-01 00:55:35 -0600[diff] [blame]63/*
64 * struct kgsl_iommu_device - Structure holding data about iommu contexts
65 * @dev: Device pointer to iommu context
66 * @attached: Indicates whether this iommu context is presently attached to
67 * a pagetable/domain or not
68 * @pt_lsb: The LSB of IOMMU_TTBR0 register which is the pagetable
69 * register
70 * @ctx_id: This iommu units context id. It can be either 0 or 1
71 * @clk_enabled: If set indicates that iommu clocks of this iommu context
72 * are on, else the clocks are off
73 */
74struct kgsl_iommu_device {
75 struct device *dev;
76 bool attached;
77 unsigned int pt_lsb;
78 enum kgsl_iommu_context_id ctx_id;
79 bool clk_enabled;
Jordan Crouse95b68472012-05-25 10:25:01 -0600[diff] [blame^]80 struct kgsl_device *kgsldev;
Shubhraprakash Daseb6df1d2012-05-01 00:55:35 -0600[diff] [blame]81};
82
83/*
84 * struct kgsl_iommu_unit - Structure holding data about iommu units. An IOMMU
85 * units is basically a separte IOMMU h/w block with it's own IOMMU contexts
86 * @dev: Pointer to array of struct kgsl_iommu_device which has information
87 * about the IOMMU contexts under this IOMMU unit
88 * @dev_count: Number of IOMMU contexts that are valid in the previous feild
89 * @reg_map: Memory descriptor which holds the mapped address of this IOMMU
90 * units register range
91 */
92struct kgsl_iommu_unit {
93 struct kgsl_iommu_device dev[KGSL_IOMMU_MAX_DEVS_PER_UNIT];
94 unsigned int dev_count;
95 struct kgsl_memdesc reg_map;
96};
97
98/*
99 * struct kgsl_iommu - Structure holding iommu data for kgsl driver
100 * @dev: Array of kgsl_iommu_device which contain information about
101 * iommu contexts owned by graphics cores
102 * @unit_count: Number of IOMMU units that are available for this
103 * instance of the IOMMU driver
104 * @iommu_last_cmd_ts: The timestamp of last command submitted that
105 * aceeses iommu registers
106 * @device: Pointer to kgsl device
107 * @asids: A bit structure indicating which id's are presently used
108 * @asid: Contains the initial value of IOMMU_CONTEXTIDR when a domain
109 * is first attached
Shubhraprakash Dasd3f937c2012-05-07 12:44:40 -0600[diff] [blame]110 * asid_reuse: Holds the number of times the reuse asid is reused
Shubhraprakash Daseb6df1d2012-05-01 00:55:35 -0600[diff] [blame]111 */
112struct kgsl_iommu {
113 struct kgsl_iommu_unit iommu_units[KGSL_IOMMU_MAX_UNITS];
114 unsigned int unit_count;
115 unsigned int iommu_last_cmd_ts;
116 struct kgsl_device *device;
117 unsigned long *asids;
118 unsigned int asid;
Shubhraprakash Dasd3f937c2012-05-07 12:44:40 -0600[diff] [blame]119 unsigned int asid_reuse;
120};
121
122/*
123 * struct kgsl_iommu_pt - Iommu pagetable structure private to kgsl driver
124 * @domain: Pointer to the iommu domain that contains the iommu pagetable
125 * @iommu: Pointer to iommu structure
126 * @asid: The asid assigned to this domain
127 */
128struct kgsl_iommu_pt {
129 struct iommu_domain *domain;
130 struct kgsl_iommu *iommu;
131 unsigned int asid;
Shubhraprakash Daseb6df1d2012-05-01 00:55:35 -0600[diff] [blame]132};
133
134#endif