blob: 15e0b7ffd2369c6a77c1013a3264e4a9e8bc2c0a [file] [log] [blame]
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001/* Copyright (c) 2009-2011, Code Aurora Forum. All rights reserved.
Daniel Walker8d747cd2010-02-25 11:37:43 -08002 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 *
Daniel Walker8d747cd2010-02-25 11:37:43 -080012 */
13
14#include <linux/kernel.h>
15#include <linux/irq.h>
16#include <linux/gpio.h>
17#include <linux/platform_device.h>
18#include <linux/delay.h>
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070019#include <linux/bootmem.h>
Daniel Walker8d747cd2010-02-25 11:37:43 -080020#include <linux/io.h>
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070021#ifdef CONFIG_SPI_QSD
22#include <linux/spi/spi.h>
23#endif
24#include <linux/mfd/pmic8058.h>
25#include <linux/mfd/marimba.h>
26#include <linux/i2c.h>
27#include <linux/input.h>
Daniel Walker8d747cd2010-02-25 11:37:43 -080028#include <linux/smsc911x.h>
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070029#include <linux/ofn_atlab.h>
30#include <linux/power_supply.h>
31#include <linux/input/pmic8058-keypad.h>
32#include <linux/i2c/isa1200.h>
33#include <linux/pwm.h>
34#include <linux/pmic8058-pwm.h>
35#include <linux/i2c/tsc2007.h>
36#include <linux/input/kp_flip_switch.h>
37#include <linux/leds-pmic8058.h>
38#include <linux/input/cy8c_ts.h>
39#include <linux/msm_adc.h>
40#include <linux/dma-mapping.h>
Daniel Walker8d747cd2010-02-25 11:37:43 -080041
42#include <asm/mach-types.h>
43#include <asm/mach/arch.h>
44#include <asm/setup.h>
45
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070046#include <mach/mpp.h>
Daniel Walker8d747cd2010-02-25 11:37:43 -080047#include <mach/board.h>
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070048#include <mach/camera.h>
49#include <mach/memory.h>
Daniel Walker8d747cd2010-02-25 11:37:43 -080050#include <mach/msm_iomap.h>
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070051#include <mach/msm_hsusb.h>
52#include <mach/rpc_hsusb.h>
53#include <mach/msm_spi.h>
54#include <mach/qdsp5v2/msm_lpa.h>
Daniel Walker8d747cd2010-02-25 11:37:43 -080055#include <mach/dma.h>
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070056#include <linux/android_pmem.h>
57#include <linux/input/msm_ts.h>
58#include <mach/pmic.h>
59#include <mach/rpc_pmapp.h>
60#include <mach/qdsp5v2/aux_pcm.h>
61#include <mach/qdsp5v2/mi2s.h>
62#include <mach/qdsp5v2/audio_dev_ctl.h>
63#include <mach/msm_battery.h>
64#include <mach/rpc_server_handset.h>
65#include <mach/msm_tsif.h>
66#include <mach/socinfo.h>
67#include <mach/msm_memtypes.h>
68#include <linux/cyttsp.h>
Daniel Walker8d747cd2010-02-25 11:37:43 -080069
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070070#include <asm/mach/mmc.h>
71#include <asm/mach/flash.h>
Daniel Walker8d747cd2010-02-25 11:37:43 -080072#include <mach/vreg.h>
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070073#include <linux/platform_data/qcom_crypto_device.h>
74
Daniel Walker8d747cd2010-02-25 11:37:43 -080075#include "devices.h"
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070076#include "timer.h"
77#ifdef CONFIG_USB_G_ANDROID
78#include <linux/usb/android.h>
79#include <mach/usbdiag.h>
80#endif
81#include "pm.h"
82#include "spm.h"
83#include <mach/dal_axi.h>
84#include <mach/msm_serial_hs.h>
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070085#include <mach/qdsp5v2/mi2s.h>
86#include <mach/qdsp5v2/audio_dev_ctl.h>
87#include <mach/sdio_al.h>
88#include "smd_private.h"
89#include <linux/bma150.h>
Daniel Walker8d747cd2010-02-25 11:37:43 -080090
Justin Paupore637a25d2011-07-14 17:11:04 -070091#include "board-msm7x30-regulator.h"
92
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -070093#define MSM_PMEM_SF_SIZE 0x1700000
94#ifdef CONFIG_FB_MSM_TRIPLE_BUFFER
95#define MSM_FB_SIZE 0x780000
96#else
97#define MSM_FB_SIZE 0x500000
98#endif
99#define MSM_PMEM_ADSP_SIZE 0x1E00000
100#define MSM_FLUID_PMEM_ADSP_SIZE 0x2800000
101#define PMEM_KERNEL_EBI0_SIZE 0x600000
102#define MSM_PMEM_AUDIO_SIZE 0x200000
Daniel Walker90e37c52010-05-12 14:24:15 -0700103
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700104#define PMIC_GPIO_INT 27
105#define PMIC_VREG_WLAN_LEVEL 2900
106#define PMIC_GPIO_SD_DET 36
107#define PMIC_GPIO_SDC4_EN_N 17 /* PMIC GPIO Number 18 */
108#define PMIC_GPIO_HDMI_5V_EN_V3 32 /* PMIC GPIO for V3 H/W */
109#define PMIC_GPIO_HDMI_5V_EN_V2 39 /* PMIC GPIO for V2 H/W */
110
111#define ADV7520_I2C_ADDR 0x39
112
113#define FPGA_SDCC_STATUS 0x8E0001A8
114
115#define FPGA_OPTNAV_GPIO_ADDR 0x8E000026
116#define OPTNAV_I2C_SLAVE_ADDR (0xB0 >> 1)
117#define OPTNAV_IRQ 20
118#define OPTNAV_CHIP_SELECT 19
119
120/* Macros assume PMIC GPIOs start at 0 */
121#define PM8058_GPIO_PM_TO_SYS(pm_gpio) (pm_gpio + NR_GPIO_IRQS)
122#define PM8058_GPIO_SYS_TO_PM(sys_gpio) (sys_gpio - NR_GPIO_IRQS)
123
124#define PMIC_GPIO_FLASH_BOOST_ENABLE 15 /* PMIC GPIO Number 16 */
125#define PMIC_GPIO_HAP_ENABLE 16 /* PMIC GPIO Number 17 */
126
127#define PMIC_GPIO_WLAN_EXT_POR 22 /* PMIC GPIO NUMBER 23 */
128
129#define BMA150_GPIO_INT 1
130
131#define HAP_LVL_SHFT_MSM_GPIO 24
132
133#define PMIC_GPIO_QUICKVX_CLK 37 /* PMIC GPIO 38 */
134
135#define PM_FLIP_MPP 5 /* PMIC MPP 06 */
136static int pm8058_gpios_init(void)
137{
138 int rc;
139 int pmic_gpio_hdmi_5v_en;
140
141#ifdef CONFIG_MMC_MSM_CARD_HW_DETECTION
142 struct pm8058_gpio sdcc_det = {
143 .direction = PM_GPIO_DIR_IN,
144 .pull = PM_GPIO_PULL_UP_1P5,
145 .vin_sel = 2,
146 .function = PM_GPIO_FUNC_NORMAL,
147 .inv_int_pol = 0,
148 };
149#endif
150 struct pm8058_gpio sdc4_en = {
151 .direction = PM_GPIO_DIR_OUT,
152 .pull = PM_GPIO_PULL_NO,
153 .vin_sel = PM_GPIO_VIN_L5,
154 .function = PM_GPIO_FUNC_NORMAL,
155 .inv_int_pol = 0,
156 .out_strength = PM_GPIO_STRENGTH_LOW,
157 .output_value = 0,
158 };
159
160 struct pm8058_gpio haptics_enable = {
161 .direction = PM_GPIO_DIR_OUT,
162 .pull = PM_GPIO_PULL_NO,
163 .out_strength = PM_GPIO_STRENGTH_HIGH,
164 .function = PM_GPIO_FUNC_NORMAL,
165 .inv_int_pol = 0,
166 .vin_sel = 2,
167 .output_buffer = PM_GPIO_OUT_BUF_CMOS,
168 .output_value = 0,
169 };
170
171 struct pm8058_gpio hdmi_5V_en = {
172 .direction = PM_GPIO_DIR_OUT,
173 .pull = PM_GPIO_PULL_NO,
174 .vin_sel = PM_GPIO_VIN_VPH,
175 .function = PM_GPIO_FUNC_NORMAL,
176 .out_strength = PM_GPIO_STRENGTH_LOW,
177 .output_value = 0,
178 };
179
180 struct pm8058_gpio flash_boost_enable = {
181 .direction = PM_GPIO_DIR_OUT,
182 .output_buffer = PM_GPIO_OUT_BUF_CMOS,
183 .output_value = 0,
184 .pull = PM_GPIO_PULL_NO,
185 .vin_sel = PM_GPIO_VIN_S3,
186 .out_strength = PM_GPIO_STRENGTH_HIGH,
187 .function = PM_GPIO_FUNC_2,
188 };
189
190 struct pm8058_gpio gpio23 = {
191 .direction = PM_GPIO_DIR_OUT,
192 .output_buffer = PM_GPIO_OUT_BUF_CMOS,
193 .output_value = 0,
194 .pull = PM_GPIO_PULL_NO,
195 .vin_sel = 2,
196 .out_strength = PM_GPIO_STRENGTH_LOW,
197 .function = PM_GPIO_FUNC_NORMAL,
198 };
199
200
201 if (machine_is_msm8x55_svlte_surf() || machine_is_msm8x55_svlte_ffa() ||
202 machine_is_msm7x30_fluid())
203 pmic_gpio_hdmi_5v_en = PMIC_GPIO_HDMI_5V_EN_V2 ;
204 else
205 pmic_gpio_hdmi_5v_en = PMIC_GPIO_HDMI_5V_EN_V3 ;
206
207 if (machine_is_msm7x30_fluid()) {
208 rc = pm8058_gpio_config(PMIC_GPIO_HAP_ENABLE, &haptics_enable);
209 if (rc) {
210 pr_err("%s: PMIC GPIO %d write failed\n", __func__,
211 (PMIC_GPIO_HAP_ENABLE + 1));
212 return rc;
213 }
214 rc = pm8058_gpio_config(PMIC_GPIO_FLASH_BOOST_ENABLE,
215 &flash_boost_enable);
216 if (rc) {
217 pr_err("%s: PMIC GPIO %d write failed\n", __func__,
218 (PMIC_GPIO_FLASH_BOOST_ENABLE + 1));
219 return rc;
220 }
221 }
222
223#ifdef CONFIG_MMC_MSM_CARD_HW_DETECTION
224 if (machine_is_msm7x30_fluid())
225 sdcc_det.inv_int_pol = 1;
226
227 rc = pm8058_gpio_config(PMIC_GPIO_SD_DET - 1, &sdcc_det);
228 if (rc) {
229 pr_err("%s PMIC_GPIO_SD_DET config failed\n", __func__);
230 return rc;
231 }
232#endif
233
234 rc = pm8058_gpio_config(pmic_gpio_hdmi_5v_en, &hdmi_5V_en);
235 if (rc) {
236 pr_err("%s PMIC_GPIO_HDMI_5V_EN config failed\n", __func__);
237 return rc;
238 }
239
240 /* Deassert GPIO#23 (source for Ext_POR on WLAN-Volans) */
241 rc = pm8058_gpio_config(PMIC_GPIO_WLAN_EXT_POR, &gpio23);
242 if (rc) {
243 pr_err("%s PMIC_GPIO_WLAN_EXT_POR config failed\n", __func__);
244 return rc;
245 }
246
247 if (machine_is_msm7x30_fluid()) {
248 rc = pm8058_gpio_config(PMIC_GPIO_SDC4_EN_N, &sdc4_en);
249 if (rc) {
250 pr_err("%s PMIC_GPIO_SDC4_EN_N config failed\n",
251 __func__);
252 return rc;
253 }
254 rc = gpio_request(PM8058_GPIO_PM_TO_SYS(PMIC_GPIO_SDC4_EN_N),
255 "sdc4_en");
256 if (rc) {
257 pr_err("%s PMIC_GPIO_SDC4_EN_N gpio_request failed\n",
258 __func__);
259 return rc;
260 }
261 gpio_set_value_cansleep(
262 PM8058_GPIO_PM_TO_SYS(PMIC_GPIO_SDC4_EN_N), 0);
263 }
264
265 return 0;
266}
267
Justin Paupore637a25d2011-07-14 17:11:04 -0700268/* Regulator API support */
269
270#ifdef CONFIG_MSM_PROC_COMM_REGULATOR
271static struct platform_device msm_proccomm_regulator_dev = {
272 .name = PROCCOMM_REGULATOR_DEV_NAME,
273 .id = -1,
274 .dev = {
275 .platform_data = &msm7x30_proccomm_regulator_data
276 }
277};
278#endif
279
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700280/*virtual key support */
281static ssize_t tma300_vkeys_show(struct kobject *kobj,
282 struct kobj_attribute *attr, char *buf)
283{
284 return sprintf(buf,
285 __stringify(EV_KEY) ":" __stringify(KEY_BACK) ":50:842:80:100"
286 ":" __stringify(EV_KEY) ":" __stringify(KEY_MENU) ":170:842:80:100"
287 ":" __stringify(EV_KEY) ":" __stringify(KEY_HOME) ":290:842:80:100"
288 ":" __stringify(EV_KEY) ":" __stringify(KEY_SEARCH) ":410:842:80:100"
289 "\n");
290}
291
292static struct kobj_attribute tma300_vkeys_attr = {
293 .attr = {
294 .mode = S_IRUGO,
295 },
296 .show = &tma300_vkeys_show,
Pavankumar Kondeti5155e2c2010-12-08 13:37:08 +0530297};
298
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700299static struct attribute *tma300_properties_attrs[] = {
300 &tma300_vkeys_attr.attr,
301 NULL
Pavankumar Kondeti5155e2c2010-12-08 13:37:08 +0530302};
303
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700304static struct attribute_group tma300_properties_attr_group = {
305 .attrs = tma300_properties_attrs,
306};
307
308static struct kobject *properties_kobj;
309
310#define CYTTSP_TS_GPIO_IRQ 150
311static int cyttsp_platform_init(struct i2c_client *client)
312{
313 int rc = -EINVAL;
314 struct vreg *vreg_ldo8, *vreg_ldo15;
315
316 vreg_ldo8 = vreg_get(NULL, "gp7");
317
318 if (!vreg_ldo8) {
319 pr_err("%s: VREG L8 get failed\n", __func__);
320 return rc;
321 }
322
323 rc = vreg_set_level(vreg_ldo8, 1800);
324 if (rc) {
325 pr_err("%s: VREG L8 set failed\n", __func__);
326 goto l8_put;
327 }
328
329 rc = vreg_enable(vreg_ldo8);
330 if (rc) {
331 pr_err("%s: VREG L8 enable failed\n", __func__);
332 goto l8_put;
333 }
334
335 vreg_ldo15 = vreg_get(NULL, "gp6");
336
337 if (!vreg_ldo15) {
338 pr_err("%s: VREG L15 get failed\n", __func__);
339 goto l8_disable;
340 }
341
342 rc = vreg_set_level(vreg_ldo15, 3050);
343 if (rc) {
344 pr_err("%s: VREG L15 set failed\n", __func__);
345 goto l8_disable;
346 }
347
348 rc = vreg_enable(vreg_ldo15);
349 if (rc) {
350 pr_err("%s: VREG L15 enable failed\n", __func__);
351 goto l8_disable;
352 }
353
354 /* check this device active by reading first byte/register */
355 rc = i2c_smbus_read_byte_data(client, 0x01);
356 if (rc < 0) {
357 pr_err("%s: i2c sanity check failed\n", __func__);
358 goto l8_disable;
359 }
360
361 rc = gpio_tlmm_config(GPIO_CFG(CYTTSP_TS_GPIO_IRQ, 0, GPIO_CFG_INPUT,
362 GPIO_CFG_PULL_UP, GPIO_CFG_6MA), GPIO_CFG_ENABLE);
363 if (rc) {
364 pr_err("%s: Could not configure gpio %d\n",
365 __func__, CYTTSP_TS_GPIO_IRQ);
366 goto l8_disable;
367 }
368
369 /* virtual keys */
370 tma300_vkeys_attr.attr.name = "virtualkeys.cyttsp-i2c";
371 properties_kobj = kobject_create_and_add("board_properties",
372 NULL);
373 if (properties_kobj)
374 rc = sysfs_create_group(properties_kobj,
375 &tma300_properties_attr_group);
376 if (!properties_kobj || rc)
377 pr_err("%s: failed to create board_properties\n",
378 __func__);
379
380 return CY_OK;
381
382l8_disable:
383 vreg_disable(vreg_ldo8);
384l8_put:
385 vreg_put(vreg_ldo8);
386 return rc;
387}
388
389static int cyttsp_platform_resume(struct i2c_client *client)
390{
391 /* add any special code to strobe a wakeup pin or chip reset */
392 mdelay(10);
393
394 return CY_OK;
395}
396
397static struct cyttsp_platform_data cyttsp_data = {
398 .fw_fname = "cyttsp_7630_fluid.hex",
399 .panel_maxx = 479,
400 .panel_maxy = 799,
401 .disp_maxx = 469,
402 .disp_maxy = 799,
403 .disp_minx = 10,
404 .disp_miny = 0,
405 .flags = 0,
406 .gen = CY_GEN3, /* or */
407 .use_st = CY_USE_ST,
408 .use_mt = CY_USE_MT,
409 .use_hndshk = CY_SEND_HNDSHK,
410 .use_trk_id = CY_USE_TRACKING_ID,
Anirudh Ghayal15187772011-06-22 17:39:41 +0530411 .use_sleep = CY_USE_DEEP_SLEEP_SEL | CY_USE_LOW_POWER_SEL,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700412 .use_gestures = CY_USE_GESTURES,
413 /* activate up to 4 groups
414 * and set active distance
415 */
416 .gest_set = CY_GEST_GRP1 | CY_GEST_GRP2 |
417 CY_GEST_GRP3 | CY_GEST_GRP4 |
418 CY_ACT_DIST,
419 /* change act_intrvl to customize the Active power state
420 * scanning/processing refresh interval for Operating mode
421 */
422 .act_intrvl = CY_ACT_INTRVL_DFLT,
423 /* change tch_tmout to customize the touch timeout for the
424 * Active power state for Operating mode
425 */
426 .tch_tmout = CY_TCH_TMOUT_DFLT,
427 /* change lp_intrvl to customize the Low Power power state
428 * scanning/processing refresh interval for Operating mode
429 */
430 .lp_intrvl = CY_LP_INTRVL_DFLT,
431 .resume = cyttsp_platform_resume,
432 .init = cyttsp_platform_init,
433 .sleep_gpio = -1,
434 .resout_gpio = -1,
435 .irq_gpio = CYTTSP_TS_GPIO_IRQ,
Mohan Pallaka49c37d62011-08-01 11:52:00 +0530436 .correct_fw_ver = 2,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700437};
438
439static int pm8058_pwm_config(struct pwm_device *pwm, int ch, int on)
440{
441 struct pm8058_gpio pwm_gpio_config = {
442 .direction = PM_GPIO_DIR_OUT,
443 .output_buffer = PM_GPIO_OUT_BUF_CMOS,
444 .output_value = 0,
445 .pull = PM_GPIO_PULL_NO,
446 .vin_sel = PM_GPIO_VIN_S3,
447 .out_strength = PM_GPIO_STRENGTH_HIGH,
448 .function = PM_GPIO_FUNC_2,
449 };
450 int rc = -EINVAL;
451 int id, mode, max_mA;
452
453 id = mode = max_mA = 0;
454 switch (ch) {
455 case 0:
456 case 1:
457 case 2:
458 if (on) {
459 id = 24 + ch;
460 rc = pm8058_gpio_config(id - 1, &pwm_gpio_config);
461 if (rc)
462 pr_err("%s: pm8058_gpio_config(%d): rc=%d\n",
463 __func__, id, rc);
464 }
465 break;
466
467 case 3:
468 id = PM_PWM_LED_KPD;
469 mode = PM_PWM_CONF_DTEST3;
470 max_mA = 200;
471 break;
472
473 case 4:
474 id = PM_PWM_LED_0;
475 mode = PM_PWM_CONF_PWM1;
476 max_mA = 40;
477 break;
478
479 case 5:
480 id = PM_PWM_LED_2;
481 mode = PM_PWM_CONF_PWM2;
482 max_mA = 40;
483 break;
484
485 case 6:
486 id = PM_PWM_LED_FLASH;
487 mode = PM_PWM_CONF_DTEST3;
488 max_mA = 200;
489 break;
490
491 default:
492 break;
493 }
494
495 if (ch >= 3 && ch <= 6) {
496 if (!on) {
497 mode = PM_PWM_CONF_NONE;
498 max_mA = 0;
499 }
500 rc = pm8058_pwm_config_led(pwm, id, mode, max_mA);
501 if (rc)
502 pr_err("%s: pm8058_pwm_config_led(ch=%d): rc=%d\n",
503 __func__, ch, rc);
504 }
505
506 return rc;
507}
508
509static int pm8058_pwm_enable(struct pwm_device *pwm, int ch, int on)
510{
511 int rc;
512
513 switch (ch) {
514 case 7:
515 rc = pm8058_pwm_set_dtest(pwm, on);
516 if (rc)
517 pr_err("%s: pwm_set_dtest(%d): rc=%d\n",
518 __func__, on, rc);
519 break;
520 default:
521 rc = -EINVAL;
522 break;
523 }
524 return rc;
525}
526
527static const unsigned int fluid_keymap[] = {
528 KEY(0, 0, KEY_7),
529 KEY(0, 1, KEY_ENTER),
530 KEY(0, 2, KEY_UP),
531 /* drop (0,3) as it always shows up in pair with(0,2) */
532 KEY(0, 4, KEY_DOWN),
533
534 KEY(1, 0, KEY_CAMERA_SNAPSHOT),
535 KEY(1, 1, KEY_SELECT),
536 KEY(1, 2, KEY_1),
537 KEY(1, 3, KEY_VOLUMEUP),
538 KEY(1, 4, KEY_VOLUMEDOWN),
539};
540
541static const unsigned int surf_keymap[] = {
542 KEY(0, 0, KEY_7),
543 KEY(0, 1, KEY_DOWN),
544 KEY(0, 2, KEY_UP),
545 KEY(0, 3, KEY_RIGHT),
546 KEY(0, 4, KEY_ENTER),
547 KEY(0, 5, KEY_L),
548 KEY(0, 6, KEY_BACK),
549 KEY(0, 7, KEY_M),
550
551 KEY(1, 0, KEY_LEFT),
552 KEY(1, 1, KEY_SEND),
553 KEY(1, 2, KEY_1),
554 KEY(1, 3, KEY_4),
555 KEY(1, 4, KEY_CLEAR),
556 KEY(1, 5, KEY_MSDOS),
557 KEY(1, 6, KEY_SPACE),
558 KEY(1, 7, KEY_COMMA),
559
560 KEY(2, 0, KEY_6),
561 KEY(2, 1, KEY_5),
562 KEY(2, 2, KEY_8),
563 KEY(2, 3, KEY_3),
564 KEY(2, 4, KEY_NUMERIC_STAR),
565 KEY(2, 5, KEY_UP),
566 KEY(2, 6, KEY_DOWN), /* SYN */
567 KEY(2, 7, KEY_LEFTSHIFT),
568
569 KEY(3, 0, KEY_9),
570 KEY(3, 1, KEY_NUMERIC_POUND),
571 KEY(3, 2, KEY_0),
572 KEY(3, 3, KEY_2),
573 KEY(3, 4, KEY_SLEEP),
574 KEY(3, 5, KEY_F1),
575 KEY(3, 6, KEY_F2),
576 KEY(3, 7, KEY_F3),
577
578 KEY(4, 0, KEY_BACK),
579 KEY(4, 1, KEY_HOME),
580 KEY(4, 2, KEY_MENU),
581 KEY(4, 3, KEY_VOLUMEUP),
582 KEY(4, 4, KEY_VOLUMEDOWN),
583 KEY(4, 5, KEY_F4),
584 KEY(4, 6, KEY_F5),
585 KEY(4, 7, KEY_F6),
586
587 KEY(5, 0, KEY_R),
588 KEY(5, 1, KEY_T),
589 KEY(5, 2, KEY_Y),
590 KEY(5, 3, KEY_LEFTALT),
591 KEY(5, 4, KEY_KPENTER),
592 KEY(5, 5, KEY_Q),
593 KEY(5, 6, KEY_W),
594 KEY(5, 7, KEY_E),
595
596 KEY(6, 0, KEY_F),
597 KEY(6, 1, KEY_G),
598 KEY(6, 2, KEY_H),
599 KEY(6, 3, KEY_CAPSLOCK),
600 KEY(6, 4, KEY_PAGEUP),
601 KEY(6, 5, KEY_A),
602 KEY(6, 6, KEY_S),
603 KEY(6, 7, KEY_D),
604
605 KEY(7, 0, KEY_V),
606 KEY(7, 1, KEY_B),
607 KEY(7, 2, KEY_N),
608 KEY(7, 3, KEY_MENU), /* REVISIT - SYM */
609 KEY(7, 4, KEY_PAGEDOWN),
610 KEY(7, 5, KEY_Z),
611 KEY(7, 6, KEY_X),
612 KEY(7, 7, KEY_C),
613
614 KEY(8, 0, KEY_P),
615 KEY(8, 1, KEY_J),
616 KEY(8, 2, KEY_K),
617 KEY(8, 3, KEY_INSERT),
618 KEY(8, 4, KEY_LINEFEED),
619 KEY(8, 5, KEY_U),
620 KEY(8, 6, KEY_I),
621 KEY(8, 7, KEY_O),
622
623 KEY(9, 0, KEY_4),
624 KEY(9, 1, KEY_5),
625 KEY(9, 2, KEY_6),
626 KEY(9, 3, KEY_7),
627 KEY(9, 4, KEY_8),
628 KEY(9, 5, KEY_1),
629 KEY(9, 6, KEY_2),
630 KEY(9, 7, KEY_3),
631
632 KEY(10, 0, KEY_F7),
633 KEY(10, 1, KEY_F8),
634 KEY(10, 2, KEY_F9),
635 KEY(10, 3, KEY_F10),
636 KEY(10, 4, KEY_FN),
637 KEY(10, 5, KEY_9),
638 KEY(10, 6, KEY_0),
639 KEY(10, 7, KEY_DOT),
640
641 KEY(11, 0, KEY_LEFTCTRL),
642 KEY(11, 1, KEY_F11), /* START */
643 KEY(11, 2, KEY_ENTER),
644 KEY(11, 3, KEY_SEARCH),
645 KEY(11, 4, KEY_DELETE),
646 KEY(11, 5, KEY_RIGHT),
647 KEY(11, 6, KEY_LEFT),
648 KEY(11, 7, KEY_RIGHTSHIFT),
649};
650
651static struct resource resources_keypad[] = {
652 {
653 .start = PM8058_KEYPAD_IRQ(PMIC8058_IRQ_BASE),
654 .end = PM8058_KEYPAD_IRQ(PMIC8058_IRQ_BASE),
655 .flags = IORESOURCE_IRQ,
Dima Zavinba5499e2011-01-10 11:00:30 -0800656 },
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700657 {
658 .start = PM8058_KEYSTUCK_IRQ(PMIC8058_IRQ_BASE),
659 .end = PM8058_KEYSTUCK_IRQ(PMIC8058_IRQ_BASE),
660 .flags = IORESOURCE_IRQ,
Dima Zavinba5499e2011-01-10 11:00:30 -0800661 },
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700662};
663
664static struct matrix_keymap_data surf_keymap_data = {
665 .keymap_size = ARRAY_SIZE(surf_keymap),
666 .keymap = surf_keymap,
667};
668
669
670static struct pmic8058_keypad_data surf_keypad_data = {
671 .input_name = "surf_keypad",
672 .input_phys_device = "surf_keypad/input0",
673 .num_rows = 12,
674 .num_cols = 8,
675 .rows_gpio_start = 8,
676 .cols_gpio_start = 0,
677 .debounce_ms = {8, 10},
678 .scan_delay_ms = 32,
679 .row_hold_ns = 91500,
680 .wakeup = 1,
681 .keymap_data = &surf_keymap_data,
682};
683
684static struct matrix_keymap_data fluid_keymap_data = {
685 .keymap_size = ARRAY_SIZE(fluid_keymap),
686 .keymap = fluid_keymap,
687};
688
689
690
691static struct pmic8058_keypad_data fluid_keypad_data = {
692 .input_name = "fluid-keypad",
693 .input_phys_device = "fluid-keypad/input0",
694 .num_rows = 5,
695 .num_cols = 5,
696 .rows_gpio_start = 8,
697 .cols_gpio_start = 0,
698 .debounce_ms = {8, 10},
699 .scan_delay_ms = 32,
700 .row_hold_ns = 91500,
701 .wakeup = 1,
702 .keymap_data = &fluid_keymap_data,
703};
704
705static struct pm8058_pwm_pdata pm8058_pwm_data = {
706 .config = pm8058_pwm_config,
707 .enable = pm8058_pwm_enable,
708};
709
710/* Put sub devices with fixed location first in sub_devices array */
711#define PM8058_SUBDEV_KPD 0
712#define PM8058_SUBDEV_LED 1
713
714static struct pm8058_gpio_platform_data pm8058_gpio_data = {
715 .gpio_base = PM8058_GPIO_PM_TO_SYS(0),
716 .irq_base = PM8058_GPIO_IRQ(PMIC8058_IRQ_BASE, 0),
717 .init = pm8058_gpios_init,
718};
719
720static struct pm8058_gpio_platform_data pm8058_mpp_data = {
721 .gpio_base = PM8058_GPIO_PM_TO_SYS(PM8058_GPIOS),
722 .irq_base = PM8058_MPP_IRQ(PMIC8058_IRQ_BASE, 0),
723};
724
725static struct pmic8058_led pmic8058_ffa_leds[] = {
726 [0] = {
727 .name = "keyboard-backlight",
728 .max_brightness = 15,
729 .id = PMIC8058_ID_LED_KB_LIGHT,
Dima Zavinba5499e2011-01-10 11:00:30 -0800730 },
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700731};
732
733static struct pmic8058_leds_platform_data pm8058_ffa_leds_data = {
734 .num_leds = ARRAY_SIZE(pmic8058_ffa_leds),
735 .leds = pmic8058_ffa_leds,
736};
737
738static struct pmic8058_led pmic8058_surf_leds[] = {
739 [0] = {
740 .name = "keyboard-backlight",
741 .max_brightness = 15,
742 .id = PMIC8058_ID_LED_KB_LIGHT,
743 },
744 [1] = {
745 .name = "voice:red",
746 .max_brightness = 20,
747 .id = PMIC8058_ID_LED_0,
748 },
749 [2] = {
750 .name = "wlan:green",
751 .max_brightness = 20,
752 .id = PMIC8058_ID_LED_2,
753 },
754};
755
756static struct mfd_cell pm8058_subdevs[] = {
757 { .name = "pm8058-keypad",
758 .id = -1,
759 .num_resources = ARRAY_SIZE(resources_keypad),
760 .resources = resources_keypad,
761 },
762 { .name = "pm8058-led",
763 .id = -1,
764 },
765 { .name = "pm8058-gpio",
766 .id = -1,
767 .platform_data = &pm8058_gpio_data,
768 .pdata_size = sizeof(pm8058_gpio_data),
769 },
770 { .name = "pm8058-mpp",
771 .id = -1,
772 .platform_data = &pm8058_mpp_data,
773 .pdata_size = sizeof(pm8058_mpp_data),
774 },
775 { .name = "pm8058-pwm",
776 .id = -1,
777 .platform_data = &pm8058_pwm_data,
778 .pdata_size = sizeof(pm8058_pwm_data),
779 },
780 { .name = "pm8058-nfc",
781 .id = -1,
782 },
783 { .name = "pm8058-upl",
784 .id = -1,
785 },
786};
787
788static struct pmic8058_leds_platform_data pm8058_surf_leds_data = {
789 .num_leds = ARRAY_SIZE(pmic8058_surf_leds),
790 .leds = pmic8058_surf_leds,
791};
792
793static struct pmic8058_led pmic8058_fluid_leds[] = {
794 [0] = {
795 .name = "keyboard-backlight",
796 .max_brightness = 15,
797 .id = PMIC8058_ID_LED_KB_LIGHT,
798 },
799 [1] = {
800 .name = "flash:led_0",
801 .max_brightness = 15,
802 .id = PMIC8058_ID_FLASH_LED_0,
803 },
804 [2] = {
805 .name = "flash:led_1",
806 .max_brightness = 15,
807 .id = PMIC8058_ID_FLASH_LED_1,
808 },
809};
810
811static struct pmic8058_leds_platform_data pm8058_fluid_leds_data = {
812 .num_leds = ARRAY_SIZE(pmic8058_fluid_leds),
813 .leds = pmic8058_fluid_leds,
814};
815
816static struct pm8058_platform_data pm8058_7x30_data = {
817 .irq_base = PMIC8058_IRQ_BASE,
818
819 .num_subdevs = ARRAY_SIZE(pm8058_subdevs),
820 .sub_devices = pm8058_subdevs,
821 .irq_trigger_flags = IRQF_TRIGGER_LOW,
822};
823
824static struct i2c_board_info pm8058_boardinfo[] __initdata = {
825 {
826 I2C_BOARD_INFO("pm8058-core", 0x55),
827 .irq = MSM_GPIO_TO_INT(PMIC_GPIO_INT),
828 .platform_data = &pm8058_7x30_data,
829 },
830};
831
832static struct i2c_board_info cy8info[] __initdata = {
833 {
834 I2C_BOARD_INFO(CY_I2C_NAME, 0x24),
835 .platform_data = &cyttsp_data,
836#ifndef CY_USE_TIMER
837 .irq = MSM_GPIO_TO_INT(CYTTSP_TS_GPIO_IRQ),
838#endif /* CY_USE_TIMER */
839 },
840};
841
842static struct i2c_board_info msm_camera_boardinfo[] __initdata = {
843#ifdef CONFIG_MT9D112
844 {
845 I2C_BOARD_INFO("mt9d112", 0x78 >> 1),
Dima Zavinba5499e2011-01-10 11:00:30 -0800846 },
847#endif
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700848#ifdef CONFIG_WEBCAM_OV9726
849 {
850 I2C_BOARD_INFO("ov9726", 0x10),
851 },
852#endif
853#ifdef CONFIG_S5K3E2FX
854 {
855 I2C_BOARD_INFO("s5k3e2fx", 0x20 >> 1),
856 },
857#endif
858#ifdef CONFIG_MT9P012
859 {
860 I2C_BOARD_INFO("mt9p012", 0x6C >> 1),
861 },
862#endif
863#ifdef CONFIG_VX6953
864 {
865 I2C_BOARD_INFO("vx6953", 0x20),
866 },
867#endif
868#ifdef CONFIG_MT9E013
869 {
870 I2C_BOARD_INFO("mt9e013", 0x6C >> 2),
871 },
872#endif
873#ifdef CONFIG_SN12M0PZ
874 {
875 I2C_BOARD_INFO("sn12m0pz", 0x34 >> 1),
876 },
877#endif
878#if defined(CONFIG_MT9T013) || defined(CONFIG_SENSORS_MT9T013)
879 {
880 I2C_BOARD_INFO("mt9t013", 0x6C),
881 },
882#endif
883
Dima Zavinba5499e2011-01-10 11:00:30 -0800884};
885
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -0700886#ifdef CONFIG_MSM_CAMERA
887#define CAM_STNDBY 143
888static uint32_t camera_off_vcm_gpio_table[] = {
889GPIO_CFG(1, 0, GPIO_CFG_OUTPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA), /* VCM */
890};
891
892static uint32_t camera_off_gpio_table[] = {
893 /* parallel CAMERA interfaces */
894 GPIO_CFG(0, 0, GPIO_CFG_OUTPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA), /* RST */
895 GPIO_CFG(2, 0, GPIO_CFG_INPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA), /* DAT2 */
896 GPIO_CFG(3, 0, GPIO_CFG_INPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA), /* DAT3 */
897 GPIO_CFG(4, 0, GPIO_CFG_INPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA), /* DAT4 */
898 GPIO_CFG(5, 0, GPIO_CFG_INPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA), /* DAT5 */
899 GPIO_CFG(6, 0, GPIO_CFG_INPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA), /* DAT6 */
900 GPIO_CFG(7, 0, GPIO_CFG_INPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA), /* DAT7 */
901 GPIO_CFG(8, 0, GPIO_CFG_INPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA), /* DAT8 */
902 GPIO_CFG(9, 0, GPIO_CFG_INPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA), /* DAT9 */
903 GPIO_CFG(10, 0, GPIO_CFG_INPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA), /* DAT10 */
904 GPIO_CFG(11, 0, GPIO_CFG_INPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA), /* DAT11 */
905 GPIO_CFG(12, 0, GPIO_CFG_INPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA), /* PCLK */
906 GPIO_CFG(13, 0, GPIO_CFG_INPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA), /* HSYNC_IN */
907 GPIO_CFG(14, 0, GPIO_CFG_INPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA), /* VSYNC_IN */
908 GPIO_CFG(15, 0, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), /* MCLK */
909};
910
911static uint32_t camera_on_vcm_gpio_table[] = {
912GPIO_CFG(1, 0, GPIO_CFG_OUTPUT, GPIO_CFG_PULL_UP, GPIO_CFG_2MA), /* VCM */
913};
914
915static uint32_t camera_on_gpio_table[] = {
916 /* parallel CAMERA interfaces */
917 GPIO_CFG(0, 0, GPIO_CFG_OUTPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA), /* RST */
918 GPIO_CFG(2, 1, GPIO_CFG_INPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA), /* DAT2 */
919 GPIO_CFG(3, 1, GPIO_CFG_INPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA), /* DAT3 */
920 GPIO_CFG(4, 1, GPIO_CFG_INPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA), /* DAT4 */
921 GPIO_CFG(5, 1, GPIO_CFG_INPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA), /* DAT5 */
922 GPIO_CFG(6, 1, GPIO_CFG_INPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA), /* DAT6 */
923 GPIO_CFG(7, 1, GPIO_CFG_INPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA), /* DAT7 */
924 GPIO_CFG(8, 1, GPIO_CFG_INPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA), /* DAT8 */
925 GPIO_CFG(9, 1, GPIO_CFG_INPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA), /* DAT9 */
926 GPIO_CFG(10, 1, GPIO_CFG_INPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA), /* DAT10 */
927 GPIO_CFG(11, 1, GPIO_CFG_INPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA), /* DAT11 */
928 GPIO_CFG(12, 1, GPIO_CFG_INPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA), /* PCLK */
929 GPIO_CFG(13, 1, GPIO_CFG_INPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA), /* HSYNC_IN */
930 GPIO_CFG(14, 1, GPIO_CFG_INPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA), /* VSYNC_IN */
931 GPIO_CFG(15, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), /* MCLK */
932};
933
934static uint32_t camera_off_gpio_fluid_table[] = {
935 /* FLUID: CAM_VGA_RST_N */
936 GPIO_CFG(31, 0, GPIO_CFG_OUTPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA),
937 /* FLUID: CAMIF_STANDBY */
938 GPIO_CFG(CAM_STNDBY, 0, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA)
939};
940
941static uint32_t camera_on_gpio_fluid_table[] = {
942 /* FLUID: CAM_VGA_RST_N */
943 GPIO_CFG(31, 0, GPIO_CFG_OUTPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA),
944 /* FLUID: CAMIF_STANDBY */
945 GPIO_CFG(CAM_STNDBY, 0, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA)
946};
947
948static void config_gpio_table(uint32_t *table, int len)
949{
950 int n, rc;
951 for (n = 0; n < len; n++) {
952 rc = gpio_tlmm_config(table[n], GPIO_CFG_ENABLE);
953 if (rc) {
954 pr_err("%s: gpio_tlmm_config(%#x)=%d\n",
955 __func__, table[n], rc);
956 break;
957 }
958 }
959}
960static int config_camera_on_gpios(void)
961{
962 config_gpio_table(camera_on_gpio_table,
963 ARRAY_SIZE(camera_on_gpio_table));
964
965 if (adie_get_detected_codec_type() != TIMPANI_ID)
966 /* GPIO1 is shared also used in Timpani RF card so
967 only configure it for non-Timpani RF card */
968 config_gpio_table(camera_on_vcm_gpio_table,
969 ARRAY_SIZE(camera_on_vcm_gpio_table));
970
971 if (machine_is_msm7x30_fluid()) {
972 config_gpio_table(camera_on_gpio_fluid_table,
973 ARRAY_SIZE(camera_on_gpio_fluid_table));
974 /* FLUID: turn on 5V booster */
975 gpio_set_value(
976 PM8058_GPIO_PM_TO_SYS(PMIC_GPIO_FLASH_BOOST_ENABLE), 1);
977 /* FLUID: drive high to put secondary sensor to STANDBY */
978 gpio_set_value(CAM_STNDBY, 1);
979 }
980 return 0;
981}
982
983static void config_camera_off_gpios(void)
984{
985 config_gpio_table(camera_off_gpio_table,
986 ARRAY_SIZE(camera_off_gpio_table));
987
988 if (adie_get_detected_codec_type() != TIMPANI_ID)
989 /* GPIO1 is shared also used in Timpani RF card so
990 only configure it for non-Timpani RF card */
991 config_gpio_table(camera_off_vcm_gpio_table,
992 ARRAY_SIZE(camera_off_vcm_gpio_table));
993
994 if (machine_is_msm7x30_fluid()) {
995 config_gpio_table(camera_off_gpio_fluid_table,
996 ARRAY_SIZE(camera_off_gpio_fluid_table));
997 /* FLUID: turn off 5V booster */
998 gpio_set_value(
999 PM8058_GPIO_PM_TO_SYS(PMIC_GPIO_FLASH_BOOST_ENABLE), 0);
1000 }
1001}
1002
1003struct resource msm_camera_resources[] = {
1004 {
1005 .start = 0xA6000000,
1006 .end = 0xA6000000 + SZ_1M - 1,
1007 .flags = IORESOURCE_MEM,
1008 },
1009 {
1010 .start = INT_VFE,
1011 .end = INT_VFE,
1012 .flags = IORESOURCE_IRQ,
1013 },
1014 {
1015 .flags = IORESOURCE_DMA,
1016 }
1017};
1018
1019struct msm_camera_device_platform_data msm_camera_device_data = {
1020 .camera_gpio_on = config_camera_on_gpios,
1021 .camera_gpio_off = config_camera_off_gpios,
1022 .ioext.camifpadphy = 0xAB000000,
1023 .ioext.camifpadsz = 0x00000400,
1024 .ioext.csiphy = 0xA6100000,
1025 .ioext.csisz = 0x00000400,
1026 .ioext.csiirq = INT_CSI,
1027 .ioclk.mclk_clk_rate = 24000000,
1028 .ioclk.vfe_clk_rate = 147456000,
1029};
1030
1031static struct msm_camera_sensor_flash_src msm_flash_src_pwm = {
1032 .flash_sr_type = MSM_CAMERA_FLASH_SRC_PWM,
1033 ._fsrc.pwm_src.freq = 1000,
1034 ._fsrc.pwm_src.max_load = 300,
1035 ._fsrc.pwm_src.low_load = 30,
1036 ._fsrc.pwm_src.high_load = 100,
1037 ._fsrc.pwm_src.channel = 7,
1038};
1039
1040#ifdef CONFIG_MT9D112
1041static struct msm_camera_sensor_flash_data flash_mt9d112 = {
1042 .flash_type = MSM_CAMERA_FLASH_LED,
1043 .flash_src = &msm_flash_src_pwm
1044};
1045
1046static struct msm_camera_sensor_info msm_camera_sensor_mt9d112_data = {
1047 .sensor_name = "mt9d112",
1048 .sensor_reset = 0,
1049 .sensor_pwd = 85,
1050 .vcm_pwd = 1,
1051 .vcm_enable = 0,
1052 .pdata = &msm_camera_device_data,
1053 .resource = msm_camera_resources,
1054 .num_resources = ARRAY_SIZE(msm_camera_resources),
1055 .flash_data = &flash_mt9d112,
1056 .csi_if = 0
1057};
1058
1059static struct platform_device msm_camera_sensor_mt9d112 = {
1060 .name = "msm_camera_mt9d112",
1061 .dev = {
1062 .platform_data = &msm_camera_sensor_mt9d112_data,
1063 },
1064};
1065#endif
1066
1067#ifdef CONFIG_WEBCAM_OV9726
1068
1069static struct msm_camera_sensor_platform_info ov9726_sensor_7630_info = {
1070 .mount_angle = 90
1071};
1072
1073static struct msm_camera_sensor_flash_data flash_ov9726 = {
1074 .flash_type = MSM_CAMERA_FLASH_LED,
1075 .flash_src = &msm_flash_src_pwm
1076};
1077static struct msm_camera_sensor_info msm_camera_sensor_ov9726_data = {
1078 .sensor_name = "ov9726",
1079 .sensor_reset = 0,
1080 .sensor_pwd = 85,
1081 .vcm_pwd = 1,
1082 .vcm_enable = 0,
1083 .pdata = &msm_camera_device_data,
1084 .resource = msm_camera_resources,
1085 .num_resources = ARRAY_SIZE(msm_camera_resources),
1086 .flash_data = &flash_ov9726,
1087 .sensor_platform_info = &ov9726_sensor_7630_info,
1088 .csi_if = 1
1089};
1090struct platform_device msm_camera_sensor_ov9726 = {
1091 .name = "msm_camera_ov9726",
1092 .dev = {
1093 .platform_data = &msm_camera_sensor_ov9726_data,
1094 },
1095};
1096#endif
1097
1098#ifdef CONFIG_S5K3E2FX
1099static struct msm_camera_sensor_flash_data flash_s5k3e2fx = {
1100 .flash_type = MSM_CAMERA_FLASH_LED,
1101 .flash_src = &msm_flash_src_pwm,
1102};
1103
1104static struct msm_camera_sensor_info msm_camera_sensor_s5k3e2fx_data = {
1105 .sensor_name = "s5k3e2fx",
1106 .sensor_reset = 0,
1107 .sensor_pwd = 85,
1108 .vcm_pwd = 1,
1109 .vcm_enable = 0,
1110 .pdata = &msm_camera_device_data,
1111 .resource = msm_camera_resources,
1112 .num_resources = ARRAY_SIZE(msm_camera_resources),
1113 .flash_data = &flash_s5k3e2fx,
1114 .csi_if = 0
1115};
1116
1117static struct platform_device msm_camera_sensor_s5k3e2fx = {
1118 .name = "msm_camera_s5k3e2fx",
1119 .dev = {
1120 .platform_data = &msm_camera_sensor_s5k3e2fx_data,
1121 },
1122};
1123#endif
1124
1125#ifdef CONFIG_MT9P012
1126static struct msm_camera_sensor_flash_data flash_mt9p012 = {
1127 .flash_type = MSM_CAMERA_FLASH_LED,
1128 .flash_src = &msm_flash_src_pwm
1129};
1130
1131static struct msm_camera_sensor_info msm_camera_sensor_mt9p012_data = {
1132 .sensor_name = "mt9p012",
1133 .sensor_reset = 0,
1134 .sensor_pwd = 85,
1135 .vcm_pwd = 1,
1136 .vcm_enable = 1,
1137 .pdata = &msm_camera_device_data,
1138 .resource = msm_camera_resources,
1139 .num_resources = ARRAY_SIZE(msm_camera_resources),
1140 .flash_data = &flash_mt9p012,
1141 .csi_if = 0
1142};
1143
1144static struct platform_device msm_camera_sensor_mt9p012 = {
1145 .name = "msm_camera_mt9p012",
1146 .dev = {
1147 .platform_data = &msm_camera_sensor_mt9p012_data,
1148 },
1149};
1150#endif
1151
1152#ifdef CONFIG_MT9E013
1153static struct msm_camera_sensor_platform_info mt9e013_sensor_7630_info = {
1154 .mount_angle = 0
1155};
1156
1157static struct msm_camera_sensor_flash_data flash_mt9e013 = {
1158 .flash_type = MSM_CAMERA_FLASH_LED,
1159 .flash_src = &msm_flash_src_pwm
1160};
1161
1162static struct msm_camera_sensor_info msm_camera_sensor_mt9e013_data = {
1163 .sensor_name = "mt9e013",
1164 .sensor_reset = 0,
1165 .sensor_pwd = 85,
1166 .vcm_pwd = 1,
1167 .vcm_enable = 1,
1168 .pdata = &msm_camera_device_data,
1169 .resource = msm_camera_resources,
1170 .num_resources = ARRAY_SIZE(msm_camera_resources),
1171 .flash_data = &flash_mt9e013,
1172 .sensor_platform_info = &mt9e013_sensor_7630_info,
1173 .csi_if = 1
1174};
1175
1176static struct platform_device msm_camera_sensor_mt9e013 = {
1177 .name = "msm_camera_mt9e013",
1178 .dev = {
1179 .platform_data = &msm_camera_sensor_mt9e013_data,
1180 },
1181};
1182#endif
1183
1184#ifdef CONFIG_VX6953
Jilai Wang971f97f2011-07-13 14:25:25 -04001185static struct msm_camera_sensor_platform_info vx6953_sensor_7630_info = {
1186 .mount_angle = 0
1187};
1188
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001189static struct msm_camera_sensor_flash_data flash_vx6953 = {
1190 .flash_type = MSM_CAMERA_FLASH_LED,
1191 .flash_src = &msm_flash_src_pwm
1192};
1193static struct msm_camera_sensor_info msm_camera_sensor_vx6953_data = {
1194 .sensor_name = "vx6953",
1195 .sensor_reset = 0,
1196 .sensor_pwd = 85,
1197 .vcm_pwd = 1,
1198 .vcm_enable = 0,
1199 .pdata = &msm_camera_device_data,
1200 .resource = msm_camera_resources,
1201 .num_resources = ARRAY_SIZE(msm_camera_resources),
Jilai Wang971f97f2011-07-13 14:25:25 -04001202 .sensor_platform_info = &vx6953_sensor_7630_info,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07001203 .flash_data = &flash_vx6953,
1204 .csi_if = 1
1205};
1206static struct platform_device msm_camera_sensor_vx6953 = {
1207 .name = "msm_camera_vx6953",
1208 .dev = {
1209 .platform_data = &msm_camera_sensor_vx6953_data,
1210 },
1211};
1212#endif
1213
1214#ifdef CONFIG_SN12M0PZ
1215static struct msm_camera_sensor_flash_src msm_flash_src_current_driver = {
1216 .flash_sr_type = MSM_CAMERA_FLASH_SRC_CURRENT_DRIVER,
1217 ._fsrc.current_driver_src.low_current = 210,
1218 ._fsrc.current_driver_src.high_current = 700,
1219 ._fsrc.current_driver_src.driver_channel = &pm8058_fluid_leds_data,
1220};
1221
1222static struct msm_camera_sensor_flash_data flash_sn12m0pz = {
1223 .flash_type = MSM_CAMERA_FLASH_LED,
1224 .flash_src = &msm_flash_src_current_driver
1225};
1226static struct msm_camera_sensor_info msm_camera_sensor_sn12m0pz_data = {
1227 .sensor_name = "sn12m0pz",
1228 .sensor_reset = 0,
1229 .sensor_pwd = 85,
1230 .vcm_pwd = 1,
1231 .vcm_enable = 1,
1232 .pdata = &msm_camera_device_data,
1233 .flash_data = &flash_sn12m0pz,
1234 .resource = msm_camera_resources,
1235 .num_resources = ARRAY_SIZE(msm_camera_resources),
1236 .csi_if = 0
1237};
1238
1239static struct platform_device msm_camera_sensor_sn12m0pz = {
1240 .name = "msm_camera_sn12m0pz",
1241 .dev = {
1242 .platform_data = &msm_camera_sensor_sn12m0pz_data,
1243 },
1244};
1245#endif
1246
1247#ifdef CONFIG_MT9T013
1248static struct msm_camera_sensor_flash_data flash_mt9t013 = {
1249 .flash_type = MSM_CAMERA_FLASH_LED,
1250 .flash_src = &msm_flash_src_pwm
1251};
1252
1253static struct msm_camera_sensor_info msm_camera_sensor_mt9t013_data = {
1254 .sensor_name = "mt9t013",
1255 .sensor_reset = 0,
1256 .sensor_pwd = 85,
1257 .vcm_pwd = 1,
1258 .vcm_enable = 0,
1259 .pdata = &msm_camera_device_data,
1260 .resource = msm_camera_resources,
1261 .num_resources = ARRAY_SIZE(msm_camera_resources),
1262 .flash_data = &flash_mt9t013,
1263 .csi_if = 1
1264};
1265
1266static struct platform_device msm_camera_sensor_mt9t013 = {
1267 .name = "msm_camera_mt9t013",
1268 .dev = {
1269 .platform_data = &msm_camera_sensor_mt9t013_data,
1270 },
1271};
1272#endif
1273
1274#ifdef CONFIG_MSM_GEMINI
1275static struct resource msm_gemini_resources[] = {
1276 {
1277 .start = 0xA3A00000,
1278 .end = 0xA3A00000 + 0x0150 - 1,
1279 .flags = IORESOURCE_MEM,
1280 },
1281 {
1282 .start = INT_JPEG,
1283 .end = INT_JPEG,
1284 .flags = IORESOURCE_IRQ,
1285 },
1286};
1287
1288static struct platform_device msm_gemini_device = {
1289 .name = "msm_gemini",
1290 .resource = msm_gemini_resources,
1291 .num_resources = ARRAY_SIZE(msm_gemini_resources),
1292};
1293#endif
1294
1295#ifdef CONFIG_MSM_VPE
1296static struct resource msm_vpe_resources[] = {
1297 {
1298 .start = 0xAD200000,
1299 .end = 0xAD200000 + SZ_1M - 1,
1300 .flags = IORESOURCE_MEM,
1301 },
1302 {
1303 .start = INT_VPE,
1304 .end = INT_VPE,
1305 .flags = IORESOURCE_IRQ,
1306 },
1307};
1308
1309static struct platform_device msm_vpe_device = {
1310 .name = "msm_vpe",
1311 .id = 0,
1312 .num_resources = ARRAY_SIZE(msm_vpe_resources),
1313 .resource = msm_vpe_resources,
1314};
1315#endif
1316
1317#endif /*CONFIG_MSM_CAMERA*/
1318
1319#ifdef CONFIG_MSM7KV2_AUDIO
1320static uint32_t audio_pamp_gpio_config =
1321 GPIO_CFG(82, 0, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA);
1322
1323static uint32_t audio_fluid_icodec_tx_config =
1324 GPIO_CFG(85, 0, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA);
1325
1326static int __init snddev_poweramp_gpio_init(void)
1327{
1328 int rc;
1329
1330 pr_info("snddev_poweramp_gpio_init \n");
1331 rc = gpio_tlmm_config(audio_pamp_gpio_config, GPIO_CFG_ENABLE);
1332 if (rc) {
1333 printk(KERN_ERR
1334 "%s: gpio_tlmm_config(%#x)=%d\n",
1335 __func__, audio_pamp_gpio_config, rc);
1336 }
1337 return rc;
1338}
1339
1340void msm_snddev_tx_route_config(void)
1341{
1342 int rc;
1343
1344 pr_debug("%s()\n", __func__);
1345
1346 if (machine_is_msm7x30_fluid()) {
1347 rc = gpio_tlmm_config(audio_fluid_icodec_tx_config,
1348 GPIO_CFG_ENABLE);
1349 if (rc) {
1350 printk(KERN_ERR
1351 "%s: gpio_tlmm_config(%#x)=%d\n",
1352 __func__, audio_fluid_icodec_tx_config, rc);
1353 } else
1354 gpio_set_value(85, 0);
1355 }
1356}
1357
1358void msm_snddev_tx_route_deconfig(void)
1359{
1360 int rc;
1361
1362 pr_debug("%s()\n", __func__);
1363
1364 if (machine_is_msm7x30_fluid()) {
1365 rc = gpio_tlmm_config(audio_fluid_icodec_tx_config,
1366 GPIO_CFG_DISABLE);
1367 if (rc) {
1368 printk(KERN_ERR
1369 "%s: gpio_tlmm_config(%#x)=%d\n",
1370 __func__, audio_fluid_icodec_tx_config, rc);
1371 }
1372 }
1373}
1374
1375void msm_snddev_poweramp_on(void)
1376{
1377 gpio_set_value(82, 1); /* enable spkr poweramp */
1378 pr_info("%s: power on amplifier\n", __func__);
1379}
1380
1381void msm_snddev_poweramp_off(void)
1382{
1383 gpio_set_value(82, 0); /* disable spkr poweramp */
1384 pr_info("%s: power off amplifier\n", __func__);
1385}
1386
1387static struct vreg *snddev_vreg_ncp, *snddev_vreg_gp4;
1388
1389void msm_snddev_hsed_voltage_on(void)
1390{
1391 int rc;
1392
1393 snddev_vreg_gp4 = vreg_get(NULL, "gp4");
1394 if (IS_ERR(snddev_vreg_gp4)) {
1395 pr_err("%s: vreg_get(%s) failed (%ld)\n",
1396 __func__, "gp4", PTR_ERR(snddev_vreg_gp4));
1397 return;
1398 }
1399 rc = vreg_enable(snddev_vreg_gp4);
1400 if (rc)
1401 pr_err("%s: vreg_enable(gp4) failed (%d)\n", __func__, rc);
1402
1403 snddev_vreg_ncp = vreg_get(NULL, "ncp");
1404 if (IS_ERR(snddev_vreg_ncp)) {
1405 pr_err("%s: vreg_get(%s) failed (%ld)\n",
1406 __func__, "ncp", PTR_ERR(snddev_vreg_ncp));
1407 return;
1408 }
1409 rc = vreg_enable(snddev_vreg_ncp);
1410 if (rc)
1411 pr_err("%s: vreg_enable(ncp) failed (%d)\n", __func__, rc);
1412}
1413
1414void msm_snddev_hsed_voltage_off(void)
1415{
1416 int rc;
1417
1418 if (IS_ERR(snddev_vreg_ncp)) {
1419 pr_err("%s: vreg_get(%s) failed (%ld)\n",
1420 __func__, "ncp", PTR_ERR(snddev_vreg_ncp));
1421 return;
1422 }
1423 rc = vreg_disable(snddev_vreg_ncp);
1424 if (rc)
1425 pr_err("%s: vreg_disable(ncp) failed (%d)\n", __func__, rc);
1426 vreg_put(snddev_vreg_ncp);
1427
1428 if (IS_ERR(snddev_vreg_gp4)) {
1429 pr_err("%s: vreg_get(%s) failed (%ld)\n",
1430 __func__, "gp4", PTR_ERR(snddev_vreg_gp4));
1431 return;
1432 }
1433 rc = vreg_disable(snddev_vreg_gp4);
1434 if (rc)
1435 pr_err("%s: vreg_disable(gp4) failed (%d)\n", __func__, rc);
1436
1437 vreg_put(snddev_vreg_gp4);
1438
1439}
1440
1441static unsigned aux_pcm_gpio_on[] = {
1442 GPIO_CFG(138, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), /* PCM_DOUT */
1443 GPIO_CFG(139, 1, GPIO_CFG_INPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), /* PCM_DIN */
1444 GPIO_CFG(140, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), /* PCM_SYNC */
1445 GPIO_CFG(141, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), /* PCM_CLK */
1446};
1447
1448static int __init aux_pcm_gpio_init(void)
1449{
1450 int pin, rc;
1451
1452 pr_info("aux_pcm_gpio_init \n");
1453 for (pin = 0; pin < ARRAY_SIZE(aux_pcm_gpio_on); pin++) {
1454 rc = gpio_tlmm_config(aux_pcm_gpio_on[pin],
1455 GPIO_CFG_ENABLE);
1456 if (rc) {
1457 printk(KERN_ERR
1458 "%s: gpio_tlmm_config(%#x)=%d\n",
1459 __func__, aux_pcm_gpio_on[pin], rc);
1460 }
1461 }
1462 return rc;
1463}
1464
1465static struct msm_gpio mi2s_clk_gpios[] = {
1466 { GPIO_CFG(145, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA),
1467 "MI2S_SCLK"},
1468 { GPIO_CFG(144, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA),
1469 "MI2S_WS"},
1470 { GPIO_CFG(120, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA),
1471 "MI2S_MCLK_A"},
1472};
1473
1474static struct msm_gpio mi2s_rx_data_lines_gpios[] = {
1475 { GPIO_CFG(121, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA),
1476 "MI2S_DATA_SD0_A"},
1477 { GPIO_CFG(122, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA),
1478 "MI2S_DATA_SD1_A"},
1479 { GPIO_CFG(123, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA),
1480 "MI2S_DATA_SD2_A"},
1481 { GPIO_CFG(146, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA),
1482 "MI2S_DATA_SD3"},
1483};
1484
1485static struct msm_gpio mi2s_tx_data_lines_gpios[] = {
1486 { GPIO_CFG(146, 1, GPIO_CFG_INPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA),
1487 "MI2S_DATA_SD3"},
1488};
1489
1490int mi2s_config_clk_gpio(void)
1491{
1492 int rc = 0;
1493
1494 rc = msm_gpios_request_enable(mi2s_clk_gpios,
1495 ARRAY_SIZE(mi2s_clk_gpios));
1496 if (rc) {
1497 pr_err("%s: enable mi2s clk gpios failed\n",
1498 __func__);
1499 return rc;
1500 }
1501 return 0;
1502}
1503
1504int mi2s_unconfig_data_gpio(u32 direction, u8 sd_line_mask)
1505{
1506 int i, rc = 0;
1507 sd_line_mask &= MI2S_SD_LINE_MASK;
1508
1509 switch (direction) {
1510 case DIR_TX:
1511 msm_gpios_disable_free(mi2s_tx_data_lines_gpios, 1);
1512 break;
1513 case DIR_RX:
1514 i = 0;
1515 while (sd_line_mask) {
1516 if (sd_line_mask & 0x1)
1517 msm_gpios_disable_free(
1518 mi2s_rx_data_lines_gpios + i , 1);
1519 sd_line_mask = sd_line_mask >> 1;
1520 i++;
1521 }
1522 break;
1523 default:
1524 pr_err("%s: Invaild direction direction = %u\n",
1525 __func__, direction);
1526 rc = -EINVAL;
1527 break;
1528 }
1529 return rc;
1530}
1531
1532int mi2s_config_data_gpio(u32 direction, u8 sd_line_mask)
1533{
1534 int i , rc = 0;
1535 u8 sd_config_done_mask = 0;
1536
1537 sd_line_mask &= MI2S_SD_LINE_MASK;
1538
1539 switch (direction) {
1540 case DIR_TX:
1541 if ((sd_line_mask & MI2S_SD_0) || (sd_line_mask & MI2S_SD_1) ||
1542 (sd_line_mask & MI2S_SD_2) || !(sd_line_mask & MI2S_SD_3)) {
1543 pr_err("%s: can not use SD0 or SD1 or SD2 for TX"
1544 ".only can use SD3. sd_line_mask = 0x%x\n",
1545 __func__ , sd_line_mask);
1546 rc = -EINVAL;
1547 } else {
1548 rc = msm_gpios_request_enable(mi2s_tx_data_lines_gpios,
1549 1);
1550 if (rc)
1551 pr_err("%s: enable mi2s gpios for TX failed\n",
1552 __func__);
1553 }
1554 break;
1555 case DIR_RX:
1556 i = 0;
1557 while (sd_line_mask && (rc == 0)) {
1558 if (sd_line_mask & 0x1) {
1559 rc = msm_gpios_request_enable(
1560 mi2s_rx_data_lines_gpios + i , 1);
1561 if (rc) {
1562 pr_err("%s: enable mi2s gpios for"
1563 "RX failed. SD line = %s\n",
1564 __func__,
1565 (mi2s_rx_data_lines_gpios + i)->label);
1566 mi2s_unconfig_data_gpio(DIR_RX,
1567 sd_config_done_mask);
1568 } else
1569 sd_config_done_mask |= (1 << i);
1570 }
1571 sd_line_mask = sd_line_mask >> 1;
1572 i++;
1573 }
1574 break;
1575 default:
1576 pr_err("%s: Invaild direction direction = %u\n",
1577 __func__, direction);
1578 rc = -EINVAL;
1579 break;
1580 }
1581 return rc;
1582}
1583
1584int mi2s_unconfig_clk_gpio(void)
1585{
1586 msm_gpios_disable_free(mi2s_clk_gpios, ARRAY_SIZE(mi2s_clk_gpios));
1587 return 0;
1588}
1589
1590#endif /* CONFIG_MSM7KV2_AUDIO */
1591
1592static int __init buses_init(void)
1593{
1594 if (gpio_tlmm_config(GPIO_CFG(PMIC_GPIO_INT, 1, GPIO_CFG_INPUT,
1595 GPIO_CFG_NO_PULL, GPIO_CFG_2MA), GPIO_CFG_ENABLE))
1596 pr_err("%s: gpio_tlmm_config (gpio=%d) failed\n",
1597 __func__, PMIC_GPIO_INT);
1598
1599 if (machine_is_msm7x30_fluid()) {
1600 pm8058_7x30_data.sub_devices[PM8058_SUBDEV_KPD].platform_data
1601 = &fluid_keypad_data;
1602 } else {
1603 pm8058_7x30_data.sub_devices[PM8058_SUBDEV_KPD].platform_data
1604 = &surf_keypad_data;
1605 pm8058_7x30_data.sub_devices[PM8058_SUBDEV_KPD].pdata_size
1606 = sizeof(surf_keypad_data);
1607 }
1608
1609 i2c_register_board_info(6 /* I2C_SSBI ID */, pm8058_boardinfo,
1610 ARRAY_SIZE(pm8058_boardinfo));
1611
1612 return 0;
1613}
1614
1615#define TIMPANI_RESET_GPIO 1
1616
1617struct bahama_config_register{
1618 u8 reg;
1619 u8 value;
1620 u8 mask;
1621};
1622
1623enum version{
1624 VER_1_0,
1625 VER_2_0,
1626 VER_UNSUPPORTED = 0xFF
1627};
1628
1629
1630static struct vreg *vreg_marimba_1;
1631static struct vreg *vreg_marimba_2;
1632static struct vreg *vreg_marimba_3;
1633
1634static struct msm_gpio timpani_reset_gpio_cfg[] = {
1635{ GPIO_CFG(TIMPANI_RESET_GPIO, 0, GPIO_CFG_OUTPUT,
1636 GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "timpani_reset"} };
1637
1638static u8 read_bahama_ver(void)
1639{
1640 int rc;
1641 struct marimba config = { .mod_id = SLAVE_ID_BAHAMA };
1642 u8 bahama_version;
1643
1644 rc = marimba_read_bit_mask(&config, 0x00, &bahama_version, 1, 0x1F);
1645 if (rc < 0) {
1646 printk(KERN_ERR
1647 "%s: version read failed: %d\n",
1648 __func__, rc);
1649 return rc;
1650 } else {
1651 printk(KERN_INFO
1652 "%s: version read got: 0x%x\n",
1653 __func__, bahama_version);
1654 }
1655
1656 switch (bahama_version) {
1657 case 0x08: /* varient of bahama v1 */
1658 case 0x10:
1659 case 0x00:
1660 return VER_1_0;
1661 case 0x09: /* variant of bahama v2 */
1662 return VER_2_0;
1663 default:
1664 return VER_UNSUPPORTED;
1665 }
1666}
1667
1668static int config_timpani_reset(void)
1669{
1670 int rc;
1671
1672 rc = msm_gpios_request_enable(timpani_reset_gpio_cfg,
1673 ARRAY_SIZE(timpani_reset_gpio_cfg));
1674 if (rc < 0) {
1675 printk(KERN_ERR
1676 "%s: msm_gpios_request_enable failed (%d)\n",
1677 __func__, rc);
1678 }
1679 return rc;
1680}
1681
1682static unsigned int msm_timpani_setup_power(void)
1683{
1684 int rc;
1685
1686 rc = config_timpani_reset();
1687 if (rc < 0)
1688 goto out;
1689
1690 rc = vreg_enable(vreg_marimba_1);
1691 if (rc) {
1692 printk(KERN_ERR "%s: vreg_enable() = %d\n",
1693 __func__, rc);
1694 goto out;
1695 }
1696 rc = vreg_enable(vreg_marimba_2);
1697 if (rc) {
1698 printk(KERN_ERR "%s: vreg_enable() = %d\n",
1699 __func__, rc);
1700 goto fail_disable_vreg_marimba_1;
1701 }
1702
1703 rc = gpio_direction_output(TIMPANI_RESET_GPIO, 1);
1704 if (rc < 0) {
1705 printk(KERN_ERR
1706 "%s: gpio_direction_output failed (%d)\n",
1707 __func__, rc);
1708 msm_gpios_free(timpani_reset_gpio_cfg,
1709 ARRAY_SIZE(timpani_reset_gpio_cfg));
1710 vreg_disable(vreg_marimba_2);
1711 } else
1712 goto out;
1713
1714
1715fail_disable_vreg_marimba_1:
1716 vreg_disable(vreg_marimba_1);
1717
1718out:
1719 return rc;
1720};
1721
1722static void msm_timpani_shutdown_power(void)
1723{
1724 int rc;
1725
1726 rc = vreg_disable(vreg_marimba_1);
1727 if (rc) {
1728 printk(KERN_ERR "%s: return val: %d\n",
1729 __func__, rc);
1730 }
1731 rc = vreg_disable(vreg_marimba_2);
1732 if (rc) {
1733 printk(KERN_ERR "%s: return val: %d\n",
1734 __func__, rc);
1735 }
1736
1737 rc = gpio_direction_output(TIMPANI_RESET_GPIO, 0);
1738 if (rc < 0) {
1739 printk(KERN_ERR
1740 "%s: gpio_direction_output failed (%d)\n",
1741 __func__, rc);
1742 }
1743
1744 msm_gpios_free(timpani_reset_gpio_cfg,
1745 ARRAY_SIZE(timpani_reset_gpio_cfg));
1746};
1747
1748static unsigned int msm_bahama_core_config(int type)
1749{
1750 int rc = 0;
1751
1752 if (type == BAHAMA_ID) {
1753
1754 int i;
1755 struct marimba config = { .mod_id = SLAVE_ID_BAHAMA };
1756
1757 const struct bahama_config_register v20_init[] = {
1758 /* reg, value, mask */
1759 { 0xF4, 0x84, 0xFF }, /* AREG */
1760 { 0xF0, 0x04, 0xFF } /* DREG */
1761 };
1762
1763 if (read_bahama_ver() == VER_2_0) {
1764 for (i = 0; i < ARRAY_SIZE(v20_init); i++) {
1765 u8 value = v20_init[i].value;
1766 rc = marimba_write_bit_mask(&config,
1767 v20_init[i].reg,
1768 &value,
1769 sizeof(v20_init[i].value),
1770 v20_init[i].mask);
1771 if (rc < 0) {
1772 printk(KERN_ERR
1773 "%s: reg %d write failed: %d\n",
1774 __func__, v20_init[i].reg, rc);
1775 return rc;
1776 }
1777 printk(KERN_INFO "%s: reg 0x%02x value 0x%02x"
1778 " mask 0x%02x\n",
1779 __func__, v20_init[i].reg,
1780 v20_init[i].value, v20_init[i].mask);
1781 }
1782 }
1783 }
1784 printk(KERN_INFO "core type: %d\n", type);
1785
1786 return rc;
1787}
1788
1789static unsigned int msm_bahama_setup_power(void)
1790{
1791 int rc;
1792
1793 rc = vreg_enable(vreg_marimba_3);
1794 if (rc) {
1795 printk(KERN_ERR "%s: vreg_enable() = %d\n",
1796 __func__, rc);
1797 }
1798
1799 return rc;
1800};
1801
1802static unsigned int msm_bahama_shutdown_power(int value)
1803{
1804 int rc = 0;
1805
1806 if (value != BAHAMA_ID) {
1807 rc = vreg_disable(vreg_marimba_3);
1808 if (rc) {
1809 printk(KERN_ERR "%s: return val: %d\n",
1810 __func__, rc);
1811 }
1812 }
1813
1814 return rc;
1815};
1816
1817static struct msm_gpio marimba_svlte_config_clock[] = {
1818 { GPIO_CFG(34, 0, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA),
1819 "MARIMBA_SVLTE_CLOCK_ENABLE" },
1820};
1821
1822static unsigned int msm_marimba_gpio_config_svlte(int gpio_cfg_marimba)
1823{
1824 if (machine_is_msm8x55_svlte_surf() ||
1825 machine_is_msm8x55_svlte_ffa()) {
1826 if (gpio_cfg_marimba)
1827 gpio_set_value(GPIO_PIN
1828 (marimba_svlte_config_clock->gpio_cfg), 1);
1829 else
1830 gpio_set_value(GPIO_PIN
1831 (marimba_svlte_config_clock->gpio_cfg), 0);
1832 }
1833
1834 return 0;
1835};
1836
1837static unsigned int msm_marimba_setup_power(void)
1838{
1839 int rc;
1840
1841 rc = vreg_enable(vreg_marimba_1);
1842 if (rc) {
1843 printk(KERN_ERR "%s: vreg_enable() = %d \n",
1844 __func__, rc);
1845 goto out;
1846 }
1847 rc = vreg_enable(vreg_marimba_2);
1848 if (rc) {
1849 printk(KERN_ERR "%s: vreg_enable() = %d \n",
1850 __func__, rc);
1851 goto out;
1852 }
1853
1854 if (machine_is_msm8x55_svlte_surf() || machine_is_msm8x55_svlte_ffa()) {
1855 rc = msm_gpios_request_enable(marimba_svlte_config_clock,
1856 ARRAY_SIZE(marimba_svlte_config_clock));
1857 if (rc < 0) {
1858 printk(KERN_ERR
1859 "%s: msm_gpios_request_enable failed (%d)\n",
1860 __func__, rc);
1861 return rc;
1862 }
1863
1864 rc = gpio_direction_output(GPIO_PIN
1865 (marimba_svlte_config_clock->gpio_cfg), 0);
1866 if (rc < 0) {
1867 printk(KERN_ERR
1868 "%s: gpio_direction_output failed (%d)\n",
1869 __func__, rc);
1870 return rc;
1871 }
1872 }
1873
1874out:
1875 return rc;
1876};
1877
1878static void msm_marimba_shutdown_power(void)
1879{
1880 int rc;
1881
1882 rc = vreg_disable(vreg_marimba_1);
1883 if (rc) {
1884 printk(KERN_ERR "%s: return val: %d\n",
1885 __func__, rc);
1886 }
1887 rc = vreg_disable(vreg_marimba_2);
1888 if (rc) {
1889 printk(KERN_ERR "%s: return val: %d \n",
1890 __func__, rc);
1891 }
1892};
1893
1894static int bahama_present(void)
1895{
1896 int id;
1897 switch (id = adie_get_detected_connectivity_type()) {
1898 case BAHAMA_ID:
1899 return 1;
1900
1901 case MARIMBA_ID:
1902 return 0;
1903
1904 case TIMPANI_ID:
1905 default:
1906 printk(KERN_ERR "%s: unexpected adie connectivity type: %d\n",
1907 __func__, id);
1908 return -ENODEV;
1909 }
1910}
1911
1912struct vreg *fm_regulator;
1913static int fm_radio_setup(struct marimba_fm_platform_data *pdata)
1914{
1915 int rc;
1916 uint32_t irqcfg;
1917 const char *id = "FMPW";
1918
1919 int bahama_not_marimba = bahama_present();
1920
1921 if (bahama_not_marimba == -1) {
1922 printk(KERN_WARNING "%s: bahama_present: %d\n",
1923 __func__, bahama_not_marimba);
1924 return -ENODEV;
1925 }
1926 if (bahama_not_marimba)
1927 fm_regulator = vreg_get(NULL, "s3");
1928 else
1929 fm_regulator = vreg_get(NULL, "s2");
1930
1931 if (IS_ERR(fm_regulator)) {
1932 printk(KERN_ERR "%s: vreg get failed (%ld)\n",
1933 __func__, PTR_ERR(fm_regulator));
1934 return -1;
1935 }
1936 if (!bahama_not_marimba) {
1937
1938 rc = pmapp_vreg_level_vote(id, PMAPP_VREG_S2, 1300);
1939
1940 if (rc < 0) {
1941 printk(KERN_ERR "%s: voltage level vote failed (%d)\n",
1942 __func__, rc);
1943 return rc;
1944 }
1945 }
1946 rc = vreg_enable(fm_regulator);
1947 if (rc) {
1948 printk(KERN_ERR "%s: vreg_enable() = %d\n",
1949 __func__, rc);
1950 return rc;
1951 }
1952
1953 rc = pmapp_clock_vote(id, PMAPP_CLOCK_ID_DO,
1954 PMAPP_CLOCK_VOTE_ON);
1955 if (rc < 0) {
1956 printk(KERN_ERR "%s: clock vote failed (%d)\n",
1957 __func__, rc);
1958 goto fm_clock_vote_fail;
1959 }
1960 /*Request the Clock Using GPIO34/AP2MDM_MRMBCK_EN in case
1961 of svlte*/
1962 if (machine_is_msm8x55_svlte_surf() ||
1963 machine_is_msm8x55_svlte_ffa()) {
1964 rc = marimba_gpio_config(1);
1965 if (rc < 0)
1966 printk(KERN_ERR "%s: clock enable for svlte : %d\n",
1967 __func__, rc);
1968 }
1969 irqcfg = GPIO_CFG(147, 0, GPIO_CFG_INPUT, GPIO_CFG_NO_PULL,
1970 GPIO_CFG_2MA);
1971 rc = gpio_tlmm_config(irqcfg, GPIO_CFG_ENABLE);
1972 if (rc) {
1973 printk(KERN_ERR "%s: gpio_tlmm_config(%#x)=%d\n",
1974 __func__, irqcfg, rc);
1975 rc = -EIO;
1976 goto fm_gpio_config_fail;
1977
1978 }
1979 return 0;
1980fm_gpio_config_fail:
1981 pmapp_clock_vote(id, PMAPP_CLOCK_ID_DO,
1982 PMAPP_CLOCK_VOTE_OFF);
1983fm_clock_vote_fail:
1984 vreg_disable(fm_regulator);
1985 return rc;
1986
1987};
1988
1989static void fm_radio_shutdown(struct marimba_fm_platform_data *pdata)
1990{
1991 int rc;
1992 const char *id = "FMPW";
1993 uint32_t irqcfg = GPIO_CFG(147, 0, GPIO_CFG_INPUT, GPIO_CFG_PULL_UP,
1994 GPIO_CFG_2MA);
1995
1996 int bahama_not_marimba = bahama_present();
1997 if (bahama_not_marimba == -1) {
1998 printk(KERN_WARNING "%s: bahama_present: %d\n",
1999 __func__, bahama_not_marimba);
2000 return;
2001 }
2002
2003 rc = gpio_tlmm_config(irqcfg, GPIO_CFG_ENABLE);
2004 if (rc) {
2005 printk(KERN_ERR "%s: gpio_tlmm_config(%#x)=%d\n",
2006 __func__, irqcfg, rc);
2007 }
2008 if (fm_regulator != NULL) {
2009 rc = vreg_disable(fm_regulator);
2010
2011 if (rc) {
2012 printk(KERN_ERR "%s: return val: %d\n",
2013 __func__, rc);
2014 }
2015 fm_regulator = NULL;
2016 }
2017 rc = pmapp_clock_vote(id, PMAPP_CLOCK_ID_DO,
2018 PMAPP_CLOCK_VOTE_OFF);
2019 if (rc < 0)
2020 printk(KERN_ERR "%s: clock_vote return val: %d\n",
2021 __func__, rc);
2022
2023 /*Disable the Clock Using GPIO34/AP2MDM_MRMBCK_EN in case
2024 of svlte*/
2025 if (machine_is_msm8x55_svlte_surf() ||
2026 machine_is_msm8x55_svlte_ffa()) {
2027 rc = marimba_gpio_config(0);
2028 if (rc < 0)
2029 printk(KERN_ERR "%s: clock disable for svlte : %d\n",
2030 __func__, rc);
2031 }
2032
2033
2034 if (!bahama_not_marimba) {
2035 rc = pmapp_vreg_level_vote(id, PMAPP_VREG_S2, 0);
2036
2037 if (rc < 0)
2038 printk(KERN_ERR "%s: vreg level vote return val: %d\n",
2039 __func__, rc);
2040 }
2041}
2042
2043static struct marimba_fm_platform_data marimba_fm_pdata = {
2044 .fm_setup = fm_radio_setup,
2045 .fm_shutdown = fm_radio_shutdown,
2046 .irq = MSM_GPIO_TO_INT(147),
2047 .vreg_s2 = NULL,
2048 .vreg_xo_out = NULL,
2049 .is_fm_soc_i2s_master = false,
2050 .config_i2s_gpio = NULL,
2051};
2052
2053
2054/* Slave id address for FM/CDC/QMEMBIST
2055 * Values can be programmed using Marimba slave id 0
2056 * should there be a conflict with other I2C devices
2057 * */
2058#define MARIMBA_SLAVE_ID_FM_ADDR 0x2A
2059#define MARIMBA_SLAVE_ID_CDC_ADDR 0x77
2060#define MARIMBA_SLAVE_ID_QMEMBIST_ADDR 0X66
2061
2062#define BAHAMA_SLAVE_ID_FM_ADDR 0x2A
2063#define BAHAMA_SLAVE_ID_QMEMBIST_ADDR 0x7B
2064
2065static const char *tsadc_id = "MADC";
2066static const char *vregs_tsadc_name[] = {
2067 "gp12",
2068 "s2",
2069};
2070static struct vreg *vregs_tsadc[ARRAY_SIZE(vregs_tsadc_name)];
2071
2072static const char *vregs_timpani_tsadc_name[] = {
2073 "s3",
2074 "gp12",
2075 "gp16"
2076};
2077static struct vreg *vregs_timpani_tsadc[ARRAY_SIZE(vregs_timpani_tsadc_name)];
2078
2079static int marimba_tsadc_power(int vreg_on)
2080{
2081 int i, rc = 0;
2082 int tsadc_adie_type = adie_get_detected_codec_type();
2083
2084 if (tsadc_adie_type == TIMPANI_ID) {
2085 for (i = 0; i < ARRAY_SIZE(vregs_timpani_tsadc_name); i++) {
2086 if (!vregs_timpani_tsadc[i]) {
2087 pr_err("%s: vreg_get %s failed(%d)\n",
2088 __func__, vregs_timpani_tsadc_name[i], rc);
2089 goto vreg_fail;
2090 }
2091
2092 rc = vreg_on ? vreg_enable(vregs_timpani_tsadc[i]) :
2093 vreg_disable(vregs_timpani_tsadc[i]);
2094 if (rc < 0) {
2095 pr_err("%s: vreg %s %s failed(%d)\n",
2096 __func__, vregs_timpani_tsadc_name[i],
2097 vreg_on ? "enable" : "disable", rc);
2098 goto vreg_fail;
2099 }
2100 }
2101 /* Vote for D0 and D1 buffer */
2102 rc = pmapp_clock_vote(tsadc_id, PMAPP_CLOCK_ID_D1,
2103 vreg_on ? PMAPP_CLOCK_VOTE_ON : PMAPP_CLOCK_VOTE_OFF);
2104 if (rc) {
2105 pr_err("%s: unable to %svote for d1 clk\n",
2106 __func__, vreg_on ? "" : "de-");
2107 goto do_vote_fail;
2108 }
2109 rc = pmapp_clock_vote(tsadc_id, PMAPP_CLOCK_ID_DO,
2110 vreg_on ? PMAPP_CLOCK_VOTE_ON : PMAPP_CLOCK_VOTE_OFF);
2111 if (rc) {
2112 pr_err("%s: unable to %svote for d1 clk\n",
2113 __func__, vreg_on ? "" : "de-");
2114 goto do_vote_fail;
2115 }
2116 } else if (tsadc_adie_type == MARIMBA_ID) {
2117 for (i = 0; i < ARRAY_SIZE(vregs_tsadc_name); i++) {
2118 if (!vregs_tsadc[i]) {
2119 pr_err("%s: vreg_get %s failed (%d)\n",
2120 __func__, vregs_tsadc_name[i], rc);
2121 goto vreg_fail;
2122 }
2123
2124 rc = vreg_on ? vreg_enable(vregs_tsadc[i]) :
2125 vreg_disable(vregs_tsadc[i]);
2126 if (rc < 0) {
2127 pr_err("%s: vreg %s %s failed (%d)\n",
2128 __func__, vregs_tsadc_name[i],
2129 vreg_on ? "enable" : "disable", rc);
2130 goto vreg_fail;
2131 }
2132 }
2133 /* If marimba vote for DO buffer */
2134 rc = pmapp_clock_vote(tsadc_id, PMAPP_CLOCK_ID_DO,
2135 vreg_on ? PMAPP_CLOCK_VOTE_ON : PMAPP_CLOCK_VOTE_OFF);
2136 if (rc) {
2137 pr_err("%s: unable to %svote for d0 clk\n",
2138 __func__, vreg_on ? "" : "de-");
2139 goto do_vote_fail;
2140 }
2141 } else {
2142 pr_err("%s:Adie %d not supported\n",
2143 __func__, tsadc_adie_type);
2144 return -ENODEV;
2145 }
2146
2147 msleep(5); /* ensure power is stable */
2148
2149 return 0;
2150
2151do_vote_fail:
2152vreg_fail:
2153 while (i) {
2154 if (vreg_on) {
2155 if (tsadc_adie_type == TIMPANI_ID)
2156 vreg_disable(vregs_timpani_tsadc[--i]);
2157 else if (tsadc_adie_type == MARIMBA_ID)
2158 vreg_disable(vregs_tsadc[--i]);
2159 } else {
2160 if (tsadc_adie_type == TIMPANI_ID)
2161 vreg_enable(vregs_timpani_tsadc[--i]);
2162 else if (tsadc_adie_type == MARIMBA_ID)
2163 vreg_enable(vregs_tsadc[--i]);
2164 }
2165 }
2166
2167 return rc;
2168}
2169
2170static int marimba_tsadc_vote(int vote_on)
2171{
2172 int rc = 0;
2173
2174 if (adie_get_detected_codec_type() == MARIMBA_ID) {
2175 int level = vote_on ? 1300 : 0;
2176 rc = pmapp_vreg_level_vote(tsadc_id, PMAPP_VREG_S2, level);
2177 if (rc < 0)
2178 pr_err("%s: vreg level %s failed (%d)\n",
2179 __func__, vote_on ? "on" : "off", rc);
2180 }
2181
2182 return rc;
2183}
2184
2185static int marimba_tsadc_init(void)
2186{
2187 int i, rc = 0;
2188 int tsadc_adie_type = adie_get_detected_codec_type();
2189
2190 if (tsadc_adie_type == TIMPANI_ID) {
2191 for (i = 0; i < ARRAY_SIZE(vregs_timpani_tsadc_name); i++) {
2192 vregs_timpani_tsadc[i] = vreg_get(NULL,
2193 vregs_timpani_tsadc_name[i]);
2194 if (IS_ERR(vregs_timpani_tsadc[i])) {
2195 pr_err("%s: vreg get %s failed (%ld)\n",
2196 __func__, vregs_timpani_tsadc_name[i],
2197 PTR_ERR(vregs_timpani_tsadc[i]));
2198 rc = PTR_ERR(vregs_timpani_tsadc[i]);
2199 goto vreg_get_fail;
2200 }
2201 }
2202 } else if (tsadc_adie_type == MARIMBA_ID) {
2203 for (i = 0; i < ARRAY_SIZE(vregs_tsadc_name); i++) {
2204 vregs_tsadc[i] = vreg_get(NULL, vregs_tsadc_name[i]);
2205 if (IS_ERR(vregs_tsadc[i])) {
2206 pr_err("%s: vreg get %s failed (%ld)\n",
2207 __func__, vregs_tsadc_name[i],
2208 PTR_ERR(vregs_tsadc[i]));
2209 rc = PTR_ERR(vregs_tsadc[i]);
2210 goto vreg_get_fail;
2211 }
2212 }
2213 } else {
2214 pr_err("%s:Adie %d not supported\n",
2215 __func__, tsadc_adie_type);
2216 return -ENODEV;
2217 }
2218
2219 return 0;
2220
2221vreg_get_fail:
2222 while (i) {
2223 if (tsadc_adie_type == TIMPANI_ID)
2224 vreg_put(vregs_timpani_tsadc[--i]);
2225 else if (tsadc_adie_type == MARIMBA_ID)
2226 vreg_put(vregs_tsadc[--i]);
2227 }
2228 return rc;
2229}
2230
2231static int marimba_tsadc_exit(void)
2232{
2233 int i, rc = 0;
2234 int tsadc_adie_type = adie_get_detected_codec_type();
2235
2236 if (tsadc_adie_type == TIMPANI_ID) {
2237 for (i = 0; i < ARRAY_SIZE(vregs_timpani_tsadc_name); i++) {
2238 if (vregs_tsadc[i])
2239 vreg_put(vregs_timpani_tsadc[i]);
2240 }
2241 } else if (tsadc_adie_type == MARIMBA_ID) {
2242 for (i = 0; i < ARRAY_SIZE(vregs_tsadc_name); i++) {
2243 if (vregs_tsadc[i])
2244 vreg_put(vregs_tsadc[i]);
2245 }
2246 rc = pmapp_vreg_level_vote(tsadc_id, PMAPP_VREG_S2, 0);
2247 if (rc < 0)
2248 pr_err("%s: vreg level off failed (%d)\n",
2249 __func__, rc);
2250 } else {
2251 pr_err("%s:Adie %d not supported\n",
2252 __func__, tsadc_adie_type);
2253 rc = -ENODEV;
2254 }
2255
2256 return rc;
2257}
2258
2259
2260static struct msm_ts_platform_data msm_ts_data = {
2261 .min_x = 0,
2262 .max_x = 4096,
2263 .min_y = 0,
2264 .max_y = 4096,
2265 .min_press = 0,
2266 .max_press = 255,
2267 .inv_x = 4096,
2268 .inv_y = 4096,
2269 .can_wakeup = false,
2270};
2271
2272static struct marimba_tsadc_platform_data marimba_tsadc_pdata = {
2273 .marimba_tsadc_power = marimba_tsadc_power,
2274 .init = marimba_tsadc_init,
2275 .exit = marimba_tsadc_exit,
2276 .level_vote = marimba_tsadc_vote,
2277 .tsadc_prechg_en = true,
2278 .can_wakeup = false,
2279 .setup = {
2280 .pen_irq_en = true,
2281 .tsadc_en = true,
2282 },
2283 .params2 = {
2284 .input_clk_khz = 2400,
2285 .sample_prd = TSADC_CLK_3,
2286 },
2287 .params3 = {
2288 .prechg_time_nsecs = 6400,
2289 .stable_time_nsecs = 6400,
2290 .tsadc_test_mode = 0,
2291 },
2292 .tssc_data = &msm_ts_data,
2293};
2294
2295static struct vreg *vreg_codec_s4;
2296static int msm_marimba_codec_power(int vreg_on)
2297{
2298 int rc = 0;
2299
2300 if (!vreg_codec_s4) {
2301
2302 vreg_codec_s4 = vreg_get(NULL, "s4");
2303
2304 if (IS_ERR(vreg_codec_s4)) {
2305 printk(KERN_ERR "%s: vreg_get() failed (%ld)\n",
2306 __func__, PTR_ERR(vreg_codec_s4));
2307 rc = PTR_ERR(vreg_codec_s4);
2308 goto vreg_codec_s4_fail;
2309 }
2310 }
2311
2312 if (vreg_on) {
2313 rc = vreg_enable(vreg_codec_s4);
2314 if (rc)
2315 printk(KERN_ERR "%s: vreg_enable() = %d \n",
2316 __func__, rc);
2317 goto vreg_codec_s4_fail;
2318 } else {
2319 rc = vreg_disable(vreg_codec_s4);
2320 if (rc)
2321 printk(KERN_ERR "%s: vreg_disable() = %d \n",
2322 __func__, rc);
2323 goto vreg_codec_s4_fail;
2324 }
2325
2326vreg_codec_s4_fail:
2327 return rc;
2328}
2329
2330static struct marimba_codec_platform_data mariba_codec_pdata = {
2331 .marimba_codec_power = msm_marimba_codec_power,
2332#ifdef CONFIG_MARIMBA_CODEC
2333 .snddev_profile_init = msm_snddev_init,
2334#endif
2335};
2336
2337static struct marimba_platform_data marimba_pdata = {
2338 .slave_id[MARIMBA_SLAVE_ID_FM] = MARIMBA_SLAVE_ID_FM_ADDR,
2339 .slave_id[MARIMBA_SLAVE_ID_CDC] = MARIMBA_SLAVE_ID_CDC_ADDR,
2340 .slave_id[MARIMBA_SLAVE_ID_QMEMBIST] = MARIMBA_SLAVE_ID_QMEMBIST_ADDR,
2341 .slave_id[SLAVE_ID_BAHAMA_FM] = BAHAMA_SLAVE_ID_FM_ADDR,
2342 .slave_id[SLAVE_ID_BAHAMA_QMEMBIST] = BAHAMA_SLAVE_ID_QMEMBIST_ADDR,
2343 .marimba_setup = msm_marimba_setup_power,
2344 .marimba_shutdown = msm_marimba_shutdown_power,
2345 .bahama_setup = msm_bahama_setup_power,
2346 .bahama_shutdown = msm_bahama_shutdown_power,
2347 .marimba_gpio_config = msm_marimba_gpio_config_svlte,
2348 .bahama_core_config = msm_bahama_core_config,
2349 .fm = &marimba_fm_pdata,
2350 .codec = &mariba_codec_pdata,
2351 .tsadc_ssbi_adap = MARIMBA_SSBI_ADAP,
2352};
2353
2354static void __init msm7x30_init_marimba(void)
2355{
2356 int rc;
2357
2358 vreg_marimba_1 = vreg_get(NULL, "s3");
2359 if (IS_ERR(vreg_marimba_1)) {
2360 printk(KERN_ERR "%s: vreg get failed (%ld)\n",
2361 __func__, PTR_ERR(vreg_marimba_1));
2362 return;
2363 }
2364 rc = vreg_set_level(vreg_marimba_1, 1800);
2365
2366 vreg_marimba_2 = vreg_get(NULL, "gp16");
2367 if (IS_ERR(vreg_marimba_1)) {
2368 printk(KERN_ERR "%s: vreg get failed (%ld)\n",
2369 __func__, PTR_ERR(vreg_marimba_1));
2370 return;
2371 }
2372 rc = vreg_set_level(vreg_marimba_2, 1200);
2373
2374 vreg_marimba_3 = vreg_get(NULL, "usb2");
2375 if (IS_ERR(vreg_marimba_3)) {
2376 printk(KERN_ERR "%s: vreg get failed (%ld)\n",
2377 __func__, PTR_ERR(vreg_marimba_3));
2378 return;
2379 }
2380 rc = vreg_set_level(vreg_marimba_3, 1800);
2381}
2382
2383static struct marimba_codec_platform_data timpani_codec_pdata = {
2384 .marimba_codec_power = msm_marimba_codec_power,
2385#ifdef CONFIG_TIMPANI_CODEC
2386 .snddev_profile_init = msm_snddev_init_timpani,
2387#endif
2388};
2389
2390static struct marimba_platform_data timpani_pdata = {
2391 .slave_id[MARIMBA_SLAVE_ID_CDC] = MARIMBA_SLAVE_ID_CDC_ADDR,
2392 .slave_id[MARIMBA_SLAVE_ID_QMEMBIST] = MARIMBA_SLAVE_ID_QMEMBIST_ADDR,
2393 .marimba_setup = msm_timpani_setup_power,
2394 .marimba_shutdown = msm_timpani_shutdown_power,
2395 .codec = &timpani_codec_pdata,
2396 .tsadc = &marimba_tsadc_pdata,
2397 .tsadc_ssbi_adap = MARIMBA_SSBI_ADAP,
2398};
2399
2400#define TIMPANI_I2C_SLAVE_ADDR 0xD
2401
2402static struct i2c_board_info msm_i2c_gsbi7_timpani_info[] = {
2403 {
2404 I2C_BOARD_INFO("timpani", TIMPANI_I2C_SLAVE_ADDR),
2405 .platform_data = &timpani_pdata,
2406 },
2407};
2408
2409#ifdef CONFIG_MSM7KV2_AUDIO
2410static struct resource msm_aictl_resources[] = {
2411 {
2412 .name = "aictl",
2413 .start = 0xa5000100,
2414 .end = 0xa5000100,
2415 .flags = IORESOURCE_MEM,
2416 }
2417};
2418
2419static struct resource msm_mi2s_resources[] = {
2420 {
2421 .name = "hdmi",
2422 .start = 0xac900000,
2423 .end = 0xac900038,
2424 .flags = IORESOURCE_MEM,
2425 },
2426 {
2427 .name = "codec_rx",
2428 .start = 0xac940040,
2429 .end = 0xac940078,
2430 .flags = IORESOURCE_MEM,
2431 },
2432 {
2433 .name = "codec_tx",
2434 .start = 0xac980080,
2435 .end = 0xac9800B8,
2436 .flags = IORESOURCE_MEM,
2437 }
2438
2439};
2440
2441static struct msm_lpa_platform_data lpa_pdata = {
2442 .obuf_hlb_size = 0x2BFF8,
2443 .dsp_proc_id = 0,
2444 .app_proc_id = 2,
2445 .nosb_config = {
2446 .llb_min_addr = 0,
2447 .llb_max_addr = 0x3ff8,
2448 .sb_min_addr = 0,
2449 .sb_max_addr = 0,
2450 },
2451 .sb_config = {
2452 .llb_min_addr = 0,
2453 .llb_max_addr = 0x37f8,
2454 .sb_min_addr = 0x3800,
2455 .sb_max_addr = 0x3ff8,
2456 }
2457};
2458
2459static struct resource msm_lpa_resources[] = {
2460 {
2461 .name = "lpa",
2462 .start = 0xa5000000,
2463 .end = 0xa50000a0,
2464 .flags = IORESOURCE_MEM,
2465 }
2466};
2467
2468static struct resource msm_aux_pcm_resources[] = {
2469
2470 {
2471 .name = "aux_codec_reg_addr",
2472 .start = 0xac9c00c0,
2473 .end = 0xac9c00c8,
2474 .flags = IORESOURCE_MEM,
2475 },
2476 {
2477 .name = "aux_pcm_dout",
2478 .start = 138,
2479 .end = 138,
2480 .flags = IORESOURCE_IO,
2481 },
2482 {
2483 .name = "aux_pcm_din",
2484 .start = 139,
2485 .end = 139,
2486 .flags = IORESOURCE_IO,
2487 },
2488 {
2489 .name = "aux_pcm_syncout",
2490 .start = 140,
2491 .end = 140,
2492 .flags = IORESOURCE_IO,
2493 },
2494 {
2495 .name = "aux_pcm_clkin_a",
2496 .start = 141,
2497 .end = 141,
2498 .flags = IORESOURCE_IO,
2499 },
2500};
2501
2502static struct platform_device msm_aux_pcm_device = {
2503 .name = "msm_aux_pcm",
2504 .id = 0,
2505 .num_resources = ARRAY_SIZE(msm_aux_pcm_resources),
2506 .resource = msm_aux_pcm_resources,
2507};
2508
2509struct platform_device msm_aictl_device = {
2510 .name = "audio_interct",
2511 .id = 0,
2512 .num_resources = ARRAY_SIZE(msm_aictl_resources),
2513 .resource = msm_aictl_resources,
2514};
2515
2516struct platform_device msm_mi2s_device = {
2517 .name = "mi2s",
2518 .id = 0,
2519 .num_resources = ARRAY_SIZE(msm_mi2s_resources),
2520 .resource = msm_mi2s_resources,
2521};
2522
2523struct platform_device msm_lpa_device = {
2524 .name = "lpa",
2525 .id = 0,
2526 .num_resources = ARRAY_SIZE(msm_lpa_resources),
2527 .resource = msm_lpa_resources,
2528 .dev = {
2529 .platform_data = &lpa_pdata,
2530 },
2531};
2532#endif /* CONFIG_MSM7KV2_AUDIO */
2533
2534#define DEC0_FORMAT ((1<<MSM_ADSP_CODEC_MP3)| \
2535 (1<<MSM_ADSP_CODEC_AAC)|(1<<MSM_ADSP_CODEC_WMA)| \
2536 (1<<MSM_ADSP_CODEC_WMAPRO)|(1<<MSM_ADSP_CODEC_AMRWB)| \
2537 (1<<MSM_ADSP_CODEC_AMRNB)|(1<<MSM_ADSP_CODEC_WAV)| \
2538 (1<<MSM_ADSP_CODEC_ADPCM)|(1<<MSM_ADSP_CODEC_YADPCM)| \
2539 (1<<MSM_ADSP_CODEC_EVRC)|(1<<MSM_ADSP_CODEC_QCELP))
2540#define DEC1_FORMAT ((1<<MSM_ADSP_CODEC_MP3)| \
2541 (1<<MSM_ADSP_CODEC_AAC)|(1<<MSM_ADSP_CODEC_WMA)| \
2542 (1<<MSM_ADSP_CODEC_WMAPRO)|(1<<MSM_ADSP_CODEC_AMRWB)| \
2543 (1<<MSM_ADSP_CODEC_AMRNB)|(1<<MSM_ADSP_CODEC_WAV)| \
2544 (1<<MSM_ADSP_CODEC_ADPCM)|(1<<MSM_ADSP_CODEC_YADPCM)| \
2545 (1<<MSM_ADSP_CODEC_EVRC)|(1<<MSM_ADSP_CODEC_QCELP))
2546 #define DEC2_FORMAT ((1<<MSM_ADSP_CODEC_MP3)| \
2547 (1<<MSM_ADSP_CODEC_AAC)|(1<<MSM_ADSP_CODEC_WMA)| \
2548 (1<<MSM_ADSP_CODEC_WMAPRO)|(1<<MSM_ADSP_CODEC_AMRWB)| \
2549 (1<<MSM_ADSP_CODEC_AMRNB)|(1<<MSM_ADSP_CODEC_WAV)| \
2550 (1<<MSM_ADSP_CODEC_ADPCM)|(1<<MSM_ADSP_CODEC_YADPCM)| \
2551 (1<<MSM_ADSP_CODEC_EVRC)|(1<<MSM_ADSP_CODEC_QCELP))
2552 #define DEC3_FORMAT ((1<<MSM_ADSP_CODEC_MP3)| \
2553 (1<<MSM_ADSP_CODEC_AAC)|(1<<MSM_ADSP_CODEC_WMA)| \
2554 (1<<MSM_ADSP_CODEC_WMAPRO)|(1<<MSM_ADSP_CODEC_AMRWB)| \
2555 (1<<MSM_ADSP_CODEC_AMRNB)|(1<<MSM_ADSP_CODEC_WAV)| \
2556 (1<<MSM_ADSP_CODEC_ADPCM)|(1<<MSM_ADSP_CODEC_YADPCM)| \
2557 (1<<MSM_ADSP_CODEC_EVRC)|(1<<MSM_ADSP_CODEC_QCELP))
2558#define DEC4_FORMAT (1<<MSM_ADSP_CODEC_MIDI)
2559
2560static unsigned int dec_concurrency_table[] = {
2561 /* Audio LP */
2562 0,
2563 (DEC3_FORMAT|(1<<MSM_ADSP_MODE_NONTUNNEL)|(1<<MSM_ADSP_OP_DM)),
2564 (DEC2_FORMAT|(1<<MSM_ADSP_MODE_NONTUNNEL)|(1<<MSM_ADSP_OP_DM)),
2565 (DEC1_FORMAT|(1<<MSM_ADSP_MODE_NONTUNNEL)|(1<<MSM_ADSP_OP_DM)),
2566 (DEC0_FORMAT|(1<<MSM_ADSP_MODE_TUNNEL)|(1<<MSM_ADSP_MODE_LP)|
2567 (1<<MSM_ADSP_OP_DM)),
2568
2569 /* Concurrency 1 */
2570 (DEC4_FORMAT),
2571 (DEC3_FORMAT|(1<<MSM_ADSP_MODE_TUNNEL)|(1<<MSM_ADSP_OP_DM)),
2572 (DEC2_FORMAT|(1<<MSM_ADSP_MODE_TUNNEL)|(1<<MSM_ADSP_OP_DM)),
2573 (DEC1_FORMAT|(1<<MSM_ADSP_MODE_TUNNEL)|(1<<MSM_ADSP_OP_DM)),
2574 (DEC0_FORMAT|(1<<MSM_ADSP_MODE_TUNNEL)|(1<<MSM_ADSP_OP_DM)),
2575
2576 /* Concurrency 2 */
2577 (DEC4_FORMAT),
2578 (DEC3_FORMAT|(1<<MSM_ADSP_MODE_TUNNEL)|(1<<MSM_ADSP_OP_DM)),
2579 (DEC2_FORMAT|(1<<MSM_ADSP_MODE_TUNNEL)|(1<<MSM_ADSP_OP_DM)),
2580 (DEC1_FORMAT|(1<<MSM_ADSP_MODE_TUNNEL)|(1<<MSM_ADSP_OP_DM)),
2581 (DEC0_FORMAT|(1<<MSM_ADSP_MODE_TUNNEL)|(1<<MSM_ADSP_OP_DM)),
2582
2583 /* Concurrency 3 */
2584 (DEC4_FORMAT),
2585 (DEC3_FORMAT|(1<<MSM_ADSP_MODE_TUNNEL)|(1<<MSM_ADSP_OP_DM)),
2586 (DEC2_FORMAT|(1<<MSM_ADSP_MODE_TUNNEL)|(1<<MSM_ADSP_OP_DM)),
2587 (DEC1_FORMAT|(1<<MSM_ADSP_MODE_TUNNEL)|(1<<MSM_ADSP_OP_DM)),
2588 (DEC0_FORMAT|(1<<MSM_ADSP_MODE_NONTUNNEL)|(1<<MSM_ADSP_OP_DM)),
2589
2590 /* Concurrency 4 */
2591 (DEC4_FORMAT),
2592 (DEC3_FORMAT|(1<<MSM_ADSP_MODE_TUNNEL)|(1<<MSM_ADSP_OP_DM)),
2593 (DEC2_FORMAT|(1<<MSM_ADSP_MODE_TUNNEL)|(1<<MSM_ADSP_OP_DM)),
2594 (DEC1_FORMAT|(1<<MSM_ADSP_MODE_NONTUNNEL)|(1<<MSM_ADSP_OP_DM)),
2595 (DEC0_FORMAT|(1<<MSM_ADSP_MODE_NONTUNNEL)|(1<<MSM_ADSP_OP_DM)),
2596
2597 /* Concurrency 5 */
2598 (DEC4_FORMAT),
2599 (DEC3_FORMAT|(1<<MSM_ADSP_MODE_TUNNEL)|(1<<MSM_ADSP_OP_DM)),
2600 (DEC2_FORMAT|(1<<MSM_ADSP_MODE_NONTUNNEL)|(1<<MSM_ADSP_OP_DM)),
2601 (DEC1_FORMAT|(1<<MSM_ADSP_MODE_NONTUNNEL)|(1<<MSM_ADSP_OP_DM)),
2602 (DEC0_FORMAT|(1<<MSM_ADSP_MODE_NONTUNNEL)|(1<<MSM_ADSP_OP_DM)),
2603
2604 /* Concurrency 6 */
2605 (DEC4_FORMAT),
2606 (DEC3_FORMAT|(1<<MSM_ADSP_MODE_NONTUNNEL)|(1<<MSM_ADSP_OP_DM)),
2607 (DEC2_FORMAT|(1<<MSM_ADSP_MODE_NONTUNNEL)|(1<<MSM_ADSP_OP_DM)),
2608 (DEC1_FORMAT|(1<<MSM_ADSP_MODE_NONTUNNEL)|(1<<MSM_ADSP_OP_DM)),
2609 (DEC0_FORMAT|(1<<MSM_ADSP_MODE_NONTUNNEL)|(1<<MSM_ADSP_OP_DM)),
2610};
2611
2612#define DEC_INFO(name, queueid, decid, nr_codec) { .module_name = name, \
2613 .module_queueid = queueid, .module_decid = decid, \
2614 .nr_codec_support = nr_codec}
2615
2616#define DEC_INSTANCE(max_instance_same, max_instance_diff) { \
2617 .max_instances_same_dec = max_instance_same, \
2618 .max_instances_diff_dec = max_instance_diff}
2619
2620static struct msm_adspdec_info dec_info_list[] = {
2621 DEC_INFO("AUDPLAY4TASK", 17, 4, 1), /* AudPlay4BitStreamCtrlQueue */
2622 DEC_INFO("AUDPLAY3TASK", 16, 3, 11), /* AudPlay3BitStreamCtrlQueue */
2623 DEC_INFO("AUDPLAY2TASK", 15, 2, 11), /* AudPlay2BitStreamCtrlQueue */
2624 DEC_INFO("AUDPLAY1TASK", 14, 1, 11), /* AudPlay1BitStreamCtrlQueue */
2625 DEC_INFO("AUDPLAY0TASK", 13, 0, 11), /* AudPlay0BitStreamCtrlQueue */
2626};
2627
2628static struct dec_instance_table dec_instance_list[][MSM_MAX_DEC_CNT] = {
2629 /* Non Turbo Mode */
2630 {
2631 DEC_INSTANCE(4, 3), /* WAV */
2632 DEC_INSTANCE(4, 3), /* ADPCM */
2633 DEC_INSTANCE(4, 2), /* MP3 */
2634 DEC_INSTANCE(0, 0), /* Real Audio */
2635 DEC_INSTANCE(4, 2), /* WMA */
2636 DEC_INSTANCE(3, 2), /* AAC */
2637 DEC_INSTANCE(0, 0), /* Reserved */
2638 DEC_INSTANCE(0, 0), /* MIDI */
2639 DEC_INSTANCE(4, 3), /* YADPCM */
2640 DEC_INSTANCE(4, 3), /* QCELP */
2641 DEC_INSTANCE(4, 3), /* AMRNB */
2642 DEC_INSTANCE(1, 1), /* AMRWB/WB+ */
2643 DEC_INSTANCE(4, 3), /* EVRC */
2644 DEC_INSTANCE(1, 1), /* WMAPRO */
2645 },
2646 /* Turbo Mode */
2647 {
2648 DEC_INSTANCE(4, 3), /* WAV */
2649 DEC_INSTANCE(4, 3), /* ADPCM */
2650 DEC_INSTANCE(4, 3), /* MP3 */
2651 DEC_INSTANCE(0, 0), /* Real Audio */
2652 DEC_INSTANCE(4, 3), /* WMA */
2653 DEC_INSTANCE(4, 3), /* AAC */
2654 DEC_INSTANCE(0, 0), /* Reserved */
2655 DEC_INSTANCE(0, 0), /* MIDI */
2656 DEC_INSTANCE(4, 3), /* YADPCM */
2657 DEC_INSTANCE(4, 3), /* QCELP */
2658 DEC_INSTANCE(4, 3), /* AMRNB */
2659 DEC_INSTANCE(2, 3), /* AMRWB/WB+ */
2660 DEC_INSTANCE(4, 3), /* EVRC */
2661 DEC_INSTANCE(1, 2), /* WMAPRO */
2662 },
2663};
2664
2665static struct msm_adspdec_database msm_device_adspdec_database = {
2666 .num_dec = ARRAY_SIZE(dec_info_list),
2667 .num_concurrency_support = (ARRAY_SIZE(dec_concurrency_table) / \
2668 ARRAY_SIZE(dec_info_list)),
2669 .dec_concurrency_table = dec_concurrency_table,
2670 .dec_info_list = dec_info_list,
2671 .dec_instance_list = &dec_instance_list[0][0],
2672};
2673
2674static struct platform_device msm_device_adspdec = {
2675 .name = "msm_adspdec",
2676 .id = -1,
2677 .dev = {
2678 .platform_data = &msm_device_adspdec_database
2679 },
2680};
2681
2682static struct resource smc91x_resources[] = {
2683 [0] = {
2684 .start = 0x8A000300,
2685 .end = 0x8A0003ff,
2686 .flags = IORESOURCE_MEM,
2687 },
2688 [1] = {
2689 .start = MSM_GPIO_TO_INT(156),
2690 .end = MSM_GPIO_TO_INT(156),
2691 .flags = IORESOURCE_IRQ,
2692 },
2693};
2694
2695static struct platform_device smc91x_device = {
2696 .name = "smc91x",
2697 .id = 0,
2698 .num_resources = ARRAY_SIZE(smc91x_resources),
2699 .resource = smc91x_resources,
2700};
2701
2702static struct smsc911x_platform_config smsc911x_config = {
2703 .phy_interface = PHY_INTERFACE_MODE_MII,
2704 .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
2705 .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL,
2706 .flags = SMSC911X_USE_32BIT,
2707};
2708
2709static struct resource smsc911x_resources[] = {
2710 [0] = {
2711 .start = 0x8D000000,
2712 .end = 0x8D000100,
2713 .flags = IORESOURCE_MEM,
2714 },
2715 [1] = {
2716 .start = MSM_GPIO_TO_INT(88),
2717 .end = MSM_GPIO_TO_INT(88),
2718 .flags = IORESOURCE_IRQ,
2719 },
2720};
2721
2722static struct platform_device smsc911x_device = {
2723 .name = "smsc911x",
2724 .id = -1,
2725 .num_resources = ARRAY_SIZE(smsc911x_resources),
2726 .resource = smsc911x_resources,
2727 .dev = {
2728 .platform_data = &smsc911x_config,
2729 },
2730};
2731
2732static struct msm_gpio smsc911x_gpios[] = {
2733 { GPIO_CFG(172, 2, GPIO_CFG_OUTPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA), "ebi2_addr6" },
2734 { GPIO_CFG(173, 2, GPIO_CFG_OUTPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA), "ebi2_addr5" },
2735 { GPIO_CFG(174, 2, GPIO_CFG_OUTPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA), "ebi2_addr4" },
2736 { GPIO_CFG(175, 2, GPIO_CFG_OUTPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA), "ebi2_addr3" },
2737 { GPIO_CFG(176, 2, GPIO_CFG_OUTPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA), "ebi2_addr2" },
2738 { GPIO_CFG(177, 2, GPIO_CFG_OUTPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA), "ebi2_addr1" },
2739 { GPIO_CFG(178, 2, GPIO_CFG_OUTPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA), "ebi2_addr0" },
2740 { GPIO_CFG(88, 2, GPIO_CFG_INPUT, GPIO_CFG_PULL_UP, GPIO_CFG_2MA), "smsc911x_irq" },
2741};
2742
2743static void msm7x30_cfg_smsc911x(void)
2744{
2745 int rc;
2746
2747 rc = msm_gpios_request_enable(smsc911x_gpios,
2748 ARRAY_SIZE(smsc911x_gpios));
2749 if (rc)
2750 pr_err("%s: unable to enable gpios\n", __func__);
2751}
2752
2753#ifdef CONFIG_USB_G_ANDROID
2754static struct android_usb_platform_data android_usb_pdata = {
2755 .update_pid_and_serial_num = usb_diag_update_pid_and_serial_num,
2756};
2757
2758static struct platform_device android_usb_device = {
2759 .name = "android_usb",
2760 .id = -1,
2761 .dev = {
2762 .platform_data = &android_usb_pdata,
2763 },
2764};
2765#endif
2766
2767static struct msm_gpio optnav_config_data[] = {
2768 { GPIO_CFG(OPTNAV_CHIP_SELECT, 0, GPIO_CFG_OUTPUT, GPIO_CFG_PULL_UP, GPIO_CFG_8MA),
2769 "optnav_chip_select" },
2770};
2771
2772static void __iomem *virtual_optnav;
2773
2774static int optnav_gpio_setup(void)
2775{
2776 int rc = -ENODEV;
2777 rc = msm_gpios_request_enable(optnav_config_data,
2778 ARRAY_SIZE(optnav_config_data));
2779
2780 /* Configure the FPGA for GPIOs */
2781 virtual_optnav = ioremap(FPGA_OPTNAV_GPIO_ADDR, 0x4);
2782 if (!virtual_optnav) {
2783 pr_err("%s:Could not ioremap region\n", __func__);
2784 return -ENOMEM;
2785 }
2786 /*
2787 * Configure the FPGA to set GPIO 19 as
2788 * normal, active(enabled), output(MSM to SURF)
2789 */
2790 writew(0x311E, virtual_optnav);
2791 return rc;
2792}
2793
2794static void optnav_gpio_release(void)
2795{
2796 msm_gpios_disable_free(optnav_config_data,
2797 ARRAY_SIZE(optnav_config_data));
2798 iounmap(virtual_optnav);
2799}
2800
2801static struct vreg *vreg_gp7;
2802static struct vreg *vreg_gp4;
2803static struct vreg *vreg_gp9;
2804static struct vreg *vreg_usb3_3;
2805
2806static int optnav_enable(void)
2807{
2808 int rc;
2809 /*
2810 * Enable the VREGs L8(gp7), L10(gp4), L12(gp9), L6(usb)
2811 * for I2C communication with keyboard.
2812 */
2813 vreg_gp7 = vreg_get(NULL, "gp7");
2814 rc = vreg_set_level(vreg_gp7, 1800);
2815 if (rc) {
2816 pr_err("%s: vreg_set_level failed \n", __func__);
2817 goto fail_vreg_gp7;
2818 }
2819
2820 rc = vreg_enable(vreg_gp7);
2821 if (rc) {
2822 pr_err("%s: vreg_enable failed \n", __func__);
2823 goto fail_vreg_gp7;
2824 }
2825
2826 vreg_gp4 = vreg_get(NULL, "gp4");
2827 rc = vreg_set_level(vreg_gp4, 2600);
2828 if (rc) {
2829 pr_err("%s: vreg_set_level failed \n", __func__);
2830 goto fail_vreg_gp4;
2831 }
2832
2833 rc = vreg_enable(vreg_gp4);
2834 if (rc) {
2835 pr_err("%s: vreg_enable failed \n", __func__);
2836 goto fail_vreg_gp4;
2837 }
2838
2839 vreg_gp9 = vreg_get(NULL, "gp9");
2840 rc = vreg_set_level(vreg_gp9, 1800);
2841 if (rc) {
2842 pr_err("%s: vreg_set_level failed \n", __func__);
2843 goto fail_vreg_gp9;
2844 }
2845
2846 rc = vreg_enable(vreg_gp9);
2847 if (rc) {
2848 pr_err("%s: vreg_enable failed \n", __func__);
2849 goto fail_vreg_gp9;
2850 }
2851
2852 vreg_usb3_3 = vreg_get(NULL, "usb");
2853 rc = vreg_set_level(vreg_usb3_3, 3300);
2854 if (rc) {
2855 pr_err("%s: vreg_set_level failed \n", __func__);
2856 goto fail_vreg_3_3;
2857 }
2858
2859 rc = vreg_enable(vreg_usb3_3);
2860 if (rc) {
2861 pr_err("%s: vreg_enable failed \n", __func__);
2862 goto fail_vreg_3_3;
2863 }
2864
2865 /* Enable the chip select GPIO */
2866 gpio_set_value(OPTNAV_CHIP_SELECT, 1);
2867 gpio_set_value(OPTNAV_CHIP_SELECT, 0);
2868
2869 return 0;
2870
2871fail_vreg_3_3:
2872 vreg_disable(vreg_gp9);
2873fail_vreg_gp9:
2874 vreg_disable(vreg_gp4);
2875fail_vreg_gp4:
2876 vreg_disable(vreg_gp7);
2877fail_vreg_gp7:
2878 return rc;
2879}
2880
2881static void optnav_disable(void)
2882{
2883 vreg_disable(vreg_usb3_3);
2884 vreg_disable(vreg_gp9);
2885 vreg_disable(vreg_gp4);
2886 vreg_disable(vreg_gp7);
2887
2888 gpio_set_value(OPTNAV_CHIP_SELECT, 1);
2889}
2890
2891static struct ofn_atlab_platform_data optnav_data = {
2892 .gpio_setup = optnav_gpio_setup,
2893 .gpio_release = optnav_gpio_release,
2894 .optnav_on = optnav_enable,
2895 .optnav_off = optnav_disable,
2896 .rotate_xy = 0,
2897 .function1 = {
2898 .no_motion1_en = true,
2899 .touch_sensor_en = true,
2900 .ofn_en = true,
2901 .clock_select_khz = 1500,
2902 .cpi_selection = 1200,
2903 },
2904 .function2 = {
2905 .invert_y = false,
2906 .invert_x = true,
2907 .swap_x_y = false,
2908 .hold_a_b_en = true,
2909 .motion_filter_en = true,
2910 },
2911};
2912
2913static int hdmi_comm_power(int on, int show);
2914static int hdmi_init_irq(void);
2915static int hdmi_enable_5v(int on);
2916static int hdmi_core_power(int on, int show);
2917static int hdmi_cec_power(int on);
2918static bool hdmi_check_hdcp_hw_support(void);
2919
2920static struct msm_hdmi_platform_data adv7520_hdmi_data = {
2921 .irq = MSM_GPIO_TO_INT(18),
2922 .comm_power = hdmi_comm_power,
2923 .init_irq = hdmi_init_irq,
2924 .enable_5v = hdmi_enable_5v,
2925 .core_power = hdmi_core_power,
2926 .cec_power = hdmi_cec_power,
2927 .check_hdcp_hw_support = hdmi_check_hdcp_hw_support,
2928};
2929
2930#ifdef CONFIG_BOSCH_BMA150
2931static struct vreg *vreg_gp6;
2932static int sensors_ldo_enable(void)
2933{
2934 int rc;
2935
2936 /*
2937 * Enable the VREGs L8(gp7), L15(gp6)
2938 * for I2C communication with sensors.
2939 */
2940 pr_info("sensors_ldo_enable called!!\n");
2941 vreg_gp7 = vreg_get(NULL, "gp7");
2942 if (IS_ERR(vreg_gp7)) {
2943 pr_err("%s: vreg_get gp7 failed\n", __func__);
2944 rc = PTR_ERR(vreg_gp7);
2945 goto fail_gp7_get;
2946 }
2947
2948 rc = vreg_set_level(vreg_gp7, 1800);
2949 if (rc) {
2950 pr_err("%s: vreg_set_level gp7 failed\n", __func__);
2951 goto fail_gp7_level;
2952 }
2953
2954 rc = vreg_enable(vreg_gp7);
2955 if (rc) {
2956 pr_err("%s: vreg_enable gp7 failed\n", __func__);
2957 goto fail_gp7_level;
2958 }
2959
2960 vreg_gp6 = vreg_get(NULL, "gp6");
2961 if (IS_ERR(vreg_gp6)) {
2962 pr_err("%s: vreg_get gp6 failed\n", __func__);
2963 rc = PTR_ERR(vreg_gp6);
2964 goto fail_gp6_get;
2965 }
2966
2967 rc = vreg_set_level(vreg_gp6, 3050);
2968 if (rc) {
2969 pr_err("%s: vreg_set_level gp6 failed\n", __func__);
2970 goto fail_gp6_level;
2971 }
2972
2973 rc = vreg_enable(vreg_gp6);
2974 if (rc) {
2975 pr_err("%s: vreg_enable gp6 failed\n", __func__);
2976 goto fail_gp6_level;
2977 }
2978
2979 return 0;
2980
2981fail_gp6_level:
2982 vreg_put(vreg_gp6);
2983fail_gp6_get:
2984 vreg_disable(vreg_gp7);
2985fail_gp7_level:
2986 vreg_put(vreg_gp7);
2987fail_gp7_get:
2988 return rc;
2989}
2990
2991static void sensors_ldo_disable(void)
2992{
2993 pr_info("sensors_ldo_disable called!!\n");
2994 vreg_disable(vreg_gp6);
2995 vreg_put(vreg_gp6);
2996 vreg_disable(vreg_gp7);
2997 vreg_put(vreg_gp7);
2998}
2999static struct bma150_platform_data bma150_data = {
3000 .power_on = sensors_ldo_enable,
3001 .power_off = sensors_ldo_disable,
3002};
3003
3004static struct i2c_board_info bma150_board_info[] __initdata = {
3005 {
3006 I2C_BOARD_INFO("bma150", 0x38),
3007 .flags = I2C_CLIENT_WAKE,
3008 .irq = MSM_GPIO_TO_INT(BMA150_GPIO_INT),
3009 .platform_data = &bma150_data,
3010 },
3011};
3012#endif
3013
3014static struct i2c_board_info msm_i2c_board_info[] = {
3015 {
3016 I2C_BOARD_INFO("m33c01", OPTNAV_I2C_SLAVE_ADDR),
3017 .irq = MSM_GPIO_TO_INT(OPTNAV_IRQ),
3018 .platform_data = &optnav_data,
3019 },
3020 {
3021 I2C_BOARD_INFO("adv7520", ADV7520_I2C_ADDR),
3022 .platform_data = &adv7520_hdmi_data,
3023 },
3024};
3025
3026static struct i2c_board_info msm_marimba_board_info[] = {
3027 {
3028 I2C_BOARD_INFO("marimba", 0xc),
3029 .platform_data = &marimba_pdata,
3030 }
3031};
3032
3033
3034static struct msm_handset_platform_data hs_platform_data = {
3035 .hs_name = "7k_handset",
3036 .pwr_key_delay_ms = 500, /* 0 will disable end key */
3037};
3038
3039static struct platform_device hs_device = {
3040 .name = "msm-handset",
3041 .id = -1,
3042 .dev = {
3043 .platform_data = &hs_platform_data,
3044 },
3045};
3046
3047static struct msm_pm_platform_data msm_pm_data[MSM_PM_SLEEP_MODE_NR] = {
3048 [MSM_PM_SLEEP_MODE_POWER_COLLAPSE] = {
3049 .idle_supported = 1,
3050 .suspend_supported = 1,
3051 .idle_enabled = 1,
3052 .suspend_enabled = 1,
3053 .latency = 8594,
3054 .residency = 23740,
3055 },
3056 [MSM_PM_SLEEP_MODE_POWER_COLLAPSE_NO_XO_SHUTDOWN] = {
3057 .idle_supported = 1,
3058 .suspend_supported = 1,
3059 .idle_enabled = 1,
3060 .suspend_enabled = 1,
3061 .latency = 4594,
3062 .residency = 23740,
3063 },
3064 [MSM_PM_SLEEP_MODE_POWER_COLLAPSE_STANDALONE] = {
3065#ifdef CONFIG_MSM_STANDALONE_POWER_COLLAPSE
3066 .idle_supported = 1,
3067 .suspend_supported = 1,
3068 .idle_enabled = 1,
3069 .suspend_enabled = 0,
3070#else /*CONFIG_MSM_STANDALONE_POWER_COLLAPSE*/
3071 .idle_supported = 0,
3072 .suspend_supported = 0,
3073 .idle_enabled = 0,
3074 .suspend_enabled = 0,
3075#endif /*CONFIG_MSM_STANDALONE_POWER_COLLAPSE*/
3076 .latency = 500,
3077 .residency = 6000,
3078 },
3079 [MSM_PM_SLEEP_MODE_RAMP_DOWN_AND_WAIT_FOR_INTERRUPT] = {
3080 .idle_supported = 1,
3081 .suspend_supported = 1,
3082 .idle_enabled = 0,
3083 .suspend_enabled = 1,
3084 .latency = 443,
3085 .residency = 1098,
3086 },
3087 [MSM_PM_SLEEP_MODE_WAIT_FOR_INTERRUPT] = {
3088 .idle_supported = 1,
3089 .suspend_supported = 1,
3090 .idle_enabled = 1,
3091 .suspend_enabled = 1,
3092 .latency = 2,
3093 .residency = 0,
3094 },
3095};
3096
3097static struct resource qsd_spi_resources[] = {
3098 {
3099 .name = "spi_irq_in",
3100 .start = INT_SPI_INPUT,
3101 .end = INT_SPI_INPUT,
3102 .flags = IORESOURCE_IRQ,
3103 },
3104 {
3105 .name = "spi_irq_out",
3106 .start = INT_SPI_OUTPUT,
3107 .end = INT_SPI_OUTPUT,
3108 .flags = IORESOURCE_IRQ,
3109 },
3110 {
3111 .name = "spi_irq_err",
3112 .start = INT_SPI_ERROR,
3113 .end = INT_SPI_ERROR,
3114 .flags = IORESOURCE_IRQ,
3115 },
3116 {
3117 .name = "spi_base",
3118 .start = 0xA8000000,
3119 .end = 0xA8000000 + SZ_4K - 1,
3120 .flags = IORESOURCE_MEM,
3121 },
3122 {
3123 .name = "spidm_channels",
3124 .flags = IORESOURCE_DMA,
3125 },
3126 {
3127 .name = "spidm_crci",
3128 .flags = IORESOURCE_DMA,
3129 },
3130};
3131
3132#define AMDH0_BASE_PHYS 0xAC200000
3133#define ADMH0_GP_CTL (ct_adm_base + 0x3D8)
3134static int msm_qsd_spi_dma_config(void)
3135{
3136 void __iomem *ct_adm_base = 0;
3137 u32 spi_mux = 0;
3138 int ret = 0;
3139
3140 ct_adm_base = ioremap(AMDH0_BASE_PHYS, PAGE_SIZE);
3141 if (!ct_adm_base) {
3142 pr_err("%s: Could not remap %x\n", __func__, AMDH0_BASE_PHYS);
3143 return -ENOMEM;
3144 }
3145
3146 spi_mux = (ioread32(ADMH0_GP_CTL) & (0x3 << 12)) >> 12;
3147
3148 qsd_spi_resources[4].start = DMOV_USB_CHAN;
3149 qsd_spi_resources[4].end = DMOV_TSIF_CHAN;
3150
3151 switch (spi_mux) {
3152 case (1):
3153 qsd_spi_resources[5].start = DMOV_HSUART1_RX_CRCI;
3154 qsd_spi_resources[5].end = DMOV_HSUART1_TX_CRCI;
3155 break;
3156 case (2):
3157 qsd_spi_resources[5].start = DMOV_HSUART2_RX_CRCI;
3158 qsd_spi_resources[5].end = DMOV_HSUART2_TX_CRCI;
3159 break;
3160 case (3):
3161 qsd_spi_resources[5].start = DMOV_CE_OUT_CRCI;
3162 qsd_spi_resources[5].end = DMOV_CE_IN_CRCI;
3163 break;
3164 default:
3165 ret = -ENOENT;
3166 }
3167
3168 iounmap(ct_adm_base);
3169
3170 return ret;
3171}
3172
3173static struct platform_device qsd_device_spi = {
3174 .name = "spi_qsd",
3175 .id = 0,
3176 .num_resources = ARRAY_SIZE(qsd_spi_resources),
3177 .resource = qsd_spi_resources,
3178};
3179
3180#ifdef CONFIG_SPI_QSD
3181static struct spi_board_info lcdc_sharp_spi_board_info[] __initdata = {
3182 {
3183 .modalias = "lcdc_sharp_ls038y7dx01",
3184 .mode = SPI_MODE_1,
3185 .bus_num = 0,
3186 .chip_select = 0,
3187 .max_speed_hz = 26331429,
3188 }
3189};
3190static struct spi_board_info lcdc_toshiba_spi_board_info[] __initdata = {
3191 {
3192 .modalias = "lcdc_toshiba_ltm030dd40",
3193 .mode = SPI_MODE_3|SPI_CS_HIGH,
3194 .bus_num = 0,
3195 .chip_select = 0,
3196 .max_speed_hz = 9963243,
3197 }
3198};
3199#endif
3200
3201static struct msm_gpio qsd_spi_gpio_config_data[] = {
3202 { GPIO_CFG(45, 1, GPIO_CFG_INPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "spi_clk" },
3203 { GPIO_CFG(46, 1, GPIO_CFG_INPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "spi_cs0" },
3204 { GPIO_CFG(47, 1, GPIO_CFG_INPUT, GPIO_CFG_NO_PULL, GPIO_CFG_8MA), "spi_mosi" },
3205 { GPIO_CFG(48, 1, GPIO_CFG_INPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "spi_miso" },
3206};
3207
3208static int msm_qsd_spi_gpio_config(void)
3209{
3210 return msm_gpios_request_enable(qsd_spi_gpio_config_data,
3211 ARRAY_SIZE(qsd_spi_gpio_config_data));
3212}
3213
3214static void msm_qsd_spi_gpio_release(void)
3215{
3216 msm_gpios_disable_free(qsd_spi_gpio_config_data,
3217 ARRAY_SIZE(qsd_spi_gpio_config_data));
3218}
3219
3220static struct msm_spi_platform_data qsd_spi_pdata = {
3221 .max_clock_speed = 26331429,
3222 .gpio_config = msm_qsd_spi_gpio_config,
3223 .gpio_release = msm_qsd_spi_gpio_release,
3224 .dma_config = msm_qsd_spi_dma_config,
3225};
3226
3227static void __init msm_qsd_spi_init(void)
3228{
3229 qsd_device_spi.dev.platform_data = &qsd_spi_pdata;
3230}
3231
3232#ifdef CONFIG_USB_EHCI_MSM_72K
3233static void msm_hsusb_vbus_power(unsigned phy_info, int on)
3234{
3235 int rc;
3236 static int vbus_is_on;
3237 struct pm8058_gpio usb_vbus = {
3238 .direction = PM_GPIO_DIR_OUT,
3239 .pull = PM_GPIO_PULL_NO,
3240 .output_buffer = PM_GPIO_OUT_BUF_CMOS,
3241 .output_value = 1,
3242 .vin_sel = 2,
3243 .out_strength = PM_GPIO_STRENGTH_MED,
3244 .function = PM_GPIO_FUNC_NORMAL,
3245 .inv_int_pol = 0,
3246 };
3247
3248 /* If VBUS is already on (or off), do nothing. */
3249 if (unlikely(on == vbus_is_on))
3250 return;
3251
3252 if (on) {
3253 rc = pm8058_gpio_config(36, &usb_vbus);
3254 if (rc) {
3255 pr_err("%s PMIC GPIO 36 write failed\n", __func__);
3256 return;
3257 }
3258 } else {
3259 gpio_set_value_cansleep(PM8058_GPIO_PM_TO_SYS(36), 0);
3260 }
3261
3262 vbus_is_on = on;
3263}
3264
3265static struct msm_usb_host_platform_data msm_usb_host_pdata = {
3266 .phy_info = (USB_PHY_INTEGRATED | USB_PHY_MODEL_45NM),
3267 .vbus_power = msm_hsusb_vbus_power,
3268 .power_budget = 180,
3269};
3270#endif
3271
3272#ifdef CONFIG_USB_MSM_OTG_72K
3273static int hsusb_rpc_connect(int connect)
3274{
3275 if (connect)
3276 return msm_hsusb_rpc_connect();
3277 else
3278 return msm_hsusb_rpc_close();
3279}
3280#endif
3281
3282#ifdef CONFIG_USB_MSM_OTG_72K
3283static struct vreg *vreg_3p3;
3284static int msm_hsusb_ldo_init(int init)
3285{
3286 uint32_t version = 0;
3287 int def_vol = 3400;
3288
3289 version = socinfo_get_version();
3290
3291 if (SOCINFO_VERSION_MAJOR(version) >= 2 &&
3292 SOCINFO_VERSION_MINOR(version) >= 1) {
3293 def_vol = 3075;
3294 pr_debug("%s: default voltage:%d\n", __func__, def_vol);
3295 }
3296
3297 if (init) {
3298 vreg_3p3 = vreg_get(NULL, "usb");
3299 if (IS_ERR(vreg_3p3))
3300 return PTR_ERR(vreg_3p3);
3301 vreg_set_level(vreg_3p3, def_vol);
3302 } else
3303 vreg_put(vreg_3p3);
3304
3305 return 0;
3306}
3307
3308static int msm_hsusb_ldo_enable(int enable)
3309{
3310 static int ldo_status;
3311
3312 if (!vreg_3p3 || IS_ERR(vreg_3p3))
3313 return -ENODEV;
3314
3315 if (ldo_status == enable)
3316 return 0;
3317
3318 ldo_status = enable;
3319
3320 if (enable)
3321 return vreg_enable(vreg_3p3);
3322
3323 return vreg_disable(vreg_3p3);
3324}
3325
3326static int msm_hsusb_ldo_set_voltage(int mV)
3327{
3328 static int cur_voltage = 3400;
3329
3330 if (!vreg_3p3 || IS_ERR(vreg_3p3))
3331 return -ENODEV;
3332
3333 if (cur_voltage == mV)
3334 return 0;
3335
3336 cur_voltage = mV;
3337
3338 pr_debug("%s: (%d)\n", __func__, mV);
3339
3340 return vreg_set_level(vreg_3p3, mV);
3341}
3342#endif
3343
3344#ifndef CONFIG_USB_EHCI_MSM_72K
3345static int msm_hsusb_pmic_notif_init(void (*callback)(int online), int init);
3346#endif
3347static struct msm_otg_platform_data msm_otg_pdata = {
3348 .rpc_connect = hsusb_rpc_connect,
3349
3350#ifndef CONFIG_USB_EHCI_MSM_72K
3351 .pmic_vbus_notif_init = msm_hsusb_pmic_notif_init,
3352#else
3353 .vbus_power = msm_hsusb_vbus_power,
3354#endif
3355 .core_clk = 1,
3356 .pemp_level = PRE_EMPHASIS_WITH_20_PERCENT,
3357 .cdr_autoreset = CDR_AUTO_RESET_DISABLE,
3358 .drv_ampl = HS_DRV_AMPLITUDE_DEFAULT,
3359 .se1_gating = SE1_GATING_DISABLE,
3360 .chg_vbus_draw = hsusb_chg_vbus_draw,
3361 .chg_connected = hsusb_chg_connected,
3362 .chg_init = hsusb_chg_init,
3363 .ldo_enable = msm_hsusb_ldo_enable,
3364 .ldo_init = msm_hsusb_ldo_init,
3365 .ldo_set_voltage = msm_hsusb_ldo_set_voltage,
3366};
3367
3368#ifdef CONFIG_USB_GADGET
3369static struct msm_hsusb_gadget_platform_data msm_gadget_pdata = {
3370 .is_phy_status_timer_on = 1,
3371};
3372#endif
3373#ifndef CONFIG_USB_EHCI_MSM_72K
3374typedef void (*notify_vbus_state) (int);
3375notify_vbus_state notify_vbus_state_func_ptr;
3376int vbus_on_irq;
3377static irqreturn_t pmic_vbus_on_irq(int irq, void *data)
3378{
3379 pr_info("%s: vbus notification from pmic\n", __func__);
3380
3381 (*notify_vbus_state_func_ptr) (1);
3382
3383 return IRQ_HANDLED;
3384}
3385static int msm_hsusb_pmic_notif_init(void (*callback)(int online), int init)
3386{
3387 int ret;
3388
3389 if (init) {
3390 if (!callback)
3391 return -ENODEV;
3392
3393 notify_vbus_state_func_ptr = callback;
3394 vbus_on_irq = platform_get_irq_byname(&msm_device_otg,
3395 "vbus_on");
3396 if (vbus_on_irq <= 0) {
3397 pr_err("%s: unable to get vbus on irq\n", __func__);
3398 return -ENODEV;
3399 }
3400
3401 ret = request_any_context_irq(vbus_on_irq, pmic_vbus_on_irq,
3402 IRQF_TRIGGER_RISING, "msm_otg_vbus_on", NULL);
3403 if (ret < 0) {
3404 pr_info("%s: request_irq for vbus_on"
3405 "interrupt failed\n", __func__);
3406 return ret;
3407 }
3408 msm_otg_pdata.pmic_vbus_irq = vbus_on_irq;
3409 return 0;
3410 } else {
3411 free_irq(vbus_on_irq, 0);
3412 notify_vbus_state_func_ptr = NULL;
3413 return 0;
3414 }
3415}
3416#endif
3417
3418static struct android_pmem_platform_data android_pmem_pdata = {
3419 .name = "pmem",
3420 .allocator_type = PMEM_ALLOCATORTYPE_ALLORNOTHING,
3421 .cached = 1,
3422 .memory_type = MEMTYPE_EBI0,
3423};
3424
3425static struct platform_device android_pmem_device = {
3426 .name = "android_pmem",
3427 .id = 0,
3428 .dev = { .platform_data = &android_pmem_pdata },
3429};
3430
3431#ifndef CONFIG_SPI_QSD
3432static int lcdc_gpio_array_num[] = {
3433 45, /* spi_clk */
3434 46, /* spi_cs */
3435 47, /* spi_mosi */
3436 48, /* spi_miso */
3437 };
3438
3439static struct msm_gpio lcdc_gpio_config_data[] = {
3440 { GPIO_CFG(45, 0, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "spi_clk" },
3441 { GPIO_CFG(46, 0, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "spi_cs0" },
3442 { GPIO_CFG(47, 0, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "spi_mosi" },
3443 { GPIO_CFG(48, 0, GPIO_CFG_INPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "spi_miso" },
3444};
3445
3446static void lcdc_config_gpios(int enable)
3447{
3448 if (enable) {
3449 msm_gpios_request_enable(lcdc_gpio_config_data,
3450 ARRAY_SIZE(
3451 lcdc_gpio_config_data));
3452 } else
3453 msm_gpios_disable_free(lcdc_gpio_config_data,
3454 ARRAY_SIZE(
3455 lcdc_gpio_config_data));
3456}
3457#endif
3458
3459static struct msm_panel_common_pdata lcdc_sharp_panel_data = {
3460#ifndef CONFIG_SPI_QSD
3461 .panel_config_gpio = lcdc_config_gpios,
3462 .gpio_num = lcdc_gpio_array_num,
3463#endif
3464 .gpio = 2, /* LPG PMIC_GPIO26 channel number */
3465};
3466
3467static struct platform_device lcdc_sharp_panel_device = {
3468 .name = "lcdc_sharp_wvga",
3469 .id = 0,
3470 .dev = {
3471 .platform_data = &lcdc_sharp_panel_data,
3472 }
3473};
3474
3475static struct msm_gpio dtv_panel_irq_gpios[] = {
3476 { GPIO_CFG(18, 0, GPIO_CFG_INPUT, GPIO_CFG_NO_PULL, GPIO_CFG_4MA),
3477 "hdmi_int" },
3478};
3479
3480static struct msm_gpio dtv_panel_gpios[] = {
3481 { GPIO_CFG(120, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_4MA), "wca_mclk" },
3482 { GPIO_CFG(121, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_4MA), "wca_sd0" },
3483 { GPIO_CFG(122, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_4MA), "wca_sd1" },
3484 { GPIO_CFG(123, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_4MA), "wca_sd2" },
3485 { GPIO_CFG(124, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_8MA), "dtv_pclk" },
3486 { GPIO_CFG(125, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_4MA), "dtv_en" },
3487 { GPIO_CFG(126, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_4MA), "dtv_vsync" },
3488 { GPIO_CFG(127, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_4MA), "dtv_hsync" },
3489 { GPIO_CFG(128, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_4MA), "dtv_data0" },
3490 { GPIO_CFG(129, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_4MA), "dtv_data1" },
3491 { GPIO_CFG(130, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_4MA), "dtv_data2" },
3492 { GPIO_CFG(131, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_4MA), "dtv_data3" },
3493 { GPIO_CFG(132, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_4MA), "dtv_data4" },
3494 { GPIO_CFG(160, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_4MA), "dtv_data5" },
3495 { GPIO_CFG(161, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_4MA), "dtv_data6" },
3496 { GPIO_CFG(162, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_4MA), "dtv_data7" },
3497 { GPIO_CFG(163, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_4MA), "dtv_data8" },
3498 { GPIO_CFG(164, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_4MA), "dtv_data9" },
3499 { GPIO_CFG(165, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_4MA), "dtv_dat10" },
3500 { GPIO_CFG(166, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_4MA), "dtv_dat11" },
3501 { GPIO_CFG(167, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_4MA), "dtv_dat12" },
3502 { GPIO_CFG(168, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_4MA), "dtv_dat13" },
3503 { GPIO_CFG(169, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_4MA), "dtv_dat14" },
3504 { GPIO_CFG(170, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_4MA), "dtv_dat15" },
3505 { GPIO_CFG(171, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_4MA), "dtv_dat16" },
3506 { GPIO_CFG(172, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_4MA), "dtv_dat17" },
3507 { GPIO_CFG(173, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_4MA), "dtv_dat18" },
3508 { GPIO_CFG(174, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_4MA), "dtv_dat19" },
3509 { GPIO_CFG(175, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_4MA), "dtv_dat20" },
3510 { GPIO_CFG(176, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_4MA), "dtv_dat21" },
3511 { GPIO_CFG(177, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_4MA), "dtv_dat22" },
3512 { GPIO_CFG(178, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_4MA), "dtv_dat23" },
3513};
3514
3515
3516#ifdef HDMI_RESET
3517static unsigned dtv_reset_gpio =
3518 GPIO_CFG(37, 0, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA);
3519#endif
3520
3521static int gpio_set(const char *label, const char *name, int level, int on)
3522{
3523 struct vreg *vreg = vreg_get(NULL, label);
3524 int rc;
3525
3526 if (IS_ERR(vreg)) {
3527 rc = PTR_ERR(vreg);
3528 pr_err("%s: vreg %s get failed (%d)\n",
3529 __func__, name, rc);
3530 return rc;
3531 }
3532
3533 rc = vreg_set_level(vreg, level);
3534 if (rc) {
3535 pr_err("%s: vreg %s set level failed (%d)\n",
3536 __func__, name, rc);
3537 return rc;
3538 }
3539
3540 if (on)
3541 rc = vreg_enable(vreg);
3542 else
3543 rc = vreg_disable(vreg);
3544 if (rc)
3545 pr_err("%s: vreg %s enable failed (%d)\n",
3546 __func__, name, rc);
3547 return rc;
3548}
3549
3550#if defined(CONFIG_FB_MSM_HDMI_ADV7520_PANEL) || defined(CONFIG_BOSCH_BMA150)
3551/* there is an i2c address conflict between adv7520 and bma150 sensor after
3552 * power up on fluid. As a solution, the default address of adv7520's packet
3553 * memory is changed as soon as possible
3554 */
3555static int __init fluid_i2c_address_fixup(void)
3556{
3557 unsigned char wBuff[16];
3558 unsigned char rBuff[16];
3559 struct i2c_msg msgs[3];
3560 int res;
3561 int rc = -EINVAL;
3562 struct vreg *vreg_ldo8;
3563 struct i2c_adapter *adapter;
3564
3565 if (machine_is_msm7x30_fluid()) {
3566 adapter = i2c_get_adapter(0);
3567 if (!adapter) {
3568 pr_err("%s: invalid i2c adapter\n", __func__);
3569 return PTR_ERR(adapter);
3570 }
3571
3572 /* turn on LDO8 */
3573 vreg_ldo8 = vreg_get(NULL, "gp7");
3574 if (!vreg_ldo8) {
3575 pr_err("%s: VREG L8 get failed\n", __func__);
3576 goto adapter_put;
3577 }
3578
3579 rc = vreg_set_level(vreg_ldo8, 1800);
3580 if (rc) {
3581 pr_err("%s: VREG L8 set failed\n", __func__);
3582 goto ldo8_put;
3583 }
3584
3585 rc = vreg_enable(vreg_ldo8);
3586 if (rc) {
3587 pr_err("%s: VREG L8 enable failed\n", __func__);
3588 goto ldo8_put;
3589 }
3590
3591 /* change packet memory address to 0x74 */
3592 wBuff[0] = 0x45;
3593 wBuff[1] = 0x74;
3594
3595 msgs[0].addr = ADV7520_I2C_ADDR;
3596 msgs[0].flags = 0;
3597 msgs[0].buf = (unsigned char *) wBuff;
3598 msgs[0].len = 2;
3599
3600 res = i2c_transfer(adapter, msgs, 1);
3601 if (res != 1) {
3602 pr_err("%s: error writing adv7520\n", __func__);
3603 goto ldo8_disable;
3604 }
3605
3606 /* powerdown adv7520 using bit 6 */
3607 /* i2c read first */
3608 wBuff[0] = 0x41;
3609
3610 msgs[0].addr = ADV7520_I2C_ADDR;
3611 msgs[0].flags = 0;
3612 msgs[0].buf = (unsigned char *) wBuff;
3613 msgs[0].len = 1;
3614
3615 msgs[1].addr = ADV7520_I2C_ADDR;
3616 msgs[1].flags = I2C_M_RD;
3617 msgs[1].buf = rBuff;
3618 msgs[1].len = 1;
3619 res = i2c_transfer(adapter, msgs, 2);
3620 if (res != 2) {
3621 pr_err("%s: error reading adv7520\n", __func__);
3622 goto ldo8_disable;
3623 }
3624
3625 /* i2c write back */
3626 wBuff[0] = 0x41;
3627 wBuff[1] = rBuff[0] | 0x40;
3628
3629 msgs[0].addr = ADV7520_I2C_ADDR;
3630 msgs[0].flags = 0;
3631 msgs[0].buf = (unsigned char *) wBuff;
3632 msgs[0].len = 2;
3633
3634 res = i2c_transfer(adapter, msgs, 1);
3635 if (res != 1) {
3636 pr_err("%s: error writing adv7520\n", __func__);
3637 goto ldo8_disable;
3638 }
3639
3640 /* for successful fixup, we release the i2c adapter */
3641 /* but leave ldo8 on so that the adv7520 is not repowered */
3642 i2c_put_adapter(adapter);
3643 pr_info("%s: fluid i2c address conflict resolved\n", __func__);
3644 }
3645 return 0;
3646
3647ldo8_disable:
3648 vreg_disable(vreg_ldo8);
3649ldo8_put:
3650 vreg_put(vreg_ldo8);
3651adapter_put:
3652 i2c_put_adapter(adapter);
3653 return rc;
3654}
3655fs_initcall_sync(fluid_i2c_address_fixup);
3656#endif
3657
3658static int hdmi_comm_power(int on, int show)
3659{
3660 int rc = gpio_set("gp7", "LDO8", 1800, on);
3661 if (rc) {
3662 pr_warning("hdmi_comm_power: LDO8 gpio failed: rc=%d\n", rc);
3663 return rc;
3664 }
3665 rc = gpio_set("gp4", "LDO10", 2600, on);
3666 if (rc)
3667 pr_warning("hdmi_comm_power: LDO10 gpio failed: rc=%d\n", rc);
3668 if (show)
3669 pr_info("%s: i2c comm: %d <LDO8+LDO10>\n", __func__, on);
3670 return rc;
3671}
3672
3673static int hdmi_init_irq(void)
3674{
3675 int rc = msm_gpios_enable(dtv_panel_irq_gpios,
3676 ARRAY_SIZE(dtv_panel_irq_gpios));
3677 if (rc < 0) {
3678 pr_err("%s: gpio enable failed: %d\n", __func__, rc);
3679 return rc;
3680 }
3681 pr_info("%s\n", __func__);
3682
3683 return 0;
3684}
3685
3686static int hdmi_enable_5v(int on)
3687{
3688 int pmic_gpio_hdmi_5v_en ;
3689
3690 if (machine_is_msm8x55_svlte_surf() || machine_is_msm8x55_svlte_ffa() ||
3691 machine_is_msm7x30_fluid())
3692 pmic_gpio_hdmi_5v_en = PMIC_GPIO_HDMI_5V_EN_V2 ;
3693 else
3694 pmic_gpio_hdmi_5v_en = PMIC_GPIO_HDMI_5V_EN_V3 ;
3695
3696 pr_info("%s: %d\n", __func__, on);
3697 if (on) {
3698 int rc;
3699 rc = gpio_request(PM8058_GPIO_PM_TO_SYS(pmic_gpio_hdmi_5v_en),
3700 "hdmi_5V_en");
3701 if (rc) {
3702 pr_err("%s PMIC_GPIO_HDMI_5V_EN gpio_request failed\n",
3703 __func__);
3704 return rc;
3705 }
3706 gpio_set_value_cansleep(
3707 PM8058_GPIO_PM_TO_SYS(pmic_gpio_hdmi_5v_en), 1);
3708 } else {
3709 gpio_set_value_cansleep(
3710 PM8058_GPIO_PM_TO_SYS(pmic_gpio_hdmi_5v_en), 0);
3711 gpio_free(PM8058_GPIO_PM_TO_SYS(pmic_gpio_hdmi_5v_en));
3712 }
3713 return 0;
3714}
3715
3716static int hdmi_core_power(int on, int show)
3717{
3718 if (show)
3719 pr_info("%s: %d <LDO8>\n", __func__, on);
3720 return gpio_set("gp7", "LDO8", 1800, on);
3721}
3722
3723static int hdmi_cec_power(int on)
3724{
3725 pr_info("%s: %d <LDO17>\n", __func__, on);
3726 return gpio_set("gp11", "LDO17", 2600, on);
3727}
3728
3729static bool hdmi_check_hdcp_hw_support(void)
3730{
3731 if (machine_is_msm7x30_fluid())
3732 return false;
3733 else
3734 return true;
3735}
3736
3737static int dtv_panel_power(int on)
3738{
3739 int flag_on = !!on;
3740 static int dtv_power_save_on;
3741 int rc;
3742
3743 if (dtv_power_save_on == flag_on)
3744 return 0;
3745
3746 dtv_power_save_on = flag_on;
3747 pr_info("%s: %d\n", __func__, on);
3748
3749#ifdef HDMI_RESET
3750 if (on) {
3751 /* reset Toshiba WeGA chip -- toggle reset pin -- gpio_180 */
3752 rc = gpio_tlmm_config(dtv_reset_gpio, GPIO_CFG_ENABLE);
3753 if (rc) {
3754 pr_err("%s: gpio_tlmm_config(%#x)=%d\n",
3755 __func__, dtv_reset_gpio, rc);
3756 return rc;
3757 }
3758
3759 /* bring reset line low to hold reset*/
3760 gpio_set_value(37, 0);
3761 }
3762#endif
3763
3764 if (on) {
3765 rc = msm_gpios_enable(dtv_panel_gpios,
3766 ARRAY_SIZE(dtv_panel_gpios));
3767 if (rc < 0) {
3768 printk(KERN_ERR "%s: gpio enable failed: %d\n",
3769 __func__, rc);
3770 return rc;
3771 }
3772 } else {
3773 rc = msm_gpios_disable(dtv_panel_gpios,
3774 ARRAY_SIZE(dtv_panel_gpios));
3775 if (rc < 0) {
3776 printk(KERN_ERR "%s: gpio disable failed: %d\n",
3777 __func__, rc);
3778 return rc;
3779 }
3780 }
3781
3782 mdelay(5); /* ensure power is stable */
3783
3784#ifdef HDMI_RESET
3785 if (on) {
3786 gpio_set_value(37, 1); /* bring reset line high */
3787 mdelay(10); /* 10 msec before IO can be accessed */
3788 }
3789#endif
3790
3791 return rc;
3792}
3793
3794static struct lcdc_platform_data dtv_pdata = {
3795 .lcdc_power_save = dtv_panel_power,
3796};
3797
3798static struct msm_serial_hs_platform_data msm_uart_dm1_pdata = {
3799 .inject_rx_on_wakeup = 1,
3800 .rx_to_inject = 0xFD,
3801};
3802
3803static struct resource msm_fb_resources[] = {
3804 {
3805 .flags = IORESOURCE_DMA,
3806 }
3807};
3808
3809static int msm_fb_detect_panel(const char *name)
3810{
3811 if (machine_is_msm7x30_fluid()) {
3812 if (!strcmp(name, "lcdc_sharp_wvga_pt"))
3813 return 0;
3814 } else {
3815 if (!strncmp(name, "mddi_toshiba_wvga_pt", 20))
3816 return -EPERM;
3817 else if (!strncmp(name, "lcdc_toshiba_wvga_pt", 20))
3818 return 0;
3819 else if (!strcmp(name, "mddi_orise"))
3820 return -EPERM;
3821 else if (!strcmp(name, "mddi_quickvx"))
3822 return -EPERM;
3823 }
3824 return -ENODEV;
3825}
3826
3827static struct msm_fb_platform_data msm_fb_pdata = {
3828 .detect_client = msm_fb_detect_panel,
3829 .mddi_prescan = 1,
3830};
3831
3832static struct platform_device msm_fb_device = {
3833 .name = "msm_fb",
3834 .id = 0,
3835 .num_resources = ARRAY_SIZE(msm_fb_resources),
3836 .resource = msm_fb_resources,
3837 .dev = {
3838 .platform_data = &msm_fb_pdata,
3839 }
3840};
3841
3842static struct platform_device msm_migrate_pages_device = {
3843 .name = "msm_migrate_pages",
3844 .id = -1,
3845};
3846
3847static struct android_pmem_platform_data android_pmem_adsp_pdata = {
3848 .name = "pmem_adsp",
3849 .allocator_type = PMEM_ALLOCATORTYPE_BITMAP,
3850 .cached = 0,
3851 .memory_type = MEMTYPE_EBI0,
3852};
3853
3854static struct android_pmem_platform_data android_pmem_audio_pdata = {
3855 .name = "pmem_audio",
3856 .allocator_type = PMEM_ALLOCATORTYPE_BITMAP,
3857 .cached = 0,
3858 .memory_type = MEMTYPE_EBI0,
3859};
3860
3861static struct platform_device android_pmem_adsp_device = {
3862 .name = "android_pmem",
3863 .id = 2,
3864 .dev = { .platform_data = &android_pmem_adsp_pdata },
3865};
3866
3867static struct platform_device android_pmem_audio_device = {
3868 .name = "android_pmem",
3869 .id = 4,
3870 .dev = { .platform_data = &android_pmem_audio_pdata },
3871};
3872
3873#if defined(CONFIG_CRYPTO_DEV_QCRYPTO) || \
3874 defined(CONFIG_CRYPTO_DEV_QCRYPTO_MODULE) || \
3875 defined(CONFIG_CRYPTO_DEV_QCEDEV) || \
3876 defined(CONFIG_CRYPTO_DEV_QCEDEV_MODULE)
3877
3878#define QCE_SIZE 0x10000
3879#define QCE_0_BASE 0xA8400000
3880
3881#define QCE_HW_KEY_SUPPORT 1
3882#define QCE_SHA_HMAC_SUPPORT 0
3883#define QCE_SHARE_CE_RESOURCE 0
3884#define QCE_CE_SHARED 0
3885
3886static struct resource qcrypto_resources[] = {
3887 [0] = {
3888 .start = QCE_0_BASE,
3889 .end = QCE_0_BASE + QCE_SIZE - 1,
3890 .flags = IORESOURCE_MEM,
3891 },
3892 [1] = {
3893 .name = "crypto_channels",
3894 .start = DMOV_CE_IN_CHAN,
3895 .end = DMOV_CE_OUT_CHAN,
3896 .flags = IORESOURCE_DMA,
3897 },
3898 [2] = {
3899 .name = "crypto_crci_in",
3900 .start = DMOV_CE_IN_CRCI,
3901 .end = DMOV_CE_IN_CRCI,
3902 .flags = IORESOURCE_DMA,
3903 },
3904 [3] = {
3905 .name = "crypto_crci_out",
3906 .start = DMOV_CE_OUT_CRCI,
3907 .end = DMOV_CE_OUT_CRCI,
3908 .flags = IORESOURCE_DMA,
3909 },
3910 [4] = {
3911 .name = "crypto_crci_hash",
3912 .start = DMOV_CE_HASH_CRCI,
3913 .end = DMOV_CE_HASH_CRCI,
3914 .flags = IORESOURCE_DMA,
3915 },
3916};
3917
3918static struct resource qcedev_resources[] = {
3919 [0] = {
3920 .start = QCE_0_BASE,
3921 .end = QCE_0_BASE + QCE_SIZE - 1,
3922 .flags = IORESOURCE_MEM,
3923 },
3924 [1] = {
3925 .name = "crypto_channels",
3926 .start = DMOV_CE_IN_CHAN,
3927 .end = DMOV_CE_OUT_CHAN,
3928 .flags = IORESOURCE_DMA,
3929 },
3930 [2] = {
3931 .name = "crypto_crci_in",
3932 .start = DMOV_CE_IN_CRCI,
3933 .end = DMOV_CE_IN_CRCI,
3934 .flags = IORESOURCE_DMA,
3935 },
3936 [3] = {
3937 .name = "crypto_crci_out",
3938 .start = DMOV_CE_OUT_CRCI,
3939 .end = DMOV_CE_OUT_CRCI,
3940 .flags = IORESOURCE_DMA,
3941 },
3942 [4] = {
3943 .name = "crypto_crci_hash",
3944 .start = DMOV_CE_HASH_CRCI,
3945 .end = DMOV_CE_HASH_CRCI,
3946 .flags = IORESOURCE_DMA,
3947 },
3948};
3949
3950#endif
3951
3952#if defined(CONFIG_CRYPTO_DEV_QCRYPTO) || \
3953 defined(CONFIG_CRYPTO_DEV_QCRYPTO_MODULE)
3954
3955static struct msm_ce_hw_support qcrypto_ce_hw_suppport = {
3956 .ce_shared = QCE_CE_SHARED,
3957 .shared_ce_resource = QCE_SHARE_CE_RESOURCE,
3958 .hw_key_support = QCE_HW_KEY_SUPPORT,
3959 .sha_hmac = QCE_SHA_HMAC_SUPPORT,
3960};
3961
3962static struct platform_device qcrypto_device = {
3963 .name = "qcrypto",
3964 .id = 0,
3965 .num_resources = ARRAY_SIZE(qcrypto_resources),
3966 .resource = qcrypto_resources,
3967 .dev = {
3968 .coherent_dma_mask = DMA_BIT_MASK(32),
3969 .platform_data = &qcrypto_ce_hw_suppport,
3970 },
3971};
3972#endif
3973
3974#if defined(CONFIG_CRYPTO_DEV_QCEDEV) || \
3975 defined(CONFIG_CRYPTO_DEV_QCEDEV_MODULE)
3976
3977static struct msm_ce_hw_support qcedev_ce_hw_suppport = {
3978 .ce_shared = QCE_CE_SHARED,
3979 .shared_ce_resource = QCE_SHARE_CE_RESOURCE,
3980 .hw_key_support = QCE_HW_KEY_SUPPORT,
3981 .sha_hmac = QCE_SHA_HMAC_SUPPORT,
3982};
3983static struct platform_device qcedev_device = {
3984 .name = "qce",
3985 .id = 0,
3986 .num_resources = ARRAY_SIZE(qcedev_resources),
3987 .resource = qcedev_resources,
3988 .dev = {
3989 .coherent_dma_mask = DMA_BIT_MASK(32),
3990 .platform_data = &qcedev_ce_hw_suppport,
3991 },
3992};
3993#endif
3994
3995static int mddi_toshiba_pmic_bl(int level)
3996{
3997 int ret = -EPERM;
3998
3999 ret = pmic_set_led_intensity(LED_LCD, level);
4000
4001 if (ret)
4002 printk(KERN_WARNING "%s: can't set lcd backlight!\n",
4003 __func__);
4004 return ret;
4005}
4006
4007static struct msm_panel_common_pdata mddi_toshiba_pdata = {
4008 .pmic_backlight = mddi_toshiba_pmic_bl,
4009};
4010
4011static struct platform_device mddi_toshiba_device = {
4012 .name = "mddi_toshiba",
4013 .id = 0,
4014 .dev = {
4015 .platform_data = &mddi_toshiba_pdata,
4016 }
4017};
4018
4019static unsigned wega_reset_gpio =
4020 GPIO_CFG(180, 0, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA);
4021
4022static struct msm_gpio fluid_vee_reset_gpio[] = {
4023 { GPIO_CFG(20, 0, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "vee_reset" },
4024};
4025
4026static unsigned char quickvx_mddi_client = 1, other_mddi_client = 1;
4027static unsigned char quickvx_ldo_enabled;
4028
4029static unsigned quickvx_vlp_gpio =
4030 GPIO_CFG(97, 0, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA);
4031
4032static struct pm8058_gpio pmic_quickvx_clk_gpio = {
4033 .direction = PM_GPIO_DIR_OUT,
4034 .output_buffer = PM_GPIO_OUT_BUF_CMOS,
4035 .output_value = 1,
4036 .pull = PM_GPIO_PULL_NO,
4037 .vin_sel = PM_GPIO_VIN_S3,
4038 .out_strength = PM_GPIO_STRENGTH_HIGH,
4039 .function = PM_GPIO_FUNC_2,
4040};
4041
4042static int display_common_power(int on)
4043{
4044 int rc = 0, flag_on = !!on;
4045 static int display_common_power_save_on;
4046 struct vreg *vreg_ldo12, *vreg_ldo15 = NULL, *vreg_ldo6;
4047 struct vreg *vreg_ldo20, *vreg_ldo16, *vreg_ldo8 = NULL;
4048
4049 if (display_common_power_save_on == flag_on)
4050 return 0;
4051
4052 display_common_power_save_on = flag_on;
4053
4054 if (on) {
4055 /* reset Toshiba WeGA chip -- toggle reset pin -- gpio_180 */
4056 rc = gpio_tlmm_config(wega_reset_gpio, GPIO_CFG_ENABLE);
4057 if (rc) {
4058 pr_err("%s: gpio_tlmm_config(%#x)=%d\n",
4059 __func__, wega_reset_gpio, rc);
4060 return rc;
4061 }
4062
4063 /* bring reset line low to hold reset*/
4064 gpio_set_value(180, 0);
4065
4066 if (quickvx_mddi_client) {
4067 /* QuickVX chip -- VLP pin -- gpio 97 */
4068 rc = gpio_tlmm_config(quickvx_vlp_gpio,
4069 GPIO_CFG_ENABLE);
4070 if (rc) {
4071 pr_err("%s: gpio_tlmm_config(%#x)=%d\n",
4072 __func__, quickvx_vlp_gpio, rc);
4073 return rc;
4074 }
4075
4076 /* bring QuickVX VLP line low */
4077 gpio_set_value(97, 0);
4078
4079 rc = pm8058_gpio_config(PMIC_GPIO_QUICKVX_CLK,
4080 &pmic_quickvx_clk_gpio);
4081 if (rc) {
4082 pr_err("%s: pm8058_gpio_config(%#x)=%d\n",
4083 __func__, PMIC_GPIO_QUICKVX_CLK + 1,
4084 rc);
4085 return rc;
4086 }
4087
4088 gpio_set_value_cansleep(PM8058_GPIO_PM_TO_SYS(
4089 PMIC_GPIO_QUICKVX_CLK), 0);
4090 }
4091 }
4092
4093 /* Toshiba WeGA power -- has 3 power source */
4094 /* 1.5V -- LDO20*/
4095 vreg_ldo20 = vreg_get(NULL, "gp13");
4096
4097 if (IS_ERR(vreg_ldo20)) {
4098 rc = PTR_ERR(vreg_ldo20);
4099 pr_err("%s: gp13 vreg get failed (%d)\n",
4100 __func__, rc);
4101 return rc;
4102 }
4103
4104 /* 1.8V -- LDO12 */
4105 vreg_ldo12 = vreg_get(NULL, "gp9");
4106
4107 if (IS_ERR(vreg_ldo12)) {
4108 rc = PTR_ERR(vreg_ldo12);
4109 pr_err("%s: gp9 vreg get failed (%d)\n",
4110 __func__, rc);
4111 return rc;
4112 }
4113
4114 /* 2.6V -- LDO16 */
4115 vreg_ldo16 = vreg_get(NULL, "gp10");
4116
4117 if (IS_ERR(vreg_ldo16)) {
4118 rc = PTR_ERR(vreg_ldo16);
4119 pr_err("%s: gp10 vreg get failed (%d)\n",
4120 __func__, rc);
4121 return rc;
4122 }
4123
4124 /* 3.075V -- LDO6 */
4125 vreg_ldo6 = vreg_get(NULL, "usb");
4126
4127 if (IS_ERR(vreg_ldo6)) {
4128 rc = PTR_ERR(vreg_ldo6);
4129 pr_err("%s: usb vreg get failed (%d)\n",
4130 __func__, rc);
4131 return rc;
4132 }
4133
4134 if (machine_is_msm7x30_fluid()) {
4135 /* 1.8V -- LDO8 */
4136 vreg_ldo8 = vreg_get(NULL, "gp7");
4137
4138 if (IS_ERR(vreg_ldo8)) {
4139 rc = PTR_ERR(vreg_ldo8);
4140 pr_err("%s: gp7 vreg get failed (%d)\n",
4141 __func__, rc);
4142 return rc;
4143 }
4144 } else {
4145 /* lcd panel power */
4146 /* 3.1V -- LDO15 */
4147 vreg_ldo15 = vreg_get(NULL, "gp6");
4148
4149 if (IS_ERR(vreg_ldo15)) {
4150 rc = PTR_ERR(vreg_ldo15);
4151 pr_err("%s: gp6 vreg get failed (%d)\n",
4152 __func__, rc);
4153 return rc;
4154 }
4155 }
4156
4157 /* For QuickLogic chip, LDO20 requires 1.8V */
4158 /* Toshiba chip requires 1.5V, but can tolerate 1.8V since max is 3V */
4159 if (quickvx_mddi_client)
4160 rc = vreg_set_level(vreg_ldo20, 1800);
4161 else
4162 rc = vreg_set_level(vreg_ldo20, 1500);
4163 if (rc) {
4164 pr_err("%s: vreg LDO20 set level failed (%d)\n",
4165 __func__, rc);
4166 return rc;
4167 }
4168
4169 rc = vreg_set_level(vreg_ldo12, 1800);
4170 if (rc) {
4171 pr_err("%s: vreg LDO12 set level failed (%d)\n",
4172 __func__, rc);
4173 return rc;
4174 }
4175
4176 if (other_mddi_client) {
4177 rc = vreg_set_level(vreg_ldo16, 2600);
4178 if (rc) {
4179 pr_err("%s: vreg LDO16 set level failed (%d)\n",
4180 __func__, rc);
4181 return rc;
4182 }
4183 }
4184
4185 if (quickvx_mddi_client) {
4186 rc = vreg_set_level(vreg_ldo6, 3075);
4187 if (rc) {
4188 pr_err("%s: vreg LDO6 set level failed (%d)\n",
4189 __func__, rc);
4190 return rc;
4191 }
4192 }
4193
4194 if (machine_is_msm7x30_fluid()) {
4195 rc = vreg_set_level(vreg_ldo8, 1800);
4196 if (rc) {
4197 pr_err("%s: vreg LDO8 set level failed (%d)\n",
4198 __func__, rc);
4199 return rc;
4200 }
4201 } else {
4202 rc = vreg_set_level(vreg_ldo15, 3100);
4203 if (rc) {
4204 pr_err("%s: vreg LDO15 set level failed (%d)\n",
4205 __func__, rc);
4206 return rc;
4207 }
4208 }
4209
4210 if (on) {
4211 rc = vreg_enable(vreg_ldo20);
4212 if (rc) {
4213 pr_err("%s: LDO20 vreg enable failed (%d)\n",
4214 __func__, rc);
4215 return rc;
4216 }
4217
4218 rc = vreg_enable(vreg_ldo12);
4219 if (rc) {
4220 pr_err("%s: LDO12 vreg enable failed (%d)\n",
4221 __func__, rc);
4222 return rc;
4223 }
4224
4225 if (other_mddi_client) {
4226 rc = vreg_enable(vreg_ldo16);
4227 if (rc) {
4228 pr_err("%s: LDO16 vreg enable failed (%d)\n",
4229 __func__, rc);
4230 return rc;
4231 }
4232 }
4233
4234 if (quickvx_mddi_client && quickvx_ldo_enabled) {
4235 /* Disable LDO6 during display ON */
4236 rc = vreg_disable(vreg_ldo6);
4237 if (rc) {
4238 pr_err("%s: LDO6 vreg disable failed (%d)\n",
4239 __func__, rc);
4240 return rc;
4241 }
4242 quickvx_ldo_enabled = 0;
4243 }
4244
4245 if (machine_is_msm7x30_fluid()) {
4246 rc = vreg_enable(vreg_ldo8);
4247 if (rc) {
4248 pr_err("%s: LDO8 vreg enable failed (%d)\n",
4249 __func__, rc);
4250 return rc;
4251 }
4252 } else {
4253 rc = vreg_enable(vreg_ldo15);
4254 if (rc) {
4255 pr_err("%s: LDO15 vreg enable failed (%d)\n",
4256 __func__, rc);
4257 return rc;
4258 }
4259 }
4260
4261 mdelay(5); /* ensure power is stable */
4262
4263 if (machine_is_msm7x30_fluid()) {
4264 rc = msm_gpios_request_enable(fluid_vee_reset_gpio,
4265 ARRAY_SIZE(fluid_vee_reset_gpio));
4266 if (rc)
4267 pr_err("%s gpio_request_enable failed rc=%d\n",
4268 __func__, rc);
4269 else {
4270 /* assert vee reset_n */
4271 gpio_set_value(20, 1);
4272 gpio_set_value(20, 0);
4273 mdelay(1);
4274 gpio_set_value(20, 1);
4275 }
4276 }
4277
4278 gpio_set_value(180, 1); /* bring reset line high */
4279 mdelay(10); /* 10 msec before IO can be accessed */
4280
4281 if (quickvx_mddi_client) {
4282 gpio_set_value(97, 1);
4283 msleep(2);
4284 gpio_set_value_cansleep(PM8058_GPIO_PM_TO_SYS(
4285 PMIC_GPIO_QUICKVX_CLK), 1);
4286 msleep(2);
4287 }
4288
4289 rc = pmapp_display_clock_config(1);
4290 if (rc) {
4291 pr_err("%s pmapp_display_clock_config rc=%d\n",
4292 __func__, rc);
4293 return rc;
4294 }
4295
4296 } else {
4297 rc = vreg_disable(vreg_ldo20);
4298 if (rc) {
4299 pr_err("%s: LDO20 vreg disable failed (%d)\n",
4300 __func__, rc);
4301 return rc;
4302 }
4303
4304
4305 if (other_mddi_client) {
4306 rc = vreg_disable(vreg_ldo16);
4307 if (rc) {
4308 pr_err("%s: LDO16 vreg disable failed (%d)\n",
4309 __func__, rc);
4310 return rc;
4311 }
4312 }
4313
4314 if (quickvx_mddi_client && !quickvx_ldo_enabled) {
4315 /* Enable LDO6 during display OFF for
4316 Quicklogic chip to sleep with data retention */
4317 rc = vreg_enable(vreg_ldo6);
4318 if (rc) {
4319 pr_err("%s: LDO6 vreg enable failed (%d)\n",
4320 __func__, rc);
4321 return rc;
4322 }
4323 quickvx_ldo_enabled = 1;
4324 }
4325
4326 gpio_set_value(180, 0); /* bring reset line low */
4327
4328 if (quickvx_mddi_client) {
4329 gpio_set_value(97, 0);
4330 gpio_set_value_cansleep(PM8058_GPIO_PM_TO_SYS(
4331 PMIC_GPIO_QUICKVX_CLK), 0);
4332 }
4333
4334 if (machine_is_msm7x30_fluid()) {
4335 rc = vreg_disable(vreg_ldo8);
4336 if (rc) {
4337 pr_err("%s: LDO8 vreg disable failed (%d)\n",
4338 __func__, rc);
4339 return rc;
4340 }
4341 } else {
4342 rc = vreg_disable(vreg_ldo15);
4343 if (rc) {
4344 pr_err("%s: LDO15 vreg disable failed (%d)\n",
4345 __func__, rc);
4346 return rc;
4347 }
4348 }
4349
4350 mdelay(5); /* ensure power is stable */
4351
4352 rc = vreg_disable(vreg_ldo12);
4353 if (rc) {
4354 pr_err("%s: LDO12 vreg disable failed (%d)\n",
4355 __func__, rc);
4356 return rc;
4357 }
4358
4359 if (machine_is_msm7x30_fluid()) {
4360 msm_gpios_disable_free(fluid_vee_reset_gpio,
4361 ARRAY_SIZE(fluid_vee_reset_gpio));
4362 }
4363
4364 rc = pmapp_display_clock_config(0);
4365 if (rc) {
4366 pr_err("%s pmapp_display_clock_config rc=%d\n",
4367 __func__, rc);
4368 return rc;
4369 }
4370 }
4371
4372 return rc;
4373}
4374
4375static int msm_fb_mddi_sel_clk(u32 *clk_rate)
4376{
4377 *clk_rate *= 2;
4378 return 0;
4379}
4380
4381static int msm_fb_mddi_client_power(u32 client_id)
4382{
4383 struct vreg *vreg_ldo20, *vreg_ldo16;
4384 int rc;
4385
4386 printk(KERN_NOTICE "\n client_id = 0x%x", client_id);
4387 /* Check if it is Quicklogic client */
4388 if (client_id == 0xc5835800) {
4389 printk(KERN_NOTICE "\n Quicklogic MDDI client");
4390 other_mddi_client = 0;
4391 vreg_ldo16 = vreg_get(NULL, "gp10");
4392
4393 if (IS_ERR(vreg_ldo16)) {
4394 rc = PTR_ERR(vreg_ldo16);
4395 pr_err("%s: gp10 vreg get failed (%d)\n",
4396 __func__, rc);
4397 return rc;
4398 }
4399
4400 rc = vreg_disable(vreg_ldo16);
4401 if (rc) {
4402 pr_err("%s: LDO16 vreg enable failed (%d)\n",
4403 __func__, rc);
4404 return rc;
4405 }
4406 } else {
4407 printk(KERN_NOTICE "\n Non-Quicklogic MDDI client");
4408 quickvx_mddi_client = 0;
4409 gpio_set_value(97, 0);
4410 gpio_set_value_cansleep(PM8058_GPIO_PM_TO_SYS(
4411 PMIC_GPIO_QUICKVX_CLK), 0);
4412
4413 vreg_ldo20 = vreg_get(NULL, "gp13");
4414
4415 if (IS_ERR(vreg_ldo20)) {
4416 rc = PTR_ERR(vreg_ldo20);
4417 pr_err("%s: gp13 vreg get failed (%d)\n",
4418 __func__, rc);
4419 return rc;
4420 }
4421 rc = vreg_set_level(vreg_ldo20, 1500);
4422 if (rc) {
4423 pr_err("%s: vreg LDO20 set level failed (%d)\n",
4424 __func__, rc);
4425 return rc;
4426 }
4427 }
4428 return 0;
4429}
4430
4431static struct mddi_platform_data mddi_pdata = {
4432 .mddi_power_save = display_common_power,
4433 .mddi_sel_clk = msm_fb_mddi_sel_clk,
4434 .mddi_client_power = msm_fb_mddi_client_power,
4435};
4436
4437int mdp_core_clk_rate_table[] = {
4438 122880000,
4439 122880000,
4440 122880000,
4441 192000000,
4442};
4443
4444static struct msm_panel_common_pdata mdp_pdata = {
4445 .hw_revision_addr = 0xac001270,
4446 .gpio = 30,
4447 .mdp_core_clk_rate = 122880000,
4448 .mdp_core_clk_table = mdp_core_clk_rate_table,
4449 .num_mdp_clk = ARRAY_SIZE(mdp_core_clk_rate_table),
4450};
4451
4452static int lcd_panel_spi_gpio_num[] = {
4453 45, /* spi_clk */
4454 46, /* spi_cs */
4455 47, /* spi_mosi */
4456 48, /* spi_miso */
4457 };
4458
4459static struct msm_gpio lcd_panel_gpios[] = {
4460/* Workaround, since HDMI_INT is using the same GPIO line (18), and is used as
4461 * input. if there is a hardware revision; we should reassign this GPIO to a
4462 * new open line; and removing it will just ensure that this will be missed in
4463 * the future.
4464 { GPIO_CFG(18, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "lcdc_grn0" },
4465 */
4466 { GPIO_CFG(19, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "lcdc_grn1" },
4467 { GPIO_CFG(20, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "lcdc_blu0" },
4468 { GPIO_CFG(21, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "lcdc_blu1" },
4469 { GPIO_CFG(22, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "lcdc_blu2" },
4470 { GPIO_CFG(23, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "lcdc_red0" },
4471 { GPIO_CFG(24, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "lcdc_red1" },
4472 { GPIO_CFG(25, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "lcdc_red2" },
4473#ifndef CONFIG_SPI_QSD
4474 { GPIO_CFG(45, 0, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "spi_clk" },
4475 { GPIO_CFG(46, 0, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "spi_cs0" },
4476 { GPIO_CFG(47, 0, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "spi_mosi" },
4477 { GPIO_CFG(48, 0, GPIO_CFG_INPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "spi_miso" },
4478#endif
4479 { GPIO_CFG(90, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "lcdc_pclk" },
4480 { GPIO_CFG(91, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "lcdc_en" },
4481 { GPIO_CFG(92, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "lcdc_vsync" },
4482 { GPIO_CFG(93, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "lcdc_hsync" },
4483 { GPIO_CFG(94, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "lcdc_grn2" },
4484 { GPIO_CFG(95, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "lcdc_grn3" },
4485 { GPIO_CFG(96, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "lcdc_grn4" },
4486 { GPIO_CFG(97, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "lcdc_grn5" },
4487 { GPIO_CFG(98, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "lcdc_grn6" },
4488 { GPIO_CFG(99, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "lcdc_grn7" },
4489 { GPIO_CFG(100, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "lcdc_blu3" },
4490 { GPIO_CFG(101, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "lcdc_blu4" },
4491 { GPIO_CFG(102, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "lcdc_blu5" },
4492 { GPIO_CFG(103, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "lcdc_blu6" },
4493 { GPIO_CFG(104, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "lcdc_blu7" },
4494 { GPIO_CFG(105, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "lcdc_red3" },
4495 { GPIO_CFG(106, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "lcdc_red4" },
4496 { GPIO_CFG(107, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "lcdc_red5" },
4497 { GPIO_CFG(108, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "lcdc_red6" },
4498 { GPIO_CFG(109, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "lcdc_red7" },
4499};
4500
4501static struct msm_gpio lcd_sharp_panel_gpios[] = {
4502 { GPIO_CFG(22, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "lcdc_blu2" },
4503 { GPIO_CFG(25, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "lcdc_red2" },
4504 { GPIO_CFG(90, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "lcdc_pclk" },
4505 { GPIO_CFG(91, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "lcdc_en" },
4506 { GPIO_CFG(92, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "lcdc_vsync" },
4507 { GPIO_CFG(93, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "lcdc_hsync" },
4508 { GPIO_CFG(94, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "lcdc_grn2" },
4509 { GPIO_CFG(95, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "lcdc_grn3" },
4510 { GPIO_CFG(96, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "lcdc_grn4" },
4511 { GPIO_CFG(97, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "lcdc_grn5" },
4512 { GPIO_CFG(98, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "lcdc_grn6" },
4513 { GPIO_CFG(99, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "lcdc_grn7" },
4514 { GPIO_CFG(100, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "lcdc_blu3" },
4515 { GPIO_CFG(101, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "lcdc_blu4" },
4516 { GPIO_CFG(102, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "lcdc_blu5" },
4517 { GPIO_CFG(103, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "lcdc_blu6" },
4518 { GPIO_CFG(104, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "lcdc_blu7" },
4519 { GPIO_CFG(105, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "lcdc_red3" },
4520 { GPIO_CFG(106, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "lcdc_red4" },
4521 { GPIO_CFG(107, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "lcdc_red5" },
4522 { GPIO_CFG(108, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "lcdc_red6" },
4523 { GPIO_CFG(109, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA), "lcdc_red7" },
4524};
4525
4526static int lcdc_toshiba_panel_power(int on)
4527{
4528 int rc, i;
4529 struct msm_gpio *gp;
4530
4531 rc = display_common_power(on);
4532 if (rc < 0) {
4533 printk(KERN_ERR "%s display_common_power failed: %d\n",
4534 __func__, rc);
4535 return rc;
4536 }
4537
4538 if (on) {
4539 rc = msm_gpios_enable(lcd_panel_gpios,
4540 ARRAY_SIZE(lcd_panel_gpios));
4541 if (rc < 0) {
4542 printk(KERN_ERR "%s: gpio enable failed: %d\n",
4543 __func__, rc);
4544 }
4545 } else { /* off */
4546 gp = lcd_panel_gpios;
4547 for (i = 0; i < ARRAY_SIZE(lcd_panel_gpios); i++) {
4548 /* ouput low */
4549 gpio_set_value(GPIO_PIN(gp->gpio_cfg), 0);
4550 gp++;
4551 }
4552 }
4553
4554 return rc;
4555}
4556
4557static int lcdc_sharp_panel_power(int on)
4558{
4559 int rc, i;
4560 struct msm_gpio *gp;
4561
4562 rc = display_common_power(on);
4563 if (rc < 0) {
4564 printk(KERN_ERR "%s display_common_power failed: %d\n",
4565 __func__, rc);
4566 return rc;
4567 }
4568
4569 if (on) {
4570 rc = msm_gpios_enable(lcd_sharp_panel_gpios,
4571 ARRAY_SIZE(lcd_sharp_panel_gpios));
4572 if (rc < 0) {
4573 printk(KERN_ERR "%s: gpio enable failed: %d\n",
4574 __func__, rc);
4575 }
4576 } else { /* off */
4577 gp = lcd_sharp_panel_gpios;
4578 for (i = 0; i < ARRAY_SIZE(lcd_sharp_panel_gpios); i++) {
4579 /* ouput low */
4580 gpio_set_value(GPIO_PIN(gp->gpio_cfg), 0);
4581 gp++;
4582 }
4583 }
4584
4585 return rc;
4586}
4587
4588static int lcdc_panel_power(int on)
4589{
4590 int flag_on = !!on;
4591 static int lcdc_power_save_on;
4592
4593 if (lcdc_power_save_on == flag_on)
4594 return 0;
4595
4596 lcdc_power_save_on = flag_on;
4597 quickvx_mddi_client = 0;
4598
4599 if (machine_is_msm7x30_fluid())
4600 return lcdc_sharp_panel_power(on);
4601 else
4602 return lcdc_toshiba_panel_power(on);
4603}
4604
4605static struct lcdc_platform_data lcdc_pdata = {
4606 .lcdc_power_save = lcdc_panel_power,
4607};
4608
4609static int atv_dac_power(int on)
4610{
4611 int rc = 0;
4612 struct vreg *vreg_s4, *vreg_ldo9;
4613
4614 vreg_s4 = vreg_get(NULL, "s4");
4615 if (IS_ERR(vreg_s4)) {
4616 rc = PTR_ERR(vreg_s4);
4617 pr_err("%s: s4 vreg get failed (%d)\n",
4618 __func__, rc);
4619 return -1;
4620 }
4621 vreg_ldo9 = vreg_get(NULL, "gp1");
4622 if (IS_ERR(vreg_ldo9)) {
4623 rc = PTR_ERR(vreg_ldo9);
4624 pr_err("%s: ldo9 vreg get failed (%d)\n",
4625 __func__, rc);
4626 return rc;
4627 }
4628
4629 if (on) {
4630 rc = vreg_enable(vreg_s4);
4631 if (rc) {
4632 pr_err("%s: s4 vreg enable failed (%d)\n",
4633 __func__, rc);
4634 return rc;
4635 }
4636 rc = vreg_enable(vreg_ldo9);
4637 if (rc) {
4638 pr_err("%s: ldo9 vreg enable failed (%d)\n",
4639 __func__, rc);
4640 return rc;
4641 }
4642 } else {
4643 rc = vreg_disable(vreg_ldo9);
4644 if (rc) {
4645 pr_err("%s: ldo9 vreg disable failed (%d)\n",
4646 __func__, rc);
4647 return rc;
4648 }
4649 rc = vreg_disable(vreg_s4);
4650 if (rc) {
4651 pr_err("%s: s4 vreg disable failed (%d)\n",
4652 __func__, rc);
4653 return rc;
4654 }
4655 }
4656 return rc;
4657}
4658
4659static struct tvenc_platform_data atv_pdata = {
4660 .poll = 1,
4661 .pm_vid_en = atv_dac_power,
4662};
4663
4664static void __init msm_fb_add_devices(void)
4665{
4666 msm_fb_register_device("mdp", &mdp_pdata);
4667 msm_fb_register_device("pmdh", &mddi_pdata);
4668 msm_fb_register_device("lcdc", &lcdc_pdata);
4669 msm_fb_register_device("dtv", &dtv_pdata);
4670 msm_fb_register_device("tvenc", &atv_pdata);
4671#ifdef CONFIG_FB_MSM_TVOUT
4672 msm_fb_register_device("tvout_device", NULL);
4673#endif
4674}
4675
4676static struct msm_panel_common_pdata lcdc_toshiba_panel_data = {
4677 .gpio_num = lcd_panel_spi_gpio_num,
4678};
4679
4680static struct platform_device lcdc_toshiba_panel_device = {
4681 .name = "lcdc_toshiba_wvga",
4682 .id = 0,
4683 .dev = {
4684 .platform_data = &lcdc_toshiba_panel_data,
4685 }
4686};
4687
4688#if defined(CONFIG_MARIMBA_CORE) && \
4689 (defined(CONFIG_MSM_BT_POWER) || defined(CONFIG_MSM_BT_POWER_MODULE))
4690static struct platform_device msm_bt_power_device = {
4691 .name = "bt_power",
4692 .id = -1
4693};
4694
4695enum {
4696 BT_RFR,
4697 BT_CTS,
4698 BT_RX,
4699 BT_TX,
4700};
4701
4702static struct msm_gpio bt_config_power_on[] = {
4703 { GPIO_CFG(134, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA),
4704 "UART1DM_RFR" },
4705 { GPIO_CFG(135, 1, GPIO_CFG_INPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA),
4706 "UART1DM_CTS" },
4707 { GPIO_CFG(136, 1, GPIO_CFG_INPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA),
4708 "UART1DM_Rx" },
4709 { GPIO_CFG(137, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA),
4710 "UART1DM_Tx" }
4711};
4712
4713static struct msm_gpio bt_config_power_off[] = {
4714 { GPIO_CFG(134, 0, GPIO_CFG_INPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA),
4715 "UART1DM_RFR" },
4716 { GPIO_CFG(135, 0, GPIO_CFG_INPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA),
4717 "UART1DM_CTS" },
4718 { GPIO_CFG(136, 0, GPIO_CFG_INPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA),
4719 "UART1DM_Rx" },
4720 { GPIO_CFG(137, 0, GPIO_CFG_INPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA),
4721 "UART1DM_Tx" }
4722};
4723
4724static const char *vregs_bt_marimba_name[] = {
4725 "s3",
4726 "s2",
4727 "gp16",
4728 "wlan"
4729};
4730static struct vreg *vregs_bt_marimba[ARRAY_SIZE(vregs_bt_marimba_name)];
4731
4732static const char *vregs_bt_bahama_name[] = {
4733 "s3",
4734 "usb2",
4735 "s2",
4736 "wlan"
4737};
4738static struct vreg *vregs_bt_bahama[ARRAY_SIZE(vregs_bt_bahama_name)];
4739
4740static u8 bahama_version;
4741
4742static int marimba_bt(int on)
4743{
4744 int rc;
4745 int i;
4746 struct marimba config = { .mod_id = MARIMBA_SLAVE_ID_MARIMBA };
4747
4748 struct marimba_config_register {
4749 u8 reg;
4750 u8 value;
4751 u8 mask;
4752 };
4753
4754 struct marimba_variant_register {
4755 const size_t size;
4756 const struct marimba_config_register *set;
4757 };
4758
4759 const struct marimba_config_register *p;
4760
4761 u8 version;
4762
4763 const struct marimba_config_register v10_bt_on[] = {
4764 { 0xE5, 0x0B, 0x0F },
4765 { 0x05, 0x02, 0x07 },
4766 { 0x06, 0x88, 0xFF },
4767 { 0xE7, 0x21, 0x21 },
4768 { 0xE3, 0x38, 0xFF },
4769 { 0xE4, 0x06, 0xFF },
4770 };
4771
4772 const struct marimba_config_register v10_bt_off[] = {
4773 { 0xE5, 0x0B, 0x0F },
4774 { 0x05, 0x08, 0x0F },
4775 { 0x06, 0x88, 0xFF },
4776 { 0xE7, 0x00, 0x21 },
4777 { 0xE3, 0x00, 0xFF },
4778 { 0xE4, 0x00, 0xFF },
4779 };
4780
4781 const struct marimba_config_register v201_bt_on[] = {
4782 { 0x05, 0x08, 0x07 },
4783 { 0x06, 0x88, 0xFF },
4784 { 0xE7, 0x21, 0x21 },
4785 { 0xE3, 0x38, 0xFF },
4786 { 0xE4, 0x06, 0xFF },
4787 };
4788
4789 const struct marimba_config_register v201_bt_off[] = {
4790 { 0x05, 0x08, 0x07 },
4791 { 0x06, 0x88, 0xFF },
4792 { 0xE7, 0x00, 0x21 },
4793 { 0xE3, 0x00, 0xFF },
4794 { 0xE4, 0x00, 0xFF },
4795 };
4796
4797 const struct marimba_config_register v210_bt_on[] = {
4798 { 0xE9, 0x01, 0x01 },
4799 { 0x06, 0x88, 0xFF },
4800 { 0xE7, 0x21, 0x21 },
4801 { 0xE3, 0x38, 0xFF },
4802 { 0xE4, 0x06, 0xFF },
4803 };
4804
4805 const struct marimba_config_register v210_bt_off[] = {
4806 { 0x06, 0x88, 0xFF },
4807 { 0xE7, 0x00, 0x21 },
4808 { 0xE9, 0x00, 0x01 },
4809 { 0xE3, 0x00, 0xFF },
4810 { 0xE4, 0x00, 0xFF },
4811 };
4812
4813 const struct marimba_variant_register bt_marimba[2][4] = {
4814 {
4815 { ARRAY_SIZE(v10_bt_off), v10_bt_off },
4816 { 0, NULL },
4817 { ARRAY_SIZE(v201_bt_off), v201_bt_off },
4818 { ARRAY_SIZE(v210_bt_off), v210_bt_off }
4819 },
4820 {
4821 { ARRAY_SIZE(v10_bt_on), v10_bt_on },
4822 { 0, NULL },
4823 { ARRAY_SIZE(v201_bt_on), v201_bt_on },
4824 { ARRAY_SIZE(v210_bt_on), v210_bt_on }
4825 }
4826 };
4827
4828 on = on ? 1 : 0;
4829
4830 rc = marimba_read_bit_mask(&config, 0x11, &version, 1, 0x1F);
4831 if (rc < 0) {
4832 printk(KERN_ERR
4833 "%s: version read failed: %d\n",
4834 __func__, rc);
4835 return rc;
4836 }
4837
4838 if ((version >= ARRAY_SIZE(bt_marimba[on])) ||
4839 (bt_marimba[on][version].size == 0)) {
4840 printk(KERN_ERR
4841 "%s: unsupported version\n",
4842 __func__);
4843 return -EIO;
4844 }
4845
4846 p = bt_marimba[on][version].set;
4847
4848 printk(KERN_INFO "%s: found version %d\n", __func__, version);
4849
4850 for (i = 0; i < bt_marimba[on][version].size; i++) {
4851 u8 value = (p+i)->value;
4852 rc = marimba_write_bit_mask(&config,
4853 (p+i)->reg,
4854 &value,
4855 sizeof((p+i)->value),
4856 (p+i)->mask);
4857 if (rc < 0) {
4858 printk(KERN_ERR
4859 "%s: reg %d write failed: %d\n",
4860 __func__, (p+i)->reg, rc);
4861 return rc;
4862 }
4863 printk(KERN_INFO "%s: reg 0x%02x value 0x%02x mask 0x%02x\n",
4864 __func__, (p+i)->reg,
4865 value, (p+i)->mask);
4866 }
4867 return 0;
4868}
4869
4870static int bahama_bt(int on)
4871{
4872 int rc;
4873 int i;
4874 struct marimba config = { .mod_id = SLAVE_ID_BAHAMA };
4875
4876 struct bahama_variant_register {
4877 const size_t size;
4878 const struct bahama_config_register *set;
4879 };
4880
4881 const struct bahama_config_register *p;
4882
4883
4884 const struct bahama_config_register v10_bt_on[] = {
4885 { 0xE9, 0x00, 0xFF },
4886 { 0xF4, 0x80, 0xFF },
4887 { 0xF0, 0x06, 0xFF },
4888 { 0xE4, 0x00, 0xFF },
4889 { 0xE5, 0x00, 0x0F },
4890#ifdef CONFIG_WLAN
4891 { 0xE6, 0x38, 0x7F },
4892 { 0xE7, 0x06, 0xFF },
4893#endif
4894 { 0x11, 0x13, 0xFF },
4895 { 0xE9, 0x21, 0xFF },
4896 { 0x01, 0x0C, 0x1F },
4897 { 0x01, 0x08, 0x1F },
4898 };
4899
4900 const struct bahama_config_register v20_bt_on_fm_off[] = {
4901 { 0x11, 0x0C, 0xFF },
4902 { 0x13, 0x01, 0xFF },
4903 { 0xF4, 0x80, 0xFF },
4904 { 0xF0, 0x00, 0xFF },
4905 { 0xE9, 0x00, 0xFF },
4906#ifdef CONFIG_WLAN
4907 { 0x81, 0x00, 0xFF },
4908 { 0x82, 0x00, 0xFF },
4909 { 0xE6, 0x38, 0x7F },
4910 { 0xE7, 0x06, 0xFF },
4911#endif
4912 { 0xE9, 0x21, 0xFF }
4913 };
4914
4915 const struct bahama_config_register v20_bt_on_fm_on[] = {
4916 { 0x11, 0x0C, 0xFF },
4917 { 0x13, 0x01, 0xFF },
4918 { 0xF4, 0x86, 0xFF },
4919 { 0xF0, 0x06, 0xFF },
4920 { 0xE9, 0x00, 0xFF },
4921#ifdef CONFIG_WLAN
4922 { 0x81, 0x00, 0xFF },
4923 { 0x82, 0x00, 0xFF },
4924 { 0xE6, 0x38, 0x7F },
4925 { 0xE7, 0x06, 0xFF },
4926#endif
4927 { 0xE9, 0x21, 0xFF }
4928 };
4929
4930 const struct bahama_config_register v10_bt_off[] = {
4931 { 0xE9, 0x00, 0xFF },
4932 };
4933
4934 const struct bahama_config_register v20_bt_off_fm_off[] = {
4935 { 0xF4, 0x84, 0xFF },
4936 { 0xF0, 0x04, 0xFF },
4937 { 0xE9, 0x00, 0xFF }
4938 };
4939
4940 const struct bahama_config_register v20_bt_off_fm_on[] = {
4941 { 0xF4, 0x86, 0xFF },
4942 { 0xF0, 0x06, 0xFF },
4943 { 0xE9, 0x00, 0xFF }
4944 };
4945
4946 const struct bahama_variant_register bt_bahama[2][3] = {
4947 {
4948 { ARRAY_SIZE(v10_bt_off), v10_bt_off },
4949 { ARRAY_SIZE(v20_bt_off_fm_off), v20_bt_off_fm_off },
4950 { ARRAY_SIZE(v20_bt_off_fm_on), v20_bt_off_fm_on }
4951 },
4952 {
4953 { ARRAY_SIZE(v10_bt_on), v10_bt_on },
4954 { ARRAY_SIZE(v20_bt_on_fm_off), v20_bt_on_fm_off },
4955 { ARRAY_SIZE(v20_bt_on_fm_on), v20_bt_on_fm_on }
4956 }
4957 };
4958
4959 u8 offset = 0; /* index into bahama configs */
4960
4961 on = on ? 1 : 0;
4962
4963 bahama_version = read_bahama_ver();
4964
4965 if (((int)bahama_version) < 0 ||
4966 bahama_version == VER_UNSUPPORTED) {
4967 dev_err(&msm_bt_power_device.dev,
4968 "%s: i2c failure or unsupported version: %d\n",
4969 __func__, bahama_version);
4970 return -EIO;
4971 }
4972
4973 if (bahama_version == VER_2_0) {
4974 if (marimba_get_fm_status(&config))
4975 offset = 0x01;
4976 }
4977
4978 p = bt_bahama[on][bahama_version + offset].set;
4979
4980 dev_info(&msm_bt_power_device.dev,
4981 "%s: found version %d\n", __func__, bahama_version);
4982
4983 for (i = 0; i < bt_bahama[on][bahama_version + offset].size; i++) {
4984 u8 value = (p+i)->value;
4985 rc = marimba_write_bit_mask(&config,
4986 (p+i)->reg,
4987 &value,
4988 sizeof((p+i)->value),
4989 (p+i)->mask);
4990 if (rc < 0) {
4991 dev_err(&msm_bt_power_device.dev,
4992 "%s: reg %d write failed: %d\n",
4993 __func__, (p+i)->reg, rc);
4994 return rc;
4995 }
4996 dev_info(&msm_bt_power_device.dev,
4997 "%s: reg 0x%02x write value 0x%02x mask 0x%02x\n",
4998 __func__, (p+i)->reg,
4999 value, (p+i)->mask);
5000 }
5001 /* Update BT status */
5002 if (on)
5003 marimba_set_bt_status(&config, true);
5004 else
5005 marimba_set_bt_status(&config, false);
5006
5007 if (bahama_version == VER_2_0 && on) { /* variant of bahama v2 */
5008 /* Disable s2 as bahama v2 uses internal LDO regulator */
5009 for (i = 0; i < ARRAY_SIZE(vregs_bt_bahama_name); i++) {
5010 if (!strcmp(vregs_bt_bahama_name[i], "s2")) {
5011 rc = vreg_disable(vregs_bt_bahama[i]);
5012 if (rc < 0) {
5013 printk(KERN_ERR
5014 "%s: vreg %s disable "
5015 "failed (%d)\n",
5016 __func__,
5017 vregs_bt_bahama_name[i], rc);
5018 return -EIO;
5019 }
5020 rc = pmapp_vreg_level_vote("BTPW",
5021 PMAPP_VREG_S2,
5022 0);
5023 if (rc < 0) {
5024 printk(KERN_ERR "%s: vreg "
5025 "level off failed (%d)\n",
5026 __func__, rc);
5027 return -EIO;
5028 }
5029 printk(KERN_INFO "%s: vreg disable & "
5030 "level off successful (%d)\n",
5031 __func__, rc);
5032 }
5033 }
5034 }
5035
5036 return 0;
5037}
5038
5039static int bluetooth_power_regulators(int on, int bahama_not_marimba)
5040{
5041 int i, rc;
5042 const char **vregs_name;
5043 struct vreg **vregs;
5044 int vregs_size;
5045
5046 if (bahama_not_marimba) {
5047 vregs_name = vregs_bt_bahama_name;
5048 vregs = vregs_bt_bahama;
5049 vregs_size = ARRAY_SIZE(vregs_bt_bahama_name);
5050 } else {
5051 vregs_name = vregs_bt_marimba_name;
5052 vregs = vregs_bt_marimba;
5053 vregs_size = ARRAY_SIZE(vregs_bt_marimba_name);
5054 }
5055
5056 for (i = 0; i < vregs_size; i++) {
5057 if (bahama_not_marimba && (bahama_version == VER_2_0) &&
5058 !on && !strcmp(vregs_bt_bahama_name[i], "s2"))
5059 continue;
5060 rc = on ? vreg_enable(vregs[i]) :
5061 vreg_disable(vregs[i]);
5062 if (rc < 0) {
5063 printk(KERN_ERR "%s: vreg %s %s failed (%d)\n",
5064 __func__, vregs_name[i],
5065 on ? "enable" : "disable", rc);
5066 return -EIO;
5067 }
5068 }
5069 return 0;
5070}
5071
5072static int bluetooth_power(int on)
5073{
5074 int rc;
5075 const char *id = "BTPW";
5076
5077 int bahama_not_marimba = bahama_present();
5078
5079 if (bahama_not_marimba == -1) {
5080 printk(KERN_WARNING "%s: bahama_present: %d\n",
5081 __func__, bahama_not_marimba);
5082 return -ENODEV;
5083 }
5084
5085 if (on) {
5086 rc = pmapp_vreg_level_vote(id, PMAPP_VREG_S2, 1300);
5087 if (rc < 0) {
5088 printk(KERN_ERR "%s: vreg level on failed (%d)\n",
5089 __func__, rc);
5090 return rc;
5091 }
5092
5093 rc = bluetooth_power_regulators(on, bahama_not_marimba);
5094 if (rc < 0)
5095 return -EIO;
5096
5097 rc = pmapp_clock_vote(id, PMAPP_CLOCK_ID_DO,
5098 PMAPP_CLOCK_VOTE_ON);
5099 if (rc < 0)
5100 return -EIO;
5101
5102 if (machine_is_msm8x55_svlte_surf() ||
5103 machine_is_msm8x55_svlte_ffa()) {
5104 rc = marimba_gpio_config(1);
5105 if (rc < 0)
5106 return -EIO;
5107 }
5108
5109 rc = (bahama_not_marimba ? bahama_bt(on) : marimba_bt(on));
5110 if (rc < 0)
5111 return -EIO;
5112
5113 msleep(10);
5114
5115 rc = pmapp_clock_vote(id, PMAPP_CLOCK_ID_DO,
5116 PMAPP_CLOCK_VOTE_PIN_CTRL);
5117 if (rc < 0)
5118 return -EIO;
5119
5120 if (machine_is_msm8x55_svlte_surf() ||
5121 machine_is_msm8x55_svlte_ffa()) {
5122 rc = marimba_gpio_config(0);
5123 if (rc < 0)
5124 return -EIO;
5125 }
5126
5127 rc = msm_gpios_enable(bt_config_power_on,
5128 ARRAY_SIZE(bt_config_power_on));
5129
5130 if (rc < 0)
5131 return rc;
5132
5133 } else {
5134 rc = msm_gpios_enable(bt_config_power_off,
5135 ARRAY_SIZE(bt_config_power_off));
5136 if (rc < 0)
5137 return rc;
5138
5139 /* check for initial RFKILL block (power off) */
5140 if (platform_get_drvdata(&msm_bt_power_device) == NULL)
5141 goto out;
5142
5143 rc = (bahama_not_marimba ? bahama_bt(on) : marimba_bt(on));
5144 if (rc < 0)
5145 return -EIO;
5146
5147 rc = pmapp_clock_vote(id, PMAPP_CLOCK_ID_DO,
5148 PMAPP_CLOCK_VOTE_OFF);
5149 if (rc < 0)
5150 return -EIO;
5151
5152 rc = bluetooth_power_regulators(on, bahama_not_marimba);
5153 if (rc < 0)
5154 return -EIO;
5155
5156 if (bahama_version == VER_1_0) {
5157 rc = pmapp_vreg_level_vote(id, PMAPP_VREG_S2, 0);
5158 if (rc < 0) {
5159 printk(KERN_ERR "%s: vreg level off failed "
5160 "(%d)\n", __func__, rc);
5161 return -EIO;
5162 }
5163 }
5164 }
5165
5166out:
5167 printk(KERN_DEBUG "Bluetooth power switch: %d\n", on);
5168
5169 return 0;
5170}
5171
5172static void __init bt_power_init(void)
5173{
5174 int i;
5175
5176 for (i = 0; i < ARRAY_SIZE(vregs_bt_marimba_name); i++) {
5177 vregs_bt_marimba[i] = vreg_get(NULL, vregs_bt_marimba_name[i]);
5178 if (IS_ERR(vregs_bt_marimba[i])) {
5179 printk(KERN_ERR "%s: vreg get %s failed (%ld)\n",
5180 __func__, vregs_bt_marimba_name[i],
5181 PTR_ERR(vregs_bt_marimba[i]));
5182 return;
5183 }
5184 }
5185
5186 for (i = 0; i < ARRAY_SIZE(vregs_bt_bahama_name); i++) {
5187 vregs_bt_bahama[i] = vreg_get(NULL, vregs_bt_bahama_name[i]);
5188 if (IS_ERR(vregs_bt_bahama[i])) {
5189 printk(KERN_ERR "%s: vreg get %s failed (%ld)\n",
5190 __func__, vregs_bt_bahama_name[i],
5191 PTR_ERR(vregs_bt_bahama[i]));
5192 return;
5193 }
5194 }
5195
5196 msm_bt_power_device.dev.platform_data = &bluetooth_power;
5197}
5198#else
5199#define bt_power_init(x) do {} while (0)
5200#endif
5201
5202static struct msm_psy_batt_pdata msm_psy_batt_data = {
5203 .voltage_min_design = 2800,
5204 .voltage_max_design = 4300,
5205 .avail_chg_sources = AC_CHG | USB_CHG ,
5206 .batt_technology = POWER_SUPPLY_TECHNOLOGY_LION,
5207};
5208
5209static struct platform_device msm_batt_device = {
5210 .name = "msm-battery",
5211 .id = -1,
5212 .dev.platform_data = &msm_psy_batt_data,
5213};
5214
5215static char *msm_adc_fluid_device_names[] = {
5216 "LTC_ADC1",
5217 "LTC_ADC2",
5218 "LTC_ADC3",
5219};
5220
5221static char *msm_adc_surf_device_names[] = {
5222 "XO_ADC",
5223};
5224
5225static struct msm_adc_platform_data msm_adc_pdata;
5226
5227static struct platform_device msm_adc_device = {
5228 .name = "msm_adc",
5229 .id = -1,
5230 .dev = {
5231 .platform_data = &msm_adc_pdata,
5232 },
5233};
5234
5235#ifdef CONFIG_MSM_SDIO_AL
5236static struct msm_gpio mdm2ap_status = {
5237 GPIO_CFG(77, 0, GPIO_CFG_INPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA),
5238 "mdm2ap_status"
5239};
5240
5241
5242static int configure_mdm2ap_status(int on)
5243{
5244 if (on)
5245 return msm_gpios_request_enable(&mdm2ap_status, 1);
5246 else {
5247 msm_gpios_disable_free(&mdm2ap_status, 1);
5248 return 0;
5249 }
5250}
5251
5252static int get_mdm2ap_status(void)
5253{
5254 return gpio_get_value(GPIO_PIN(mdm2ap_status.gpio_cfg));
5255}
5256
5257static struct sdio_al_platform_data sdio_al_pdata = {
5258 .config_mdm2ap_status = configure_mdm2ap_status,
5259 .get_mdm2ap_status = get_mdm2ap_status,
5260 .allow_sdioc_version_major_2 = 1,
5261 .peer_sdioc_version_minor = 0x0001,
5262 .peer_sdioc_version_major = 0x0003,
5263 .peer_sdioc_boot_version_minor = 0x0001,
5264 .peer_sdioc_boot_version_major = 0x0003,
5265};
5266
5267struct platform_device msm_device_sdio_al = {
5268 .name = "msm_sdio_al",
5269 .id = -1,
5270 .dev = {
5271 .platform_data = &sdio_al_pdata,
5272 },
5273};
5274
5275#endif /* CONFIG_MSM_SDIO_AL */
5276
Daniel Walker8d747cd2010-02-25 11:37:43 -08005277static struct platform_device *devices[] __initdata = {
Daniel Walker90e37c52010-05-12 14:24:15 -07005278#if defined(CONFIG_SERIAL_MSM) || defined(CONFIG_MSM_SERIAL_DEBUGGER)
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005279 &msm_device_uart2,
5280#endif
Justin Paupore637a25d2011-07-14 17:11:04 -07005281#ifdef CONFIG_MSM_PROC_COMM_REGULATOR
5282 &msm_proccomm_regulator_dev,
5283#endif
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005284 &asoc_msm_pcm,
5285 &asoc_msm_dai0,
5286 &asoc_msm_dai1,
5287#if defined (CONFIG_SND_MSM_MVS_DAI_SOC)
5288 &asoc_msm_mvs,
5289 &asoc_mvs_dai0,
5290 &asoc_mvs_dai1,
Daniel Walker90e37c52010-05-12 14:24:15 -07005291#endif
Niranjana Vishwanathapuraa8855e92010-10-06 13:52:10 -07005292 &msm_device_smd,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005293 &msm_device_dmov,
5294 &smc91x_device,
5295 &smsc911x_device,
5296 &msm_device_nand,
5297#ifdef CONFIG_USB_MSM_OTG_72K
Pavankumar Kondeti5155e2c2010-12-08 13:37:08 +05305298 &msm_device_otg,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005299#ifdef CONFIG_USB_GADGET
5300 &msm_device_gadget_peripheral,
5301#endif
5302#endif
5303#ifdef CONFIG_USB_G_ANDROID
5304 &android_usb_device,
5305#endif
5306 &qsd_device_spi,
5307#ifdef CONFIG_I2C_SSBI
5308 &msm_device_ssbi6,
5309 &msm_device_ssbi7,
5310#endif
5311 &android_pmem_device,
5312 &msm_fb_device,
5313 &msm_migrate_pages_device,
5314 &mddi_toshiba_device,
5315 &lcdc_toshiba_panel_device,
5316#ifdef CONFIG_MSM_ROTATOR
5317 &msm_rotator_device,
5318#endif
5319 &lcdc_sharp_panel_device,
5320 &android_pmem_adsp_device,
5321 &android_pmem_audio_device,
5322 &msm_device_i2c,
5323 &msm_device_i2c_2,
5324 &msm_device_uart_dm1,
5325 &hs_device,
5326#ifdef CONFIG_MSM7KV2_AUDIO
5327 &msm_aictl_device,
5328 &msm_mi2s_device,
5329 &msm_lpa_device,
5330 &msm_aux_pcm_device,
5331#endif
5332 &msm_device_adspdec,
5333 &qup_device_i2c,
5334#if defined(CONFIG_MARIMBA_CORE) && \
5335 (defined(CONFIG_MSM_BT_POWER) || defined(CONFIG_MSM_BT_POWER_MODULE))
5336 &msm_bt_power_device,
5337#endif
5338 &msm_kgsl_3d0,
5339 &msm_kgsl_2d0,
5340#ifdef CONFIG_MT9T013
5341 &msm_camera_sensor_mt9t013,
5342#endif
5343#ifdef CONFIG_MT9D112
5344 &msm_camera_sensor_mt9d112,
5345#endif
5346#ifdef CONFIG_WEBCAM_OV9726
5347 &msm_camera_sensor_ov9726,
5348#endif
5349#ifdef CONFIG_S5K3E2FX
5350 &msm_camera_sensor_s5k3e2fx,
5351#endif
5352#ifdef CONFIG_MT9P012
5353 &msm_camera_sensor_mt9p012,
5354#endif
5355#ifdef CONFIG_MT9E013
5356 &msm_camera_sensor_mt9e013,
5357#endif
5358#ifdef CONFIG_VX6953
5359 &msm_camera_sensor_vx6953,
5360#endif
5361#ifdef CONFIG_SN12M0PZ
5362 &msm_camera_sensor_sn12m0pz,
5363#endif
5364 &msm_device_vidc_720p,
5365#ifdef CONFIG_MSM_GEMINI
5366 &msm_gemini_device,
5367#endif
5368#ifdef CONFIG_MSM_VPE
5369 &msm_vpe_device,
5370#endif
5371#if defined(CONFIG_TSIF) || defined(CONFIG_TSIF_MODULE)
5372 &msm_device_tsif,
5373#endif
5374#ifdef CONFIG_MSM_SDIO_AL
5375 &msm_device_sdio_al,
5376#endif
5377
5378#if defined(CONFIG_CRYPTO_DEV_QCRYPTO) || \
5379 defined(CONFIG_CRYPTO_DEV_QCRYPTO_MODULE)
5380 &qcrypto_device,
5381#endif
5382
5383#if defined(CONFIG_CRYPTO_DEV_QCEDEV) || \
5384 defined(CONFIG_CRYPTO_DEV_QCEDEV_MODULE)
5385 &qcedev_device,
5386#endif
5387
5388 &msm_batt_device,
5389 &msm_adc_device,
5390 &msm_ebi0_thermal,
5391 &msm_ebi1_thermal
5392};
5393
5394static struct msm_gpio msm_i2c_gpios_hw[] = {
5395 { GPIO_CFG(70, 1, GPIO_CFG_INPUT, GPIO_CFG_NO_PULL, GPIO_CFG_16MA), "i2c_scl" },
5396 { GPIO_CFG(71, 1, GPIO_CFG_INPUT, GPIO_CFG_NO_PULL, GPIO_CFG_16MA), "i2c_sda" },
5397};
5398
5399static struct msm_gpio msm_i2c_gpios_io[] = {
5400 { GPIO_CFG(70, 0, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_16MA), "i2c_scl" },
5401 { GPIO_CFG(71, 0, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_16MA), "i2c_sda" },
5402};
5403
5404static struct msm_gpio qup_i2c_gpios_io[] = {
5405 { GPIO_CFG(16, 0, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_16MA), "qup_scl" },
5406 { GPIO_CFG(17, 0, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_16MA), "qup_sda" },
5407};
5408static struct msm_gpio qup_i2c_gpios_hw[] = {
5409 { GPIO_CFG(16, 2, GPIO_CFG_INPUT, GPIO_CFG_NO_PULL, GPIO_CFG_16MA), "qup_scl" },
5410 { GPIO_CFG(17, 2, GPIO_CFG_INPUT, GPIO_CFG_NO_PULL, GPIO_CFG_16MA), "qup_sda" },
5411};
5412
5413static void
5414msm_i2c_gpio_config(int adap_id, int config_type)
5415{
5416 struct msm_gpio *msm_i2c_table;
5417
5418 /* Each adapter gets 2 lines from the table */
5419 if (adap_id > 0)
5420 return;
5421 if (config_type)
5422 msm_i2c_table = &msm_i2c_gpios_hw[adap_id*2];
5423 else
5424 msm_i2c_table = &msm_i2c_gpios_io[adap_id*2];
5425 msm_gpios_enable(msm_i2c_table, 2);
5426}
5427/*This needs to be enabled only for OEMS*/
5428#ifndef CONFIG_QUP_EXCLUSIVE_TO_CAMERA
5429static struct vreg *qup_vreg;
5430#endif
5431static void
5432qup_i2c_gpio_config(int adap_id, int config_type)
5433{
5434 int rc = 0;
5435 struct msm_gpio *qup_i2c_table;
5436 /* Each adapter gets 2 lines from the table */
5437 if (adap_id != 4)
5438 return;
5439 if (config_type)
5440 qup_i2c_table = qup_i2c_gpios_hw;
5441 else
5442 qup_i2c_table = qup_i2c_gpios_io;
5443 rc = msm_gpios_enable(qup_i2c_table, 2);
5444 if (rc < 0)
5445 printk(KERN_ERR "QUP GPIO enable failed: %d\n", rc);
5446 /*This needs to be enabled only for OEMS*/
5447#ifndef CONFIG_QUP_EXCLUSIVE_TO_CAMERA
5448 if (qup_vreg) {
5449 int rc = vreg_set_level(qup_vreg, 1800);
5450 if (rc) {
5451 pr_err("%s: vreg LVS1 set level failed (%d)\n",
5452 __func__, rc);
5453 }
5454 rc = vreg_enable(qup_vreg);
5455 if (rc) {
5456 pr_err("%s: vreg_enable() = %d \n",
5457 __func__, rc);
5458 }
5459 }
5460#endif
5461}
5462
5463static struct msm_i2c_platform_data msm_i2c_pdata = {
5464 .clk_freq = 100000,
5465 .pri_clk = 70,
5466 .pri_dat = 71,
5467 .rmutex = 1,
5468 .rsl_id = "D:I2C02000021",
5469 .msm_i2c_config_gpio = msm_i2c_gpio_config,
5470};
5471
5472static void __init msm_device_i2c_init(void)
5473{
5474 if (msm_gpios_request(msm_i2c_gpios_hw, ARRAY_SIZE(msm_i2c_gpios_hw)))
5475 pr_err("failed to request I2C gpios\n");
5476
5477 msm_device_i2c.dev.platform_data = &msm_i2c_pdata;
5478}
5479
5480static struct msm_i2c_platform_data msm_i2c_2_pdata = {
5481 .clk_freq = 100000,
5482 .rmutex = 1,
5483 .rsl_id = "D:I2C02000022",
5484 .msm_i2c_config_gpio = msm_i2c_gpio_config,
5485};
5486
5487static void __init msm_device_i2c_2_init(void)
5488{
5489 msm_device_i2c_2.dev.platform_data = &msm_i2c_2_pdata;
5490}
5491
5492static struct msm_i2c_platform_data qup_i2c_pdata = {
5493 .clk_freq = 384000,
5494 .pclk = "camif_pad_pclk",
5495 .msm_i2c_config_gpio = qup_i2c_gpio_config,
5496};
5497
5498static void __init qup_device_i2c_init(void)
5499{
5500 if (msm_gpios_request(qup_i2c_gpios_hw, ARRAY_SIZE(qup_i2c_gpios_hw)))
5501 pr_err("failed to request I2C gpios\n");
5502
5503 qup_device_i2c.dev.platform_data = &qup_i2c_pdata;
5504 /*This needs to be enabled only for OEMS*/
5505#ifndef CONFIG_QUP_EXCLUSIVE_TO_CAMERA
5506 qup_vreg = vreg_get(NULL, "lvsw1");
5507 if (IS_ERR(qup_vreg)) {
5508 printk(KERN_ERR "%s: vreg get failed (%ld)\n",
5509 __func__, PTR_ERR(qup_vreg));
5510 }
5511#endif
5512}
5513
5514#ifdef CONFIG_I2C_SSBI
5515static struct msm_i2c_ssbi_platform_data msm_i2c_ssbi6_pdata = {
5516 .rsl_id = "D:PMIC_SSBI",
5517 .controller_type = MSM_SBI_CTRL_SSBI2,
5518};
5519
5520static struct msm_i2c_ssbi_platform_data msm_i2c_ssbi7_pdata = {
5521 .rsl_id = "D:CODEC_SSBI",
5522 .controller_type = MSM_SBI_CTRL_SSBI,
5523};
5524#endif
5525
5526static struct msm_acpu_clock_platform_data msm7x30_clock_data = {
5527 .acpu_switch_time_us = 50,
5528 .vdd_switch_time_us = 62,
Daniel Walker8d747cd2010-02-25 11:37:43 -08005529};
5530
5531static void __init msm7x30_init_irq(void)
5532{
5533 msm_init_irq();
5534}
5535
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07005536static struct msm_gpio msm_nand_ebi2_cfg_data[] = {
5537 {GPIO_CFG(86, 1, GPIO_CFG_OUTPUT, GPIO_CFG_PULL_UP, GPIO_CFG_8MA), "ebi2_cs1"},
5538 {GPIO_CFG(115, 2, GPIO_CFG_OUTPUT, GPIO_CFG_PULL_UP, GPIO_CFG_8MA), "ebi2_busy1"},
5539};
5540
5541struct vreg *vreg_s3;
5542struct vreg *vreg_mmc;
5543
5544#if (defined(CONFIG_MMC_MSM_SDC1_SUPPORT)\
5545 || defined(CONFIG_MMC_MSM_SDC2_SUPPORT)\
5546 || defined(CONFIG_MMC_MSM_SDC3_SUPPORT)\
5547 || defined(CONFIG_MMC_MSM_SDC4_SUPPORT))
5548
5549struct sdcc_gpio {
5550 struct msm_gpio *cfg_data;
5551 uint32_t size;
5552 struct msm_gpio *sleep_cfg_data;
5553};
5554#if defined(CONFIG_MMC_MSM_SDC1_SUPPORT)
5555static struct msm_gpio sdc1_lvlshft_cfg_data[] = {
5556 {GPIO_CFG(35, 1, GPIO_CFG_OUTPUT, GPIO_CFG_PULL_UP, GPIO_CFG_16MA), "sdc1_lvlshft"},
5557};
5558#endif
5559static struct msm_gpio sdc1_cfg_data[] = {
5560 {GPIO_CFG(38, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_16MA), "sdc1_clk"},
5561 {GPIO_CFG(39, 1, GPIO_CFG_OUTPUT, GPIO_CFG_PULL_UP, GPIO_CFG_8MA), "sdc1_cmd"},
5562 {GPIO_CFG(40, 1, GPIO_CFG_OUTPUT, GPIO_CFG_PULL_UP, GPIO_CFG_8MA), "sdc1_dat_3"},
5563 {GPIO_CFG(41, 1, GPIO_CFG_OUTPUT, GPIO_CFG_PULL_UP, GPIO_CFG_8MA), "sdc1_dat_2"},
5564 {GPIO_CFG(42, 1, GPIO_CFG_OUTPUT, GPIO_CFG_PULL_UP, GPIO_CFG_8MA), "sdc1_dat_1"},
5565 {GPIO_CFG(43, 1, GPIO_CFG_OUTPUT, GPIO_CFG_PULL_UP, GPIO_CFG_8MA), "sdc1_dat_0"},
5566};
5567
5568static struct msm_gpio sdc2_cfg_data[] = {
5569 {GPIO_CFG(64, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_16MA), "sdc2_clk"},
5570 {GPIO_CFG(65, 1, GPIO_CFG_OUTPUT, GPIO_CFG_PULL_UP, GPIO_CFG_8MA), "sdc2_cmd"},
5571 {GPIO_CFG(66, 1, GPIO_CFG_OUTPUT, GPIO_CFG_PULL_UP, GPIO_CFG_8MA), "sdc2_dat_3"},
5572 {GPIO_CFG(67, 1, GPIO_CFG_OUTPUT, GPIO_CFG_PULL_UP, GPIO_CFG_8MA), "sdc2_dat_2"},
5573 {GPIO_CFG(68, 1, GPIO_CFG_OUTPUT, GPIO_CFG_PULL_UP, GPIO_CFG_8MA), "sdc2_dat_1"},
5574 {GPIO_CFG(69, 1, GPIO_CFG_OUTPUT, GPIO_CFG_PULL_UP, GPIO_CFG_8MA), "sdc2_dat_0"},
5575
5576#ifdef CONFIG_MMC_MSM_SDC2_8_BIT_SUPPORT
5577 {GPIO_CFG(115, 1, GPIO_CFG_OUTPUT, GPIO_CFG_PULL_UP, GPIO_CFG_8MA), "sdc2_dat_4"},
5578 {GPIO_CFG(114, 1, GPIO_CFG_OUTPUT, GPIO_CFG_PULL_UP, GPIO_CFG_8MA), "sdc2_dat_5"},
5579 {GPIO_CFG(113, 1, GPIO_CFG_OUTPUT, GPIO_CFG_PULL_UP, GPIO_CFG_8MA), "sdc2_dat_6"},
5580 {GPIO_CFG(112, 1, GPIO_CFG_OUTPUT, GPIO_CFG_PULL_UP, GPIO_CFG_8MA), "sdc2_dat_7"},
5581#endif
5582};
5583
5584static struct msm_gpio sdc3_cfg_data[] = {
5585 {GPIO_CFG(110, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_16MA), "sdc3_clk"},
5586 {GPIO_CFG(111, 1, GPIO_CFG_OUTPUT, GPIO_CFG_PULL_UP, GPIO_CFG_8MA), "sdc3_cmd"},
5587 {GPIO_CFG(116, 1, GPIO_CFG_OUTPUT, GPIO_CFG_PULL_UP, GPIO_CFG_8MA), "sdc3_dat_3"},
5588 {GPIO_CFG(117, 1, GPIO_CFG_OUTPUT, GPIO_CFG_PULL_UP, GPIO_CFG_8MA), "sdc3_dat_2"},
5589 {GPIO_CFG(118, 1, GPIO_CFG_OUTPUT, GPIO_CFG_PULL_UP, GPIO_CFG_8MA), "sdc3_dat_1"},
5590 {GPIO_CFG(119, 1, GPIO_CFG_OUTPUT, GPIO_CFG_PULL_UP, GPIO_CFG_8MA), "sdc3_dat_0"},
5591};
5592
5593static struct msm_gpio sdc3_sleep_cfg_data[] = {
5594 {GPIO_CFG(110, 0, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA),
5595 "sdc3_clk"},
5596 {GPIO_CFG(111, 0, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA),
5597 "sdc3_cmd"},
5598 {GPIO_CFG(116, 0, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA),
5599 "sdc3_dat_3"},
5600 {GPIO_CFG(117, 0, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA),
5601 "sdc3_dat_2"},
5602 {GPIO_CFG(118, 0, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA),
5603 "sdc3_dat_1"},
5604 {GPIO_CFG(119, 0, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA),
5605 "sdc3_dat_0"},
5606};
5607
5608static struct msm_gpio sdc4_cfg_data[] = {
5609 {GPIO_CFG(58, 1, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_16MA), "sdc4_clk"},
5610 {GPIO_CFG(59, 1, GPIO_CFG_OUTPUT, GPIO_CFG_PULL_UP, GPIO_CFG_8MA), "sdc4_cmd"},
5611 {GPIO_CFG(60, 1, GPIO_CFG_OUTPUT, GPIO_CFG_PULL_UP, GPIO_CFG_8MA), "sdc4_dat_3"},
5612 {GPIO_CFG(61, 1, GPIO_CFG_OUTPUT, GPIO_CFG_PULL_UP, GPIO_CFG_8MA), "sdc4_dat_2"},
5613 {GPIO_CFG(62, 1, GPIO_CFG_OUTPUT, GPIO_CFG_PULL_UP, GPIO_CFG_8MA), "sdc4_dat_1"},
5614 {GPIO_CFG(63, 1, GPIO_CFG_OUTPUT, GPIO_CFG_PULL_UP, GPIO_CFG_8MA), "sdc4_dat_0"},
5615};
5616
5617static struct sdcc_gpio sdcc_cfg_data[] = {
5618 {
5619 .cfg_data = sdc1_cfg_data,
5620 .size = ARRAY_SIZE(sdc1_cfg_data),
5621 .sleep_cfg_data = NULL,
5622 },
5623 {
5624 .cfg_data = sdc2_cfg_data,
5625 .size = ARRAY_SIZE(sdc2_cfg_data),
5626 .sleep_cfg_data = NULL,
5627 },
5628 {
5629 .cfg_data = sdc3_cfg_data,
5630 .size = ARRAY_SIZE(sdc3_cfg_data),
5631 .sleep_cfg_data = sdc3_sleep_cfg_data,
5632 },
5633 {
5634 .cfg_data = sdc4_cfg_data,
5635 .size = ARRAY_SIZE(sdc4_cfg_data),
5636 .sleep_cfg_data = NULL,
5637 },
5638};
5639
5640struct sdcc_vreg {
5641 struct vreg *vreg_data;
5642 unsigned level;
5643};
5644
5645static struct sdcc_vreg sdcc_vreg_data[4];
5646
5647static unsigned long vreg_sts, gpio_sts;
5648
5649static uint32_t msm_sdcc_setup_gpio(int dev_id, unsigned int enable)
5650{
5651 int rc = 0;
5652 struct sdcc_gpio *curr;
5653
5654 curr = &sdcc_cfg_data[dev_id - 1];
5655
5656 if (!(test_bit(dev_id, &gpio_sts)^enable))
5657 return rc;
5658
5659 if (enable) {
5660 set_bit(dev_id, &gpio_sts);
5661 rc = msm_gpios_request_enable(curr->cfg_data, curr->size);
5662 if (rc)
5663 printk(KERN_ERR "%s: Failed to turn on GPIOs for slot %d\n",
5664 __func__, dev_id);
5665 } else {
5666 clear_bit(dev_id, &gpio_sts);
5667 if (curr->sleep_cfg_data) {
5668 msm_gpios_enable(curr->sleep_cfg_data, curr->size);
5669 msm_gpios_free(curr->sleep_cfg_data, curr->size);
5670 } else {
5671 msm_gpios_disable_free(curr->cfg_data, curr->size);
5672 }
5673 }
5674
5675 return rc;
5676}
5677
5678static uint32_t msm_sdcc_setup_vreg(int dev_id, unsigned int enable)
5679{
5680 int rc = 0;
5681 struct sdcc_vreg *curr;
5682 static int enabled_once[] = {0, 0, 0, 0};
5683
5684 curr = &sdcc_vreg_data[dev_id - 1];
5685
5686 if (!(test_bit(dev_id, &vreg_sts)^enable))
5687 return rc;
5688
5689 if (!enable || enabled_once[dev_id - 1])
5690 return 0;
5691
5692 if (enable) {
5693 set_bit(dev_id, &vreg_sts);
5694 rc = vreg_set_level(curr->vreg_data, curr->level);
5695 if (rc) {
5696 printk(KERN_ERR "%s: vreg_set_level() = %d \n",
5697 __func__, rc);
5698 }
5699 rc = vreg_enable(curr->vreg_data);
5700 if (rc) {
5701 printk(KERN_ERR "%s: vreg_enable() = %d \n",
5702 __func__, rc);
5703 }
5704 enabled_once[dev_id - 1] = 1;
5705 } else {
5706 clear_bit(dev_id, &vreg_sts);
5707 rc = vreg_disable(curr->vreg_data);
5708 if (rc) {
5709 printk(KERN_ERR "%s: vreg_disable() = %d \n",
5710 __func__, rc);
5711 }
5712 }
5713 return rc;
5714}
5715
5716static uint32_t msm_sdcc_setup_power(struct device *dv, unsigned int vdd)
5717{
5718 int rc = 0;
5719 struct platform_device *pdev;
5720
5721 pdev = container_of(dv, struct platform_device, dev);
5722 rc = msm_sdcc_setup_gpio(pdev->id, (vdd ? 1 : 0));
5723 if (rc)
5724 goto out;
5725
5726 if (pdev->id == 4) /* S3 is always ON and cannot be disabled */
5727 rc = msm_sdcc_setup_vreg(pdev->id, (vdd ? 1 : 0));
5728out:
5729 return rc;
5730}
5731
5732#if defined(CONFIG_MMC_MSM_SDC1_SUPPORT) && \
5733 defined(CONFIG_CSDIO_VENDOR_ID) && \
5734 defined(CONFIG_CSDIO_DEVICE_ID) && \
5735 (CONFIG_CSDIO_VENDOR_ID == 0x70 && CONFIG_CSDIO_DEVICE_ID == 0x1117)
5736
5737#define MBP_ON 1
5738#define MBP_OFF 0
5739
5740#define MBP_RESET_N \
5741 GPIO_CFG(44, 0, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_8MA)
5742#define MBP_INT0 \
5743 GPIO_CFG(46, 0, GPIO_CFG_INPUT, GPIO_CFG_PULL_UP, GPIO_CFG_8MA)
5744
5745#define MBP_MODE_CTRL_0 \
5746 GPIO_CFG(35, 0, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA)
5747#define MBP_MODE_CTRL_1 \
5748 GPIO_CFG(36, 0, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA)
5749#define MBP_MODE_CTRL_2 \
5750 GPIO_CFG(34, 0, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA)
5751#define TSIF_EN \
5752 GPIO_CFG(35, 1, GPIO_CFG_INPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA)
5753#define TSIF_DATA \
5754 GPIO_CFG(36, 1, GPIO_CFG_INPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA)
5755#define TSIF_CLK \
5756 GPIO_CFG(34, 1, GPIO_CFG_INPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA)
5757
5758static struct msm_gpio mbp_cfg_data[] = {
5759 {GPIO_CFG(44, 0, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_16MA),
5760 "mbp_reset"},
5761 {GPIO_CFG(85, 0, GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL, GPIO_CFG_16MA),
5762 "mbp_io_voltage"},
5763};
5764
5765static int mbp_config_gpios_pre_init(int enable)
5766{
5767 int rc = 0;
5768
5769 if (enable) {
5770 rc = msm_gpios_request_enable(mbp_cfg_data,
5771 ARRAY_SIZE(mbp_cfg_data));
5772 if (rc) {
5773 printk(KERN_ERR
5774 "%s: Failed to turnon GPIOs for mbp chip(%d)\n",
5775 __func__, rc);
5776 }
5777 } else
5778 msm_gpios_disable_free(mbp_cfg_data, ARRAY_SIZE(mbp_cfg_data));
5779 return rc;
5780}
5781
5782static int mbp_setup_rf_vregs(int state)
5783{
5784 struct vreg *vreg_rf = NULL;
5785 struct vreg *vreg_rf_switch = NULL;
5786 int rc;
5787
5788 vreg_rf = vreg_get(NULL, "s2");
5789 if (IS_ERR(vreg_rf)) {
5790 pr_err("%s: s2 vreg get failed (%ld)",
5791 __func__, PTR_ERR(vreg_rf));
5792 return -EFAULT;
5793 }
5794 vreg_rf_switch = vreg_get(NULL, "rf");
5795 if (IS_ERR(vreg_rf_switch)) {
5796 pr_err("%s: rf vreg get failed (%ld)",
5797 __func__, PTR_ERR(vreg_rf_switch));
5798 return -EFAULT;
5799 }
5800
5801 if (state) {
5802 rc = vreg_set_level(vreg_rf, 1300);
5803 if (rc) {
5804 pr_err("%s: vreg s2 set level failed (%d)\n",
5805 __func__, rc);
5806 return rc;
5807 }
5808
5809 rc = vreg_enable(vreg_rf);
5810 if (rc) {
5811 printk(KERN_ERR "%s: vreg_enable(s2) = %d\n",
5812 __func__, rc);
5813 }
5814
5815 rc = vreg_set_level(vreg_rf_switch, 2600);
5816 if (rc) {
5817 pr_err("%s: vreg rf switch set level failed (%d)\n",
5818 __func__, rc);
5819 return rc;
5820 }
5821 rc = vreg_enable(vreg_rf_switch);
5822 if (rc) {
5823 printk(KERN_ERR "%s: vreg_enable(rf) = %d\n",
5824 __func__, rc);
5825 }
5826 } else {
5827 (void) vreg_disable(vreg_rf);
5828 (void) vreg_disable(vreg_rf_switch);
5829 }
5830 return 0;
5831}
5832
5833static int mbp_setup_vregs(int state)
5834{
5835 struct vreg *vreg_analog = NULL;
5836 struct vreg *vreg_io = NULL;
5837 int rc;
5838
5839 vreg_analog = vreg_get(NULL, "gp4");
5840 if (IS_ERR(vreg_analog)) {
5841 pr_err("%s: gp4 vreg get failed (%ld)",
5842 __func__, PTR_ERR(vreg_analog));
5843 return -EFAULT;
5844 }
5845 vreg_io = vreg_get(NULL, "s3");
5846 if (IS_ERR(vreg_io)) {
5847 pr_err("%s: s3 vreg get failed (%ld)",
5848 __func__, PTR_ERR(vreg_io));
5849 return -EFAULT;
5850 }
5851 if (state) {
5852 rc = vreg_set_level(vreg_analog, 2600);
5853 if (rc) {
5854 pr_err("%s: vreg_set_level failed (%d)",
5855 __func__, rc);
5856 }
5857 rc = vreg_enable(vreg_analog);
5858 if (rc) {
5859 pr_err("%s: analog vreg enable failed (%d)",
5860 __func__, rc);
5861 }
5862 rc = vreg_set_level(vreg_io, 1800);
5863 if (rc) {
5864 pr_err("%s: vreg_set_level failed (%d)",
5865 __func__, rc);
5866 }
5867 rc = vreg_enable(vreg_io);
5868 if (rc) {
5869 pr_err("%s: io vreg enable failed (%d)",
5870 __func__, rc);
5871 }
5872 } else {
5873 rc = vreg_disable(vreg_analog);
5874 if (rc) {
5875 pr_err("%s: analog vreg disable failed (%d)",
5876 __func__, rc);
5877 }
5878 rc = vreg_disable(vreg_io);
5879 if (rc) {
5880 pr_err("%s: io vreg disable failed (%d)",
5881 __func__, rc);
5882 }
5883 }
5884 return rc;
5885}
5886
5887static int mbp_set_tcxo_en(int enable)
5888{
5889 int rc;
5890 const char *id = "UBMC";
5891 struct vreg *vreg_analog = NULL;
5892
5893 rc = pmapp_clock_vote(id, PMAPP_CLOCK_ID_A1,
5894 enable ? PMAPP_CLOCK_VOTE_ON : PMAPP_CLOCK_VOTE_OFF);
5895 if (rc < 0) {
5896 printk(KERN_ERR "%s: unable to %svote for a1 clk\n",
5897 __func__, enable ? "" : "de-");
5898 return -EIO;
5899 }
5900 if (!enable) {
5901 vreg_analog = vreg_get(NULL, "gp4");
5902 if (IS_ERR(vreg_analog)) {
5903 pr_err("%s: gp4 vreg get failed (%ld)",
5904 __func__, PTR_ERR(vreg_analog));
5905 return -EFAULT;
5906 }
5907
5908 (void) vreg_disable(vreg_analog);
5909 }
5910 return rc;
5911}
5912
5913static void mbp_set_freeze_io(int state)
5914{
5915 if (state)
5916 gpio_set_value(85, 0);
5917 else
5918 gpio_set_value(85, 1);
5919}
5920
5921static int mbp_set_core_voltage_en(int enable)
5922{
5923 int rc;
5924 struct vreg *vreg_core1p2 = NULL;
5925
5926 vreg_core1p2 = vreg_get(NULL, "gp16");
5927 if (IS_ERR(vreg_core1p2)) {
5928 pr_err("%s: gp16 vreg get failed (%ld)",
5929 __func__, PTR_ERR(vreg_core1p2));
5930 return -EFAULT;
5931 }
5932 if (enable) {
5933 rc = vreg_set_level(vreg_core1p2, 1200);
5934 if (rc) {
5935 pr_err("%s: vreg_set_level failed (%d)",
5936 __func__, rc);
5937 }
5938 (void) vreg_enable(vreg_core1p2);
5939
5940 return 80;
5941 } else {
5942 gpio_set_value(85, 1);
5943 return 0;
5944 }
5945 return rc;
5946}
5947
5948static void mbp_set_reset(int state)
5949{
5950 if (state)
5951 gpio_set_value(GPIO_PIN(MBP_RESET_N), 0);
5952 else
5953 gpio_set_value(GPIO_PIN(MBP_RESET_N), 1);
5954}
5955
5956static int mbp_config_interface_mode(int state)
5957{
5958 if (state) {
5959 gpio_tlmm_config(MBP_MODE_CTRL_0, GPIO_CFG_ENABLE);
5960 gpio_tlmm_config(MBP_MODE_CTRL_1, GPIO_CFG_ENABLE);
5961 gpio_tlmm_config(MBP_MODE_CTRL_2, GPIO_CFG_ENABLE);
5962 gpio_set_value(GPIO_PIN(MBP_MODE_CTRL_0), 0);
5963 gpio_set_value(GPIO_PIN(MBP_MODE_CTRL_1), 1);
5964 gpio_set_value(GPIO_PIN(MBP_MODE_CTRL_2), 0);
5965 } else {
5966 gpio_tlmm_config(MBP_MODE_CTRL_0, GPIO_CFG_DISABLE);
5967 gpio_tlmm_config(MBP_MODE_CTRL_1, GPIO_CFG_DISABLE);
5968 gpio_tlmm_config(MBP_MODE_CTRL_2, GPIO_CFG_DISABLE);
5969 }
5970 return 0;
5971}
5972
5973static int mbp_setup_adc_vregs(int state)
5974{
5975 struct vreg *vreg_adc = NULL;
5976 int rc;
5977
5978 vreg_adc = vreg_get(NULL, "s4");
5979 if (IS_ERR(vreg_adc)) {
5980 pr_err("%s: s4 vreg get failed (%ld)",
5981 __func__, PTR_ERR(vreg_adc));
5982 return -EFAULT;
5983 }
5984 if (state) {
5985 rc = vreg_set_level(vreg_adc, 2200);
5986 if (rc) {
5987 pr_err("%s: vreg_set_level failed (%d)",
5988 __func__, rc);
5989 }
5990 rc = vreg_enable(vreg_adc);
5991 if (rc) {
5992 pr_err("%s: enable vreg adc failed (%d)",
5993 __func__, rc);
5994 }
5995 } else {
5996 rc = vreg_disable(vreg_adc);
5997 if (rc) {
5998 pr_err("%s: disable vreg adc failed (%d)",
5999 __func__, rc);
6000 }
6001 }
6002 return rc;
6003}
6004
6005static int mbp_power_up(void)
6006{
6007 int rc;
6008
6009 rc = mbp_config_gpios_pre_init(MBP_ON);
6010 if (rc)
6011 goto exit;
6012 pr_debug("%s: mbp_config_gpios_pre_init() done\n", __func__);
6013
6014 rc = mbp_setup_vregs(MBP_ON);
6015 if (rc)
6016 goto exit;
6017 pr_debug("%s: gp4 (2.6) and s3 (1.8) done\n", __func__);
6018
6019 rc = mbp_set_tcxo_en(MBP_ON);
6020 if (rc)
6021 goto exit;
6022 pr_debug("%s: tcxo clock done\n", __func__);
6023
6024 mbp_set_freeze_io(MBP_OFF);
6025 pr_debug("%s: set gpio 85 to 1 done\n", __func__);
6026
6027 udelay(100);
6028 mbp_set_reset(MBP_ON);
6029
6030 udelay(300);
6031 rc = mbp_config_interface_mode(MBP_ON);
6032 if (rc)
6033 goto exit;
6034 pr_debug("%s: mbp_config_interface_mode() done\n", __func__);
6035
6036 udelay(100 + mbp_set_core_voltage_en(MBP_ON));
6037 pr_debug("%s: power gp16 1.2V done\n", __func__);
6038
6039 mbp_set_freeze_io(MBP_ON);
6040 pr_debug("%s: set gpio 85 to 0 done\n", __func__);
6041
6042 udelay(100);
6043
6044 rc = mbp_setup_rf_vregs(MBP_ON);
6045 if (rc)
6046 goto exit;
6047 pr_debug("%s: s2 1.3V and rf 2.6V done\n", __func__);
6048
6049 rc = mbp_setup_adc_vregs(MBP_ON);
6050 if (rc)
6051 goto exit;
6052 pr_debug("%s: s4 2.2V done\n", __func__);
6053
6054 udelay(200);
6055
6056 mbp_set_reset(MBP_OFF);
6057 pr_debug("%s: close gpio 44 done\n", __func__);
6058
6059 msleep(20);
6060exit:
6061 return rc;
6062}
6063
6064static int mbp_power_down(void)
6065{
6066 int rc;
6067 struct vreg *vreg_adc = NULL;
6068
6069 vreg_adc = vreg_get(NULL, "s4");
6070 if (IS_ERR(vreg_adc)) {
6071 pr_err("%s: s4 vreg get failed (%ld)",
6072 __func__, PTR_ERR(vreg_adc));
6073 return -EFAULT;
6074 }
6075
6076 mbp_set_reset(MBP_ON);
6077 pr_debug("%s: mbp_set_reset(MBP_ON) done\n", __func__);
6078
6079 udelay(100);
6080
6081 rc = mbp_setup_adc_vregs(MBP_OFF);
6082 if (rc)
6083 goto exit;
6084 pr_debug("%s: vreg_disable(vreg_adc) done\n", __func__);
6085
6086 udelay(5);
6087
6088 rc = mbp_setup_rf_vregs(MBP_OFF);
6089 if (rc)
6090 goto exit;
6091 pr_debug("%s: mbp_setup_rf_vregs(MBP_OFF) done\n", __func__);
6092
6093 udelay(5);
6094
6095 mbp_set_freeze_io(MBP_OFF);
6096 pr_debug("%s: mbp_set_freeze_io(MBP_OFF) done\n", __func__);
6097
6098 udelay(100);
6099 rc = mbp_set_core_voltage_en(MBP_OFF);
6100 if (rc)
6101 goto exit;
6102 pr_debug("%s: mbp_set_core_voltage_en(MBP_OFF) done\n", __func__);
6103
6104 gpio_set_value(85, 1);
6105
6106 rc = mbp_set_tcxo_en(MBP_OFF);
6107 if (rc)
6108 goto exit;
6109 pr_debug("%s: mbp_set_tcxo_en(MBP_OFF) done\n", __func__);
6110
6111 rc = mbp_config_gpios_pre_init(MBP_OFF);
6112 if (rc)
6113 goto exit;
6114exit:
6115 return rc;
6116}
6117
6118static void (*mbp_status_notify_cb)(int card_present, void *dev_id);
6119static void *mbp_status_notify_cb_devid;
6120static int mbp_power_status;
6121static int mbp_power_init_done;
6122
6123static uint32_t mbp_setup_power(struct device *dv,
6124 unsigned int power_status)
6125{
6126 int rc = 0;
6127 struct platform_device *pdev;
6128
6129 pdev = container_of(dv, struct platform_device, dev);
6130
6131 if (power_status == mbp_power_status)
6132 goto exit;
6133 if (power_status) {
6134 pr_debug("turn on power of mbp slot");
6135 rc = mbp_power_up();
6136 mbp_power_status = 1;
6137 } else {
6138 pr_debug("turn off power of mbp slot");
6139 rc = mbp_power_down();
6140 mbp_power_status = 0;
6141 }
6142exit:
6143 return rc;
6144};
6145
6146int mbp_register_status_notify(void (*callback)(int, void *),
6147 void *dev_id)
6148{
6149 mbp_status_notify_cb = callback;
6150 mbp_status_notify_cb_devid = dev_id;
6151 return 0;
6152}
6153
6154static unsigned int mbp_status(struct device *dev)
6155{
6156 return mbp_power_status;
6157}
6158
6159static uint32_t msm_sdcc_setup_power_mbp(struct device *dv, unsigned int vdd)
6160{
6161 struct platform_device *pdev;
6162 uint32_t rc = 0;
6163
6164 pdev = container_of(dv, struct platform_device, dev);
6165 rc = msm_sdcc_setup_power(dv, vdd);
6166 if (rc) {
6167 pr_err("%s: Failed to setup power (%d)\n",
6168 __func__, rc);
6169 goto out;
6170 }
6171 if (!mbp_power_init_done) {
6172 mbp_setup_power(dv, 1);
6173 mbp_setup_power(dv, 0);
6174 mbp_power_init_done = 1;
6175 }
6176 if (vdd >= 0x8000) {
6177 rc = mbp_setup_power(dv, (0x8000 == vdd) ? 0 : 1);
6178 if (rc) {
6179 pr_err("%s: Failed to config mbp chip power (%d)\n",
6180 __func__, rc);
6181 goto out;
6182 }
6183 if (mbp_status_notify_cb) {
6184 mbp_status_notify_cb(mbp_power_status,
6185 mbp_status_notify_cb_devid);
6186 }
6187 }
6188out:
6189 /* should return 0 only */
6190 return 0;
6191}
6192
6193#endif
6194
6195#endif
6196
6197#ifdef CONFIG_MMC_MSM_SDC4_SUPPORT
6198#ifdef CONFIG_MMC_MSM_CARD_HW_DETECTION
6199static unsigned int msm7x30_sdcc_slot_status(struct device *dev)
6200{
6201 return (unsigned int)
6202 gpio_get_value_cansleep(
6203 PM8058_GPIO_PM_TO_SYS(PMIC_GPIO_SD_DET - 1));
6204}
6205#endif
6206
6207static int msm_sdcc_get_wpswitch(struct device *dv)
6208{
6209 void __iomem *wp_addr = 0;
6210 uint32_t ret = 0;
6211 struct platform_device *pdev;
6212
6213 if (!(machine_is_msm7x30_surf()))
6214 return -1;
6215 pdev = container_of(dv, struct platform_device, dev);
6216
6217 wp_addr = ioremap(FPGA_SDCC_STATUS, 4);
6218 if (!wp_addr) {
6219 pr_err("%s: Could not remap %x\n", __func__, FPGA_SDCC_STATUS);
6220 return -ENOMEM;
6221 }
6222
6223 ret = (((readl(wp_addr) >> 4) >> (pdev->id-1)) & 0x01);
6224 pr_info("%s: WP Status for Slot %d = 0x%x \n", __func__,
6225 pdev->id, ret);
6226 iounmap(wp_addr);
6227
6228 return ret;
6229}
6230#endif
6231
6232#if defined(CONFIG_MMC_MSM_SDC1_SUPPORT)
6233#if defined(CONFIG_CSDIO_VENDOR_ID) && \
6234 defined(CONFIG_CSDIO_DEVICE_ID) && \
6235 (CONFIG_CSDIO_VENDOR_ID == 0x70 && CONFIG_CSDIO_DEVICE_ID == 0x1117)
6236static struct mmc_platform_data msm7x30_sdc1_data = {
6237 .ocr_mask = MMC_VDD_165_195 | MMC_VDD_27_28 | MMC_VDD_28_29,
6238 .translate_vdd = msm_sdcc_setup_power_mbp,
6239 .mmc_bus_width = MMC_CAP_4_BIT_DATA,
6240 .status = mbp_status,
6241 .register_status_notify = mbp_register_status_notify,
6242#ifdef CONFIG_MMC_MSM_SDC1_DUMMY52_REQUIRED
6243 .dummy52_required = 1,
6244#endif
6245 .msmsdcc_fmin = 144000,
6246 .msmsdcc_fmid = 24576000,
6247 .msmsdcc_fmax = 24576000,
6248 .nonremovable = 0,
6249};
6250#else
6251static struct mmc_platform_data msm7x30_sdc1_data = {
6252 .ocr_mask = MMC_VDD_165_195,
6253 .translate_vdd = msm_sdcc_setup_power,
6254 .mmc_bus_width = MMC_CAP_4_BIT_DATA,
6255#ifdef CONFIG_MMC_MSM_SDC1_DUMMY52_REQUIRED
6256 .dummy52_required = 1,
6257#endif
6258 .msmsdcc_fmin = 144000,
6259 .msmsdcc_fmid = 24576000,
6260 .msmsdcc_fmax = 49152000,
6261 .nonremovable = 0,
6262};
6263#endif
6264#endif
6265
6266#ifdef CONFIG_MMC_MSM_SDC2_SUPPORT
6267static struct mmc_platform_data msm7x30_sdc2_data = {
6268 .ocr_mask = MMC_VDD_165_195 | MMC_VDD_27_28,
6269 .translate_vdd = msm_sdcc_setup_power,
6270#ifdef CONFIG_MMC_MSM_SDC2_8_BIT_SUPPORT
6271 .mmc_bus_width = MMC_CAP_8_BIT_DATA,
6272#else
6273 .mmc_bus_width = MMC_CAP_4_BIT_DATA,
6274#endif
6275#ifdef CONFIG_MMC_MSM_SDC2_DUMMY52_REQUIRED
6276 .dummy52_required = 1,
6277#endif
6278 .msmsdcc_fmin = 144000,
6279 .msmsdcc_fmid = 24576000,
6280 .msmsdcc_fmax = 49152000,
6281 .nonremovable = 1,
6282};
6283#endif
6284
6285#ifdef CONFIG_MMC_MSM_SDC3_SUPPORT
6286static struct mmc_platform_data msm7x30_sdc3_data = {
6287 .ocr_mask = MMC_VDD_27_28 | MMC_VDD_28_29,
6288 .translate_vdd = msm_sdcc_setup_power,
6289 .mmc_bus_width = MMC_CAP_4_BIT_DATA,
6290#ifdef CONFIG_MMC_MSM_SDIO_SUPPORT
6291 .sdiowakeup_irq = MSM_GPIO_TO_INT(118),
6292#endif
6293#ifdef CONFIG_MMC_MSM_SDC3_DUMMY52_REQUIRED
6294 .dummy52_required = 1,
6295#endif
6296 .msmsdcc_fmin = 144000,
6297 .msmsdcc_fmid = 24576000,
6298 .msmsdcc_fmax = 49152000,
6299 .nonremovable = 0,
6300};
6301#endif
6302
6303#ifdef CONFIG_MMC_MSM_SDC4_SUPPORT
6304static struct mmc_platform_data msm7x30_sdc4_data = {
6305 .ocr_mask = MMC_VDD_27_28 | MMC_VDD_28_29,
6306 .translate_vdd = msm_sdcc_setup_power,
6307 .mmc_bus_width = MMC_CAP_4_BIT_DATA,
6308#ifdef CONFIG_MMC_MSM_CARD_HW_DETECTION
6309 .status = msm7x30_sdcc_slot_status,
6310 .status_irq = PM8058_GPIO_IRQ(PMIC8058_IRQ_BASE, PMIC_GPIO_SD_DET - 1),
6311 .irq_flags = IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING,
6312#endif
6313 .wpswitch = msm_sdcc_get_wpswitch,
6314#ifdef CONFIG_MMC_MSM_SDC4_DUMMY52_REQUIRED
6315 .dummy52_required = 1,
6316#endif
6317 .msmsdcc_fmin = 144000,
6318 .msmsdcc_fmid = 24576000,
6319 .msmsdcc_fmax = 49152000,
6320 .nonremovable = 0,
6321};
6322#endif
6323
6324#ifdef CONFIG_MMC_MSM_SDC1_SUPPORT
6325static void msm_sdc1_lvlshft_enable(void)
6326{
6327 int rc;
6328
6329 /* Enable LDO5, an input to the FET that powers slot 1 */
6330 rc = vreg_set_level(vreg_mmc, 2850);
6331 if (rc)
6332 printk(KERN_ERR "%s: vreg_set_level() = %d \n", __func__, rc);
6333
6334 rc = vreg_enable(vreg_mmc);
6335 if (rc)
6336 printk(KERN_ERR "%s: vreg_enable() = %d \n", __func__, rc);
6337
6338 /* Enable GPIO 35, to turn on the FET that powers slot 1 */
6339 rc = msm_gpios_request_enable(sdc1_lvlshft_cfg_data,
6340 ARRAY_SIZE(sdc1_lvlshft_cfg_data));
6341 if (rc)
6342 printk(KERN_ERR "%s: Failed to enable GPIO 35\n", __func__);
6343
6344 rc = gpio_direction_output(GPIO_PIN(sdc1_lvlshft_cfg_data[0].gpio_cfg),
6345 1);
6346 if (rc)
6347 printk(KERN_ERR "%s: Failed to turn on GPIO 35\n", __func__);
6348}
6349#endif
6350
6351static void __init msm7x30_init_mmc(void)
6352{
6353 vreg_s3 = vreg_get(NULL, "s3");
6354 if (IS_ERR(vreg_s3)) {
6355 printk(KERN_ERR "%s: vreg get failed (%ld)\n",
6356 __func__, PTR_ERR(vreg_s3));
6357 return;
6358 }
6359
6360 vreg_mmc = vreg_get(NULL, "mmc");
6361 if (IS_ERR(vreg_mmc)) {
6362 printk(KERN_ERR "%s: vreg get failed (%ld)\n",
6363 __func__, PTR_ERR(vreg_mmc));
6364 return;
6365 }
6366
6367#ifdef CONFIG_MMC_MSM_SDC1_SUPPORT
6368 if (machine_is_msm7x30_fluid()) {
6369 msm7x30_sdc1_data.ocr_mask = MMC_VDD_27_28 | MMC_VDD_28_29;
6370 msm_sdc1_lvlshft_enable();
6371 }
6372 sdcc_vreg_data[0].vreg_data = vreg_s3;
6373 sdcc_vreg_data[0].level = 1800;
6374 msm_add_sdcc(1, &msm7x30_sdc1_data);
6375#endif
6376#ifdef CONFIG_MMC_MSM_SDC2_SUPPORT
6377 if (machine_is_msm8x55_svlte_surf())
6378 msm7x30_sdc2_data.msmsdcc_fmax = 24576000;
6379 sdcc_vreg_data[1].vreg_data = vreg_s3;
6380 sdcc_vreg_data[1].level = 1800;
6381 msm_add_sdcc(2, &msm7x30_sdc2_data);
6382#endif
6383#ifdef CONFIG_MMC_MSM_SDC3_SUPPORT
6384 sdcc_vreg_data[2].vreg_data = vreg_s3;
6385 sdcc_vreg_data[2].level = 1800;
6386 msm_sdcc_setup_gpio(3, 1);
6387 msm_add_sdcc(3, &msm7x30_sdc3_data);
6388#endif
6389#ifdef CONFIG_MMC_MSM_SDC4_SUPPORT
6390 sdcc_vreg_data[3].vreg_data = vreg_mmc;
6391 sdcc_vreg_data[3].level = 2850;
6392 msm_add_sdcc(4, &msm7x30_sdc4_data);
6393#endif
6394
6395}
6396
6397static void __init msm7x30_init_nand(void)
6398{
6399 char *build_id;
6400 struct flash_platform_data *plat_data;
6401
6402 build_id = socinfo_get_build_id();
6403 if (build_id == NULL) {
6404 pr_err("%s: Build ID not available from socinfo\n", __func__);
6405 return;
6406 }
6407
6408 if (build_id[8] == 'C' &&
6409 !msm_gpios_request_enable(msm_nand_ebi2_cfg_data,
6410 ARRAY_SIZE(msm_nand_ebi2_cfg_data))) {
6411 plat_data = msm_device_nand.dev.platform_data;
6412 plat_data->interleave = 1;
6413 printk(KERN_INFO "%s: Interleave mode Build ID found\n",
6414 __func__);
6415 }
6416}
6417
6418#ifdef CONFIG_SERIAL_MSM_CONSOLE
6419static struct msm_gpio uart2_config_data[] = {
6420 { GPIO_CFG(49, 2, GPIO_CFG_OUTPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA), "UART2_RFR"},
6421 { GPIO_CFG(50, 2, GPIO_CFG_INPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA), "UART2_CTS"},
6422 { GPIO_CFG(51, 2, GPIO_CFG_INPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA), "UART2_Rx"},
6423 { GPIO_CFG(52, 2, GPIO_CFG_OUTPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA), "UART2_Tx"},
6424};
6425
6426static void msm7x30_init_uart2(void)
6427{
6428 msm_gpios_request_enable(uart2_config_data,
6429 ARRAY_SIZE(uart2_config_data));
6430
6431}
6432#endif
6433
6434/* TSIF begin */
6435#if defined(CONFIG_TSIF) || defined(CONFIG_TSIF_MODULE)
6436
6437#define TSIF_B_SYNC GPIO_CFG(37, 1, GPIO_CFG_INPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA)
6438#define TSIF_B_DATA GPIO_CFG(36, 1, GPIO_CFG_INPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA)
6439#define TSIF_B_EN GPIO_CFG(35, 1, GPIO_CFG_INPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA)
6440#define TSIF_B_CLK GPIO_CFG(34, 1, GPIO_CFG_INPUT, GPIO_CFG_PULL_DOWN, GPIO_CFG_2MA)
6441
6442static const struct msm_gpio tsif_gpios[] = {
6443 { .gpio_cfg = TSIF_B_CLK, .label = "tsif_clk", },
6444 { .gpio_cfg = TSIF_B_EN, .label = "tsif_en", },
6445 { .gpio_cfg = TSIF_B_DATA, .label = "tsif_data", },
6446 { .gpio_cfg = TSIF_B_SYNC, .label = "tsif_sync", },
6447};
6448
6449static struct msm_tsif_platform_data tsif_platform_data = {
6450 .num_gpios = ARRAY_SIZE(tsif_gpios),
6451 .gpios = tsif_gpios,
6452 .tsif_pclk = "tsif_pclk",
6453 .tsif_ref_clk = "tsif_ref_clk",
6454};
6455#endif /* defined(CONFIG_TSIF) || defined(CONFIG_TSIF_MODULE) */
6456/* TSIF end */
6457
6458static void __init pmic8058_leds_init(void)
6459{
6460 if (machine_is_msm7x30_surf()) {
6461 pm8058_7x30_data.sub_devices[PM8058_SUBDEV_LED].platform_data
6462 = &pm8058_surf_leds_data;
6463 } else if (!machine_is_msm7x30_fluid()) {
6464 pm8058_7x30_data.sub_devices[PM8058_SUBDEV_LED].platform_data
6465 = &pm8058_ffa_leds_data;
6466 } else if (machine_is_msm7x30_fluid()) {
6467 pm8058_7x30_data.sub_devices[PM8058_SUBDEV_LED].platform_data
6468 = &pm8058_fluid_leds_data;
6469 }
6470}
6471
6472static struct msm_spm_platform_data msm_spm_data __initdata = {
6473 .reg_base_addr = MSM_SAW_BASE,
6474
6475 .reg_init_values[MSM_SPM_REG_SAW_CFG] = 0x05,
6476 .reg_init_values[MSM_SPM_REG_SAW_SPM_CTL] = 0x18,
6477 .reg_init_values[MSM_SPM_REG_SAW_SPM_SLP_TMR_DLY] = 0x00006666,
6478 .reg_init_values[MSM_SPM_REG_SAW_SPM_WAKE_TMR_DLY] = 0xFF000666,
6479
6480 .reg_init_values[MSM_SPM_REG_SAW_SLP_CLK_EN] = 0x01,
6481 .reg_init_values[MSM_SPM_REG_SAW_SLP_HSFS_PRECLMP_EN] = 0x03,
6482 .reg_init_values[MSM_SPM_REG_SAW_SLP_HSFS_POSTCLMP_EN] = 0x00,
6483
6484 .reg_init_values[MSM_SPM_REG_SAW_SLP_CLMP_EN] = 0x01,
6485 .reg_init_values[MSM_SPM_REG_SAW_SLP_RST_EN] = 0x00,
6486 .reg_init_values[MSM_SPM_REG_SAW_SPM_MPM_CFG] = 0x00,
6487
6488 .awake_vlevel = 0xF2,
6489 .retention_vlevel = 0xE0,
6490 .collapse_vlevel = 0x72,
6491 .retention_mid_vlevel = 0xE0,
6492 .collapse_mid_vlevel = 0xE0,
6493
6494 .vctl_timeout_us = 50,
6495};
6496
6497#if defined(CONFIG_TOUCHSCREEN_TSC2007) || \
6498 defined(CONFIG_TOUCHSCREEN_TSC2007_MODULE)
6499
6500#define TSC2007_TS_PEN_INT 20
6501
6502static struct msm_gpio tsc2007_config_data[] = {
6503 { GPIO_CFG(TSC2007_TS_PEN_INT, 0, GPIO_CFG_INPUT, GPIO_CFG_NO_PULL, GPIO_CFG_2MA),
6504 "tsc2007_irq" },
6505};
6506
6507static struct vreg *vreg_tsc_s3;
6508static struct vreg *vreg_tsc_s2;
6509
6510static int tsc2007_init(void)
6511{
6512 int rc;
6513
6514 vreg_tsc_s3 = vreg_get(NULL, "s3");
6515 if (IS_ERR(vreg_tsc_s3)) {
6516 printk(KERN_ERR "%s: vreg get failed (%ld)\n",
6517 __func__, PTR_ERR(vreg_tsc_s3));
6518 return -ENODEV;
6519 }
6520
6521 rc = vreg_set_level(vreg_tsc_s3, 1800);
6522 if (rc) {
6523 pr_err("%s: vreg_set_level failed \n", __func__);
6524 goto fail_vreg_set_level;
6525 }
6526
6527 rc = vreg_enable(vreg_tsc_s3);
6528 if (rc) {
6529 pr_err("%s: vreg_enable failed \n", __func__);
6530 goto fail_vreg_set_level;
6531 }
6532
6533 vreg_tsc_s2 = vreg_get(NULL, "s2");
6534 if (IS_ERR(vreg_tsc_s2)) {
6535 printk(KERN_ERR "%s: vreg get failed (%ld)\n",
6536 __func__, PTR_ERR(vreg_tsc_s2));
6537 goto fail_vreg_get;
6538 }
6539
6540 rc = vreg_set_level(vreg_tsc_s2, 1300);
6541 if (rc) {
6542 pr_err("%s: vreg_set_level failed \n", __func__);
6543 goto fail_vreg_s2_level;
6544 }
6545
6546 rc = vreg_enable(vreg_tsc_s2);
6547 if (rc) {
6548 pr_err("%s: vreg_enable failed \n", __func__);
6549 goto fail_vreg_s2_level;
6550 }
6551
6552 rc = msm_gpios_request_enable(tsc2007_config_data,
6553 ARRAY_SIZE(tsc2007_config_data));
6554 if (rc) {
6555 pr_err("%s: Unable to request gpios\n", __func__);
6556 goto fail_gpio_req;
6557 }
6558
6559 return 0;
6560
6561fail_gpio_req:
6562 vreg_disable(vreg_tsc_s2);
6563fail_vreg_s2_level:
6564 vreg_put(vreg_tsc_s2);
6565fail_vreg_get:
6566 vreg_disable(vreg_tsc_s3);
6567fail_vreg_set_level:
6568 vreg_put(vreg_tsc_s3);
6569 return rc;
6570}
6571
6572static int tsc2007_get_pendown_state(void)
6573{
6574 int rc;
6575
6576 rc = gpio_get_value(TSC2007_TS_PEN_INT);
6577 if (rc < 0) {
6578 pr_err("%s: MSM GPIO %d read failed\n", __func__,
6579 TSC2007_TS_PEN_INT);
6580 return rc;
6581 }
6582
6583 return (rc == 0 ? 1 : 0);
6584}
6585
6586static void tsc2007_exit(void)
6587{
6588 vreg_disable(vreg_tsc_s3);
6589 vreg_put(vreg_tsc_s3);
6590 vreg_disable(vreg_tsc_s2);
6591 vreg_put(vreg_tsc_s2);
6592
6593 msm_gpios_disable_free(tsc2007_config_data,
6594 ARRAY_SIZE(tsc2007_config_data));
6595}
6596
6597static int tsc2007_power_shutdown(bool enable)
6598{
6599 int rc;
6600
6601 if (enable == false) {
6602 rc = vreg_enable(vreg_tsc_s2);
6603 if (rc) {
6604 pr_err("%s: vreg_enable failed\n", __func__);
6605 return rc;
6606 }
6607 rc = vreg_enable(vreg_tsc_s3);
6608 if (rc) {
6609 pr_err("%s: vreg_enable failed\n", __func__);
6610 vreg_disable(vreg_tsc_s2);
6611 return rc;
6612 }
6613 /* Voltage settling delay */
6614 msleep(20);
6615 } else {
6616 rc = vreg_disable(vreg_tsc_s2);
6617 if (rc) {
6618 pr_err("%s: vreg_disable failed\n", __func__);
6619 return rc;
6620 }
6621 rc = vreg_disable(vreg_tsc_s3);
6622 if (rc) {
6623 pr_err("%s: vreg_disable failed\n", __func__);
6624 vreg_enable(vreg_tsc_s2);
6625 return rc;
6626 }
6627 }
6628
6629 return rc;
6630}
6631
6632static struct tsc2007_platform_data tsc2007_ts_data = {
6633 .model = 2007,
6634 .x_plate_ohms = 300,
6635 .irq_flags = IRQF_TRIGGER_LOW,
6636 .init_platform_hw = tsc2007_init,
6637 .exit_platform_hw = tsc2007_exit,
6638 .power_shutdown = tsc2007_power_shutdown,
6639 .invert_x = true,
6640 .invert_y = true,
6641 /* REVISIT: Temporary fix for reversed pressure */
6642 .invert_z1 = true,
6643 .invert_z2 = true,
6644 .get_pendown_state = tsc2007_get_pendown_state,
6645};
6646
6647static struct i2c_board_info tsc_i2c_board_info[] = {
6648 {
6649 I2C_BOARD_INFO("tsc2007", 0x48),
6650 .irq = MSM_GPIO_TO_INT(TSC2007_TS_PEN_INT),
6651 .platform_data = &tsc2007_ts_data,
6652 },
6653};
6654#endif
6655
6656static const char *vregs_isa1200_name[] = {
6657 "gp7",
6658 "gp10",
6659};
6660
6661static const int vregs_isa1200_val[] = {
6662 1800,
6663 2600,
6664};
6665static struct vreg *vregs_isa1200[ARRAY_SIZE(vregs_isa1200_name)];
6666
6667static int isa1200_power(int vreg_on)
6668{
6669 int i, rc = 0;
6670
6671 for (i = 0; i < ARRAY_SIZE(vregs_isa1200_name); i++) {
6672 if (!vregs_isa1200[i]) {
6673 pr_err("%s: vreg_get %s failed (%d)\n",
6674 __func__, vregs_isa1200_name[i], rc);
6675 goto vreg_fail;
6676 }
6677
6678 rc = vreg_on ? vreg_enable(vregs_isa1200[i]) :
6679 vreg_disable(vregs_isa1200[i]);
6680 if (rc < 0) {
6681 pr_err("%s: vreg %s %s failed (%d)\n",
6682 __func__, vregs_isa1200_name[i],
6683 vreg_on ? "enable" : "disable", rc);
6684 goto vreg_fail;
6685 }
6686 }
6687
6688 /* vote for DO buffer */
6689 rc = pmapp_clock_vote("VIBR", PMAPP_CLOCK_ID_DO,
6690 vreg_on ? PMAPP_CLOCK_VOTE_ON : PMAPP_CLOCK_VOTE_OFF);
6691 if (rc) {
6692 pr_err("%s: unable to %svote for d0 clk\n",
6693 __func__, vreg_on ? "" : "de-");
6694 goto vreg_fail;
6695 }
6696
6697 return 0;
6698
6699vreg_fail:
6700 while (i)
6701 vreg_disable(vregs_isa1200[--i]);
6702 return rc;
6703}
6704
6705static int isa1200_dev_setup(bool enable)
6706{
6707 int i, rc;
6708
6709 if (enable == true) {
6710 for (i = 0; i < ARRAY_SIZE(vregs_isa1200_name); i++) {
6711 vregs_isa1200[i] = vreg_get(NULL,
6712 vregs_isa1200_name[i]);
6713 if (IS_ERR(vregs_isa1200[i])) {
6714 pr_err("%s: vreg get %s failed (%ld)\n",
6715 __func__, vregs_isa1200_name[i],
6716 PTR_ERR(vregs_isa1200[i]));
6717 rc = PTR_ERR(vregs_isa1200[i]);
6718 goto vreg_get_fail;
6719 }
6720 rc = vreg_set_level(vregs_isa1200[i],
6721 vregs_isa1200_val[i]);
6722 if (rc) {
6723 pr_err("%s: vreg_set_level() = %d\n",
6724 __func__, rc);
6725 goto vreg_get_fail;
6726 }
6727 }
6728
6729 rc = gpio_tlmm_config(GPIO_CFG(HAP_LVL_SHFT_MSM_GPIO, 0,
6730 GPIO_CFG_OUTPUT, GPIO_CFG_NO_PULL,
6731 GPIO_CFG_2MA), GPIO_CFG_ENABLE);
6732 if (rc) {
6733 pr_err("%s: Could not configure gpio %d\n",
6734 __func__, HAP_LVL_SHFT_MSM_GPIO);
6735 goto vreg_get_fail;
6736 }
6737
6738 rc = gpio_request(HAP_LVL_SHFT_MSM_GPIO, "haptics_shft_lvl_oe");
6739 if (rc) {
6740 pr_err("%s: unable to request gpio %d (%d)\n",
6741 __func__, HAP_LVL_SHFT_MSM_GPIO, rc);
6742 goto vreg_get_fail;
6743 }
6744
6745 gpio_set_value(HAP_LVL_SHFT_MSM_GPIO, 1);
6746 } else {
6747 for (i = 0; i < ARRAY_SIZE(vregs_isa1200_name); i++)
6748 vreg_put(vregs_isa1200[i]);
6749
6750 gpio_free(HAP_LVL_SHFT_MSM_GPIO);
6751 }
6752
6753 return 0;
6754vreg_get_fail:
6755 while (i)
6756 vreg_put(vregs_isa1200[--i]);
6757 return rc;
6758}
6759static struct isa1200_platform_data isa1200_1_pdata = {
6760 .name = "vibrator",
6761 .power_on = isa1200_power,
6762 .dev_setup = isa1200_dev_setup,
6763 .pwm_ch_id = 1, /*channel id*/
6764 /*gpio to enable haptic*/
6765 .hap_en_gpio = PM8058_GPIO_PM_TO_SYS(PMIC_GPIO_HAP_ENABLE),
6766 .max_timeout = 15000,
6767 .mode_ctrl = PWM_GEN_MODE,
6768 .pwm_fd = {
6769 .pwm_div = 256,
6770 },
6771 .is_erm = false,
6772 .smart_en = true,
6773 .ext_clk_en = true,
6774 .chip_en = 1,
6775};
6776
6777static struct i2c_board_info msm_isa1200_board_info[] = {
6778 {
6779 I2C_BOARD_INFO("isa1200_1", 0x90>>1),
6780 .platform_data = &isa1200_1_pdata,
6781 },
6782};
6783
6784
6785static int kp_flip_mpp_config(void)
6786{
6787 return pm8058_mpp_config_digital_in(PM_FLIP_MPP,
6788 PM8058_MPP_DIG_LEVEL_S3, PM_MPP_DIN_TO_INT);
6789}
6790
6791static struct flip_switch_pdata flip_switch_data = {
6792 .name = "kp_flip_switch",
6793 .flip_gpio = PM8058_GPIO_PM_TO_SYS(PM8058_GPIOS) + PM_FLIP_MPP,
6794 .left_key = KEY_OPEN,
6795 .right_key = KEY_CLOSE,
6796 .active_low = 0,
6797 .wakeup = 1,
6798 .flip_mpp_config = kp_flip_mpp_config,
6799};
6800
6801static struct platform_device flip_switch_device = {
6802 .name = "kp_flip_switch",
6803 .id = -1,
6804 .dev = {
6805 .platform_data = &flip_switch_data,
6806 }
6807};
6808
6809static const char *vregs_tma300_name[] = {
6810 "gp6",
6811 "gp7",
6812};
6813
6814static const int vregs_tma300_val[] = {
6815 3050,
6816 1800,
6817};
6818static struct vreg *vregs_tma300[ARRAY_SIZE(vregs_tma300_name)];
6819
6820static int tma300_power(int vreg_on)
6821{
6822 int i, rc = -EINVAL;
6823
6824 for (i = 0; i < ARRAY_SIZE(vregs_tma300_name); i++) {
6825 /* Never disable gp6 for fluid as lcd has a problem with it */
6826 if (!i && !vreg_on)
6827 continue;
6828 if (!vregs_tma300[i]) {
6829 printk(KERN_ERR "%s: vreg_get %s failed (%d)\n",
6830 __func__, vregs_tma300_name[i], rc);
6831 return rc;
6832 }
6833
6834 rc = vreg_on ? vreg_enable(vregs_tma300[i]) :
6835 vreg_disable(vregs_tma300[i]);
6836 if (rc < 0) {
6837 printk(KERN_ERR "%s: vreg %s %s failed (%d)\n",
6838 __func__, vregs_tma300_name[i],
6839 vreg_on ? "enable" : "disable", rc);
6840 return rc;
6841 }
6842 }
6843
6844 return 0;
6845}
6846
6847#define TS_GPIO_IRQ 150
6848
6849static int tma300_dev_setup(bool enable)
6850{
6851 int i, rc;
6852
6853 if (enable) {
6854 /* get voltage sources */
6855 for (i = 0; i < ARRAY_SIZE(vregs_tma300_name); i++) {
6856 vregs_tma300[i] = vreg_get(NULL, vregs_tma300_name[i]);
6857 if (IS_ERR(vregs_tma300[i])) {
6858 pr_err("%s: vreg get %s failed (%ld)\n",
6859 __func__, vregs_tma300_name[i],
6860 PTR_ERR(vregs_tma300[i]));
6861 rc = PTR_ERR(vregs_tma300[i]);
6862 goto vreg_get_fail;
6863 }
6864 rc = vreg_set_level(vregs_tma300[i],
6865 vregs_tma300_val[i]);
6866 if (rc) {
6867 pr_err("%s: vreg_set_level() = %d\n",
6868 __func__, rc);
6869 i++;
6870 goto vreg_get_fail;
6871 }
6872 }
6873
6874 /* enable interrupt gpio */
6875 rc = gpio_tlmm_config(GPIO_CFG(TS_GPIO_IRQ, 0, GPIO_CFG_INPUT,
6876 GPIO_CFG_PULL_UP, GPIO_CFG_6MA), GPIO_CFG_ENABLE);
6877 if (rc) {
6878 pr_err("%s: Could not configure gpio %d\n",
6879 __func__, TS_GPIO_IRQ);
6880 goto vreg_get_fail;
6881 }
6882
6883 /* virtual keys */
6884 tma300_vkeys_attr.attr.name = "virtualkeys.msm_tma300_ts";
6885 properties_kobj = kobject_create_and_add("board_properties",
6886 NULL);
6887 if (!properties_kobj) {
6888 pr_err("%s: failed to create a kobject"
6889 "for board_properites\n", __func__);
6890 rc = -ENOMEM;
6891 goto vreg_get_fail;
6892 }
6893 rc = sysfs_create_group(properties_kobj,
6894 &tma300_properties_attr_group);
6895 if (rc) {
6896 pr_err("%s: failed to create a sysfs entry %s\n",
6897 __func__, tma300_vkeys_attr.attr.name);
6898 kobject_put(properties_kobj);
6899 goto vreg_get_fail;
6900 }
6901 } else {
6902 /* put voltage sources */
6903 for (i = 0; i < ARRAY_SIZE(vregs_tma300_name); i++)
6904 vreg_put(vregs_tma300[i]);
6905 /* destroy virtual keys */
6906 if (properties_kobj) {
6907 sysfs_remove_group(properties_kobj,
6908 &tma300_properties_attr_group);
6909 kobject_put(properties_kobj);
6910 }
6911 }
6912 return 0;
6913
6914vreg_get_fail:
6915 while (i)
6916 vreg_put(vregs_tma300[--i]);
6917 return rc;
6918}
6919
6920static struct cy8c_ts_platform_data cy8ctma300_pdata = {
6921 .power_on = tma300_power,
6922 .dev_setup = tma300_dev_setup,
6923 .ts_name = "msm_tma300_ts",
6924 .dis_min_x = 0,
6925 .dis_max_x = 479,
6926 .dis_min_y = 0,
6927 .dis_max_y = 799,
6928 .res_x = 479,
6929 .res_y = 1009,
6930 .min_tid = 1,
6931 .max_tid = 255,
6932 .min_touch = 0,
6933 .max_touch = 255,
6934 .min_width = 0,
6935 .max_width = 255,
6936 .invert_y = 1,
6937 .nfingers = 4,
6938 .irq_gpio = TS_GPIO_IRQ,
6939 .resout_gpio = -1,
6940};
6941
6942static struct i2c_board_info cy8ctma300_board_info[] = {
6943 {
6944 I2C_BOARD_INFO("cy8ctma300", 0x2),
6945 .platform_data = &cy8ctma300_pdata,
6946 }
6947};
6948
Daniel Walker8d747cd2010-02-25 11:37:43 -08006949static void __init msm7x30_init(void)
6950{
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07006951 int rc;
6952 unsigned smem_size;
6953 uint32_t usb_hub_gpio_cfg_value = GPIO_CFG(56,
6954 0,
6955 GPIO_CFG_OUTPUT,
6956 GPIO_CFG_NO_PULL,
6957 GPIO_CFG_2MA);
6958 uint32_t soc_version = 0;
Pavankumar Kondeti5155e2c2010-12-08 13:37:08 +05306959
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07006960 if (socinfo_init() < 0)
6961 printk(KERN_ERR "%s: socinfo_init() failed!\n",
6962 __func__);
6963
6964 soc_version = socinfo_get_version();
6965
6966 msm7x30_clock_init();
6967#ifdef CONFIG_SERIAL_MSM_CONSOLE
6968 msm7x30_init_uart2();
6969#endif
6970 msm_spm_init(&msm_spm_data, 1);
6971 msm_acpu_clock_init(&msm7x30_clock_data);
6972 if (machine_is_msm7x30_surf() || machine_is_msm7x30_fluid())
6973 msm7x30_cfg_smsc911x();
6974
6975#ifdef CONFIG_USB_MSM_OTG_72K
6976 if (SOCINFO_VERSION_MAJOR(soc_version) >= 2 &&
6977 SOCINFO_VERSION_MINOR(soc_version) >= 1) {
6978 pr_debug("%s: SOC Version:2.(1 or more)\n", __func__);
6979 msm_otg_pdata.ldo_set_voltage = 0;
6980 }
6981
6982 msm_device_otg.dev.platform_data = &msm_otg_pdata;
6983#ifdef CONFIG_USB_GADGET
6984 msm_otg_pdata.swfi_latency =
6985 msm_pm_data
6986 [MSM_PM_SLEEP_MODE_RAMP_DOWN_AND_WAIT_FOR_INTERRUPT].latency;
6987 msm_device_gadget_peripheral.dev.platform_data = &msm_gadget_pdata;
6988#endif
6989#endif
6990 msm_uart_dm1_pdata.wakeup_irq = gpio_to_irq(136);
6991 msm_device_uart_dm1.dev.platform_data = &msm_uart_dm1_pdata;
6992#if defined(CONFIG_TSIF) || defined(CONFIG_TSIF_MODULE)
6993 msm_device_tsif.dev.platform_data = &tsif_platform_data;
6994#endif
6995 if (machine_is_msm7x30_fluid()) {
6996 msm_adc_pdata.dev_names = msm_adc_fluid_device_names;
6997 msm_adc_pdata.num_adc = ARRAY_SIZE(msm_adc_fluid_device_names);
6998 } else {
6999 msm_adc_pdata.dev_names = msm_adc_surf_device_names;
7000 msm_adc_pdata.num_adc = ARRAY_SIZE(msm_adc_surf_device_names);
7001 }
7002
7003 platform_add_devices(msm_footswitch_devices,
7004 msm_num_footswitch_devices);
Daniel Walker8d747cd2010-02-25 11:37:43 -08007005 platform_add_devices(devices, ARRAY_SIZE(devices));
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07007006#ifdef CONFIG_USB_EHCI_MSM_72K
7007 msm_add_host(0, &msm_usb_host_pdata);
7008#endif
7009 msm7x30_init_mmc();
7010 msm7x30_init_nand();
7011 msm_qsd_spi_init();
7012
7013#ifdef CONFIG_SPI_QSD
7014 if (machine_is_msm7x30_fluid())
7015 spi_register_board_info(lcdc_sharp_spi_board_info,
7016 ARRAY_SIZE(lcdc_sharp_spi_board_info));
7017 else
7018 spi_register_board_info(lcdc_toshiba_spi_board_info,
7019 ARRAY_SIZE(lcdc_toshiba_spi_board_info));
7020#endif
7021
7022 msm_fb_add_devices();
7023 msm_pm_set_platform_data(msm_pm_data, ARRAY_SIZE(msm_pm_data));
7024 msm_device_i2c_init();
7025 msm_device_i2c_2_init();
7026 qup_device_i2c_init();
7027 buses_init();
7028 msm7x30_init_marimba();
7029#ifdef CONFIG_MSM7KV2_AUDIO
7030 snddev_poweramp_gpio_init();
7031 aux_pcm_gpio_init();
7032#endif
7033
7034 i2c_register_board_info(0, msm_i2c_board_info,
7035 ARRAY_SIZE(msm_i2c_board_info));
7036
7037 if (!machine_is_msm8x55_svlte_ffa() && !machine_is_msm7x30_fluid())
7038 marimba_pdata.tsadc = &marimba_tsadc_pdata;
7039
7040 if (machine_is_msm7x30_fluid())
7041 i2c_register_board_info(0, cy8info,
7042 ARRAY_SIZE(cy8info));
7043#ifdef CONFIG_BOSCH_BMA150
7044 if (machine_is_msm7x30_fluid())
7045 i2c_register_board_info(0, bma150_board_info,
7046 ARRAY_SIZE(bma150_board_info));
7047#endif
7048
7049 i2c_register_board_info(2, msm_marimba_board_info,
7050 ARRAY_SIZE(msm_marimba_board_info));
7051
7052 i2c_register_board_info(2, msm_i2c_gsbi7_timpani_info,
7053 ARRAY_SIZE(msm_i2c_gsbi7_timpani_info));
7054
7055 i2c_register_board_info(4 /* QUP ID */, msm_camera_boardinfo,
7056 ARRAY_SIZE(msm_camera_boardinfo));
7057
7058 bt_power_init();
7059#ifdef CONFIG_I2C_SSBI
7060 msm_device_ssbi6.dev.platform_data = &msm_i2c_ssbi6_pdata;
7061 msm_device_ssbi7.dev.platform_data = &msm_i2c_ssbi7_pdata;
7062#endif
7063 if (machine_is_msm7x30_fluid())
7064 i2c_register_board_info(0, msm_isa1200_board_info,
7065 ARRAY_SIZE(msm_isa1200_board_info));
7066
7067#if defined(CONFIG_TOUCHSCREEN_TSC2007) || \
7068 defined(CONFIG_TOUCHSCREEN_TSC2007_MODULE)
7069 if (machine_is_msm8x55_svlte_ffa())
7070 i2c_register_board_info(2, tsc_i2c_board_info,
7071 ARRAY_SIZE(tsc_i2c_board_info));
7072#endif
7073
7074 if (machine_is_msm7x30_surf())
7075 platform_device_register(&flip_switch_device);
7076 pmic8058_leds_init();
7077
7078 if (machine_is_msm7x30_fluid()) {
7079 /* Initialize platform data for fluid v2 hardware */
7080 if (SOCINFO_VERSION_MAJOR(
7081 socinfo_get_platform_version()) == 2) {
7082 cy8ctma300_pdata.res_y = 920;
7083 cy8ctma300_pdata.invert_y = 0;
7084 }
7085 i2c_register_board_info(0, cy8ctma300_board_info,
7086 ARRAY_SIZE(cy8ctma300_board_info));
7087 }
7088
7089 if (machine_is_msm8x55_svlte_surf() || machine_is_msm8x55_svlte_ffa()) {
7090 rc = gpio_tlmm_config(usb_hub_gpio_cfg_value, GPIO_CFG_ENABLE);
7091 if (rc)
7092 pr_err("%s: gpio_tlmm_config(%#x)=%d\n",
7093 __func__, usb_hub_gpio_cfg_value, rc);
7094 }
7095
7096 boot_reason = *(unsigned int *)
7097 (smem_get_entry(SMEM_POWER_ON_STATUS_INFO, &smem_size));
7098 printk(KERN_NOTICE "Boot Reason = 0x%02x\n", boot_reason);
7099}
7100
7101static unsigned pmem_sf_size = MSM_PMEM_SF_SIZE;
7102static int __init pmem_sf_size_setup(char *p)
7103{
7104 pmem_sf_size = memparse(p, NULL);
7105 return 0;
7106}
7107early_param("pmem_sf_size", pmem_sf_size_setup);
7108
7109static unsigned fb_size = MSM_FB_SIZE;
7110static int __init fb_size_setup(char *p)
7111{
7112 fb_size = memparse(p, NULL);
7113 return 0;
7114}
7115early_param("fb_size", fb_size_setup);
7116
7117static unsigned pmem_adsp_size = MSM_PMEM_ADSP_SIZE;
7118static int __init pmem_adsp_size_setup(char *p)
7119{
7120 pmem_adsp_size = memparse(p, NULL);
7121 return 0;
7122}
7123early_param("pmem_adsp_size", pmem_adsp_size_setup);
7124
7125static unsigned fluid_pmem_adsp_size = MSM_FLUID_PMEM_ADSP_SIZE;
7126static int __init fluid_pmem_adsp_size_setup(char *p)
7127{
7128 fluid_pmem_adsp_size = memparse(p, NULL);
7129 return 0;
7130}
7131early_param("fluid_pmem_adsp_size", fluid_pmem_adsp_size_setup);
7132
7133static unsigned pmem_audio_size = MSM_PMEM_AUDIO_SIZE;
7134static int __init pmem_audio_size_setup(char *p)
7135{
7136 pmem_audio_size = memparse(p, NULL);
7137 return 0;
7138}
7139early_param("pmem_audio_size", pmem_audio_size_setup);
7140
7141static unsigned pmem_kernel_ebi0_size = PMEM_KERNEL_EBI0_SIZE;
7142static int __init pmem_kernel_ebi0_size_setup(char *p)
7143{
7144 pmem_kernel_ebi0_size = memparse(p, NULL);
7145 return 0;
7146}
7147early_param("pmem_kernel_ebi0_size", pmem_kernel_ebi0_size_setup);
7148
7149static struct memtype_reserve msm7x30_reserve_table[] __initdata = {
7150 [MEMTYPE_SMI] = {
7151 },
7152 [MEMTYPE_EBI0] = {
7153 .flags = MEMTYPE_FLAGS_1M_ALIGN,
7154 },
7155 [MEMTYPE_EBI1] = {
7156 .flags = MEMTYPE_FLAGS_1M_ALIGN,
7157 },
7158};
7159
7160static void __init size_pmem_devices(void)
7161{
7162#ifdef CONFIG_ANDROID_PMEM
7163 unsigned long size;
7164
7165 if machine_is_msm7x30_fluid()
7166 size = fluid_pmem_adsp_size;
7167 else
7168 size = pmem_adsp_size;
7169 android_pmem_adsp_pdata.size = size;
7170 android_pmem_audio_pdata.size = pmem_audio_size;
7171 android_pmem_pdata.size = pmem_sf_size;
7172#endif
7173}
7174
7175static void __init reserve_memory_for(struct android_pmem_platform_data *p)
7176{
7177 msm7x30_reserve_table[p->memory_type].size += p->size;
7178}
7179
7180static void __init reserve_pmem_memory(void)
7181{
7182#ifdef CONFIG_ANDROID_PMEM
7183 reserve_memory_for(&android_pmem_adsp_pdata);
7184 reserve_memory_for(&android_pmem_audio_pdata);
7185 reserve_memory_for(&android_pmem_pdata);
7186 msm7x30_reserve_table[MEMTYPE_EBI0].size += pmem_kernel_ebi0_size;
7187#endif
7188}
7189
7190static void __init msm7x30_calculate_reserve_sizes(void)
7191{
7192 size_pmem_devices();
7193 reserve_pmem_memory();
7194}
7195
7196static int msm7x30_paddr_to_memtype(unsigned int paddr)
7197{
7198 if (paddr < 0x40000000)
7199 return MEMTYPE_EBI0;
7200 if (paddr >= 0x40000000 && paddr < 0x80000000)
7201 return MEMTYPE_EBI1;
7202 return MEMTYPE_NONE;
7203}
7204
7205static struct reserve_info msm7x30_reserve_info __initdata = {
7206 .memtype_reserve_table = msm7x30_reserve_table,
7207 .calculate_reserve_sizes = msm7x30_calculate_reserve_sizes,
7208 .paddr_to_memtype = msm7x30_paddr_to_memtype,
7209};
7210
7211static void __init msm7x30_reserve(void)
7212{
7213 reserve_info = &msm7x30_reserve_info;
7214 msm_reserve();
7215}
7216
7217static void __init msm7x30_allocate_memory_regions(void)
7218{
7219 void *addr;
7220 unsigned long size;
7221
7222 size = fb_size ? : MSM_FB_SIZE;
7223 addr = alloc_bootmem_align(size, 0x1000);
7224 msm_fb_resources[0].start = __pa(addr);
7225 msm_fb_resources[0].end = msm_fb_resources[0].start + size - 1;
7226 pr_info("allocating %lu bytes at %p (%lx physical) for fb\n",
7227 size, addr, __pa(addr));
Daniel Walker8d747cd2010-02-25 11:37:43 -08007228}
7229
7230static void __init msm7x30_map_io(void)
7231{
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07007232 msm_shared_ram_phys = 0x00100000;
Daniel Walker8d747cd2010-02-25 11:37:43 -08007233 msm_map_msm7x30_io();
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07007234}
7235
7236static void __init msm7x30_init_early(void)
7237{
7238 msm7x30_allocate_memory_regions();
Daniel Walker8d747cd2010-02-25 11:37:43 -08007239}
7240
7241MACHINE_START(MSM7X30_SURF, "QCT MSM7X30 SURF")
Russell Kingb75c1782011-01-04 19:03:16 +00007242 .boot_params = PLAT_PHYS_OFFSET + 0x100,
Daniel Walker8d747cd2010-02-25 11:37:43 -08007243 .map_io = msm7x30_map_io,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07007244 .reserve = msm7x30_reserve,
Daniel Walker8d747cd2010-02-25 11:37:43 -08007245 .init_irq = msm7x30_init_irq,
7246 .init_machine = msm7x30_init,
7247 .timer = &msm_timer,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07007248 .init_early = msm7x30_init_early,
Daniel Walker8d747cd2010-02-25 11:37:43 -08007249MACHINE_END
7250
7251MACHINE_START(MSM7X30_FFA, "QCT MSM7X30 FFA")
Russell Kingb75c1782011-01-04 19:03:16 +00007252 .boot_params = PLAT_PHYS_OFFSET + 0x100,
Daniel Walker8d747cd2010-02-25 11:37:43 -08007253 .map_io = msm7x30_map_io,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07007254 .reserve = msm7x30_reserve,
Daniel Walker8d747cd2010-02-25 11:37:43 -08007255 .init_irq = msm7x30_init_irq,
7256 .init_machine = msm7x30_init,
7257 .timer = &msm_timer,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07007258 .init_early = msm7x30_init_early,
Daniel Walker8d747cd2010-02-25 11:37:43 -08007259MACHINE_END
7260
7261MACHINE_START(MSM7X30_FLUID, "QCT MSM7X30 FLUID")
Russell Kingb75c1782011-01-04 19:03:16 +00007262 .boot_params = PLAT_PHYS_OFFSET + 0x100,
Daniel Walker8d747cd2010-02-25 11:37:43 -08007263 .map_io = msm7x30_map_io,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07007264 .reserve = msm7x30_reserve,
Daniel Walker8d747cd2010-02-25 11:37:43 -08007265 .init_irq = msm7x30_init_irq,
7266 .init_machine = msm7x30_init,
7267 .timer = &msm_timer,
Bryan Huntsman3f2bc4d2011-08-16 17:27:22 -07007268 .init_early = msm7x30_init_early,
7269MACHINE_END
7270
7271MACHINE_START(MSM8X55_SURF, "QCT MSM8X55 SURF")
7272 .boot_params = PHYS_OFFSET + 0x100,
7273 .map_io = msm7x30_map_io,
7274 .reserve = msm7x30_reserve,
7275 .init_irq = msm7x30_init_irq,
7276 .init_machine = msm7x30_init,
7277 .timer = &msm_timer,
7278 .init_early = msm7x30_init_early,
7279MACHINE_END
7280
7281MACHINE_START(MSM8X55_FFA, "QCT MSM8X55 FFA")
7282 .boot_params = PHYS_OFFSET + 0x100,
7283 .map_io = msm7x30_map_io,
7284 .reserve = msm7x30_reserve,
7285 .init_irq = msm7x30_init_irq,
7286 .init_machine = msm7x30_init,
7287 .timer = &msm_timer,
7288 .init_early = msm7x30_init_early,
7289MACHINE_END
7290MACHINE_START(MSM8X55_SVLTE_SURF, "QCT MSM8X55 SVLTE SURF")
7291 .boot_params = PHYS_OFFSET + 0x100,
7292 .map_io = msm7x30_map_io,
7293 .reserve = msm7x30_reserve,
7294 .init_irq = msm7x30_init_irq,
7295 .init_machine = msm7x30_init,
7296 .timer = &msm_timer,
7297 .init_early = msm7x30_init_early,
7298MACHINE_END
7299MACHINE_START(MSM8X55_SVLTE_FFA, "QCT MSM8X55 SVLTE FFA")
7300 .boot_params = PHYS_OFFSET + 0x100,
7301 .map_io = msm7x30_map_io,
7302 .reserve = msm7x30_reserve,
7303 .init_irq = msm7x30_init_irq,
7304 .init_machine = msm7x30_init,
7305 .timer = &msm_timer,
7306 .init_early = msm7x30_init_early,
Daniel Walker8d747cd2010-02-25 11:37:43 -08007307MACHINE_END