| David Howells | 0bc42d7 | 2010-10-27 17:28:41 +0100 | [diff] [blame] | 1 | # |
| 2 | # MN10300 CPU cache options |
| 3 | # |
| 4 | |
| 5 | choice |
| 6 | prompt "CPU Caching mode" |
| 7 | default MN10300_CACHE_WBACK |
| 8 | help |
| 9 | This option determines the caching mode for the kernel. |
| 10 | |
| 11 | Write-Back caching mode involves the all reads and writes causing |
| 12 | the affected cacheline to be read into the cache first before being |
| 13 | operated upon. Memory is not then updated by a write until the cache |
| 14 | is filled and a cacheline needs to be displaced from the cache to |
| 15 | make room. Only at that point is it written back. |
| 16 | |
| 17 | Write-Through caching only fetches cachelines from memory on a |
| 18 | read. Writes always get written directly to memory. If the affected |
| 19 | cacheline is also in cache, it will be updated too. |
| 20 | |
| 21 | The final option is to turn of caching entirely. |
| 22 | |
| 23 | config MN10300_CACHE_WBACK |
| 24 | bool "Write-Back" |
| 25 | |
| 26 | config MN10300_CACHE_WTHRU |
| 27 | bool "Write-Through" |
| 28 | |
| 29 | config MN10300_CACHE_DISABLED |
| 30 | bool "Disabled" |
| 31 | |
| 32 | endchoice |
| David Howells | 344af92 | 2010-10-27 17:28:42 +0100 | [diff] [blame] | 33 | |
| 34 | config MN10300_CACHE_ENABLED |
| 35 | def_bool y if !MN10300_CACHE_DISABLED |
| David Howells | 518d4bb | 2010-10-27 17:28:43 +0100 | [diff] [blame] | 36 | |
| 37 | |
| 38 | choice |
| 39 | prompt "CPU cache flush/invalidate method" |
| Akira Takeuchi | 9731d23 | 2010-10-27 17:28:45 +0100 | [diff] [blame^] | 40 | default MN10300_CACHE_MANAGE_BY_TAG if !AM34_2 |
| 41 | default MN10300_CACHE_MANAGE_BY_REG if AM34_2 |
| David Howells | 518d4bb | 2010-10-27 17:28:43 +0100 | [diff] [blame] | 42 | depends on MN10300_CACHE_ENABLED |
| 43 | help |
| 44 | This determines the method by which CPU cache flushing and |
| 45 | invalidation is performed. |
| 46 | |
| 47 | config MN10300_CACHE_MANAGE_BY_TAG |
| 48 | bool "Use the cache tag registers directly" |
| 49 | |
| Akira Takeuchi | 9731d23 | 2010-10-27 17:28:45 +0100 | [diff] [blame^] | 50 | config MN10300_CACHE_MANAGE_BY_REG |
| 51 | bool "Flush areas by way of automatic purge registers (AM34 only)" |
| 52 | depends on AM34_2 |
| 53 | |
| David Howells | 518d4bb | 2010-10-27 17:28:43 +0100 | [diff] [blame] | 54 | endchoice |
| 55 | |
| 56 | config MN10300_CACHE_INV_BY_TAG |
| 57 | def_bool y if MN10300_CACHE_MANAGE_BY_TAG && MN10300_CACHE_ENABLED |
| 58 | |
| Akira Takeuchi | 9731d23 | 2010-10-27 17:28:45 +0100 | [diff] [blame^] | 59 | config MN10300_CACHE_INV_BY_REG |
| 60 | def_bool y if MN10300_CACHE_MANAGE_BY_REG && MN10300_CACHE_ENABLED |
| 61 | |
| David Howells | 518d4bb | 2010-10-27 17:28:43 +0100 | [diff] [blame] | 62 | config MN10300_CACHE_FLUSH_BY_TAG |
| 63 | def_bool y if MN10300_CACHE_MANAGE_BY_TAG && MN10300_CACHE_WBACK |
| Akira Takeuchi | 9731d23 | 2010-10-27 17:28:45 +0100 | [diff] [blame^] | 64 | |
| 65 | config MN10300_CACHE_FLUSH_BY_REG |
| 66 | def_bool y if MN10300_CACHE_MANAGE_BY_REG && MN10300_CACHE_WBACK |